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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.68 100.00 98.62 97.45 98.37


Total test records in report: 457
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T316 /workspace/coverage/default/48.rom_ctrl_alert_test.3389349403 Jul 23 04:39:03 PM PDT 24 Jul 23 04:39:28 PM PDT 24 5135584558 ps
T317 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2212651638 Jul 23 04:38:55 PM PDT 24 Jul 23 04:39:19 PM PDT 24 9691102460 ps
T318 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3663209631 Jul 23 04:39:02 PM PDT 24 Jul 23 04:39:41 PM PDT 24 5721868221 ps
T319 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2882260791 Jul 23 04:38:41 PM PDT 24 Jul 23 04:49:12 PM PDT 24 280924754003 ps
T320 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3901837425 Jul 23 04:39:02 PM PDT 24 Jul 23 04:44:10 PM PDT 24 103947924818 ps
T321 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2717681812 Jul 23 04:38:19 PM PDT 24 Jul 23 04:42:53 PM PDT 24 25690810330 ps
T322 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1579465591 Jul 23 04:38:30 PM PDT 24 Jul 23 04:38:41 PM PDT 24 1338657931 ps
T323 /workspace/coverage/default/10.rom_ctrl_alert_test.192439104 Jul 23 04:38:27 PM PDT 24 Jul 23 04:38:36 PM PDT 24 435558512 ps
T324 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.183587598 Jul 23 04:38:49 PM PDT 24 Jul 23 04:43:29 PM PDT 24 6746937731 ps
T325 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1905641758 Jul 23 04:38:51 PM PDT 24 Jul 23 04:39:55 PM PDT 24 32752262025 ps
T326 /workspace/coverage/default/24.rom_ctrl_alert_test.492842609 Jul 23 04:38:44 PM PDT 24 Jul 23 04:38:54 PM PDT 24 689635744 ps
T327 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1894731273 Jul 23 04:38:45 PM PDT 24 Jul 23 04:39:49 PM PDT 24 7204233159 ps
T328 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.206927865 Jul 23 04:39:01 PM PDT 24 Jul 23 04:39:14 PM PDT 24 709147039 ps
T329 /workspace/coverage/default/25.rom_ctrl_smoke.628255817 Jul 23 04:38:45 PM PDT 24 Jul 23 04:39:51 PM PDT 24 23966564949 ps
T330 /workspace/coverage/default/15.rom_ctrl_alert_test.4266379785 Jul 23 04:38:32 PM PDT 24 Jul 23 04:38:42 PM PDT 24 256606716 ps
T331 /workspace/coverage/default/28.rom_ctrl_stress_all.242097602 Jul 23 04:38:52 PM PDT 24 Jul 23 04:40:40 PM PDT 24 14382768605 ps
T332 /workspace/coverage/default/46.rom_ctrl_smoke.1021595993 Jul 23 04:39:00 PM PDT 24 Jul 23 04:39:27 PM PDT 24 2685133218 ps
T103 /workspace/coverage/default/23.rom_ctrl_smoke.2367224852 Jul 23 04:38:37 PM PDT 24 Jul 23 04:39:26 PM PDT 24 6379469163 ps
T104 /workspace/coverage/default/32.rom_ctrl_stress_all.399938830 Jul 23 04:38:48 PM PDT 24 Jul 23 04:39:52 PM PDT 24 5257046974 ps
T105 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.431473205 Jul 23 04:38:45 PM PDT 24 Jul 23 04:38:58 PM PDT 24 266665263 ps
T106 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2203245308 Jul 23 04:39:00 PM PDT 24 Jul 23 04:45:41 PM PDT 24 38308871309 ps
T107 /workspace/coverage/default/46.rom_ctrl_alert_test.2710684135 Jul 23 04:38:59 PM PDT 24 Jul 23 04:39:25 PM PDT 24 10793233436 ps
T108 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3210244947 Jul 23 04:38:44 PM PDT 24 Jul 23 04:39:42 PM PDT 24 6484152417 ps
T109 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1679310427 Jul 23 04:38:49 PM PDT 24 Jul 23 04:51:48 PM PDT 24 312042292382 ps
T110 /workspace/coverage/default/21.rom_ctrl_smoke.4056002040 Jul 23 04:38:36 PM PDT 24 Jul 23 04:39:01 PM PDT 24 1806624114 ps
T111 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2617374825 Jul 23 04:38:37 PM PDT 24 Jul 23 04:39:26 PM PDT 24 9882949864 ps
T112 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1400693221 Jul 23 04:38:38 PM PDT 24 Jul 23 04:39:32 PM PDT 24 20417001055 ps
T333 /workspace/coverage/default/13.rom_ctrl_alert_test.2485398196 Jul 23 04:38:56 PM PDT 24 Jul 23 04:39:19 PM PDT 24 11028468047 ps
T334 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2392410002 Jul 23 04:39:04 PM PDT 24 Jul 23 04:39:34 PM PDT 24 1313725005 ps
T335 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1100662812 Jul 23 04:38:31 PM PDT 24 Jul 23 04:47:45 PM PDT 24 65478775995 ps
T336 /workspace/coverage/default/25.rom_ctrl_stress_all.43147180 Jul 23 04:38:42 PM PDT 24 Jul 23 04:39:11 PM PDT 24 722543104 ps
T118 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2238998981 Jul 23 04:38:56 PM PDT 24 Jul 23 04:39:26 PM PDT 24 3498369873 ps
T337 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1696009751 Jul 23 04:38:45 PM PDT 24 Jul 23 04:39:46 PM PDT 24 6485687927 ps
T338 /workspace/coverage/default/42.rom_ctrl_stress_all.3901768051 Jul 23 04:38:54 PM PDT 24 Jul 23 04:39:38 PM PDT 24 49728811739 ps
T339 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.536055222 Jul 23 04:38:42 PM PDT 24 Jul 23 04:39:42 PM PDT 24 6778958619 ps
T340 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1826737641 Jul 23 04:38:45 PM PDT 24 Jul 23 04:39:07 PM PDT 24 2951015588 ps
T341 /workspace/coverage/default/38.rom_ctrl_stress_all.1975877894 Jul 23 04:38:55 PM PDT 24 Jul 23 04:40:03 PM PDT 24 1705784066 ps
T342 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4074213244 Jul 23 04:38:20 PM PDT 24 Jul 23 04:38:31 PM PDT 24 353678343 ps
T343 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.90061226 Jul 23 04:38:27 PM PDT 24 Jul 23 04:39:00 PM PDT 24 15740601188 ps
T344 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1982602224 Jul 23 04:38:33 PM PDT 24 Jul 23 04:41:46 PM PDT 24 2771125814 ps
T345 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4278042131 Jul 23 04:38:24 PM PDT 24 Jul 23 04:38:35 PM PDT 24 725106760 ps
T346 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3981628906 Jul 23 04:38:14 PM PDT 24 Jul 23 04:38:39 PM PDT 24 8855999338 ps
T347 /workspace/coverage/default/34.rom_ctrl_alert_test.1151952218 Jul 23 04:38:49 PM PDT 24 Jul 23 04:38:59 PM PDT 24 689267383 ps
T348 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3260884962 Jul 23 04:38:04 PM PDT 24 Jul 23 04:39:20 PM PDT 24 71330517291 ps
T58 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3581621029 Jul 23 04:38:44 PM PDT 24 Jul 23 05:17:36 PM PDT 24 38929301961 ps
T349 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2453402713 Jul 23 04:38:41 PM PDT 24 Jul 23 04:43:31 PM PDT 24 16909582760 ps
T350 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.302499579 Jul 23 04:38:34 PM PDT 24 Jul 23 04:38:46 PM PDT 24 355059862 ps
T351 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1009722464 Jul 23 04:38:45 PM PDT 24 Jul 23 04:39:06 PM PDT 24 332782778 ps
T28 /workspace/coverage/default/3.rom_ctrl_sec_cm.492900364 Jul 23 04:38:13 PM PDT 24 Jul 23 04:41:59 PM PDT 24 702476310 ps
T352 /workspace/coverage/default/30.rom_ctrl_smoke.1109395768 Jul 23 04:38:46 PM PDT 24 Jul 23 04:39:24 PM PDT 24 8595755882 ps
T353 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.136312217 Jul 23 04:39:00 PM PDT 24 Jul 23 04:42:53 PM PDT 24 21723477867 ps
T354 /workspace/coverage/default/3.rom_ctrl_alert_test.3293075226 Jul 23 04:38:13 PM PDT 24 Jul 23 04:38:23 PM PDT 24 167308751 ps
T355 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3416639340 Jul 23 04:38:49 PM PDT 24 Jul 23 04:39:01 PM PDT 24 1315995276 ps
T356 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4121409014 Jul 23 04:38:58 PM PDT 24 Jul 23 04:49:29 PM PDT 24 139614085052 ps
T357 /workspace/coverage/default/8.rom_ctrl_smoke.2594627069 Jul 23 04:38:24 PM PDT 24 Jul 23 04:39:31 PM PDT 24 27700072116 ps
T358 /workspace/coverage/default/41.rom_ctrl_stress_all.558882023 Jul 23 04:38:46 PM PDT 24 Jul 23 04:41:43 PM PDT 24 65492968494 ps
T359 /workspace/coverage/default/26.rom_ctrl_smoke.3658223871 Jul 23 04:38:44 PM PDT 24 Jul 23 04:39:21 PM PDT 24 2694394056 ps
T360 /workspace/coverage/default/3.rom_ctrl_smoke.3087304435 Jul 23 04:38:15 PM PDT 24 Jul 23 04:38:40 PM PDT 24 1828463856 ps
T361 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1650931228 Jul 23 04:38:45 PM PDT 24 Jul 23 04:48:48 PM PDT 24 62013402678 ps
T362 /workspace/coverage/default/20.rom_ctrl_smoke.4175446584 Jul 23 04:38:44 PM PDT 24 Jul 23 04:40:03 PM PDT 24 44320926576 ps
T363 /workspace/coverage/default/23.rom_ctrl_alert_test.1819998585 Jul 23 04:38:46 PM PDT 24 Jul 23 04:38:57 PM PDT 24 345902656 ps
T364 /workspace/coverage/default/12.rom_ctrl_smoke.100808780 Jul 23 04:38:26 PM PDT 24 Jul 23 04:38:50 PM PDT 24 6353970613 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2931261984 Jul 23 04:43:06 PM PDT 24 Jul 23 04:44:01 PM PDT 24 1318244412 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3508178487 Jul 23 04:43:09 PM PDT 24 Jul 23 04:45:10 PM PDT 24 32817564561 ps
T60 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4273040742 Jul 23 04:43:22 PM PDT 24 Jul 23 04:46:22 PM PDT 24 4487308291 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1483094948 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:54 PM PDT 24 1442198552 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1450143173 Jul 23 04:42:50 PM PDT 24 Jul 23 04:43:55 PM PDT 24 8103579134 ps
T119 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.138141554 Jul 23 04:43:12 PM PDT 24 Jul 23 04:44:04 PM PDT 24 7923738566 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2401463412 Jul 23 04:42:45 PM PDT 24 Jul 23 04:43:48 PM PDT 24 735631123 ps
T61 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.94651464 Jul 23 04:43:01 PM PDT 24 Jul 23 04:43:50 PM PDT 24 196869966 ps
T113 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1678930101 Jul 23 04:42:56 PM PDT 24 Jul 23 04:43:50 PM PDT 24 523707164 ps
T78 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4023953967 Jul 23 04:43:02 PM PDT 24 Jul 23 04:43:56 PM PDT 24 4258467199 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2850171938 Jul 23 04:43:03 PM PDT 24 Jul 23 04:44:06 PM PDT 24 6274691883 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2036631841 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:46 PM PDT 24 1197918701 ps
T121 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2956646275 Jul 23 04:43:03 PM PDT 24 Jul 23 04:44:38 PM PDT 24 3964347539 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3369557446 Jul 23 04:43:13 PM PDT 24 Jul 23 04:43:57 PM PDT 24 2305924064 ps
T69 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1178379603 Jul 23 04:43:10 PM PDT 24 Jul 23 04:45:05 PM PDT 24 525819849 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4277414731 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:47 PM PDT 24 254877595 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2861335528 Jul 23 04:42:55 PM PDT 24 Jul 23 04:44:32 PM PDT 24 12059333619 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.422142165 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:04 PM PDT 24 21323289539 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.549878986 Jul 23 04:43:03 PM PDT 24 Jul 23 04:43:56 PM PDT 24 574410770 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.990311374 Jul 23 04:42:57 PM PDT 24 Jul 23 04:43:46 PM PDT 24 717357672 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.818423292 Jul 23 04:42:52 PM PDT 24 Jul 23 04:44:02 PM PDT 24 6226332661 ps
T83 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3740650026 Jul 23 04:43:04 PM PDT 24 Jul 23 04:44:13 PM PDT 24 8226477664 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4117190451 Jul 23 04:43:10 PM PDT 24 Jul 23 04:44:02 PM PDT 24 3434435368 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3882062160 Jul 23 04:43:13 PM PDT 24 Jul 23 04:43:52 PM PDT 24 661504867 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2094320022 Jul 23 04:43:02 PM PDT 24 Jul 23 04:44:00 PM PDT 24 1917614722 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2992006756 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:45 PM PDT 24 1100120080 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1799058599 Jul 23 04:42:54 PM PDT 24 Jul 23 04:45:14 PM PDT 24 9494000879 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2820807010 Jul 23 04:42:59 PM PDT 24 Jul 23 04:45:12 PM PDT 24 6079865959 ps
T123 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.726602582 Jul 23 04:43:02 PM PDT 24 Jul 23 04:46:17 PM PDT 24 639878897 ps
T130 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3952993081 Jul 23 04:43:09 PM PDT 24 Jul 23 04:45:12 PM PDT 24 6418464468 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.452154179 Jul 23 04:43:03 PM PDT 24 Jul 23 04:45:37 PM PDT 24 13895321361 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.275540141 Jul 23 04:42:46 PM PDT 24 Jul 23 04:44:10 PM PDT 24 15307109277 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2148609478 Jul 23 04:43:06 PM PDT 24 Jul 23 04:43:50 PM PDT 24 167788355 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3133914530 Jul 23 04:42:49 PM PDT 24 Jul 23 04:43:52 PM PDT 24 2801348044 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1127303706 Jul 23 04:43:03 PM PDT 24 Jul 23 04:43:54 PM PDT 24 360268573 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4292419624 Jul 23 04:43:16 PM PDT 24 Jul 23 04:44:01 PM PDT 24 3379561492 ps
T131 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3716244837 Jul 23 04:43:07 PM PDT 24 Jul 23 04:45:22 PM PDT 24 3767711637 ps
T376 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3119056975 Jul 23 04:43:08 PM PDT 24 Jul 23 04:44:21 PM PDT 24 5698187728 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1437121910 Jul 23 04:42:57 PM PDT 24 Jul 23 04:43:53 PM PDT 24 729587433 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.544373381 Jul 23 04:42:45 PM PDT 24 Jul 23 04:44:11 PM PDT 24 719201325 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2559186992 Jul 23 04:43:01 PM PDT 24 Jul 23 04:44:06 PM PDT 24 8905099444 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1104004397 Jul 23 04:42:52 PM PDT 24 Jul 23 04:43:47 PM PDT 24 176437408 ps
T380 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.865621627 Jul 23 04:43:10 PM PDT 24 Jul 23 04:43:56 PM PDT 24 174553457 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1843046857 Jul 23 04:43:02 PM PDT 24 Jul 23 04:44:11 PM PDT 24 14501543909 ps
T132 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.976053113 Jul 23 04:42:55 PM PDT 24 Jul 23 04:46:30 PM PDT 24 4357971170 ps
T122 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2073128828 Jul 23 04:43:02 PM PDT 24 Jul 23 04:46:42 PM PDT 24 23140517905 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.882258866 Jul 23 04:43:17 PM PDT 24 Jul 23 04:44:15 PM PDT 24 4506992057 ps
T383 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4015809880 Jul 23 04:43:09 PM PDT 24 Jul 23 04:44:16 PM PDT 24 16344454235 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3727448821 Jul 23 04:43:11 PM PDT 24 Jul 23 04:45:20 PM PDT 24 5878204126 ps
T116 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2753699702 Jul 23 04:43:16 PM PDT 24 Jul 23 04:44:03 PM PDT 24 3273519378 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2799652781 Jul 23 04:43:02 PM PDT 24 Jul 23 04:43:50 PM PDT 24 1314504717 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2863878508 Jul 23 04:43:22 PM PDT 24 Jul 23 04:44:04 PM PDT 24 8252859719 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.316113844 Jul 23 04:43:14 PM PDT 24 Jul 23 04:44:16 PM PDT 24 4121314549 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.165535528 Jul 23 04:43:08 PM PDT 24 Jul 23 04:44:12 PM PDT 24 29602492939 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2440125643 Jul 23 04:42:54 PM PDT 24 Jul 23 04:43:51 PM PDT 24 3899968189 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.785828183 Jul 23 04:42:48 PM PDT 24 Jul 23 04:45:33 PM PDT 24 15022708794 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1333444226 Jul 23 04:42:54 PM PDT 24 Jul 23 04:43:50 PM PDT 24 508522433 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2304376426 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:45 PM PDT 24 751217547 ps
T117 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1102922053 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:10 PM PDT 24 15948351278 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.725673441 Jul 23 04:43:05 PM PDT 24 Jul 23 04:44:07 PM PDT 24 2555141116 ps
T392 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.434511194 Jul 23 04:42:55 PM PDT 24 Jul 23 04:44:14 PM PDT 24 718797816 ps
T126 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.476989727 Jul 23 04:43:08 PM PDT 24 Jul 23 04:46:25 PM PDT 24 2028869740 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1260773036 Jul 23 04:42:48 PM PDT 24 Jul 23 04:43:42 PM PDT 24 331632256 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2956100694 Jul 23 04:42:53 PM PDT 24 Jul 23 04:44:39 PM PDT 24 8998006400 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2185599010 Jul 23 04:43:02 PM PDT 24 Jul 23 04:45:23 PM PDT 24 41346753769 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3651246463 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:01 PM PDT 24 4824013491 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4058685075 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:45 PM PDT 24 176066615 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2339605438 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:45 PM PDT 24 185877182 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.635649757 Jul 23 04:42:57 PM PDT 24 Jul 23 04:44:04 PM PDT 24 8759602561 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2220951960 Jul 23 04:43:08 PM PDT 24 Jul 23 04:43:51 PM PDT 24 1649984219 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3987035118 Jul 23 04:42:55 PM PDT 24 Jul 23 04:44:08 PM PDT 24 4111818946 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.752723430 Jul 23 04:43:03 PM PDT 24 Jul 23 04:44:12 PM PDT 24 28202369266 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2805658928 Jul 23 04:43:08 PM PDT 24 Jul 23 04:44:09 PM PDT 24 3344706838 ps
T97 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.220870870 Jul 23 04:43:08 PM PDT 24 Jul 23 04:45:33 PM PDT 24 8988869102 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2196335189 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:57 PM PDT 24 785438848 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3917638663 Jul 23 04:43:15 PM PDT 24 Jul 23 04:44:14 PM PDT 24 26240828125 ps
T127 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3163957847 Jul 23 04:43:02 PM PDT 24 Jul 23 04:45:07 PM PDT 24 1398728416 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4201190265 Jul 23 04:42:46 PM PDT 24 Jul 23 04:44:04 PM PDT 24 37333465774 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.724720403 Jul 23 04:43:05 PM PDT 24 Jul 23 04:44:05 PM PDT 24 2066166934 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1661091659 Jul 23 04:42:57 PM PDT 24 Jul 23 04:43:55 PM PDT 24 1354947368 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2994232084 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:50 PM PDT 24 319739706 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.614497841 Jul 23 04:43:02 PM PDT 24 Jul 23 04:44:10 PM PDT 24 7527794963 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.253254675 Jul 23 04:43:05 PM PDT 24 Jul 23 04:44:38 PM PDT 24 1092031942 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4226592276 Jul 23 04:43:21 PM PDT 24 Jul 23 04:46:16 PM PDT 24 32829775590 ps
T408 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.165076372 Jul 23 04:43:04 PM PDT 24 Jul 23 04:44:12 PM PDT 24 8725217756 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4213439601 Jul 23 04:43:14 PM PDT 24 Jul 23 04:44:05 PM PDT 24 6117507176 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.923648850 Jul 23 04:43:06 PM PDT 24 Jul 23 04:44:08 PM PDT 24 13301480735 ps
T411 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.733536070 Jul 23 04:43:10 PM PDT 24 Jul 23 04:43:52 PM PDT 24 737279783 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3520817815 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:10 PM PDT 24 6281449691 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1893456248 Jul 23 04:43:02 PM PDT 24 Jul 23 04:44:11 PM PDT 24 16111806565 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3433578472 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:08 PM PDT 24 10861129690 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3669923266 Jul 23 04:43:03 PM PDT 24 Jul 23 04:44:04 PM PDT 24 2426333338 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.989589325 Jul 23 04:43:14 PM PDT 24 Jul 23 04:44:02 PM PDT 24 1458039172 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1977020851 Jul 23 04:43:21 PM PDT 24 Jul 23 04:44:19 PM PDT 24 32245360588 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.109828661 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:54 PM PDT 24 5097173301 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3367441216 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:13 PM PDT 24 18532561241 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1665149690 Jul 23 04:42:55 PM PDT 24 Jul 23 04:44:10 PM PDT 24 5261711254 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1089995786 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:09 PM PDT 24 16541977048 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3585812084 Jul 23 04:42:57 PM PDT 24 Jul 23 04:43:58 PM PDT 24 33830919744 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2300440628 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:47 PM PDT 24 784143625 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4081833968 Jul 23 04:42:56 PM PDT 24 Jul 23 04:43:54 PM PDT 24 1462944638 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.489971908 Jul 23 04:43:15 PM PDT 24 Jul 23 04:43:55 PM PDT 24 672937129 ps
T98 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.82644403 Jul 23 04:43:11 PM PDT 24 Jul 23 04:45:21 PM PDT 24 5951785226 ps
T133 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.834884352 Jul 23 04:42:59 PM PDT 24 Jul 23 04:45:04 PM PDT 24 1896668509 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4220752539 Jul 23 04:43:11 PM PDT 24 Jul 23 04:44:05 PM PDT 24 28055980290 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2243980044 Jul 23 04:43:11 PM PDT 24 Jul 23 04:43:59 PM PDT 24 4184251348 ps
T428 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2501587199 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:09 PM PDT 24 7817131918 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1221150080 Jul 23 04:43:15 PM PDT 24 Jul 23 04:43:54 PM PDT 24 182602497 ps
T128 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.481564738 Jul 23 04:42:56 PM PDT 24 Jul 23 04:46:09 PM PDT 24 1155572798 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2629405306 Jul 23 04:42:55 PM PDT 24 Jul 23 04:44:06 PM PDT 24 13746329369 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3063795284 Jul 23 04:42:56 PM PDT 24 Jul 23 04:43:46 PM PDT 24 2355644148 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1074664659 Jul 23 04:42:54 PM PDT 24 Jul 23 04:44:02 PM PDT 24 2838178580 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.949007011 Jul 23 04:43:10 PM PDT 24 Jul 23 04:44:07 PM PDT 24 1974532608 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1880749406 Jul 23 04:43:04 PM PDT 24 Jul 23 04:44:17 PM PDT 24 17227543360 ps
T129 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.401922236 Jul 23 04:43:14 PM PDT 24 Jul 23 04:46:32 PM PDT 24 6146256531 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1275489077 Jul 23 04:42:53 PM PDT 24 Jul 23 04:43:50 PM PDT 24 1939194046 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1186594216 Jul 23 04:43:05 PM PDT 24 Jul 23 04:47:02 PM PDT 24 26692767911 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1732754004 Jul 23 04:43:14 PM PDT 24 Jul 23 04:44:14 PM PDT 24 16380106468 ps
T99 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.662083456 Jul 23 04:42:44 PM PDT 24 Jul 23 04:44:05 PM PDT 24 3065374135 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1197884189 Jul 23 04:43:03 PM PDT 24 Jul 23 04:44:05 PM PDT 24 7706126146 ps
T135 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3311779970 Jul 23 04:43:06 PM PDT 24 Jul 23 04:45:02 PM PDT 24 483603071 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1428741248 Jul 23 04:43:07 PM PDT 24 Jul 23 04:43:51 PM PDT 24 167402466 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.296722465 Jul 23 04:43:04 PM PDT 24 Jul 23 04:44:01 PM PDT 24 5082177847 ps
T124 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1601773844 Jul 23 04:42:45 PM PDT 24 Jul 23 04:46:26 PM PDT 24 18280632795 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1827489603 Jul 23 04:44:36 PM PDT 24 Jul 23 04:45:18 PM PDT 24 2997018747 ps
T442 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.905565242 Jul 23 04:43:12 PM PDT 24 Jul 23 04:45:29 PM PDT 24 12693602695 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1612544673 Jul 23 04:43:10 PM PDT 24 Jul 23 04:43:53 PM PDT 24 2271433085 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2209489865 Jul 23 04:43:06 PM PDT 24 Jul 23 04:44:05 PM PDT 24 5072039184 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2009552659 Jul 23 04:43:04 PM PDT 24 Jul 23 04:46:15 PM PDT 24 917389961 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.785878940 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:10 PM PDT 24 3445420294 ps
T134 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3544871258 Jul 23 04:43:03 PM PDT 24 Jul 23 04:46:33 PM PDT 24 7881952359 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1412577871 Jul 23 04:42:58 PM PDT 24 Jul 23 04:44:55 PM PDT 24 6236742073 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1815406481 Jul 23 04:42:59 PM PDT 24 Jul 23 04:44:06 PM PDT 24 12025901639 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.672232004 Jul 23 04:42:55 PM PDT 24 Jul 23 04:43:45 PM PDT 24 332510389 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2426862501 Jul 23 04:42:44 PM PDT 24 Jul 23 04:44:58 PM PDT 24 3510877583 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3661603231 Jul 23 04:42:45 PM PDT 24 Jul 23 04:43:59 PM PDT 24 11862540898 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3857756518 Jul 23 04:43:11 PM PDT 24 Jul 23 04:45:19 PM PDT 24 4856925648 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1158189852 Jul 23 04:43:01 PM PDT 24 Jul 23 04:43:50 PM PDT 24 196812473 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.868039645 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:07 PM PDT 24 3675266729 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1429840412 Jul 23 04:43:09 PM PDT 24 Jul 23 04:44:14 PM PDT 24 3276566191 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2059494191 Jul 23 04:43:01 PM PDT 24 Jul 23 04:45:12 PM PDT 24 2170996665 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2214120232 Jul 23 04:42:48 PM PDT 24 Jul 23 04:43:56 PM PDT 24 32943725931 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2010102716 Jul 23 04:42:56 PM PDT 24 Jul 23 04:44:07 PM PDT 24 5714218205 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2162679583 Jul 23 04:42:48 PM PDT 24 Jul 23 04:44:00 PM PDT 24 12090345474 ps
T457 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1194604782 Jul 23 04:43:15 PM PDT 24 Jul 23 04:43:53 PM PDT 24 174601735 ps

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3634550450
Short name T10
Test name
Test status
Simulation time 45510753609 ps
CPU time 195.3 seconds
Started Jul 23 04:38:30 PM PDT 24
Finished Jul 23 04:41:46 PM PDT 24
Peak memory 222380 kb
Host smart-b9c9aaaf-5034-43fd-bb80-f9a33cdce3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634550450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3634550450
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.845038472
Short name T14
Test name
Test status
Simulation time 663911359145 ps
CPU time 2055.84 seconds
Started Jul 23 04:39:03 PM PDT 24
Finished Jul 23 05:13:21 PM PDT 24
Peak memory 248804 kb
Host smart-b9199fbb-14d6-4d7a-b0c1-0e80702e14d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845038472 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.845038472
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4283503973
Short name T13
Test name
Test status
Simulation time 199094769036 ps
CPU time 581.9 seconds
Started Jul 23 04:38:48 PM PDT 24
Finished Jul 23 04:48:32 PM PDT 24
Peak memory 233864 kb
Host smart-34d2fcac-d2a9-48b2-a9bd-c6f5caef3d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283503973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4283503973
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2961549873
Short name T1
Test name
Test status
Simulation time 28823241985 ps
CPU time 138.68 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 220396 kb
Host smart-ce2a4055-2a99-4eeb-923d-d0d1ec1983e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961549873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2961549873
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3733770532
Short name T26
Test name
Test status
Simulation time 94105796566 ps
CPU time 61.15 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:57 PM PDT 24
Peak memory 219080 kb
Host smart-9509ab65-8725-4ff1-a66c-18acff171be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733770532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3733770532
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1799058599
Short name T70
Test name
Test status
Simulation time 9494000879 ps
CPU time 96.67 seconds
Started Jul 23 04:42:54 PM PDT 24
Finished Jul 23 04:45:14 PM PDT 24
Peak memory 213836 kb
Host smart-c9f01be2-68a1-4897-bc43-954f485cadef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799058599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1799058599
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3060589901
Short name T235
Test name
Test status
Simulation time 13216390115 ps
CPU time 515.05 seconds
Started Jul 23 04:38:31 PM PDT 24
Finished Jul 23 04:47:07 PM PDT 24
Peak memory 228432 kb
Host smart-d9623136-7a26-45ec-94b4-a17dcb68a720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060589901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3060589901
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3914794661
Short name T23
Test name
Test status
Simulation time 12104799769 ps
CPU time 125.73 seconds
Started Jul 23 04:38:19 PM PDT 24
Finished Jul 23 04:40:26 PM PDT 24
Peak memory 237384 kb
Host smart-d163eb41-d333-4e27-988e-0a18598e8877
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914794661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3914794661
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.481564738
Short name T128
Test name
Test status
Simulation time 1155572798 ps
CPU time 151.46 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:46:09 PM PDT 24
Peak memory 214700 kb
Host smart-8b7ca516-8c49-4cfa-b7fd-58e13a90778b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481564738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.481564738
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1450143173
Short name T79
Test name
Test status
Simulation time 8103579134 ps
CPU time 20.2 seconds
Started Jul 23 04:42:50 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 210684 kb
Host smart-fd6137d0-e145-4384-bbae-642b100a3aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450143173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1450143173
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3530114705
Short name T12
Test name
Test status
Simulation time 1035914681 ps
CPU time 24.03 seconds
Started Jul 23 04:38:35 PM PDT 24
Finished Jul 23 04:39:00 PM PDT 24
Peak memory 216780 kb
Host smart-b3ecac35-b4f4-48b0-b3df-a18942f20d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530114705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3530114705
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4001330431
Short name T75
Test name
Test status
Simulation time 3557518389 ps
CPU time 30.91 seconds
Started Jul 23 04:38:07 PM PDT 24
Finished Jul 23 04:38:38 PM PDT 24
Peak memory 217092 kb
Host smart-f4556ed3-a97b-49eb-9fd6-3351400a2a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001330431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4001330431
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1412577871
Short name T100
Test name
Test status
Simulation time 6236742073 ps
CPU time 75.5 seconds
Started Jul 23 04:42:58 PM PDT 24
Finished Jul 23 04:44:55 PM PDT 24
Peak memory 215360 kb
Host smart-b64b8a7e-6d94-4ed1-b5f7-9d4b1229cddd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412577871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1412577871
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1892465818
Short name T241
Test name
Test status
Simulation time 1223656898 ps
CPU time 18.54 seconds
Started Jul 23 04:38:30 PM PDT 24
Finished Jul 23 04:38:49 PM PDT 24
Peak memory 219208 kb
Host smart-f64f002e-400b-438f-b07d-cb96ba82dcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892465818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1892465818
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.755438472
Short name T54
Test name
Test status
Simulation time 5971810141 ps
CPU time 55.58 seconds
Started Jul 23 04:38:35 PM PDT 24
Finished Jul 23 04:39:32 PM PDT 24
Peak memory 219268 kb
Host smart-e5a2fdf9-7e79-49b7-872b-16bd3aba3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755438472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.755438472
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.401922236
Short name T129
Test name
Test status
Simulation time 6146256531 ps
CPU time 166.56 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:46:32 PM PDT 24
Peak memory 215348 kb
Host smart-32445a1c-af1d-4eaf-9e81-fa5a5fbb13ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401922236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.401922236
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1601773844
Short name T124
Test name
Test status
Simulation time 18280632795 ps
CPU time 173.12 seconds
Started Jul 23 04:42:45 PM PDT 24
Finished Jul 23 04:46:26 PM PDT 24
Peak memory 214148 kb
Host smart-2892fa80-2ed5-48ad-9fa8-dae74a8dc27b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601773844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1601773844
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3133914530
Short name T115
Test name
Test status
Simulation time 2801348044 ps
CPU time 16.81 seconds
Started Jul 23 04:42:49 PM PDT 24
Finished Jul 23 04:43:52 PM PDT 24
Peak memory 211076 kb
Host smart-0741d154-f7cd-4ad9-bd7b-d39276c99c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133914530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3133914530
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2367224852
Short name T103
Test name
Test status
Simulation time 6379469163 ps
CPU time 48.25 seconds
Started Jul 23 04:38:37 PM PDT 24
Finished Jul 23 04:39:26 PM PDT 24
Peak memory 217176 kb
Host smart-07ee03cb-abd6-4bc7-8ef1-b28dc24776d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367224852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2367224852
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1260773036
Short name T95
Test name
Test status
Simulation time 331632256 ps
CPU time 8.08 seconds
Started Jul 23 04:42:48 PM PDT 24
Finished Jul 23 04:43:42 PM PDT 24
Peak memory 210560 kb
Host smart-dd44964b-ae39-4727-bb10-6be31237657f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260773036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1260773036
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.109828661
Short name T418
Test name
Test status
Simulation time 5097173301 ps
CPU time 16.57 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 210628 kb
Host smart-2da8199e-40c1-4435-ac8a-2bed02f6b54f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109828661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.109828661
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4292419624
Short name T87
Test name
Test status
Simulation time 3379561492 ps
CPU time 15.18 seconds
Started Jul 23 04:43:16 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 211924 kb
Host smart-be2ad77a-9470-4899-a4d5-0a1e6a655f57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292419624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4292419624
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3661603231
Short name T448
Test name
Test status
Simulation time 11862540898 ps
CPU time 25.56 seconds
Started Jul 23 04:42:45 PM PDT 24
Finished Jul 23 04:43:59 PM PDT 24
Peak memory 215940 kb
Host smart-d8bfe460-56ba-4b67-80a9-a168fe6626cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661603231 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3661603231
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.818423292
Short name T370
Test name
Test status
Simulation time 6226332661 ps
CPU time 25.76 seconds
Started Jul 23 04:42:52 PM PDT 24
Finished Jul 23 04:44:02 PM PDT 24
Peak memory 211672 kb
Host smart-b2136e3a-e00f-4f02-8062-ce5ca703d551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818423292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.818423292
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2162679583
Short name T456
Test name
Test status
Simulation time 12090345474 ps
CPU time 25.86 seconds
Started Jul 23 04:42:48 PM PDT 24
Finished Jul 23 04:44:00 PM PDT 24
Peak memory 210532 kb
Host smart-9fbab694-1ccb-4f3b-99f3-78d764c5b48c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162679583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2162679583
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2339605438
Short name T395
Test name
Test status
Simulation time 185877182 ps
CPU time 7.95 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:45 PM PDT 24
Peak memory 210340 kb
Host smart-87018b7d-8e53-497f-bb3e-e06897b8692f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339605438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2339605438
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.785828183
Short name T92
Test name
Test status
Simulation time 15022708794 ps
CPU time 119.44 seconds
Started Jul 23 04:42:48 PM PDT 24
Finished Jul 23 04:45:33 PM PDT 24
Peak memory 210764 kb
Host smart-971b2ad9-a5d0-4c4f-a3d4-840b6ae9ed2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785828183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.785828183
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4201190265
Short name T402
Test name
Test status
Simulation time 37333465774 ps
CPU time 30.77 seconds
Started Jul 23 04:42:46 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 218532 kb
Host smart-5be50c91-01c2-4f9d-af2d-a81e1b43abe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201190265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4201190265
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.316113844
Short name T386
Test name
Test status
Simulation time 4121314549 ps
CPU time 31.29 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:44:16 PM PDT 24
Peak memory 211140 kb
Host smart-290ccc5f-6185-4f28-9564-6aa09d004b68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316113844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.316113844
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4058685075
Short name T394
Test name
Test status
Simulation time 176066615 ps
CPU time 8.32 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:45 PM PDT 24
Peak memory 210492 kb
Host smart-e09d55a5-b703-4c5c-ab6e-3ddd3d86f3c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058685075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4058685075
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.662083456
Short name T99
Test name
Test status
Simulation time 3065374135 ps
CPU time 32.71 seconds
Started Jul 23 04:42:44 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 211172 kb
Host smart-ca39353b-7966-490e-a638-551551988a00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662083456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.662083456
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1843046857
Short name T381
Test name
Test status
Simulation time 14501543909 ps
CPU time 30.1 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:44:11 PM PDT 24
Peak memory 217336 kb
Host smart-816823ae-f807-402a-b504-2646bf74219f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843046857 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1843046857
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.989589325
Short name T416
Test name
Test status
Simulation time 1458039172 ps
CPU time 16.64 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:44:02 PM PDT 24
Peak memory 210340 kb
Host smart-fe5c2172-9c9c-47a2-b6ea-68ee7004a411
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989589325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.989589325
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2214120232
Short name T454
Test name
Test status
Simulation time 32943725931 ps
CPU time 22.25 seconds
Started Jul 23 04:42:48 PM PDT 24
Finished Jul 23 04:43:56 PM PDT 24
Peak memory 210892 kb
Host smart-6f2e6618-4b75-44ae-a7da-823769c7323a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214120232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2214120232
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1732754004
Short name T437
Test name
Test status
Simulation time 16380106468 ps
CPU time 29.59 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:44:14 PM PDT 24
Peak memory 212584 kb
Host smart-dc956044-ef85-46c4-8614-20cfcd00fb31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732754004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1732754004
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.275540141
Short name T374
Test name
Test status
Simulation time 15307109277 ps
CPU time 36.43 seconds
Started Jul 23 04:42:46 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 217584 kb
Host smart-01f11382-25a7-4bb7-9ee8-a948d4fc8a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275540141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.275540141
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.94651464
Short name T61
Test name
Test status
Simulation time 196869966 ps
CPU time 9.26 seconds
Started Jul 23 04:43:01 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 217340 kb
Host smart-a2b244a7-c24a-468b-945b-171a9fca97ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94651464 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.94651464
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2148609478
Short name T86
Test name
Test status
Simulation time 167788355 ps
CPU time 8.32 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 210424 kb
Host smart-9ad9ca79-4663-466f-9927-11cc7ba9397c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148609478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2148609478
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1186594216
Short name T436
Test name
Test status
Simulation time 26692767911 ps
CPU time 200.15 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:47:02 PM PDT 24
Peak memory 214972 kb
Host smart-b99403d5-0187-4e23-8532-32a1a007ec71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186594216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1186594216
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3669923266
Short name T415
Test name
Test status
Simulation time 2426333338 ps
CPU time 22.42 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 212120 kb
Host smart-7ac7356c-b71e-4e0d-800d-c6d8adea31f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669923266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3669923266
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4015809880
Short name T383
Test name
Test status
Simulation time 16344454235 ps
CPU time 33.29 seconds
Started Jul 23 04:43:09 PM PDT 24
Finished Jul 23 04:44:16 PM PDT 24
Peak memory 218788 kb
Host smart-35af75c3-c12e-4f77-bf80-55cb1e21616d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015809880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4015809880
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.726602582
Short name T123
Test name
Test status
Simulation time 639878897 ps
CPU time 155.97 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:46:17 PM PDT 24
Peak memory 213756 kb
Host smart-83a19c8c-88f4-4ff0-be13-cc0580050dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726602582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.726602582
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1158189852
Short name T450
Test name
Test status
Simulation time 196812473 ps
CPU time 9.77 seconds
Started Jul 23 04:43:01 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 217700 kb
Host smart-1275ef72-70ad-4f1b-980c-1ef34c4d41f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158189852 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1158189852
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1428741248
Short name T439
Test name
Test status
Simulation time 167402466 ps
CPU time 8.02 seconds
Started Jul 23 04:43:07 PM PDT 24
Finished Jul 23 04:43:51 PM PDT 24
Peak memory 210492 kb
Host smart-6977b846-3aa8-43a4-9863-fa5b634e8b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428741248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1428741248
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.253254675
Short name T407
Test name
Test status
Simulation time 1092031942 ps
CPU time 56.29 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:44:38 PM PDT 24
Peak memory 213804 kb
Host smart-bcaa5e54-0ed0-4de3-a01f-dee25bd29e84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253254675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.253254675
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1197884189
Short name T438
Test name
Test status
Simulation time 7706126146 ps
CPU time 24.26 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 212232 kb
Host smart-e6562639-0380-47c2-bbb1-3fbe65d7e347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197884189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1197884189
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.296722465
Short name T440
Test name
Test status
Simulation time 5082177847 ps
CPU time 19.7 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 217664 kb
Host smart-6568051f-0363-4890-947b-6865b6309fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296722465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.296722465
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.476989727
Short name T126
Test name
Test status
Simulation time 2028869740 ps
CPU time 161.81 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:46:25 PM PDT 24
Peak memory 213720 kb
Host smart-d758ba04-1ec4-49cb-9c4e-9db511814ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476989727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.476989727
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2209489865
Short name T444
Test name
Test status
Simulation time 5072039184 ps
CPU time 23.29 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 217392 kb
Host smart-e7c5f216-a783-4db3-a73e-b4e5307fa4b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209489865 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2209489865
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.614497841
Short name T406
Test name
Test status
Simulation time 7527794963 ps
CPU time 29.1 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 211700 kb
Host smart-ec169349-6fa7-49df-a365-425f07eadf90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614497841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.614497841
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2073128828
Short name T122
Test name
Test status
Simulation time 23140517905 ps
CPU time 181.58 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:46:42 PM PDT 24
Peak memory 215120 kb
Host smart-db2714c4-75a6-4a08-8dad-fac73b42b17b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073128828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2073128828
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1880749406
Short name T434
Test name
Test status
Simulation time 17227543360 ps
CPU time 35.48 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:44:17 PM PDT 24
Peak memory 212748 kb
Host smart-48bbb41c-6d45-4fab-b470-61b7e0e6562f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880749406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1880749406
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2559186992
Short name T378
Test name
Test status
Simulation time 8905099444 ps
CPU time 25.11 seconds
Started Jul 23 04:43:01 PM PDT 24
Finished Jul 23 04:44:06 PM PDT 24
Peak memory 218888 kb
Host smart-b50485b7-2c6c-4e97-87e9-c442d70e9cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559186992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2559186992
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3716244837
Short name T131
Test name
Test status
Simulation time 3767711637 ps
CPU time 99.5 seconds
Started Jul 23 04:43:07 PM PDT 24
Finished Jul 23 04:45:22 PM PDT 24
Peak memory 213404 kb
Host smart-f166767d-7ce6-4c75-b6ff-aac9a4b8eb21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716244837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3716244837
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2850171938
Short name T365
Test name
Test status
Simulation time 6274691883 ps
CPU time 25.08 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:44:06 PM PDT 24
Peak memory 217512 kb
Host smart-7e4e6da6-7bd4-41fc-b5ab-00d4c74fdcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850171938 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2850171938
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.165535528
Short name T387
Test name
Test status
Simulation time 29602492939 ps
CPU time 29.32 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:44:12 PM PDT 24
Peak memory 212228 kb
Host smart-64616b7f-4233-44b0-bc80-9e63e4574cd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165535528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.165535528
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2956646275
Short name T121
Test name
Test status
Simulation time 3964347539 ps
CPU time 57.41 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:44:38 PM PDT 24
Peak memory 215164 kb
Host smart-1990421d-49c9-40f1-8d94-07b11c293747
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956646275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2956646275
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3740650026
Short name T83
Test name
Test status
Simulation time 8226477664 ps
CPU time 31.85 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:44:13 PM PDT 24
Peak memory 212480 kb
Host smart-27f494c4-3781-4155-9e0d-bce114f93c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740650026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3740650026
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.549878986
Short name T368
Test name
Test status
Simulation time 574410770 ps
CPU time 14.83 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:43:56 PM PDT 24
Peak memory 216736 kb
Host smart-f7fabb53-b348-4bb0-b0f3-a3e65302ba93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549878986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.549878986
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3163957847
Short name T127
Test name
Test status
Simulation time 1398728416 ps
CPU time 86.82 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:45:07 PM PDT 24
Peak memory 213488 kb
Host smart-4a1235b7-bfe5-4594-ac57-9b27359e34c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163957847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3163957847
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1612544673
Short name T443
Test name
Test status
Simulation time 2271433085 ps
CPU time 9.16 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:43:53 PM PDT 24
Peak memory 217052 kb
Host smart-346dbc0f-12e4-4e1e-be81-b432d62a7d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612544673 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1612544673
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1977020851
Short name T417
Test name
Test status
Simulation time 32245360588 ps
CPU time 31.09 seconds
Started Jul 23 04:43:21 PM PDT 24
Finished Jul 23 04:44:19 PM PDT 24
Peak memory 212116 kb
Host smart-6bb7cb7e-737c-4894-855b-32bd7eb45632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977020851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1977020851
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.220870870
Short name T97
Test name
Test status
Simulation time 8988869102 ps
CPU time 109.79 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:45:33 PM PDT 24
Peak memory 218836 kb
Host smart-ec662158-f9af-477c-9a40-97dac6f1c357
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220870870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.220870870
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4220752539
Short name T426
Test name
Test status
Simulation time 28055980290 ps
CPU time 21.23 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 212768 kb
Host smart-02c2a4b9-0766-4b7d-b762-61a76b900162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220752539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4220752539
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.725673441
Short name T391
Test name
Test status
Simulation time 2555141116 ps
CPU time 25.71 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:44:07 PM PDT 24
Peak memory 218028 kb
Host smart-f4af7b95-eb66-4b02-b749-dd57f66eb266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725673441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.725673441
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3311779970
Short name T135
Test name
Test status
Simulation time 483603071 ps
CPU time 80.21 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:45:02 PM PDT 24
Peak memory 212444 kb
Host smart-a0f1c884-56e3-43b3-a895-c88cf7be9c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311779970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3311779970
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2243980044
Short name T427
Test name
Test status
Simulation time 4184251348 ps
CPU time 15.17 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:43:59 PM PDT 24
Peak memory 216848 kb
Host smart-34e343a0-684a-42f9-a53a-16be688f3ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243980044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2243980044
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3367441216
Short name T419
Test name
Test status
Simulation time 18532561241 ps
CPU time 28.87 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:13 PM PDT 24
Peak memory 211908 kb
Host smart-44ea580c-bc00-45f5-a51f-c89501e50b97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367441216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3367441216
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3508178487
Short name T71
Test name
Test status
Simulation time 32817564561 ps
CPU time 86.49 seconds
Started Jul 23 04:43:09 PM PDT 24
Finished Jul 23 04:45:10 PM PDT 24
Peak memory 213784 kb
Host smart-1dc71680-1136-4e08-9e33-ecf8a3ffe1e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508178487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3508178487
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1194604782
Short name T457
Test name
Test status
Simulation time 174601735 ps
CPU time 8.18 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:43:53 PM PDT 24
Peak memory 211284 kb
Host smart-35a33bfd-4109-4de2-a710-be41caaf3bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194604782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1194604782
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.865621627
Short name T380
Test name
Test status
Simulation time 174553457 ps
CPU time 12.06 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:43:56 PM PDT 24
Peak memory 216192 kb
Host smart-ec7ff9ac-9b94-4780-a55d-e8240d1ae42d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865621627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.865621627
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1178379603
Short name T69
Test name
Test status
Simulation time 525819849 ps
CPU time 81.15 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:45:05 PM PDT 24
Peak memory 213428 kb
Host smart-b31a6a20-5e47-498a-a0aa-0cdb5f56bf5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178379603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1178379603
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.733536070
Short name T411
Test name
Test status
Simulation time 737279783 ps
CPU time 8.46 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:43:52 PM PDT 24
Peak memory 214224 kb
Host smart-49c641c2-0b2b-44c2-a6f2-f7cd74df0a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733536070 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.733536070
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.138141554
Short name T119
Test name
Test status
Simulation time 7923738566 ps
CPU time 19.64 seconds
Started Jul 23 04:43:12 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 212072 kb
Host smart-0eba82ae-721a-49f4-8985-9c965d800690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138141554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.138141554
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4226592276
Short name T102
Test name
Test status
Simulation time 32829775590 ps
CPU time 148.76 seconds
Started Jul 23 04:43:21 PM PDT 24
Finished Jul 23 04:46:16 PM PDT 24
Peak memory 214948 kb
Host smart-20144bd8-9902-4452-9b2d-e75d039cac2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226592276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4226592276
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4117190451
Short name T114
Test name
Test status
Simulation time 3434435368 ps
CPU time 17.91 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:44:02 PM PDT 24
Peak memory 212064 kb
Host smart-f94cb4a4-b71e-4438-ab96-4cb60bb4dbb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117190451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4117190451
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.949007011
Short name T433
Test name
Test status
Simulation time 1974532608 ps
CPU time 23.41 seconds
Started Jul 23 04:43:10 PM PDT 24
Finished Jul 23 04:44:07 PM PDT 24
Peak memory 218168 kb
Host smart-8bd7d5f4-da94-4fee-94d1-711514346c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949007011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.949007011
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3727448821
Short name T384
Test name
Test status
Simulation time 5878204126 ps
CPU time 95.82 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:45:20 PM PDT 24
Peak memory 218916 kb
Host smart-02428b7f-dad8-481f-8554-0f5070824163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727448821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3727448821
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1221150080
Short name T429
Test name
Test status
Simulation time 182602497 ps
CPU time 8.33 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 214024 kb
Host smart-2bf795ce-b003-494e-95e2-7429d2ad6348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221150080 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1221150080
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3882062160
Short name T371
Test name
Test status
Simulation time 661504867 ps
CPU time 7.95 seconds
Started Jul 23 04:43:13 PM PDT 24
Finished Jul 23 04:43:52 PM PDT 24
Peak memory 210828 kb
Host smart-3f1ec072-e55d-418e-af8c-ea4a112c6894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882062160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3882062160
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1827489603
Short name T441
Test name
Test status
Simulation time 2997018747 ps
CPU time 35.98 seconds
Started Jul 23 04:44:36 PM PDT 24
Finished Jul 23 04:45:18 PM PDT 24
Peak memory 213928 kb
Host smart-f976c834-fd1f-4b73-b9d6-0a129ef5416c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827489603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1827489603
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.489971908
Short name T425
Test name
Test status
Simulation time 672937129 ps
CPU time 10.31 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 210972 kb
Host smart-d344df04-7534-4e17-97d6-18449be99bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489971908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.489971908
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3520817815
Short name T412
Test name
Test status
Simulation time 6281449691 ps
CPU time 26.3 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 217516 kb
Host smart-8dde905f-a336-4c1f-ad12-0175c265a50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520817815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3520817815
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4273040742
Short name T60
Test name
Test status
Simulation time 4487308291 ps
CPU time 154.32 seconds
Started Jul 23 04:43:22 PM PDT 24
Finished Jul 23 04:46:22 PM PDT 24
Peak memory 214092 kb
Host smart-f94a79a5-b462-490d-9cf2-c3b864ea8ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273040742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4273040742
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2863878508
Short name T385
Test name
Test status
Simulation time 8252859719 ps
CPU time 16.18 seconds
Started Jul 23 04:43:22 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 215764 kb
Host smart-6924d52e-7e39-497a-a935-11a8b66259ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863878508 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2863878508
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3651246463
Short name T93
Test name
Test status
Simulation time 4824013491 ps
CPU time 16.7 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 211808 kb
Host smart-78997bfc-a876-42fa-98d0-3858505f2097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651246463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3651246463
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.82644403
Short name T98
Test name
Test status
Simulation time 5951785226 ps
CPU time 97 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:45:21 PM PDT 24
Peak memory 215844 kb
Host smart-5a83efba-6b31-41bc-992f-c13be56e3776
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82644403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pas
sthru_mem_tl_intg_err.82644403
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1102922053
Short name T117
Test name
Test status
Simulation time 15948351278 ps
CPU time 26.27 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 212476 kb
Host smart-38a712a0-1804-4ecf-b6af-f796b79ff8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102922053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1102922053
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4213439601
Short name T409
Test name
Test status
Simulation time 6117507176 ps
CPU time 20.25 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 217024 kb
Host smart-c6f82230-0955-4b2a-abea-316ec8a15a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213439601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4213439601
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3952993081
Short name T130
Test name
Test status
Simulation time 6418464468 ps
CPU time 88.39 seconds
Started Jul 23 04:43:09 PM PDT 24
Finished Jul 23 04:45:12 PM PDT 24
Peak memory 213600 kb
Host smart-86765afb-ea25-4d36-92f9-a420ce50ffdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952993081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3952993081
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3917638663
Short name T401
Test name
Test status
Simulation time 26240828125 ps
CPU time 29.27 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:44:14 PM PDT 24
Peak memory 213936 kb
Host smart-7e16804b-5f16-4984-adca-5afab1b5893e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917638663 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3917638663
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3369557446
Short name T80
Test name
Test status
Simulation time 2305924064 ps
CPU time 12.24 seconds
Started Jul 23 04:43:13 PM PDT 24
Finished Jul 23 04:43:57 PM PDT 24
Peak memory 210876 kb
Host smart-fd61939e-f3f9-48e9-b821-6bf06a089eea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369557446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3369557446
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.905565242
Short name T442
Test name
Test status
Simulation time 12693602695 ps
CPU time 104.89 seconds
Started Jul 23 04:43:12 PM PDT 24
Finished Jul 23 04:45:29 PM PDT 24
Peak memory 213844 kb
Host smart-a53bf500-b9bb-40da-9dca-a213ac9e866c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905565242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.905565242
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2753699702
Short name T116
Test name
Test status
Simulation time 3273519378 ps
CPU time 17.8 seconds
Started Jul 23 04:43:16 PM PDT 24
Finished Jul 23 04:44:03 PM PDT 24
Peak memory 212160 kb
Host smart-d4e3d403-c9a2-4c13-831d-95afce03196e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753699702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2753699702
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.422142165
Short name T367
Test name
Test status
Simulation time 21323289539 ps
CPU time 19.81 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 218720 kb
Host smart-977a4af8-9639-4231-9d9f-b135cefbc69d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422142165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.422142165
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3857756518
Short name T449
Test name
Test status
Simulation time 4856925648 ps
CPU time 94.76 seconds
Started Jul 23 04:43:11 PM PDT 24
Finished Jul 23 04:45:19 PM PDT 24
Peak memory 218892 kb
Host smart-4f3f025b-f4a2-42ba-bd7b-2b3451664c69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857756518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3857756518
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3063795284
Short name T431
Test name
Test status
Simulation time 2355644148 ps
CPU time 8.26 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:43:46 PM PDT 24
Peak memory 210504 kb
Host smart-171454c5-4fe2-4070-95b6-9f16eb3ea10c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063795284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3063795284
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1275489077
Short name T435
Test name
Test status
Simulation time 1939194046 ps
CPU time 13.14 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 210444 kb
Host smart-64fb7c3a-9349-4408-bc16-73365927d2ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275489077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1275489077
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2401463412
Short name T120
Test name
Test status
Simulation time 735631123 ps
CPU time 14.81 seconds
Started Jul 23 04:42:45 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 211972 kb
Host smart-4dd0a0e3-f9d0-4a40-adcf-051cf85d905b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401463412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2401463412
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1074664659
Short name T432
Test name
Test status
Simulation time 2838178580 ps
CPU time 24.63 seconds
Started Jul 23 04:42:54 PM PDT 24
Finished Jul 23 04:44:02 PM PDT 24
Peak memory 217432 kb
Host smart-b9ff5b88-9bd4-4cf0-a49c-35e0a576b1c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074664659 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1074664659
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1815406481
Short name T94
Test name
Test status
Simulation time 12025901639 ps
CPU time 26.78 seconds
Started Jul 23 04:42:59 PM PDT 24
Finished Jul 23 04:44:06 PM PDT 24
Peak memory 212028 kb
Host smart-1577bab0-f607-4066-b895-db92a256f976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815406481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1815406481
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1665149690
Short name T420
Test name
Test status
Simulation time 5261711254 ps
CPU time 32.45 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 210780 kb
Host smart-4ed1dc91-f28d-4622-a5c9-e31f88116416
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665149690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1665149690
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.882258866
Short name T382
Test name
Test status
Simulation time 4506992057 ps
CPU time 28.18 seconds
Started Jul 23 04:43:17 PM PDT 24
Finished Jul 23 04:44:15 PM PDT 24
Peak memory 210536 kb
Host smart-419e7b4d-0aa8-4fc7-8155-ecfafd1dcdd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882258866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
882258866
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.544373381
Short name T90
Test name
Test status
Simulation time 719201325 ps
CPU time 38.26 seconds
Started Jul 23 04:42:45 PM PDT 24
Finished Jul 23 04:44:11 PM PDT 24
Peak memory 211260 kb
Host smart-47f97879-1957-4c7d-8c90-b6c87ea3ac7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544373381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.544373381
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4277414731
Short name T81
Test name
Test status
Simulation time 254877595 ps
CPU time 9.84 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 211120 kb
Host smart-c7bfff98-1e0b-4150-8e7d-33399dbe9fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277414731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4277414731
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1104004397
Short name T379
Test name
Test status
Simulation time 176437408 ps
CPU time 11.11 seconds
Started Jul 23 04:42:52 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 215912 kb
Host smart-d46be649-38a8-4417-8431-d1b477c83f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104004397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1104004397
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2426862501
Short name T125
Test name
Test status
Simulation time 3510877583 ps
CPU time 85.42 seconds
Started Jul 23 04:42:44 PM PDT 24
Finished Jul 23 04:44:58 PM PDT 24
Peak memory 213152 kb
Host smart-1522010e-3cc5-4126-84be-57f344435a82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426862501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2426862501
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1893456248
Short name T413
Test name
Test status
Simulation time 16111806565 ps
CPU time 30.38 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:44:11 PM PDT 24
Peak memory 211492 kb
Host smart-9e122bc5-e3e4-4dab-a378-0b286ec7e5cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893456248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1893456248
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.990311374
Short name T369
Test name
Test status
Simulation time 717357672 ps
CPU time 8.25 seconds
Started Jul 23 04:42:57 PM PDT 24
Finished Jul 23 04:43:46 PM PDT 24
Peak memory 210500 kb
Host smart-387e067a-fa38-4fad-98dd-dde8cb947850
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990311374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.990311374
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2629405306
Short name T430
Test name
Test status
Simulation time 13746329369 ps
CPU time 28.94 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:44:06 PM PDT 24
Peak memory 210664 kb
Host smart-6134bf15-ea6c-4a8c-8ced-3845e1c14fb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629405306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2629405306
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2300440628
Short name T423
Test name
Test status
Simulation time 784143625 ps
CPU time 9.58 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 217112 kb
Host smart-4cbf70fc-60b4-4d23-82ff-0c662e88af80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300440628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2300440628
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1661091659
Short name T404
Test name
Test status
Simulation time 1354947368 ps
CPU time 16.63 seconds
Started Jul 23 04:42:57 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 211744 kb
Host smart-2b6d52ce-3bc9-4fd8-a949-28abebd73506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661091659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1661091659
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2992006756
Short name T373
Test name
Test status
Simulation time 1100120080 ps
CPU time 8.04 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:45 PM PDT 24
Peak memory 210340 kb
Host smart-10ab5868-86b7-4be7-baab-aac56d076e22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992006756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2992006756
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2440125643
Short name T388
Test name
Test status
Simulation time 3899968189 ps
CPU time 13.64 seconds
Started Jul 23 04:42:54 PM PDT 24
Finished Jul 23 04:43:51 PM PDT 24
Peak memory 210372 kb
Host smart-8b5ec80e-26a3-4458-8fa1-c4ed62e5feed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440125643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2440125643
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2820807010
Short name T84
Test name
Test status
Simulation time 6079865959 ps
CPU time 92.49 seconds
Started Jul 23 04:42:59 PM PDT 24
Finished Jul 23 04:45:12 PM PDT 24
Peak memory 214196 kb
Host smart-add2d7d6-418e-4f38-b5a3-2ab0a4f16764
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820807010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2820807010
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.635649757
Short name T396
Test name
Test status
Simulation time 8759602561 ps
CPU time 26.01 seconds
Started Jul 23 04:42:57 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 212580 kb
Host smart-e82c0bc6-be05-4293-bafd-aed6bda58420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635649757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.635649757
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2994232084
Short name T405
Test name
Test status
Simulation time 319739706 ps
CPU time 12.55 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 216112 kb
Host smart-bde344ca-3c9c-4645-803b-640f934d3547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994232084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2994232084
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.976053113
Short name T132
Test name
Test status
Simulation time 4357971170 ps
CPU time 172.68 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:46:30 PM PDT 24
Peak memory 214124 kb
Host smart-9af5751d-c33c-4f9a-af03-d1edfbce878d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976053113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.976053113
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3585812084
Short name T422
Test name
Test status
Simulation time 33830919744 ps
CPU time 20.32 seconds
Started Jul 23 04:42:57 PM PDT 24
Finished Jul 23 04:43:58 PM PDT 24
Peak memory 211848 kb
Host smart-d0dcc6af-9fac-491c-acaf-7acdd7092fc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585812084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3585812084
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1483094948
Short name T72
Test name
Test status
Simulation time 1442198552 ps
CPU time 16.96 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 211300 kb
Host smart-ca73d9c4-1f68-4d75-bfe8-1391547300dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483094948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1483094948
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2196335189
Short name T400
Test name
Test status
Simulation time 785438848 ps
CPU time 20.22 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:57 PM PDT 24
Peak memory 211812 kb
Host smart-767792f9-9f85-4004-a859-b76f1ac24e9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196335189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2196335189
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2036631841
Short name T366
Test name
Test status
Simulation time 1197918701 ps
CPU time 9.8 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:46 PM PDT 24
Peak memory 217088 kb
Host smart-e9b41723-1c28-4a5d-ba94-5c428e05a49e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036631841 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2036631841
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3987035118
Short name T96
Test name
Test status
Simulation time 4111818946 ps
CPU time 30.5 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:44:08 PM PDT 24
Peak memory 211424 kb
Host smart-7c7d1c86-4aa9-4cba-b7e6-420160ef48a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987035118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3987035118
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3433578472
Short name T414
Test name
Test status
Simulation time 10861129690 ps
CPU time 30.33 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:08 PM PDT 24
Peak memory 210784 kb
Host smart-d390fd6a-55bc-44b2-9ca8-26ce9ca6291b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433578472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3433578472
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2304376426
Short name T390
Test name
Test status
Simulation time 751217547 ps
CPU time 8.06 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:43:45 PM PDT 24
Peak memory 210356 kb
Host smart-ec4fae81-c5e4-4daa-882c-e82656e55f1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304376426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2304376426
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2956100694
Short name T393
Test name
Test status
Simulation time 8998006400 ps
CPU time 62.01 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:44:39 PM PDT 24
Peak memory 213592 kb
Host smart-d71e6d21-ff69-49a1-907b-3daee51d8b0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956100694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2956100694
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1678930101
Short name T113
Test name
Test status
Simulation time 523707164 ps
CPU time 12.27 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 212180 kb
Host smart-0b04fdc7-67e4-4058-919d-f061f8f2401a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678930101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1678930101
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2010102716
Short name T455
Test name
Test status
Simulation time 5714218205 ps
CPU time 28.96 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:07 PM PDT 24
Peak memory 218580 kb
Host smart-c2b7ab1c-40cf-4569-ace4-31a0353e90d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010102716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2010102716
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1089995786
Short name T421
Test name
Test status
Simulation time 16541977048 ps
CPU time 31.34 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:09 PM PDT 24
Peak memory 218352 kb
Host smart-87512658-79a3-48dd-ba84-1dd0d1819f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089995786 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1089995786
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2501587199
Short name T428
Test name
Test status
Simulation time 7817131918 ps
CPU time 31 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:09 PM PDT 24
Peak memory 212080 kb
Host smart-a110a254-9dc8-4c24-9f19-aa6dc521f2cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501587199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2501587199
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.434511194
Short name T392
Test name
Test status
Simulation time 718797816 ps
CPU time 36.92 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:44:14 PM PDT 24
Peak memory 213672 kb
Host smart-1cbca92e-8b26-417b-870f-af071478b63f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434511194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.434511194
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.868039645
Short name T451
Test name
Test status
Simulation time 3675266729 ps
CPU time 29.19 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:07 PM PDT 24
Peak memory 212372 kb
Host smart-a5690070-f350-44d1-8a4a-cb7f88ba2b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868039645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.868039645
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1437121910
Short name T377
Test name
Test status
Simulation time 729587433 ps
CPU time 15.21 seconds
Started Jul 23 04:42:57 PM PDT 24
Finished Jul 23 04:43:53 PM PDT 24
Peak memory 218180 kb
Host smart-654084b8-9840-4759-8ecb-0e7728d571fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437121910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1437121910
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.834884352
Short name T133
Test name
Test status
Simulation time 1896668509 ps
CPU time 84.15 seconds
Started Jul 23 04:42:59 PM PDT 24
Finished Jul 23 04:45:04 PM PDT 24
Peak memory 213408 kb
Host smart-dcb517aa-6010-4d71-8bf4-2e27bc24debf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834884352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.834884352
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4081833968
Short name T424
Test name
Test status
Simulation time 1462944638 ps
CPU time 16.53 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 214356 kb
Host smart-11875941-7dd8-4573-8a86-40f77c16a713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081833968 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4081833968
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.672232004
Short name T447
Test name
Test status
Simulation time 332510389 ps
CPU time 8.08 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:43:45 PM PDT 24
Peak memory 210800 kb
Host smart-7ffbef36-edd4-4d27-99fd-05ae9aa4173e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672232004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.672232004
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2861335528
Short name T82
Test name
Test status
Simulation time 12059333619 ps
CPU time 55.11 seconds
Started Jul 23 04:42:55 PM PDT 24
Finished Jul 23 04:44:32 PM PDT 24
Peak memory 218868 kb
Host smart-549ac35a-9cbb-4a04-9199-c4f81cb5382f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861335528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2861335528
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.785878940
Short name T446
Test name
Test status
Simulation time 3445420294 ps
CPU time 31.87 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 212252 kb
Host smart-5fa275c7-9037-4d9e-be52-1efb2ab01462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785878940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.785878940
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1333444226
Short name T389
Test name
Test status
Simulation time 508522433 ps
CPU time 13.02 seconds
Started Jul 23 04:42:54 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 217108 kb
Host smart-35d3f337-fea6-412a-a233-b34f85b7dad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333444226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1333444226
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.752723430
Short name T398
Test name
Test status
Simulation time 28202369266 ps
CPU time 31.08 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:44:12 PM PDT 24
Peak memory 218392 kb
Host smart-e26a5aaa-d49f-49b6-9648-b4343ea64b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752723430 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.752723430
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2805658928
Short name T399
Test name
Test status
Simulation time 3344706838 ps
CPU time 26.38 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:44:09 PM PDT 24
Peak memory 211776 kb
Host smart-4371959e-fc55-4203-8d17-99ef9841f2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805658928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2805658928
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.452154179
Short name T85
Test name
Test status
Simulation time 13895321361 ps
CPU time 116.13 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:45:37 PM PDT 24
Peak memory 213896 kb
Host smart-6600dd51-abbf-40dd-bc39-2d1432fc37c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452154179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.452154179
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.923648850
Short name T410
Test name
Test status
Simulation time 13301480735 ps
CPU time 25.78 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:44:08 PM PDT 24
Peak memory 212264 kb
Host smart-140b6d3a-8972-4595-8dcc-a5e8480decaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923648850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.923648850
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2931261984
Short name T59
Test name
Test status
Simulation time 1318244412 ps
CPU time 19.47 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 217032 kb
Host smart-f6085dba-00f8-442d-9b34-cfe2091c383b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931261984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2931261984
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2059494191
Short name T453
Test name
Test status
Simulation time 2170996665 ps
CPU time 91.26 seconds
Started Jul 23 04:43:01 PM PDT 24
Finished Jul 23 04:45:12 PM PDT 24
Peak memory 212084 kb
Host smart-61b1c274-672b-4dd6-9f49-5188983b66ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059494191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2059494191
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2094320022
Short name T372
Test name
Test status
Simulation time 1917614722 ps
CPU time 19.52 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:44:00 PM PDT 24
Peak memory 217172 kb
Host smart-b37b2468-2ba8-473c-bf0a-5b4c9925082a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094320022 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2094320022
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2220951960
Short name T397
Test name
Test status
Simulation time 1649984219 ps
CPU time 7.79 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:43:51 PM PDT 24
Peak memory 210936 kb
Host smart-d2210027-df95-4358-967c-f98e3f0999b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220951960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2220951960
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3119056975
Short name T376
Test name
Test status
Simulation time 5698187728 ps
CPU time 37.69 seconds
Started Jul 23 04:43:08 PM PDT 24
Finished Jul 23 04:44:21 PM PDT 24
Peak memory 213424 kb
Host smart-0fa870dc-d96c-4a2d-b4ad-cc4c511246c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119056975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3119056975
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.165076372
Short name T408
Test name
Test status
Simulation time 8725217756 ps
CPU time 31.08 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:44:12 PM PDT 24
Peak memory 212536 kb
Host smart-616800b5-f77f-4a81-abfc-987f09c555e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165076372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.165076372
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.724720403
Short name T403
Test name
Test status
Simulation time 2066166934 ps
CPU time 23.76 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 216968 kb
Host smart-d8fce28a-033a-416a-8a0e-b9c59b6161cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724720403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.724720403
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2009552659
Short name T445
Test name
Test status
Simulation time 917389961 ps
CPU time 153.76 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:46:15 PM PDT 24
Peak memory 213820 kb
Host smart-1d71eedc-cf7e-4232-bca1-145ea0c89f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009552659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2009552659
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4023953967
Short name T78
Test name
Test status
Simulation time 4258467199 ps
CPU time 15.3 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:43:56 PM PDT 24
Peak memory 214704 kb
Host smart-debe4693-b33f-4ff8-8062-83cc4b713573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023953967 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4023953967
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2799652781
Short name T91
Test name
Test status
Simulation time 1314504717 ps
CPU time 9.75 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 210964 kb
Host smart-84e19591-7078-4753-80ee-5b35fe1c60e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799652781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2799652781
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2185599010
Short name T101
Test name
Test status
Simulation time 41346753769 ps
CPU time 101.91 seconds
Started Jul 23 04:43:02 PM PDT 24
Finished Jul 23 04:45:23 PM PDT 24
Peak memory 215272 kb
Host smart-ade61b8a-de84-49a3-9bd9-78ec175e9f80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185599010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2185599010
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1429840412
Short name T452
Test name
Test status
Simulation time 3276566191 ps
CPU time 31.15 seconds
Started Jul 23 04:43:09 PM PDT 24
Finished Jul 23 04:44:14 PM PDT 24
Peak memory 212268 kb
Host smart-461b4459-4cb1-4242-9b38-76d78fb66870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429840412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1429840412
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1127303706
Short name T375
Test name
Test status
Simulation time 360268573 ps
CPU time 13.1 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 218320 kb
Host smart-e66a35b8-29bb-4dbd-9580-e274090300af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127303706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1127303706
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3544871258
Short name T134
Test name
Test status
Simulation time 7881952359 ps
CPU time 171.73 seconds
Started Jul 23 04:43:03 PM PDT 24
Finished Jul 23 04:46:33 PM PDT 24
Peak memory 213080 kb
Host smart-ce7b3232-73df-4171-9052-7b37dc58c7a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544871258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3544871258
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3442721326
Short name T287
Test name
Test status
Simulation time 592810518544 ps
CPU time 619.32 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:48:28 PM PDT 24
Peak memory 233212 kb
Host smart-cc389466-20f8-4d35-a353-466e62aa9579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442721326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3442721326
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.759785410
Short name T33
Test name
Test status
Simulation time 5673469372 ps
CPU time 38.49 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:38:43 PM PDT 24
Peak memory 219108 kb
Host smart-32f91d8a-a0a9-4f66-adcb-aa3c1c38af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759785410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.759785410
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4027569956
Short name T19
Test name
Test status
Simulation time 9965509527 ps
CPU time 24.37 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:38:40 PM PDT 24
Peak memory 217636 kb
Host smart-6e64503f-61f2-445f-8a6d-98e4bc2f0bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027569956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4027569956
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2486647827
Short name T27
Test name
Test status
Simulation time 13874221877 ps
CPU time 242.75 seconds
Started Jul 23 04:38:03 PM PDT 24
Finished Jul 23 04:42:07 PM PDT 24
Peak memory 237136 kb
Host smart-baf99261-14bc-4164-a94e-c22e858aa214
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486647827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2486647827
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1804232899
Short name T166
Test name
Test status
Simulation time 42964541212 ps
CPU time 86.53 seconds
Started Jul 23 04:38:05 PM PDT 24
Finished Jul 23 04:39:33 PM PDT 24
Peak memory 217276 kb
Host smart-1921d7d2-371b-4304-a00e-ae79977407ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804232899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1804232899
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1563349939
Short name T155
Test name
Test status
Simulation time 9895855353 ps
CPU time 23.64 seconds
Started Jul 23 04:38:02 PM PDT 24
Finished Jul 23 04:38:27 PM PDT 24
Peak memory 216616 kb
Host smart-c3e54d91-3fc5-43ae-80e8-67b59ddf4d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563349939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1563349939
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2484417227
Short name T312
Test name
Test status
Simulation time 7579221438 ps
CPU time 31.99 seconds
Started Jul 23 04:38:10 PM PDT 24
Finished Jul 23 04:38:43 PM PDT 24
Peak memory 217420 kb
Host smart-2943c106-6e00-416d-9e06-e55273d88791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484417227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2484417227
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2343781604
Short name T249
Test name
Test status
Simulation time 62702375579 ps
CPU time 606 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:48:13 PM PDT 24
Peak memory 234348 kb
Host smart-8c345146-fd77-4cf2-a776-92281a8adbad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343781604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2343781604
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3260884962
Short name T348
Test name
Test status
Simulation time 71330517291 ps
CPU time 74.65 seconds
Started Jul 23 04:38:04 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 219196 kb
Host smart-c863c6e4-d121-4a91-b0cc-12999611aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260884962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3260884962
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2277347036
Short name T140
Test name
Test status
Simulation time 829522264 ps
CPU time 10.42 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:38:17 PM PDT 24
Peak memory 219212 kb
Host smart-569c2044-7648-4cb9-a890-cdeef4ca6291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277347036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2277347036
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3724051490
Short name T24
Test name
Test status
Simulation time 7123377155 ps
CPU time 241.31 seconds
Started Jul 23 04:38:21 PM PDT 24
Finished Jul 23 04:42:23 PM PDT 24
Peak memory 239108 kb
Host smart-3dbb04e0-e3ab-40d9-a486-ebc10f978880
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724051490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3724051490
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.44989895
Short name T265
Test name
Test status
Simulation time 18519156787 ps
CPU time 75.84 seconds
Started Jul 23 04:38:06 PM PDT 24
Finished Jul 23 04:39:23 PM PDT 24
Peak memory 216904 kb
Host smart-23f9d0fd-7d43-430d-9d3b-466a1ddda796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44989895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.44989895
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2805260155
Short name T229
Test name
Test status
Simulation time 21521864208 ps
CPU time 174.67 seconds
Started Jul 23 04:38:01 PM PDT 24
Finished Jul 23 04:40:56 PM PDT 24
Peak memory 219260 kb
Host smart-46029aa6-3ace-4d22-8443-0656e3497ea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805260155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2805260155
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.192439104
Short name T323
Test name
Test status
Simulation time 435558512 ps
CPU time 8.24 seconds
Started Jul 23 04:38:27 PM PDT 24
Finished Jul 23 04:38:36 PM PDT 24
Peak memory 216984 kb
Host smart-457ef799-80bf-47c9-97a7-b191202e755f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192439104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.192439104
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.389598639
Short name T21
Test name
Test status
Simulation time 34391928773 ps
CPU time 297.69 seconds
Started Jul 23 04:38:26 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 219412 kb
Host smart-d4e2c89f-32dc-45f6-99d9-56761f914390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389598639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.389598639
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4081584961
Short name T62
Test name
Test status
Simulation time 38275559791 ps
CPU time 35.66 seconds
Started Jul 23 04:38:26 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 219228 kb
Host smart-79d3b292-187f-4bb9-afb9-aa78c9009f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081584961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4081584961
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.90061226
Short name T343
Test name
Test status
Simulation time 15740601188 ps
CPU time 32.76 seconds
Started Jul 23 04:38:27 PM PDT 24
Finished Jul 23 04:39:00 PM PDT 24
Peak memory 219232 kb
Host smart-f9ce20c6-2d8c-43a7-8745-1b474d4e9442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90061226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.90061226
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4103604426
Short name T20
Test name
Test status
Simulation time 6926319942 ps
CPU time 30.74 seconds
Started Jul 23 04:38:25 PM PDT 24
Finished Jul 23 04:38:57 PM PDT 24
Peak memory 217872 kb
Host smart-a1a19fbc-0e3d-4e3a-a53e-823df977058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103604426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4103604426
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.430562745
Short name T245
Test name
Test status
Simulation time 6302408672 ps
CPU time 57.15 seconds
Started Jul 23 04:38:31 PM PDT 24
Finished Jul 23 04:39:29 PM PDT 24
Peak memory 216968 kb
Host smart-e9e962ab-99ef-477e-8faf-d9d92b76ed03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430562745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.430562745
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.850859168
Short name T221
Test name
Test status
Simulation time 174489161 ps
CPU time 8.16 seconds
Started Jul 23 04:38:30 PM PDT 24
Finished Jul 23 04:38:39 PM PDT 24
Peak memory 217096 kb
Host smart-cf741ea1-365e-4d2c-a0db-98dccc5e04e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850859168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.850859168
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.572219114
Short name T42
Test name
Test status
Simulation time 28860610036 ps
CPU time 434.67 seconds
Started Jul 23 04:38:27 PM PDT 24
Finished Jul 23 04:45:42 PM PDT 24
Peak memory 240360 kb
Host smart-4c87471d-a4e0-45d4-b404-469207731f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572219114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.572219114
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2617374825
Short name T111
Test name
Test status
Simulation time 9882949864 ps
CPU time 48.33 seconds
Started Jul 23 04:38:37 PM PDT 24
Finished Jul 23 04:39:26 PM PDT 24
Peak memory 219260 kb
Host smart-a5e22d61-3200-4ea0-bec3-05270f41ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617374825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2617374825
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4278042131
Short name T345
Test name
Test status
Simulation time 725106760 ps
CPU time 10.46 seconds
Started Jul 23 04:38:24 PM PDT 24
Finished Jul 23 04:38:35 PM PDT 24
Peak memory 219180 kb
Host smart-ee410d87-e728-4e71-b1e5-75cc7a795311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278042131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4278042131
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4231932160
Short name T288
Test name
Test status
Simulation time 21191106892 ps
CPU time 63.68 seconds
Started Jul 23 04:38:16 PM PDT 24
Finished Jul 23 04:39:22 PM PDT 24
Peak memory 216092 kb
Host smart-7600d0dd-85ad-4142-b0d9-2092433eaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231932160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4231932160
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1285876236
Short name T251
Test name
Test status
Simulation time 17917946594 ps
CPU time 44.92 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:39:21 PM PDT 24
Peak memory 219160 kb
Host smart-2bfc7cc8-e68c-40f5-9602-ca5f11174138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285876236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1285876236
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2834208238
Short name T313
Test name
Test status
Simulation time 3154581877 ps
CPU time 25.14 seconds
Started Jul 23 04:38:19 PM PDT 24
Finished Jul 23 04:38:45 PM PDT 24
Peak memory 217092 kb
Host smart-97cd7af7-97fd-4f34-b664-766d75c8ce60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834208238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2834208238
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1168299088
Short name T29
Test name
Test status
Simulation time 10856084429 ps
CPU time 174.6 seconds
Started Jul 23 04:38:29 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 225052 kb
Host smart-2d2a8404-65ce-4ca8-bd5e-b34f88826e1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168299088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1168299088
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3825526435
Short name T197
Test name
Test status
Simulation time 8069450084 ps
CPU time 33.39 seconds
Started Jul 23 04:38:37 PM PDT 24
Finished Jul 23 04:39:11 PM PDT 24
Peak memory 211572 kb
Host smart-431e1129-da91-4c6f-a366-dde3864a1c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825526435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3825526435
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.100808780
Short name T364
Test name
Test status
Simulation time 6353970613 ps
CPU time 23.97 seconds
Started Jul 23 04:38:26 PM PDT 24
Finished Jul 23 04:38:50 PM PDT 24
Peak memory 216552 kb
Host smart-8ffa2d9c-3cb7-49ab-8f7e-7f533d0a9cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100808780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.100808780
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3851543388
Short name T88
Test name
Test status
Simulation time 12545831538 ps
CPU time 65.25 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:39:39 PM PDT 24
Peak memory 220648 kb
Host smart-cba9363c-76da-43cb-93d6-92bbad729638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851543388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3851543388
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2485398196
Short name T333
Test name
Test status
Simulation time 11028468047 ps
CPU time 21.4 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:19 PM PDT 24
Peak memory 217372 kb
Host smart-1409190f-cfe1-463c-a543-95cf82aa88f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485398196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2485398196
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2965202871
Short name T178
Test name
Test status
Simulation time 31572251953 ps
CPU time 65.24 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:39:47 PM PDT 24
Peak memory 219292 kb
Host smart-dac1c778-a00d-4005-bc5a-036da4de129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965202871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2965202871
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1579465591
Short name T322
Test name
Test status
Simulation time 1338657931 ps
CPU time 10.16 seconds
Started Jul 23 04:38:30 PM PDT 24
Finished Jul 23 04:38:41 PM PDT 24
Peak memory 219236 kb
Host smart-c162986b-2d6c-44f5-80fc-a14cc3d8f748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579465591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1579465591
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.739697717
Short name T189
Test name
Test status
Simulation time 612595897 ps
CPU time 20.87 seconds
Started Jul 23 04:38:21 PM PDT 24
Finished Jul 23 04:38:42 PM PDT 24
Peak memory 215824 kb
Host smart-b9e68423-42a3-41c4-b598-edd127b4d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739697717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.739697717
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.775910389
Short name T274
Test name
Test status
Simulation time 38609947970 ps
CPU time 83.51 seconds
Started Jul 23 04:38:29 PM PDT 24
Finished Jul 23 04:39:53 PM PDT 24
Peak memory 219248 kb
Host smart-2b6bc72a-9eb2-4aa4-815b-5aa0c44297db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775910389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.775910389
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.135529633
Short name T16
Test name
Test status
Simulation time 307845846414 ps
CPU time 3334.28 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 05:34:20 PM PDT 24
Peak memory 252160 kb
Host smart-fa05bc35-22aa-4289-b48b-7594a0eb1272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135529633 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.135529633
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3149388608
Short name T269
Test name
Test status
Simulation time 2212167995 ps
CPU time 12.28 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:38:48 PM PDT 24
Peak memory 213268 kb
Host smart-c80383c4-8220-4a95-9f3d-3f2c8d7f5b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149388608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3149388608
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2924866647
Short name T254
Test name
Test status
Simulation time 201170262833 ps
CPU time 441.94 seconds
Started Jul 23 04:38:38 PM PDT 24
Finished Jul 23 04:46:01 PM PDT 24
Peak memory 219480 kb
Host smart-af9dafe5-c693-4ddb-abaa-4944bb5a8b03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924866647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2924866647
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.367378988
Short name T163
Test name
Test status
Simulation time 5304869753 ps
CPU time 49.41 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:34 PM PDT 24
Peak memory 219292 kb
Host smart-0fc86748-41cf-4974-95ee-af14ace92a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367378988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.367378988
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4282851881
Short name T139
Test name
Test status
Simulation time 1707083722 ps
CPU time 17.38 seconds
Started Jul 23 04:38:38 PM PDT 24
Finished Jul 23 04:38:56 PM PDT 24
Peak memory 217584 kb
Host smart-a16e1d9f-a254-438a-a4d2-6884589d0407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282851881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4282851881
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3413669595
Short name T307
Test name
Test status
Simulation time 31456527810 ps
CPU time 128.43 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:40:56 PM PDT 24
Peak memory 219276 kb
Host smart-e542dedc-385b-4173-a84a-dbf91f44a064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413669595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3413669595
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4266379785
Short name T330
Test name
Test status
Simulation time 256606716 ps
CPU time 9.71 seconds
Started Jul 23 04:38:32 PM PDT 24
Finished Jul 23 04:38:42 PM PDT 24
Peak memory 213188 kb
Host smart-3954a1f4-dc4e-49fb-8c34-9b2e27b1f09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266379785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4266379785
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2453402713
Short name T349
Test name
Test status
Simulation time 16909582760 ps
CPU time 287.89 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 234700 kb
Host smart-a337f450-f28c-4e99-86ee-697df25e677e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453402713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2453402713
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.200767742
Short name T66
Test name
Test status
Simulation time 14777965099 ps
CPU time 28.43 seconds
Started Jul 23 04:38:37 PM PDT 24
Finished Jul 23 04:39:06 PM PDT 24
Peak memory 219272 kb
Host smart-6c06ebd2-f399-44cb-9ba4-3f7f9fc7e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200767742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.200767742
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2457700410
Short name T253
Test name
Test status
Simulation time 2057142024 ps
CPU time 22.67 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:39:05 PM PDT 24
Peak memory 219188 kb
Host smart-9e173b8f-d51d-4051-aec2-52bf40593df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457700410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2457700410
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3038295187
Short name T154
Test name
Test status
Simulation time 2052888413 ps
CPU time 32.94 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 215976 kb
Host smart-2248d245-cff6-47cb-b954-413e049ce1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038295187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3038295187
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3108446889
Short name T151
Test name
Test status
Simulation time 897078190 ps
CPU time 50.01 seconds
Started Jul 23 04:38:35 PM PDT 24
Finished Jul 23 04:39:26 PM PDT 24
Peak memory 219744 kb
Host smart-0f96b5ef-188d-4141-9a62-f8361ec7ee69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108446889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3108446889
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3844839932
Short name T285
Test name
Test status
Simulation time 719204228 ps
CPU time 8.37 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:38:55 PM PDT 24
Peak memory 213164 kb
Host smart-42fcf155-12d8-4c21-bdcf-230a7168191e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844839932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3844839932
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2365547404
Short name T41
Test name
Test status
Simulation time 9758842043 ps
CPU time 269.41 seconds
Started Jul 23 04:38:39 PM PDT 24
Finished Jul 23 04:43:09 PM PDT 24
Peak memory 214736 kb
Host smart-cd12129a-85fb-43bd-8a68-b9b1e590946f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365547404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2365547404
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1450507165
Short name T7
Test name
Test status
Simulation time 51427103542 ps
CPU time 63.5 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:39:37 PM PDT 24
Peak memory 219296 kb
Host smart-725e1ade-894f-465d-a50d-e28e55514a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450507165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1450507165
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2428883834
Short name T143
Test name
Test status
Simulation time 1031188400 ps
CPU time 11.72 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:38:59 PM PDT 24
Peak memory 219248 kb
Host smart-8087c074-eb1b-4bde-8193-221c1027225e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428883834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2428883834
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1808238237
Short name T50
Test name
Test status
Simulation time 34100801412 ps
CPU time 78.78 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:40:01 PM PDT 24
Peak memory 216672 kb
Host smart-46153084-6c75-4e52-b98d-0d5bb4152a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808238237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1808238237
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1338547858
Short name T315
Test name
Test status
Simulation time 727651896 ps
CPU time 46.97 seconds
Started Jul 23 04:38:32 PM PDT 24
Finished Jul 23 04:39:19 PM PDT 24
Peak memory 219268 kb
Host smart-bccd995b-ce91-4421-a469-9b4ac2a6f349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338547858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1338547858
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2548836212
Short name T211
Test name
Test status
Simulation time 12785129240 ps
CPU time 27.53 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 217388 kb
Host smart-655755bb-93ab-4f5d-8a14-57ca3e9238c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548836212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2548836212
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2882260791
Short name T319
Test name
Test status
Simulation time 280924754003 ps
CPU time 628.92 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:49:12 PM PDT 24
Peak memory 233460 kb
Host smart-db926877-dc31-4c0f-87e0-eaa6ddb6e445
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882260791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2882260791
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3676873987
Short name T181
Test name
Test status
Simulation time 2355094804 ps
CPU time 35.32 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:39:10 PM PDT 24
Peak memory 219120 kb
Host smart-9177f782-d528-4018-88ce-b98c503a79c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676873987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3676873987
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1597898742
Short name T11
Test name
Test status
Simulation time 16496393551 ps
CPU time 29.76 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:13 PM PDT 24
Peak memory 219296 kb
Host smart-e5d4c8bb-c2b6-43c6-b4a8-966935067167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597898742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1597898742
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.721494410
Short name T156
Test name
Test status
Simulation time 4677361175 ps
CPU time 47.71 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:31 PM PDT 24
Peak memory 216356 kb
Host smart-6c3180ab-8ad7-4f26-99b6-cc6b4ebedeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721494410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.721494410
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.972747209
Short name T172
Test name
Test status
Simulation time 5219614668 ps
CPU time 27.17 seconds
Started Jul 23 04:38:36 PM PDT 24
Finished Jul 23 04:39:04 PM PDT 24
Peak memory 219208 kb
Host smart-a9b309a0-b7af-4938-a36a-f34706dac542
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972747209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.972747209
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.162913876
Short name T57
Test name
Test status
Simulation time 17568628128 ps
CPU time 679.07 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:49:52 PM PDT 24
Peak memory 235768 kb
Host smart-722a5321-8836-4fcd-815e-ddff7e75bf33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162913876 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.162913876
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2987962069
Short name T185
Test name
Test status
Simulation time 4900489240 ps
CPU time 23.65 seconds
Started Jul 23 04:38:38 PM PDT 24
Finished Jul 23 04:39:02 PM PDT 24
Peak memory 213240 kb
Host smart-4a61d4c5-3799-4d42-9972-aa99469037c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987962069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2987962069
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3856986054
Short name T292
Test name
Test status
Simulation time 139082354351 ps
CPU time 379.64 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:45:01 PM PDT 24
Peak memory 225380 kb
Host smart-b9ff8b2d-40fc-4531-9536-2906cd2983b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856986054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3856986054
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1567493826
Short name T47
Test name
Test status
Simulation time 2894660073 ps
CPU time 34.54 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:19 PM PDT 24
Peak memory 219296 kb
Host smart-85264556-4629-47ad-8335-5be86aeaf1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567493826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1567493826
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2410035767
Short name T193
Test name
Test status
Simulation time 2192492969 ps
CPU time 17.25 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:38:59 PM PDT 24
Peak memory 219232 kb
Host smart-3b4ceed8-a610-4744-93ca-284760adfc73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410035767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2410035767
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4040487657
Short name T243
Test name
Test status
Simulation time 874746135 ps
CPU time 26.93 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:12 PM PDT 24
Peak memory 216004 kb
Host smart-633f6812-a1c5-4717-b67c-f488286a5bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040487657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4040487657
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.318941824
Short name T250
Test name
Test status
Simulation time 25696002002 ps
CPU time 42.57 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:27 PM PDT 24
Peak memory 219172 kb
Host smart-5475f773-964d-44cf-abf2-f6a5ad1b4578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318941824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.318941824
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.684839351
Short name T56
Test name
Test status
Simulation time 10385274492 ps
CPU time 45.45 seconds
Started Jul 23 04:38:35 PM PDT 24
Finished Jul 23 04:39:22 PM PDT 24
Peak memory 220432 kb
Host smart-b4ec5759-e670-4b28-bea7-2565a7a1fc79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684839351 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.684839351
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3736143676
Short name T49
Test name
Test status
Simulation time 4905502120 ps
CPU time 23.47 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:38:58 PM PDT 24
Peak memory 213240 kb
Host smart-acf8d446-e575-4107-8d5a-17b640305216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736143676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3736143676
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3730302157
Short name T308
Test name
Test status
Simulation time 7095093541 ps
CPU time 144.79 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:41:11 PM PDT 24
Peak memory 237892 kb
Host smart-73b70114-b982-41a7-9b78-f7689bb5cf03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730302157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3730302157
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.536055222
Short name T339
Test name
Test status
Simulation time 6778958619 ps
CPU time 57.93 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:42 PM PDT 24
Peak memory 219276 kb
Host smart-c1f257ab-3803-4fc9-b378-e656874a25a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536055222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.536055222
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2959013855
Short name T268
Test name
Test status
Simulation time 1365964688 ps
CPU time 18.53 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:38:53 PM PDT 24
Peak memory 219204 kb
Host smart-9ca9f06a-be60-4165-b6fa-9f73fa8bd71b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959013855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2959013855
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3531617475
Short name T64
Test name
Test status
Simulation time 3776223802 ps
CPU time 43.23 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:27 PM PDT 24
Peak memory 216428 kb
Host smart-7e540b74-890c-4a25-a704-3ba30e0879f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531617475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3531617475
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2278415707
Short name T262
Test name
Test status
Simulation time 15249909057 ps
CPU time 123.74 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 219304 kb
Host smart-a17363fe-3f68-4c8f-9220-e087a28ce235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278415707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2278415707
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.558597990
Short name T293
Test name
Test status
Simulation time 167507690 ps
CPU time 8.39 seconds
Started Jul 23 04:38:22 PM PDT 24
Finished Jul 23 04:38:31 PM PDT 24
Peak memory 217064 kb
Host smart-11fe65cc-7d5e-4c2a-baca-63454f18bd4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558597990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.558597990
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.651390344
Short name T38
Test name
Test status
Simulation time 177407139651 ps
CPU time 419.43 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:45:13 PM PDT 24
Peak memory 234644 kb
Host smart-9485ecfb-c4e7-4fd3-bc37-d9b48c455fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651390344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.651390344
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1553090482
Short name T233
Test name
Test status
Simulation time 2496884019 ps
CPU time 25.41 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:38:46 PM PDT 24
Peak memory 218684 kb
Host smart-daa22282-2715-4cd9-850b-ce2b06b55c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553090482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1553090482
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4074213244
Short name T342
Test name
Test status
Simulation time 353678343 ps
CPU time 10.52 seconds
Started Jul 23 04:38:20 PM PDT 24
Finished Jul 23 04:38:31 PM PDT 24
Peak memory 219156 kb
Host smart-5c06ac55-adc5-4706-a167-8d3abfefe1cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074213244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4074213244
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2934808999
Short name T152
Test name
Test status
Simulation time 20728575072 ps
CPU time 61.63 seconds
Started Jul 23 04:38:12 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 218000 kb
Host smart-5dee0464-5b31-460f-945e-7f4da9590fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934808999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2934808999
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1668692540
Short name T277
Test name
Test status
Simulation time 90462169093 ps
CPU time 209.94 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:41:46 PM PDT 24
Peak memory 228580 kb
Host smart-cdf1968b-2c6d-41d5-a1e9-a0b54c3ac6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668692540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1668692540
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1582638768
Short name T198
Test name
Test status
Simulation time 6191469760 ps
CPU time 26.52 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:39:08 PM PDT 24
Peak memory 217356 kb
Host smart-3483bf7c-09fd-4829-91b2-afcfb947fd69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582638768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1582638768
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1982602224
Short name T344
Test name
Test status
Simulation time 2771125814 ps
CPU time 192.55 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:41:46 PM PDT 24
Peak memory 225592 kb
Host smart-9372e8b6-c013-4e0d-bfdf-65a88acc45c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982602224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1982602224
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.39008002
Short name T237
Test name
Test status
Simulation time 332165907 ps
CPU time 19.3 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 219232 kb
Host smart-1cb3d35b-541a-478a-875f-ca9e137cda2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39008002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.39008002
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.302499579
Short name T350
Test name
Test status
Simulation time 355059862 ps
CPU time 10.2 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:38:46 PM PDT 24
Peak memory 219304 kb
Host smart-59fc273c-b2c1-4ffa-b386-45b5dc343fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302499579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.302499579
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4175446584
Short name T362
Test name
Test status
Simulation time 44320926576 ps
CPU time 75.88 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:40:03 PM PDT 24
Peak memory 216240 kb
Host smart-4c8c8a4c-63fb-4feb-a25b-e2f815e5aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175446584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4175446584
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.205491867
Short name T17
Test name
Test status
Simulation time 63468789037 ps
CPU time 1151.35 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:57:47 PM PDT 24
Peak memory 235768 kb
Host smart-ecfe4f0a-be36-4285-a6a7-1571068bd1f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205491867 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.205491867
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3655920946
Short name T167
Test name
Test status
Simulation time 1624019182 ps
CPU time 17.61 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:02 PM PDT 24
Peak memory 217060 kb
Host smart-6b85a922-020e-44b9-b0d0-cc1d8f8325fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655920946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3655920946
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3812233398
Short name T216
Test name
Test status
Simulation time 7680519797 ps
CPU time 143.68 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 235856 kb
Host smart-edf929ad-f08c-4e4d-95fa-8cb204d08923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812233398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3812233398
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1696009751
Short name T337
Test name
Test status
Simulation time 6485687927 ps
CPU time 58.09 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:46 PM PDT 24
Peak memory 219256 kb
Host smart-5ee0947f-fc33-4231-a094-cd74e193a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696009751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1696009751
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3576657107
Short name T280
Test name
Test status
Simulation time 3398431925 ps
CPU time 28.91 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:13 PM PDT 24
Peak memory 217632 kb
Host smart-17a220c5-ee01-427f-ae57-38a758cd63e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576657107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3576657107
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4056002040
Short name T110
Test name
Test status
Simulation time 1806624114 ps
CPU time 24.35 seconds
Started Jul 23 04:38:36 PM PDT 24
Finished Jul 23 04:39:01 PM PDT 24
Peak memory 216700 kb
Host smart-2f5faf55-ac13-4b11-9824-b5547b643e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056002040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4056002040
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1232013392
Short name T305
Test name
Test status
Simulation time 3714037320 ps
CPU time 63.19 seconds
Started Jul 23 04:38:36 PM PDT 24
Finished Jul 23 04:39:40 PM PDT 24
Peak memory 219300 kb
Host smart-92132a66-2200-4d3b-994a-ce861060f17d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232013392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1232013392
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.572586590
Short name T25
Test name
Test status
Simulation time 14784951926 ps
CPU time 31.3 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:15 PM PDT 24
Peak memory 213176 kb
Host smart-0bd67a7d-130a-4716-9f57-b96ceaa7c643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572586590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.572586590
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.95472360
Short name T261
Test name
Test status
Simulation time 67915829466 ps
CPU time 429 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:45:44 PM PDT 24
Peak memory 235144 kb
Host smart-6bf9bd8f-86b3-4fca-b24b-3b2c6d912ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95472360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_co
rrupt_sig_fatal_chk.95472360
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1400693221
Short name T112
Test name
Test status
Simulation time 20417001055 ps
CPU time 52.46 seconds
Started Jul 23 04:38:38 PM PDT 24
Finished Jul 23 04:39:32 PM PDT 24
Peak memory 219200 kb
Host smart-68a5fffb-fe21-44e9-b71d-b7545d97ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400693221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1400693221
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1852982706
Short name T3
Test name
Test status
Simulation time 8434559766 ps
CPU time 32.79 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 219252 kb
Host smart-5b9a7f06-885f-4117-af73-160d49cf6cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852982706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1852982706
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.338410209
Short name T191
Test name
Test status
Simulation time 14689145630 ps
CPU time 62.32 seconds
Started Jul 23 04:38:47 PM PDT 24
Finished Jul 23 04:39:52 PM PDT 24
Peak memory 216964 kb
Host smart-ea16fcc3-27cc-4bed-9088-8d5d7725d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338410209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.338410209
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2962266886
Short name T311
Test name
Test status
Simulation time 7798960178 ps
CPU time 39.6 seconds
Started Jul 23 04:38:33 PM PDT 24
Finished Jul 23 04:39:13 PM PDT 24
Peak memory 219316 kb
Host smart-4c1a6bd8-ddd3-4534-a1c5-beeaf9cc5b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962266886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2962266886
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1819998585
Short name T363
Test name
Test status
Simulation time 345902656 ps
CPU time 8.16 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:38:57 PM PDT 24
Peak memory 216976 kb
Host smart-82b0dbb7-f6a3-4940-b766-b6e65c905716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819998585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1819998585
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2285423569
Short name T39
Test name
Test status
Simulation time 37939766073 ps
CPU time 442.81 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:46:11 PM PDT 24
Peak memory 236844 kb
Host smart-bd62a75f-e16d-4358-bcfb-b068ceaa936b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285423569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2285423569
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.778556837
Short name T63
Test name
Test status
Simulation time 332593788 ps
CPU time 18.96 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 219108 kb
Host smart-2b66f348-dcf8-4922-ad37-8b22b55cdb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778556837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.778556837
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.205257712
Short name T188
Test name
Test status
Simulation time 5258901692 ps
CPU time 18.03 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 211900 kb
Host smart-c84b0bce-07e0-470c-8e19-bb67274ea18f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205257712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.205257712
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4121651516
Short name T144
Test name
Test status
Simulation time 4931112207 ps
CPU time 63.68 seconds
Started Jul 23 04:38:39 PM PDT 24
Finished Jul 23 04:39:44 PM PDT 24
Peak memory 217916 kb
Host smart-9e66502e-f18a-457a-8223-a026da071c65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121651516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4121651516
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.492842609
Short name T326
Test name
Test status
Simulation time 689635744 ps
CPU time 8.08 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:38:54 PM PDT 24
Peak memory 216804 kb
Host smart-75f6ff66-ca50-4dbb-b266-0813faaee014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492842609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.492842609
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.741137720
Short name T246
Test name
Test status
Simulation time 14710118924 ps
CPU time 273.72 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:43:19 PM PDT 24
Peak memory 234868 kb
Host smart-2231e674-2043-4a04-812e-4e055ce13b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741137720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.741137720
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.489925300
Short name T275
Test name
Test status
Simulation time 6889245281 ps
CPU time 29.52 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 219296 kb
Host smart-72b05b35-4fec-49b2-b92c-6937ac630aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489925300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.489925300
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2643110967
Short name T199
Test name
Test status
Simulation time 348422436 ps
CPU time 19.82 seconds
Started Jul 23 04:38:47 PM PDT 24
Finished Jul 23 04:39:09 PM PDT 24
Peak memory 216300 kb
Host smart-f792a224-a9a1-42f3-aaf5-e6ff105ee3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643110967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2643110967
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.755916374
Short name T264
Test name
Test status
Simulation time 16242730485 ps
CPU time 150.32 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:41:17 PM PDT 24
Peak memory 219680 kb
Host smart-4b3cbee8-e6f6-4975-8920-fb83af9c1e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755916374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.755916374
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4172450603
Short name T300
Test name
Test status
Simulation time 4898342894 ps
CPU time 22.62 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 213228 kb
Host smart-8cbedfdb-779a-41c1-8afb-c6c10a05c418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172450603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4172450603
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2497126890
Short name T231
Test name
Test status
Simulation time 318517098670 ps
CPU time 767.63 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:51:30 PM PDT 24
Peak memory 234052 kb
Host smart-7a569599-e9b5-4f8c-a8d7-8e8868d3813c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497126890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2497126890
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1894731273
Short name T327
Test name
Test status
Simulation time 7204233159 ps
CPU time 60.51 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:49 PM PDT 24
Peak memory 219268 kb
Host smart-f18faf65-c4c9-4289-b00c-98313a5c834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894731273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1894731273
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1826737641
Short name T340
Test name
Test status
Simulation time 2951015588 ps
CPU time 19.73 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 211360 kb
Host smart-3aae169e-3447-46c4-b9b1-60dcef48c363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826737641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1826737641
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.628255817
Short name T329
Test name
Test status
Simulation time 23966564949 ps
CPU time 63.82 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:51 PM PDT 24
Peak memory 215760 kb
Host smart-cdb26f06-c6c1-4d0b-846d-aa2b9d64c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628255817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.628255817
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.43147180
Short name T336
Test name
Test status
Simulation time 722543104 ps
CPU time 26.67 seconds
Started Jul 23 04:38:42 PM PDT 24
Finished Jul 23 04:39:11 PM PDT 24
Peak memory 219120 kb
Host smart-8c61d235-ef29-4c25-805f-fd8d334589e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43147180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.rom_ctrl_stress_all.43147180
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.936745324
Short name T306
Test name
Test status
Simulation time 41776359541 ps
CPU time 33.15 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 217396 kb
Host smart-78816dfc-80e0-48ca-b7cd-2130b9bbaa94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936745324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.936745324
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1467495469
Short name T224
Test name
Test status
Simulation time 20795768668 ps
CPU time 180.13 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 219452 kb
Host smart-66b085f5-0234-450a-8208-0fb3bba35ef1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467495469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1467495469
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3883130622
Short name T203
Test name
Test status
Simulation time 71992602227 ps
CPU time 62.2 seconds
Started Jul 23 04:38:40 PM PDT 24
Finished Jul 23 04:39:44 PM PDT 24
Peak memory 219292 kb
Host smart-00fe3a5d-b016-43c3-9f1b-00cd4e20a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883130622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3883130622
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1748477050
Short name T222
Test name
Test status
Simulation time 2361752940 ps
CPU time 16.3 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:38:59 PM PDT 24
Peak memory 218468 kb
Host smart-b59b6742-e60b-44aa-9934-0c148de6f3af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748477050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1748477050
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3658223871
Short name T359
Test name
Test status
Simulation time 2694394056 ps
CPU time 35.15 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:21 PM PDT 24
Peak memory 215740 kb
Host smart-c522e186-3f4b-42b9-9479-b163ba516b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658223871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3658223871
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1451933008
Short name T291
Test name
Test status
Simulation time 6373338403 ps
CPU time 54.68 seconds
Started Jul 23 04:38:41 PM PDT 24
Finished Jul 23 04:39:37 PM PDT 24
Peak memory 219300 kb
Host smart-50e78473-3946-4477-869a-2c5751f97aa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451933008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1451933008
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3616967393
Short name T210
Test name
Test status
Simulation time 6831479267 ps
CPU time 28.56 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 217380 kb
Host smart-fc757a52-2a6c-4c82-8b0d-02f2ad5e0e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616967393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3616967393
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1702765973
Short name T5
Test name
Test status
Simulation time 14379757845 ps
CPU time 280.6 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:43:28 PM PDT 24
Peak memory 238444 kb
Host smart-9f9a76c0-2a54-49be-b65b-d121c9a914d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702765973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1702765973
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2819458986
Short name T310
Test name
Test status
Simulation time 1333198576 ps
CPU time 28.22 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 218252 kb
Host smart-47b2d90d-62ad-47c5-b212-149ce244491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819458986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2819458986
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2533630579
Short name T290
Test name
Test status
Simulation time 2585608042 ps
CPU time 18.27 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:11 PM PDT 24
Peak memory 217636 kb
Host smart-5b2e1b57-3067-49fe-beea-7233a7661396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533630579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2533630579
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2180020745
Short name T304
Test name
Test status
Simulation time 8331355546 ps
CPU time 82.65 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:40:10 PM PDT 24
Peak memory 216412 kb
Host smart-82d8b8ae-3e1e-492b-b3eb-606bd86d5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180020745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2180020745
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1572956871
Short name T171
Test name
Test status
Simulation time 4048248909 ps
CPU time 23.8 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:09 PM PDT 24
Peak memory 219032 kb
Host smart-82d5f36d-c9ac-4190-b47e-15f162f4c860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572956871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1572956871
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1549223033
Short name T157
Test name
Test status
Simulation time 8680360000 ps
CPU time 31.59 seconds
Started Jul 23 04:38:43 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 217404 kb
Host smart-87f041f6-d90b-4ab1-abf1-031ecd843f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549223033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1549223033
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.183587598
Short name T324
Test name
Test status
Simulation time 6746937731 ps
CPU time 278.11 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:43:29 PM PDT 24
Peak memory 242200 kb
Host smart-f2a5d049-64d6-4008-9866-fbfae1f45ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183587598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.183587598
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1570755503
Short name T202
Test name
Test status
Simulation time 5003131578 ps
CPU time 36 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:27 PM PDT 24
Peak memory 219216 kb
Host smart-80cbe444-4612-41ef-bb9a-7e479d292f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570755503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1570755503
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2212651638
Short name T317
Test name
Test status
Simulation time 9691102460 ps
CPU time 22.71 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:19 PM PDT 24
Peak memory 211852 kb
Host smart-3b454f1e-cfa5-4247-bd1b-ffa85ae89242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212651638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2212651638
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4072964411
Short name T146
Test name
Test status
Simulation time 15403461701 ps
CPU time 70.99 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:57 PM PDT 24
Peak memory 216668 kb
Host smart-324fbfc5-e3c4-4913-99c6-821735805f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072964411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4072964411
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.242097602
Short name T331
Test name
Test status
Simulation time 14382768605 ps
CPU time 105.9 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:40:40 PM PDT 24
Peak memory 219244 kb
Host smart-4aafd944-7b82-4c56-bbab-94e3c79ff202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242097602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.242097602
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.713319852
Short name T74
Test name
Test status
Simulation time 4777813880 ps
CPU time 15.59 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:10 PM PDT 24
Peak memory 217332 kb
Host smart-09be30de-5807-4bd1-9e9c-0d283ead07ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713319852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.713319852
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.446952461
Short name T225
Test name
Test status
Simulation time 1361851614 ps
CPU time 28 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 218676 kb
Host smart-871657e1-c5a2-4352-b27c-b6acbd6d1bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446952461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.446952461
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3416639340
Short name T355
Test name
Test status
Simulation time 1315995276 ps
CPU time 10.01 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:01 PM PDT 24
Peak memory 219216 kb
Host smart-0c9b20f4-e26a-4119-869b-700ae953ce70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416639340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3416639340
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3489014148
Short name T258
Test name
Test status
Simulation time 650410783 ps
CPU time 19.03 seconds
Started Jul 23 04:38:47 PM PDT 24
Finished Jul 23 04:39:09 PM PDT 24
Peak memory 216564 kb
Host smart-d471a1ee-ccd3-4820-9102-c2c4b19d87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489014148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3489014148
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.598495041
Short name T187
Test name
Test status
Simulation time 2134781302 ps
CPU time 26.04 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 219112 kb
Host smart-b92a0b6c-f852-411f-a8d8-38f9ce9f09f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598495041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.598495041
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3581621029
Short name T58
Test name
Test status
Simulation time 38929301961 ps
CPU time 2329.82 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 05:17:36 PM PDT 24
Peak memory 233920 kb
Host smart-ff4cad63-5401-4358-a864-eedba67ec7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581621029 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3581621029
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3293075226
Short name T354
Test name
Test status
Simulation time 167308751 ps
CPU time 8.42 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:38:23 PM PDT 24
Peak memory 217096 kb
Host smart-cdf5e48f-49f9-4843-a9bd-fb28434e0d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293075226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3293075226
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2717681812
Short name T321
Test name
Test status
Simulation time 25690810330 ps
CPU time 272.84 seconds
Started Jul 23 04:38:19 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 219448 kb
Host smart-65c162b2-a0ab-4887-b0f2-a36e5d0d2181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717681812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2717681812
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.786604901
Short name T284
Test name
Test status
Simulation time 1270882410 ps
CPU time 19.27 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:38:34 PM PDT 24
Peak memory 219144 kb
Host smart-d8d9c5a1-fbab-4d2b-abf1-863fd35992b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786604901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.786604901
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1182452406
Short name T34
Test name
Test status
Simulation time 44143339777 ps
CPU time 30.18 seconds
Started Jul 23 04:38:27 PM PDT 24
Finished Jul 23 04:38:58 PM PDT 24
Peak memory 219296 kb
Host smart-1d4bd2ee-f187-4b79-a9c3-8a2c934a4f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182452406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1182452406
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.492900364
Short name T28
Test name
Test status
Simulation time 702476310 ps
CPU time 223.85 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:41:59 PM PDT 24
Peak memory 235936 kb
Host smart-9d4cf3c0-6ce8-4f7a-a167-273cf57b3ce8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492900364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.492900364
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3087304435
Short name T360
Test name
Test status
Simulation time 1828463856 ps
CPU time 23.38 seconds
Started Jul 23 04:38:15 PM PDT 24
Finished Jul 23 04:38:40 PM PDT 24
Peak memory 216708 kb
Host smart-f58c578f-9280-4291-b953-b9d832fad4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087304435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3087304435
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1339602513
Short name T266
Test name
Test status
Simulation time 29144169331 ps
CPU time 72.58 seconds
Started Jul 23 04:38:15 PM PDT 24
Finished Jul 23 04:39:30 PM PDT 24
Peak memory 219248 kb
Host smart-fd0b4208-a7d5-424a-a38d-2ce0b2a315de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339602513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1339602513
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1775127846
Short name T206
Test name
Test status
Simulation time 2856114866 ps
CPU time 26.39 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 217148 kb
Host smart-0ff34fb2-79ea-47d6-ad35-21d31f905f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775127846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1775127846
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1650931228
Short name T361
Test name
Test status
Simulation time 62013402678 ps
CPU time 599.77 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:48:48 PM PDT 24
Peak memory 219764 kb
Host smart-8e01012c-3cef-4d1b-9128-8017998333e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650931228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1650931228
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1427506174
Short name T176
Test name
Test status
Simulation time 7680015990 ps
CPU time 28.61 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 215580 kb
Host smart-2742a710-fd97-4561-bd39-d7842039cf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427506174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1427506174
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1790343554
Short name T282
Test name
Test status
Simulation time 2166480325 ps
CPU time 22.39 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 219268 kb
Host smart-a8644085-7c63-4ebe-93a6-a9185f2616d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790343554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1790343554
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1109395768
Short name T352
Test name
Test status
Simulation time 8595755882 ps
CPU time 35.36 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:39:24 PM PDT 24
Peak memory 217252 kb
Host smart-4239b4c7-756d-402f-84be-3ee67ab21087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109395768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1109395768
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1737679846
Short name T6
Test name
Test status
Simulation time 77039875511 ps
CPU time 116.49 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:40:51 PM PDT 24
Peak memory 219276 kb
Host smart-1f32bc54-677a-4c8a-afdb-3f3edd7921ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737679846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1737679846
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.818157116
Short name T248
Test name
Test status
Simulation time 185703467 ps
CPU time 8.21 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:01 PM PDT 24
Peak memory 217200 kb
Host smart-066eaf05-7a27-41d6-ae8a-b47796058a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818157116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.818157116
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3523356702
Short name T169
Test name
Test status
Simulation time 5563866795 ps
CPU time 187.33 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 239668 kb
Host smart-bcb15093-2a20-46aa-8564-ff82b024450e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523356702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3523356702
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3996150834
Short name T257
Test name
Test status
Simulation time 45644884344 ps
CPU time 58.45 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:51 PM PDT 24
Peak memory 219208 kb
Host smart-bea3b96f-ae48-4ebc-bb8c-d0608b2d5e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996150834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3996150834
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.662661939
Short name T141
Test name
Test status
Simulation time 179301645 ps
CPU time 10.42 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 219208 kb
Host smart-a0fd9c08-79a8-41be-914b-9d2748a3f90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662661939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.662661939
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3145815572
Short name T142
Test name
Test status
Simulation time 5937375441 ps
CPU time 51.81 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:45 PM PDT 24
Peak memory 216980 kb
Host smart-9f474598-c1da-4e96-910e-f3b2cbff773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145815572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3145815572
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3244079782
Short name T226
Test name
Test status
Simulation time 2798916571 ps
CPU time 51.8 seconds
Started Jul 23 04:38:59 PM PDT 24
Finished Jul 23 04:39:52 PM PDT 24
Peak memory 219288 kb
Host smart-215e92a4-1b8b-499b-8682-9473e2a85489
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244079782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3244079782
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.519859206
Short name T195
Test name
Test status
Simulation time 4430733024 ps
CPU time 15.54 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:39:04 PM PDT 24
Peak memory 213288 kb
Host smart-4f3b2c7d-8506-4292-a6c0-8ca8561aa8e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519859206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.519859206
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1145591965
Short name T136
Test name
Test status
Simulation time 152288081768 ps
CPU time 421.79 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:45:58 PM PDT 24
Peak memory 234228 kb
Host smart-c35d3055-37a7-4af4-b950-efaca01cbefc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145591965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1145591965
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3210244947
Short name T108
Test name
Test status
Simulation time 6484152417 ps
CPU time 55.64 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:42 PM PDT 24
Peak memory 219272 kb
Host smart-2fb124a0-29ab-4820-b969-ad53eb06aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210244947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3210244947
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.50338728
Short name T177
Test name
Test status
Simulation time 11387799613 ps
CPU time 26.2 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:13 PM PDT 24
Peak memory 211968 kb
Host smart-f0c43300-afa9-4c1d-978b-b1c9f91051c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50338728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.50338728
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2500085311
Short name T217
Test name
Test status
Simulation time 11446663095 ps
CPU time 47.88 seconds
Started Jul 23 04:38:48 PM PDT 24
Finished Jul 23 04:39:38 PM PDT 24
Peak memory 217004 kb
Host smart-5a0326ec-7282-44a5-8cb6-1ad8c6e5fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500085311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2500085311
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.399938830
Short name T104
Test name
Test status
Simulation time 5257046974 ps
CPU time 61.62 seconds
Started Jul 23 04:38:48 PM PDT 24
Finished Jul 23 04:39:52 PM PDT 24
Peak memory 217608 kb
Host smart-69fc1a27-4a0a-46b6-8e2e-0a4abe27f019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399938830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.399938830
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1148221584
Short name T201
Test name
Test status
Simulation time 11330605316 ps
CPU time 23.98 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 213260 kb
Host smart-db18eb8f-c54b-40d7-a8a9-49abc10f5331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148221584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1148221584
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2589086785
Short name T255
Test name
Test status
Simulation time 399843349959 ps
CPU time 629.56 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:49:23 PM PDT 24
Peak memory 219224 kb
Host smart-c6bee261-06a4-4ece-88ae-07ac3d34a0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589086785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2589086785
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2225492670
Short name T153
Test name
Test status
Simulation time 24617865993 ps
CPU time 50.5 seconds
Started Jul 23 04:38:54 PM PDT 24
Finished Jul 23 04:39:46 PM PDT 24
Peak memory 219260 kb
Host smart-201f5e0c-64bf-423d-b884-a09d35f385f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225492670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2225492670
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1855240130
Short name T236
Test name
Test status
Simulation time 7214957490 ps
CPU time 20.79 seconds
Started Jul 23 04:38:53 PM PDT 24
Finished Jul 23 04:39:15 PM PDT 24
Peak memory 217832 kb
Host smart-835afb9e-223f-491a-afa7-a710e753e132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855240130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1855240130
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4033338238
Short name T218
Test name
Test status
Simulation time 11173619719 ps
CPU time 25.2 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 216992 kb
Host smart-a82d5bbc-b6b2-484d-a7b1-9c3db5ff0d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033338238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4033338238
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4191954213
Short name T160
Test name
Test status
Simulation time 1636375336 ps
CPU time 62.43 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:53 PM PDT 24
Peak memory 219500 kb
Host smart-f98c62c7-6b79-41ad-977e-b2edd588075c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191954213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4191954213
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1151952218
Short name T347
Test name
Test status
Simulation time 689267383 ps
CPU time 8.32 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:38:59 PM PDT 24
Peak memory 213200 kb
Host smart-c1d0c2c0-95bb-4bbe-9384-4783b13e11d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151952218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1151952218
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.656832698
Short name T298
Test name
Test status
Simulation time 98485722708 ps
CPU time 219.99 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:42:33 PM PDT 24
Peak memory 215856 kb
Host smart-12d1ada3-f03c-4783-b584-fc904f1147c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656832698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.656832698
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.55421460
Short name T204
Test name
Test status
Simulation time 1319269977 ps
CPU time 18.11 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:39:10 PM PDT 24
Peak memory 218900 kb
Host smart-65f395ee-29b1-482f-9578-ba934155ea43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55421460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.55421460
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4033989880
Short name T194
Test name
Test status
Simulation time 12288854043 ps
CPU time 25.86 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:19 PM PDT 24
Peak memory 219236 kb
Host smart-e129584b-b12f-4941-a2cd-18dcf9a86ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033989880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4033989880
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1803343547
Short name T150
Test name
Test status
Simulation time 8057432221 ps
CPU time 64.36 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:39:53 PM PDT 24
Peak memory 216908 kb
Host smart-6d0b3203-a96c-4a34-9fff-a75d095b0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803343547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1803343547
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.184608670
Short name T212
Test name
Test status
Simulation time 181549169190 ps
CPU time 192.52 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 220580 kb
Host smart-0e4ee093-8d02-4e3d-a5a1-3c2d1d020221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184608670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.184608670
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3859540102
Short name T228
Test name
Test status
Simulation time 19445180123 ps
CPU time 26.53 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:23 PM PDT 24
Peak memory 213244 kb
Host smart-2c8a1d5c-8d9b-41b6-84ad-233df01aea1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859540102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3859540102
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.600442353
Short name T276
Test name
Test status
Simulation time 110153084184 ps
CPU time 431.1 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:46:04 PM PDT 24
Peak memory 228416 kb
Host smart-688766cd-762d-4cc0-85bb-ff3d12b09a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600442353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.600442353
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1905641758
Short name T325
Test name
Test status
Simulation time 32752262025 ps
CPU time 61.48 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:55 PM PDT 24
Peak memory 219296 kb
Host smart-ca418f4a-7edf-45a4-9c65-7777c5e14cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905641758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1905641758
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4084068023
Short name T192
Test name
Test status
Simulation time 385567562 ps
CPU time 10.18 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:39:02 PM PDT 24
Peak memory 219256 kb
Host smart-5943bc3f-3cfc-498f-96fe-69d488265145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084068023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4084068023
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1155523339
Short name T32
Test name
Test status
Simulation time 32872489196 ps
CPU time 72.86 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:40:06 PM PDT 24
Peak memory 215904 kb
Host smart-9bbc4d63-deb4-4b9c-ba37-3e5accf8f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155523339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1155523339
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3701848100
Short name T148
Test name
Test status
Simulation time 53131957722 ps
CPU time 124.86 seconds
Started Jul 23 04:38:50 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 219324 kb
Host smart-54707f63-da9f-4018-94ae-7e2e8f641277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701848100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3701848100
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1013515549
Short name T147
Test name
Test status
Simulation time 1472030352 ps
CPU time 17.64 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 213064 kb
Host smart-f0b61db6-85ce-467a-bf5f-a8b107ca600f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013515549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1013515549
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3950424043
Short name T238
Test name
Test status
Simulation time 9842150698 ps
CPU time 133.85 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:41:11 PM PDT 24
Peak memory 228368 kb
Host smart-b40e33b8-11fb-4f4e-b01c-ae289c06df79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950424043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3950424043
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2995216389
Short name T302
Test name
Test status
Simulation time 5466909685 ps
CPU time 27.93 seconds
Started Jul 23 04:38:57 PM PDT 24
Finished Jul 23 04:39:26 PM PDT 24
Peak memory 219296 kb
Host smart-7c188c1f-74d9-411e-a316-d09258fae7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995216389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2995216389
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1208003707
Short name T270
Test name
Test status
Simulation time 2998468485 ps
CPU time 14.36 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 219156 kb
Host smart-4ed7354c-e7ef-49ee-912c-e7e03decd73d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208003707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1208003707
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3155908699
Short name T89
Test name
Test status
Simulation time 34962592716 ps
CPU time 76.63 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:40:14 PM PDT 24
Peak memory 216696 kb
Host smart-0d005681-9edf-48ac-90fd-9ffed70cb863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155908699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3155908699
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3274440547
Short name T209
Test name
Test status
Simulation time 59720525360 ps
CPU time 78.14 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 219160 kb
Host smart-fdbf1248-65fb-48e0-aa97-97cd7bcbbbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274440547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3274440547
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1234884169
Short name T77
Test name
Test status
Simulation time 10158566487 ps
CPU time 23.72 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:21 PM PDT 24
Peak memory 213228 kb
Host smart-edaf4280-4d59-4efb-a4ea-37b78063239b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234884169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1234884169
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3546142913
Short name T53
Test name
Test status
Simulation time 5457860363 ps
CPU time 178.37 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 219340 kb
Host smart-c6692dbf-88f7-4115-908f-e0ec45b5e017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546142913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3546142913
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1788507616
Short name T168
Test name
Test status
Simulation time 19281203256 ps
CPU time 51.7 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:49 PM PDT 24
Peak memory 219160 kb
Host smart-e901f1d7-d832-40fd-91bf-ccdf47bee191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788507616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1788507616
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2238998981
Short name T118
Test name
Test status
Simulation time 3498369873 ps
CPU time 28.69 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:26 PM PDT 24
Peak memory 211256 kb
Host smart-3c3b90d4-1296-47f7-b4c2-20396849a553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238998981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2238998981
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1861694935
Short name T162
Test name
Test status
Simulation time 1531707097 ps
CPU time 19.71 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:39:16 PM PDT 24
Peak memory 216592 kb
Host smart-75f3822c-2051-4b6a-b085-207fa8c5cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861694935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1861694935
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1460274182
Short name T30
Test name
Test status
Simulation time 14048497792 ps
CPU time 64.46 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:40:02 PM PDT 24
Peak memory 217524 kb
Host smart-9ff12031-b210-4a8c-aa66-6bc44fd0d1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460274182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1460274182
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1795426372
Short name T183
Test name
Test status
Simulation time 3863493437 ps
CPU time 31.47 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:31 PM PDT 24
Peak memory 217144 kb
Host smart-e50d06cf-a97e-465b-ab70-95786e3bdc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795426372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1795426372
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2894498775
Short name T281
Test name
Test status
Simulation time 158018405138 ps
CPU time 354.07 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:44:51 PM PDT 24
Peak memory 219424 kb
Host smart-2b0d53cf-40f9-45df-a698-4c3c04b489a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894498775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2894498775
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4251414387
Short name T4
Test name
Test status
Simulation time 3664981564 ps
CPU time 23.64 seconds
Started Jul 23 04:38:57 PM PDT 24
Finished Jul 23 04:39:22 PM PDT 24
Peak memory 218688 kb
Host smart-52caf198-b0e1-4363-9724-b22ae748d6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251414387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4251414387
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.431473205
Short name T105
Test name
Test status
Simulation time 266665263 ps
CPU time 11.41 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:38:58 PM PDT 24
Peak memory 219252 kb
Host smart-cd867651-f138-450b-a87c-4919196c905f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431473205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.431473205
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2833236641
Short name T48
Test name
Test status
Simulation time 690851232 ps
CPU time 20.89 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 216568 kb
Host smart-ab117553-ed10-4fa9-8cf6-604595a4b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833236641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2833236641
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1975877894
Short name T341
Test name
Test status
Simulation time 1705784066 ps
CPU time 66.95 seconds
Started Jul 23 04:38:55 PM PDT 24
Finished Jul 23 04:40:03 PM PDT 24
Peak memory 219656 kb
Host smart-a5a74514-ed0e-442c-a5d2-de0e9907844c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975877894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1975877894
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3624666975
Short name T207
Test name
Test status
Simulation time 1562652109 ps
CPU time 18.47 seconds
Started Jul 23 04:38:57 PM PDT 24
Finished Jul 23 04:39:17 PM PDT 24
Peak memory 213192 kb
Host smart-8d07db22-6422-44cb-b89f-32981f2e1333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624666975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3624666975
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4121409014
Short name T356
Test name
Test status
Simulation time 139614085052 ps
CPU time 629.69 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:49:29 PM PDT 24
Peak memory 228952 kb
Host smart-12660704-a589-4469-835d-bf3475edeace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121409014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4121409014
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3906162624
Short name T170
Test name
Test status
Simulation time 7735653146 ps
CPU time 64.15 seconds
Started Jul 23 04:38:44 PM PDT 24
Finished Jul 23 04:39:51 PM PDT 24
Peak memory 219328 kb
Host smart-3a6c34a7-0d4e-4034-930c-1c00ad046b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906162624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3906162624
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.668098730
Short name T138
Test name
Test status
Simulation time 183867673 ps
CPU time 10.34 seconds
Started Jul 23 04:38:51 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 219204 kb
Host smart-76b569b3-b97d-4bf9-9be3-034093938444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668098730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.668098730
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.153510605
Short name T179
Test name
Test status
Simulation time 54721335075 ps
CPU time 40.92 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:39 PM PDT 24
Peak memory 216492 kb
Host smart-169b6825-5515-41e9-9ec3-3ce88b3025ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153510605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.153510605
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2808366833
Short name T165
Test name
Test status
Simulation time 209765267 ps
CPU time 11.37 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:39:02 PM PDT 24
Peak memory 218568 kb
Host smart-e04d6122-6cbb-4ca7-86ab-32a6389c90e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808366833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2808366833
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2643788252
Short name T73
Test name
Test status
Simulation time 3763457119 ps
CPU time 30.19 seconds
Started Jul 23 04:38:17 PM PDT 24
Finished Jul 23 04:38:49 PM PDT 24
Peak memory 217108 kb
Host smart-0594339d-e093-42dd-be86-88bd42424273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643788252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2643788252
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.92365754
Short name T43
Test name
Test status
Simulation time 17279327269 ps
CPU time 236.35 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:42:10 PM PDT 24
Peak memory 240120 kb
Host smart-e7c916f0-6b3b-4e3b-ac8c-568a4e2a8d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92365754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.92365754
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3316843639
Short name T303
Test name
Test status
Simulation time 373440706 ps
CPU time 19.31 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:38:34 PM PDT 24
Peak memory 218912 kb
Host smart-8ce668cf-d4a6-429d-b4d6-44ff45c01f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316843639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3316843639
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1625533182
Short name T278
Test name
Test status
Simulation time 185602863 ps
CPU time 10.36 seconds
Started Jul 23 04:38:32 PM PDT 24
Finished Jul 23 04:38:43 PM PDT 24
Peak memory 219208 kb
Host smart-15cfc276-2602-40c6-b83d-23f747030762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625533182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1625533182
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1526703813
Short name T22
Test name
Test status
Simulation time 2156789087 ps
CPU time 115.82 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:40:12 PM PDT 24
Peak memory 237000 kb
Host smart-5c2a09a4-117d-490c-aef2-c924b5d12c59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526703813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1526703813
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2067491742
Short name T283
Test name
Test status
Simulation time 8892736595 ps
CPU time 47.22 seconds
Started Jul 23 04:38:12 PM PDT 24
Finished Jul 23 04:39:00 PM PDT 24
Peak memory 216032 kb
Host smart-3e29da5f-e38a-48a8-aaeb-33e84408cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067491742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2067491742
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.973514812
Short name T164
Test name
Test status
Simulation time 7328681560 ps
CPU time 85.67 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:39:41 PM PDT 24
Peak memory 219516 kb
Host smart-f9693ee7-76de-46b5-9cfb-29db470451a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973514812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.973514812
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4131285448
Short name T190
Test name
Test status
Simulation time 718024186 ps
CPU time 8.35 seconds
Started Jul 23 04:38:53 PM PDT 24
Finished Jul 23 04:39:03 PM PDT 24
Peak memory 217024 kb
Host smart-bcfb947a-259b-443e-b953-314555d94590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131285448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4131285448
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4291714098
Short name T219
Test name
Test status
Simulation time 185025389773 ps
CPU time 493.04 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:47:12 PM PDT 24
Peak memory 236004 kb
Host smart-edf19774-85f6-465e-9fac-421eea4e638b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291714098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4291714098
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1976731198
Short name T51
Test name
Test status
Simulation time 2533752718 ps
CPU time 19.55 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:39:08 PM PDT 24
Peak memory 219400 kb
Host smart-dc59365f-533c-4238-89b3-dbc13f7dd0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976731198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1976731198
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1628318285
Short name T240
Test name
Test status
Simulation time 181694144 ps
CPU time 10.15 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:08 PM PDT 24
Peak memory 219208 kb
Host smart-26f9f716-2ae4-449d-a8bd-e8f5813ab7a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628318285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1628318285
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3244479129
Short name T239
Test name
Test status
Simulation time 1357243783 ps
CPU time 20.45 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:18 PM PDT 24
Peak memory 216196 kb
Host smart-bee2de4d-9a0f-4db3-9750-aceed04dbdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244479129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3244479129
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2403656373
Short name T8
Test name
Test status
Simulation time 52149067141 ps
CPU time 75.11 seconds
Started Jul 23 04:38:47 PM PDT 24
Finished Jul 23 04:40:05 PM PDT 24
Peak memory 217116 kb
Host smart-3dcfcf8b-82ee-4847-8ed2-36505e4ecb96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403656373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2403656373
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2471800145
Short name T31
Test name
Test status
Simulation time 688400727 ps
CPU time 8.04 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:08 PM PDT 24
Peak memory 213152 kb
Host smart-4051f94f-ca1a-4ec4-a8a7-f67b56b4fcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471800145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2471800145
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1679310427
Short name T109
Test name
Test status
Simulation time 312042292382 ps
CPU time 776.71 seconds
Started Jul 23 04:38:49 PM PDT 24
Finished Jul 23 04:51:48 PM PDT 24
Peak memory 236444 kb
Host smart-d69bb4f3-451e-4ffb-ac6f-56077276b3f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679310427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1679310427
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2798741197
Short name T244
Test name
Test status
Simulation time 6761640843 ps
CPU time 53.53 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:48 PM PDT 24
Peak memory 219292 kb
Host smart-87732f86-ed0d-4526-afb1-67654826f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798741197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2798741197
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.812991012
Short name T173
Test name
Test status
Simulation time 12026567845 ps
CPU time 26.09 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 217832 kb
Host smart-406371e4-462c-44ca-aaa2-eeb70227ac07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812991012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.812991012
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.844426988
Short name T175
Test name
Test status
Simulation time 350975287 ps
CPU time 19.71 seconds
Started Jul 23 04:38:56 PM PDT 24
Finished Jul 23 04:39:18 PM PDT 24
Peak memory 218860 kb
Host smart-8524998c-3596-419c-a48f-571a7526cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844426988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.844426988
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.558882023
Short name T358
Test name
Test status
Simulation time 65492968494 ps
CPU time 174.37 seconds
Started Jul 23 04:38:46 PM PDT 24
Finished Jul 23 04:41:43 PM PDT 24
Peak memory 219592 kb
Host smart-ad5c4764-091a-4764-b30a-3d5e401320cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558882023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.558882023
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3302432383
Short name T2
Test name
Test status
Simulation time 4652770672 ps
CPU time 23.03 seconds
Started Jul 23 04:38:48 PM PDT 24
Finished Jul 23 04:39:13 PM PDT 24
Peak memory 213240 kb
Host smart-98e3ebb0-34ab-49f4-8a51-43b4b6fe4682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302432383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3302432383
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3099476860
Short name T260
Test name
Test status
Simulation time 65377052677 ps
CPU time 531.72 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:47:46 PM PDT 24
Peak memory 219424 kb
Host smart-3ce2913f-671c-4108-9ddf-4b38469bc068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099476860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3099476860
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4098833629
Short name T256
Test name
Test status
Simulation time 2905474124 ps
CPU time 26.5 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:20 PM PDT 24
Peak memory 219264 kb
Host smart-cf826d95-3115-40b6-bec7-bf6e3b229b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098833629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4098833629
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3407631202
Short name T184
Test name
Test status
Simulation time 1008779474 ps
CPU time 20.58 seconds
Started Jul 23 04:38:52 PM PDT 24
Finished Jul 23 04:39:15 PM PDT 24
Peak memory 216860 kb
Host smart-12432243-9bd7-428b-9518-8662c7df2943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407631202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3407631202
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3901768051
Short name T338
Test name
Test status
Simulation time 49728811739 ps
CPU time 43.3 seconds
Started Jul 23 04:38:54 PM PDT 24
Finished Jul 23 04:39:38 PM PDT 24
Peak memory 217628 kb
Host smart-fd7c3e7b-5474-4aae-abf5-5e59ef6d9778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901768051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3901768051
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1234217612
Short name T252
Test name
Test status
Simulation time 595207078 ps
CPU time 12.09 seconds
Started Jul 23 04:38:54 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 216872 kb
Host smart-f6a01a12-4270-40dc-9f92-d706d81c07dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234217612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1234217612
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3324983018
Short name T159
Test name
Test status
Simulation time 94261632279 ps
CPU time 306 seconds
Started Jul 23 04:38:54 PM PDT 24
Finished Jul 23 04:44:02 PM PDT 24
Peak memory 240864 kb
Host smart-682a2623-19d7-4af7-be3f-f88c874a3c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324983018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3324983018
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1009722464
Short name T351
Test name
Test status
Simulation time 332782778 ps
CPU time 19.19 seconds
Started Jul 23 04:38:45 PM PDT 24
Finished Jul 23 04:39:06 PM PDT 24
Peak memory 219504 kb
Host smart-84f7887a-96e4-4378-95ca-0d363a11fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009722464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1009722464
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3713620869
Short name T44
Test name
Test status
Simulation time 20981654316 ps
CPU time 33.21 seconds
Started Jul 23 04:38:53 PM PDT 24
Finished Jul 23 04:39:28 PM PDT 24
Peak memory 211908 kb
Host smart-9f41feaf-e436-4b98-8b89-640f1549085c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713620869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3713620869
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.820620841
Short name T182
Test name
Test status
Simulation time 6816290013 ps
CPU time 72.07 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:40:12 PM PDT 24
Peak memory 217572 kb
Host smart-421ed813-182e-4c61-962b-3e9e93a1bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820620841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.820620841
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3492124178
Short name T294
Test name
Test status
Simulation time 19698415970 ps
CPU time 40.21 seconds
Started Jul 23 04:38:53 PM PDT 24
Finished Jul 23 04:39:35 PM PDT 24
Peak memory 219184 kb
Host smart-373ec702-4145-4176-80de-f6c504f8209c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492124178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3492124178
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3979240320
Short name T9
Test name
Test status
Simulation time 5744118768 ps
CPU time 17.19 seconds
Started Jul 23 04:39:05 PM PDT 24
Finished Jul 23 04:39:24 PM PDT 24
Peak memory 213252 kb
Host smart-4f22c280-b47e-4a8e-963f-2cb31bcd4d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979240320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3979240320
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3901837425
Short name T320
Test name
Test status
Simulation time 103947924818 ps
CPU time 305.66 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:44:10 PM PDT 24
Peak memory 239848 kb
Host smart-ff49610a-2ba0-44d9-a9ca-8e2186200afb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901837425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3901837425
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1549723541
Short name T297
Test name
Test status
Simulation time 346452107 ps
CPU time 18.85 seconds
Started Jul 23 04:38:57 PM PDT 24
Finished Jul 23 04:39:18 PM PDT 24
Peak memory 219272 kb
Host smart-3472ec25-4d9a-4851-b96b-03cd8640690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549723541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1549723541
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2294755463
Short name T223
Test name
Test status
Simulation time 190774708 ps
CPU time 10.19 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:39:15 PM PDT 24
Peak memory 219072 kb
Host smart-144cf647-ab75-4ea2-b1e8-84a275be2b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294755463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2294755463
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4231406706
Short name T289
Test name
Test status
Simulation time 12720702158 ps
CPU time 38.95 seconds
Started Jul 23 04:39:03 PM PDT 24
Finished Jul 23 04:39:44 PM PDT 24
Peak memory 217148 kb
Host smart-cd184a1a-3dea-4ceb-bf56-f360348bd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231406706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4231406706
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1226764914
Short name T230
Test name
Test status
Simulation time 8985132901 ps
CPU time 81.68 seconds
Started Jul 23 04:38:53 PM PDT 24
Finished Jul 23 04:40:16 PM PDT 24
Peak memory 218396 kb
Host smart-7a92468b-fe7a-4902-86e7-5ec94ef52799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226764914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1226764914
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3962812061
Short name T214
Test name
Test status
Simulation time 4234288661 ps
CPU time 33.67 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:33 PM PDT 24
Peak memory 213216 kb
Host smart-a8d8bae0-2829-4378-834a-32c2796aa353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962812061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3962812061
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2762620994
Short name T232
Test name
Test status
Simulation time 16824581340 ps
CPU time 179.91 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:42:03 PM PDT 24
Peak memory 226492 kb
Host smart-d667a48b-a318-4f91-951c-358e5ef2c052
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762620994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2762620994
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2440996999
Short name T259
Test name
Test status
Simulation time 377310704 ps
CPU time 19.01 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:39:23 PM PDT 24
Peak memory 219244 kb
Host smart-ff9d82b1-8ec1-4863-8755-fe5f646ab313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440996999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2440996999
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2642743404
Short name T200
Test name
Test status
Simulation time 9436619857 ps
CPU time 35.24 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:39:40 PM PDT 24
Peak memory 217864 kb
Host smart-6d8b901f-df11-4e3e-a564-4bcac72f4802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642743404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2642743404
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4273576870
Short name T37
Test name
Test status
Simulation time 3459233706 ps
CPU time 43.86 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:39:52 PM PDT 24
Peak memory 214656 kb
Host smart-f6dd598f-1bf0-4714-a377-bae7df0d15c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273576870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4273576870
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3125767066
Short name T18
Test name
Test status
Simulation time 5032367699 ps
CPU time 49.38 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:49 PM PDT 24
Peak memory 216624 kb
Host smart-90bd7590-e4cc-44b1-95aa-2c4e7ae494d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125767066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3125767066
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2710684135
Short name T107
Test name
Test status
Simulation time 10793233436 ps
CPU time 24.01 seconds
Started Jul 23 04:38:59 PM PDT 24
Finished Jul 23 04:39:25 PM PDT 24
Peak memory 217344 kb
Host smart-dc9627d2-5bb0-4382-9525-68b1641eede6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710684135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2710684135
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2203245308
Short name T106
Test name
Test status
Simulation time 38308871309 ps
CPU time 399.04 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:45:41 PM PDT 24
Peak memory 234768 kb
Host smart-13ba5048-f14c-4b37-a786-d90541358808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203245308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2203245308
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3663209631
Short name T318
Test name
Test status
Simulation time 5721868221 ps
CPU time 36.74 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:39:41 PM PDT 24
Peak memory 219220 kb
Host smart-e0791e8b-9908-47bb-b2e3-c295327f7614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663209631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3663209631
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1886921257
Short name T301
Test name
Test status
Simulation time 11280335390 ps
CPU time 25.54 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:30 PM PDT 24
Peak memory 219268 kb
Host smart-a7822f74-0e8d-48cc-ba1c-70e044999db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886921257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1886921257
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1021595993
Short name T332
Test name
Test status
Simulation time 2685133218 ps
CPU time 25.41 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:39:27 PM PDT 24
Peak memory 216576 kb
Host smart-89e96016-f105-4c61-9efe-bd18198c8836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021595993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1021595993
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.693612198
Short name T205
Test name
Test status
Simulation time 686699769 ps
CPU time 21.42 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:39:24 PM PDT 24
Peak memory 219104 kb
Host smart-6d36ef8b-b0e7-4323-88a3-797981402ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693612198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.693612198
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3352556809
Short name T215
Test name
Test status
Simulation time 8536188976 ps
CPU time 21.12 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:39:25 PM PDT 24
Peak memory 213240 kb
Host smart-d869a05b-670f-4506-97fe-2b3f60b97465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352556809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3352556809
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.136312217
Short name T353
Test name
Test status
Simulation time 21723477867 ps
CPU time 231.95 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 234748 kb
Host smart-75d4db94-1ace-4d7f-a0eb-eef774f58d5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136312217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.136312217
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2392410002
Short name T334
Test name
Test status
Simulation time 1313725005 ps
CPU time 27.82 seconds
Started Jul 23 04:39:04 PM PDT 24
Finished Jul 23 04:39:34 PM PDT 24
Peak memory 218688 kb
Host smart-fd8ae302-bb79-41b0-a5a3-31022c4c524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392410002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2392410002
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.206927865
Short name T328
Test name
Test status
Simulation time 709147039 ps
CPU time 10.43 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:39:14 PM PDT 24
Peak memory 219188 kb
Host smart-e03dff57-ffde-45ee-9ab1-cf6d23819908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206927865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.206927865
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2939280272
Short name T46
Test name
Test status
Simulation time 1166875491 ps
CPU time 28.98 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:39:31 PM PDT 24
Peak memory 215728 kb
Host smart-b6dadf2a-12a6-45fb-a514-0fb00fd4b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939280272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2939280272
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.978769471
Short name T35
Test name
Test status
Simulation time 16092247670 ps
CPU time 62.91 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:40:07 PM PDT 24
Peak memory 219220 kb
Host smart-f2c7931a-6395-4af9-a98d-3abb2502b536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978769471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.978769471
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3389349403
Short name T316
Test name
Test status
Simulation time 5135584558 ps
CPU time 23.2 seconds
Started Jul 23 04:39:03 PM PDT 24
Finished Jul 23 04:39:28 PM PDT 24
Peak memory 213260 kb
Host smart-7bf965bb-e0a4-49a0-b928-f60f34151c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389349403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3389349403
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1880056548
Short name T208
Test name
Test status
Simulation time 89525487343 ps
CPU time 504.64 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:47:26 PM PDT 24
Peak memory 234004 kb
Host smart-6628f1c2-a67c-4464-a775-71034c1e9688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880056548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1880056548
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1658324049
Short name T45
Test name
Test status
Simulation time 894067227 ps
CPU time 18.78 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:39:21 PM PDT 24
Peak memory 219236 kb
Host smart-93b0ec06-c5e8-433d-bb49-383d6d95915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658324049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1658324049
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.671885801
Short name T67
Test name
Test status
Simulation time 5482590588 ps
CPU time 24.99 seconds
Started Jul 23 04:39:01 PM PDT 24
Finished Jul 23 04:39:28 PM PDT 24
Peak memory 211876 kb
Host smart-5146e63c-e307-4929-812a-88f1c54b197e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671885801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.671885801
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2701691999
Short name T145
Test name
Test status
Simulation time 8469818230 ps
CPU time 91.5 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 216824 kb
Host smart-23404c8a-5b39-4378-87e6-fba3e0483b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701691999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2701691999
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3907701478
Short name T227
Test name
Test status
Simulation time 115248320341 ps
CPU time 163.35 seconds
Started Jul 23 04:39:02 PM PDT 24
Finished Jul 23 04:41:48 PM PDT 24
Peak memory 219588 kb
Host smart-74604641-17c0-4d47-81e1-c3dc562d08f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907701478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3907701478
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.469488439
Short name T76
Test name
Test status
Simulation time 52678129899 ps
CPU time 32.45 seconds
Started Jul 23 04:38:59 PM PDT 24
Finished Jul 23 04:39:33 PM PDT 24
Peak memory 213200 kb
Host smart-a76f59da-36ad-46d2-9586-94ddc343d28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469488439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.469488439
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4230014481
Short name T55
Test name
Test status
Simulation time 34521292628 ps
CPU time 332.2 seconds
Started Jul 23 04:39:03 PM PDT 24
Finished Jul 23 04:44:38 PM PDT 24
Peak memory 236796 kb
Host smart-5d695101-05f6-472b-b9d1-859c5e98d82e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230014481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4230014481
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2842345677
Short name T52
Test name
Test status
Simulation time 47340717793 ps
CPU time 43.41 seconds
Started Jul 23 04:39:05 PM PDT 24
Finished Jul 23 04:39:50 PM PDT 24
Peak memory 219232 kb
Host smart-b23974f8-5b3f-43ac-a381-9957a8a126bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842345677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2842345677
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2108275495
Short name T272
Test name
Test status
Simulation time 4528830722 ps
CPU time 33.98 seconds
Started Jul 23 04:39:00 PM PDT 24
Finished Jul 23 04:39:35 PM PDT 24
Peak memory 211852 kb
Host smart-8ee9181f-f0af-4c8c-8ad7-87a72ae799cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108275495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2108275495
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2677117415
Short name T149
Test name
Test status
Simulation time 22027751151 ps
CPU time 57.65 seconds
Started Jul 23 04:38:58 PM PDT 24
Finished Jul 23 04:39:58 PM PDT 24
Peak memory 215904 kb
Host smart-195c3a74-ab25-4e77-b96f-c395905fbda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677117415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2677117415
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3116920679
Short name T174
Test name
Test status
Simulation time 8470152419 ps
CPU time 37.53 seconds
Started Jul 23 04:39:03 PM PDT 24
Finished Jul 23 04:39:43 PM PDT 24
Peak memory 219580 kb
Host smart-8d65a501-b564-469c-adb7-96f391dab3b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116920679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3116920679
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1440375552
Short name T68
Test name
Test status
Simulation time 15691732942 ps
CPU time 30.76 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:38:47 PM PDT 24
Peak memory 217396 kb
Host smart-dbb59e0b-eb93-4097-b3b3-87f3cff6cb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440375552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1440375552
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2756178008
Short name T263
Test name
Test status
Simulation time 48264766502 ps
CPU time 373.85 seconds
Started Jul 23 04:38:30 PM PDT 24
Finished Jul 23 04:44:44 PM PDT 24
Peak memory 238080 kb
Host smart-ca7de39c-7517-4da9-bd74-c9c7ac7f71d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756178008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2756178008
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4015939767
Short name T299
Test name
Test status
Simulation time 8253909654 ps
CPU time 69.26 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:39:25 PM PDT 24
Peak memory 219136 kb
Host smart-9e48f9d6-80a5-4a9f-8ad1-9db8853eaa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015939767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4015939767
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2986828891
Short name T286
Test name
Test status
Simulation time 20486747321 ps
CPU time 27.5 seconds
Started Jul 23 04:38:15 PM PDT 24
Finished Jul 23 04:38:45 PM PDT 24
Peak memory 217804 kb
Host smart-9dd0b833-3aff-40f0-87a6-3bfe438a099e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986828891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2986828891
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.229925929
Short name T295
Test name
Test status
Simulation time 367115180 ps
CPU time 19.66 seconds
Started Jul 23 04:38:10 PM PDT 24
Finished Jul 23 04:38:30 PM PDT 24
Peak memory 215616 kb
Host smart-b55b2a69-8269-4379-aa98-0dc0d3d1cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229925929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.229925929
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4036571349
Short name T273
Test name
Test status
Simulation time 14330582524 ps
CPU time 95.96 seconds
Started Jul 23 04:38:11 PM PDT 24
Finished Jul 23 04:39:48 PM PDT 24
Peak memory 221392 kb
Host smart-45739a4e-8beb-4f3d-9c0f-abcd417e68cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036571349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4036571349
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4097954629
Short name T309
Test name
Test status
Simulation time 13399547485 ps
CPU time 28.63 seconds
Started Jul 23 04:38:31 PM PDT 24
Finished Jul 23 04:39:01 PM PDT 24
Peak memory 213252 kb
Host smart-b099ddc8-1d3e-4d61-9aa0-4c1a36187259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097954629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4097954629
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1100662812
Short name T335
Test name
Test status
Simulation time 65478775995 ps
CPU time 553.29 seconds
Started Jul 23 04:38:31 PM PDT 24
Finished Jul 23 04:47:45 PM PDT 24
Peak memory 236332 kb
Host smart-c78fa5f0-57c5-442f-afb1-c6aba96e692b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100662812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1100662812
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2269968036
Short name T158
Test name
Test status
Simulation time 7677636038 ps
CPU time 63.66 seconds
Started Jul 23 04:38:24 PM PDT 24
Finished Jul 23 04:39:28 PM PDT 24
Peak memory 219316 kb
Host smart-512b5362-8fd5-406b-9809-1acd7930ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269968036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2269968036
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1781922574
Short name T180
Test name
Test status
Simulation time 1979328508 ps
CPU time 22.43 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:38:38 PM PDT 24
Peak memory 219208 kb
Host smart-161fd786-4f3e-4bed-9ce1-ce5a3aff1c62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781922574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1781922574
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3838334764
Short name T186
Test name
Test status
Simulation time 11604836577 ps
CPU time 65.83 seconds
Started Jul 23 04:38:18 PM PDT 24
Finished Jul 23 04:39:24 PM PDT 24
Peak memory 216360 kb
Host smart-70738343-777f-4597-9579-43519b88f9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838334764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3838334764
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3152414766
Short name T137
Test name
Test status
Simulation time 34541508518 ps
CPU time 93.54 seconds
Started Jul 23 04:38:19 PM PDT 24
Finished Jul 23 04:39:54 PM PDT 24
Peak memory 219812 kb
Host smart-19e40cac-185e-42e8-b1ab-5840f78153de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152414766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3152414766
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2623709255
Short name T65
Test name
Test status
Simulation time 7824263428 ps
CPU time 19.63 seconds
Started Jul 23 04:38:15 PM PDT 24
Finished Jul 23 04:38:37 PM PDT 24
Peak memory 213200 kb
Host smart-bb3d5219-1ca2-487f-a030-c0940d2e0b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623709255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2623709255
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2626842523
Short name T296
Test name
Test status
Simulation time 9343501061 ps
CPU time 291.91 seconds
Started Jul 23 04:38:13 PM PDT 24
Finished Jul 23 04:43:06 PM PDT 24
Peak memory 215768 kb
Host smart-8dc92e45-7b23-4b16-946d-222664e2a76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626842523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2626842523
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3300024201
Short name T220
Test name
Test status
Simulation time 48172690181 ps
CPU time 65.2 seconds
Started Jul 23 04:38:21 PM PDT 24
Finished Jul 23 04:39:27 PM PDT 24
Peak memory 219304 kb
Host smart-16ef6382-d827-4ebf-afda-76d1066b980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300024201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3300024201
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1628272607
Short name T267
Test name
Test status
Simulation time 10311039202 ps
CPU time 23.57 seconds
Started Jul 23 04:38:15 PM PDT 24
Finished Jul 23 04:38:41 PM PDT 24
Peak memory 219200 kb
Host smart-92ae5c5a-e4f6-4bd8-8d90-eed371a5ae32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628272607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1628272607
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.332296998
Short name T196
Test name
Test status
Simulation time 354011731 ps
CPU time 19.99 seconds
Started Jul 23 04:38:25 PM PDT 24
Finished Jul 23 04:38:45 PM PDT 24
Peak memory 215572 kb
Host smart-4bb8b17c-d228-443f-be8d-cd4bbe5af749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332296998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.332296998
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1736022399
Short name T279
Test name
Test status
Simulation time 1528515548 ps
CPU time 15.12 seconds
Started Jul 23 04:38:19 PM PDT 24
Finished Jul 23 04:38:35 PM PDT 24
Peak memory 219176 kb
Host smart-9a91adb1-50f6-4677-85f8-1fea61ca8227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736022399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1736022399
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3202888182
Short name T213
Test name
Test status
Simulation time 662033956 ps
CPU time 8.3 seconds
Started Jul 23 04:38:31 PM PDT 24
Finished Jul 23 04:38:40 PM PDT 24
Peak memory 216932 kb
Host smart-e02a3090-add9-4e35-88dc-0e9422057f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202888182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3202888182
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.450255905
Short name T40
Test name
Test status
Simulation time 82153856074 ps
CPU time 673.09 seconds
Started Jul 23 04:38:28 PM PDT 24
Finished Jul 23 04:49:42 PM PDT 24
Peak memory 219396 kb
Host smart-1f28b860-eb32-4bad-bf81-35631fe6662c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450255905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.450255905
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2520653896
Short name T247
Test name
Test status
Simulation time 581490101 ps
CPU time 19.3 seconds
Started Jul 23 04:38:16 PM PDT 24
Finished Jul 23 04:38:37 PM PDT 24
Peak memory 219204 kb
Host smart-f929f76f-c5c9-4a10-a56c-fb89915f7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520653896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2520653896
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2342546846
Short name T271
Test name
Test status
Simulation time 183336348 ps
CPU time 10.5 seconds
Started Jul 23 04:38:24 PM PDT 24
Finished Jul 23 04:38:35 PM PDT 24
Peak memory 219176 kb
Host smart-804bb033-a381-457b-9e1c-e05b0781d9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342546846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2342546846
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2594627069
Short name T357
Test name
Test status
Simulation time 27700072116 ps
CPU time 65.92 seconds
Started Jul 23 04:38:24 PM PDT 24
Finished Jul 23 04:39:31 PM PDT 24
Peak memory 216612 kb
Host smart-f5527888-1ae1-4f48-ab3b-c283756596ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594627069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2594627069
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2303894800
Short name T15
Test name
Test status
Simulation time 19188176645 ps
CPU time 716.94 seconds
Started Jul 23 04:38:17 PM PDT 24
Finished Jul 23 04:50:15 PM PDT 24
Peak memory 235768 kb
Host smart-2c0297a1-8256-46f5-bd32-fcce4e3e7279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303894800 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2303894800
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.606587759
Short name T36
Test name
Test status
Simulation time 1893712263 ps
CPU time 20.04 seconds
Started Jul 23 04:38:17 PM PDT 24
Finished Jul 23 04:38:38 PM PDT 24
Peak memory 213144 kb
Host smart-170423a3-8fcd-4887-be90-a19dcaede6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606587759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.606587759
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2801242539
Short name T314
Test name
Test status
Simulation time 89017285740 ps
CPU time 378.26 seconds
Started Jul 23 04:38:23 PM PDT 24
Finished Jul 23 04:44:42 PM PDT 24
Peak memory 237884 kb
Host smart-dd8d493d-0a60-4883-9cde-e6dc22760058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801242539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2801242539
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3892639253
Short name T242
Test name
Test status
Simulation time 15654123602 ps
CPU time 42.04 seconds
Started Jul 23 04:38:24 PM PDT 24
Finished Jul 23 04:39:07 PM PDT 24
Peak memory 219164 kb
Host smart-2a05c2be-b444-4197-b790-69a6983f1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892639253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3892639253
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3981628906
Short name T346
Test name
Test status
Simulation time 8855999338 ps
CPU time 22.89 seconds
Started Jul 23 04:38:14 PM PDT 24
Finished Jul 23 04:38:39 PM PDT 24
Peak memory 211600 kb
Host smart-3d218e5b-07f3-4956-b513-9acf77bbdac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981628906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3981628906
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3628872143
Short name T161
Test name
Test status
Simulation time 7368310981 ps
CPU time 57.33 seconds
Started Jul 23 04:38:34 PM PDT 24
Finished Jul 23 04:39:33 PM PDT 24
Peak memory 216372 kb
Host smart-cd7ffcdc-321f-42f9-9eff-c9743ca51eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628872143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3628872143
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1735581799
Short name T234
Test name
Test status
Simulation time 585794136 ps
CPU time 38.87 seconds
Started Jul 23 04:38:17 PM PDT 24
Finished Jul 23 04:38:57 PM PDT 24
Peak memory 219216 kb
Host smart-a537b3e4-edb6-4b3b-b75a-eadcd967b014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735581799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1735581799
Directory /workspace/9.rom_ctrl_stress_all/latest
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