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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.68 100.00 98.62 97.30 98.37


Total test records in report: 453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T305 /workspace/coverage/default/18.rom_ctrl_stress_all.565664975 Jul 24 04:57:25 PM PDT 24 Jul 24 04:57:39 PM PDT 24 3079073094 ps
T306 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1786917521 Jul 24 04:57:56 PM PDT 24 Jul 24 05:05:35 PM PDT 24 164613155872 ps
T307 /workspace/coverage/default/24.rom_ctrl_alert_test.1840696653 Jul 24 04:57:41 PM PDT 24 Jul 24 04:58:05 PM PDT 24 11151086458 ps
T308 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1005812463 Jul 24 04:58:16 PM PDT 24 Jul 24 05:02:05 PM PDT 24 13418824929 ps
T309 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2714666290 Jul 24 04:57:44 PM PDT 24 Jul 24 04:58:06 PM PDT 24 7576686200 ps
T310 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.345361669 Jul 24 04:57:52 PM PDT 24 Jul 24 05:06:27 PM PDT 24 65218546753 ps
T311 /workspace/coverage/default/12.rom_ctrl_smoke.2277335615 Jul 24 04:57:14 PM PDT 24 Jul 24 04:58:29 PM PDT 24 8526421484 ps
T312 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4285267418 Jul 24 04:56:57 PM PDT 24 Jul 24 05:01:47 PM PDT 24 3974871022 ps
T313 /workspace/coverage/default/41.rom_ctrl_alert_test.568865782 Jul 24 04:57:59 PM PDT 24 Jul 24 04:58:30 PM PDT 24 8571666491 ps
T314 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.987741958 Jul 24 04:57:25 PM PDT 24 Jul 24 04:58:12 PM PDT 24 19082512867 ps
T315 /workspace/coverage/default/25.rom_ctrl_stress_all.1421387385 Jul 24 04:57:39 PM PDT 24 Jul 24 04:58:12 PM PDT 24 4774378899 ps
T316 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3299496892 Jul 24 04:57:11 PM PDT 24 Jul 24 04:57:42 PM PDT 24 7517444522 ps
T317 /workspace/coverage/default/32.rom_ctrl_alert_test.1420885581 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:10 PM PDT 24 174458511 ps
T318 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2299440510 Jul 24 04:57:43 PM PDT 24 Jul 24 04:58:03 PM PDT 24 3029542365 ps
T319 /workspace/coverage/default/47.rom_ctrl_stress_all.1485830187 Jul 24 04:58:14 PM PDT 24 Jul 24 04:58:44 PM PDT 24 2415981257 ps
T320 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2599060188 Jul 24 04:57:47 PM PDT 24 Jul 24 05:01:12 PM PDT 24 3024509530 ps
T321 /workspace/coverage/default/15.rom_ctrl_alert_test.1615566921 Jul 24 04:57:31 PM PDT 24 Jul 24 04:57:54 PM PDT 24 2404364330 ps
T322 /workspace/coverage/default/9.rom_ctrl_alert_test.38874313 Jul 24 04:57:19 PM PDT 24 Jul 24 04:57:45 PM PDT 24 7023211461 ps
T323 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4271816025 Jul 24 04:58:17 PM PDT 24 Jul 24 05:07:40 PM PDT 24 54872688505 ps
T324 /workspace/coverage/default/40.rom_ctrl_alert_test.61963639 Jul 24 04:58:05 PM PDT 24 Jul 24 04:58:27 PM PDT 24 2376185158 ps
T325 /workspace/coverage/default/16.rom_ctrl_smoke.2128745229 Jul 24 04:57:16 PM PDT 24 Jul 24 04:57:36 PM PDT 24 349296090 ps
T326 /workspace/coverage/default/25.rom_ctrl_alert_test.666652150 Jul 24 04:57:44 PM PDT 24 Jul 24 04:57:53 PM PDT 24 174532179 ps
T327 /workspace/coverage/default/44.rom_ctrl_stress_all.1420839408 Jul 24 04:58:05 PM PDT 24 Jul 24 04:59:41 PM PDT 24 80123413751 ps
T328 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4265945853 Jul 24 04:56:58 PM PDT 24 Jul 24 05:02:09 PM PDT 24 140503148736 ps
T329 /workspace/coverage/default/15.rom_ctrl_smoke.1107678242 Jul 24 04:57:16 PM PDT 24 Jul 24 04:58:23 PM PDT 24 7056054715 ps
T330 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2050862202 Jul 24 04:57:28 PM PDT 24 Jul 24 05:05:49 PM PDT 24 195911716855 ps
T331 /workspace/coverage/default/6.rom_ctrl_stress_all.3793289483 Jul 24 04:57:17 PM PDT 24 Jul 24 04:59:15 PM PDT 24 77516979725 ps
T332 /workspace/coverage/default/45.rom_ctrl_stress_all.3301148961 Jul 24 04:58:18 PM PDT 24 Jul 24 04:58:59 PM PDT 24 2257805163 ps
T333 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2217253492 Jul 24 04:57:33 PM PDT 24 Jul 24 05:10:32 PM PDT 24 806773711427 ps
T334 /workspace/coverage/default/12.rom_ctrl_stress_all.2864566225 Jul 24 04:57:16 PM PDT 24 Jul 24 04:58:35 PM PDT 24 15548169916 ps
T335 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3781900853 Jul 24 04:58:03 PM PDT 24 Jul 24 05:04:40 PM PDT 24 36501173075 ps
T336 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2397430623 Jul 24 04:58:20 PM PDT 24 Jul 24 04:59:28 PM PDT 24 8444290951 ps
T337 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2643330603 Jul 24 04:57:45 PM PDT 24 Jul 24 04:58:03 PM PDT 24 335782938 ps
T338 /workspace/coverage/default/14.rom_ctrl_stress_all.870428960 Jul 24 04:57:15 PM PDT 24 Jul 24 05:00:52 PM PDT 24 30936787013 ps
T339 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4198387980 Jul 24 04:58:03 PM PDT 24 Jul 24 04:58:58 PM PDT 24 6014355068 ps
T340 /workspace/coverage/default/12.rom_ctrl_alert_test.1768359988 Jul 24 04:57:13 PM PDT 24 Jul 24 04:57:46 PM PDT 24 4085993635 ps
T341 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4273517544 Jul 24 04:57:01 PM PDT 24 Jul 24 04:57:52 PM PDT 24 22817282979 ps
T342 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3922973060 Jul 24 04:56:55 PM PDT 24 Jul 24 05:03:43 PM PDT 24 110662834147 ps
T343 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3774144856 Jul 24 04:57:43 PM PDT 24 Jul 24 04:57:54 PM PDT 24 672651361 ps
T344 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2306621458 Jul 24 04:58:07 PM PDT 24 Jul 24 05:03:06 PM PDT 24 4453626979 ps
T345 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.212360685 Jul 24 04:57:39 PM PDT 24 Jul 24 04:58:35 PM PDT 24 13071117461 ps
T346 /workspace/coverage/default/44.rom_ctrl_smoke.1102981271 Jul 24 04:58:06 PM PDT 24 Jul 24 04:58:37 PM PDT 24 9111168753 ps
T347 /workspace/coverage/default/35.rom_ctrl_stress_all.3265396235 Jul 24 04:57:58 PM PDT 24 Jul 24 04:59:45 PM PDT 24 9267231496 ps
T348 /workspace/coverage/default/27.rom_ctrl_stress_all.3883571205 Jul 24 04:57:41 PM PDT 24 Jul 24 04:58:03 PM PDT 24 400485894 ps
T349 /workspace/coverage/default/36.rom_ctrl_smoke.1765195048 Jul 24 04:57:59 PM PDT 24 Jul 24 04:58:49 PM PDT 24 5268090125 ps
T350 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3080313836 Jul 24 04:58:01 PM PDT 24 Jul 24 05:12:56 PM PDT 24 171320049705 ps
T351 /workspace/coverage/default/39.rom_ctrl_smoke.155461375 Jul 24 04:57:58 PM PDT 24 Jul 24 04:58:54 PM PDT 24 5488171303 ps
T352 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1597754717 Jul 24 04:57:43 PM PDT 24 Jul 24 04:58:11 PM PDT 24 2900790218 ps
T353 /workspace/coverage/default/6.rom_ctrl_smoke.1917962495 Jul 24 04:57:12 PM PDT 24 Jul 24 04:58:03 PM PDT 24 8706338239 ps
T354 /workspace/coverage/default/37.rom_ctrl_stress_all.1347535510 Jul 24 04:57:56 PM PDT 24 Jul 24 04:59:30 PM PDT 24 63099042044 ps
T355 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3689818768 Jul 24 04:57:48 PM PDT 24 Jul 24 04:58:25 PM PDT 24 10470354365 ps
T356 /workspace/coverage/default/30.rom_ctrl_stress_all.2983221547 Jul 24 04:57:52 PM PDT 24 Jul 24 04:58:32 PM PDT 24 2938212248 ps
T357 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4246363602 Jul 24 04:57:53 PM PDT 24 Jul 24 04:58:23 PM PDT 24 14779383162 ps
T358 /workspace/coverage/default/16.rom_ctrl_stress_all.3137845045 Jul 24 04:57:31 PM PDT 24 Jul 24 04:58:12 PM PDT 24 2111467289 ps
T359 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1184202348 Jul 24 04:57:03 PM PDT 24 Jul 24 04:57:13 PM PDT 24 185587795 ps
T27 /workspace/coverage/default/4.rom_ctrl_sec_cm.124321643 Jul 24 04:57:12 PM PDT 24 Jul 24 04:59:32 PM PDT 24 70540288930 ps
T360 /workspace/coverage/default/38.rom_ctrl_smoke.3690203288 Jul 24 04:57:53 PM PDT 24 Jul 24 04:58:48 PM PDT 24 4970581006 ps
T361 /workspace/coverage/default/23.rom_ctrl_alert_test.2078133704 Jul 24 04:57:33 PM PDT 24 Jul 24 04:58:02 PM PDT 24 3639763473 ps
T362 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3347330522 Jul 24 04:57:11 PM PDT 24 Jul 24 04:57:40 PM PDT 24 3291803285 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1767837281 Jul 24 04:55:17 PM PDT 24 Jul 24 04:55:49 PM PDT 24 16455677524 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2147732653 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:42 PM PDT 24 1806486267 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3631764142 Jul 24 04:55:22 PM PDT 24 Jul 24 04:55:40 PM PDT 24 1597070398 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2911767606 Jul 24 04:55:07 PM PDT 24 Jul 24 04:55:18 PM PDT 24 1644801006 ps
T48 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3363515661 Jul 24 04:55:27 PM PDT 24 Jul 24 04:55:54 PM PDT 24 2346994056 ps
T67 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.100765132 Jul 24 04:55:20 PM PDT 24 Jul 24 04:55:34 PM PDT 24 2203871011 ps
T49 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1358692232 Jul 24 04:55:30 PM PDT 24 Jul 24 04:55:43 PM PDT 24 169238316 ps
T50 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.113875582 Jul 24 04:55:30 PM PDT 24 Jul 24 04:55:41 PM PDT 24 174230147 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1994142881 Jul 24 04:55:29 PM PDT 24 Jul 24 04:56:50 PM PDT 24 487995192 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2135522144 Jul 24 04:55:31 PM PDT 24 Jul 24 04:57:50 PM PDT 24 15862708657 ps
T75 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.775782375 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:47 PM PDT 24 52523780967 ps
T76 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.882632857 Jul 24 04:55:27 PM PDT 24 Jul 24 04:56:36 PM PDT 24 10079082933 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.531730002 Jul 24 04:55:01 PM PDT 24 Jul 24 04:55:33 PM PDT 24 13149717496 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.535849321 Jul 24 04:55:22 PM PDT 24 Jul 24 04:55:31 PM PDT 24 332099598 ps
T78 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1540288022 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:51 PM PDT 24 24449737819 ps
T52 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2246988379 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:41 PM PDT 24 3609040785 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1629618345 Jul 24 04:55:04 PM PDT 24 Jul 24 04:55:41 PM PDT 24 3960458801 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3240925853 Jul 24 04:55:21 PM PDT 24 Jul 24 04:55:42 PM PDT 24 11349020503 ps
T62 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1568320364 Jul 24 04:55:29 PM PDT 24 Jul 24 04:58:22 PM PDT 24 3925423437 ps
T73 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.644367128 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:56 PM PDT 24 2149899658 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1502216144 Jul 24 04:55:27 PM PDT 24 Jul 24 04:55:48 PM PDT 24 7940777605 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.400257180 Jul 24 04:55:21 PM PDT 24 Jul 24 04:55:30 PM PDT 24 687698437 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1615821686 Jul 24 04:55:31 PM PDT 24 Jul 24 04:55:59 PM PDT 24 10971688748 ps
T367 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.188352610 Jul 24 04:55:34 PM PDT 24 Jul 24 04:55:54 PM PDT 24 1806939730 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2580885478 Jul 24 04:55:23 PM PDT 24 Jul 24 04:56:52 PM PDT 24 20632563210 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.653073825 Jul 24 04:55:09 PM PDT 24 Jul 24 04:55:25 PM PDT 24 1295990334 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.829613593 Jul 24 04:55:13 PM PDT 24 Jul 24 04:55:47 PM PDT 24 27550819104 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2443848220 Jul 24 04:55:11 PM PDT 24 Jul 24 04:55:35 PM PDT 24 2920689567 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.739072679 Jul 24 04:55:04 PM PDT 24 Jul 24 04:55:12 PM PDT 24 170852111 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.641695250 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:59 PM PDT 24 4114934995 ps
T82 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2734024587 Jul 24 04:55:20 PM PDT 24 Jul 24 04:55:28 PM PDT 24 189841050 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.78981772 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:53 PM PDT 24 16067107425 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2904548139 Jul 24 04:55:25 PM PDT 24 Jul 24 04:55:49 PM PDT 24 5623732906 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3481799211 Jul 24 04:55:24 PM PDT 24 Jul 24 04:55:41 PM PDT 24 2335643733 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1603829858 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:52 PM PDT 24 7913885224 ps
T374 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3147001125 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:55 PM PDT 24 3668751285 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.50816138 Jul 24 04:55:18 PM PDT 24 Jul 24 04:58:33 PM PDT 24 98717956437 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4037939697 Jul 24 04:55:12 PM PDT 24 Jul 24 04:55:20 PM PDT 24 352630443 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.531483768 Jul 24 04:55:35 PM PDT 24 Jul 24 04:55:58 PM PDT 24 2309174433 ps
T377 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1075568493 Jul 24 04:55:21 PM PDT 24 Jul 24 04:57:31 PM PDT 24 16105346044 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.325452739 Jul 24 04:55:27 PM PDT 24 Jul 24 04:55:58 PM PDT 24 30365362316 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2933654855 Jul 24 04:55:16 PM PDT 24 Jul 24 04:55:26 PM PDT 24 373546867 ps
T380 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2579293546 Jul 24 04:55:18 PM PDT 24 Jul 24 04:55:54 PM PDT 24 64030918806 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.135970837 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:41 PM PDT 24 5948630820 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1273584880 Jul 24 04:55:18 PM PDT 24 Jul 24 04:55:49 PM PDT 24 7979323208 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1605787220 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:31 PM PDT 24 338854771 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1817531586 Jul 24 04:55:32 PM PDT 24 Jul 24 04:56:53 PM PDT 24 4283291457 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.860008549 Jul 24 04:55:25 PM PDT 24 Jul 24 04:55:33 PM PDT 24 660826967 ps
T119 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4128783008 Jul 24 04:55:27 PM PDT 24 Jul 24 04:58:08 PM PDT 24 3710527084 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2031204469 Jul 24 04:55:21 PM PDT 24 Jul 24 04:55:37 PM PDT 24 1356607920 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4104042356 Jul 24 04:54:56 PM PDT 24 Jul 24 04:55:10 PM PDT 24 11708741951 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1781836027 Jul 24 04:55:24 PM PDT 24 Jul 24 04:56:55 PM PDT 24 9618524335 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.480572963 Jul 24 04:55:03 PM PDT 24 Jul 24 04:55:11 PM PDT 24 231293317 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1266156065 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:40 PM PDT 24 672900947 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1675820764 Jul 24 04:55:22 PM PDT 24 Jul 24 04:56:48 PM PDT 24 19988180977 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4022830162 Jul 24 04:55:18 PM PDT 24 Jul 24 04:58:26 PM PDT 24 122079739578 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1845001894 Jul 24 04:55:08 PM PDT 24 Jul 24 04:55:46 PM PDT 24 11395651076 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2368277298 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:44 PM PDT 24 6714615120 ps
T390 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3669476385 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:57 PM PDT 24 2557693736 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3501877744 Jul 24 04:55:15 PM PDT 24 Jul 24 04:55:32 PM PDT 24 2055312364 ps
T116 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3511402176 Jul 24 04:55:09 PM PDT 24 Jul 24 04:56:36 PM PDT 24 1727901124 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3818305336 Jul 24 04:55:28 PM PDT 24 Jul 24 04:56:00 PM PDT 24 4018407656 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2087978276 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:51 PM PDT 24 2467303672 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1897263299 Jul 24 04:55:22 PM PDT 24 Jul 24 04:55:41 PM PDT 24 924734705 ps
T124 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1067409004 Jul 24 04:55:06 PM PDT 24 Jul 24 04:57:50 PM PDT 24 8064456832 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2064921410 Jul 24 04:55:29 PM PDT 24 Jul 24 04:56:01 PM PDT 24 17805537471 ps
T120 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.679611218 Jul 24 04:55:14 PM PDT 24 Jul 24 04:56:53 PM PDT 24 14346002832 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1294073133 Jul 24 04:55:23 PM PDT 24 Jul 24 04:57:22 PM PDT 24 57577292758 ps
T396 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.528052357 Jul 24 04:55:21 PM PDT 24 Jul 24 04:55:45 PM PDT 24 9777096045 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3979349845 Jul 24 04:55:29 PM PDT 24 Jul 24 04:55:58 PM PDT 24 13260469495 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2576984933 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:52 PM PDT 24 10591441689 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3004492153 Jul 24 04:55:05 PM PDT 24 Jul 24 04:55:37 PM PDT 24 19402466759 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3101269129 Jul 24 04:55:06 PM PDT 24 Jul 24 04:55:39 PM PDT 24 34920561501 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4132294858 Jul 24 04:55:23 PM PDT 24 Jul 24 04:56:57 PM PDT 24 2216784951 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1368359917 Jul 24 04:55:07 PM PDT 24 Jul 24 04:55:19 PM PDT 24 582849138 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1195556096 Jul 24 04:55:15 PM PDT 24 Jul 24 04:55:47 PM PDT 24 18576569381 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.917415116 Jul 24 04:55:18 PM PDT 24 Jul 24 04:57:20 PM PDT 24 14856700314 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2983705614 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:37 PM PDT 24 176006363 ps
T121 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1904526678 Jul 24 04:55:31 PM PDT 24 Jul 24 04:58:05 PM PDT 24 497873469 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1827531235 Jul 24 04:55:24 PM PDT 24 Jul 24 04:55:53 PM PDT 24 21554151259 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1030041785 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:36 PM PDT 24 345653873 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1550483750 Jul 24 04:55:29 PM PDT 24 Jul 24 04:55:46 PM PDT 24 2310152216 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2830547587 Jul 24 04:55:10 PM PDT 24 Jul 24 04:55:33 PM PDT 24 5500819776 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3512529316 Jul 24 04:55:06 PM PDT 24 Jul 24 04:55:43 PM PDT 24 14237559768 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2437637141 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:40 PM PDT 24 1711690653 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2457917575 Jul 24 04:55:06 PM PDT 24 Jul 24 04:55:32 PM PDT 24 3372626314 ps
T126 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3777861428 Jul 24 04:55:20 PM PDT 24 Jul 24 04:57:56 PM PDT 24 551467907 ps
T122 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3266607617 Jul 24 04:55:23 PM PDT 24 Jul 24 04:58:18 PM PDT 24 4092321064 ps
T117 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3243982463 Jul 24 04:55:25 PM PDT 24 Jul 24 04:57:04 PM PDT 24 19400539868 ps
T412 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2180952728 Jul 24 04:55:32 PM PDT 24 Jul 24 04:55:55 PM PDT 24 9466140015 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2807832626 Jul 24 04:55:17 PM PDT 24 Jul 24 04:58:23 PM PDT 24 88787200971 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1216177477 Jul 24 04:55:03 PM PDT 24 Jul 24 04:55:31 PM PDT 24 40981285908 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2529644251 Jul 24 04:55:18 PM PDT 24 Jul 24 04:55:26 PM PDT 24 174432459 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3490751209 Jul 24 04:55:23 PM PDT 24 Jul 24 04:55:50 PM PDT 24 12150245451 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1753755928 Jul 24 04:55:22 PM PDT 24 Jul 24 04:55:30 PM PDT 24 331948602 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2184867265 Jul 24 04:55:17 PM PDT 24 Jul 24 04:58:21 PM PDT 24 22566591371 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3953472252 Jul 24 04:55:20 PM PDT 24 Jul 24 04:55:47 PM PDT 24 3471515281 ps
T127 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3560275250 Jul 24 04:55:19 PM PDT 24 Jul 24 04:58:06 PM PDT 24 3411237373 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1365025442 Jul 24 04:55:19 PM PDT 24 Jul 24 04:55:48 PM PDT 24 14033129177 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3105057183 Jul 24 04:55:30 PM PDT 24 Jul 24 04:55:46 PM PDT 24 3158103738 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2647831715 Jul 24 04:55:31 PM PDT 24 Jul 24 04:57:09 PM PDT 24 6346626477 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3129018552 Jul 24 04:55:05 PM PDT 24 Jul 24 04:55:14 PM PDT 24 354587749 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2090436546 Jul 24 04:55:27 PM PDT 24 Jul 24 04:56:59 PM PDT 24 10677296092 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2416170345 Jul 24 04:55:08 PM PDT 24 Jul 24 04:55:37 PM PDT 24 6301166863 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3656818626 Jul 24 04:55:30 PM PDT 24 Jul 24 04:57:50 PM PDT 24 14896505704 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1999657971 Jul 24 04:55:03 PM PDT 24 Jul 24 04:55:12 PM PDT 24 338669221 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1193065086 Jul 24 04:55:25 PM PDT 24 Jul 24 04:55:44 PM PDT 24 3943415429 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.290865316 Jul 24 04:55:17 PM PDT 24 Jul 24 04:56:48 PM PDT 24 18361698157 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3264217905 Jul 24 04:55:02 PM PDT 24 Jul 24 04:56:21 PM PDT 24 4552718474 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3139495967 Jul 24 04:55:21 PM PDT 24 Jul 24 04:56:51 PM PDT 24 3875278397 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1879203722 Jul 24 04:55:24 PM PDT 24 Jul 24 04:55:33 PM PDT 24 186618875 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2306407166 Jul 24 04:55:32 PM PDT 24 Jul 24 04:55:56 PM PDT 24 8185900072 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3086926664 Jul 24 04:55:26 PM PDT 24 Jul 24 04:56:23 PM PDT 24 4136354394 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3116899307 Jul 24 04:55:14 PM PDT 24 Jul 24 04:55:36 PM PDT 24 2422778858 ps
T99 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3024894505 Jul 24 04:55:06 PM PDT 24 Jul 24 04:57:47 PM PDT 24 18275722129 ps
T125 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.852220290 Jul 24 04:55:20 PM PDT 24 Jul 24 04:57:52 PM PDT 24 344215126 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.105494201 Jul 24 04:55:18 PM PDT 24 Jul 24 04:55:44 PM PDT 24 2515454528 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1685753293 Jul 24 04:55:13 PM PDT 24 Jul 24 04:55:21 PM PDT 24 612709475 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3733090562 Jul 24 04:55:15 PM PDT 24 Jul 24 04:55:36 PM PDT 24 12609030412 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3481953970 Jul 24 04:55:05 PM PDT 24 Jul 24 04:55:21 PM PDT 24 395010331 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4149846225 Jul 24 04:55:29 PM PDT 24 Jul 24 04:56:05 PM PDT 24 4205860741 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1717335068 Jul 24 04:55:27 PM PDT 24 Jul 24 04:55:49 PM PDT 24 2262991291 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3987565936 Jul 24 04:55:24 PM PDT 24 Jul 24 04:55:45 PM PDT 24 3771123880 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2420815148 Jul 24 04:55:30 PM PDT 24 Jul 24 04:56:05 PM PDT 24 3929115734 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2323963078 Jul 24 04:55:14 PM PDT 24 Jul 24 04:55:22 PM PDT 24 2060419143 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1766919679 Jul 24 04:55:04 PM PDT 24 Jul 24 04:55:32 PM PDT 24 11277179350 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2685628192 Jul 24 04:55:02 PM PDT 24 Jul 24 04:55:24 PM PDT 24 1513160358 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.168301719 Jul 24 04:55:15 PM PDT 24 Jul 24 04:55:46 PM PDT 24 4339029927 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3434277647 Jul 24 04:55:28 PM PDT 24 Jul 24 04:55:37 PM PDT 24 836874741 ps
T118 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2858623224 Jul 24 04:55:23 PM PDT 24 Jul 24 04:58:06 PM PDT 24 4080297948 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2854628278 Jul 24 04:55:21 PM PDT 24 Jul 24 04:55:42 PM PDT 24 4878465799 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3473066762 Jul 24 04:55:37 PM PDT 24 Jul 24 04:56:06 PM PDT 24 6109143390 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2362396969 Jul 24 04:55:20 PM PDT 24 Jul 24 04:55:38 PM PDT 24 1175877520 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2889595704 Jul 24 04:55:26 PM PDT 24 Jul 24 04:58:16 PM PDT 24 5679373327 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.681467299 Jul 24 04:55:02 PM PDT 24 Jul 24 04:55:30 PM PDT 24 12037680836 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.784106597 Jul 24 04:55:16 PM PDT 24 Jul 24 04:57:27 PM PDT 24 56029507413 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1484693438 Jul 24 04:55:18 PM PDT 24 Jul 24 04:55:27 PM PDT 24 167530294 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2537536324 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:38 PM PDT 24 515845201 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2368293728 Jul 24 04:55:14 PM PDT 24 Jul 24 04:55:25 PM PDT 24 364916999 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.678437269 Jul 24 04:55:26 PM PDT 24 Jul 24 04:55:51 PM PDT 24 12323888230 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.356157421 Jul 24 04:55:08 PM PDT 24 Jul 24 04:57:54 PM PDT 24 2735710520 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.554315445 Jul 24 04:55:24 PM PDT 24 Jul 24 04:55:46 PM PDT 24 8942433878 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2441388363 Jul 24 04:55:11 PM PDT 24 Jul 24 04:55:39 PM PDT 24 3476907154 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.650949399 Jul 24 04:55:10 PM PDT 24 Jul 24 04:55:29 PM PDT 24 3599117697 ps

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3957718108
Short name T10
Test name
Test status
Simulation time 21580674559 ps
CPU time 354.21 seconds
Started Jul 24 04:57:28 PM PDT 24
Finished Jul 24 05:03:22 PM PDT 24
Peak memory 237408 kb
Host smart-56530161-9e65-48d6-b632-edaa75f6a319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957718108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3957718108
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1391304350
Short name T14
Test name
Test status
Simulation time 101135445432 ps
CPU time 1025 seconds
Started Jul 24 04:58:20 PM PDT 24
Finished Jul 24 05:15:25 PM PDT 24
Peak memory 237096 kb
Host smart-31bf9f9a-9e74-4eb6-8743-5068fc015805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391304350 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1391304350
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1252054468
Short name T12
Test name
Test status
Simulation time 343811713 ps
CPU time 19.94 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:57:36 PM PDT 24
Peak memory 215792 kb
Host smart-2c06d1d8-e288-4349-acb8-8132553c8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252054468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1252054468
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3304309186
Short name T31
Test name
Test status
Simulation time 1380316767 ps
CPU time 18.53 seconds
Started Jul 24 04:58:17 PM PDT 24
Finished Jul 24 04:58:35 PM PDT 24
Peak memory 211268 kb
Host smart-ee7f5aea-22b3-4e70-8a52-257bec33afd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304309186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3304309186
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.637560334
Short name T19
Test name
Test status
Simulation time 23371880410 ps
CPU time 40.26 seconds
Started Jul 24 04:58:02 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 215892 kb
Host smart-dda24592-4df8-4b00-bc2a-eaaa2e0e035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637560334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.637560334
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4128783008
Short name T119
Test name
Test status
Simulation time 3710527084 ps
CPU time 160.08 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:58:08 PM PDT 24
Peak memory 212672 kb
Host smart-e711e723-6d5f-4110-afbc-2fd8b7c974bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128783008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4128783008
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.542228388
Short name T23
Test name
Test status
Simulation time 6341292867 ps
CPU time 26.15 seconds
Started Jul 24 04:57:17 PM PDT 24
Finished Jul 24 04:57:43 PM PDT 24
Peak memory 217380 kb
Host smart-a838ae33-1430-4f60-8fcd-e09ead094411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542228388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.542228388
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3746397927
Short name T139
Test name
Test status
Simulation time 2382025126 ps
CPU time 24.49 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:38 PM PDT 24
Peak memory 219364 kb
Host smart-184a6096-a933-4204-a90a-794baa26fd2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746397927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3746397927
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4274842376
Short name T21
Test name
Test status
Simulation time 8178166630 ps
CPU time 137.43 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 04:59:24 PM PDT 24
Peak memory 238240 kb
Host smart-de185189-4547-4a13-bd57-838598f46ac6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274842376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4274842376
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2288285687
Short name T8
Test name
Test status
Simulation time 177369673 ps
CPU time 10.21 seconds
Started Jul 24 04:57:24 PM PDT 24
Finished Jul 24 04:57:34 PM PDT 24
Peak memory 219188 kb
Host smart-f681048f-eb66-4889-b318-9735a42da16c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288285687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2288285687
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.775782375
Short name T75
Test name
Test status
Simulation time 52523780967 ps
CPU time 23.53 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:47 PM PDT 24
Peak memory 211912 kb
Host smart-82a2fb51-e05e-40c3-a810-e0d8464b1080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775782375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.775782375
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3266607617
Short name T122
Test name
Test status
Simulation time 4092321064 ps
CPU time 173.88 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 213772 kb
Host smart-8a0049a8-907a-41d6-a9d2-74db92f43f99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266607617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3266607617
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.538476102
Short name T89
Test name
Test status
Simulation time 2439200803 ps
CPU time 40.3 seconds
Started Jul 24 04:58:09 PM PDT 24
Finished Jul 24 04:58:50 PM PDT 24
Peak memory 219116 kb
Host smart-52ec57ab-02d2-45f8-89fa-cc3f2ceae82c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538476102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.538476102
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2908781751
Short name T6
Test name
Test status
Simulation time 91352110412 ps
CPU time 100.23 seconds
Started Jul 24 04:57:33 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 220464 kb
Host smart-a051922b-70bb-4da9-b9f5-c02e02f4af4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908781751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2908781751
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.293007351
Short name T175
Test name
Test status
Simulation time 424919539351 ps
CPU time 801.91 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 05:10:33 PM PDT 24
Peak memory 239116 kb
Host smart-0c58ff01-30c7-431a-84f9-4ea2a05751f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293007351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.293007351
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3418198333
Short name T25
Test name
Test status
Simulation time 15338546246 ps
CPU time 62.93 seconds
Started Jul 24 04:56:52 PM PDT 24
Finished Jul 24 04:57:55 PM PDT 24
Peak memory 219316 kb
Host smart-9aa04714-0135-4895-930d-b77d1fba7fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418198333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3418198333
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1982334746
Short name T45
Test name
Test status
Simulation time 7372475797 ps
CPU time 58.27 seconds
Started Jul 24 04:57:17 PM PDT 24
Finished Jul 24 04:58:15 PM PDT 24
Peak memory 219304 kb
Host smart-df49a83d-a417-4109-8619-33991e0ea563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982334746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1982334746
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3486944936
Short name T224
Test name
Test status
Simulation time 32532430986 ps
CPU time 64.8 seconds
Started Jul 24 04:57:29 PM PDT 24
Finished Jul 24 04:58:34 PM PDT 24
Peak memory 219284 kb
Host smart-13b707ad-b210-41a9-a46c-a144f56bbf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486944936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3486944936
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2580885478
Short name T80
Test name
Test status
Simulation time 20632563210 ps
CPU time 88.94 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:56:52 PM PDT 24
Peak memory 214252 kb
Host smart-bea34d1e-8ce0-43a1-8467-8846b9cd09cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580885478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2580885478
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3243982463
Short name T117
Test name
Test status
Simulation time 19400539868 ps
CPU time 98.51 seconds
Started Jul 24 04:55:25 PM PDT 24
Finished Jul 24 04:57:04 PM PDT 24
Peak memory 213824 kb
Host smart-aee7a154-ec2d-46f4-a6db-fa2070c8ed2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243982463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3243982463
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3264217905
Short name T425
Test name
Test status
Simulation time 4552718474 ps
CPU time 78.58 seconds
Started Jul 24 04:55:02 PM PDT 24
Finished Jul 24 04:56:21 PM PDT 24
Peak memory 213784 kb
Host smart-d44e3c5b-2948-4dd9-a960-2077d4529df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264217905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3264217905
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1994142881
Short name T51
Test name
Test status
Simulation time 487995192 ps
CPU time 81.4 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:56:50 PM PDT 24
Peak memory 213388 kb
Host smart-ab3bd309-db9f-41d9-a1c9-96fe2bf6e00b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994142881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1994142881
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4104042356
Short name T93
Test name
Test status
Simulation time 11708741951 ps
CPU time 13.79 seconds
Started Jul 24 04:54:56 PM PDT 24
Finished Jul 24 04:55:10 PM PDT 24
Peak memory 211856 kb
Host smart-80f97f0e-5ca7-4fa6-a936-9276b8298ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104042356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4104042356
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3427031366
Short name T232
Test name
Test status
Simulation time 157351328893 ps
CPU time 106.69 seconds
Started Jul 24 04:57:04 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 220092 kb
Host smart-57adf77c-9ebf-4572-ab96-5ac8b9d06e94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427031366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3427031366
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2443848220
Short name T369
Test name
Test status
Simulation time 2920689567 ps
CPU time 23.63 seconds
Started Jul 24 04:55:11 PM PDT 24
Finished Jul 24 04:55:35 PM PDT 24
Peak memory 211428 kb
Host smart-c4d5e053-ac82-4d15-9745-319d9d8b0523
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443848220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2443848220
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.739072679
Short name T370
Test name
Test status
Simulation time 170852111 ps
CPU time 8.3 seconds
Started Jul 24 04:55:04 PM PDT 24
Finished Jul 24 04:55:12 PM PDT 24
Peak memory 210528 kb
Host smart-000b6694-ac70-4f8f-a73f-0d4730dedd06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739072679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.739072679
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.531730002
Short name T77
Test name
Test status
Simulation time 13149717496 ps
CPU time 31.38 seconds
Started Jul 24 04:55:01 PM PDT 24
Finished Jul 24 04:55:33 PM PDT 24
Peak memory 211808 kb
Host smart-87cf60c8-b81a-4fde-9710-a14823f92216
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531730002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.531730002
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3004492153
Short name T399
Test name
Test status
Simulation time 19402466759 ps
CPU time 32.04 seconds
Started Jul 24 04:55:05 PM PDT 24
Finished Jul 24 04:55:37 PM PDT 24
Peak memory 219024 kb
Host smart-4df7ea0e-6983-450b-8724-83c57abc249c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004492153 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3004492153
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1999657971
Short name T423
Test name
Test status
Simulation time 338669221 ps
CPU time 8.46 seconds
Started Jul 24 04:55:03 PM PDT 24
Finished Jul 24 04:55:12 PM PDT 24
Peak memory 210444 kb
Host smart-a8bf7ca4-e923-4de7-b70b-3a318562ab0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999657971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1999657971
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2441388363
Short name T452
Test name
Test status
Simulation time 3476907154 ps
CPU time 27.77 seconds
Started Jul 24 04:55:11 PM PDT 24
Finished Jul 24 04:55:39 PM PDT 24
Peak memory 210448 kb
Host smart-65d29eec-a34f-4465-93af-743caf4ac006
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441388363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2441388363
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.168301719
Short name T440
Test name
Test status
Simulation time 4339029927 ps
CPU time 30.65 seconds
Started Jul 24 04:55:15 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 210664 kb
Host smart-3ca69144-3185-48f8-9b9a-1e33d5203aeb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168301719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
168301719
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2184867265
Short name T96
Test name
Test status
Simulation time 22566591371 ps
CPU time 182.85 seconds
Started Jul 24 04:55:17 PM PDT 24
Finished Jul 24 04:58:21 PM PDT 24
Peak memory 215264 kb
Host smart-77790dd1-b98a-4115-8508-c6ef983e8c2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184867265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2184867265
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3101269129
Short name T400
Test name
Test status
Simulation time 34920561501 ps
CPU time 33.04 seconds
Started Jul 24 04:55:06 PM PDT 24
Finished Jul 24 04:55:39 PM PDT 24
Peak memory 212460 kb
Host smart-e4179035-eb55-4302-91e4-e8e41c331e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101269129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3101269129
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3481953970
Short name T433
Test name
Test status
Simulation time 395010331 ps
CPU time 15.63 seconds
Started Jul 24 04:55:05 PM PDT 24
Finished Jul 24 04:55:21 PM PDT 24
Peak memory 218404 kb
Host smart-107ce3c1-0c4e-4590-bb64-d320aef812ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481953970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3481953970
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.356157421
Short name T450
Test name
Test status
Simulation time 2735710520 ps
CPU time 165.55 seconds
Started Jul 24 04:55:08 PM PDT 24
Finished Jul 24 04:57:54 PM PDT 24
Peak memory 212664 kb
Host smart-228cc954-c395-46b9-b2d4-9a28c03305fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356157421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.356157421
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1195556096
Short name T403
Test name
Test status
Simulation time 18576569381 ps
CPU time 31.78 seconds
Started Jul 24 04:55:15 PM PDT 24
Finished Jul 24 04:55:47 PM PDT 24
Peak memory 211912 kb
Host smart-34e4aa0e-9f39-40f5-aeed-9f49831f0f67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195556096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1195556096
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.100765132
Short name T67
Test name
Test status
Simulation time 2203871011 ps
CPU time 12.73 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:55:34 PM PDT 24
Peak memory 210580 kb
Host smart-3cd141e1-2b73-4f81-8397-15be76292d14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100765132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.100765132
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3512529316
Short name T410
Test name
Test status
Simulation time 14237559768 ps
CPU time 36.7 seconds
Started Jul 24 04:55:06 PM PDT 24
Finished Jul 24 04:55:43 PM PDT 24
Peak memory 211704 kb
Host smart-f0955a56-a78e-4ac1-9424-f4d07778dd1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512529316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3512529316
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3129018552
Short name T420
Test name
Test status
Simulation time 354587749 ps
CPU time 8.79 seconds
Started Jul 24 04:55:05 PM PDT 24
Finished Jul 24 04:55:14 PM PDT 24
Peak memory 216816 kb
Host smart-a9770e14-5b36-4727-94e0-03079abeb5bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129018552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3129018552
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2911767606
Short name T364
Test name
Test status
Simulation time 1644801006 ps
CPU time 11.18 seconds
Started Jul 24 04:55:07 PM PDT 24
Finished Jul 24 04:55:18 PM PDT 24
Peak memory 210364 kb
Host smart-146fc4c3-a986-486d-b4b1-8425ce14ba0f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911767606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2911767606
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2830547587
Short name T409
Test name
Test status
Simulation time 5500819776 ps
CPU time 22.53 seconds
Started Jul 24 04:55:10 PM PDT 24
Finished Jul 24 04:55:33 PM PDT 24
Peak memory 210464 kb
Host smart-81d2675f-a147-4cab-91b8-f634ec997473
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830547587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2830547587
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3024894505
Short name T99
Test name
Test status
Simulation time 18275722129 ps
CPU time 160.88 seconds
Started Jul 24 04:55:06 PM PDT 24
Finished Jul 24 04:57:47 PM PDT 24
Peak memory 215208 kb
Host smart-a46040b8-1522-49aa-b37a-f776123ab2ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024894505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3024894505
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2457917575
Short name T411
Test name
Test status
Simulation time 3372626314 ps
CPU time 25.81 seconds
Started Jul 24 04:55:06 PM PDT 24
Finished Jul 24 04:55:32 PM PDT 24
Peak memory 212008 kb
Host smart-62d01304-4464-4d7b-b8af-0da6b042f268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457917575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2457917575
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.829613593
Short name T368
Test name
Test status
Simulation time 27550819104 ps
CPU time 33.52 seconds
Started Jul 24 04:55:13 PM PDT 24
Finished Jul 24 04:55:47 PM PDT 24
Peak memory 218728 kb
Host smart-19688133-4af9-4478-a28f-989348f89203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829613593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.829613593
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2246988379
Short name T52
Test name
Test status
Simulation time 3609040785 ps
CPU time 17.86 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 216268 kb
Host smart-78f08930-1df9-43ac-bb47-d1d8c7a5b353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246988379 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2246988379
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2437637141
Short name T100
Test name
Test status
Simulation time 1711690653 ps
CPU time 13.77 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:40 PM PDT 24
Peak memory 210456 kb
Host smart-a140c162-66fb-43b2-be3d-40bf4892c508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437637141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2437637141
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1675820764
Short name T386
Test name
Test status
Simulation time 19988180977 ps
CPU time 85.15 seconds
Started Jul 24 04:55:22 PM PDT 24
Finished Jul 24 04:56:48 PM PDT 24
Peak memory 214912 kb
Host smart-cba81de3-8c5e-443a-be24-584caac33229
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675820764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1675820764
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3818305336
Short name T392
Test name
Test status
Simulation time 4018407656 ps
CPU time 31.37 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:56:00 PM PDT 24
Peak memory 212008 kb
Host smart-a1a51b42-a6b9-4bd0-8fcc-b84144654f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818305336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3818305336
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.105494201
Short name T430
Test name
Test status
Simulation time 2515454528 ps
CPU time 25.82 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:55:44 PM PDT 24
Peak memory 218760 kb
Host smart-620d4b1f-ad11-409d-8c14-335d2016af79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105494201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.105494201
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3560275250
Short name T127
Test name
Test status
Simulation time 3411237373 ps
CPU time 166.82 seconds
Started Jul 24 04:55:19 PM PDT 24
Finished Jul 24 04:58:06 PM PDT 24
Peak memory 213776 kb
Host smart-db524392-a339-4741-9bbb-c228990e89c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560275250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3560275250
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2537536324
Short name T447
Test name
Test status
Simulation time 515845201 ps
CPU time 11.8 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:38 PM PDT 24
Peak memory 216444 kb
Host smart-b014a7c0-c5ca-4b6b-b264-7ef9d1f73caf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537536324 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2537536324
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2904548139
Short name T83
Test name
Test status
Simulation time 5623732906 ps
CPU time 23.15 seconds
Started Jul 24 04:55:25 PM PDT 24
Finished Jul 24 04:55:49 PM PDT 24
Peak memory 211848 kb
Host smart-4868a102-d1c9-4ce2-97f4-23f6768695ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904548139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2904548139
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.50816138
Short name T375
Test name
Test status
Simulation time 98717956437 ps
CPU time 194.25 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:58:33 PM PDT 24
Peak memory 215092 kb
Host smart-a214528c-cee6-4906-a99c-31c92302121d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50816138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pas
sthru_mem_tl_intg_err.50816138
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.860008549
Short name T108
Test name
Test status
Simulation time 660826967 ps
CPU time 8.09 seconds
Started Jul 24 04:55:25 PM PDT 24
Finished Jul 24 04:55:33 PM PDT 24
Peak memory 211392 kb
Host smart-a7e4fb79-4950-4d3d-a0df-b650d3d95139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860008549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.860008549
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3363515661
Short name T48
Test name
Test status
Simulation time 2346994056 ps
CPU time 26.13 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:55:54 PM PDT 24
Peak memory 218256 kb
Host smart-4b643db6-52ec-4389-9b42-6b10167c710c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363515661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3363515661
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3777861428
Short name T126
Test name
Test status
Simulation time 551467907 ps
CPU time 155.39 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:57:56 PM PDT 24
Peak memory 218704 kb
Host smart-530d027b-632e-4707-871c-d9b0dc748548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777861428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3777861428
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2933654855
Short name T379
Test name
Test status
Simulation time 373546867 ps
CPU time 9.67 seconds
Started Jul 24 04:55:16 PM PDT 24
Finished Jul 24 04:55:26 PM PDT 24
Peak memory 217580 kb
Host smart-b9781673-90e7-4ed9-918b-6763525ef86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933654855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2933654855
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1753755928
Short name T95
Test name
Test status
Simulation time 331948602 ps
CPU time 7.97 seconds
Started Jul 24 04:55:22 PM PDT 24
Finished Jul 24 04:55:30 PM PDT 24
Peak memory 210500 kb
Host smart-c5b918ac-6e80-46dd-a3da-491485185d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753755928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1753755928
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1781836027
Short name T109
Test name
Test status
Simulation time 9618524335 ps
CPU time 91.22 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:56:55 PM PDT 24
Peak memory 214184 kb
Host smart-4c765abf-5697-45b0-af5e-d82d587a5071
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781836027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1781836027
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3987565936
Short name T436
Test name
Test status
Simulation time 3771123880 ps
CPU time 20.5 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:55:45 PM PDT 24
Peak memory 211912 kb
Host smart-0cb427f6-977e-4a17-9604-5d10bf641c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987565936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3987565936
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4149846225
Short name T434
Test name
Test status
Simulation time 4205860741 ps
CPU time 35.43 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:56:05 PM PDT 24
Peak memory 218380 kb
Host smart-774c3f25-e8ee-496f-86eb-36af64a04b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149846225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4149846225
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.852220290
Short name T125
Test name
Test status
Simulation time 344215126 ps
CPU time 151.88 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:57:52 PM PDT 24
Peak memory 214872 kb
Host smart-2dddb356-093a-4c2c-a710-8396eba46054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852220290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.852220290
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1502216144
Short name T365
Test name
Test status
Simulation time 7940777605 ps
CPU time 20.27 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:55:48 PM PDT 24
Peak memory 216852 kb
Host smart-a207521b-67c7-4ed5-9085-df45b65d3f89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502216144 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1502216144
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.528052357
Short name T396
Test name
Test status
Simulation time 9777096045 ps
CPU time 23.49 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:55:45 PM PDT 24
Peak memory 212028 kb
Host smart-8cdc1c89-fdb5-4700-a257-dd2e81c4d235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528052357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.528052357
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2368277298
Short name T389
Test name
Test status
Simulation time 6714615120 ps
CPU time 17.69 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:44 PM PDT 24
Peak memory 211380 kb
Host smart-dbaf491a-64ef-496f-bd13-92621e1e8bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368277298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2368277298
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.641695250
Short name T371
Test name
Test status
Simulation time 4114934995 ps
CPU time 35.59 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:59 PM PDT 24
Peak memory 217940 kb
Host smart-4fd0d03e-0e3e-4178-9638-a083b8a459a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641695250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.641695250
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3434277647
Short name T441
Test name
Test status
Simulation time 836874741 ps
CPU time 9.01 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:37 PM PDT 24
Peak memory 216612 kb
Host smart-bdb3e3d9-118a-4042-af03-013d15637e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434277647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3434277647
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.535849321
Short name T110
Test name
Test status
Simulation time 332099598 ps
CPU time 7.94 seconds
Started Jul 24 04:55:22 PM PDT 24
Finished Jul 24 04:55:31 PM PDT 24
Peak memory 210396 kb
Host smart-527b98c8-bd93-4853-8516-0a5967be08e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535849321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.535849321
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3086926664
Short name T104
Test name
Test status
Simulation time 4136354394 ps
CPU time 56.42 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:56:23 PM PDT 24
Peak memory 215164 kb
Host smart-73688bcf-2ff1-431f-bc78-e43479da8de5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086926664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3086926664
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2576984933
Short name T398
Test name
Test status
Simulation time 10591441689 ps
CPU time 23.36 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:52 PM PDT 24
Peak memory 212568 kb
Host smart-223ffa9a-060d-410e-99f9-ddd5e7acd069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576984933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2576984933
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2420815148
Short name T437
Test name
Test status
Simulation time 3929115734 ps
CPU time 34.07 seconds
Started Jul 24 04:55:30 PM PDT 24
Finished Jul 24 04:56:05 PM PDT 24
Peak memory 217164 kb
Host smart-5ab5b1ff-d7b8-4f41-839f-dde693ecdf3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420815148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2420815148
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1879203722
Short name T427
Test name
Test status
Simulation time 186618875 ps
CPU time 8.33 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:55:33 PM PDT 24
Peak memory 213628 kb
Host smart-c16e18ee-6614-4d55-a30e-aaca1950f4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879203722 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1879203722
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2064921410
Short name T395
Test name
Test status
Simulation time 17805537471 ps
CPU time 31.7 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:56:01 PM PDT 24
Peak memory 211892 kb
Host smart-294bc55e-2907-487a-822e-f16e9377b17e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064921410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2064921410
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.882632857
Short name T76
Test name
Test status
Simulation time 10079082933 ps
CPU time 68.52 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:56:36 PM PDT 24
Peak memory 213712 kb
Host smart-a6a9dcdc-fe39-4242-9708-db4696cf42ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882632857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.882632857
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1540288022
Short name T78
Test name
Test status
Simulation time 24449737819 ps
CPU time 25.16 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:51 PM PDT 24
Peak memory 212508 kb
Host smart-d5f35107-d9c1-46ce-a784-14b61a46c8a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540288022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1540288022
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1615821686
Short name T366
Test name
Test status
Simulation time 10971688748 ps
CPU time 28.03 seconds
Started Jul 24 04:55:31 PM PDT 24
Finished Jul 24 04:55:59 PM PDT 24
Peak memory 218212 kb
Host smart-2f9edd7d-66b2-4f03-9019-4a946eb3eae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615821686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1615821686
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2889595704
Short name T123
Test name
Test status
Simulation time 5679373327 ps
CPU time 169.63 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:58:16 PM PDT 24
Peak memory 213920 kb
Host smart-9a2c3c23-74a9-4f59-ba24-22a02b0ca226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889595704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2889595704
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.678437269
Short name T449
Test name
Test status
Simulation time 12323888230 ps
CPU time 24.83 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:51 PM PDT 24
Peak memory 218040 kb
Host smart-aa8f739b-8797-41c7-89e5-ec75c14aab24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678437269 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.678437269
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2983705614
Short name T405
Test name
Test status
Simulation time 176006363 ps
CPU time 8.18 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:37 PM PDT 24
Peak memory 210688 kb
Host smart-11d4d2ec-bd96-440b-82ac-4ea3a550404a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983705614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2983705614
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2090436546
Short name T421
Test name
Test status
Simulation time 10677296092 ps
CPU time 91.62 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:56:59 PM PDT 24
Peak memory 214476 kb
Host smart-9dcffaba-5c19-4e75-8e8f-b4405c29b6e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090436546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2090436546
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3105057183
Short name T418
Test name
Test status
Simulation time 3158103738 ps
CPU time 15.75 seconds
Started Jul 24 04:55:30 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 210864 kb
Host smart-bf6fb1fe-14e1-4668-b7b5-75bf3e1c438c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105057183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3105057183
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1603829858
Short name T373
Test name
Test status
Simulation time 7913885224 ps
CPU time 24.03 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:52 PM PDT 24
Peak memory 217568 kb
Host smart-18c5b2d0-eda2-4f0c-bf4d-7d73273fdb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603829858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1603829858
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1904526678
Short name T121
Test name
Test status
Simulation time 497873469 ps
CPU time 153.67 seconds
Started Jul 24 04:55:31 PM PDT 24
Finished Jul 24 04:58:05 PM PDT 24
Peak memory 213856 kb
Host smart-65bc80c4-327a-4183-ad3e-8820f9ac3e38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904526678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1904526678
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.188352610
Short name T367
Test name
Test status
Simulation time 1806939730 ps
CPU time 19.45 seconds
Started Jul 24 04:55:34 PM PDT 24
Finished Jul 24 04:55:54 PM PDT 24
Peak memory 216788 kb
Host smart-6eedfc6a-b5e1-4439-b781-1db3dc556c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188352610 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.188352610
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3147001125
Short name T374
Test name
Test status
Simulation time 3668751285 ps
CPU time 28.75 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:55 PM PDT 24
Peak memory 211600 kb
Host smart-3ce10d09-5c0c-4f28-bca7-cf2b8fae00d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147001125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3147001125
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2135522144
Short name T74
Test name
Test status
Simulation time 15862708657 ps
CPU time 139.14 seconds
Started Jul 24 04:55:31 PM PDT 24
Finished Jul 24 04:57:50 PM PDT 24
Peak memory 215128 kb
Host smart-e78a3fe6-9238-466f-a35f-f09afd04d847
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135522144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2135522144
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1550483750
Short name T408
Test name
Test status
Simulation time 2310152216 ps
CPU time 16.68 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 211048 kb
Host smart-862bc459-7c09-4852-a19d-affc5082cea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550483750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1550483750
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2306407166
Short name T428
Test name
Test status
Simulation time 8185900072 ps
CPU time 24.33 seconds
Started Jul 24 04:55:32 PM PDT 24
Finished Jul 24 04:55:56 PM PDT 24
Peak memory 218728 kb
Host smart-8eb9a64b-d719-417b-ab8f-10cf574cb3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306407166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2306407166
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.531483768
Short name T376
Test name
Test status
Simulation time 2309174433 ps
CPU time 22.9 seconds
Started Jul 24 04:55:35 PM PDT 24
Finished Jul 24 04:55:58 PM PDT 24
Peak memory 217500 kb
Host smart-09c63894-dd5a-439c-bd38-0bbc0e67352a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531483768 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.531483768
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3979349845
Short name T397
Test name
Test status
Simulation time 13260469495 ps
CPU time 28.37 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:55:58 PM PDT 24
Peak memory 211744 kb
Host smart-f43edfa9-6ab0-42f6-86c4-7dcafb8ba4d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979349845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3979349845
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2087978276
Short name T393
Test name
Test status
Simulation time 2467303672 ps
CPU time 21.99 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:51 PM PDT 24
Peak memory 212036 kb
Host smart-0fe59fd7-2f9a-4381-bb32-09d0ff90c57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087978276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2087978276
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.113875582
Short name T50
Test name
Test status
Simulation time 174230147 ps
CPU time 11.21 seconds
Started Jul 24 04:55:30 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 216960 kb
Host smart-42ec1d81-8945-4fea-9d58-76e467bb5393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113875582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.113875582
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2647831715
Short name T419
Test name
Test status
Simulation time 6346626477 ps
CPU time 97.69 seconds
Started Jul 24 04:55:31 PM PDT 24
Finished Jul 24 04:57:09 PM PDT 24
Peak memory 213376 kb
Host smart-89905d0d-7b3a-4149-930c-f2674f68f20e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647831715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2647831715
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3473066762
Short name T443
Test name
Test status
Simulation time 6109143390 ps
CPU time 28.35 seconds
Started Jul 24 04:55:37 PM PDT 24
Finished Jul 24 04:56:06 PM PDT 24
Peak memory 216984 kb
Host smart-41f88f27-a458-49bb-8960-325273712024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473066762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3473066762
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1030041785
Short name T407
Test name
Test status
Simulation time 345653873 ps
CPU time 8.21 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:36 PM PDT 24
Peak memory 210764 kb
Host smart-109650a2-e253-42a9-bf9b-f01ea16b3491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030041785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1030041785
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3656818626
Short name T97
Test name
Test status
Simulation time 14896505704 ps
CPU time 140.28 seconds
Started Jul 24 04:55:30 PM PDT 24
Finished Jul 24 04:57:50 PM PDT 24
Peak memory 214184 kb
Host smart-21ffcb8e-f035-4baa-93d9-13bdc74da46a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656818626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3656818626
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2180952728
Short name T412
Test name
Test status
Simulation time 9466140015 ps
CPU time 22.7 seconds
Started Jul 24 04:55:32 PM PDT 24
Finished Jul 24 04:55:55 PM PDT 24
Peak memory 212516 kb
Host smart-936a2d86-1f33-455b-81c0-7ea609468296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180952728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2180952728
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1358692232
Short name T49
Test name
Test status
Simulation time 169238316 ps
CPU time 12.75 seconds
Started Jul 24 04:55:30 PM PDT 24
Finished Jul 24 04:55:43 PM PDT 24
Peak memory 217104 kb
Host smart-249d0b76-a2dd-4f63-9c6c-cc49c0257345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358692232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1358692232
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1568320364
Short name T62
Test name
Test status
Simulation time 3925423437 ps
CPU time 172.09 seconds
Started Jul 24 04:55:29 PM PDT 24
Finished Jul 24 04:58:22 PM PDT 24
Peak memory 213784 kb
Host smart-82f7a981-edd8-4a88-9d4f-ba501a39492b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568320364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1568320364
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3240925853
Short name T79
Test name
Test status
Simulation time 11349020503 ps
CPU time 20.79 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:55:42 PM PDT 24
Peak memory 211544 kb
Host smart-595e7227-af75-4ec9-82d9-98483750be4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240925853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3240925853
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3116899307
Short name T429
Test name
Test status
Simulation time 2422778858 ps
CPU time 21.79 seconds
Started Jul 24 04:55:14 PM PDT 24
Finished Jul 24 04:55:36 PM PDT 24
Peak memory 211452 kb
Host smart-443a9858-a2a3-4728-ad6a-5d4d0212b6f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116899307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3116899307
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1766919679
Short name T101
Test name
Test status
Simulation time 11277179350 ps
CPU time 26.82 seconds
Started Jul 24 04:55:04 PM PDT 24
Finished Jul 24 04:55:32 PM PDT 24
Peak memory 211792 kb
Host smart-1e181d49-97aa-4b01-80f4-2cee9f8de2b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766919679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1766919679
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.554315445
Short name T451
Test name
Test status
Simulation time 8942433878 ps
CPU time 22.31 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 218104 kb
Host smart-782380ae-7815-47c5-8ae9-d9246cea9971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554315445 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.554315445
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.681467299
Short name T102
Test name
Test status
Simulation time 12037680836 ps
CPU time 27.34 seconds
Started Jul 24 04:55:02 PM PDT 24
Finished Jul 24 04:55:30 PM PDT 24
Peak memory 211872 kb
Host smart-b4bc4562-adcc-4b77-a11c-2850de2afcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681467299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.681467299
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2529644251
Short name T414
Test name
Test status
Simulation time 174432459 ps
CPU time 7.76 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:55:26 PM PDT 24
Peak memory 210372 kb
Host smart-19496f37-72f3-4f77-85af-c7d8cd853535
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529644251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2529644251
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1216177477
Short name T413
Test name
Test status
Simulation time 40981285908 ps
CPU time 27.18 seconds
Started Jul 24 04:55:03 PM PDT 24
Finished Jul 24 04:55:31 PM PDT 24
Peak memory 210428 kb
Host smart-24a55431-e6ba-48d4-acad-25c78c134e7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216177477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1216177477
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.290865316
Short name T98
Test name
Test status
Simulation time 18361698157 ps
CPU time 90.96 seconds
Started Jul 24 04:55:17 PM PDT 24
Finished Jul 24 04:56:48 PM PDT 24
Peak memory 218828 kb
Host smart-dc582657-f02b-4d4d-bead-e4f2b8086ae6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290865316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.290865316
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2323963078
Short name T438
Test name
Test status
Simulation time 2060419143 ps
CPU time 8.05 seconds
Started Jul 24 04:55:14 PM PDT 24
Finished Jul 24 04:55:22 PM PDT 24
Peak memory 211168 kb
Host smart-7b9e0dd8-0363-4392-bbe3-363d4736a599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323963078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2323963078
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2685628192
Short name T439
Test name
Test status
Simulation time 1513160358 ps
CPU time 22.22 seconds
Started Jul 24 04:55:02 PM PDT 24
Finished Jul 24 04:55:24 PM PDT 24
Peak memory 218244 kb
Host smart-d971a917-e52d-4385-9429-08832b4f1dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685628192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2685628192
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3511402176
Short name T116
Test name
Test status
Simulation time 1727901124 ps
CPU time 87.61 seconds
Started Jul 24 04:55:09 PM PDT 24
Finished Jul 24 04:56:36 PM PDT 24
Peak memory 213504 kb
Host smart-3d0d0803-5926-4506-a239-56651caa6d79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511402176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3511402176
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1685753293
Short name T431
Test name
Test status
Simulation time 612709475 ps
CPU time 8.24 seconds
Started Jul 24 04:55:13 PM PDT 24
Finished Jul 24 04:55:21 PM PDT 24
Peak memory 210392 kb
Host smart-5fff303e-28a8-43c8-a52c-ef296d8eaceb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685753293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1685753293
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2147732653
Short name T66
Test name
Test status
Simulation time 1806486267 ps
CPU time 18.66 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:42 PM PDT 24
Peak memory 211612 kb
Host smart-d0bc846c-09cf-4f1b-bde1-bd039ea581ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147732653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2147732653
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1629618345
Short name T111
Test name
Test status
Simulation time 3960458801 ps
CPU time 37.18 seconds
Started Jul 24 04:55:04 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 211024 kb
Host smart-199259ce-ac29-46a6-b0bf-4cd049fd1ad3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629618345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1629618345
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2368293728
Short name T448
Test name
Test status
Simulation time 364916999 ps
CPU time 10.87 seconds
Started Jul 24 04:55:14 PM PDT 24
Finished Jul 24 04:55:25 PM PDT 24
Peak memory 215992 kb
Host smart-7aaa7df9-3d1e-42ef-8595-ad222a31fb20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368293728 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2368293728
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.650949399
Short name T453
Test name
Test status
Simulation time 3599117697 ps
CPU time 18.43 seconds
Started Jul 24 04:55:10 PM PDT 24
Finished Jul 24 04:55:29 PM PDT 24
Peak memory 211928 kb
Host smart-19d52f41-ac10-440e-8c94-4698a89ff05f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650949399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.650949399
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3631764142
Short name T363
Test name
Test status
Simulation time 1597070398 ps
CPU time 18.2 seconds
Started Jul 24 04:55:22 PM PDT 24
Finished Jul 24 04:55:40 PM PDT 24
Peak memory 210256 kb
Host smart-b6aeef6c-f097-41dc-97c4-a4665583927e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631764142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3631764142
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3490751209
Short name T415
Test name
Test status
Simulation time 12150245451 ps
CPU time 26.03 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:50 PM PDT 24
Peak memory 210760 kb
Host smart-b0a92e8a-adba-46cd-b778-335481d69714
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490751209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3490751209
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1845001894
Short name T388
Test name
Test status
Simulation time 11395651076 ps
CPU time 37.45 seconds
Started Jul 24 04:55:08 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 213888 kb
Host smart-0b214ee1-32b4-4ca4-b052-008a302c8a9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845001894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1845001894
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4037939697
Short name T107
Test name
Test status
Simulation time 352630443 ps
CPU time 8.24 seconds
Started Jul 24 04:55:12 PM PDT 24
Finished Jul 24 04:55:20 PM PDT 24
Peak memory 210604 kb
Host smart-ce78cabb-7f0c-45cb-b33c-91aa5f0ec93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037939697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4037939697
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2362396969
Short name T444
Test name
Test status
Simulation time 1175877520 ps
CPU time 18.26 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:55:38 PM PDT 24
Peak memory 218392 kb
Host smart-ccd54232-da53-4238-b806-998779513978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362396969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2362396969
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.679611218
Short name T120
Test name
Test status
Simulation time 14346002832 ps
CPU time 99.03 seconds
Started Jul 24 04:55:14 PM PDT 24
Finished Jul 24 04:56:53 PM PDT 24
Peak memory 212848 kb
Host smart-5e6601b7-308c-4752-8dec-ff4addbbe31f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679611218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.679611218
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3733090562
Short name T432
Test name
Test status
Simulation time 12609030412 ps
CPU time 21.18 seconds
Started Jul 24 04:55:15 PM PDT 24
Finished Jul 24 04:55:36 PM PDT 24
Peak memory 211920 kb
Host smart-e9c21310-a518-40ab-8ca9-73919d7467c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733090562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3733090562
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1273584880
Short name T92
Test name
Test status
Simulation time 7979323208 ps
CPU time 30.6 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:55:49 PM PDT 24
Peak memory 211596 kb
Host smart-2ab76e85-77ab-43b8-bc57-a378aacf5786
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273584880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1273584880
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2416170345
Short name T422
Test name
Test status
Simulation time 6301166863 ps
CPU time 28.86 seconds
Started Jul 24 04:55:08 PM PDT 24
Finished Jul 24 04:55:37 PM PDT 24
Peak memory 211472 kb
Host smart-469e9f31-67af-41c1-8dcd-927464bb63ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416170345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2416170345
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.325452739
Short name T378
Test name
Test status
Simulation time 30365362316 ps
CPU time 31.58 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:55:58 PM PDT 24
Peak memory 216516 kb
Host smart-771f10b3-690a-4f99-862b-418a348d0fad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325452739 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.325452739
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.653073825
Short name T81
Test name
Test status
Simulation time 1295990334 ps
CPU time 16.6 seconds
Started Jul 24 04:55:09 PM PDT 24
Finished Jul 24 04:55:25 PM PDT 24
Peak memory 211548 kb
Host smart-134d83a5-95c2-43b4-862f-ec896bb1d8ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653073825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.653073825
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2031204469
Short name T383
Test name
Test status
Simulation time 1356607920 ps
CPU time 16.2 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:55:37 PM PDT 24
Peak memory 210384 kb
Host smart-6a70b166-76ce-4a5d-89dc-4ef50986b28e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031204469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2031204469
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.480572963
Short name T384
Test name
Test status
Simulation time 231293317 ps
CPU time 8 seconds
Started Jul 24 04:55:03 PM PDT 24
Finished Jul 24 04:55:11 PM PDT 24
Peak memory 210360 kb
Host smart-8ca95c50-648c-4817-a62b-9cdaaa7c6049
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480572963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
480572963
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2807832626
Short name T103
Test name
Test status
Simulation time 88787200971 ps
CPU time 186.08 seconds
Started Jul 24 04:55:17 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 214860 kb
Host smart-791dfe5e-f5b3-4fb1-8d02-e809b1934a58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807832626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2807832626
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1368359917
Short name T402
Test name
Test status
Simulation time 582849138 ps
CPU time 11.73 seconds
Started Jul 24 04:55:07 PM PDT 24
Finished Jul 24 04:55:19 PM PDT 24
Peak memory 210804 kb
Host smart-bb5c3c4e-c01f-4dae-9445-5622b417aa26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368359917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1368359917
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3501877744
Short name T391
Test name
Test status
Simulation time 2055312364 ps
CPU time 16.05 seconds
Started Jul 24 04:55:15 PM PDT 24
Finished Jul 24 04:55:32 PM PDT 24
Peak memory 217224 kb
Host smart-f41a81f5-cbbb-4a95-9f9b-4a2883635f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501877744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3501877744
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1067409004
Short name T124
Test name
Test status
Simulation time 8064456832 ps
CPU time 164.11 seconds
Started Jul 24 04:55:06 PM PDT 24
Finished Jul 24 04:57:50 PM PDT 24
Peak memory 214232 kb
Host smart-12b97777-5af1-4f3a-9f7e-feac4bbc4e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067409004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1067409004
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3953472252
Short name T416
Test name
Test status
Simulation time 3471515281 ps
CPU time 26.83 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:55:47 PM PDT 24
Peak memory 216976 kb
Host smart-cb8b6afc-027f-4072-9cc4-a77e2985db07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953472252 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3953472252
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2734024587
Short name T82
Test name
Test status
Simulation time 189841050 ps
CPU time 8.15 seconds
Started Jul 24 04:55:20 PM PDT 24
Finished Jul 24 04:55:28 PM PDT 24
Peak memory 210544 kb
Host smart-955ade5f-e791-4082-9cce-6acc7bf9c4a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734024587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2734024587
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4022830162
Short name T387
Test name
Test status
Simulation time 122079739578 ps
CPU time 188.03 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:58:26 PM PDT 24
Peak memory 218864 kb
Host smart-9c42b245-851f-4318-a7a8-73c13d1cf0eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022830162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4022830162
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3481799211
Short name T106
Test name
Test status
Simulation time 2335643733 ps
CPU time 17 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 212284 kb
Host smart-043da3f4-84f6-43fc-8e58-569957862f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481799211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3481799211
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2579293546
Short name T380
Test name
Test status
Simulation time 64030918806 ps
CPU time 36.02 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:55:54 PM PDT 24
Peak memory 218632 kb
Host smart-3197cd7d-72a0-485b-9aa9-0a4c0b0cd9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579293546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2579293546
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4132294858
Short name T401
Test name
Test status
Simulation time 2216784951 ps
CPU time 93.3 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:56:57 PM PDT 24
Peak memory 213428 kb
Host smart-5ed07291-c9a1-46c9-b81d-7d6a4a877415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132294858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4132294858
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2854628278
Short name T442
Test name
Test status
Simulation time 4878465799 ps
CPU time 21.36 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:55:42 PM PDT 24
Peak memory 218408 kb
Host smart-7b0a966b-5519-40d2-a33c-a41d2e0fa0e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854628278 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2854628278
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1827531235
Short name T406
Test name
Test status
Simulation time 21554151259 ps
CPU time 28.45 seconds
Started Jul 24 04:55:24 PM PDT 24
Finished Jul 24 04:55:53 PM PDT 24
Peak memory 212096 kb
Host smart-d6826558-5044-4f00-b3a1-32e07b8364c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827531235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1827531235
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.784106597
Short name T445
Test name
Test status
Simulation time 56029507413 ps
CPU time 130.69 seconds
Started Jul 24 04:55:16 PM PDT 24
Finished Jul 24 04:57:27 PM PDT 24
Peak memory 215080 kb
Host smart-d436dca7-c0c4-436d-90f2-5c6a77a8666e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784106597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.784106597
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1484693438
Short name T446
Test name
Test status
Simulation time 167530294 ps
CPU time 8.6 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:55:27 PM PDT 24
Peak memory 211368 kb
Host smart-0a7e3779-79fc-4a5e-8585-b6a19b2eee24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484693438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1484693438
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3669476385
Short name T390
Test name
Test status
Simulation time 2557693736 ps
CPU time 28.57 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:57 PM PDT 24
Peak memory 218800 kb
Host smart-db7b95ec-a0cc-46b4-8ba7-49d33c9bcedf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669476385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3669476385
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3139495967
Short name T426
Test name
Test status
Simulation time 3875278397 ps
CPU time 90.22 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:56:51 PM PDT 24
Peak memory 213520 kb
Host smart-994577ea-335d-4022-b4db-4c4b484b6100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139495967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3139495967
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.78981772
Short name T372
Test name
Test status
Simulation time 16067107425 ps
CPU time 30.19 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:53 PM PDT 24
Peak memory 217536 kb
Host smart-5c005792-9874-46ab-8764-01da6e075780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78981772 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.78981772
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1365025442
Short name T417
Test name
Test status
Simulation time 14033129177 ps
CPU time 28.66 seconds
Started Jul 24 04:55:19 PM PDT 24
Finished Jul 24 04:55:48 PM PDT 24
Peak memory 211616 kb
Host smart-3b37a3a5-95df-4dd9-8275-ef806ca248fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365025442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1365025442
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1294073133
Short name T94
Test name
Test status
Simulation time 57577292758 ps
CPU time 118.77 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:57:22 PM PDT 24
Peak memory 213924 kb
Host smart-4cd1c374-3371-4129-9494-2c867e8c9190
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294073133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1294073133
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1193065086
Short name T424
Test name
Test status
Simulation time 3943415429 ps
CPU time 18.79 seconds
Started Jul 24 04:55:25 PM PDT 24
Finished Jul 24 04:55:44 PM PDT 24
Peak memory 211844 kb
Host smart-75c859bb-c8db-4293-b264-4cad6dc0547c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193065086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1193065086
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.644367128
Short name T73
Test name
Test status
Simulation time 2149899658 ps
CPU time 27.65 seconds
Started Jul 24 04:55:28 PM PDT 24
Finished Jul 24 04:55:56 PM PDT 24
Peak memory 217228 kb
Host smart-0b0a1f8d-e055-4c41-913c-db4afb9a36e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644367128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.644367128
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1266156065
Short name T385
Test name
Test status
Simulation time 672900947 ps
CPU time 12.98 seconds
Started Jul 24 04:55:26 PM PDT 24
Finished Jul 24 04:55:40 PM PDT 24
Peak memory 213724 kb
Host smart-76ee17c7-a72c-40d0-8900-26738e90fa4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266156065 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1266156065
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1605787220
Short name T382
Test name
Test status
Simulation time 338854771 ps
CPU time 8.08 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:31 PM PDT 24
Peak memory 210640 kb
Host smart-14138001-99c3-411f-9466-696ef54f5e10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605787220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1605787220
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1075568493
Short name T377
Test name
Test status
Simulation time 16105346044 ps
CPU time 130.7 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:57:31 PM PDT 24
Peak memory 213752 kb
Host smart-ac762dfc-3dc3-4b80-ac42-6cb9b92557a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075568493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1075568493
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1767837281
Short name T65
Test name
Test status
Simulation time 16455677524 ps
CPU time 31.26 seconds
Started Jul 24 04:55:17 PM PDT 24
Finished Jul 24 04:55:49 PM PDT 24
Peak memory 212396 kb
Host smart-61586987-f194-4872-ae1e-44e1bee34cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767837281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1767837281
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1717335068
Short name T435
Test name
Test status
Simulation time 2262991291 ps
CPU time 22.25 seconds
Started Jul 24 04:55:27 PM PDT 24
Finished Jul 24 04:55:49 PM PDT 24
Peak memory 218316 kb
Host smart-f7ada740-597c-4e77-bda3-225f0681e389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717335068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1717335068
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1817531586
Short name T63
Test name
Test status
Simulation time 4283291457 ps
CPU time 80.45 seconds
Started Jul 24 04:55:32 PM PDT 24
Finished Jul 24 04:56:53 PM PDT 24
Peak memory 213468 kb
Host smart-1b7ec9aa-b8f7-4a3a-8f04-d0c10fe44227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817531586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1817531586
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.135970837
Short name T381
Test name
Test status
Simulation time 5948630820 ps
CPU time 16.99 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 217300 kb
Host smart-7dfe73b2-44f4-417e-8f89-aeccef8f9c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135970837 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.135970837
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.917415116
Short name T404
Test name
Test status
Simulation time 14856700314 ps
CPU time 122.61 seconds
Started Jul 24 04:55:18 PM PDT 24
Finished Jul 24 04:57:20 PM PDT 24
Peak memory 213668 kb
Host smart-8d272987-919f-43a4-9251-51ef80ddc9f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917415116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.917415116
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.400257180
Short name T105
Test name
Test status
Simulation time 687698437 ps
CPU time 8.48 seconds
Started Jul 24 04:55:21 PM PDT 24
Finished Jul 24 04:55:30 PM PDT 24
Peak memory 210928 kb
Host smart-111a307c-c9c2-46d5-baff-39ea075cb777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400257180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.400257180
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1897263299
Short name T394
Test name
Test status
Simulation time 924734705 ps
CPU time 18.86 seconds
Started Jul 24 04:55:22 PM PDT 24
Finished Jul 24 04:55:41 PM PDT 24
Peak memory 218200 kb
Host smart-d0ed19e9-2098-4fa2-a7cc-fc683fbe38cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897263299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1897263299
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2858623224
Short name T118
Test name
Test status
Simulation time 4080297948 ps
CPU time 162.08 seconds
Started Jul 24 04:55:23 PM PDT 24
Finished Jul 24 04:58:06 PM PDT 24
Peak memory 213800 kb
Host smart-39d06bd6-402b-418a-8e8d-98dcf666a707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858623224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2858623224
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3590402546
Short name T216
Test name
Test status
Simulation time 2130872109 ps
CPU time 20.76 seconds
Started Jul 24 04:56:49 PM PDT 24
Finished Jul 24 04:57:10 PM PDT 24
Peak memory 217060 kb
Host smart-a8d8f5f6-c6df-42e5-8287-dfadbb0bba8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590402546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3590402546
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3922973060
Short name T342
Test name
Test status
Simulation time 110662834147 ps
CPU time 408.38 seconds
Started Jul 24 04:56:55 PM PDT 24
Finished Jul 24 05:03:43 PM PDT 24
Peak memory 235656 kb
Host smart-de9d44d2-f9fc-4e38-bbdd-187b8074a9fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922973060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3922973060
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1325801572
Short name T194
Test name
Test status
Simulation time 5982885856 ps
CPU time 54.04 seconds
Started Jul 24 04:56:57 PM PDT 24
Finished Jul 24 04:57:52 PM PDT 24
Peak memory 219308 kb
Host smart-0dcf77db-888f-42bc-951b-290cd9af8572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325801572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1325801572
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3608111236
Short name T135
Test name
Test status
Simulation time 176856943 ps
CPU time 10.35 seconds
Started Jul 24 04:56:57 PM PDT 24
Finished Jul 24 04:57:07 PM PDT 24
Peak memory 219244 kb
Host smart-832fba56-3fa5-4a0b-8c52-7d9d1e287a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608111236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3608111236
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2199594626
Short name T20
Test name
Test status
Simulation time 2425082522 ps
CPU time 129.44 seconds
Started Jul 24 04:57:01 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 239696 kb
Host smart-47994e36-2940-46d2-af27-f29ca7d5a932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199594626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2199594626
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.868371016
Short name T291
Test name
Test status
Simulation time 16483187110 ps
CPU time 83.22 seconds
Started Jul 24 04:56:53 PM PDT 24
Finished Jul 24 04:58:17 PM PDT 24
Peak memory 216716 kb
Host smart-0188d571-a8ce-4ece-b213-36a26aa87360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868371016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.868371016
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4085499655
Short name T272
Test name
Test status
Simulation time 515974391 ps
CPU time 33.18 seconds
Started Jul 24 04:56:59 PM PDT 24
Finished Jul 24 04:57:33 PM PDT 24
Peak memory 217580 kb
Host smart-4bb8f8c4-e627-4f10-9d04-a51a5a7b99ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085499655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4085499655
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.145701232
Short name T29
Test name
Test status
Simulation time 688474378 ps
CPU time 8.18 seconds
Started Jul 24 04:56:50 PM PDT 24
Finished Jul 24 04:56:59 PM PDT 24
Peak memory 217164 kb
Host smart-17457220-0222-4b6c-83cd-630fe09360a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145701232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.145701232
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.744477357
Short name T196
Test name
Test status
Simulation time 88496675603 ps
CPU time 401.7 seconds
Started Jul 24 04:56:52 PM PDT 24
Finished Jul 24 05:03:34 PM PDT 24
Peak memory 218764 kb
Host smart-a19602a5-babf-4ff0-9f55-06e69ab62a01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744477357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.744477357
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2027843313
Short name T197
Test name
Test status
Simulation time 695723038 ps
CPU time 10.19 seconds
Started Jul 24 04:56:51 PM PDT 24
Finished Jul 24 04:57:01 PM PDT 24
Peak memory 219160 kb
Host smart-4ee8e853-b278-4c6e-a917-9a3a1c93b9be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027843313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2027843313
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2880179603
Short name T26
Test name
Test status
Simulation time 59468845273 ps
CPU time 133.98 seconds
Started Jul 24 04:56:57 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 237720 kb
Host smart-cd03f4bc-21da-4c58-a8e8-12dddda1cd56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880179603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2880179603
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3445111894
Short name T184
Test name
Test status
Simulation time 5858660482 ps
CPU time 40.48 seconds
Started Jul 24 04:57:04 PM PDT 24
Finished Jul 24 04:57:44 PM PDT 24
Peak memory 215848 kb
Host smart-aee54927-0b59-4b86-a64b-01ca8d3c4981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445111894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3445111894
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4196187897
Short name T169
Test name
Test status
Simulation time 10788916755 ps
CPU time 24.23 seconds
Started Jul 24 04:57:09 PM PDT 24
Finished Jul 24 04:57:34 PM PDT 24
Peak memory 217388 kb
Host smart-b468cdff-5a1e-4cd4-8619-629871621f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196187897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4196187897
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.987741958
Short name T314
Test name
Test status
Simulation time 19082512867 ps
CPU time 47.3 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 218880 kb
Host smart-9d04e858-9d46-4bfa-9cd5-591f24bdec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987741958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.987741958
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2595404764
Short name T268
Test name
Test status
Simulation time 508144599 ps
CPU time 10.27 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:22 PM PDT 24
Peak memory 219308 kb
Host smart-d21d9442-9630-424a-bd44-6ae91f2b2c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595404764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2595404764
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2225152890
Short name T222
Test name
Test status
Simulation time 14210601327 ps
CPU time 44 seconds
Started Jul 24 04:57:12 PM PDT 24
Finished Jul 24 04:57:56 PM PDT 24
Peak memory 216616 kb
Host smart-66b65d99-bb03-4ba7-9e8e-a5f9039d6989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225152890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2225152890
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1406229274
Short name T241
Test name
Test status
Simulation time 36439345703 ps
CPU time 91.14 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 219360 kb
Host smart-eabad820-044d-455a-81c0-b8a7243c568f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406229274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1406229274
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3265454936
Short name T56
Test name
Test status
Simulation time 467553586818 ps
CPU time 603.67 seconds
Started Jul 24 04:57:03 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 224412 kb
Host smart-818b0988-2f86-4110-a72c-b947f7c0c2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265454936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3265454936
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2567767134
Short name T208
Test name
Test status
Simulation time 1395537541 ps
CPU time 26.2 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:38 PM PDT 24
Peak memory 219260 kb
Host smart-ca811c74-e5fc-400c-a317-149bf5998042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567767134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2567767134
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2692601551
Short name T61
Test name
Test status
Simulation time 1464134543 ps
CPU time 18.33 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:57:33 PM PDT 24
Peak memory 211256 kb
Host smart-7dcf36fb-cbed-4532-8708-c50712ea6852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692601551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2692601551
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3145625872
Short name T292
Test name
Test status
Simulation time 27132686343 ps
CPU time 46.64 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:58:02 PM PDT 24
Peak memory 216732 kb
Host smart-5e00e819-7d8a-419f-9a3a-f3b5f68d5efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145625872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3145625872
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1850067372
Short name T54
Test name
Test status
Simulation time 4740235955 ps
CPU time 62.84 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 04:58:13 PM PDT 24
Peak memory 219320 kb
Host smart-77a058e0-9360-479c-92e6-28d760853730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850067372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1850067372
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2205242461
Short name T46
Test name
Test status
Simulation time 374653890450 ps
CPU time 1828.8 seconds
Started Jul 24 04:57:14 PM PDT 24
Finished Jul 24 05:27:43 PM PDT 24
Peak memory 243912 kb
Host smart-5024943c-bae3-4be6-adf8-1df4187545d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205242461 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2205242461
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1768359988
Short name T340
Test name
Test status
Simulation time 4085993635 ps
CPU time 32.53 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:46 PM PDT 24
Peak memory 217064 kb
Host smart-b39900ce-1a67-4606-88ee-d5c3f169bae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768359988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1768359988
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.529705292
Short name T38
Test name
Test status
Simulation time 68607628518 ps
CPU time 440.3 seconds
Started Jul 24 04:57:18 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 240288 kb
Host smart-22e0a83a-d9a0-43f5-bc3b-cd608ef18da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529705292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.529705292
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1927047683
Short name T36
Test name
Test status
Simulation time 4855091275 ps
CPU time 47.16 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:58:02 PM PDT 24
Peak memory 219340 kb
Host smart-1095c0c5-5863-4997-b315-82ac70f8002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927047683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1927047683
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2663437247
Short name T174
Test name
Test status
Simulation time 721014574 ps
CPU time 10.38 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:57:26 PM PDT 24
Peak memory 219248 kb
Host smart-016a847a-620d-487d-894e-94b21b06b9b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663437247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2663437247
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2277335615
Short name T311
Test name
Test status
Simulation time 8526421484 ps
CPU time 74.63 seconds
Started Jul 24 04:57:14 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 217236 kb
Host smart-1cea8e8e-58de-42a3-b8bb-30a8895e0ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277335615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2277335615
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2864566225
Short name T334
Test name
Test status
Simulation time 15548169916 ps
CPU time 78.69 seconds
Started Jul 24 04:57:16 PM PDT 24
Finished Jul 24 04:58:35 PM PDT 24
Peak memory 227600 kb
Host smart-7e73508c-8226-4735-90d9-97eee38660dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864566225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2864566225
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4210010407
Short name T207
Test name
Test status
Simulation time 1979606497 ps
CPU time 18.73 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 04:57:34 PM PDT 24
Peak memory 217156 kb
Host smart-ad5faed6-d553-4570-b566-ae25463092ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210010407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4210010407
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4286449795
Short name T296
Test name
Test status
Simulation time 1306591213 ps
CPU time 100.49 seconds
Started Jul 24 04:57:04 PM PDT 24
Finished Jul 24 04:58:45 PM PDT 24
Peak memory 226392 kb
Host smart-260de72c-a3ec-4c72-947a-c4e8df69d8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286449795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4286449795
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3340397273
Short name T7
Test name
Test status
Simulation time 22719577742 ps
CPU time 39.52 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:53 PM PDT 24
Peak memory 219152 kb
Host smart-9657093f-74ad-4611-9217-cd016e20ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340397273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3340397273
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.116055501
Short name T299
Test name
Test status
Simulation time 5584087282 ps
CPU time 18.01 seconds
Started Jul 24 04:57:03 PM PDT 24
Finished Jul 24 04:57:21 PM PDT 24
Peak memory 211880 kb
Host smart-cc9f9480-c23c-48b0-83b1-b474e7d696da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116055501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.116055501
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3191906632
Short name T150
Test name
Test status
Simulation time 29448400959 ps
CPU time 242.83 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 05:01:14 PM PDT 24
Peak memory 222252 kb
Host smart-dcadc3e9-3bf8-4d5d-8e31-eb7f31330e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191906632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3191906632
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3343264175
Short name T236
Test name
Test status
Simulation time 487663798 ps
CPU time 8.15 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:57:51 PM PDT 24
Peak memory 217056 kb
Host smart-4dc505a0-91a1-446e-b396-f1abf761ee5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343264175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3343264175
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3960029551
Short name T39
Test name
Test status
Simulation time 12373713138 ps
CPU time 229.81 seconds
Started Jul 24 04:57:29 PM PDT 24
Finished Jul 24 05:01:19 PM PDT 24
Peak memory 234528 kb
Host smart-384a7368-e1cc-454e-95bc-d4b57e677069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960029551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3960029551
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1135984156
Short name T237
Test name
Test status
Simulation time 10909505520 ps
CPU time 37.12 seconds
Started Jul 24 04:57:17 PM PDT 24
Finished Jul 24 04:57:54 PM PDT 24
Peak memory 219148 kb
Host smart-e36b0f17-1d92-4a80-8b51-ea9fc976b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135984156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1135984156
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2771634992
Short name T161
Test name
Test status
Simulation time 1374723253 ps
CPU time 19.69 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:33 PM PDT 24
Peak memory 216620 kb
Host smart-af5b6e8d-ac52-4516-9568-366f97dea29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771634992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2771634992
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.870428960
Short name T338
Test name
Test status
Simulation time 30936787013 ps
CPU time 217.43 seconds
Started Jul 24 04:57:15 PM PDT 24
Finished Jul 24 05:00:52 PM PDT 24
Peak memory 221228 kb
Host smart-91b9cb92-097a-48fb-95a6-1a4ce1720146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870428960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.870428960
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1615566921
Short name T321
Test name
Test status
Simulation time 2404364330 ps
CPU time 22.44 seconds
Started Jul 24 04:57:31 PM PDT 24
Finished Jul 24 04:57:54 PM PDT 24
Peak memory 217208 kb
Host smart-4d1869de-542a-430a-8efa-fde5a6e8cd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615566921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1615566921
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.903076269
Short name T33
Test name
Test status
Simulation time 115414076211 ps
CPU time 603.58 seconds
Started Jul 24 04:57:34 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 234908 kb
Host smart-fa0741c8-e96e-43bc-bc88-5b638e5b28f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903076269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.903076269
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1397191289
Short name T218
Test name
Test status
Simulation time 4200412119 ps
CPU time 30.6 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:44 PM PDT 24
Peak memory 219328 kb
Host smart-9fc94ea3-231d-4abb-9123-ebf03a1b8896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397191289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1397191289
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1107678242
Short name T329
Test name
Test status
Simulation time 7056054715 ps
CPU time 67.06 seconds
Started Jul 24 04:57:16 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 216936 kb
Host smart-d966b9e6-787f-4641-878e-2429a9aad4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107678242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1107678242
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.285275460
Short name T284
Test name
Test status
Simulation time 9150924854 ps
CPU time 77.56 seconds
Started Jul 24 04:57:18 PM PDT 24
Finished Jul 24 04:58:36 PM PDT 24
Peak memory 217892 kb
Host smart-81a0cc24-2f25-4d9c-8be9-a49062e4a2ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285275460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.285275460
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.10803665
Short name T24
Test name
Test status
Simulation time 167496814 ps
CPU time 8.35 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:21 PM PDT 24
Peak memory 217124 kb
Host smart-b94fc336-4d30-4c25-9bd2-4ddfa3c08de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.10803665
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3111431692
Short name T153
Test name
Test status
Simulation time 6474817692 ps
CPU time 54.91 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:58:20 PM PDT 24
Peak memory 219356 kb
Host smart-eba788de-d0c9-4208-b529-bec3b638e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111431692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3111431692
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.104591819
Short name T131
Test name
Test status
Simulation time 224555115 ps
CPU time 10.35 seconds
Started Jul 24 04:57:19 PM PDT 24
Finished Jul 24 04:57:30 PM PDT 24
Peak memory 219200 kb
Host smart-70a79532-53e4-4326-bf52-974fc9220dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104591819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.104591819
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2128745229
Short name T325
Test name
Test status
Simulation time 349296090 ps
CPU time 19.89 seconds
Started Jul 24 04:57:16 PM PDT 24
Finished Jul 24 04:57:36 PM PDT 24
Peak memory 215840 kb
Host smart-c9ec25a6-7f11-4dc3-a415-181ebe13f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128745229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2128745229
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3137845045
Short name T358
Test name
Test status
Simulation time 2111467289 ps
CPU time 40.55 seconds
Started Jul 24 04:57:31 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 219332 kb
Host smart-5f064ecd-fdb7-4043-aaf7-25d03c517e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137845045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3137845045
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4098393180
Short name T34
Test name
Test status
Simulation time 13821086232 ps
CPU time 27.31 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:08 PM PDT 24
Peak memory 213308 kb
Host smart-aee8bc76-e9b7-4058-aeb8-eb3d145a50a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098393180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4098393180
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2217253492
Short name T333
Test name
Test status
Simulation time 806773711427 ps
CPU time 778.57 seconds
Started Jul 24 04:57:33 PM PDT 24
Finished Jul 24 05:10:32 PM PDT 24
Peak memory 219036 kb
Host smart-5d742b9d-360d-4327-949d-e2c2ebed99ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217253492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2217253492
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3299496892
Short name T316
Test name
Test status
Simulation time 7517444522 ps
CPU time 31.27 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:42 PM PDT 24
Peak memory 215592 kb
Host smart-1b089286-b401-4b17-b7e4-7dcf4a522160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299496892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3299496892
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.130730159
Short name T191
Test name
Test status
Simulation time 1408997903 ps
CPU time 12.55 seconds
Started Jul 24 04:57:35 PM PDT 24
Finished Jul 24 04:57:48 PM PDT 24
Peak memory 218752 kb
Host smart-fbca4395-0178-4e80-ab7a-a64a8a69697c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130730159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.130730159
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1299004297
Short name T88
Test name
Test status
Simulation time 2475621363 ps
CPU time 42.2 seconds
Started Jul 24 04:57:28 PM PDT 24
Finished Jul 24 04:58:11 PM PDT 24
Peak memory 216240 kb
Host smart-4d5c1be6-2175-41ae-b96a-2aa315971ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299004297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1299004297
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.709470004
Short name T261
Test name
Test status
Simulation time 51361089906 ps
CPU time 100.66 seconds
Started Jul 24 04:57:30 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 227512 kb
Host smart-b7935d35-be77-430b-8b6d-3c7bd5d8fa1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709470004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.709470004
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1485154830
Short name T47
Test name
Test status
Simulation time 157757631160 ps
CPU time 772.68 seconds
Started Jul 24 04:57:27 PM PDT 24
Finished Jul 24 05:10:20 PM PDT 24
Peak memory 235728 kb
Host smart-54492982-a356-4d33-9616-a5fa618dbf46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485154830 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1485154830
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4009891321
Short name T200
Test name
Test status
Simulation time 2797672031 ps
CPU time 17.8 seconds
Started Jul 24 04:57:27 PM PDT 24
Finished Jul 24 04:57:45 PM PDT 24
Peak memory 213264 kb
Host smart-c277e761-2505-4840-b425-49648ccdc275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009891321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4009891321
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2050862202
Short name T330
Test name
Test status
Simulation time 195911716855 ps
CPU time 501.1 seconds
Started Jul 24 04:57:28 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 227972 kb
Host smart-13cc1e99-b1d3-43ee-83b3-61a30f9abe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050862202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2050862202
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.125708526
Short name T178
Test name
Test status
Simulation time 14638473381 ps
CPU time 58.64 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 219312 kb
Host smart-1305571f-eb34-4398-bff3-fa419d3d183a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125708526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.125708526
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.208777462
Short name T134
Test name
Test status
Simulation time 12355009432 ps
CPU time 38.61 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:58:04 PM PDT 24
Peak memory 217684 kb
Host smart-032c50d6-0748-40ad-bd17-44d072b3db0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208777462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.208777462
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.565664975
Short name T305
Test name
Test status
Simulation time 3079073094 ps
CPU time 14.02 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:57:39 PM PDT 24
Peak memory 214508 kb
Host smart-5a8e39e8-a785-4cc3-9e9f-fc96e655bca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565664975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.565664975
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3826385270
Short name T72
Test name
Test status
Simulation time 25591780817 ps
CPU time 32.38 seconds
Started Jul 24 04:57:18 PM PDT 24
Finished Jul 24 04:57:51 PM PDT 24
Peak memory 213224 kb
Host smart-8e4cdba2-9487-4079-9d07-a7cde7dfbdb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826385270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3826385270
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1784104398
Short name T41
Test name
Test status
Simulation time 369519092748 ps
CPU time 498.8 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 216824 kb
Host smart-d2286600-4331-414a-8b8e-8dd5add59fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784104398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1784104398
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3582129502
Short name T249
Test name
Test status
Simulation time 933340886 ps
CPU time 16.32 seconds
Started Jul 24 04:57:19 PM PDT 24
Finished Jul 24 04:57:36 PM PDT 24
Peak memory 219208 kb
Host smart-f7789bc1-324a-428c-81a8-7f811a64f330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582129502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3582129502
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1011904693
Short name T137
Test name
Test status
Simulation time 1056485081 ps
CPU time 23.09 seconds
Started Jul 24 04:57:25 PM PDT 24
Finished Jul 24 04:57:48 PM PDT 24
Peak memory 216088 kb
Host smart-ebac095d-9705-497d-bbda-ec2ae48b9545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011904693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1011904693
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4286748867
Short name T283
Test name
Test status
Simulation time 5854173329 ps
CPU time 23.24 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:05 PM PDT 24
Peak memory 214644 kb
Host smart-9f0c8cb1-7aec-4cac-9a24-d96897c52e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286748867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4286748867
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1706048063
Short name T71
Test name
Test status
Simulation time 338774756 ps
CPU time 8.28 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 04:57:15 PM PDT 24
Peak memory 217020 kb
Host smart-6d3884d8-ad34-45a3-8c2e-4ca73a1a4887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706048063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1706048063
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.689712636
Short name T225
Test name
Test status
Simulation time 989523810241 ps
CPU time 541.99 seconds
Started Jul 24 04:56:54 PM PDT 24
Finished Jul 24 05:05:56 PM PDT 24
Peak memory 235236 kb
Host smart-7edc3954-b200-4509-9f63-e6449c70c6b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689712636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.689712636
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1230812348
Short name T44
Test name
Test status
Simulation time 637104571 ps
CPU time 19.14 seconds
Started Jul 24 04:56:52 PM PDT 24
Finished Jul 24 04:57:11 PM PDT 24
Peak memory 219308 kb
Host smart-993cca38-5a80-419c-a399-3b0b9e5bb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230812348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1230812348
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1270302581
Short name T251
Test name
Test status
Simulation time 2483936906 ps
CPU time 24.28 seconds
Started Jul 24 04:56:56 PM PDT 24
Finished Jul 24 04:57:20 PM PDT 24
Peak memory 219296 kb
Host smart-a0a4f7f4-b814-4f51-91da-946b328715bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270302581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1270302581
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3751713684
Short name T256
Test name
Test status
Simulation time 7285944324 ps
CPU time 45.89 seconds
Started Jul 24 04:56:53 PM PDT 24
Finished Jul 24 04:57:39 PM PDT 24
Peak memory 216540 kb
Host smart-06ce0cf0-b39d-4d24-a180-d2d335af50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751713684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3751713684
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1330162872
Short name T142
Test name
Test status
Simulation time 3740144588 ps
CPU time 42.75 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 04:57:53 PM PDT 24
Peak memory 216592 kb
Host smart-49c609f0-add9-4738-9c68-d4a9699b817a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330162872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1330162872
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3660263848
Short name T255
Test name
Test status
Simulation time 776916837 ps
CPU time 13.5 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:57:55 PM PDT 24
Peak memory 217004 kb
Host smart-815b4c8c-ee7a-4c17-aaa9-a2863a4aed6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660263848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3660263848
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3433177520
Short name T221
Test name
Test status
Simulation time 5818134382 ps
CPU time 102.9 seconds
Started Jul 24 04:57:20 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 228700 kb
Host smart-1840970a-8123-4b2a-baec-e422e12b4567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433177520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3433177520
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.212360685
Short name T345
Test name
Test status
Simulation time 13071117461 ps
CPU time 55.47 seconds
Started Jul 24 04:57:39 PM PDT 24
Finished Jul 24 04:58:35 PM PDT 24
Peak memory 219272 kb
Host smart-f8bf1062-141a-43e9-bb4d-948f36df8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212360685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.212360685
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.877786544
Short name T60
Test name
Test status
Simulation time 12922006229 ps
CPU time 21.05 seconds
Started Jul 24 04:57:39 PM PDT 24
Finished Jul 24 04:58:00 PM PDT 24
Peak memory 211940 kb
Host smart-a7ef6db8-547e-4af2-be10-5b6038041cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877786544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.877786544
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2010491384
Short name T155
Test name
Test status
Simulation time 12908767619 ps
CPU time 60.72 seconds
Started Jul 24 04:57:23 PM PDT 24
Finished Jul 24 04:58:24 PM PDT 24
Peak memory 216504 kb
Host smart-4ff80342-974f-42a2-85b4-ff36aa2bae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010491384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2010491384
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1885208255
Short name T245
Test name
Test status
Simulation time 1668824427 ps
CPU time 34.85 seconds
Started Jul 24 04:57:38 PM PDT 24
Finished Jul 24 04:58:13 PM PDT 24
Peak memory 216840 kb
Host smart-e853856c-f4e6-4e3e-bb3e-b9133edbea77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885208255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1885208255
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1283852628
Short name T53
Test name
Test status
Simulation time 3432076868 ps
CPU time 26.65 seconds
Started Jul 24 04:57:40 PM PDT 24
Finished Jul 24 04:58:06 PM PDT 24
Peak memory 217168 kb
Host smart-2f133beb-7a7e-4fec-8896-8ad2975ec149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283852628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1283852628
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1937953696
Short name T294
Test name
Test status
Simulation time 2403785678 ps
CPU time 151.08 seconds
Started Jul 24 04:57:37 PM PDT 24
Finished Jul 24 05:00:08 PM PDT 24
Peak memory 218864 kb
Host smart-8966f17c-1959-4031-8670-1a87383a59b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937953696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1937953696
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.914197162
Short name T229
Test name
Test status
Simulation time 1810163279 ps
CPU time 30.77 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:13 PM PDT 24
Peak memory 219232 kb
Host smart-e3b9216c-a63a-4583-8b11-ee37869fc18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914197162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.914197162
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2239962862
Short name T129
Test name
Test status
Simulation time 55815213536 ps
CPU time 29.52 seconds
Started Jul 24 04:57:35 PM PDT 24
Finished Jul 24 04:58:04 PM PDT 24
Peak memory 217868 kb
Host smart-373ba3b7-9af5-46f5-b92a-f6856528d78e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239962862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2239962862
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1595165827
Short name T273
Test name
Test status
Simulation time 1424564955 ps
CPU time 20.17 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:01 PM PDT 24
Peak memory 216336 kb
Host smart-3644d1f4-1cd9-4658-8c5e-ab9d19542134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595165827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1595165827
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2640994210
Short name T151
Test name
Test status
Simulation time 368228472 ps
CPU time 16.4 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:58:01 PM PDT 24
Peak memory 218952 kb
Host smart-7be0b33f-9c0c-4a0f-8e67-367f9374f794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640994210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2640994210
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.152576374
Short name T68
Test name
Test status
Simulation time 748680216 ps
CPU time 13.28 seconds
Started Jul 24 04:57:38 PM PDT 24
Finished Jul 24 04:57:52 PM PDT 24
Peak memory 213180 kb
Host smart-9a8fdd69-4b8a-4435-9755-d85d39df77c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152576374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.152576374
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2695266613
Short name T212
Test name
Test status
Simulation time 335215646097 ps
CPU time 835.79 seconds
Started Jul 24 04:57:40 PM PDT 24
Finished Jul 24 05:11:36 PM PDT 24
Peak memory 217776 kb
Host smart-df79f35d-a488-45ac-b32b-31b0b7fe135d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695266613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2695266613
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3871764243
Short name T239
Test name
Test status
Simulation time 5719296585 ps
CPU time 52.14 seconds
Started Jul 24 04:57:32 PM PDT 24
Finished Jul 24 04:58:24 PM PDT 24
Peak memory 219280 kb
Host smart-978e2dd7-8aed-4c04-b10a-ca50ac06bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871764243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3871764243
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2299440510
Short name T318
Test name
Test status
Simulation time 3029542365 ps
CPU time 19.43 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 211704 kb
Host smart-2d9fbf39-821b-41b6-95e1-a98dce406570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299440510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2299440510
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1841964339
Short name T275
Test name
Test status
Simulation time 15795128759 ps
CPU time 45.27 seconds
Started Jul 24 04:57:37 PM PDT 24
Finished Jul 24 04:58:22 PM PDT 24
Peak memory 217324 kb
Host smart-526bbacd-12ba-4e42-804d-a280c95854af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841964339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1841964339
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.245137243
Short name T35
Test name
Test status
Simulation time 1935791607 ps
CPU time 24.93 seconds
Started Jul 24 04:57:30 PM PDT 24
Finished Jul 24 04:57:56 PM PDT 24
Peak memory 219304 kb
Host smart-75a99bb1-2d7d-4641-8870-34f3e248016c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245137243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.245137243
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2078133704
Short name T361
Test name
Test status
Simulation time 3639763473 ps
CPU time 28.69 seconds
Started Jul 24 04:57:33 PM PDT 24
Finished Jul 24 04:58:02 PM PDT 24
Peak memory 217144 kb
Host smart-1ca953d5-87e7-46af-8909-07c4223f61f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078133704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2078133704
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1711034908
Short name T252
Test name
Test status
Simulation time 30016703856 ps
CPU time 332.22 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 05:03:14 PM PDT 24
Peak memory 219492 kb
Host smart-033ee7a8-140e-4d26-a421-69a5ccb46651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711034908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1711034908
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2514229983
Short name T9
Test name
Test status
Simulation time 19495606445 ps
CPU time 49.09 seconds
Started Jul 24 04:57:40 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 219340 kb
Host smart-20940a70-6136-42ab-85e8-66fe95ae23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514229983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2514229983
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2714666290
Short name T309
Test name
Test status
Simulation time 7576686200 ps
CPU time 21.81 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:58:06 PM PDT 24
Peak memory 219340 kb
Host smart-d2e98f5f-f9a2-408c-b5f9-6ca4eb9ed2ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714666290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2714666290
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1700975281
Short name T279
Test name
Test status
Simulation time 55362230942 ps
CPU time 73.92 seconds
Started Jul 24 04:57:26 PM PDT 24
Finished Jul 24 04:58:40 PM PDT 24
Peak memory 216828 kb
Host smart-d0b12680-1d39-4c85-a399-d1b7494ed242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700975281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1700975281
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.659209948
Short name T215
Test name
Test status
Simulation time 2894206661 ps
CPU time 46.82 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:58:30 PM PDT 24
Peak memory 219324 kb
Host smart-f06177aa-b314-453a-a5fb-0a01d379e77b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659209948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.659209948
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1840696653
Short name T307
Test name
Test status
Simulation time 11151086458 ps
CPU time 23.56 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:05 PM PDT 24
Peak memory 213200 kb
Host smart-1d76d22a-5c40-49ee-bd70-d2f3ad89caad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840696653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1840696653
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.708369791
Short name T58
Test name
Test status
Simulation time 33786292859 ps
CPU time 212.99 seconds
Started Jul 24 04:57:45 PM PDT 24
Finished Jul 24 05:01:18 PM PDT 24
Peak memory 228764 kb
Host smart-4af4465f-05ba-49cc-aeb2-632b0769d13b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708369791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.708369791
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.453013403
Short name T193
Test name
Test status
Simulation time 8430451321 ps
CPU time 69 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 219368 kb
Host smart-cf6ff9cb-64c3-4532-afc0-bc0a9f9c6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453013403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.453013403
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.19168012
Short name T213
Test name
Test status
Simulation time 7836512692 ps
CPU time 21.99 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 211748 kb
Host smart-d17b8604-b1a9-4a72-befe-270d2cfbee05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19168012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.19168012
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3231034265
Short name T17
Test name
Test status
Simulation time 7884321899 ps
CPU time 43.75 seconds
Started Jul 24 04:57:34 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 216888 kb
Host smart-c54423b6-4d31-48c6-a94e-e9bc08723aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231034265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3231034265
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.666652150
Short name T326
Test name
Test status
Simulation time 174532179 ps
CPU time 8.11 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:57:53 PM PDT 24
Peak memory 216976 kb
Host smart-830b3cbe-294a-4570-a6de-7657ee738eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666652150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.666652150
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3718881025
Short name T149
Test name
Test status
Simulation time 67615401070 ps
CPU time 269.09 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 05:02:10 PM PDT 24
Peak memory 224904 kb
Host smart-d32f5e8f-10d3-436c-a62b-5abf345c5412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718881025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3718881025
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2935714557
Short name T190
Test name
Test status
Simulation time 497736207 ps
CPU time 21.37 seconds
Started Jul 24 04:57:36 PM PDT 24
Finished Jul 24 04:57:58 PM PDT 24
Peak memory 219256 kb
Host smart-27b2483a-fe9f-4d0a-a6ce-a550b3f52a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935714557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2935714557
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4047030133
Short name T204
Test name
Test status
Simulation time 3163704926 ps
CPU time 26.64 seconds
Started Jul 24 04:57:39 PM PDT 24
Finished Jul 24 04:58:06 PM PDT 24
Peak memory 211320 kb
Host smart-dbdb5b65-f566-431d-b03f-882dc86f3b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047030133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4047030133
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.682031623
Short name T144
Test name
Test status
Simulation time 5436630349 ps
CPU time 56.76 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:38 PM PDT 24
Peak memory 216868 kb
Host smart-fab5ba1d-8606-40f9-bcfd-3fbf3dbd6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682031623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.682031623
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1421387385
Short name T315
Test name
Test status
Simulation time 4774378899 ps
CPU time 33.06 seconds
Started Jul 24 04:57:39 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 218052 kb
Host smart-5922aff4-a224-44fb-8c4c-6b3f1472e0e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421387385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1421387385
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3375422298
Short name T203
Test name
Test status
Simulation time 687961387 ps
CPU time 8.29 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:57:50 PM PDT 24
Peak memory 217120 kb
Host smart-c7a65f2e-6f0d-46b7-9278-8a2783a3ef5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375422298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3375422298
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1357369797
Short name T4
Test name
Test status
Simulation time 3156185433 ps
CPU time 160.08 seconds
Started Jul 24 04:57:49 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 238924 kb
Host smart-0faf7f4a-29f8-47f6-83e8-75cf24d291c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357369797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1357369797
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1607427896
Short name T170
Test name
Test status
Simulation time 10272633117 ps
CPU time 49.65 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:58:32 PM PDT 24
Peak memory 219372 kb
Host smart-dceb5489-4334-44d8-8a5c-f5fb324aa763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607427896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1607427896
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3808239294
Short name T138
Test name
Test status
Simulation time 2715666776 ps
CPU time 25.85 seconds
Started Jul 24 04:57:46 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 211248 kb
Host smart-cf50e7ba-e235-4531-9860-7ebdb8275acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808239294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3808239294
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.821473706
Short name T147
Test name
Test status
Simulation time 3607628246 ps
CPU time 44.92 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 04:58:46 PM PDT 24
Peak memory 215812 kb
Host smart-566525cb-1f3e-4ea0-abfa-3cb0dbfe8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821473706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.821473706
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1967731745
Short name T86
Test name
Test status
Simulation time 21744480311 ps
CPU time 35.61 seconds
Started Jul 24 04:57:40 PM PDT 24
Finished Jul 24 04:58:16 PM PDT 24
Peak memory 218592 kb
Host smart-c8e410d1-8cf4-4b33-88de-3241f56606d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967731745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1967731745
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1384336547
Short name T186
Test name
Test status
Simulation time 7005860578 ps
CPU time 29.41 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:58:14 PM PDT 24
Peak memory 216876 kb
Host smart-46df6f4e-4f5c-4fe3-a8b5-400caea24cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384336547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1384336547
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3778653413
Short name T286
Test name
Test status
Simulation time 2921972355 ps
CPU time 198.73 seconds
Started Jul 24 04:57:45 PM PDT 24
Finished Jul 24 05:01:04 PM PDT 24
Peak memory 229804 kb
Host smart-7db96335-e57e-4b31-99b8-30e4bc0285c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778653413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3778653413
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3115442644
Short name T199
Test name
Test status
Simulation time 8535298918 ps
CPU time 33.15 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:58:17 PM PDT 24
Peak memory 219388 kb
Host smart-ed9f49ae-ed1c-45e8-9d85-dd778dd68c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115442644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3115442644
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3668588124
Short name T180
Test name
Test status
Simulation time 18202337856 ps
CPU time 34.12 seconds
Started Jul 24 04:57:44 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 217652 kb
Host smart-d88f3c9d-ef13-42a6-9986-57ef6b424c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668588124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3668588124
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2846556522
Short name T133
Test name
Test status
Simulation time 19973072842 ps
CPU time 65.4 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 216572 kb
Host smart-8656f707-4753-4399-9869-c1db18751945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846556522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2846556522
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3883571205
Short name T348
Test name
Test status
Simulation time 400485894 ps
CPU time 21.05 seconds
Started Jul 24 04:57:41 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 217080 kb
Host smart-318ae2e6-fbb2-42fd-8713-c2b8b6a59735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883571205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3883571205
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2268110673
Short name T32
Test name
Test status
Simulation time 10635204513 ps
CPU time 23.45 seconds
Started Jul 24 04:57:46 PM PDT 24
Finished Jul 24 04:58:10 PM PDT 24
Peak memory 217216 kb
Host smart-40b6f188-e1b2-4de5-a1ff-aff1750fdf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268110673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2268110673
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3648451546
Short name T209
Test name
Test status
Simulation time 4100681034 ps
CPU time 281.17 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 05:02:24 PM PDT 24
Peak memory 239976 kb
Host smart-9de1e4a3-67dc-4f77-a391-57745cebf062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648451546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3648451546
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1731704591
Short name T198
Test name
Test status
Simulation time 3748562124 ps
CPU time 41.86 seconds
Started Jul 24 04:57:47 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 219296 kb
Host smart-d9ee9c35-ccd1-4aee-9d30-8b54f706aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731704591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1731704591
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2075917143
Short name T188
Test name
Test status
Simulation time 1057278339 ps
CPU time 11.65 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:57:54 PM PDT 24
Peak memory 211684 kb
Host smart-f565f6c7-2d35-4998-8cde-6b43afb19ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075917143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2075917143
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.675620156
Short name T168
Test name
Test status
Simulation time 2282427021 ps
CPU time 33.07 seconds
Started Jul 24 04:57:46 PM PDT 24
Finished Jul 24 04:58:19 PM PDT 24
Peak memory 216580 kb
Host smart-2401b9b9-201a-4c4e-83a0-721db687abbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675620156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.675620156
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2455389396
Short name T302
Test name
Test status
Simulation time 125156047174 ps
CPU time 238.73 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 05:01:43 PM PDT 24
Peak memory 222068 kb
Host smart-b58e2aa8-8add-4d91-a8a0-84470dc3ce69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455389396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2455389396
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.461445878
Short name T259
Test name
Test status
Simulation time 8501906568 ps
CPU time 21.18 seconds
Started Jul 24 04:57:50 PM PDT 24
Finished Jul 24 04:58:11 PM PDT 24
Peak memory 217480 kb
Host smart-69cc385c-65ff-483d-a9a4-7dcf05a01936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461445878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.461445878
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1365347986
Short name T220
Test name
Test status
Simulation time 36123758187 ps
CPU time 377.67 seconds
Started Jul 24 04:57:46 PM PDT 24
Finished Jul 24 05:04:04 PM PDT 24
Peak memory 236924 kb
Host smart-2a76f1f4-d718-4dae-a0d4-cb49d6644512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365347986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1365347986
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4246363602
Short name T357
Test name
Test status
Simulation time 14779383162 ps
CPU time 29.29 seconds
Started Jul 24 04:57:53 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 219276 kb
Host smart-ca06d1c0-ab73-4df9-833a-5871552f78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246363602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4246363602
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1444122730
Short name T112
Test name
Test status
Simulation time 6085237535 ps
CPU time 19.61 seconds
Started Jul 24 04:57:45 PM PDT 24
Finished Jul 24 04:58:05 PM PDT 24
Peak memory 211664 kb
Host smart-14eb9c3e-0d8c-4ae3-a45b-da45c003e86b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444122730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1444122730
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2961407748
Short name T113
Test name
Test status
Simulation time 2922788822 ps
CPU time 25.34 seconds
Started Jul 24 04:57:47 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 215796 kb
Host smart-c7d07547-b075-4a53-ac70-3e5860ec3c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961407748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2961407748
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2502379096
Short name T270
Test name
Test status
Simulation time 7333704647 ps
CPU time 83.18 seconds
Started Jul 24 04:57:49 PM PDT 24
Finished Jul 24 04:59:12 PM PDT 24
Peak memory 220656 kb
Host smart-c53e141a-8137-4aca-9dc1-3692d5f67467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502379096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2502379096
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2385875601
Short name T69
Test name
Test status
Simulation time 751165875 ps
CPU time 8.31 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 04:57:20 PM PDT 24
Peak memory 216872 kb
Host smart-25eb21c1-0f42-4a4b-bea3-e767116fea8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385875601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2385875601
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4265945853
Short name T328
Test name
Test status
Simulation time 140503148736 ps
CPU time 310.16 seconds
Started Jul 24 04:56:58 PM PDT 24
Finished Jul 24 05:02:09 PM PDT 24
Peak memory 239448 kb
Host smart-66d0dd30-eb13-4fe6-8082-77aebf49be49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265945853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4265945853
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4273517544
Short name T341
Test name
Test status
Simulation time 22817282979 ps
CPU time 51.1 seconds
Started Jul 24 04:57:01 PM PDT 24
Finished Jul 24 04:57:52 PM PDT 24
Peak memory 219328 kb
Host smart-6535840e-295a-489d-99a4-afa8bcf91f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273517544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4273517544
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1399243350
Short name T115
Test name
Test status
Simulation time 13692690980 ps
CPU time 30.19 seconds
Started Jul 24 04:57:01 PM PDT 24
Finished Jul 24 04:57:32 PM PDT 24
Peak memory 217876 kb
Host smart-a6f04e44-ac83-4f0c-a41a-fd9dab09d624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399243350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1399243350
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1689378999
Short name T22
Test name
Test status
Simulation time 8931489641 ps
CPU time 249.06 seconds
Started Jul 24 04:56:56 PM PDT 24
Finished Jul 24 05:01:05 PM PDT 24
Peak memory 236028 kb
Host smart-f647feef-55f9-4c52-91bb-17ece3f33af6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689378999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1689378999
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.940832868
Short name T267
Test name
Test status
Simulation time 360722802 ps
CPU time 20.42 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 04:57:33 PM PDT 24
Peak memory 216016 kb
Host smart-b015c25e-beb8-4c7c-bbf0-b4cdcce44c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940832868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.940832868
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.735281904
Short name T217
Test name
Test status
Simulation time 562235346 ps
CPU time 30.97 seconds
Started Jul 24 04:57:00 PM PDT 24
Finished Jul 24 04:57:32 PM PDT 24
Peak memory 217700 kb
Host smart-b0737646-3935-4e97-8b0d-9913ef8a1ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735281904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.735281904
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1871060129
Short name T181
Test name
Test status
Simulation time 689216999 ps
CPU time 8.45 seconds
Started Jul 24 04:57:49 PM PDT 24
Finished Jul 24 04:57:58 PM PDT 24
Peak memory 213224 kb
Host smart-25892088-53e2-490a-991a-12b84e89c3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871060129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1871060129
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.345361669
Short name T310
Test name
Test status
Simulation time 65218546753 ps
CPU time 514.47 seconds
Started Jul 24 04:57:52 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 239548 kb
Host smart-d77b436a-b4a1-41e0-9def-554df4156cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345361669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.345361669
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2643330603
Short name T337
Test name
Test status
Simulation time 335782938 ps
CPU time 18.5 seconds
Started Jul 24 04:57:45 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 219252 kb
Host smart-09792122-ba2f-4284-ba11-11d62185459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643330603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2643330603
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1597754717
Short name T352
Test name
Test status
Simulation time 2900790218 ps
CPU time 26.7 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 04:58:11 PM PDT 24
Peak memory 211304 kb
Host smart-62afefef-c147-4483-9745-5b76f39cb09f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597754717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1597754717
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2725267413
Short name T87
Test name
Test status
Simulation time 8730360782 ps
CPU time 52 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:46 PM PDT 24
Peak memory 216560 kb
Host smart-590b5d9e-4e33-45f8-89f2-2e16492a4a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725267413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2725267413
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2983221547
Short name T356
Test name
Test status
Simulation time 2938212248 ps
CPU time 38.96 seconds
Started Jul 24 04:57:52 PM PDT 24
Finished Jul 24 04:58:32 PM PDT 24
Peak memory 219604 kb
Host smart-a6bd7378-c7c8-4290-a3d5-31c0df09e37f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983221547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2983221547
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1698819853
Short name T262
Test name
Test status
Simulation time 2994309511 ps
CPU time 25.85 seconds
Started Jul 24 04:57:51 PM PDT 24
Finished Jul 24 04:58:17 PM PDT 24
Peak memory 217200 kb
Host smart-315f1715-45bd-4686-8808-79017d516ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698819853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1698819853
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1393868883
Short name T128
Test name
Test status
Simulation time 41484865798 ps
CPU time 427.12 seconds
Started Jul 24 04:57:45 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 236036 kb
Host smart-c9ea50d5-65e0-4e0f-b7e5-5cb4c8f63252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393868883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1393868883
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3052280371
Short name T227
Test name
Test status
Simulation time 3666014197 ps
CPU time 18.75 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 04:58:02 PM PDT 24
Peak memory 219320 kb
Host smart-94243146-7a08-440f-be79-e860ad2d7513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052280371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3052280371
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3774144856
Short name T343
Test name
Test status
Simulation time 672651361 ps
CPU time 10.24 seconds
Started Jul 24 04:57:43 PM PDT 24
Finished Jul 24 04:57:54 PM PDT 24
Peak memory 219300 kb
Host smart-aaedbb2e-f7c5-457a-a2a1-dffac99db7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774144856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3774144856
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2894825612
Short name T141
Test name
Test status
Simulation time 12710532046 ps
CPU time 64.19 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:58:47 PM PDT 24
Peak memory 216824 kb
Host smart-ad150af2-ed77-4a95-8050-120f39141e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894825612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2894825612
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4162090107
Short name T293
Test name
Test status
Simulation time 8545161234 ps
CPU time 90.53 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 04:59:28 PM PDT 24
Peak memory 218532 kb
Host smart-df1301d2-a8de-4f98-89d9-faf4e57f0987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162090107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4162090107
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1420885581
Short name T317
Test name
Test status
Simulation time 174458511 ps
CPU time 8.23 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 217016 kb
Host smart-1555d573-4d10-4089-90a7-b10865998d9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420885581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1420885581
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1786917521
Short name T306
Test name
Test status
Simulation time 164613155872 ps
CPU time 458.06 seconds
Started Jul 24 04:57:56 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 227952 kb
Host smart-fca122c1-869b-4aa3-9998-fea01a6bd1e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786917521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1786917521
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2526542898
Short name T263
Test name
Test status
Simulation time 8026714714 ps
CPU time 67.51 seconds
Started Jul 24 04:57:56 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 219280 kb
Host smart-695ed316-6b60-4540-b3fe-d40b2dcf824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526542898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2526542898
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.592166738
Short name T189
Test name
Test status
Simulation time 5612195049 ps
CPU time 29.69 seconds
Started Jul 24 04:57:59 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 217740 kb
Host smart-eb9e75c8-9e10-4544-ba4d-0576cbd76a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592166738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.592166738
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3124572112
Short name T165
Test name
Test status
Simulation time 3286154983 ps
CPU time 41.05 seconds
Started Jul 24 04:57:49 PM PDT 24
Finished Jul 24 04:58:30 PM PDT 24
Peak memory 215888 kb
Host smart-0bf0c765-985c-44f4-ba7c-5b75a8ce02b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124572112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3124572112
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1391119357
Short name T258
Test name
Test status
Simulation time 108308492751 ps
CPU time 170.95 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 219312 kb
Host smart-2e61fea6-2d93-48bc-9810-36cb54fcb0a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391119357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1391119357
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2216468029
Short name T145
Test name
Test status
Simulation time 169092115 ps
CPU time 8.07 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 217064 kb
Host smart-f1c3c5ff-d514-47e9-83d6-e2bad00cc9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216468029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2216468029
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2599060188
Short name T320
Test name
Test status
Simulation time 3024509530 ps
CPU time 204.82 seconds
Started Jul 24 04:57:47 PM PDT 24
Finished Jul 24 05:01:12 PM PDT 24
Peak memory 233916 kb
Host smart-ab05ee31-6d76-4bfd-a889-9f75fd4bc01a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599060188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2599060188
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3689818768
Short name T355
Test name
Test status
Simulation time 10470354365 ps
CPU time 36.91 seconds
Started Jul 24 04:57:48 PM PDT 24
Finished Jul 24 04:58:25 PM PDT 24
Peak memory 219144 kb
Host smart-e13b1928-9c3a-40e4-b3f9-094edd3daa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689818768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3689818768
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1692259293
Short name T246
Test name
Test status
Simulation time 13318994993 ps
CPU time 27.62 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:22 PM PDT 24
Peak memory 211744 kb
Host smart-60f7bfd7-8c1c-4019-a1c2-3d3c86e00015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692259293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1692259293
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.242599844
Short name T173
Test name
Test status
Simulation time 356432837 ps
CPU time 20.26 seconds
Started Jul 24 04:57:47 PM PDT 24
Finished Jul 24 04:58:08 PM PDT 24
Peak memory 216216 kb
Host smart-2ebcea1f-b475-4d8a-a571-865983cbc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242599844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.242599844
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.745903245
Short name T114
Test name
Test status
Simulation time 5722975648 ps
CPU time 19.05 seconds
Started Jul 24 04:57:53 PM PDT 24
Finished Jul 24 04:58:13 PM PDT 24
Peak memory 214864 kb
Host smart-e1458bc3-a2a2-467c-947c-e0365b2bfcd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745903245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.745903245
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.709689308
Short name T70
Test name
Test status
Simulation time 13083288513 ps
CPU time 30.67 seconds
Started Jul 24 04:57:51 PM PDT 24
Finished Jul 24 04:58:22 PM PDT 24
Peak memory 213244 kb
Host smart-f9374b5f-8eb7-44b5-bd94-716d3cbf8dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709689308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.709689308
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3278696814
Short name T166
Test name
Test status
Simulation time 519501438129 ps
CPU time 906.43 seconds
Started Jul 24 04:57:50 PM PDT 24
Finished Jul 24 05:12:57 PM PDT 24
Peak memory 237920 kb
Host smart-5c7810f9-f7ec-4e2c-bab7-8e982a751c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278696814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3278696814
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.718667711
Short name T205
Test name
Test status
Simulation time 342966802 ps
CPU time 19.04 seconds
Started Jul 24 04:57:58 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 219196 kb
Host smart-74345c09-b52e-4bba-8104-4af2082ada8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718667711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.718667711
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3887628118
Short name T64
Test name
Test status
Simulation time 516363716 ps
CPU time 13.68 seconds
Started Jul 24 04:58:00 PM PDT 24
Finished Jul 24 04:58:14 PM PDT 24
Peak memory 219244 kb
Host smart-9379c288-c1f9-4635-9b69-6d6f4862660a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887628118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3887628118
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3726424374
Short name T182
Test name
Test status
Simulation time 5132648773 ps
CPU time 50.29 seconds
Started Jul 24 04:57:52 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 215964 kb
Host smart-0b7e97c2-6d69-45b3-a5fb-06a21ee9c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726424374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3726424374
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.481823016
Short name T278
Test name
Test status
Simulation time 13325379585 ps
CPU time 58.28 seconds
Started Jul 24 04:57:52 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 217744 kb
Host smart-71c517d2-a417-4957-9a22-6bf562f3788b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481823016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.481823016
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1549979737
Short name T290
Test name
Test status
Simulation time 2043987558 ps
CPU time 19.94 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 213164 kb
Host smart-305f9627-f5fd-4a01-a99e-a8384ebb3baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549979737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1549979737
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4016758236
Short name T231
Test name
Test status
Simulation time 69094255807 ps
CPU time 241.91 seconds
Started Jul 24 04:57:47 PM PDT 24
Finished Jul 24 05:01:49 PM PDT 24
Peak memory 234992 kb
Host smart-d6fadeb5-893a-4288-9cff-8f84fa7364cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016758236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4016758236
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3597486699
Short name T210
Test name
Test status
Simulation time 8822780411 ps
CPU time 47.67 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 219384 kb
Host smart-489de8e8-b7b1-4524-876a-ad3e7b4ad9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597486699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3597486699
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1407230089
Short name T254
Test name
Test status
Simulation time 4473173429 ps
CPU time 13.77 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:09 PM PDT 24
Peak memory 219268 kb
Host smart-71da264f-697c-4204-ac6d-b5026c704308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407230089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1407230089
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.37395520
Short name T136
Test name
Test status
Simulation time 31432280578 ps
CPU time 61.18 seconds
Started Jul 24 04:57:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 216960 kb
Host smart-52c20ffb-c200-48e0-b85a-0598377607ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37395520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.37395520
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3265396235
Short name T347
Test name
Test status
Simulation time 9267231496 ps
CPU time 106.4 seconds
Started Jul 24 04:57:58 PM PDT 24
Finished Jul 24 04:59:45 PM PDT 24
Peak memory 219460 kb
Host smart-485ac799-73b2-4c1e-8fdc-2b647ed92425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265396235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3265396235
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.396359193
Short name T187
Test name
Test status
Simulation time 188012269 ps
CPU time 8.36 seconds
Started Jul 24 04:57:58 PM PDT 24
Finished Jul 24 04:58:07 PM PDT 24
Peak memory 217168 kb
Host smart-ab2e51ca-8f78-4b7e-8c35-553dae132c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396359193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.396359193
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3065362587
Short name T223
Test name
Test status
Simulation time 3015501238 ps
CPU time 109.33 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 240128 kb
Host smart-4a4eb531-3f28-46f6-8514-ed63db922711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065362587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3065362587
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.930646011
Short name T260
Test name
Test status
Simulation time 2016999901 ps
CPU time 33.22 seconds
Started Jul 24 04:57:55 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 219212 kb
Host smart-eec60f17-2a96-4e02-8311-3b4559d4cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930646011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.930646011
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.248937739
Short name T179
Test name
Test status
Simulation time 1088507843 ps
CPU time 10.59 seconds
Started Jul 24 04:58:04 PM PDT 24
Finished Jul 24 04:58:14 PM PDT 24
Peak memory 219296 kb
Host smart-34c49684-56d2-4c13-85d7-0e9b3e07dd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248937739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.248937739
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1765195048
Short name T349
Test name
Test status
Simulation time 5268090125 ps
CPU time 49.59 seconds
Started Jul 24 04:57:59 PM PDT 24
Finished Jul 24 04:58:49 PM PDT 24
Peak memory 216488 kb
Host smart-e656d729-abf9-4c0c-9412-320caacc1643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765195048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1765195048
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2171633444
Short name T164
Test name
Test status
Simulation time 23813105020 ps
CPU time 122.91 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 05:00:01 PM PDT 24
Peak memory 220796 kb
Host smart-51d00b27-4576-4fc0-a7bf-5d3064669e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171633444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2171633444
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3407177332
Short name T157
Test name
Test status
Simulation time 1022623705 ps
CPU time 15.21 seconds
Started Jul 24 04:57:48 PM PDT 24
Finished Jul 24 04:58:04 PM PDT 24
Peak memory 216992 kb
Host smart-51fbc4e2-ec21-43a5-bc93-5ace853f6f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407177332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3407177332
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3080313836
Short name T350
Test name
Test status
Simulation time 171320049705 ps
CPU time 895.35 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 05:12:56 PM PDT 24
Peak memory 225320 kb
Host smart-ede11b8d-52e1-4cfa-b7b9-de9e296c79a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080313836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3080313836
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2575925964
Short name T159
Test name
Test status
Simulation time 20417797147 ps
CPU time 50.48 seconds
Started Jul 24 04:57:52 PM PDT 24
Finished Jul 24 04:58:43 PM PDT 24
Peak memory 219276 kb
Host smart-23720a20-3527-4721-a425-003745409177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575925964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2575925964
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2630773673
Short name T171
Test name
Test status
Simulation time 29912191660 ps
CPU time 24.61 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:19 PM PDT 24
Peak memory 219368 kb
Host smart-b09acb43-a4a3-48ad-b5d6-ff7b4d163e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630773673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2630773673
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1202175887
Short name T2
Test name
Test status
Simulation time 1175239408 ps
CPU time 28.61 seconds
Started Jul 24 04:58:00 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 215600 kb
Host smart-2145d30e-8489-4c98-a1f4-019a53f153d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202175887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1202175887
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1347535510
Short name T354
Test name
Test status
Simulation time 63099042044 ps
CPU time 93.9 seconds
Started Jul 24 04:57:56 PM PDT 24
Finished Jul 24 04:59:30 PM PDT 24
Peak memory 217124 kb
Host smart-e12011e7-89ab-45de-b916-0a026651b9fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347535510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1347535510
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.774623217
Short name T248
Test name
Test status
Simulation time 3760849425 ps
CPU time 20.1 seconds
Started Jul 24 04:58:03 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 213268 kb
Host smart-99f51cc8-7d41-4552-84b2-2dda93af1665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774623217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.774623217
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1801767238
Short name T28
Test name
Test status
Simulation time 154407797928 ps
CPU time 430.51 seconds
Started Jul 24 04:57:51 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 233812 kb
Host smart-730ff77e-13b1-4779-b3fa-2456994353f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801767238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1801767238
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3341725022
Short name T285
Test name
Test status
Simulation time 11065732129 ps
CPU time 54.74 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 04:58:56 PM PDT 24
Peak memory 216888 kb
Host smart-3b79871e-c7fd-47af-915e-62c29446cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341725022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3341725022
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2890777360
Short name T172
Test name
Test status
Simulation time 7160074791 ps
CPU time 29.57 seconds
Started Jul 24 04:57:56 PM PDT 24
Finished Jul 24 04:58:26 PM PDT 24
Peak memory 219388 kb
Host smart-f53e6940-4d34-4245-8a2c-d98faa6b8303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890777360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2890777360
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3690203288
Short name T360
Test name
Test status
Simulation time 4970581006 ps
CPU time 54.18 seconds
Started Jul 24 04:57:53 PM PDT 24
Finished Jul 24 04:58:48 PM PDT 24
Peak memory 215660 kb
Host smart-434b29a2-7fc8-4ec0-a329-69e97002d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690203288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3690203288
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.270723033
Short name T277
Test name
Test status
Simulation time 5639373776 ps
CPU time 34.85 seconds
Started Jul 24 04:58:00 PM PDT 24
Finished Jul 24 04:58:35 PM PDT 24
Peak memory 219188 kb
Host smart-8d80bc75-ae1c-436f-9894-54a901d4de30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270723033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.270723033
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3166921253
Short name T152
Test name
Test status
Simulation time 1968864975 ps
CPU time 11.95 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:07 PM PDT 24
Peak memory 213172 kb
Host smart-2e13bbf2-7e86-4188-a3c7-5faf44aeda3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166921253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3166921253
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2886008646
Short name T59
Test name
Test status
Simulation time 103406342019 ps
CPU time 328.71 seconds
Started Jul 24 04:58:05 PM PDT 24
Finished Jul 24 05:03:34 PM PDT 24
Peak memory 216712 kb
Host smart-a2f4f4d1-2d6c-45d1-8cc5-7842ad2a0022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886008646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2886008646
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4103853998
Short name T280
Test name
Test status
Simulation time 35417495485 ps
CPU time 70.94 seconds
Started Jul 24 04:58:03 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 219232 kb
Host smart-275202fe-7176-40dd-95c1-c7aed523cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103853998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4103853998
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.579791025
Short name T176
Test name
Test status
Simulation time 5109110858 ps
CPU time 25.48 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 04:58:27 PM PDT 24
Peak memory 219420 kb
Host smart-524421bb-0359-4992-83f4-79f1f4868b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579791025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.579791025
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.155461375
Short name T351
Test name
Test status
Simulation time 5488171303 ps
CPU time 55.72 seconds
Started Jul 24 04:57:58 PM PDT 24
Finished Jul 24 04:58:54 PM PDT 24
Peak memory 216124 kb
Host smart-f87dd2b4-ffe4-4671-9f47-33b1326acea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155461375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.155461375
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3496446632
Short name T140
Test name
Test status
Simulation time 33347640521 ps
CPU time 105.69 seconds
Started Jul 24 04:57:57 PM PDT 24
Finished Jul 24 04:59:43 PM PDT 24
Peak memory 219360 kb
Host smart-1aaa78e5-cd48-4cf0-81a1-163dd21f9c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496446632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3496446632
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1339275376
Short name T148
Test name
Test status
Simulation time 8103701539 ps
CPU time 32.22 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:43 PM PDT 24
Peak memory 217376 kb
Host smart-27a8a33b-81c0-4974-b9ff-ec1081e53989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339275376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1339275376
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2704209897
Short name T289
Test name
Test status
Simulation time 119822797279 ps
CPU time 556.55 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 233852 kb
Host smart-23f4c895-cd3c-44cd-ad5b-c83255100d6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704209897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2704209897
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3295893857
Short name T158
Test name
Test status
Simulation time 9227571338 ps
CPU time 46.14 seconds
Started Jul 24 04:57:04 PM PDT 24
Finished Jul 24 04:57:50 PM PDT 24
Peak memory 219392 kb
Host smart-c053d41c-4353-4f92-ba53-164c0a3f8026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295893857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3295893857
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.428205596
Short name T235
Test name
Test status
Simulation time 959317020 ps
CPU time 16.03 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 04:57:27 PM PDT 24
Peak memory 218288 kb
Host smart-40caad2a-215b-4245-94c9-557b851f75be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428205596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.428205596
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.124321643
Short name T27
Test name
Test status
Simulation time 70540288930 ps
CPU time 139.82 seconds
Started Jul 24 04:57:12 PM PDT 24
Finished Jul 24 04:59:32 PM PDT 24
Peak memory 238476 kb
Host smart-77da66f4-f613-4aa7-9b5c-4a4e9a20eb1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124321643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.124321643
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3585778711
Short name T91
Test name
Test status
Simulation time 26708757089 ps
CPU time 72.19 seconds
Started Jul 24 04:57:02 PM PDT 24
Finished Jul 24 04:58:14 PM PDT 24
Peak memory 216776 kb
Host smart-1ee896ec-6a36-4749-9cc5-53d07dec61f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585778711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3585778711
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1774236658
Short name T287
Test name
Test status
Simulation time 8412883378 ps
CPU time 74.27 seconds
Started Jul 24 04:57:03 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 219264 kb
Host smart-05a71870-b193-4d07-80a3-127cb2bfc9d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774236658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1774236658
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.61963639
Short name T324
Test name
Test status
Simulation time 2376185158 ps
CPU time 22.43 seconds
Started Jul 24 04:58:05 PM PDT 24
Finished Jul 24 04:58:27 PM PDT 24
Peak memory 213216 kb
Host smart-ddee1d5f-6f19-4307-abec-b4b46f3f4b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61963639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.61963639
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3781900853
Short name T335
Test name
Test status
Simulation time 36501173075 ps
CPU time 396.67 seconds
Started Jul 24 04:58:03 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 219548 kb
Host smart-294125ec-0338-4146-98df-92e6a8594813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781900853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3781900853
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3390850821
Short name T264
Test name
Test status
Simulation time 63389148103 ps
CPU time 47.22 seconds
Started Jul 24 04:57:55 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 219332 kb
Host smart-519d57b2-7b40-4cc6-8cbe-6cf646ce5617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390850821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3390850821
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.162811871
Short name T13
Test name
Test status
Simulation time 2773810886 ps
CPU time 15.21 seconds
Started Jul 24 04:58:08 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 218596 kb
Host smart-e1d62f5c-d604-4c8e-a2cd-c99f5b1d9da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162811871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.162811871
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.99849554
Short name T276
Test name
Test status
Simulation time 32872188110 ps
CPU time 75.83 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 217292 kb
Host smart-65c4ce75-e6ff-4f2d-92c4-32d3da7f8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99849554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.99849554
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1798315540
Short name T295
Test name
Test status
Simulation time 4285083665 ps
CPU time 41.78 seconds
Started Jul 24 04:57:54 PM PDT 24
Finished Jul 24 04:58:36 PM PDT 24
Peak memory 219124 kb
Host smart-368ea5c4-2186-46dc-a67d-8867f9e94a45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798315540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1798315540
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.568865782
Short name T313
Test name
Test status
Simulation time 8571666491 ps
CPU time 30.73 seconds
Started Jul 24 04:57:59 PM PDT 24
Finished Jul 24 04:58:30 PM PDT 24
Peak memory 217492 kb
Host smart-9229b0d0-3c3a-423b-850f-a9745ece8130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568865782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.568865782
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3103125129
Short name T42
Test name
Test status
Simulation time 58211063168 ps
CPU time 493.04 seconds
Started Jul 24 04:58:08 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 226688 kb
Host smart-69b27e63-3bb8-4f6b-a7a3-48685dd21724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103125129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3103125129
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3464273698
Short name T288
Test name
Test status
Simulation time 7515164103 ps
CPU time 58.15 seconds
Started Jul 24 04:58:06 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 219284 kb
Host smart-c63a68c9-d0aa-478d-adc9-a1e5657e7078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464273698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3464273698
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2586737511
Short name T177
Test name
Test status
Simulation time 4608205962 ps
CPU time 17.23 seconds
Started Jul 24 04:57:55 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 219304 kb
Host smart-b350c46f-2dc0-4e63-a00e-cfbab313ba4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586737511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2586737511
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2758147639
Short name T154
Test name
Test status
Simulation time 3134147985 ps
CPU time 39.82 seconds
Started Jul 24 04:58:00 PM PDT 24
Finished Jul 24 04:58:40 PM PDT 24
Peak memory 216572 kb
Host smart-c166d12c-e92c-49b4-8c1b-64bdfdab3ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758147639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2758147639
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4234149170
Short name T30
Test name
Test status
Simulation time 32746199964 ps
CPU time 89.91 seconds
Started Jul 24 04:58:01 PM PDT 24
Finished Jul 24 04:59:32 PM PDT 24
Peak memory 219280 kb
Host smart-c43780a4-987f-4830-a5d8-7fc85da33091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234149170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4234149170
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4158435787
Short name T201
Test name
Test status
Simulation time 9029142953 ps
CPU time 19.54 seconds
Started Jul 24 04:58:09 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 217392 kb
Host smart-7a65ee66-fded-4ff0-924b-938ec6d16f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158435787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4158435787
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2306621458
Short name T344
Test name
Test status
Simulation time 4453626979 ps
CPU time 298.59 seconds
Started Jul 24 04:58:07 PM PDT 24
Finished Jul 24 05:03:06 PM PDT 24
Peak memory 226300 kb
Host smart-80db37f0-c115-4b77-a579-05d52e94d24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306621458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2306621458
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4198387980
Short name T339
Test name
Test status
Simulation time 6014355068 ps
CPU time 55.08 seconds
Started Jul 24 04:58:03 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 219372 kb
Host smart-dc3a952d-fc45-442b-accb-909fb7c1fdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198387980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4198387980
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3472735200
Short name T130
Test name
Test status
Simulation time 821462914 ps
CPU time 10.13 seconds
Started Jul 24 04:58:05 PM PDT 24
Finished Jul 24 04:58:15 PM PDT 24
Peak memory 219308 kb
Host smart-da17d5ae-bcfb-4982-bd4d-08d9b77d5a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472735200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3472735200
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4200175980
Short name T163
Test name
Test status
Simulation time 9488923545 ps
CPU time 16.87 seconds
Started Jul 24 04:58:06 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 213336 kb
Host smart-3c590537-476c-4f2a-aa02-aa0b8f0dc22b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200175980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4200175980
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2952062902
Short name T206
Test name
Test status
Simulation time 144647092020 ps
CPU time 207.17 seconds
Started Jul 24 04:58:09 PM PDT 24
Finished Jul 24 05:01:36 PM PDT 24
Peak memory 238400 kb
Host smart-786cf04d-7c01-43fa-8b2e-6ee983095e2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952062902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2952062902
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3536066908
Short name T257
Test name
Test status
Simulation time 98379251886 ps
CPU time 66.66 seconds
Started Jul 24 04:58:07 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 219292 kb
Host smart-857ff93d-d402-4eba-be72-7adc983dc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536066908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3536066908
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2060682949
Short name T219
Test name
Test status
Simulation time 1130828541 ps
CPU time 17.53 seconds
Started Jul 24 04:58:10 PM PDT 24
Finished Jul 24 04:58:28 PM PDT 24
Peak memory 219336 kb
Host smart-c6517ed5-e28c-452f-9f6c-bffd9c70911e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060682949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2060682949
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.582465749
Short name T84
Test name
Test status
Simulation time 2304831317 ps
CPU time 32.33 seconds
Started Jul 24 04:58:03 PM PDT 24
Finished Jul 24 04:58:35 PM PDT 24
Peak memory 216160 kb
Host smart-7a305dc5-10af-490a-bd7b-b0d98a152ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582465749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.582465749
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.752481255
Short name T298
Test name
Test status
Simulation time 2323880626 ps
CPU time 21.67 seconds
Started Jul 24 04:58:13 PM PDT 24
Finished Jul 24 04:58:34 PM PDT 24
Peak memory 217124 kb
Host smart-63940826-5300-43cf-8654-f6e64b21ab0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752481255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.752481255
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2988687590
Short name T281
Test name
Test status
Simulation time 31246271176 ps
CPU time 273.93 seconds
Started Jul 24 04:58:08 PM PDT 24
Finished Jul 24 05:02:42 PM PDT 24
Peak memory 219480 kb
Host smart-4744c003-2680-42dd-b8a3-363685e8412c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988687590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2988687590
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2560320053
Short name T160
Test name
Test status
Simulation time 29348708714 ps
CPU time 61.07 seconds
Started Jul 24 04:58:11 PM PDT 24
Finished Jul 24 04:59:12 PM PDT 24
Peak memory 219324 kb
Host smart-a2e4578a-44fe-48cd-91fc-9cf6b96bd253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560320053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2560320053
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1794293513
Short name T183
Test name
Test status
Simulation time 22726753984 ps
CPU time 26.41 seconds
Started Jul 24 04:58:07 PM PDT 24
Finished Jul 24 04:58:34 PM PDT 24
Peak memory 219268 kb
Host smart-dbf21f57-888f-4a4f-9691-9cfb3c6fd267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794293513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1794293513
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1102981271
Short name T346
Test name
Test status
Simulation time 9111168753 ps
CPU time 31.37 seconds
Started Jul 24 04:58:06 PM PDT 24
Finished Jul 24 04:58:37 PM PDT 24
Peak memory 215920 kb
Host smart-fd1b6dc5-fffb-4bd3-b439-f71cbef16a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102981271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1102981271
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1420839408
Short name T327
Test name
Test status
Simulation time 80123413751 ps
CPU time 95.83 seconds
Started Jul 24 04:58:05 PM PDT 24
Finished Jul 24 04:59:41 PM PDT 24
Peak memory 217632 kb
Host smart-04078662-2508-43ea-a5e4-3d2921bb4b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420839408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1420839408
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.449852776
Short name T211
Test name
Test status
Simulation time 939572794 ps
CPU time 14.49 seconds
Started Jul 24 04:58:16 PM PDT 24
Finished Jul 24 04:58:31 PM PDT 24
Peak memory 217132 kb
Host smart-97c82e63-705e-4d4e-81be-207edb915949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449852776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.449852776
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4102547013
Short name T37
Test name
Test status
Simulation time 418195770925 ps
CPU time 570.79 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 05:07:51 PM PDT 24
Peak memory 225048 kb
Host smart-7ae687aa-a5f3-469e-b07f-ca567c2108ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102547013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4102547013
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3130128654
Short name T243
Test name
Test status
Simulation time 16490793416 ps
CPU time 25.6 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 04:58:45 PM PDT 24
Peak memory 218988 kb
Host smart-f159a4a9-ec24-4da2-912a-99dd19f882a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130128654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3130128654
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3141495671
Short name T192
Test name
Test status
Simulation time 182972042 ps
CPU time 10.27 seconds
Started Jul 24 04:58:15 PM PDT 24
Finished Jul 24 04:58:26 PM PDT 24
Peak memory 219224 kb
Host smart-d4b29f51-92aa-43bb-8c7a-eb25ed7ee6bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141495671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3141495671
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2787653779
Short name T242
Test name
Test status
Simulation time 17118453150 ps
CPU time 63.66 seconds
Started Jul 24 04:58:14 PM PDT 24
Finished Jul 24 04:59:18 PM PDT 24
Peak memory 216244 kb
Host smart-c5d04b37-4219-49fe-8197-fda2e4d31159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787653779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2787653779
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3301148961
Short name T332
Test name
Test status
Simulation time 2257805163 ps
CPU time 40.78 seconds
Started Jul 24 04:58:18 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 218900 kb
Host smart-34ac81e0-313d-4f09-8a80-cfe294710c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301148961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3301148961
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2097278367
Short name T297
Test name
Test status
Simulation time 1812248658 ps
CPU time 19.33 seconds
Started Jul 24 04:58:06 PM PDT 24
Finished Jul 24 04:58:25 PM PDT 24
Peak memory 213164 kb
Host smart-98b296ee-3b85-428c-b87d-f44bac1e74c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097278367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2097278367
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.769945264
Short name T214
Test name
Test status
Simulation time 36256840292 ps
CPU time 432.91 seconds
Started Jul 24 04:58:12 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 227428 kb
Host smart-e550d3ef-6f23-422f-adc8-81d58295d627
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769945264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.769945264
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.574131399
Short name T57
Test name
Test status
Simulation time 6826621319 ps
CPU time 58.73 seconds
Started Jul 24 04:58:11 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 219408 kb
Host smart-8ec929ef-ccc8-40ce-adeb-797f8bd152d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574131399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.574131399
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.569212074
Short name T55
Test name
Test status
Simulation time 2466034948 ps
CPU time 10.38 seconds
Started Jul 24 04:58:09 PM PDT 24
Finished Jul 24 04:58:20 PM PDT 24
Peak memory 219240 kb
Host smart-9e086986-8abf-491d-976e-2f6cb249f312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569212074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.569212074
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3435235053
Short name T3
Test name
Test status
Simulation time 8265252986 ps
CPU time 25.66 seconds
Started Jul 24 04:58:16 PM PDT 24
Finished Jul 24 04:58:42 PM PDT 24
Peak memory 216720 kb
Host smart-c4066b9d-7653-4509-a9d9-1db88d64555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435235053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3435235053
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1324914060
Short name T162
Test name
Test status
Simulation time 2086530581 ps
CPU time 37.19 seconds
Started Jul 24 04:58:17 PM PDT 24
Finished Jul 24 04:58:55 PM PDT 24
Peak memory 219388 kb
Host smart-cefb424f-62a4-4e1f-b190-ea5ac27f8a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324914060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1324914060
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1650994108
Short name T247
Test name
Test status
Simulation time 1635727606 ps
CPU time 19.27 seconds
Started Jul 24 04:58:17 PM PDT 24
Finished Jul 24 04:58:37 PM PDT 24
Peak memory 213176 kb
Host smart-11daba33-2823-47a5-ad36-8eb0124772da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650994108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1650994108
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1005812463
Short name T308
Test name
Test status
Simulation time 13418824929 ps
CPU time 228.8 seconds
Started Jul 24 04:58:16 PM PDT 24
Finished Jul 24 05:02:05 PM PDT 24
Peak memory 227676 kb
Host smart-0a9f3290-a432-4ddc-9ca7-f51ff013975b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005812463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1005812463
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1620027795
Short name T1
Test name
Test status
Simulation time 677499058 ps
CPU time 19.11 seconds
Started Jul 24 04:58:28 PM PDT 24
Finished Jul 24 04:58:47 PM PDT 24
Peak memory 219252 kb
Host smart-10908b51-eb6a-4081-9816-dc5eddd24602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620027795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1620027795
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1483912668
Short name T234
Test name
Test status
Simulation time 3897481504 ps
CPU time 31.92 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 219412 kb
Host smart-adada7e0-d01c-4deb-b117-ef35c7eb69c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483912668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1483912668
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3881259730
Short name T228
Test name
Test status
Simulation time 6816583231 ps
CPU time 67.1 seconds
Started Jul 24 04:58:10 PM PDT 24
Finished Jul 24 04:59:17 PM PDT 24
Peak memory 216644 kb
Host smart-ae6949fe-5902-4a7b-aabf-c67284867fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881259730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3881259730
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1485830187
Short name T319
Test name
Test status
Simulation time 2415981257 ps
CPU time 30.11 seconds
Started Jul 24 04:58:14 PM PDT 24
Finished Jul 24 04:58:44 PM PDT 24
Peak memory 219328 kb
Host smart-f263eb82-b1ca-4e7a-9506-83fdb2de861f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485830187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1485830187
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4270697998
Short name T16
Test name
Test status
Simulation time 100011660800 ps
CPU time 940.34 seconds
Started Jul 24 04:58:20 PM PDT 24
Finished Jul 24 05:14:00 PM PDT 24
Peak memory 235736 kb
Host smart-70fe7fe4-57e6-4ce2-8593-e66a30ca508d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270697998 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4270697998
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2229989047
Short name T226
Test name
Test status
Simulation time 3050232119 ps
CPU time 26.73 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 04:58:46 PM PDT 24
Peak memory 217168 kb
Host smart-6a83d7ab-4288-4faf-9a1d-7b67c0057800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229989047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2229989047
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1927992837
Short name T303
Test name
Test status
Simulation time 225046897033 ps
CPU time 650.55 seconds
Started Jul 24 04:58:20 PM PDT 24
Finished Jul 24 05:09:11 PM PDT 24
Peak memory 239304 kb
Host smart-28ea8eab-fbdd-481a-a76d-7c7fcdc38426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927992837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1927992837
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3937334378
Short name T143
Test name
Test status
Simulation time 10334248103 ps
CPU time 36.99 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 04:58:56 PM PDT 24
Peak memory 219252 kb
Host smart-7abbbad8-9a81-488a-8675-6b6b4d93d97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937334378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3937334378
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2829871589
Short name T274
Test name
Test status
Simulation time 7382471413 ps
CPU time 74.85 seconds
Started Jul 24 04:58:19 PM PDT 24
Finished Jul 24 04:59:34 PM PDT 24
Peak memory 216508 kb
Host smart-0598fc15-5a92-43a5-9789-b4c392a6bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829871589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2829871589
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1812759723
Short name T156
Test name
Test status
Simulation time 11059234392 ps
CPU time 62.64 seconds
Started Jul 24 04:58:18 PM PDT 24
Finished Jul 24 04:59:21 PM PDT 24
Peak memory 216592 kb
Host smart-fc400b72-6fe6-4a10-b593-f29c23ec7c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812759723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1812759723
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2201514856
Short name T202
Test name
Test status
Simulation time 7908834265 ps
CPU time 32.5 seconds
Started Jul 24 04:58:31 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 217464 kb
Host smart-fa5a242d-7c64-415e-8a3e-82250d7ed24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201514856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2201514856
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1691295224
Short name T40
Test name
Test status
Simulation time 145397794950 ps
CPU time 455.51 seconds
Started Jul 24 04:58:22 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 239820 kb
Host smart-698aacd6-f6e1-45aa-88d9-0d9bbbc58cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691295224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1691295224
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2397430623
Short name T336
Test name
Test status
Simulation time 8444290951 ps
CPU time 67.92 seconds
Started Jul 24 04:58:20 PM PDT 24
Finished Jul 24 04:59:28 PM PDT 24
Peak memory 219284 kb
Host smart-a5df5212-e557-43de-b245-5925937b96bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397430623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2397430623
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.523781454
Short name T132
Test name
Test status
Simulation time 794620617 ps
CPU time 10.29 seconds
Started Jul 24 04:58:20 PM PDT 24
Finished Jul 24 04:58:30 PM PDT 24
Peak memory 219224 kb
Host smart-dea4da0f-f670-4bd4-820e-77dfe35cb089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523781454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.523781454
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.548483179
Short name T146
Test name
Test status
Simulation time 693517846 ps
CPU time 20.71 seconds
Started Jul 24 04:58:18 PM PDT 24
Finished Jul 24 04:58:39 PM PDT 24
Peak memory 216396 kb
Host smart-58f60c07-b753-4ad5-bfc3-239a640e2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548483179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.548483179
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3166093983
Short name T265
Test name
Test status
Simulation time 12352762161 ps
CPU time 74.21 seconds
Started Jul 24 04:58:17 PM PDT 24
Finished Jul 24 04:59:31 PM PDT 24
Peak memory 219312 kb
Host smart-cedd407b-5741-4696-9db3-d1504774666d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166093983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3166093983
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3184187577
Short name T5
Test name
Test status
Simulation time 14673074085 ps
CPU time 31.3 seconds
Started Jul 24 04:56:58 PM PDT 24
Finished Jul 24 04:57:30 PM PDT 24
Peak memory 213200 kb
Host smart-124ec4bd-52ab-4e35-b9b3-bb98a7fba6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184187577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3184187577
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4285267418
Short name T312
Test name
Test status
Simulation time 3974871022 ps
CPU time 289.95 seconds
Started Jul 24 04:56:57 PM PDT 24
Finished Jul 24 05:01:47 PM PDT 24
Peak memory 229772 kb
Host smart-64417d28-ff06-4ed6-9cea-7544cc47aaca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285267418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4285267418
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1948741662
Short name T244
Test name
Test status
Simulation time 9781948653 ps
CPU time 52.88 seconds
Started Jul 24 04:57:02 PM PDT 24
Finished Jul 24 04:57:55 PM PDT 24
Peak memory 219204 kb
Host smart-8d525b90-151f-4ec8-8351-e3f8574bfd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948741662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1948741662
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.335335004
Short name T304
Test name
Test status
Simulation time 271535314 ps
CPU time 11.96 seconds
Started Jul 24 04:57:07 PM PDT 24
Finished Jul 24 04:57:19 PM PDT 24
Peak memory 219208 kb
Host smart-750d5ac4-7ada-4c00-bfbb-5748e6bc5c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335335004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.335335004
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2406187095
Short name T233
Test name
Test status
Simulation time 21885140854 ps
CPU time 45.16 seconds
Started Jul 24 04:56:58 PM PDT 24
Finished Jul 24 04:57:43 PM PDT 24
Peak memory 216344 kb
Host smart-fe37b496-8663-41a4-98fc-ad27d4f4136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406187095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2406187095
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2517287112
Short name T282
Test name
Test status
Simulation time 7039501816 ps
CPU time 72.56 seconds
Started Jul 24 04:57:09 PM PDT 24
Finished Jul 24 04:58:21 PM PDT 24
Peak memory 217332 kb
Host smart-1a46bbc1-d48a-403e-a303-7623af440777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517287112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2517287112
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.818292732
Short name T300
Test name
Test status
Simulation time 174581035 ps
CPU time 8.09 seconds
Started Jul 24 04:57:06 PM PDT 24
Finished Jul 24 04:57:15 PM PDT 24
Peak memory 216260 kb
Host smart-a8737a7a-6df9-487f-8390-ea717266c16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818292732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.818292732
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2736702426
Short name T250
Test name
Test status
Simulation time 70753938006 ps
CPU time 708.24 seconds
Started Jul 24 04:57:01 PM PDT 24
Finished Jul 24 05:08:49 PM PDT 24
Peak memory 238068 kb
Host smart-2568d003-4896-4bb4-bd12-c3ced7f1e4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736702426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2736702426
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3405630156
Short name T253
Test name
Test status
Simulation time 21765096979 ps
CPU time 53.82 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 04:58:04 PM PDT 24
Peak memory 219312 kb
Host smart-5822c3ac-fdf3-4cc7-a095-5b94048cbf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405630156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3405630156
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1184202348
Short name T359
Test name
Test status
Simulation time 185587795 ps
CPU time 10.14 seconds
Started Jul 24 04:57:03 PM PDT 24
Finished Jul 24 04:57:13 PM PDT 24
Peak memory 219204 kb
Host smart-a54e4347-0e23-4aa1-83ed-cf748c224ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184202348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1184202348
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1917962495
Short name T353
Test name
Test status
Simulation time 8706338239 ps
CPU time 49.93 seconds
Started Jul 24 04:57:12 PM PDT 24
Finished Jul 24 04:58:03 PM PDT 24
Peak memory 217232 kb
Host smart-2134d4bf-8bdb-47ac-ace4-ec0e02541585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917962495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1917962495
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3793289483
Short name T331
Test name
Test status
Simulation time 77516979725 ps
CPU time 117.89 seconds
Started Jul 24 04:57:17 PM PDT 24
Finished Jul 24 04:59:15 PM PDT 24
Peak memory 219272 kb
Host smart-23a77c87-d230-4fd2-aaeb-33472d3f162a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793289483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3793289483
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3456615423
Short name T240
Test name
Test status
Simulation time 9155669169 ps
CPU time 23.13 seconds
Started Jul 24 04:57:06 PM PDT 24
Finished Jul 24 04:57:30 PM PDT 24
Peak memory 213296 kb
Host smart-dba8416b-f8eb-4145-bce1-e8ff6e50eb3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456615423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3456615423
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4271816025
Short name T323
Test name
Test status
Simulation time 54872688505 ps
CPU time 562.63 seconds
Started Jul 24 04:58:17 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 234932 kb
Host smart-551f83d6-f4d0-4628-8e22-5ba8f7def2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271816025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4271816025
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2866513103
Short name T43
Test name
Test status
Simulation time 16349834050 ps
CPU time 42.51 seconds
Started Jul 24 04:57:08 PM PDT 24
Finished Jul 24 04:57:51 PM PDT 24
Peak memory 219368 kb
Host smart-a47a3403-2289-4f03-bb64-0cfa1b1401bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866513103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2866513103
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4044467275
Short name T11
Test name
Test status
Simulation time 353970168 ps
CPU time 10.02 seconds
Started Jul 24 04:57:09 PM PDT 24
Finished Jul 24 04:57:19 PM PDT 24
Peak memory 219328 kb
Host smart-666ee895-8943-40d5-880d-f41e88f766ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044467275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4044467275
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.628863758
Short name T271
Test name
Test status
Simulation time 540034298 ps
CPU time 23.06 seconds
Started Jul 24 04:57:00 PM PDT 24
Finished Jul 24 04:57:23 PM PDT 24
Peak memory 217536 kb
Host smart-d956538b-021e-4bbf-aac3-83536c8dacce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628863758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.628863758
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3081076504
Short name T85
Test name
Test status
Simulation time 11322758017 ps
CPU time 123.79 seconds
Started Jul 24 04:57:42 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 219968 kb
Host smart-5ff09144-43a7-4c86-8314-3264f11537db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081076504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3081076504
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1402092974
Short name T301
Test name
Test status
Simulation time 13324399564 ps
CPU time 15.56 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:29 PM PDT 24
Peak memory 213232 kb
Host smart-4a376864-0b03-4504-b988-aa57b5734cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402092974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1402092974
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1499265416
Short name T18
Test name
Test status
Simulation time 64062078953 ps
CPU time 549.95 seconds
Started Jul 24 04:57:06 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 236492 kb
Host smart-565467a3-b575-46ea-b10b-4941ad280354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499265416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1499265416
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.718439754
Short name T266
Test name
Test status
Simulation time 1320105439 ps
CPU time 19.18 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:31 PM PDT 24
Peak memory 219224 kb
Host smart-d6061ed2-1940-4c47-905f-cb8814fcd556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718439754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.718439754
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1237277351
Short name T195
Test name
Test status
Simulation time 2395131094 ps
CPU time 15.99 seconds
Started Jul 24 04:57:14 PM PDT 24
Finished Jul 24 04:57:30 PM PDT 24
Peak memory 211680 kb
Host smart-74f42699-3453-40cf-a918-eb761b33f670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237277351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1237277351
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3683567733
Short name T185
Test name
Test status
Simulation time 844681770 ps
CPU time 20.2 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:34 PM PDT 24
Peak memory 216328 kb
Host smart-0511b4c7-dfef-4a2b-9494-33b96d47c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683567733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3683567733
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3457428112
Short name T90
Test name
Test status
Simulation time 3748164852 ps
CPU time 47.13 seconds
Started Jul 24 04:57:09 PM PDT 24
Finished Jul 24 04:57:57 PM PDT 24
Peak memory 218656 kb
Host smart-7122825c-4af6-49af-a3ef-13da0e16f9d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457428112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3457428112
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.38874313
Short name T322
Test name
Test status
Simulation time 7023211461 ps
CPU time 25.61 seconds
Started Jul 24 04:57:19 PM PDT 24
Finished Jul 24 04:57:45 PM PDT 24
Peak memory 217412 kb
Host smart-7aa76dd0-934e-4619-a8d1-3d40a43a6191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.38874313
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3698992037
Short name T238
Test name
Test status
Simulation time 152362884506 ps
CPU time 637.4 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 05:07:48 PM PDT 24
Peak memory 225432 kb
Host smart-c1d2da95-936c-4ef8-9e1c-01843e9ceb78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698992037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3698992037
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2024936522
Short name T230
Test name
Test status
Simulation time 90912148577 ps
CPU time 70.02 seconds
Started Jul 24 04:57:10 PM PDT 24
Finished Jul 24 04:58:20 PM PDT 24
Peak memory 219300 kb
Host smart-c637a70d-45d8-4d2c-90f6-186986b3b312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024936522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2024936522
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3347330522
Short name T362
Test name
Test status
Simulation time 3291803285 ps
CPU time 28.65 seconds
Started Jul 24 04:57:11 PM PDT 24
Finished Jul 24 04:57:40 PM PDT 24
Peak memory 219260 kb
Host smart-5ef94247-211a-46e8-8754-b2ece5e9dba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347330522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3347330522
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3108397965
Short name T269
Test name
Test status
Simulation time 862620691 ps
CPU time 25.74 seconds
Started Jul 24 04:57:13 PM PDT 24
Finished Jul 24 04:57:39 PM PDT 24
Peak memory 215840 kb
Host smart-515d7f27-a127-441b-9bb9-4a63ecf8e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108397965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3108397965
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3025006265
Short name T167
Test name
Test status
Simulation time 3233449484 ps
CPU time 53.64 seconds
Started Jul 24 04:57:06 PM PDT 24
Finished Jul 24 04:58:00 PM PDT 24
Peak memory 219284 kb
Host smart-4b504e80-a564-419c-a339-0957ba24cb9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025006265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3025006265
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2369031906
Short name T15
Test name
Test status
Simulation time 155933022301 ps
CPU time 1741.9 seconds
Started Jul 24 04:57:12 PM PDT 24
Finished Jul 24 05:26:15 PM PDT 24
Peak memory 239144 kb
Host smart-9c100296-31ae-4a75-98d2-10141c2edbbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369031906 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2369031906
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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