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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.68 100.00 98.62 97.45 98.37


Total test records in report: 469
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T299 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1491165995 Jul 25 04:48:16 PM PDT 24 Jul 25 04:48:27 PM PDT 24 180731610 ps
T300 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3578821616 Jul 25 04:48:22 PM PDT 24 Jul 25 04:48:33 PM PDT 24 182708561 ps
T301 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2202903807 Jul 25 04:48:36 PM PDT 24 Jul 25 04:49:03 PM PDT 24 1985222298 ps
T302 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.327940685 Jul 25 04:48:32 PM PDT 24 Jul 25 04:50:47 PM PDT 24 2812737590 ps
T303 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3410433108 Jul 25 04:48:25 PM PDT 24 Jul 25 04:48:38 PM PDT 24 1025084835 ps
T304 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.505204005 Jul 25 04:48:03 PM PDT 24 Jul 25 07:28:00 PM PDT 24 94561246582 ps
T305 /workspace/coverage/default/43.rom_ctrl_alert_test.1871447732 Jul 25 04:48:40 PM PDT 24 Jul 25 04:48:51 PM PDT 24 4115476154 ps
T306 /workspace/coverage/default/1.rom_ctrl_stress_all.3871085900 Jul 25 04:47:57 PM PDT 24 Jul 25 04:48:35 PM PDT 24 1041454025 ps
T307 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2051883491 Jul 25 04:48:22 PM PDT 24 Jul 25 04:48:34 PM PDT 24 1001873116 ps
T308 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.956152655 Jul 25 04:48:05 PM PDT 24 Jul 25 04:48:16 PM PDT 24 179392074 ps
T309 /workspace/coverage/default/34.rom_ctrl_smoke.3381004842 Jul 25 04:48:33 PM PDT 24 Jul 25 04:48:57 PM PDT 24 513498658 ps
T310 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1108593827 Jul 25 04:48:25 PM PDT 24 Jul 25 05:00:17 PM PDT 24 37353154436 ps
T311 /workspace/coverage/default/7.rom_ctrl_stress_all.2011902770 Jul 25 04:48:10 PM PDT 24 Jul 25 04:49:20 PM PDT 24 2568819512 ps
T312 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3477148507 Jul 25 04:48:38 PM PDT 24 Jul 25 04:48:55 PM PDT 24 4516392874 ps
T313 /workspace/coverage/default/31.rom_ctrl_alert_test.2763603322 Jul 25 04:48:32 PM PDT 24 Jul 25 04:48:43 PM PDT 24 262756164 ps
T314 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1792242989 Jul 25 04:48:28 PM PDT 24 Jul 25 04:48:48 PM PDT 24 346235801 ps
T315 /workspace/coverage/default/34.rom_ctrl_alert_test.1018411480 Jul 25 04:48:24 PM PDT 24 Jul 25 04:48:34 PM PDT 24 1029471735 ps
T316 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2767264679 Jul 25 04:47:54 PM PDT 24 Jul 25 04:48:15 PM PDT 24 1321728408 ps
T317 /workspace/coverage/default/39.rom_ctrl_alert_test.3581542437 Jul 25 04:48:47 PM PDT 24 Jul 25 04:48:57 PM PDT 24 1125673820 ps
T318 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1966814503 Jul 25 04:48:21 PM PDT 24 Jul 25 04:48:32 PM PDT 24 643227422 ps
T319 /workspace/coverage/default/25.rom_ctrl_smoke.974856068 Jul 25 04:48:37 PM PDT 24 Jul 25 04:48:56 PM PDT 24 1436219193 ps
T320 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3328389841 Jul 25 04:48:17 PM PDT 24 Jul 25 04:48:39 PM PDT 24 1034645101 ps
T321 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1099471769 Jul 25 04:48:27 PM PDT 24 Jul 25 04:48:46 PM PDT 24 1577940601 ps
T322 /workspace/coverage/default/34.rom_ctrl_stress_all.3711510843 Jul 25 04:48:36 PM PDT 24 Jul 25 04:49:06 PM PDT 24 3321343984 ps
T323 /workspace/coverage/default/38.rom_ctrl_stress_all.519670753 Jul 25 04:48:27 PM PDT 24 Jul 25 04:48:55 PM PDT 24 754465832 ps
T324 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1068320689 Jul 25 04:48:23 PM PDT 24 Jul 25 04:51:05 PM PDT 24 2360641489 ps
T325 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2510911271 Jul 25 04:48:04 PM PDT 24 Jul 25 04:48:17 PM PDT 24 2173569777 ps
T326 /workspace/coverage/default/39.rom_ctrl_smoke.2803697852 Jul 25 04:48:33 PM PDT 24 Jul 25 04:48:56 PM PDT 24 525771034 ps
T327 /workspace/coverage/default/0.rom_ctrl_alert_test.347800973 Jul 25 04:48:16 PM PDT 24 Jul 25 04:48:26 PM PDT 24 1035036055 ps
T328 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2045317398 Jul 25 04:48:22 PM PDT 24 Jul 25 04:48:33 PM PDT 24 178290973 ps
T329 /workspace/coverage/default/33.rom_ctrl_alert_test.3445885797 Jul 25 04:48:24 PM PDT 24 Jul 25 04:48:33 PM PDT 24 167358627 ps
T330 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1461566499 Jul 25 04:48:47 PM PDT 24 Jul 25 04:49:09 PM PDT 24 2149568303 ps
T331 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2081610304 Jul 25 04:48:55 PM PDT 24 Jul 25 04:49:07 PM PDT 24 266799602 ps
T332 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1655794609 Jul 25 04:48:35 PM PDT 24 Jul 25 04:51:27 PM PDT 24 2152252821 ps
T333 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3611596223 Jul 25 04:48:37 PM PDT 24 Jul 25 04:48:48 PM PDT 24 190578892 ps
T334 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3814506726 Jul 25 04:48:25 PM PDT 24 Jul 25 04:53:32 PM PDT 24 66389126139 ps
T335 /workspace/coverage/default/25.rom_ctrl_alert_test.1397964928 Jul 25 04:48:22 PM PDT 24 Jul 25 04:48:31 PM PDT 24 172656858 ps
T336 /workspace/coverage/default/19.rom_ctrl_stress_all.3807040231 Jul 25 04:48:32 PM PDT 24 Jul 25 04:48:51 PM PDT 24 545449607 ps
T337 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2135771876 Jul 25 04:48:08 PM PDT 24 Jul 25 04:48:18 PM PDT 24 182423035 ps
T338 /workspace/coverage/default/42.rom_ctrl_smoke.1702128664 Jul 25 04:48:54 PM PDT 24 Jul 25 04:49:14 PM PDT 24 360923919 ps
T339 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1256927445 Jul 25 04:48:24 PM PDT 24 Jul 25 04:48:36 PM PDT 24 342676941 ps
T340 /workspace/coverage/default/14.rom_ctrl_stress_all.38228711 Jul 25 04:48:26 PM PDT 24 Jul 25 04:48:46 PM PDT 24 1662037107 ps
T341 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3771340612 Jul 25 04:48:18 PM PDT 24 Jul 25 04:50:08 PM PDT 24 7849746977 ps
T342 /workspace/coverage/default/30.rom_ctrl_alert_test.1350571916 Jul 25 04:48:25 PM PDT 24 Jul 25 04:48:41 PM PDT 24 1019613507 ps
T343 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1066334682 Jul 25 04:48:07 PM PDT 24 Jul 25 04:51:16 PM PDT 24 10367467583 ps
T344 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2034443484 Jul 25 04:48:56 PM PDT 24 Jul 25 04:49:18 PM PDT 24 5491141315 ps
T345 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.512885415 Jul 25 04:48:25 PM PDT 24 Jul 25 04:55:27 PM PDT 24 10086595134 ps
T346 /workspace/coverage/default/32.rom_ctrl_stress_all.639644706 Jul 25 04:48:35 PM PDT 24 Jul 25 04:49:16 PM PDT 24 797636782 ps
T347 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3653869910 Jul 25 04:48:38 PM PDT 24 Jul 25 04:54:01 PM PDT 24 3855664039 ps
T348 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2295901718 Jul 25 04:48:29 PM PDT 24 Jul 25 04:52:42 PM PDT 24 6920123510 ps
T349 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4049496728 Jul 25 04:48:36 PM PDT 24 Jul 25 04:48:55 PM PDT 24 333454791 ps
T350 /workspace/coverage/default/3.rom_ctrl_alert_test.3570377115 Jul 25 04:48:14 PM PDT 24 Jul 25 04:48:25 PM PDT 24 249927013 ps
T351 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2630069258 Jul 25 04:48:09 PM PDT 24 Jul 25 04:48:21 PM PDT 24 3225489775 ps
T352 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3740893920 Jul 25 04:48:16 PM PDT 24 Jul 25 04:48:34 PM PDT 24 2064577504 ps
T353 /workspace/coverage/default/45.rom_ctrl_alert_test.2863560216 Jul 25 04:48:36 PM PDT 24 Jul 25 04:48:45 PM PDT 24 688284615 ps
T354 /workspace/coverage/default/26.rom_ctrl_smoke.1574775141 Jul 25 04:48:31 PM PDT 24 Jul 25 04:49:06 PM PDT 24 21986241971 ps
T355 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1915086706 Jul 25 04:48:21 PM PDT 24 Jul 25 04:52:37 PM PDT 24 10176288399 ps
T356 /workspace/coverage/default/26.rom_ctrl_alert_test.3970609506 Jul 25 04:48:32 PM PDT 24 Jul 25 04:48:41 PM PDT 24 2073207050 ps
T357 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3028148610 Jul 25 04:48:24 PM PDT 24 Jul 25 04:48:57 PM PDT 24 2053592566 ps
T358 /workspace/coverage/default/5.rom_ctrl_smoke.1145997315 Jul 25 04:48:09 PM PDT 24 Jul 25 04:48:29 PM PDT 24 352930324 ps
T359 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.242555934 Jul 25 04:48:16 PM PDT 24 Jul 25 04:48:35 PM PDT 24 347241332 ps
T360 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3708171933 Jul 25 04:48:20 PM PDT 24 Jul 25 04:53:40 PM PDT 24 24953653986 ps
T361 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4031728201 Jul 25 04:48:01 PM PDT 24 Jul 25 04:48:34 PM PDT 24 2033599956 ps
T362 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3167928779 Jul 25 04:48:12 PM PDT 24 Jul 25 04:53:29 PM PDT 24 5379484891 ps
T363 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2366387745 Jul 25 04:48:23 PM PDT 24 Jul 25 04:48:36 PM PDT 24 1111530156 ps
T364 /workspace/coverage/default/40.rom_ctrl_smoke.3850744015 Jul 25 04:48:25 PM PDT 24 Jul 25 04:48:46 PM PDT 24 358721368 ps
T365 /workspace/coverage/default/22.rom_ctrl_smoke.2201576993 Jul 25 04:48:24 PM PDT 24 Jul 25 04:48:47 PM PDT 24 528303966 ps
T366 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4123392541 Jul 25 04:48:09 PM PDT 24 Jul 25 04:51:08 PM PDT 24 2802294001 ps
T367 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.578868428 Jul 25 04:48:26 PM PDT 24 Jul 25 04:48:45 PM PDT 24 346274088 ps
T368 /workspace/coverage/default/31.rom_ctrl_stress_all.2924458005 Jul 25 04:48:27 PM PDT 24 Jul 25 04:49:04 PM PDT 24 401626678 ps
T369 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1102166090 Jul 25 04:48:34 PM PDT 24 Jul 25 04:48:46 PM PDT 24 521758106 ps
T370 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.254093812 Jul 25 04:47:49 PM PDT 24 Jul 25 04:48:02 PM PDT 24 521475584 ps
T371 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.92684809 Jul 25 04:48:10 PM PDT 24 Jul 25 04:50:19 PM PDT 24 1927674163 ps
T372 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4163006977 Jul 25 04:48:04 PM PDT 24 Jul 25 05:10:58 PM PDT 24 135979518551 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3754985562 Jul 25 04:47:40 PM PDT 24 Jul 25 04:49:01 PM PDT 24 422075752 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3538452100 Jul 25 04:47:49 PM PDT 24 Jul 25 04:48:00 PM PDT 24 496683501 ps
T63 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.8187102 Jul 25 04:47:36 PM PDT 24 Jul 25 04:47:57 PM PDT 24 3946857209 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2466575697 Jul 25 04:47:51 PM PDT 24 Jul 25 04:48:07 PM PDT 24 14305889897 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3989165713 Jul 25 04:47:37 PM PDT 24 Jul 25 04:47:52 PM PDT 24 5752708621 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2064807251 Jul 25 04:47:55 PM PDT 24 Jul 25 04:48:03 PM PDT 24 2744451076 ps
T59 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.34844735 Jul 25 04:48:04 PM PDT 24 Jul 25 04:49:25 PM PDT 24 265065143 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.125220140 Jul 25 04:47:32 PM PDT 24 Jul 25 04:47:58 PM PDT 24 3949756381 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1610053642 Jul 25 04:47:34 PM PDT 24 Jul 25 04:47:42 PM PDT 24 168058816 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4179171977 Jul 25 04:47:41 PM PDT 24 Jul 25 04:48:48 PM PDT 24 6607635152 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2631505732 Jul 25 04:47:36 PM PDT 24 Jul 25 04:47:46 PM PDT 24 921607575 ps
T69 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4121808898 Jul 25 04:48:03 PM PDT 24 Jul 25 04:48:40 PM PDT 24 733172225 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2645464139 Jul 25 04:47:45 PM PDT 24 Jul 25 04:47:57 PM PDT 24 680399087 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3272438040 Jul 25 04:47:51 PM PDT 24 Jul 25 04:48:34 PM PDT 24 3615495461 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.298088700 Jul 25 04:48:03 PM PDT 24 Jul 25 04:48:18 PM PDT 24 1024593490 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3291187400 Jul 25 04:48:05 PM PDT 24 Jul 25 04:48:17 PM PDT 24 175377006 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2304877842 Jul 25 04:48:19 PM PDT 24 Jul 25 04:48:29 PM PDT 24 495478703 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.782691251 Jul 25 04:47:44 PM PDT 24 Jul 25 04:47:52 PM PDT 24 241651275 ps
T60 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2257834065 Jul 25 04:48:06 PM PDT 24 Jul 25 04:49:29 PM PDT 24 616688478 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1195334197 Jul 25 04:47:37 PM PDT 24 Jul 25 04:48:33 PM PDT 24 2112140445 ps
T377 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.215449356 Jul 25 04:47:57 PM PDT 24 Jul 25 04:48:11 PM PDT 24 362791878 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.241509753 Jul 25 04:47:40 PM PDT 24 Jul 25 04:47:59 PM PDT 24 1006270133 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3221758185 Jul 25 04:47:42 PM PDT 24 Jul 25 04:47:55 PM PDT 24 506570667 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2962269643 Jul 25 04:47:48 PM PDT 24 Jul 25 04:48:03 PM PDT 24 986712361 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.706577421 Jul 25 04:47:58 PM PDT 24 Jul 25 04:48:12 PM PDT 24 265891720 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4063613275 Jul 25 04:48:02 PM PDT 24 Jul 25 04:48:46 PM PDT 24 2034273920 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1650858630 Jul 25 04:47:41 PM PDT 24 Jul 25 04:47:56 PM PDT 24 1458660437 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2401805473 Jul 25 04:47:49 PM PDT 24 Jul 25 04:48:05 PM PDT 24 1029265461 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1699623932 Jul 25 04:47:55 PM PDT 24 Jul 25 04:48:13 PM PDT 24 984631988 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4107130085 Jul 25 04:48:07 PM PDT 24 Jul 25 04:48:17 PM PDT 24 2465818871 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2902751721 Jul 25 04:48:07 PM PDT 24 Jul 25 04:48:19 PM PDT 24 191886908 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3760443006 Jul 25 04:47:54 PM PDT 24 Jul 25 04:49:14 PM PDT 24 1208078013 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1068102879 Jul 25 04:47:53 PM PDT 24 Jul 25 04:48:04 PM PDT 24 256844195 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2879779827 Jul 25 04:47:38 PM PDT 24 Jul 25 04:47:52 PM PDT 24 612701632 ps
T387 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.605946577 Jul 25 04:48:06 PM PDT 24 Jul 25 04:48:15 PM PDT 24 711302517 ps
T98 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1184653036 Jul 25 04:48:00 PM PDT 24 Jul 25 04:49:06 PM PDT 24 1552662494 ps
T99 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2982736897 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:54 PM PDT 24 1077823085 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1803221024 Jul 25 04:48:00 PM PDT 24 Jul 25 04:50:39 PM PDT 24 431286267 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3951597679 Jul 25 04:48:15 PM PDT 24 Jul 25 04:48:28 PM PDT 24 948612643 ps
T100 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1218336278 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:06 PM PDT 24 502259617 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3814619792 Jul 25 04:47:31 PM PDT 24 Jul 25 04:47:49 PM PDT 24 3590171138 ps
T389 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2448669827 Jul 25 04:47:54 PM PDT 24 Jul 25 04:48:39 PM PDT 24 5055433901 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2140351966 Jul 25 04:47:46 PM PDT 24 Jul 25 04:47:58 PM PDT 24 183711559 ps
T115 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3972535999 Jul 25 04:47:50 PM PDT 24 Jul 25 04:50:22 PM PDT 24 1419396177 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2978905376 Jul 25 04:47:37 PM PDT 24 Jul 25 04:47:54 PM PDT 24 514992821 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1254771484 Jul 25 04:47:38 PM PDT 24 Jul 25 04:47:47 PM PDT 24 1830568549 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1224672844 Jul 25 04:47:56 PM PDT 24 Jul 25 04:48:09 PM PDT 24 167640028 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2913021840 Jul 25 04:47:53 PM PDT 24 Jul 25 04:48:07 PM PDT 24 1029197583 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2577174954 Jul 25 04:48:13 PM PDT 24 Jul 25 04:48:24 PM PDT 24 175272039 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1378250994 Jul 25 04:47:59 PM PDT 24 Jul 25 04:48:08 PM PDT 24 1378111012 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1826060550 Jul 25 04:48:04 PM PDT 24 Jul 25 04:48:19 PM PDT 24 1031609805 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2539670160 Jul 25 04:47:40 PM PDT 24 Jul 25 04:47:53 PM PDT 24 496125539 ps
T77 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4154777498 Jul 25 04:47:56 PM PDT 24 Jul 25 04:48:09 PM PDT 24 501533722 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1045083666 Jul 25 04:51:17 PM PDT 24 Jul 25 04:52:13 PM PDT 24 8553875607 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2217889187 Jul 25 04:47:49 PM PDT 24 Jul 25 04:48:27 PM PDT 24 2856425274 ps
T116 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4152951458 Jul 25 04:48:03 PM PDT 24 Jul 25 04:49:24 PM PDT 24 2303804934 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4127306493 Jul 25 04:48:19 PM PDT 24 Jul 25 04:48:34 PM PDT 24 1897938990 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2879460967 Jul 25 04:48:06 PM PDT 24 Jul 25 04:48:25 PM PDT 24 1401449789 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3151301234 Jul 25 04:47:41 PM PDT 24 Jul 25 04:47:51 PM PDT 24 260199935 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3741459543 Jul 25 04:48:01 PM PDT 24 Jul 25 04:48:09 PM PDT 24 691724563 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3348659985 Jul 25 04:48:10 PM PDT 24 Jul 25 04:48:20 PM PDT 24 1035317716 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3424011459 Jul 25 04:48:02 PM PDT 24 Jul 25 04:48:13 PM PDT 24 274078684 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2109967382 Jul 25 04:47:36 PM PDT 24 Jul 25 04:47:46 PM PDT 24 988398379 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3863020420 Jul 25 04:47:58 PM PDT 24 Jul 25 04:48:06 PM PDT 24 661956603 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2656937395 Jul 25 04:47:41 PM PDT 24 Jul 25 04:47:51 PM PDT 24 1241240698 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1483645184 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:03 PM PDT 24 262811207 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1376839076 Jul 25 04:47:38 PM PDT 24 Jul 25 04:47:48 PM PDT 24 1764686988 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.464956744 Jul 25 04:47:50 PM PDT 24 Jul 25 04:48:02 PM PDT 24 168030782 ps
T80 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2805275393 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:52 PM PDT 24 346124139 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.76312854 Jul 25 04:48:10 PM PDT 24 Jul 25 04:48:21 PM PDT 24 253244869 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3779729596 Jul 25 04:47:32 PM PDT 24 Jul 25 04:47:45 PM PDT 24 248945734 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1099642228 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:53 PM PDT 24 517689616 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1277295434 Jul 25 04:47:40 PM PDT 24 Jul 25 04:49:03 PM PDT 24 3987146725 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.92083599 Jul 25 04:47:58 PM PDT 24 Jul 25 04:50:36 PM PDT 24 419523093 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4151703918 Jul 25 04:47:40 PM PDT 24 Jul 25 04:47:51 PM PDT 24 274303395 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4141858692 Jul 25 04:47:59 PM PDT 24 Jul 25 04:48:08 PM PDT 24 689082560 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1096296933 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:59 PM PDT 24 4124270418 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2229220771 Jul 25 04:47:47 PM PDT 24 Jul 25 04:47:57 PM PDT 24 258057451 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.572622835 Jul 25 04:47:44 PM PDT 24 Jul 25 04:47:55 PM PDT 24 1119270381 ps
T81 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2492554317 Jul 25 04:47:57 PM PDT 24 Jul 25 04:48:05 PM PDT 24 353045108 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1139524708 Jul 25 04:47:50 PM PDT 24 Jul 25 04:47:59 PM PDT 24 168975282 ps
T87 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1135031472 Jul 25 04:47:58 PM PDT 24 Jul 25 04:48:53 PM PDT 24 1044952832 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.507489180 Jul 25 04:47:50 PM PDT 24 Jul 25 04:48:00 PM PDT 24 1178308643 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4180555184 Jul 25 04:47:38 PM PDT 24 Jul 25 04:48:45 PM PDT 24 9527680231 ps
T422 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.921086636 Jul 25 04:47:59 PM PDT 24 Jul 25 04:48:11 PM PDT 24 181301353 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1006809950 Jul 25 04:47:58 PM PDT 24 Jul 25 04:49:23 PM PDT 24 961349741 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3125775856 Jul 25 04:48:01 PM PDT 24 Jul 25 04:48:10 PM PDT 24 673958962 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1239699584 Jul 25 04:47:42 PM PDT 24 Jul 25 04:47:50 PM PDT 24 169203871 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2433797577 Jul 25 04:47:31 PM PDT 24 Jul 25 04:47:41 PM PDT 24 253892702 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1579049660 Jul 25 04:47:30 PM PDT 24 Jul 25 04:47:42 PM PDT 24 254749850 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2820359559 Jul 25 04:47:41 PM PDT 24 Jul 25 04:47:50 PM PDT 24 179535468 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3058473537 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:02 PM PDT 24 252725146 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1754886894 Jul 25 04:48:12 PM PDT 24 Jul 25 04:48:22 PM PDT 24 293940018 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2663963693 Jul 25 04:47:46 PM PDT 24 Jul 25 04:47:56 PM PDT 24 266253273 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.692270304 Jul 25 04:47:53 PM PDT 24 Jul 25 04:48:01 PM PDT 24 340650853 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3274473160 Jul 25 04:48:12 PM PDT 24 Jul 25 04:48:21 PM PDT 24 785639919 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2027961857 Jul 25 04:47:57 PM PDT 24 Jul 25 04:48:05 PM PDT 24 1836834322 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3724388319 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:53 PM PDT 24 989868385 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2464507880 Jul 25 04:48:02 PM PDT 24 Jul 25 04:49:08 PM PDT 24 8458186893 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.716860659 Jul 25 04:47:40 PM PDT 24 Jul 25 04:47:50 PM PDT 24 1768342536 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.398092856 Jul 25 04:48:10 PM PDT 24 Jul 25 04:49:07 PM PDT 24 14660653113 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4129609230 Jul 25 04:47:57 PM PDT 24 Jul 25 04:50:33 PM PDT 24 1876353489 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3489206463 Jul 25 04:47:31 PM PDT 24 Jul 25 04:47:41 PM PDT 24 259756535 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2261577851 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:05 PM PDT 24 986694314 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2165425101 Jul 25 04:47:48 PM PDT 24 Jul 25 04:47:57 PM PDT 24 663049447 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2648651638 Jul 25 04:48:08 PM PDT 24 Jul 25 04:48:16 PM PDT 24 178159628 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.915584112 Jul 25 04:48:04 PM PDT 24 Jul 25 04:48:15 PM PDT 24 2363396472 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.814563087 Jul 25 04:47:43 PM PDT 24 Jul 25 04:48:49 PM PDT 24 1565450656 ps
T86 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2112535722 Jul 25 04:48:06 PM PDT 24 Jul 25 04:49:00 PM PDT 24 6906574192 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2469319738 Jul 25 04:47:55 PM PDT 24 Jul 25 04:50:31 PM PDT 24 834119560 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2363620502 Jul 25 04:47:44 PM PDT 24 Jul 25 04:48:41 PM PDT 24 3807187457 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3233467723 Jul 25 04:47:32 PM PDT 24 Jul 25 04:48:53 PM PDT 24 234178973 ps
T445 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2105865906 Jul 25 04:47:47 PM PDT 24 Jul 25 04:47:57 PM PDT 24 1079939784 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4185020438 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:04 PM PDT 24 177843266 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.652845224 Jul 25 04:48:15 PM PDT 24 Jul 25 04:50:50 PM PDT 24 818051271 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1473993174 Jul 25 04:47:31 PM PDT 24 Jul 25 04:48:38 PM PDT 24 3048484232 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3538529833 Jul 25 04:47:56 PM PDT 24 Jul 25 04:48:04 PM PDT 24 338356474 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1286209593 Jul 25 04:48:06 PM PDT 24 Jul 25 04:48:15 PM PDT 24 663474351 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3321064434 Jul 25 04:47:39 PM PDT 24 Jul 25 04:49:00 PM PDT 24 919677046 ps
T448 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1926618101 Jul 25 04:47:56 PM PDT 24 Jul 25 04:48:05 PM PDT 24 198557876 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1835718736 Jul 25 04:47:37 PM PDT 24 Jul 25 04:48:15 PM PDT 24 693862643 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4285168692 Jul 25 04:47:44 PM PDT 24 Jul 25 04:47:59 PM PDT 24 1937534785 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3328023952 Jul 25 04:47:55 PM PDT 24 Jul 25 04:49:22 PM PDT 24 1154305554 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.699713294 Jul 25 04:48:05 PM PDT 24 Jul 25 04:48:15 PM PDT 24 259388029 ps
T453 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2459472494 Jul 25 04:47:53 PM PDT 24 Jul 25 04:48:49 PM PDT 24 4321497607 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3449157421 Jul 25 04:47:57 PM PDT 24 Jul 25 04:50:31 PM PDT 24 1602874363 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3353742505 Jul 25 04:47:52 PM PDT 24 Jul 25 04:48:03 PM PDT 24 277582676 ps
T455 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3488988326 Jul 25 04:48:09 PM PDT 24 Jul 25 04:48:18 PM PDT 24 718541066 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3584847232 Jul 25 04:48:09 PM PDT 24 Jul 25 04:50:44 PM PDT 24 5075810359 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1972948122 Jul 25 04:48:07 PM PDT 24 Jul 25 04:50:39 PM PDT 24 1482491246 ps
T456 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.43760965 Jul 25 04:47:41 PM PDT 24 Jul 25 04:47:50 PM PDT 24 168221919 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1873020702 Jul 25 04:47:51 PM PDT 24 Jul 25 04:49:12 PM PDT 24 235407036 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1991719530 Jul 25 04:47:31 PM PDT 24 Jul 25 04:47:49 PM PDT 24 1135113155 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3754216617 Jul 25 04:47:54 PM PDT 24 Jul 25 04:48:05 PM PDT 24 3716919525 ps
T459 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.449465020 Jul 25 04:47:46 PM PDT 24 Jul 25 04:47:59 PM PDT 24 308402110 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3208065110 Jul 25 04:48:02 PM PDT 24 Jul 25 04:48:13 PM PDT 24 528164080 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.429566647 Jul 25 04:47:38 PM PDT 24 Jul 25 04:47:49 PM PDT 24 884975021 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3793872196 Jul 25 04:48:10 PM PDT 24 Jul 25 04:48:20 PM PDT 24 264219901 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3226969286 Jul 25 04:47:43 PM PDT 24 Jul 25 04:47:52 PM PDT 24 169132330 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.322148723 Jul 25 04:47:55 PM PDT 24 Jul 25 04:48:05 PM PDT 24 528365447 ps
T465 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3677009518 Jul 25 04:48:06 PM PDT 24 Jul 25 04:48:15 PM PDT 24 747724373 ps
T466 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1410529248 Jul 25 04:47:36 PM PDT 24 Jul 25 04:47:45 PM PDT 24 201393265 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.987837159 Jul 25 04:48:05 PM PDT 24 Jul 25 04:48:22 PM PDT 24 1674720736 ps
T468 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1259261827 Jul 25 04:47:43 PM PDT 24 Jul 25 04:48:54 PM PDT 24 1527168430 ps
T469 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2378205591 Jul 25 04:48:04 PM PDT 24 Jul 25 04:48:20 PM PDT 24 1647648902 ps

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.298146403
Short name T5
Test name
Test status
Simulation time 36609938061 ps
CPU time 690.93 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 05:00:00 PM PDT 24
Peak memory 235404 kb
Host smart-4cea7265-6e17-4546-ae97-7bf8c3e40577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298146403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.298146403
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1867361100
Short name T16
Test name
Test status
Simulation time 22955492662 ps
CPU time 916.61 seconds
Started Jul 25 04:48:53 PM PDT 24
Finished Jul 25 05:04:10 PM PDT 24
Peak memory 235244 kb
Host smart-7e59422a-df26-4445-970f-1a94f75222d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867361100 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1867361100
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4062502585
Short name T14
Test name
Test status
Simulation time 14884234640 ps
CPU time 52.82 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 221116 kb
Host smart-d7c4715c-61eb-43aa-8297-9c03cdc92a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062502585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4062502585
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2233761419
Short name T9
Test name
Test status
Simulation time 2113592846 ps
CPU time 40.17 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 219168 kb
Host smart-ed96c9a2-2b5b-46ac-ad63-13f225179319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233761419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2233761419
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1803221024
Short name T108
Test name
Test status
Simulation time 431286267 ps
CPU time 158.47 seconds
Started Jul 25 04:48:00 PM PDT 24
Finished Jul 25 04:50:39 PM PDT 24
Peak memory 214284 kb
Host smart-950353e2-26da-4faf-994a-6920b388061b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803221024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1803221024
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1236470962
Short name T51
Test name
Test status
Simulation time 280379131802 ps
CPU time 4077.16 seconds
Started Jul 25 04:48:57 PM PDT 24
Finished Jul 25 05:56:54 PM PDT 24
Peak memory 252756 kb
Host smart-78a42688-d08c-4474-8a5d-a7431a8869f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236470962 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1236470962
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2785264758
Short name T28
Test name
Test status
Simulation time 1284513646 ps
CPU time 119.46 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 238936 kb
Host smart-ab2a9d3f-9140-4979-9e65-b094ce10fcce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785264758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2785264758
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4179171977
Short name T67
Test name
Test status
Simulation time 6607635152 ps
CPU time 66.62 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 214980 kb
Host smart-aca88da8-c2bb-4019-84f7-8fe50a1b3c7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179171977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4179171977
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3974396185
Short name T3
Test name
Test status
Simulation time 13413911578 ps
CPU time 127.27 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:50:53 PM PDT 24
Peak memory 239540 kb
Host smart-5e9cacd6-6dc9-464f-9fb9-307e2023678d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974396185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3974396185
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.950486190
Short name T7
Test name
Test status
Simulation time 661844674 ps
CPU time 8.1 seconds
Started Jul 25 04:48:42 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 218916 kb
Host smart-025fe013-93ae-426c-8b48-07b1aafbd1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950486190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.950486190
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3449157421
Short name T110
Test name
Test status
Simulation time 1602874363 ps
CPU time 154.23 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 214180 kb
Host smart-3975a0e0-5cf1-43bf-b81d-e59f81d7c81b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449157421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3449157421
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3584847232
Short name T105
Test name
Test status
Simulation time 5075810359 ps
CPU time 155.07 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 214460 kb
Host smart-9c738375-68f5-4c93-988b-2e4d5a95bfb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584847232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3584847232
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2735549230
Short name T91
Test name
Test status
Simulation time 348237599 ps
CPU time 19.85 seconds
Started Jul 25 04:47:59 PM PDT 24
Finished Jul 25 04:48:19 PM PDT 24
Peak memory 219840 kb
Host smart-ee04432e-4235-4ee9-a92f-1b814072ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735549230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2735549230
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.611143707
Short name T167
Test name
Test status
Simulation time 9827532323 ps
CPU time 32.52 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:54 PM PDT 24
Peak memory 219792 kb
Host smart-e4643cdc-eff9-4998-be51-e8eded88bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611143707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.611143707
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1986886387
Short name T30
Test name
Test status
Simulation time 993395278 ps
CPU time 22.74 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 219828 kb
Host smart-125fc356-acf0-452c-879b-e5f58ebdedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986886387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1986886387
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1873020702
Short name T113
Test name
Test status
Simulation time 235407036 ps
CPU time 81.27 seconds
Started Jul 25 04:47:51 PM PDT 24
Finished Jul 25 04:49:12 PM PDT 24
Peak memory 213732 kb
Host smart-864386f1-0c84-4cda-8b70-502277a452af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873020702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1873020702
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2601608668
Short name T15
Test name
Test status
Simulation time 53457099998 ps
CPU time 824.07 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 05:01:24 PM PDT 24
Peak memory 232252 kb
Host smart-3a34fd1a-51c3-488f-bb03-adbdf306c39f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601608668 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2601608668
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2469319738
Short name T114
Test name
Test status
Simulation time 834119560 ps
CPU time 155.29 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 214156 kb
Host smart-84497172-0f5e-44e0-8ba8-45e6bb3b75d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469319738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2469319738
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2631505732
Short name T68
Test name
Test status
Simulation time 921607575 ps
CPU time 9.8 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:46 PM PDT 24
Peak memory 210628 kb
Host smart-7488fb43-35c6-4170-9ecc-9d99e92aa82d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631505732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2631505732
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1353928771
Short name T88
Test name
Test status
Simulation time 367316379 ps
CPU time 12.15 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219788 kb
Host smart-eb6df6a5-97ef-49f4-8ffe-4b1cbd85b646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353928771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1353928771
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1329607623
Short name T145
Test name
Test status
Simulation time 7817445705 ps
CPU time 35.72 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 220576 kb
Host smart-4a613993-d755-4c9a-8c18-b937fcb0ff5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329607623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1329607623
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1227197150
Short name T21
Test name
Test status
Simulation time 32269849172 ps
CPU time 1215.49 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 05:08:49 PM PDT 24
Peak memory 234268 kb
Host smart-1e087131-8b5a-4e59-a398-ce213794dda9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227197150 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1227197150
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2027961857
Short name T83
Test name
Test status
Simulation time 1836834322 ps
CPU time 8.31 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 210592 kb
Host smart-292da52d-9281-4b3b-bdd4-a014ec61d5ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027961857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2027961857
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2401805473
Short name T382
Test name
Test status
Simulation time 1029265461 ps
CPU time 10.18 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 210848 kb
Host smart-78acfa31-6e3d-4c22-a8f5-264139daa56e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401805473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2401805473
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.8187102
Short name T63
Test name
Test status
Simulation time 3946857209 ps
CPU time 21.02 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:57 PM PDT 24
Peak memory 212028 kb
Host smart-f7d96033-3b04-4db6-987b-3a2a0d7c2abd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8187102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_rese
t.8187102
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2466575697
Short name T373
Test name
Test status
Simulation time 14305889897 ps
CPU time 15.73 seconds
Started Jul 25 04:47:51 PM PDT 24
Finished Jul 25 04:48:07 PM PDT 24
Peak memory 217900 kb
Host smart-20050c62-9ae7-482c-bf90-5c6c6c2acc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466575697 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2466575697
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1610053642
Short name T66
Test name
Test status
Simulation time 168058816 ps
CPU time 7.88 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 210640 kb
Host smart-ff6a4fd0-2e12-4511-9b4d-d7200a421e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610053642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1610053642
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2433797577
Short name T425
Test name
Test status
Simulation time 253892702 ps
CPU time 9.8 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:41 PM PDT 24
Peak memory 210408 kb
Host smart-b86462c3-976f-44cd-aef4-edaee6ca3223
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433797577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2433797577
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3989165713
Short name T374
Test name
Test status
Simulation time 5752708621 ps
CPU time 14.39 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 210448 kb
Host smart-ae3ddf2b-288b-4c7a-8879-192ec4bae7af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989165713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3989165713
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4063613275
Short name T73
Test name
Test status
Simulation time 2034273920 ps
CPU time 43.47 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 213748 kb
Host smart-8a3ce173-4d91-425e-9a85-c91c471e0bab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063613275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4063613275
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2645464139
Short name T70
Test name
Test status
Simulation time 680399087 ps
CPU time 11.81 seconds
Started Jul 25 04:47:45 PM PDT 24
Finished Jul 25 04:47:57 PM PDT 24
Peak memory 212496 kb
Host smart-c3e8fa83-294c-4474-aca9-cd2c1fa9678a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645464139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2645464139
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2539670160
Short name T398
Test name
Test status
Simulation time 496125539 ps
CPU time 12.78 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:53 PM PDT 24
Peak memory 216984 kb
Host smart-6b39fb0c-f644-4312-b16d-15b6a68e5574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539670160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2539670160
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3328023952
Short name T451
Test name
Test status
Simulation time 1154305554 ps
CPU time 86.26 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 212704 kb
Host smart-7ed7929d-ba42-4ee2-8f45-87bf50bfd10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328023952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3328023952
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.429566647
Short name T461
Test name
Test status
Simulation time 884975021 ps
CPU time 9.84 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:49 PM PDT 24
Peak memory 211096 kb
Host smart-f4ef6c1a-fb7a-4891-a7ae-e8967a5a5ef1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429566647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.429566647
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3741459543
Short name T402
Test name
Test status
Simulation time 691724563 ps
CPU time 8.4 seconds
Started Jul 25 04:48:01 PM PDT 24
Finished Jul 25 04:48:09 PM PDT 24
Peak memory 210512 kb
Host smart-7dc9ba80-05bf-4ca6-ab4b-24e6f401acf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741459543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3741459543
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1991719530
Short name T457
Test name
Test status
Simulation time 1135113155 ps
CPU time 13.24 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:49 PM PDT 24
Peak memory 211720 kb
Host smart-5ccfc6ef-3121-4069-9d78-0879dfaa9727
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991719530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1991719530
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3754216617
Short name T458
Test name
Test status
Simulation time 3716919525 ps
CPU time 10.67 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 216988 kb
Host smart-7e8a7ad0-693a-45c3-ae83-e5bfc8bb7364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754216617 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3754216617
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3538529833
Short name T447
Test name
Test status
Simulation time 338356474 ps
CPU time 7.99 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:04 PM PDT 24
Peak memory 210408 kb
Host smart-29c372c9-c9b1-418b-9d17-41a9143a92c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538529833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3538529833
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.716860659
Short name T435
Test name
Test status
Simulation time 1768342536 ps
CPU time 10.01 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 210484 kb
Host smart-fb384148-3593-4b39-a06a-407c8eb1d1d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716860659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
716860659
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.814563087
Short name T442
Test name
Test status
Simulation time 1565450656 ps
CPU time 65.95 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 215092 kb
Host smart-44e5c109-e05a-4176-9104-7c82e196b426
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814563087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.814563087
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3151301234
Short name T401
Test name
Test status
Simulation time 260199935 ps
CPU time 9.89 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:51 PM PDT 24
Peak memory 211432 kb
Host smart-875930f9-ae82-4aed-b4ce-ff4d8e257652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151301234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3151301234
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2879779827
Short name T386
Test name
Test status
Simulation time 612701632 ps
CPU time 13 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 218728 kb
Host smart-ec0c2ae3-0964-4706-9aa2-11683b34e7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879779827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2879779827
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2648651638
Short name T440
Test name
Test status
Simulation time 178159628 ps
CPU time 8.7 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:16 PM PDT 24
Peak memory 215588 kb
Host smart-45987a53-67ef-43f1-8a2b-d49c9a1ba5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648651638 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2648651638
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1254771484
Short name T392
Test name
Test status
Simulation time 1830568549 ps
CPU time 7.84 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 210972 kb
Host smart-16f74bf0-1717-41df-9f17-a8f3532ceb1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254771484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1254771484
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2464507880
Short name T434
Test name
Test status
Simulation time 8458186893 ps
CPU time 65.96 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:49:08 PM PDT 24
Peak memory 215140 kb
Host smart-dd3b2100-db3f-4e6b-ac96-2b7c76398ea7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464507880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2464507880
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1378250994
Short name T396
Test name
Test status
Simulation time 1378111012 ps
CPU time 8.29 seconds
Started Jul 25 04:47:59 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 211132 kb
Host smart-ca7bab32-7e12-4fd8-9f7f-20f89af8428d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378250994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1378250994
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2378205591
Short name T469
Test name
Test status
Simulation time 1647648902 ps
CPU time 14.99 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:20 PM PDT 24
Peak memory 217568 kb
Host smart-e5a9bdd0-ee79-40c5-9008-5640347d1f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378205591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2378205591
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.215449356
Short name T377
Test name
Test status
Simulation time 362791878 ps
CPU time 9.28 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:11 PM PDT 24
Peak memory 217044 kb
Host smart-4a452bff-c7e3-484f-a497-39a161c2f0c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215449356 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.215449356
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3348659985
Short name T403
Test name
Test status
Simulation time 1035317716 ps
CPU time 9.93 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:48:20 PM PDT 24
Peak memory 210972 kb
Host smart-fd1b5d30-1737-4a2b-8409-c06e0f55837e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348659985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3348659985
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4180555184
Short name T421
Test name
Test status
Simulation time 9527680231 ps
CPU time 66.42 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 218852 kb
Host smart-3faf5aba-ee77-4c0a-9922-699c91793836
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180555184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4180555184
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2304877842
Short name T95
Test name
Test status
Simulation time 495478703 ps
CPU time 9.92 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 211548 kb
Host smart-bef409bd-ec56-4472-9d0d-5991a6c23e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304877842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2304877842
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2261577851
Short name T438
Test name
Test status
Simulation time 986694314 ps
CPU time 12.74 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 217212 kb
Host smart-01b2dca1-5842-49cf-bd42-e8f55af7807a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261577851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2261577851
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1972948122
Short name T106
Test name
Test status
Simulation time 1482491246 ps
CPU time 152.11 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:50:39 PM PDT 24
Peak memory 212964 kb
Host smart-190de1ae-4a05-4ac4-8403-808e46a26f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972948122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1972948122
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3125775856
Short name T423
Test name
Test status
Simulation time 673958962 ps
CPU time 8.22 seconds
Started Jul 25 04:48:01 PM PDT 24
Finished Jul 25 04:48:10 PM PDT 24
Peak memory 212972 kb
Host smart-844dfb48-bf9c-4a05-a32f-51c74abef856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125775856 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3125775856
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.43760965
Short name T456
Test name
Test status
Simulation time 168221919 ps
CPU time 8.06 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 210808 kb
Host smart-86cc5e94-e70e-41c0-87c6-dfab5848c791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43760965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.43760965
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2656937395
Short name T407
Test name
Test status
Simulation time 1241240698 ps
CPU time 9.95 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:51 PM PDT 24
Peak memory 211328 kb
Host smart-1b662b97-19c5-4cd5-ba51-51355a8f4428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656937395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2656937395
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.298088700
Short name T375
Test name
Test status
Simulation time 1024593490 ps
CPU time 14.17 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:48:18 PM PDT 24
Peak memory 217436 kb
Host smart-7df2bee9-5c0d-4fa9-afb4-9b4a8dbd0d11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298088700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.298088700
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4129609230
Short name T436
Test name
Test status
Simulation time 1876353489 ps
CPU time 155.46 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:50:33 PM PDT 24
Peak memory 213120 kb
Host smart-11b0bcfa-e9a9-4c62-88cf-218d9d064cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129609230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4129609230
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.915584112
Short name T441
Test name
Test status
Simulation time 2363396472 ps
CPU time 10.31 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 216288 kb
Host smart-00c49604-2729-4493-b594-effb598927d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915584112 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.915584112
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3538452100
Short name T62
Test name
Test status
Simulation time 496683501 ps
CPU time 10.08 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:48:00 PM PDT 24
Peak memory 210616 kb
Host smart-6d500fbc-fa21-4cdf-803b-5b78d49ea878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538452100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3538452100
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.398092856
Short name T84
Test name
Test status
Simulation time 14660653113 ps
CPU time 56.72 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:49:07 PM PDT 24
Peak memory 215456 kb
Host smart-9f8bd5dc-99a7-4076-9afc-cc99a18a524d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398092856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.398092856
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2140351966
Short name T390
Test name
Test status
Simulation time 183711559 ps
CPU time 12.22 seconds
Started Jul 25 04:47:46 PM PDT 24
Finished Jul 25 04:47:58 PM PDT 24
Peak memory 212364 kb
Host smart-fd528d7e-db44-4b9e-bd34-b618026d763c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140351966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2140351966
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4127306493
Short name T399
Test name
Test status
Simulation time 1897938990 ps
CPU time 14.33 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 217664 kb
Host smart-6cb6b296-125c-4aaa-a901-1a13f7445754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127306493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4127306493
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4152951458
Short name T116
Test name
Test status
Simulation time 2303804934 ps
CPU time 80.28 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 213684 kb
Host smart-af43b288-ad8f-4a73-9022-f2cf48592017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152951458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4152951458
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.572622835
Short name T419
Test name
Test status
Simulation time 1119270381 ps
CPU time 10.94 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:55 PM PDT 24
Peak memory 217420 kb
Host smart-cb1a7e42-fcf0-4035-925e-435ac775f692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572622835 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.572622835
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2229220771
Short name T418
Test name
Test status
Simulation time 258057451 ps
CPU time 9.86 seconds
Started Jul 25 04:47:47 PM PDT 24
Finished Jul 25 04:47:57 PM PDT 24
Peak memory 210912 kb
Host smart-93a1e7a9-4cf5-47e0-85fc-4ce5d4992c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229220771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2229220771
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2363620502
Short name T443
Test name
Test status
Simulation time 3807187457 ps
CPU time 56.05 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:48:41 PM PDT 24
Peak memory 215184 kb
Host smart-0404136b-de3d-472c-aed9-b90b2126d13e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363620502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2363620502
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3863020420
Short name T406
Test name
Test status
Simulation time 661956603 ps
CPU time 8.09 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:48:06 PM PDT 24
Peak memory 211336 kb
Host smart-c26c62b3-a3b5-4c80-8923-4ab07701d61c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863020420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3863020420
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3291187400
Short name T376
Test name
Test status
Simulation time 175377006 ps
CPU time 11.2 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 218784 kb
Host smart-93d96199-9ef3-41ce-bb25-d45b553cdb53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291187400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3291187400
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3760443006
Short name T107
Test name
Test status
Simulation time 1208078013 ps
CPU time 80.15 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:49:14 PM PDT 24
Peak memory 213844 kb
Host smart-87ba2a27-281a-4609-a35a-1f8b1438bf28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760443006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3760443006
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.605946577
Short name T387
Test name
Test status
Simulation time 711302517 ps
CPU time 9.1 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 216488 kb
Host smart-f26ab206-da48-4ad6-ad2e-0cde580b3c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605946577 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.605946577
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4154777498
Short name T77
Test name
Test status
Simulation time 501533722 ps
CPU time 7.85 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:09 PM PDT 24
Peak memory 210880 kb
Host smart-3c066b49-8c94-4297-966b-10a099b89446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154777498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4154777498
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2448669827
Short name T389
Test name
Test status
Simulation time 5055433901 ps
CPU time 44.34 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 214128 kb
Host smart-b3cf4473-ae57-4af2-b87e-f9d546cda21a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448669827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2448669827
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3793872196
Short name T462
Test name
Test status
Simulation time 264219901 ps
CPU time 10.28 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:48:20 PM PDT 24
Peak memory 211344 kb
Host smart-bee24bbd-173f-46e0-8f52-adbe5c4bdeb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793872196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3793872196
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1224672844
Short name T393
Test name
Test status
Simulation time 167640028 ps
CPU time 12.51 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:09 PM PDT 24
Peak memory 218432 kb
Host smart-f97d0d82-0952-4d55-9d9a-af4ab0158dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224672844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1224672844
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2257834065
Short name T60
Test name
Test status
Simulation time 616688478 ps
CPU time 82.32 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 212700 kb
Host smart-7ddd06d9-017e-46c2-9621-218326f211c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257834065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2257834065
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1826060550
Short name T397
Test name
Test status
Simulation time 1031609805 ps
CPU time 14.98 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:19 PM PDT 24
Peak memory 215616 kb
Host smart-08564ce4-5799-4134-b226-eb16f3a4ed2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826060550 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1826060550
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.692270304
Short name T431
Test name
Test status
Simulation time 340650853 ps
CPU time 8.14 seconds
Started Jul 25 04:47:53 PM PDT 24
Finished Jul 25 04:48:01 PM PDT 24
Peak memory 210664 kb
Host smart-d35b62ba-ac82-42d6-aed4-43a13f6cbf15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692270304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.692270304
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1259261827
Short name T468
Test name
Test status
Simulation time 1527168430 ps
CPU time 65.31 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:48:54 PM PDT 24
Peak memory 218872 kb
Host smart-e32c9dab-6441-419d-8e22-f3ed99626cfb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259261827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1259261827
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4151703918
Short name T415
Test name
Test status
Simulation time 274303395 ps
CPU time 10.02 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:51 PM PDT 24
Peak memory 211564 kb
Host smart-1f4ea207-8f35-44e4-8882-609562fc65bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151703918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4151703918
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3951597679
Short name T388
Test name
Test status
Simulation time 948612643 ps
CPU time 12.85 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:28 PM PDT 24
Peak memory 218152 kb
Host smart-b30df52f-415f-4ca3-bda0-9e16d74fbd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951597679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3951597679
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3972535999
Short name T115
Test name
Test status
Simulation time 1419396177 ps
CPU time 152.24 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 214052 kb
Host smart-566786a3-8ae5-4239-ae81-46a9c6cb2392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972535999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3972535999
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3208065110
Short name T460
Test name
Test status
Simulation time 528164080 ps
CPU time 10.53 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:48:13 PM PDT 24
Peak memory 217344 kb
Host smart-48943ef9-d67d-4e1d-9583-b9fc39ede0bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208065110 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3208065110
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3488988326
Short name T455
Test name
Test status
Simulation time 718541066 ps
CPU time 8.26 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:48:18 PM PDT 24
Peak memory 211028 kb
Host smart-c914e6ed-6168-4f33-afb6-458ab5c7580f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488988326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3488988326
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4121808898
Short name T69
Test name
Test status
Simulation time 733172225 ps
CPU time 36.91 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:48:40 PM PDT 24
Peak memory 213852 kb
Host smart-f83ae223-2e5b-40f0-99ab-8b7b23fa2e1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121808898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4121808898
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.921086636
Short name T422
Test name
Test status
Simulation time 181301353 ps
CPU time 11.88 seconds
Started Jul 25 04:47:59 PM PDT 24
Finished Jul 25 04:48:11 PM PDT 24
Peak memory 212252 kb
Host smart-7f23fbfe-554b-4fc8-ac2a-f36bce676841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921086636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.921086636
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.449465020
Short name T459
Test name
Test status
Simulation time 308402110 ps
CPU time 13.3 seconds
Started Jul 25 04:47:46 PM PDT 24
Finished Jul 25 04:47:59 PM PDT 24
Peak memory 218560 kb
Host smart-d0807b47-4db7-4b7a-b146-29c9a3d72e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449465020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.449465020
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1006809950
Short name T111
Test name
Test status
Simulation time 961349741 ps
CPU time 84.13 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:49:23 PM PDT 24
Peak memory 213604 kb
Host smart-4d661a5d-b3b1-47fa-a5a3-e9378e92d94a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006809950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1006809950
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1483645184
Short name T408
Test name
Test status
Simulation time 262811207 ps
CPU time 10.64 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:03 PM PDT 24
Peak memory 216560 kb
Host smart-840dac91-fbef-45cb-a15a-ac4fe3946057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483645184 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1483645184
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3274473160
Short name T432
Test name
Test status
Simulation time 785639919 ps
CPU time 8.14 seconds
Started Jul 25 04:48:12 PM PDT 24
Finished Jul 25 04:48:21 PM PDT 24
Peak memory 210628 kb
Host smart-0c13978e-cf22-48ea-97a3-78edcdc09156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274473160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3274473160
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2112535722
Short name T86
Test name
Test status
Simulation time 6906574192 ps
CPU time 54.38 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 214316 kb
Host smart-f3f4fbb5-eb2d-421f-abab-76b477a318fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112535722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2112535722
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1139524708
Short name T420
Test name
Test status
Simulation time 168975282 ps
CPU time 8.27 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:47:59 PM PDT 24
Peak memory 211336 kb
Host smart-8eedd29e-152b-4e92-8ac4-1aa9362541f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139524708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1139524708
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2902751721
Short name T385
Test name
Test status
Simulation time 191886908 ps
CPU time 11.79 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:48:19 PM PDT 24
Peak memory 216528 kb
Host smart-efa7df85-a977-40e4-91d7-b1b2a0a79d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902751721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2902751721
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1926618101
Short name T448
Test name
Test status
Simulation time 198557876 ps
CPU time 8.82 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 216948 kb
Host smart-06745619-aa32-4e75-809d-29740481e688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926618101 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1926618101
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4107130085
Short name T384
Test name
Test status
Simulation time 2465818871 ps
CPU time 9.81 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 211024 kb
Host smart-0c4e0da1-6ba3-45f5-b57b-41b4c49131b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107130085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4107130085
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2459472494
Short name T453
Test name
Test status
Simulation time 4321497607 ps
CPU time 56.64 seconds
Started Jul 25 04:47:53 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 218796 kb
Host smart-4b64be8b-2640-449c-9bf5-623f4bece45f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459472494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2459472494
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2982736897
Short name T99
Test name
Test status
Simulation time 1077823085 ps
CPU time 9.85 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:54 PM PDT 24
Peak memory 211028 kb
Host smart-53f28c00-5e11-45f7-8dc4-9e28f2c453d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982736897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2982736897
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.706577421
Short name T380
Test name
Test status
Simulation time 265891720 ps
CPU time 13.83 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:48:12 PM PDT 24
Peak memory 218536 kb
Host smart-d1837c45-ddff-4bad-aec1-a66d23ea0973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706577421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.706577421
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.92083599
Short name T112
Test name
Test status
Simulation time 419523093 ps
CPU time 157.88 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:50:36 PM PDT 24
Peak memory 214044 kb
Host smart-1124f9ea-f579-4ddc-90a2-4a9e4a7f8d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92083599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.92083599
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.507489180
Short name T82
Test name
Test status
Simulation time 1178308643 ps
CPU time 9.96 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:48:00 PM PDT 24
Peak memory 210548 kb
Host smart-01af3477-d27e-4a3e-9901-4e254ba1ef45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507489180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.507489180
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.76312854
Short name T411
Test name
Test status
Simulation time 253244869 ps
CPU time 10.41 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:48:21 PM PDT 24
Peak memory 210552 kb
Host smart-b0602ec9-f23f-400f-9c26-44caa6f038ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76312854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.76312854
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2978905376
Short name T391
Test name
Test status
Simulation time 514992821 ps
CPU time 17.12 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:54 PM PDT 24
Peak memory 211820 kb
Host smart-43362699-886a-41a2-8b80-e6101af70788
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978905376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2978905376
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3677009518
Short name T465
Test name
Test status
Simulation time 747724373 ps
CPU time 8.58 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 217336 kb
Host smart-c06cf677-e8ad-4e53-853a-e5acefbf38c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677009518 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3677009518
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.322148723
Short name T464
Test name
Test status
Simulation time 528365447 ps
CPU time 9.95 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 210472 kb
Host smart-bddc1c56-c477-42f2-840d-67a6814f119c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322148723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.322148723
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2165425101
Short name T439
Test name
Test status
Simulation time 663049447 ps
CPU time 8.09 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:47:57 PM PDT 24
Peak memory 210404 kb
Host smart-3c6c96d4-4b04-42e5-ac21-041cfcbe8b0d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165425101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2165425101
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2109967382
Short name T405
Test name
Test status
Simulation time 988398379 ps
CPU time 9.63 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:46 PM PDT 24
Peak memory 210380 kb
Host smart-96b60403-c305-478a-92aa-a65f193ba69c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109967382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2109967382
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3272438040
Short name T101
Test name
Test status
Simulation time 3615495461 ps
CPU time 42.52 seconds
Started Jul 25 04:47:51 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 213748 kb
Host smart-27e70713-0bb0-48a9-9086-a703ac22ff6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272438040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3272438040
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.125220140
Short name T94
Test name
Test status
Simulation time 3949756381 ps
CPU time 15.53 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:58 PM PDT 24
Peak memory 212772 kb
Host smart-ce7580ea-3cb9-4981-8fec-719a7c2786a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125220140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.125220140
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3779729596
Short name T412
Test name
Test status
Simulation time 248945734 ps
CPU time 12.66 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 217364 kb
Host smart-4a7e82d4-f5eb-4e75-88dd-a98728f7f3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779729596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3779729596
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.34844735
Short name T59
Test name
Test status
Simulation time 265065143 ps
CPU time 80.61 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:49:25 PM PDT 24
Peak memory 212640 kb
Host smart-4d24be41-b852-4896-8a2c-b1d05afeef94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34844735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg
_err.34844735
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1099642228
Short name T413
Test name
Test status
Simulation time 517689616 ps
CPU time 9.56 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:53 PM PDT 24
Peak memory 210564 kb
Host smart-8351ce0f-0fa4-4979-bcef-d02e77bc9a76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099642228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1099642228
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3489206463
Short name T437
Test name
Test status
Simulation time 259756535 ps
CPU time 9.84 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:41 PM PDT 24
Peak memory 210556 kb
Host smart-c011b13c-7106-4fd9-aaf5-368ef984ea4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489206463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3489206463
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.987837159
Short name T467
Test name
Test status
Simulation time 1674720736 ps
CPU time 17.3 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:48:22 PM PDT 24
Peak memory 212048 kb
Host smart-354523bc-6ba7-459b-8fba-89c58555620b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987837159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.987837159
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2820359559
Short name T427
Test name
Test status
Simulation time 179535468 ps
CPU time 8.47 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 213720 kb
Host smart-3e161e66-888e-4dfc-8563-04ff652897a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820359559 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2820359559
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1376839076
Short name T409
Test name
Test status
Simulation time 1764686988 ps
CPU time 9.74 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:48 PM PDT 24
Peak memory 211224 kb
Host smart-af823256-dddd-436d-b931-c28214542141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376839076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1376839076
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1650858630
Short name T381
Test name
Test status
Simulation time 1458660437 ps
CPU time 9.7 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:56 PM PDT 24
Peak memory 210392 kb
Host smart-5d855275-6e37-4816-9dfe-a218ed7bb45c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650858630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1650858630
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3058473537
Short name T428
Test name
Test status
Simulation time 252725146 ps
CPU time 9.51 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:02 PM PDT 24
Peak memory 210396 kb
Host smart-4b047e39-b90b-4864-9c5e-7131ed3020ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058473537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3058473537
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1045083666
Short name T78
Test name
Test status
Simulation time 8553875607 ps
CPU time 55.88 seconds
Started Jul 25 04:51:17 PM PDT 24
Finished Jul 25 04:52:13 PM PDT 24
Peak memory 218908 kb
Host smart-28223e61-279b-4754-a655-7d4709d5d8cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045083666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1045083666
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.699713294
Short name T452
Test name
Test status
Simulation time 259388029 ps
CPU time 10.12 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 211388 kb
Host smart-8e0728d1-b160-4eaf-81a4-61010ddbe1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699713294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.699713294
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2577174954
Short name T395
Test name
Test status
Simulation time 175272039 ps
CPU time 10.83 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:48:24 PM PDT 24
Peak memory 217312 kb
Host smart-b14ce551-4b20-437d-b45c-7771692c84f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577174954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2577174954
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3754985562
Short name T58
Test name
Test status
Simulation time 422075752 ps
CPU time 81.36 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 213540 kb
Host smart-06d2e100-86e9-4d37-bf59-eb8abc2b2135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754985562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3754985562
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3724388319
Short name T433
Test name
Test status
Simulation time 989868385 ps
CPU time 10.04 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:53 PM PDT 24
Peak memory 210816 kb
Host smart-1c38bd2b-c408-44ac-8d41-2d64cad143b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724388319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3724388319
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3226969286
Short name T463
Test name
Test status
Simulation time 169132330 ps
CPU time 8.7 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 210648 kb
Host smart-8c32c8ae-4f27-4c8a-bb10-28b2878c235c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226969286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3226969286
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3814619792
Short name T76
Test name
Test status
Simulation time 3590171138 ps
CPU time 17.31 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:49 PM PDT 24
Peak memory 211748 kb
Host smart-31bba7f9-fd85-4e19-9372-4ac04a03510b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814619792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3814619792
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1096296933
Short name T417
Test name
Test status
Simulation time 4124270418 ps
CPU time 15.71 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:59 PM PDT 24
Peak memory 216932 kb
Host smart-aadf2162-a409-4bed-ad8d-3b1adcdc5dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096296933 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1096296933
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.782691251
Short name T71
Test name
Test status
Simulation time 241651275 ps
CPU time 8.18 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 210512 kb
Host smart-e95ae48c-d7ef-4d7b-a102-400c6f4a4e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782691251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.782691251
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1239699584
Short name T424
Test name
Test status
Simulation time 169203871 ps
CPU time 8.14 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 210492 kb
Host smart-8a2cba2c-b71e-4008-886a-d705695f3e5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239699584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1239699584
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4285168692
Short name T450
Test name
Test status
Simulation time 1937534785 ps
CPU time 14.58 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:59 PM PDT 24
Peak memory 210672 kb
Host smart-f8331d2d-4818-48e4-af84-72f05038b2f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285168692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4285168692
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1835718736
Short name T449
Test name
Test status
Simulation time 693862643 ps
CPU time 38.1 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 218756 kb
Host smart-0ac58249-0ebd-4cf2-aac9-6765a749f595
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835718736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1835718736
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4185020438
Short name T446
Test name
Test status
Simulation time 177843266 ps
CPU time 12.32 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:04 PM PDT 24
Peak memory 212452 kb
Host smart-2b214ba8-9e95-4b46-a45a-90069a4791fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185020438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4185020438
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2913021840
Short name T394
Test name
Test status
Simulation time 1029197583 ps
CPU time 14.45 seconds
Started Jul 25 04:47:53 PM PDT 24
Finished Jul 25 04:48:07 PM PDT 24
Peak memory 217668 kb
Host smart-86221b90-1948-4582-a8ce-220cc9f9811c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913021840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2913021840
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.652845224
Short name T117
Test name
Test status
Simulation time 818051271 ps
CPU time 154.28 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:50:50 PM PDT 24
Peak memory 214036 kb
Host smart-6fd6a0ed-5994-450d-8d14-cae200bae9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652845224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.652845224
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4141858692
Short name T416
Test name
Test status
Simulation time 689082560 ps
CPU time 8.42 seconds
Started Jul 25 04:47:59 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 214732 kb
Host smart-412655a6-4d95-434f-a724-4d59220d81fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141858692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4141858692
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1579049660
Short name T426
Test name
Test status
Simulation time 254749850 ps
CPU time 9.76 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 211096 kb
Host smart-dc289b5c-fb7e-4897-8c6a-29a12e7e8e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579049660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1579049660
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1473993174
Short name T85
Test name
Test status
Simulation time 3048484232 ps
CPU time 66.64 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 215304 kb
Host smart-59a299e4-6519-4bf5-991d-edc5e42c5f2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473993174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1473993174
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2105865906
Short name T445
Test name
Test status
Simulation time 1079939784 ps
CPU time 9.95 seconds
Started Jul 25 04:47:47 PM PDT 24
Finished Jul 25 04:47:57 PM PDT 24
Peak memory 211024 kb
Host smart-d1452d24-dd89-45a8-93cd-18631a22a644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105865906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2105865906
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3221758185
Short name T378
Test name
Test status
Simulation time 506570667 ps
CPU time 12.4 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:47:55 PM PDT 24
Peak memory 217232 kb
Host smart-1fb39300-ac32-48e0-a0bf-35f958d273e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221758185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3221758185
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1277295434
Short name T414
Test name
Test status
Simulation time 3987146725 ps
CPU time 82.52 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:49:03 PM PDT 24
Peak memory 213560 kb
Host smart-f721dcae-b741-46b5-9b39-f6fa6da411aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277295434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1277295434
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1754886894
Short name T429
Test name
Test status
Simulation time 293940018 ps
CPU time 10.39 seconds
Started Jul 25 04:48:12 PM PDT 24
Finished Jul 25 04:48:22 PM PDT 24
Peak memory 216972 kb
Host smart-7a92ae30-37fa-418d-951a-1064cb899ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754886894 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1754886894
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2805275393
Short name T80
Test name
Test status
Simulation time 346124139 ps
CPU time 8 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 211276 kb
Host smart-83520365-d48e-4d78-8425-de27a74a90fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805275393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2805275393
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1195334197
Short name T72
Test name
Test status
Simulation time 2112140445 ps
CPU time 55.68 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 215160 kb
Host smart-3ee26ad6-a72b-49c4-9251-483ecaa695ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195334197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1195334197
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.241509753
Short name T96
Test name
Test status
Simulation time 1006270133 ps
CPU time 13.59 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:59 PM PDT 24
Peak memory 211532 kb
Host smart-a26c2e60-c48b-4473-b771-52a4a779b5f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241509753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.241509753
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2962269643
Short name T379
Test name
Test status
Simulation time 986712361 ps
CPU time 15.14 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:48:03 PM PDT 24
Peak memory 217540 kb
Host smart-fc7143a1-326f-4080-9917-6525937eca70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962269643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2962269643
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3233467723
Short name T444
Test name
Test status
Simulation time 234178973 ps
CPU time 81.49 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 212684 kb
Host smart-61b1f904-4fdd-4fcf-8bb0-06ac22444dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233467723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3233467723
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3424011459
Short name T404
Test name
Test status
Simulation time 274078684 ps
CPU time 10.66 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:48:13 PM PDT 24
Peak memory 217228 kb
Host smart-a9c689bf-50e0-46a4-b1ea-4ee0fc648fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424011459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3424011459
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1410529248
Short name T466
Test name
Test status
Simulation time 201393265 ps
CPU time 8.17 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 211012 kb
Host smart-f4103d2d-e707-4738-9a69-905c9816601c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410529248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1410529248
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2217889187
Short name T103
Test name
Test status
Simulation time 2856425274 ps
CPU time 37.91 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:48:27 PM PDT 24
Peak memory 213868 kb
Host smart-7fcb19df-962e-4643-9b98-82c1b57e16ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217889187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2217889187
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1218336278
Short name T100
Test name
Test status
Simulation time 502259617 ps
CPU time 13.7 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:06 PM PDT 24
Peak memory 212548 kb
Host smart-0f467cf0-bf28-4792-b0ae-169fc29b5ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218336278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1218336278
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.464956744
Short name T410
Test name
Test status
Simulation time 168030782 ps
CPU time 11.68 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:48:02 PM PDT 24
Peak memory 216984 kb
Host smart-ea7f5198-617a-4139-a935-09c85e8777b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464956744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.464956744
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3321064434
Short name T109
Test name
Test status
Simulation time 919677046 ps
CPU time 80.63 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 213728 kb
Host smart-8e6a0b98-f6c4-4d01-8823-a6eb4e18b826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321064434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3321064434
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3353742505
Short name T454
Test name
Test status
Simulation time 277582676 ps
CPU time 10.96 seconds
Started Jul 25 04:47:52 PM PDT 24
Finished Jul 25 04:48:03 PM PDT 24
Peak memory 217608 kb
Host smart-3ba06af1-85c2-4d81-96a2-c877ae80a3f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353742505 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3353742505
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1286209593
Short name T79
Test name
Test status
Simulation time 663474351 ps
CPU time 8.2 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 210472 kb
Host smart-d8dadc54-2992-449f-9d23-6953b7a46d3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286209593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1286209593
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1135031472
Short name T87
Test name
Test status
Simulation time 1044952832 ps
CPU time 54.76 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 215076 kb
Host smart-24ea2541-6598-4ff1-9422-5e5cb490c09b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135031472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1135031472
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1068102879
Short name T97
Test name
Test status
Simulation time 256844195 ps
CPU time 10.41 seconds
Started Jul 25 04:47:53 PM PDT 24
Finished Jul 25 04:48:04 PM PDT 24
Peak memory 211148 kb
Host smart-52c32990-9a5c-41fa-9e6a-c9eaaa2561b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068102879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1068102879
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1699623932
Short name T383
Test name
Test status
Simulation time 984631988 ps
CPU time 18.24 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:48:13 PM PDT 24
Peak memory 218220 kb
Host smart-bdab405a-aea8-49a4-9eeb-278ec2f63fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699623932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1699623932
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2663963693
Short name T430
Test name
Test status
Simulation time 266253273 ps
CPU time 10.23 seconds
Started Jul 25 04:47:46 PM PDT 24
Finished Jul 25 04:47:56 PM PDT 24
Peak memory 216708 kb
Host smart-a1a85bd3-dfc6-4b35-a961-74b94c561504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663963693 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2663963693
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2492554317
Short name T81
Test name
Test status
Simulation time 353045108 ps
CPU time 8.3 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 211296 kb
Host smart-c8a28d05-7e94-43b7-9214-241d9e5bff78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492554317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2492554317
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1184653036
Short name T98
Test name
Test status
Simulation time 1552662494 ps
CPU time 65.41 seconds
Started Jul 25 04:48:00 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 218800 kb
Host smart-3f4b6f36-6430-45d9-b296-076e948d8e2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184653036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1184653036
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2064807251
Short name T65
Test name
Test status
Simulation time 2744451076 ps
CPU time 8.18 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:48:03 PM PDT 24
Peak memory 211288 kb
Host smart-a4a87d31-6d6e-465d-a244-ee09f89a1edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064807251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2064807251
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2879460967
Short name T400
Test name
Test status
Simulation time 1401449789 ps
CPU time 19.45 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 218476 kb
Host smart-c18052a7-08a9-4ec8-a09d-ceebf839c7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879460967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2879460967
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.347800973
Short name T327
Test name
Test status
Simulation time 1035036055 ps
CPU time 10.12 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:26 PM PDT 24
Peak memory 218816 kb
Host smart-334d2fed-1003-4a71-8758-176aac03e093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347800973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.347800973
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4123392541
Short name T366
Test name
Test status
Simulation time 2802294001 ps
CPU time 179.39 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:51:08 PM PDT 24
Peak memory 234940 kb
Host smart-59627a86-702a-45f6-ba17-1f71245bee38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123392541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4123392541
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4031728201
Short name T361
Test name
Test status
Simulation time 2033599956 ps
CPU time 32.47 seconds
Started Jul 25 04:48:01 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219800 kb
Host smart-5dfedab9-43aa-4165-b967-50fbdfb43775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031728201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4031728201
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.254093812
Short name T370
Test name
Test status
Simulation time 521475584 ps
CPU time 12.5 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:48:02 PM PDT 24
Peak memory 219884 kb
Host smart-799f7d48-244a-463e-905f-16e3ff8b6ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254093812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.254093812
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3008812045
Short name T32
Test name
Test status
Simulation time 1621633446 ps
CPU time 227.48 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:51:53 PM PDT 24
Peak memory 239448 kb
Host smart-49527912-eae5-4b5b-96cc-450fae2a860a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008812045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3008812045
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3418233184
Short name T224
Test name
Test status
Simulation time 1014708425 ps
CPU time 23.54 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:20 PM PDT 24
Peak memory 219224 kb
Host smart-ec5ff0a7-57c4-45bb-aa67-b55e90dab837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418233184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3418233184
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1918317551
Short name T177
Test name
Test status
Simulation time 1263507227 ps
CPU time 58.72 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 219752 kb
Host smart-ff48b2c4-b8bc-4020-8891-61aea171de05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918317551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1918317551
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1375233880
Short name T238
Test name
Test status
Simulation time 347675443 ps
CPU time 8.38 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:47:58 PM PDT 24
Peak memory 218880 kb
Host smart-5c111683-8ad5-4f5a-bd1d-cb73ada6c27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375233880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1375233880
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1440815825
Short name T144
Test name
Test status
Simulation time 22254620953 ps
CPU time 345.62 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:53:44 PM PDT 24
Peak memory 237364 kb
Host smart-54402c5a-a7e3-4816-8687-4e47bb387d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440815825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1440815825
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.773262791
Short name T276
Test name
Test status
Simulation time 273030362 ps
CPU time 12.57 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:21 PM PDT 24
Peak memory 219764 kb
Host smart-50378086-dc49-49eb-81cd-1ed5afe17c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773262791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.773262791
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3718245175
Short name T31
Test name
Test status
Simulation time 377973282 ps
CPU time 222.3 seconds
Started Jul 25 04:48:14 PM PDT 24
Finished Jul 25 04:51:56 PM PDT 24
Peak memory 239736 kb
Host smart-4271fe2d-de4b-40cd-b321-cec2bdcee95e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718245175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3718245175
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1025987279
Short name T294
Test name
Test status
Simulation time 2121236399 ps
CPU time 23.05 seconds
Started Jul 25 04:47:56 PM PDT 24
Finished Jul 25 04:48:20 PM PDT 24
Peak memory 219228 kb
Host smart-1c40da84-b668-4bb1-a601-7aeffd9044c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025987279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1025987279
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3871085900
Short name T306
Test name
Test status
Simulation time 1041454025 ps
CPU time 37.26 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:35 PM PDT 24
Peak memory 221152 kb
Host smart-34637313-371b-4d56-9158-7763e9f15708
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871085900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3871085900
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2036982407
Short name T285
Test name
Test status
Simulation time 992952552 ps
CPU time 10.08 seconds
Started Jul 25 04:48:11 PM PDT 24
Finished Jul 25 04:48:21 PM PDT 24
Peak memory 217900 kb
Host smart-db2893ad-68e8-4313-80c2-83dce43199df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036982407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2036982407
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3124897414
Short name T175
Test name
Test status
Simulation time 28697647790 ps
CPU time 251.87 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:52:18 PM PDT 24
Peak memory 219952 kb
Host smart-fa076fc2-cb46-4441-855d-016ce65c5720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124897414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3124897414
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2613139374
Short name T237
Test name
Test status
Simulation time 1577612291 ps
CPU time 19.27 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 219788 kb
Host smart-6769995c-f3bc-428a-b33f-6cccc510c0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613139374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2613139374
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3307044430
Short name T174
Test name
Test status
Simulation time 1008089781 ps
CPU time 17.04 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 219072 kb
Host smart-c3d43da4-7615-423d-9c12-87a0417cd499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307044430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3307044430
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3871017203
Short name T90
Test name
Test status
Simulation time 2451099178 ps
CPU time 20.37 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 219372 kb
Host smart-b630ee49-d146-4eac-9654-fa2f8bea7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871017203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3871017203
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2583067477
Short name T191
Test name
Test status
Simulation time 371759396 ps
CPU time 24.28 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 219180 kb
Host smart-45bfd9b8-52b3-4e04-9328-168ab1c67d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583067477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2583067477
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1166610834
Short name T160
Test name
Test status
Simulation time 360523141 ps
CPU time 8.33 seconds
Started Jul 25 04:48:30 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 218832 kb
Host smart-342837b3-9f04-481b-89d8-8f83384ff625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166610834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1166610834
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2709732171
Short name T269
Test name
Test status
Simulation time 22303756910 ps
CPU time 218.64 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:52:00 PM PDT 24
Peak memory 230316 kb
Host smart-1f9a513c-395d-4ec6-8791-be888887cfa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709732171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2709732171
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3913094605
Short name T11
Test name
Test status
Simulation time 518261651 ps
CPU time 22.41 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219808 kb
Host smart-a2ee5558-b3f8-40dd-9712-d59d934b94fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913094605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3913094605
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1292289097
Short name T133
Test name
Test status
Simulation time 269545991 ps
CPU time 12.48 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 219768 kb
Host smart-6af229f3-515c-42fa-b77e-476d6579644b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292289097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1292289097
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2706404968
Short name T271
Test name
Test status
Simulation time 2093249307 ps
CPU time 24.52 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:50 PM PDT 24
Peak memory 218780 kb
Host smart-8ce34773-1c18-4d1c-8e4b-c3dd36e40a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706404968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2706404968
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.903495620
Short name T22
Test name
Test status
Simulation time 287367575 ps
CPU time 13.07 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 219176 kb
Host smart-1c4f1a9f-dd31-4e64-93da-3c8994e7f3af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903495620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.903495620
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2337243283
Short name T184
Test name
Test status
Simulation time 1177171613 ps
CPU time 8.32 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 218788 kb
Host smart-9918fa91-8a28-486b-81e9-a9b670657018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337243283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2337243283
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.990184804
Short name T189
Test name
Test status
Simulation time 2622436404 ps
CPU time 149.16 seconds
Started Jul 25 04:48:18 PM PDT 24
Finished Jul 25 04:50:47 PM PDT 24
Peak memory 225196 kb
Host smart-4c3607a5-f3c1-49d7-964b-7e30711d43a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990184804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.990184804
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3328389841
Short name T320
Test name
Test status
Simulation time 1034645101 ps
CPU time 21.83 seconds
Started Jul 25 04:48:17 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 219712 kb
Host smart-56ef248f-a7dd-4666-84b0-adc3a017ac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328389841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3328389841
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2051883491
Short name T307
Test name
Test status
Simulation time 1001873116 ps
CPU time 12.34 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219792 kb
Host smart-426ecb31-d14e-46fd-8c47-717a09dca6d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051883491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2051883491
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2813273787
Short name T75
Test name
Test status
Simulation time 2027538024 ps
CPU time 35.01 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 219248 kb
Host smart-2da1ef8b-a5c9-4d96-a8a3-25911387fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813273787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2813273787
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2975316449
Short name T264
Test name
Test status
Simulation time 1712219400 ps
CPU time 53.22 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:49:09 PM PDT 24
Peak memory 220072 kb
Host smart-eb4c6033-1be8-40fc-b67f-1d10b920f2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975316449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2975316449
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1937025070
Short name T10
Test name
Test status
Simulation time 988667824 ps
CPU time 9.86 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 218792 kb
Host smart-6b117182-0fc0-42e0-9daa-f847158e024e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937025070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1937025070
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3771340612
Short name T341
Test name
Test status
Simulation time 7849746977 ps
CPU time 110.4 seconds
Started Jul 25 04:48:18 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 236120 kb
Host smart-6278d889-0e38-403b-9a85-8fdc1228d3fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771340612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3771340612
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3578821616
Short name T300
Test name
Test status
Simulation time 182708561 ps
CPU time 10.49 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 219872 kb
Host smart-4ba04dff-6965-4f34-80b7-f79cdfa9659b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578821616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3578821616
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.253233326
Short name T207
Test name
Test status
Simulation time 3972620205 ps
CPU time 37.43 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219336 kb
Host smart-2f455475-efba-401c-ba72-c7fe5887b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253233326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.253233326
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3377449065
Short name T126
Test name
Test status
Simulation time 691153730 ps
CPU time 8.31 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:48:31 PM PDT 24
Peak memory 218768 kb
Host smart-47b389ec-5e95-4d89-87c9-2689e1f8e184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377449065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3377449065
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.879832746
Short name T227
Test name
Test status
Simulation time 64627940821 ps
CPU time 333.45 seconds
Started Jul 25 04:48:17 PM PDT 24
Finished Jul 25 04:53:51 PM PDT 24
Peak memory 219548 kb
Host smart-3fe402df-eb47-4d08-b6e2-76c6f74103f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879832746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.879832746
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1752012179
Short name T196
Test name
Test status
Simulation time 1127878539 ps
CPU time 22.52 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219868 kb
Host smart-44c03dec-80e8-4628-8c50-4086c008bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752012179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1752012179
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3410433108
Short name T303
Test name
Test status
Simulation time 1025084835 ps
CPU time 12.16 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 219768 kb
Host smart-cbc8ceaa-b686-4192-a456-aab416ca026a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410433108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3410433108
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4162523662
Short name T162
Test name
Test status
Simulation time 504670820 ps
CPU time 23.9 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 219276 kb
Host smart-49a944b4-e03e-4a42-ae68-22b1da303cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162523662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4162523662
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.38228711
Short name T340
Test name
Test status
Simulation time 1662037107 ps
CPU time 14.52 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219268 kb
Host smart-71a2b6af-445c-4ad6-9e24-8cd9983eaf52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38228711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.38228711
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3893039257
Short name T236
Test name
Test status
Simulation time 254376146 ps
CPU time 10.17 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 218868 kb
Host smart-e6e28e2c-4e16-4d0b-b6aa-c238e243378a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893039257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3893039257
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1559309359
Short name T215
Test name
Test status
Simulation time 6878608837 ps
CPU time 262.84 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:52:42 PM PDT 24
Peak memory 238272 kb
Host smart-cbb6bb26-75ff-40b5-a56f-2f1e839a5e10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559309359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1559309359
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3194523147
Short name T143
Test name
Test status
Simulation time 2487184969 ps
CPU time 23.06 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:48:52 PM PDT 24
Peak memory 219852 kb
Host smart-1167be93-8419-4c73-ba11-c021389e295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194523147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3194523147
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2872927189
Short name T102
Test name
Test status
Simulation time 1064033751 ps
CPU time 12.33 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:27 PM PDT 24
Peak memory 219804 kb
Host smart-a7cad77d-4881-479c-9430-9f69a997e101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872927189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2872927189
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2023743148
Short name T40
Test name
Test status
Simulation time 691760306 ps
CPU time 20.33 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 219232 kb
Host smart-bfce3edd-bd91-4af9-a447-09daebb1be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023743148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2023743148
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2310644540
Short name T149
Test name
Test status
Simulation time 1060020226 ps
CPU time 47.34 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 219736 kb
Host smart-77e1a4c4-e6be-4bfe-a353-01ff0137f1e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310644540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2310644540
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2679124731
Short name T180
Test name
Test status
Simulation time 688377490 ps
CPU time 8.43 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 217828 kb
Host smart-a78c849b-978e-4e22-98a4-93753ec258ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679124731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2679124731
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3292759642
Short name T235
Test name
Test status
Simulation time 7842654748 ps
CPU time 112.21 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 231136 kb
Host smart-2fc3fea1-184d-46dc-859a-6d4905b0be6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292759642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3292759642
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1817400768
Short name T239
Test name
Test status
Simulation time 1102169455 ps
CPU time 22.61 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 219808 kb
Host smart-e969c83c-2b0d-4619-8c51-816300d59ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817400768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1817400768
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.77882566
Short name T163
Test name
Test status
Simulation time 717087304 ps
CPU time 10.29 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:35 PM PDT 24
Peak memory 219780 kb
Host smart-aa13300f-494a-4633-8572-9c07cf7720c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77882566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.77882566
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1116190920
Short name T193
Test name
Test status
Simulation time 2117771963 ps
CPU time 23.52 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:48:37 PM PDT 24
Peak memory 219324 kb
Host smart-65b394ee-7aa9-446c-afa4-e199681efa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116190920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1116190920
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3573974809
Short name T290
Test name
Test status
Simulation time 4328048825 ps
CPU time 52.05 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:49:12 PM PDT 24
Peak memory 219828 kb
Host smart-1262ef61-6a1a-470d-a2e3-84f6e2911287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573974809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3573974809
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3443687286
Short name T265
Test name
Test status
Simulation time 245806179936 ps
CPU time 2480.01 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 05:29:47 PM PDT 24
Peak memory 243472 kb
Host smart-14355fd5-4236-497f-a18e-5a0f4d6c305a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443687286 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3443687286
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3985320372
Short name T123
Test name
Test status
Simulation time 175009337 ps
CPU time 8.37 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 218860 kb
Host smart-dbe08bd1-1a69-40c1-8e89-88574b1ac40b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985320372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3985320372
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1892635222
Short name T209
Test name
Test status
Simulation time 10190880489 ps
CPU time 121.18 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 240084 kb
Host smart-81d85944-f6c8-4ad6-a820-8abe9a519cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892635222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1892635222
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.531763307
Short name T50
Test name
Test status
Simulation time 625579970 ps
CPU time 19.36 seconds
Started Jul 25 04:48:14 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219808 kb
Host smart-eec1e5a6-888e-44b7-a4e7-30cee3dbbdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531763307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.531763307
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2366387745
Short name T363
Test name
Test status
Simulation time 1111530156 ps
CPU time 12.23 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 219812 kb
Host smart-fe22edae-eedb-4eb8-90ab-02968e6a53ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366387745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2366387745
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3208657779
Short name T296
Test name
Test status
Simulation time 2033607696 ps
CPU time 22.88 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 219240 kb
Host smart-d759026f-97fe-4299-b0b8-a84d52309110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208657779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3208657779
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1227341508
Short name T168
Test name
Test status
Simulation time 1319165970 ps
CPU time 59.68 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 219744 kb
Host smart-7360e349-5440-4dbf-941e-7f15f1893654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227341508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1227341508
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.327940685
Short name T302
Test name
Test status
Simulation time 2812737590 ps
CPU time 133.85 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:50:47 PM PDT 24
Peak memory 219928 kb
Host smart-1eb1f279-3e4a-4c4f-8a1d-371714d218ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327940685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.327940685
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1099471769
Short name T321
Test name
Test status
Simulation time 1577940601 ps
CPU time 18.69 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219832 kb
Host smart-98f29397-1024-4a3e-9853-f568497627a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099471769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1099471769
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.619808951
Short name T277
Test name
Test status
Simulation time 523687858 ps
CPU time 12.14 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:48:52 PM PDT 24
Peak memory 219760 kb
Host smart-232b3f11-2f97-485e-a214-cbaf4cd92772
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619808951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.619808951
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1681793854
Short name T268
Test name
Test status
Simulation time 543870359 ps
CPU time 23.97 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219248 kb
Host smart-faa5c423-430c-4a1d-a43a-65c2312816ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681793854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1681793854
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3761353746
Short name T178
Test name
Test status
Simulation time 2133261876 ps
CPU time 33.05 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 219700 kb
Host smart-0e8e727c-c33b-4180-aef8-128ce02be2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761353746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3761353746
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3401113426
Short name T1
Test name
Test status
Simulation time 259159676 ps
CPU time 10.06 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:37 PM PDT 24
Peak memory 218864 kb
Host smart-396b9fb2-fe71-4638-bdf7-e6d52f643ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401113426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3401113426
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1915086706
Short name T355
Test name
Test status
Simulation time 10176288399 ps
CPU time 256.45 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:52:37 PM PDT 24
Peak memory 219928 kb
Host smart-91c41c7f-019f-40b8-904e-db6a2b35874c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915086706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1915086706
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.578868428
Short name T367
Test name
Test status
Simulation time 346274088 ps
CPU time 19.13 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 219760 kb
Host smart-988278b0-6a11-45ae-a1c3-159b31244324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578868428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.578868428
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.647403308
Short name T202
Test name
Test status
Simulation time 731225710 ps
CPU time 10.65 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219740 kb
Host smart-23e28fee-7996-4a64-94cc-d0bd33e4d2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647403308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.647403308
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2584989093
Short name T141
Test name
Test status
Simulation time 1806627979 ps
CPU time 20.06 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 219304 kb
Host smart-896d42bf-38ba-49d4-a25e-a36ff99d2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584989093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2584989093
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3807040231
Short name T336
Test name
Test status
Simulation time 545449607 ps
CPU time 19.21 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219660 kb
Host smart-045027cf-c25b-4c26-a600-3abe235cbbb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807040231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3807040231
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1873101190
Short name T188
Test name
Test status
Simulation time 327189818 ps
CPU time 8.57 seconds
Started Jul 25 04:48:00 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 218804 kb
Host smart-c3ae630a-9a33-4fe1-8e49-b367cbdf310e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873101190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1873101190
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.92684809
Short name T371
Test name
Test status
Simulation time 1927674163 ps
CPU time 129.27 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 239160 kb
Host smart-fbf77354-f423-48f2-a234-01948d3b13bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92684809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_cor
rupt_sig_fatal_chk.92684809
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4162699489
Short name T131
Test name
Test status
Simulation time 518243903 ps
CPU time 22.77 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:48:30 PM PDT 24
Peak memory 219756 kb
Host smart-f51b7c37-b4f1-4f84-8712-1766fd49d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162699489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4162699489
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.956152655
Short name T308
Test name
Test status
Simulation time 179392074 ps
CPU time 10.68 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:48:16 PM PDT 24
Peak memory 219808 kb
Host smart-129d8b63-edd7-423f-b787-49122f311ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956152655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.956152655
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1877529900
Short name T27
Test name
Test status
Simulation time 222795485 ps
CPU time 117.05 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 239036 kb
Host smart-15f5e059-7102-45f2-a059-f41d72a21032
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877529900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1877529900
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3424013528
Short name T208
Test name
Test status
Simulation time 1816300514 ps
CPU time 23.25 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:28 PM PDT 24
Peak memory 219276 kb
Host smart-f570a565-dee4-409d-b1a4-424cf0e71c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424013528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3424013528
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1455127230
Short name T155
Test name
Test status
Simulation time 3166270828 ps
CPU time 39.64 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:48:42 PM PDT 24
Peak memory 219780 kb
Host smart-6896dcd5-c35e-4318-abaf-3cf3960c1d84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455127230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1455127230
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.107756757
Short name T122
Test name
Test status
Simulation time 176555086 ps
CPU time 8.28 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:48:42 PM PDT 24
Peak memory 219748 kb
Host smart-e7056394-56c6-47fe-b9ca-5a955e5ef4c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107756757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.107756757
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3042917176
Short name T164
Test name
Test status
Simulation time 689812893 ps
CPU time 19.17 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219784 kb
Host smart-3996def4-1c52-4c15-a8d2-d955a2fbe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042917176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3042917176
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3477148507
Short name T312
Test name
Test status
Simulation time 4516392874 ps
CPU time 16.78 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219516 kb
Host smart-0deac5aa-ef00-47c9-b7b7-82e83cd819d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477148507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3477148507
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2988938061
Short name T229
Test name
Test status
Simulation time 352388375 ps
CPU time 19.44 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:47 PM PDT 24
Peak memory 219160 kb
Host smart-eb5a7de9-c797-47da-9d7b-d3748f7830c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988938061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2988938061
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2475772039
Short name T170
Test name
Test status
Simulation time 561258261 ps
CPU time 32.75 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:49:08 PM PDT 24
Peak memory 219856 kb
Host smart-98cd05f6-a94c-4b3c-b8fa-3fab397b4743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475772039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2475772039
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3471640634
Short name T89
Test name
Test status
Simulation time 171501366 ps
CPU time 8.58 seconds
Started Jul 25 04:48:39 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 218884 kb
Host smart-5191d9c0-0fe2-413b-85c1-df96f871c247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471640634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3471640634
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3708171933
Short name T360
Test name
Test status
Simulation time 24953653986 ps
CPU time 319.28 seconds
Started Jul 25 04:48:20 PM PDT 24
Finished Jul 25 04:53:40 PM PDT 24
Peak memory 226104 kb
Host smart-1c54f8fa-3338-4a28-95ab-334e39274bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708171933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3708171933
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2913804635
Short name T172
Test name
Test status
Simulation time 347467081 ps
CPU time 19.68 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:47 PM PDT 24
Peak memory 219792 kb
Host smart-0b513fa0-5a47-4c55-8925-2b517f636230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913804635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2913804635
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1491165995
Short name T299
Test name
Test status
Simulation time 180731610 ps
CPU time 10.29 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:27 PM PDT 24
Peak memory 219744 kb
Host smart-bcc3b29f-ba95-4ca5-8166-08a9e60af9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491165995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1491165995
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3932588988
Short name T195
Test name
Test status
Simulation time 350351223 ps
CPU time 19.8 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 218764 kb
Host smart-fd4a78e2-4f87-4853-ac4b-5b349cff7e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932588988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3932588988
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2881399900
Short name T232
Test name
Test status
Simulation time 6266192511 ps
CPU time 51.08 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:49:18 PM PDT 24
Peak memory 219952 kb
Host smart-7aa557ae-0ea2-430b-b073-8ae1613ba298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881399900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2881399900
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1108593827
Short name T310
Test name
Test status
Simulation time 37353154436 ps
CPU time 711.23 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 05:00:17 PM PDT 24
Peak memory 236312 kb
Host smart-fb0a1edb-840b-43cc-93a3-171410c3a6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108593827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1108593827
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1332718044
Short name T57
Test name
Test status
Simulation time 2745891339 ps
CPU time 8.47 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 218840 kb
Host smart-52f9c457-0e5f-44f5-9cec-197304ec8a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332718044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1332718044
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3286997044
Short name T231
Test name
Test status
Simulation time 12391825126 ps
CPU time 264.19 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 237112 kb
Host smart-09b38937-26e1-4c56-a9cf-0e0666653580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286997044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3286997044
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.629617019
Short name T197
Test name
Test status
Simulation time 3298926829 ps
CPU time 22.58 seconds
Started Jul 25 04:48:31 PM PDT 24
Finished Jul 25 04:48:54 PM PDT 24
Peak memory 219868 kb
Host smart-e351079e-696c-49da-8b00-1ae09ac0612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629617019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.629617019
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1966814503
Short name T318
Test name
Test status
Simulation time 643227422 ps
CPU time 10.36 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 219884 kb
Host smart-953ebb9a-e66f-438b-b33b-6b0c8eb9fe3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966814503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1966814503
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2201576993
Short name T365
Test name
Test status
Simulation time 528303966 ps
CPU time 23.05 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:47 PM PDT 24
Peak memory 219240 kb
Host smart-cc82d1e7-e50b-4376-bf2b-f31b5ae5916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201576993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2201576993
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2101601707
Short name T37
Test name
Test status
Simulation time 4008532937 ps
CPU time 45.23 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 219780 kb
Host smart-9c570fd9-640d-4234-a8be-e6def7205836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101601707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2101601707
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3933115366
Short name T35
Test name
Test status
Simulation time 993177938 ps
CPU time 9.93 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:38 PM PDT 24
Peak memory 218776 kb
Host smart-0695f3b3-d57b-49ba-bbc3-92411f2ef466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933115366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3933115366
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3814506726
Short name T334
Test name
Test status
Simulation time 66389126139 ps
CPU time 306.52 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:53:32 PM PDT 24
Peak memory 234636 kb
Host smart-7e34df02-fb78-4bf6-8c56-9a7589a3740b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814506726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3814506726
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2311955259
Short name T253
Test name
Test status
Simulation time 1987970107 ps
CPU time 22.76 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:50 PM PDT 24
Peak memory 219752 kb
Host smart-372b9e6a-c30a-4126-9697-5378839fb213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311955259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2311955259
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3107993643
Short name T119
Test name
Test status
Simulation time 272572454 ps
CPU time 12.09 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219780 kb
Host smart-aeac2101-d3f3-4dc9-9215-82edccea94c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107993643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3107993643
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.848595883
Short name T267
Test name
Test status
Simulation time 344928005 ps
CPU time 19.98 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 219304 kb
Host smart-696c12ad-5927-46ad-b413-e0e95417da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848595883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.848595883
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2040994922
Short name T74
Test name
Test status
Simulation time 365051975 ps
CPU time 24.76 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219412 kb
Host smart-100c10e3-2daa-47cc-9bb1-b77710bf6cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040994922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2040994922
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.228220217
Short name T248
Test name
Test status
Simulation time 171510234 ps
CPU time 8.5 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:31 PM PDT 24
Peak memory 218840 kb
Host smart-1fbd6fc5-20ba-4023-a790-5277d259d8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228220217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.228220217
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.53955667
Short name T249
Test name
Test status
Simulation time 44021538814 ps
CPU time 135.96 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 234328 kb
Host smart-4cd7caf9-808f-45ea-bf39-4c9bb0a5f4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53955667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_co
rrupt_sig_fatal_chk.53955667
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2732451530
Short name T169
Test name
Test status
Simulation time 527403253 ps
CPU time 22.27 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219808 kb
Host smart-1b2d3b58-3e65-4e39-8e8f-c3ff50d9d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732451530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2732451530
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1079109608
Short name T279
Test name
Test status
Simulation time 542342685 ps
CPU time 11.91 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 219708 kb
Host smart-fed3c2ee-daef-48cd-be88-337196b2fa42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079109608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1079109608
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1730588026
Short name T226
Test name
Test status
Simulation time 2109797984 ps
CPU time 22.39 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 219316 kb
Host smart-c2d62cd0-4228-44f0-a09d-4bc7c6a6702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730588026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1730588026
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2204899111
Short name T24
Test name
Test status
Simulation time 562862730 ps
CPU time 27.56 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219436 kb
Host smart-c4b8e3d9-c675-485d-af6c-bdefdcaeee07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204899111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2204899111
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1397964928
Short name T335
Test name
Test status
Simulation time 172656858 ps
CPU time 8.34 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:31 PM PDT 24
Peak memory 218292 kb
Host smart-04898866-1ed2-4a96-a2de-c1e37f995c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397964928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1397964928
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1331857577
Short name T250
Test name
Test status
Simulation time 2333295215 ps
CPU time 136.98 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:50:50 PM PDT 24
Peak memory 237236 kb
Host smart-58888b9f-8da6-4c9d-be4f-19150dfacc34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331857577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1331857577
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1792242989
Short name T314
Test name
Test status
Simulation time 346235801 ps
CPU time 19.37 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219804 kb
Host smart-c93730da-70d6-4730-ace9-01438bc49fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792242989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1792242989
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1102166090
Short name T369
Test name
Test status
Simulation time 521758106 ps
CPU time 12.2 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219752 kb
Host smart-1d517e62-162e-46ee-b6f2-d6cc0867ee7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102166090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1102166090
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.974856068
Short name T319
Test name
Test status
Simulation time 1436219193 ps
CPU time 19.74 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219220 kb
Host smart-fbee2b09-3c0a-4da2-8a20-76ff0bb823cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974856068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.974856068
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2230090753
Short name T23
Test name
Test status
Simulation time 2140064061 ps
CPU time 42.06 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 219180 kb
Host smart-4549c19a-d746-4ff4-8b20-4ebe8101fd35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230090753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2230090753
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3970609506
Short name T356
Test name
Test status
Simulation time 2073207050 ps
CPU time 8.55 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:41 PM PDT 24
Peak memory 218800 kb
Host smart-376087b4-a7f5-4090-afcb-94fb363ac01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970609506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3970609506
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1611373923
Short name T42
Test name
Test status
Simulation time 3997798551 ps
CPU time 194.97 seconds
Started Jul 25 04:48:43 PM PDT 24
Finished Jul 25 04:51:58 PM PDT 24
Peak memory 234728 kb
Host smart-ce82287e-3ac5-402e-84a6-97712b9c9225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611373923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1611373923
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3940269245
Short name T185
Test name
Test status
Simulation time 1501705924 ps
CPU time 19.05 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 219816 kb
Host smart-a9804ea7-d761-45c0-a4b4-e08bc173f634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940269245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3940269245
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2569566924
Short name T228
Test name
Test status
Simulation time 1994853694 ps
CPU time 17.13 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:41 PM PDT 24
Peak memory 219404 kb
Host smart-62fcded3-bce8-4690-8af5-bb10b705e6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569566924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2569566924
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1574775141
Short name T354
Test name
Test status
Simulation time 21986241971 ps
CPU time 35.5 seconds
Started Jul 25 04:48:31 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 219248 kb
Host smart-04eb3940-ffb0-4b2f-8f38-93e92daa6848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574775141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1574775141
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1498985538
Short name T33
Test name
Test status
Simulation time 18570448843 ps
CPU time 57.43 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 219832 kb
Host smart-b7ddfba1-04b5-46a6-9751-7f2a4025ba08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498985538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1498985538
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2037656506
Short name T138
Test name
Test status
Simulation time 539361692 ps
CPU time 10.31 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:47 PM PDT 24
Peak memory 218884 kb
Host smart-822241fd-05ea-4bd7-a2df-0f22bbce03b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037656506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2037656506
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2376402401
Short name T220
Test name
Test status
Simulation time 2880608909 ps
CPU time 186.4 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:51:45 PM PDT 24
Peak memory 232664 kb
Host smart-d683a685-ccae-4a05-8933-d0c8e3257940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376402401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2376402401
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3028148610
Short name T357
Test name
Test status
Simulation time 2053592566 ps
CPU time 32.6 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 219796 kb
Host smart-6675924e-3684-4ed5-b97d-8d5c154486b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028148610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3028148610
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.203995668
Short name T206
Test name
Test status
Simulation time 2308249365 ps
CPU time 11.9 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 219768 kb
Host smart-78085746-116d-4827-9b40-64a8a40c41a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203995668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.203995668
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2345673032
Short name T181
Test name
Test status
Simulation time 1426386948 ps
CPU time 19.95 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219280 kb
Host smart-6e5140d8-154d-4ea4-9246-370e0829cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345673032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2345673032
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.701036792
Short name T242
Test name
Test status
Simulation time 2162376655 ps
CPU time 61.03 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 220376 kb
Host smart-1a468094-2e79-4cda-b7fe-751e2bce0d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701036792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.701036792
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3396942248
Short name T266
Test name
Test status
Simulation time 93248539696 ps
CPU time 1431.85 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 05:12:29 PM PDT 24
Peak memory 244444 kb
Host smart-41ce0f85-c9a4-4ddc-b039-1dca0eea5052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396942248 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3396942248
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.811584602
Short name T199
Test name
Test status
Simulation time 495398298 ps
CPU time 9.79 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 218872 kb
Host smart-f7b8d23d-517c-4141-875b-7af7d992f943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811584602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.811584602
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3576038717
Short name T256
Test name
Test status
Simulation time 13652622298 ps
CPU time 209.77 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:52:03 PM PDT 24
Peak memory 228368 kb
Host smart-4bc9feea-d71c-4f28-966d-494983d2c4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576038717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3576038717
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1397413724
Short name T286
Test name
Test status
Simulation time 505403896 ps
CPU time 22.01 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219788 kb
Host smart-b0843554-782c-43e2-b7e0-c39f2f162006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397413724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1397413724
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2568550598
Short name T120
Test name
Test status
Simulation time 1223029375 ps
CPU time 11.82 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219752 kb
Host smart-c18b04ee-4de2-47d6-8c4c-9b5c38de4817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568550598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2568550598
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1067173452
Short name T213
Test name
Test status
Simulation time 512216076 ps
CPU time 23.13 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219292 kb
Host smart-392ee698-fd75-4a20-a53b-c091e8ca7d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067173452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1067173452
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2991640117
Short name T121
Test name
Test status
Simulation time 1647251646 ps
CPU time 36.17 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 219732 kb
Host smart-5b873f98-4295-4ca6-b191-89f1a8916fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991640117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2991640117
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.781176928
Short name T34
Test name
Test status
Simulation time 528628749 ps
CPU time 10.03 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 218804 kb
Host smart-a63118b4-a20f-4e38-be9e-c061a037527a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781176928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.781176928
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2295901718
Short name T348
Test name
Test status
Simulation time 6920123510 ps
CPU time 253.41 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:52:42 PM PDT 24
Peak memory 239452 kb
Host smart-7a5662c2-4bf2-415c-a366-64035fead5c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295901718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2295901718
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3613437983
Short name T48
Test name
Test status
Simulation time 3660323274 ps
CPU time 18.46 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219864 kb
Host smart-5f6e1cd1-5da5-47b3-8844-093b80b0f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613437983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3613437983
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3611596223
Short name T333
Test name
Test status
Simulation time 190578892 ps
CPU time 10.69 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219832 kb
Host smart-d2aabdab-a527-49bc-874d-56ecb333b909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611596223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3611596223
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2972419973
Short name T92
Test name
Test status
Simulation time 6264481229 ps
CPU time 24.52 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 219488 kb
Host smart-62a82498-87ec-4843-853e-946e45fb6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972419973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2972419973
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1715591566
Short name T218
Test name
Test status
Simulation time 4235202150 ps
CPU time 47.22 seconds
Started Jul 25 04:48:31 PM PDT 24
Finished Jul 25 04:49:19 PM PDT 24
Peak memory 219412 kb
Host smart-a9843335-652b-49f8-bb66-06e245a51901
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715591566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1715591566
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3570377115
Short name T350
Test name
Test status
Simulation time 249927013 ps
CPU time 10.18 seconds
Started Jul 25 04:48:14 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 218772 kb
Host smart-e4130837-3d16-4a5c-b0da-d1221e66dffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570377115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3570377115
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3531805034
Short name T254
Test name
Test status
Simulation time 23431315085 ps
CPU time 342.45 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 244980 kb
Host smart-ca6837b5-ed98-4bd2-96f8-84cb7a5049e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531805034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3531805034
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.242555934
Short name T359
Test name
Test status
Simulation time 347241332 ps
CPU time 19.29 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:35 PM PDT 24
Peak memory 219748 kb
Host smart-99a8fbf3-50b2-43bd-93d2-e7898abff4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242555934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.242555934
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3045299852
Short name T287
Test name
Test status
Simulation time 1842105645 ps
CPU time 12.17 seconds
Started Jul 25 04:48:13 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 219752 kb
Host smart-45495916-6402-41a3-8d3e-91ccf8125799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045299852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3045299852
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3768961206
Short name T252
Test name
Test status
Simulation time 1059215202 ps
CPU time 23.14 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:27 PM PDT 24
Peak memory 218728 kb
Host smart-06afc786-0fba-4079-8e9a-8d91e24e5ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768961206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3768961206
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1652759105
Short name T259
Test name
Test status
Simulation time 536582931 ps
CPU time 16.78 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 218484 kb
Host smart-34759f2f-a9e9-4180-80c0-2069587930cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652759105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1652759105
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4163006977
Short name T372
Test name
Test status
Simulation time 135979518551 ps
CPU time 1368.5 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 05:10:58 PM PDT 24
Peak memory 239808 kb
Host smart-a14cfc51-5114-4816-a710-ee65eddec159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163006977 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4163006977
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1350571916
Short name T342
Test name
Test status
Simulation time 1019613507 ps
CPU time 15.45 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:41 PM PDT 24
Peak memory 218900 kb
Host smart-6f89cc2a-ee0a-41b3-af76-48f24a3745ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350571916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1350571916
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1068320689
Short name T324
Test name
Test status
Simulation time 2360641489 ps
CPU time 161.99 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:51:05 PM PDT 24
Peak memory 237928 kb
Host smart-07de9b7f-39ad-4b01-8313-7f71492b4bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068320689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1068320689
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1461566499
Short name T330
Test name
Test status
Simulation time 2149568303 ps
CPU time 22.32 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:49:09 PM PDT 24
Peak memory 219740 kb
Host smart-e9734cd1-a6a5-41ee-b04d-b83de7a12f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461566499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1461566499
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2252624994
Short name T150
Test name
Test status
Simulation time 925376380 ps
CPU time 12.06 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 219788 kb
Host smart-15bf8ce0-c034-41d7-8927-94dbdd4a66f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252624994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2252624994
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.466611350
Short name T41
Test name
Test status
Simulation time 483843203 ps
CPU time 20.06 seconds
Started Jul 25 04:48:39 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 218888 kb
Host smart-7e3aeacc-a3c2-45ac-89ba-6d23b64c573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466611350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.466611350
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2763603322
Short name T313
Test name
Test status
Simulation time 262756164 ps
CPU time 10.04 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 218836 kb
Host smart-2da6c7dd-5cb8-43f9-8f66-8e031251bda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763603322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2763603322
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1940435956
Short name T255
Test name
Test status
Simulation time 2098115137 ps
CPU time 215.44 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:52:08 PM PDT 24
Peak memory 239408 kb
Host smart-c4a06469-e7ca-451f-862a-3cdedad00101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940435956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1940435956
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3007451886
Short name T241
Test name
Test status
Simulation time 1900891459 ps
CPU time 22.1 seconds
Started Jul 25 04:48:59 PM PDT 24
Finished Jul 25 04:49:21 PM PDT 24
Peak memory 219836 kb
Host smart-d26e3cd3-e522-4e29-9168-8a24dc48830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007451886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3007451886
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2742456424
Short name T13
Test name
Test status
Simulation time 183393619 ps
CPU time 10.38 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 219828 kb
Host smart-11097334-765c-4511-8a85-4d8cddc6f557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742456424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2742456424
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3243372496
Short name T130
Test name
Test status
Simulation time 11646667561 ps
CPU time 32.63 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 219380 kb
Host smart-b6b86520-534f-4974-a489-819360e0b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243372496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3243372496
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2924458005
Short name T368
Test name
Test status
Simulation time 401626678 ps
CPU time 36.06 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 219828 kb
Host smart-041dca8c-255c-448c-bc02-120731cb1015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924458005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2924458005
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.512885415
Short name T345
Test name
Test status
Simulation time 10086595134 ps
CPU time 421.89 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:55:27 PM PDT 24
Peak memory 229556 kb
Host smart-9a8b5300-4525-489d-8d64-0296369fe721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512885415 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.512885415
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1892332634
Short name T166
Test name
Test status
Simulation time 950483921 ps
CPU time 10.27 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:47 PM PDT 24
Peak memory 218844 kb
Host smart-cbd548d1-7b37-4ead-8565-5129d479e614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892332634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1892332634
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2382639847
Short name T280
Test name
Test status
Simulation time 3950422200 ps
CPU time 295.56 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:53:28 PM PDT 24
Peak memory 238368 kb
Host smart-ca876cb2-7f82-4705-b700-77f7ee5a6383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382639847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2382639847
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2515151628
Short name T183
Test name
Test status
Simulation time 12296297978 ps
CPU time 32.23 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:58 PM PDT 24
Peak memory 219728 kb
Host smart-7382d389-5a4c-4689-a941-e96bf7019ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515151628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2515151628
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.26433409
Short name T93
Test name
Test status
Simulation time 706102802 ps
CPU time 10.68 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219816 kb
Host smart-cf5c95d6-80ad-4b72-b031-6a52c1543daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26433409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.26433409
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.584991967
Short name T134
Test name
Test status
Simulation time 347209920 ps
CPU time 19.56 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 219292 kb
Host smart-7fdf78c1-9037-4532-8e1e-26bcc9731688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584991967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.584991967
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.639644706
Short name T346
Test name
Test status
Simulation time 797636782 ps
CPU time 41.3 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:49:16 PM PDT 24
Peak memory 219728 kb
Host smart-61bca372-8eb6-4a2d-bab9-aa0c998f6df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639644706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.639644706
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3445885797
Short name T329
Test name
Test status
Simulation time 167358627 ps
CPU time 8.35 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 218772 kb
Host smart-a12712e3-9a17-4768-9132-a47a25599ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445885797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3445885797
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.869398887
Short name T223
Test name
Test status
Simulation time 8163590287 ps
CPU time 206.2 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:52:02 PM PDT 24
Peak memory 218564 kb
Host smart-50b08846-2482-483d-aed7-c988fde3d9de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869398887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.869398887
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2885137697
Short name T147
Test name
Test status
Simulation time 1976516193 ps
CPU time 22.85 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219820 kb
Host smart-335fc96f-97e8-40c7-9977-a3c30db97d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885137697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2885137697
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4228036279
Short name T275
Test name
Test status
Simulation time 514273438 ps
CPU time 12.07 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 219760 kb
Host smart-d8e95b76-8711-4a40-9114-6dd059022f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228036279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4228036279
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3504482460
Short name T128
Test name
Test status
Simulation time 1494451493 ps
CPU time 20.54 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 219264 kb
Host smart-be198993-db9c-4c97-8232-d644b13fb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504482460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3504482460
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.876302730
Short name T247
Test name
Test status
Simulation time 4506882964 ps
CPU time 56.31 seconds
Started Jul 25 04:48:30 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 220456 kb
Host smart-0bfc3e45-bcf2-47fe-8c89-4d74c10294d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876302730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.876302730
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2027816929
Short name T53
Test name
Test status
Simulation time 71386208985 ps
CPU time 667.88 seconds
Started Jul 25 04:48:31 PM PDT 24
Finished Jul 25 04:59:39 PM PDT 24
Peak memory 234572 kb
Host smart-009d0e63-4f27-48f3-8cfe-2d2139fda50a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027816929 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2027816929
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1018411480
Short name T315
Test name
Test status
Simulation time 1029471735 ps
CPU time 9.71 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 218880 kb
Host smart-62e87a0e-6cad-4545-b172-2649649d0e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018411480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1018411480
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2172444297
Short name T198
Test name
Test status
Simulation time 5197347479 ps
CPU time 276.93 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:53:04 PM PDT 24
Peak memory 234232 kb
Host smart-86fa43b0-0158-490c-8750-8ef0f4051a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172444297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2172444297
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4049496728
Short name T349
Test name
Test status
Simulation time 333454791 ps
CPU time 18.94 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219776 kb
Host smart-9334166c-0c9a-4432-a2ab-a6bf436f3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049496728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4049496728
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3806168704
Short name T281
Test name
Test status
Simulation time 187861001 ps
CPU time 10.58 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 219712 kb
Host smart-26b78cca-9cd7-4487-a187-0063290ec5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806168704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3806168704
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3381004842
Short name T309
Test name
Test status
Simulation time 513498658 ps
CPU time 22.98 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 219276 kb
Host smart-4c51df3f-2d0f-4e0b-be8f-5b7954188369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381004842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3381004842
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3711510843
Short name T322
Test name
Test status
Simulation time 3321343984 ps
CPU time 29.68 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 219796 kb
Host smart-cba69597-8c95-4a99-9db3-cd41150554b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711510843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3711510843
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1760214401
Short name T273
Test name
Test status
Simulation time 109271628871 ps
CPU time 3577.96 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 05:48:02 PM PDT 24
Peak memory 255828 kb
Host smart-a0a2bd37-54ec-4638-8eeb-fe23efd3073b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760214401 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1760214401
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1425984830
Short name T216
Test name
Test status
Simulation time 174673943 ps
CPU time 8.17 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 218800 kb
Host smart-da05b7b6-8b2d-431d-9834-0782ae6b52f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425984830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1425984830
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3215292681
Short name T272
Test name
Test status
Simulation time 10498685289 ps
CPU time 172.25 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:51:28 PM PDT 24
Peak memory 240912 kb
Host smart-7bbcf269-7392-4027-a011-07fa44ceb90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215292681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3215292681
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1311189466
Short name T171
Test name
Test status
Simulation time 1980706858 ps
CPU time 22.55 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 219784 kb
Host smart-958b4f73-62e7-4fa5-ab8e-34a1b6be78a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311189466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1311189466
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2045317398
Short name T328
Test name
Test status
Simulation time 178290973 ps
CPU time 10.46 seconds
Started Jul 25 04:48:22 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 219748 kb
Host smart-bfb506cd-cf52-4e9d-b3d7-3c6360ead373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045317398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2045317398
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4225606508
Short name T222
Test name
Test status
Simulation time 1341257873 ps
CPU time 23.42 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 219256 kb
Host smart-bc1016e2-0af3-4259-a0f6-6ba2da942651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225606508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4225606508
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1666181585
Short name T194
Test name
Test status
Simulation time 3465403241 ps
CPU time 28.17 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219528 kb
Host smart-60033671-11dd-4ebe-ba87-f8d1baa78441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666181585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1666181585
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2518602984
Short name T288
Test name
Test status
Simulation time 1034919024 ps
CPU time 10.17 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 218792 kb
Host smart-2d2e955c-3320-44bb-ae01-90b209d0cd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518602984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2518602984
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3281705155
Short name T298
Test name
Test status
Simulation time 7270249154 ps
CPU time 407.48 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:55:34 PM PDT 24
Peak memory 240468 kb
Host smart-cb8b147f-6829-4166-a370-032b57c378bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281705155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3281705155
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1261346475
Short name T200
Test name
Test status
Simulation time 1382577186 ps
CPU time 19.21 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 219808 kb
Host smart-eb94bfea-1031-48a1-91ca-18139efc1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261346475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1261346475
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2733883868
Short name T244
Test name
Test status
Simulation time 2356061927 ps
CPU time 12.3 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:40 PM PDT 24
Peak memory 219872 kb
Host smart-46d994f6-c044-45d7-bc31-1408d9664afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733883868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2733883868
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4270348916
Short name T139
Test name
Test status
Simulation time 610262013 ps
CPU time 23.62 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 219348 kb
Host smart-c2294405-013a-4e27-b0f2-eb34e44aa201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270348916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4270348916
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1924003647
Short name T127
Test name
Test status
Simulation time 252322504 ps
CPU time 10.12 seconds
Started Jul 25 04:48:51 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 218876 kb
Host smart-961c202c-4a6b-4e40-a924-88bd383b8787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924003647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1924003647
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.166834934
Short name T219
Test name
Test status
Simulation time 16336773755 ps
CPU time 217.87 seconds
Started Jul 25 04:48:54 PM PDT 24
Finished Jul 25 04:52:32 PM PDT 24
Peak memory 219724 kb
Host smart-6e886b2c-7777-43ba-8732-f9841958639b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166834934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.166834934
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2189330952
Short name T278
Test name
Test status
Simulation time 508373321 ps
CPU time 22.69 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:50 PM PDT 24
Peak memory 219772 kb
Host smart-10f61bc8-8686-4ddb-82c2-3b93c0048155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189330952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2189330952
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1485577699
Short name T125
Test name
Test status
Simulation time 517278902 ps
CPU time 11.91 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219792 kb
Host smart-f48dfa2c-7b97-458a-97ab-21ebd626dacb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485577699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1485577699
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.342907405
Short name T6
Test name
Test status
Simulation time 4559909147 ps
CPU time 23.42 seconds
Started Jul 25 04:48:58 PM PDT 24
Finished Jul 25 04:49:21 PM PDT 24
Peak memory 219356 kb
Host smart-6036fe02-6296-4024-973e-d5ffda3689a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342907405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.342907405
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1666932282
Short name T263
Test name
Test status
Simulation time 257637975 ps
CPU time 11.45 seconds
Started Jul 25 04:48:39 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219628 kb
Host smart-ca998162-3906-4fa8-8f03-4ea64069522a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666932282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1666932282
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.996227418
Short name T47
Test name
Test status
Simulation time 260506927 ps
CPU time 9.92 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 218916 kb
Host smart-b383c476-468c-4579-b3be-4d4272c571bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996227418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.996227418
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4240496412
Short name T44
Test name
Test status
Simulation time 20895068884 ps
CPU time 403.68 seconds
Started Jul 25 04:48:46 PM PDT 24
Finished Jul 25 04:55:30 PM PDT 24
Peak memory 226116 kb
Host smart-e03d4d66-6049-4585-9694-956f31069153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240496412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4240496412
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.501164870
Short name T211
Test name
Test status
Simulation time 333210969 ps
CPU time 12.2 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:49 PM PDT 24
Peak memory 219748 kb
Host smart-653a45d2-88d4-4fe0-a503-ff7719b92db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501164870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.501164870
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.130341265
Short name T187
Test name
Test status
Simulation time 1811234198 ps
CPU time 20.05 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 218644 kb
Host smart-b74f3054-1fac-4f24-97c2-6ab34bd83580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130341265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.130341265
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.519670753
Short name T323
Test name
Test status
Simulation time 754465832 ps
CPU time 27.42 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219336 kb
Host smart-a2030ada-cc10-4aaf-b028-b006c5039541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519670753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.519670753
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2885349432
Short name T19
Test name
Test status
Simulation time 108203760584 ps
CPU time 8560.33 seconds
Started Jul 25 04:48:41 PM PDT 24
Finished Jul 25 07:11:22 PM PDT 24
Peak memory 236888 kb
Host smart-31aeb532-388e-48b8-889f-ceb7cf30ab33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885349432 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2885349432
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3581542437
Short name T317
Test name
Test status
Simulation time 1125673820 ps
CPU time 9.92 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 218756 kb
Host smart-27547feb-4eda-4d7b-b438-733b1a1f90e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581542437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3581542437
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1619475325
Short name T240
Test name
Test status
Simulation time 6062242756 ps
CPU time 318.69 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:54:00 PM PDT 24
Peak memory 234988 kb
Host smart-daec6023-8e74-4b3e-98e7-ef19be36e6a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619475325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1619475325
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1080956617
Short name T212
Test name
Test status
Simulation time 524419638 ps
CPU time 22.64 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219824 kb
Host smart-094f731b-2075-443e-bb37-fdf78d031973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080956617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1080956617
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3835665661
Short name T165
Test name
Test status
Simulation time 1071018521 ps
CPU time 12.11 seconds
Started Jul 25 04:48:55 PM PDT 24
Finished Jul 25 04:49:07 PM PDT 24
Peak memory 219836 kb
Host smart-563b3c09-aeed-48ae-ad4c-4bbd43a6490a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835665661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3835665661
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2803697852
Short name T326
Test name
Test status
Simulation time 525771034 ps
CPU time 22.84 seconds
Started Jul 25 04:48:33 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219280 kb
Host smart-b0a2e40d-c5b0-4760-894b-ccb0a260f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803697852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2803697852
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4093796258
Short name T234
Test name
Test status
Simulation time 720490660 ps
CPU time 32.06 seconds
Started Jul 25 04:48:48 PM PDT 24
Finished Jul 25 04:49:21 PM PDT 24
Peak memory 219788 kb
Host smart-6f4b53cd-b5db-47bd-9c9d-cd694bb59c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093796258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4093796258
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1679758511
Short name T260
Test name
Test status
Simulation time 495930875 ps
CPU time 9.9 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:35 PM PDT 24
Peak memory 218800 kb
Host smart-6ea2a53b-0b20-48c6-ab31-ea8bfaa664dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679758511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1679758511
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1066334682
Short name T343
Test name
Test status
Simulation time 10367467583 ps
CPU time 188.81 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:51:16 PM PDT 24
Peak memory 235044 kb
Host smart-c4113360-8642-408c-b070-850b958ec292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066334682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1066334682
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4101675154
Short name T152
Test name
Test status
Simulation time 2205742454 ps
CPU time 18.58 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219908 kb
Host smart-9b2e0d5e-a8ce-494a-9715-efee21643cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101675154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4101675154
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2630069258
Short name T351
Test name
Test status
Simulation time 3225489775 ps
CPU time 12.33 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:48:21 PM PDT 24
Peak memory 219824 kb
Host smart-ce48170b-df68-4699-8e72-f07568adf25f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630069258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2630069258
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4123788002
Short name T29
Test name
Test status
Simulation time 418610302 ps
CPU time 115.75 seconds
Started Jul 25 04:48:11 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 233644 kb
Host smart-6d1c17ec-bcb5-4b2b-8e95-b885e3cbefc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123788002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4123788002
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3079288664
Short name T262
Test name
Test status
Simulation time 4048971313 ps
CPU time 34.31 seconds
Started Jul 25 04:48:18 PM PDT 24
Finished Jul 25 04:48:52 PM PDT 24
Peak memory 219340 kb
Host smart-f11abb57-3e8b-4051-a39e-199e85bbf0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079288664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3079288664
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.322634191
Short name T118
Test name
Test status
Simulation time 387700729 ps
CPU time 24.89 seconds
Started Jul 25 04:48:14 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 219164 kb
Host smart-7e502a90-13b8-4f5f-b7a2-50c12b805e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322634191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.322634191
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2754369303
Short name T104
Test name
Test status
Simulation time 32940215467 ps
CPU time 1225.45 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 05:08:41 PM PDT 24
Peak memory 236264 kb
Host smart-b4580932-4616-4d30-bba0-a60865d01657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754369303 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2754369303
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2036114922
Short name T176
Test name
Test status
Simulation time 661773672 ps
CPU time 8.37 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 218804 kb
Host smart-86668e8e-0f16-4b75-9153-f6a1e2f68bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036114922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2036114922
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2034443484
Short name T344
Test name
Test status
Simulation time 5491141315 ps
CPU time 22.7 seconds
Started Jul 25 04:48:56 PM PDT 24
Finished Jul 25 04:49:18 PM PDT 24
Peak memory 219832 kb
Host smart-f2dc33f2-ecf9-4797-9913-a5559a1abe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034443484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2034443484
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.488485531
Short name T295
Test name
Test status
Simulation time 1023309079 ps
CPU time 11.92 seconds
Started Jul 25 04:48:31 PM PDT 24
Finished Jul 25 04:48:43 PM PDT 24
Peak memory 219772 kb
Host smart-f63845d5-6935-48c8-b519-dc95792695d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488485531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.488485531
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3850744015
Short name T364
Test name
Test status
Simulation time 358721368 ps
CPU time 20.85 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:46 PM PDT 24
Peak memory 219240 kb
Host smart-0f1b1e1e-3f73-44ed-9f7e-4fef53f07f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850744015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3850744015
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2557177506
Short name T142
Test name
Test status
Simulation time 9330472582 ps
CPU time 96.17 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 221580 kb
Host smart-46d7d4e0-d5cb-48d7-8736-475845cf1947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557177506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2557177506
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.658816010
Short name T210
Test name
Test status
Simulation time 637676555 ps
CPU time 10.19 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 04:48:42 PM PDT 24
Peak memory 218880 kb
Host smart-d9d1f7b2-9301-44a2-903c-078971591ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658816010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.658816010
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2589975172
Short name T192
Test name
Test status
Simulation time 24886316095 ps
CPU time 320.12 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:53:49 PM PDT 24
Peak memory 242776 kb
Host smart-10fe157f-050c-467b-8b72-33daa0c5a63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589975172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2589975172
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1189430125
Short name T49
Test name
Test status
Simulation time 332548431 ps
CPU time 19.49 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 219776 kb
Host smart-40dc910b-890b-4bed-9142-845b3c630288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189430125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1189430125
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1256927445
Short name T339
Test name
Test status
Simulation time 342676941 ps
CPU time 12.28 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:36 PM PDT 24
Peak memory 219796 kb
Host smart-68caceb0-aa08-4d7a-8667-476bac5a8642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256927445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1256927445
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.753278171
Short name T158
Test name
Test status
Simulation time 4996803993 ps
CPU time 23.24 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 219300 kb
Host smart-b7181bd8-f25b-443b-9058-8d685c16deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753278171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.753278171
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1614452898
Short name T251
Test name
Test status
Simulation time 569791541 ps
CPU time 26.61 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219676 kb
Host smart-407b00d8-97c5-4be2-87c7-c0c6d8466a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614452898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1614452898
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1549483928
Short name T4
Test name
Test status
Simulation time 248826261 ps
CPU time 9.84 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 218872 kb
Host smart-b804f930-9607-434d-9df1-d6a4c72d604a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549483928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1549483928
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3531587512
Short name T45
Test name
Test status
Simulation time 3526753338 ps
CPU time 216.19 seconds
Started Jul 25 04:48:53 PM PDT 24
Finished Jul 25 04:52:29 PM PDT 24
Peak memory 226852 kb
Host smart-d1fe910d-e501-43c1-a23d-4e6cb578fcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531587512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3531587512
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4146261655
Short name T36
Test name
Test status
Simulation time 338999865 ps
CPU time 20.06 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219804 kb
Host smart-908257ff-1d56-43ea-a8b4-1c9901eb8098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146261655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4146261655
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2627332946
Short name T153
Test name
Test status
Simulation time 1455157981 ps
CPU time 10.78 seconds
Started Jul 25 04:48:43 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 219800 kb
Host smart-36ad6a25-b3ad-405c-8cdf-e34221e7d916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627332946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2627332946
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1702128664
Short name T338
Test name
Test status
Simulation time 360923919 ps
CPU time 20.35 seconds
Started Jul 25 04:48:54 PM PDT 24
Finished Jul 25 04:49:14 PM PDT 24
Peak memory 219192 kb
Host smart-5963d1cb-d964-4835-b2de-5da7acffe071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702128664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1702128664
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2579644608
Short name T289
Test name
Test status
Simulation time 4234208047 ps
CPU time 57.24 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:37 PM PDT 24
Peak memory 220968 kb
Host smart-7a3f7690-8d91-4886-ba41-e2c0d1e6f0fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579644608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2579644608
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1871447732
Short name T305
Test name
Test status
Simulation time 4115476154 ps
CPU time 10.02 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219024 kb
Host smart-250f5475-6688-4eeb-ac5d-6ec513a7b589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871447732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1871447732
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1655794609
Short name T332
Test name
Test status
Simulation time 2152252821 ps
CPU time 172.77 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:51:27 PM PDT 24
Peak memory 239496 kb
Host smart-4fc9be34-221e-4885-8c93-a6ecd98d221e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655794609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1655794609
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.591488248
Short name T157
Test name
Test status
Simulation time 2061782463 ps
CPU time 22.3 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:50 PM PDT 24
Peak memory 219796 kb
Host smart-ac670f21-d5ed-4140-86e9-daec8e544658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591488248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.591488248
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1734383179
Short name T151
Test name
Test status
Simulation time 186801071 ps
CPU time 10.52 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:51 PM PDT 24
Peak memory 219876 kb
Host smart-a18cee94-c8bd-407f-961f-27d9194109aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734383179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1734383179
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1787869524
Short name T154
Test name
Test status
Simulation time 1882776005 ps
CPU time 23.46 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 219764 kb
Host smart-a391bbca-a189-41e7-80a6-3749ca7a476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787869524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1787869524
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.265833737
Short name T161
Test name
Test status
Simulation time 2950433642 ps
CPU time 45.27 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 220560 kb
Host smart-ec3918d6-94aa-4518-809b-2208da8b8e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265833737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.265833737
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.467376203
Short name T282
Test name
Test status
Simulation time 262424621 ps
CPU time 9.66 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:37 PM PDT 24
Peak memory 218688 kb
Host smart-9e6e48a1-70ef-44c4-a1ed-73b9bfcbcd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467376203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.467376203
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3653869910
Short name T347
Test name
Test status
Simulation time 3855664039 ps
CPU time 323.22 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:54:01 PM PDT 24
Peak memory 236884 kb
Host smart-e5aa54a7-d539-44b7-b6f5-709b5a4ed1c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653869910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3653869910
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2655914773
Short name T243
Test name
Test status
Simulation time 409843859 ps
CPU time 19.62 seconds
Started Jul 25 04:48:54 PM PDT 24
Finished Jul 25 04:49:14 PM PDT 24
Peak memory 219796 kb
Host smart-50cc385a-5520-432d-bbfe-d5426c4ff649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655914773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2655914773
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4192055792
Short name T201
Test name
Test status
Simulation time 2333974677 ps
CPU time 12.17 seconds
Started Jul 25 04:48:47 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 219856 kb
Host smart-591d5983-deb8-4619-9960-012981273134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192055792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4192055792
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.929290521
Short name T56
Test name
Test status
Simulation time 341312695 ps
CPU time 19.5 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 219280 kb
Host smart-034e40bd-706d-483e-b06c-77070b44464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929290521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.929290521
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.662733720
Short name T261
Test name
Test status
Simulation time 579214389 ps
CPU time 37.06 seconds
Started Jul 25 04:48:26 PM PDT 24
Finished Jul 25 04:49:03 PM PDT 24
Peak memory 219504 kb
Host smart-5cc27c25-c964-40b6-89bd-05d746a78050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662733720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.662733720
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2683108733
Short name T52
Test name
Test status
Simulation time 104897321286 ps
CPU time 1708.24 seconds
Started Jul 25 04:48:54 PM PDT 24
Finished Jul 25 05:17:22 PM PDT 24
Peak memory 251672 kb
Host smart-8dcce676-18f5-4f67-86c9-767385dd270e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683108733 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2683108733
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2863560216
Short name T353
Test name
Test status
Simulation time 688284615 ps
CPU time 8.36 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:48:45 PM PDT 24
Peak memory 218804 kb
Host smart-3b264044-2ce4-4dab-906b-f25c1696f565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863560216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2863560216
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.351349705
Short name T284
Test name
Test status
Simulation time 3447894204 ps
CPU time 238.97 seconds
Started Jul 25 04:48:29 PM PDT 24
Finished Jul 25 04:52:28 PM PDT 24
Peak memory 219616 kb
Host smart-e30f6e23-deb2-4d15-9f91-40633fba35a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351349705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.351349705
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.921729533
Short name T233
Test name
Test status
Simulation time 2149658247 ps
CPU time 22.64 seconds
Started Jul 25 04:48:43 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 219900 kb
Host smart-ae6c7b5d-d4ad-4071-a9a5-a97922839c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921729533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.921729533
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2081610304
Short name T331
Test name
Test status
Simulation time 266799602 ps
CPU time 12.08 seconds
Started Jul 25 04:48:55 PM PDT 24
Finished Jul 25 04:49:07 PM PDT 24
Peak memory 219836 kb
Host smart-f2e6462e-e96c-4638-adcf-15143665e511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081610304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2081610304
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2269777253
Short name T135
Test name
Test status
Simulation time 512585942 ps
CPU time 23.58 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 219112 kb
Host smart-7070405b-997f-44a1-843e-43cab3954e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269777253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2269777253
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.932867833
Short name T182
Test name
Test status
Simulation time 1176344154 ps
CPU time 29.5 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 219720 kb
Host smart-a975535d-7bed-4cfc-8bd5-a9ef43db2336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932867833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.932867833
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1612045948
Short name T136
Test name
Test status
Simulation time 2355306665 ps
CPU time 8.26 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:37 PM PDT 24
Peak memory 218904 kb
Host smart-ffc630e3-1fa9-41f2-afec-363f241844fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612045948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1612045948
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.19848307
Short name T179
Test name
Test status
Simulation time 6624504300 ps
CPU time 255.39 seconds
Started Jul 25 04:48:56 PM PDT 24
Finished Jul 25 04:53:12 PM PDT 24
Peak memory 225232 kb
Host smart-3d43a282-e2dd-40ef-9924-6846340871d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19848307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co
rrupt_sig_fatal_chk.19848307
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2202903807
Short name T301
Test name
Test status
Simulation time 1985222298 ps
CPU time 22.32 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:49:03 PM PDT 24
Peak memory 219772 kb
Host smart-eb949ca8-9c1c-446a-801f-3d454d320142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202903807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2202903807
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4252457999
Short name T292
Test name
Test status
Simulation time 1405088891 ps
CPU time 18.88 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:48:56 PM PDT 24
Peak memory 219212 kb
Host smart-9702339b-84b4-4524-a8f2-03b2f5494958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252457999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4252457999
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2557427567
Short name T156
Test name
Test status
Simulation time 4688416207 ps
CPU time 65.16 seconds
Started Jul 25 04:48:44 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 222488 kb
Host smart-0fad5b5a-b1a8-46df-98fc-211ba4f614c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557427567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2557427567
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.565992018
Short name T17
Test name
Test status
Simulation time 42076775063 ps
CPU time 1575.41 seconds
Started Jul 25 04:49:01 PM PDT 24
Finished Jul 25 05:15:16 PM PDT 24
Peak memory 236176 kb
Host smart-8fc22a21-d068-4fbb-b020-a7c59bfadb1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565992018 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.565992018
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3226868396
Short name T257
Test name
Test status
Simulation time 664519077 ps
CPU time 8.31 seconds
Started Jul 25 04:49:07 PM PDT 24
Finished Jul 25 04:49:15 PM PDT 24
Peak memory 218820 kb
Host smart-41bf5dec-0b71-4ab2-8c8a-90832022dd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226868396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3226868396
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3109716181
Short name T148
Test name
Test status
Simulation time 12197948255 ps
CPU time 172.97 seconds
Started Jul 25 04:48:34 PM PDT 24
Finished Jul 25 04:51:27 PM PDT 24
Peak memory 238416 kb
Host smart-df47e880-096c-406c-b434-b8a7a6f5607c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109716181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3109716181
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3146772735
Short name T274
Test name
Test status
Simulation time 4014285740 ps
CPU time 32.32 seconds
Started Jul 25 04:48:37 PM PDT 24
Finished Jul 25 04:49:10 PM PDT 24
Peak memory 219516 kb
Host smart-a82c3c6a-7e6e-4b16-bead-8ac5c139b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146772735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3146772735
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1733177675
Short name T204
Test name
Test status
Simulation time 261667462 ps
CPU time 12.45 seconds
Started Jul 25 04:48:39 PM PDT 24
Finished Jul 25 04:48:52 PM PDT 24
Peak memory 219796 kb
Host smart-1ccbd8b1-25ef-4034-8b10-ea97e0dd12dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733177675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1733177675
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2186623997
Short name T137
Test name
Test status
Simulation time 352050098 ps
CPU time 20.27 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:48 PM PDT 24
Peak memory 219184 kb
Host smart-77708fb2-8e76-49f3-9744-f604789ce5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186623997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2186623997
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1573416549
Short name T291
Test name
Test status
Simulation time 4226308358 ps
CPU time 44.42 seconds
Started Jul 25 04:48:36 PM PDT 24
Finished Jul 25 04:49:21 PM PDT 24
Peak memory 221384 kb
Host smart-7942954c-ffb0-484a-875d-8ceb4d90a757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573416549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1573416549
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1447455836
Short name T54
Test name
Test status
Simulation time 155683004510 ps
CPU time 1073.29 seconds
Started Jul 25 04:48:32 PM PDT 24
Finished Jul 25 05:06:26 PM PDT 24
Peak memory 237436 kb
Host smart-8f6687a6-7bd7-4652-b77d-7799a5a93bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447455836 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1447455836
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.638387592
Short name T64
Test name
Test status
Simulation time 346088520 ps
CPU time 8.32 seconds
Started Jul 25 04:48:58 PM PDT 24
Finished Jul 25 04:49:06 PM PDT 24
Peak memory 218908 kb
Host smart-8fde929f-261c-4e71-af36-99c203e7fb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638387592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.638387592
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1972400095
Short name T38
Test name
Test status
Simulation time 3113245141 ps
CPU time 170.25 seconds
Started Jul 25 04:49:06 PM PDT 24
Finished Jul 25 04:51:56 PM PDT 24
Peak memory 233960 kb
Host smart-05506d61-4568-4c7d-afe4-3961345480e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972400095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1972400095
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3572167455
Short name T283
Test name
Test status
Simulation time 342528337 ps
CPU time 19.34 seconds
Started Jul 25 04:48:40 PM PDT 24
Finished Jul 25 04:48:59 PM PDT 24
Peak memory 219824 kb
Host smart-9a4d5c27-f556-413c-85be-3f078c3b1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572167455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3572167455
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3344064329
Short name T225
Test name
Test status
Simulation time 4280522072 ps
CPU time 12.66 seconds
Started Jul 25 04:48:46 PM PDT 24
Finished Jul 25 04:48:58 PM PDT 24
Peak memory 219872 kb
Host smart-07d98b1f-600d-445c-887c-810efa891686
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344064329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3344064329
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2040444294
Short name T217
Test name
Test status
Simulation time 748478568 ps
CPU time 19.55 seconds
Started Jul 25 04:48:56 PM PDT 24
Finished Jul 25 04:49:16 PM PDT 24
Peak memory 219264 kb
Host smart-e634612d-01c2-4ba1-88b8-20d6c7e55738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040444294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2040444294
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1183799534
Short name T297
Test name
Test status
Simulation time 1873051612 ps
CPU time 22.72 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:49:01 PM PDT 24
Peak memory 219368 kb
Host smart-00f08a07-c54b-498b-8f69-9a1353411ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183799534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1183799534
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.700054057
Short name T20
Test name
Test status
Simulation time 15827307972 ps
CPU time 616.89 seconds
Started Jul 25 04:48:49 PM PDT 24
Finished Jul 25 04:59:06 PM PDT 24
Peak memory 231096 kb
Host smart-cb3dafd1-7142-42e7-aa23-79c6cae20913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700054057 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.700054057
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.493741965
Short name T186
Test name
Test status
Simulation time 260061646 ps
CPU time 10.41 seconds
Started Jul 25 04:49:00 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 218812 kb
Host smart-85335bac-8132-4825-9c86-42120cc4922e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493741965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.493741965
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1493077126
Short name T129
Test name
Test status
Simulation time 5732579583 ps
CPU time 284.82 seconds
Started Jul 25 04:48:56 PM PDT 24
Finished Jul 25 04:53:41 PM PDT 24
Peak memory 236832 kb
Host smart-73f3ffac-93e3-48ac-a5c6-3eb523ed5a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493077126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1493077126
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3213079451
Short name T258
Test name
Test status
Simulation time 1328727637 ps
CPU time 20.06 seconds
Started Jul 25 04:48:51 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 219784 kb
Host smart-722269aa-8610-494e-923a-23f53d152e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213079451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3213079451
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.350648364
Short name T245
Test name
Test status
Simulation time 309743165 ps
CPU time 12.03 seconds
Started Jul 25 04:48:48 PM PDT 24
Finished Jul 25 04:49:00 PM PDT 24
Peak memory 219776 kb
Host smart-f005c34c-2fec-4a0f-ae10-94742201ab4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350648364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.350648364
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4073123091
Short name T159
Test name
Test status
Simulation time 7905120535 ps
CPU time 32.52 seconds
Started Jul 25 04:48:38 PM PDT 24
Finished Jul 25 04:49:11 PM PDT 24
Peak memory 219680 kb
Host smart-0bdff588-1650-4222-b5d6-c3a8997b59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073123091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4073123091
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2275514457
Short name T18
Test name
Test status
Simulation time 535019938 ps
CPU time 27.23 seconds
Started Jul 25 04:48:35 PM PDT 24
Finished Jul 25 04:49:03 PM PDT 24
Peak memory 219340 kb
Host smart-149435dc-d427-49a5-9455-9005912ad47a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275514457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2275514457
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2850564611
Short name T55
Test name
Test status
Simulation time 33714219240 ps
CPU time 634.81 seconds
Started Jul 25 04:48:58 PM PDT 24
Finished Jul 25 04:59:33 PM PDT 24
Peak memory 236340 kb
Host smart-51f78284-433a-421d-9b38-3468d7ef82d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850564611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2850564611
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.157359637
Short name T214
Test name
Test status
Simulation time 1643173036 ps
CPU time 9.75 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:48:12 PM PDT 24
Peak memory 218888 kb
Host smart-25070e37-02a9-4ece-ad0e-8543b163263c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157359637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.157359637
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.175194915
Short name T43
Test name
Test status
Simulation time 26524832258 ps
CPU time 362.76 seconds
Started Jul 25 04:48:01 PM PDT 24
Finished Jul 25 04:54:04 PM PDT 24
Peak memory 239944 kb
Host smart-906d1730-ed29-404b-93c3-884f95cb9e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175194915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.175194915
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3680155059
Short name T190
Test name
Test status
Simulation time 1011430688 ps
CPU time 23.11 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219872 kb
Host smart-6811b6c5-1e65-4d6d-bb54-4e16a2b58144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680155059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3680155059
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.502908920
Short name T8
Test name
Test status
Simulation time 2074784982 ps
CPU time 16.69 seconds
Started Jul 25 04:48:00 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 219760 kb
Host smart-72c94b4e-ab63-4e38-8582-5df26297cdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502908920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.502908920
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1145997315
Short name T358
Test name
Test status
Simulation time 352930324 ps
CPU time 20.29 seconds
Started Jul 25 04:48:09 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 218708 kb
Host smart-46a5a66d-78e0-4eea-9e73-0c3533a0d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145997315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1145997315
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.660604749
Short name T230
Test name
Test status
Simulation time 2125381058 ps
CPU time 31.87 seconds
Started Jul 25 04:48:00 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 219464 kb
Host smart-012ab1f9-ea25-478a-ab0a-98424f5113f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660604749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.660604749
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2029715554
Short name T205
Test name
Test status
Simulation time 257243642 ps
CPU time 10.27 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:48:27 PM PDT 24
Peak memory 218676 kb
Host smart-d4d71a07-9d23-40d1-aaf5-66b2ed368aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029715554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2029715554
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1503187595
Short name T173
Test name
Test status
Simulation time 9520837724 ps
CPU time 267.15 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:52:34 PM PDT 24
Peak memory 234356 kb
Host smart-9f2b5be9-4e28-452e-9fd8-e9d9dcaee4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503187595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1503187595
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2312494785
Short name T270
Test name
Test status
Simulation time 5509834825 ps
CPU time 23.06 seconds
Started Jul 25 04:48:17 PM PDT 24
Finished Jul 25 04:48:40 PM PDT 24
Peak memory 219844 kb
Host smart-3b4aae50-e8b6-4a15-b038-8354a67d1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312494785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2312494785
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2135771876
Short name T337
Test name
Test status
Simulation time 182423035 ps
CPU time 10.38 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:18 PM PDT 24
Peak memory 219824 kb
Host smart-f987a910-465b-41b2-8550-b57421019937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135771876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2135771876
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1841824909
Short name T61
Test name
Test status
Simulation time 354450878 ps
CPU time 20.65 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 218848 kb
Host smart-57475570-bd6f-4300-bb67-8156b9fdf150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841824909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1841824909
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4201973274
Short name T12
Test name
Test status
Simulation time 2028622710 ps
CPU time 51.58 seconds
Started Jul 25 04:48:21 PM PDT 24
Finished Jul 25 04:49:13 PM PDT 24
Peak memory 219804 kb
Host smart-edceb571-8061-46e0-bcf5-027a466da53a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201973274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4201973274
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.505204005
Short name T304
Test name
Test status
Simulation time 94561246582 ps
CPU time 9595.81 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 07:28:00 PM PDT 24
Peak memory 237140 kb
Host smart-98e1fceb-41e2-401a-8bb5-9e48b7863ec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505204005 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.505204005
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1133334749
Short name T146
Test name
Test status
Simulation time 256556455 ps
CPU time 10.22 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 218876 kb
Host smart-df89e674-fde0-42e6-be96-349ce075c6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133334749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1133334749
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1049545526
Short name T46
Test name
Test status
Simulation time 3769119019 ps
CPU time 267.83 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:52:32 PM PDT 24
Peak memory 225568 kb
Host smart-770f304c-a0bb-4572-af9a-cea083b29e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049545526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1049545526
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2430582842
Short name T2
Test name
Test status
Simulation time 516849865 ps
CPU time 22.49 seconds
Started Jul 25 04:48:19 PM PDT 24
Finished Jul 25 04:48:42 PM PDT 24
Peak memory 219864 kb
Host smart-8c73c99d-578e-4a4e-b4f4-5ee0742bb8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430582842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2430582842
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2510911271
Short name T325
Test name
Test status
Simulation time 2173569777 ps
CPU time 12.47 seconds
Started Jul 25 04:48:04 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 219904 kb
Host smart-cde785ab-7311-43fb-a0ba-a59aec646adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510911271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2510911271
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.724199571
Short name T132
Test name
Test status
Simulation time 355349911 ps
CPU time 18.9 seconds
Started Jul 25 04:48:03 PM PDT 24
Finished Jul 25 04:48:22 PM PDT 24
Peak memory 219052 kb
Host smart-20560012-db3e-4306-bf62-bc397f9dcf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724199571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.724199571
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2011902770
Short name T311
Test name
Test status
Simulation time 2568819512 ps
CPU time 64.3 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:49:20 PM PDT 24
Peak memory 221892 kb
Host smart-0b9f496d-6f70-48df-93e2-f07f7e5e6f4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011902770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2011902770
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2882757288
Short name T203
Test name
Test status
Simulation time 168292717 ps
CPU time 8.36 seconds
Started Jul 25 04:48:23 PM PDT 24
Finished Jul 25 04:48:31 PM PDT 24
Peak memory 218844 kb
Host smart-0a13c3e3-7d5f-426a-a682-d5b4b9ada895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882757288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2882757288
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1958912258
Short name T25
Test name
Test status
Simulation time 24703369152 ps
CPU time 363.67 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:54:06 PM PDT 24
Peak memory 239012 kb
Host smart-d8fd7dce-a247-45e9-a3c1-24c321bbb8d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958912258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1958912258
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2767264679
Short name T316
Test name
Test status
Simulation time 1321728408 ps
CPU time 20.03 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:48:15 PM PDT 24
Peak memory 219848 kb
Host smart-a7abd207-2f2f-4d00-9cd4-60951e36d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767264679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2767264679
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1040564007
Short name T221
Test name
Test status
Simulation time 536814151 ps
CPU time 12.3 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:48:11 PM PDT 24
Peak memory 219736 kb
Host smart-0bd4757c-eb0d-4ae8-9049-2e47a00bd2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040564007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1040564007
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1933953862
Short name T293
Test name
Test status
Simulation time 8446975717 ps
CPU time 23.29 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:48:33 PM PDT 24
Peak memory 219408 kb
Host smart-af9fffd1-9f74-40de-9a8f-47b6ee9f4701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933953862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1933953862
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2591143743
Short name T39
Test name
Test status
Simulation time 281589755 ps
CPU time 19.79 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 219396 kb
Host smart-8b54f0d1-30a0-46e2-91d3-8bbe747e928f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591143743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2591143743
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.50265464
Short name T124
Test name
Test status
Simulation time 2233640676 ps
CPU time 9.84 seconds
Started Jul 25 04:48:15 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 218976 kb
Host smart-ff396ffa-8906-4bbf-9334-604cdb98d3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50265464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.50265464
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3167928779
Short name T362
Test name
Test status
Simulation time 5379484891 ps
CPU time 316.95 seconds
Started Jul 25 04:48:12 PM PDT 24
Finished Jul 25 04:53:29 PM PDT 24
Peak memory 234272 kb
Host smart-131f0688-f936-4808-94be-751e51b987f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167928779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3167928779
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3740893920
Short name T352
Test name
Test status
Simulation time 2064577504 ps
CPU time 18.29 seconds
Started Jul 25 04:48:16 PM PDT 24
Finished Jul 25 04:48:34 PM PDT 24
Peak memory 219724 kb
Host smart-085050e1-4ea3-4e42-a9a7-b331aad33c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740893920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3740893920
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2543922842
Short name T140
Test name
Test status
Simulation time 176747254 ps
CPU time 10.66 seconds
Started Jul 25 04:48:24 PM PDT 24
Finished Jul 25 04:48:35 PM PDT 24
Peak memory 219808 kb
Host smart-719cdeca-fbd4-4bba-abc5-11789b4c1f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543922842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2543922842
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3956271280
Short name T246
Test name
Test status
Simulation time 720070214 ps
CPU time 19.08 seconds
Started Jul 25 04:48:25 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 219148 kb
Host smart-187618f3-2410-4ea6-86e8-c8bdda81143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956271280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3956271280
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.570491733
Short name T26
Test name
Test status
Simulation time 2786040673 ps
CPU time 40.06 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:49:07 PM PDT 24
Peak memory 219692 kb
Host smart-d0368532-0cf8-47ba-a550-47d24ae6a4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570491733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.570491733
Directory /workspace/9.rom_ctrl_stress_all/latest
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