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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.68 100.00 98.62 97.30 98.37


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T302 /workspace/coverage/default/7.rom_ctrl_alert_test.1105439379 Jul 26 04:57:48 PM PDT 24 Jul 26 04:57:58 PM PDT 24 249527008 ps
T303 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2991942307 Jul 26 04:58:05 PM PDT 24 Jul 26 04:58:17 PM PDT 24 1836976295 ps
T304 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2633309689 Jul 26 04:57:50 PM PDT 24 Jul 26 04:58:03 PM PDT 24 263791996 ps
T305 /workspace/coverage/default/29.rom_ctrl_alert_test.1236824744 Jul 26 04:58:03 PM PDT 24 Jul 26 04:58:13 PM PDT 24 514624179 ps
T306 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1593773892 Jul 26 04:58:07 PM PDT 24 Jul 26 05:02:47 PM PDT 24 8315724680 ps
T14 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1472673068 Jul 26 04:57:33 PM PDT 24 Jul 26 06:20:48 PM PDT 24 16401600312 ps
T307 /workspace/coverage/default/26.rom_ctrl_alert_test.244793154 Jul 26 04:58:02 PM PDT 24 Jul 26 04:58:12 PM PDT 24 1079177129 ps
T15 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3297711150 Jul 26 04:58:00 PM PDT 24 Jul 26 05:51:28 PM PDT 24 916569114953 ps
T308 /workspace/coverage/default/26.rom_ctrl_smoke.1472233331 Jul 26 04:57:58 PM PDT 24 Jul 26 04:58:21 PM PDT 24 526955203 ps
T309 /workspace/coverage/default/13.rom_ctrl_smoke.2756246068 Jul 26 04:57:48 PM PDT 24 Jul 26 04:58:11 PM PDT 24 512972305 ps
T310 /workspace/coverage/default/31.rom_ctrl_alert_test.700753237 Jul 26 04:57:59 PM PDT 24 Jul 26 04:58:07 PM PDT 24 167867530 ps
T311 /workspace/coverage/default/47.rom_ctrl_smoke.3278366142 Jul 26 04:58:07 PM PDT 24 Jul 26 04:58:31 PM PDT 24 510359889 ps
T312 /workspace/coverage/default/13.rom_ctrl_alert_test.2678405301 Jul 26 04:58:02 PM PDT 24 Jul 26 04:58:17 PM PDT 24 986954885 ps
T313 /workspace/coverage/default/32.rom_ctrl_smoke.2551020653 Jul 26 04:58:17 PM PDT 24 Jul 26 04:58:41 PM PDT 24 1017729366 ps
T314 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.29604246 Jul 26 04:57:38 PM PDT 24 Jul 26 05:00:57 PM PDT 24 92141712400 ps
T315 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1034571512 Jul 26 04:57:50 PM PDT 24 Jul 26 04:58:02 PM PDT 24 1025956283 ps
T316 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.543427563 Jul 26 04:58:13 PM PDT 24 Jul 26 04:58:25 PM PDT 24 270420316 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.2761431944 Jul 26 04:57:44 PM PDT 24 Jul 26 05:01:31 PM PDT 24 365014549 ps
T317 /workspace/coverage/default/18.rom_ctrl_alert_test.4090840852 Jul 26 04:57:50 PM PDT 24 Jul 26 04:58:00 PM PDT 24 953578982 ps
T318 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2839661987 Jul 26 04:57:53 PM PDT 24 Jul 26 04:58:05 PM PDT 24 521797067 ps
T319 /workspace/coverage/default/8.rom_ctrl_alert_test.2140873206 Jul 26 04:57:41 PM PDT 24 Jul 26 04:57:49 PM PDT 24 174440013 ps
T320 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1951520899 Jul 26 04:58:05 PM PDT 24 Jul 26 07:09:57 PM PDT 24 16237841566 ps
T321 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2239301645 Jul 26 04:57:42 PM PDT 24 Jul 26 04:57:54 PM PDT 24 270361854 ps
T322 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3672451007 Jul 26 04:57:48 PM PDT 24 Jul 26 05:01:53 PM PDT 24 4325270796 ps
T323 /workspace/coverage/default/25.rom_ctrl_alert_test.1324209498 Jul 26 04:58:05 PM PDT 24 Jul 26 04:58:16 PM PDT 24 1901092315 ps
T324 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3015886662 Jul 26 04:58:14 PM PDT 24 Jul 26 04:58:25 PM PDT 24 179172055 ps
T325 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3013206079 Jul 26 04:57:34 PM PDT 24 Jul 26 05:00:34 PM PDT 24 11757603082 ps
T326 /workspace/coverage/default/29.rom_ctrl_stress_all.3206518320 Jul 26 04:57:56 PM PDT 24 Jul 26 04:58:30 PM PDT 24 1095980745 ps
T327 /workspace/coverage/default/11.rom_ctrl_alert_test.991060950 Jul 26 04:57:36 PM PDT 24 Jul 26 04:57:46 PM PDT 24 504287777 ps
T328 /workspace/coverage/default/41.rom_ctrl_alert_test.854848759 Jul 26 04:58:06 PM PDT 24 Jul 26 04:58:14 PM PDT 24 663724151 ps
T329 /workspace/coverage/default/15.rom_ctrl_alert_test.493907347 Jul 26 04:57:49 PM PDT 24 Jul 26 04:57:58 PM PDT 24 692397889 ps
T330 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1967221347 Jul 26 04:58:12 PM PDT 24 Jul 26 04:58:25 PM PDT 24 261737277 ps
T331 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2992025029 Jul 26 04:58:17 PM PDT 24 Jul 26 05:01:03 PM PDT 24 2787365623 ps
T332 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.934332981 Jul 26 04:57:50 PM PDT 24 Jul 26 04:59:45 PM PDT 24 1805393630 ps
T333 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.494739781 Jul 26 04:57:24 PM PDT 24 Jul 26 04:57:46 PM PDT 24 513452920 ps
T334 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1683626494 Jul 26 04:57:59 PM PDT 24 Jul 26 05:02:26 PM PDT 24 19578831447 ps
T335 /workspace/coverage/default/16.rom_ctrl_stress_all.2276366669 Jul 26 04:57:48 PM PDT 24 Jul 26 04:58:20 PM PDT 24 1108873561 ps
T336 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1233996747 Jul 26 04:57:48 PM PDT 24 Jul 26 04:58:07 PM PDT 24 2208878725 ps
T337 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3544780839 Jul 26 04:58:14 PM PDT 24 Jul 26 04:58:37 PM PDT 24 498008151 ps
T338 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1057958696 Jul 26 04:58:14 PM PDT 24 Jul 26 04:58:26 PM PDT 24 256793404 ps
T339 /workspace/coverage/default/9.rom_ctrl_smoke.1155700270 Jul 26 04:57:32 PM PDT 24 Jul 26 04:57:53 PM PDT 24 485477701 ps
T340 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.617077617 Jul 26 04:58:13 PM PDT 24 Jul 26 04:58:32 PM PDT 24 1376112055 ps
T341 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.958109773 Jul 26 04:58:14 PM PDT 24 Jul 26 05:03:20 PM PDT 24 4291218342 ps
T342 /workspace/coverage/default/37.rom_ctrl_smoke.2551464853 Jul 26 04:58:17 PM PDT 24 Jul 26 04:58:50 PM PDT 24 3983090039 ps
T343 /workspace/coverage/default/37.rom_ctrl_stress_all.1526782778 Jul 26 04:57:59 PM PDT 24 Jul 26 04:58:38 PM PDT 24 2988539013 ps
T344 /workspace/coverage/default/19.rom_ctrl_smoke.3879966505 Jul 26 04:57:48 PM PDT 24 Jul 26 04:58:12 PM PDT 24 2046165716 ps
T345 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4091822652 Jul 26 04:57:58 PM PDT 24 Jul 26 05:03:55 PM PDT 24 19293165739 ps
T346 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3730417569 Jul 26 04:58:04 PM PDT 24 Jul 26 04:58:26 PM PDT 24 1031987735 ps
T347 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2803064719 Jul 26 04:58:06 PM PDT 24 Jul 26 04:58:23 PM PDT 24 1037324765 ps
T348 /workspace/coverage/default/20.rom_ctrl_alert_test.994560199 Jul 26 04:58:10 PM PDT 24 Jul 26 04:58:20 PM PDT 24 1454195405 ps
T349 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3137339095 Jul 26 04:58:21 PM PDT 24 Jul 26 04:58:41 PM PDT 24 661732751 ps
T350 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.934034334 Jul 26 04:57:53 PM PDT 24 Jul 26 05:10:23 PM PDT 24 51606601900 ps
T351 /workspace/coverage/default/16.rom_ctrl_alert_test.277860294 Jul 26 04:58:02 PM PDT 24 Jul 26 04:58:18 PM PDT 24 5426367631 ps
T352 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1728480198 Jul 26 04:58:21 PM PDT 24 Jul 26 05:03:58 PM PDT 24 23757944199 ps
T353 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1315611515 Jul 26 04:57:48 PM PDT 24 Jul 26 05:00:55 PM PDT 24 11294785179 ps
T354 /workspace/coverage/default/1.rom_ctrl_stress_all.2019225539 Jul 26 04:57:21 PM PDT 24 Jul 26 04:57:44 PM PDT 24 1122789078 ps
T355 /workspace/coverage/default/46.rom_ctrl_alert_test.777379910 Jul 26 04:58:15 PM PDT 24 Jul 26 04:58:26 PM PDT 24 252590803 ps
T356 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1397471473 Jul 26 04:58:03 PM PDT 24 Jul 26 04:58:13 PM PDT 24 2164786524 ps
T357 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3000004371 Jul 26 04:58:06 PM PDT 24 Jul 26 04:58:17 PM PDT 24 356342086 ps
T358 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3733551941 Jul 26 04:57:59 PM PDT 24 Jul 26 04:58:16 PM PDT 24 4118772944 ps
T359 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1430729550 Jul 26 04:57:47 PM PDT 24 Jul 26 04:58:04 PM PDT 24 4148102412 ps
T360 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3586494850 Jul 26 04:58:06 PM PDT 24 Jul 26 04:58:29 PM PDT 24 517785647 ps
T361 /workspace/coverage/default/5.rom_ctrl_smoke.3832111575 Jul 26 04:57:33 PM PDT 24 Jul 26 04:57:57 PM PDT 24 517458111 ps
T362 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2297934750 Jul 26 04:58:08 PM PDT 24 Jul 26 04:58:21 PM PDT 24 542958507 ps
T363 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1540289260 Jul 26 04:58:07 PM PDT 24 Jul 26 05:03:40 PM PDT 24 26458435327 ps
T364 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3530505403 Jul 26 04:58:15 PM PDT 24 Jul 26 04:58:37 PM PDT 24 517577914 ps
T365 /workspace/coverage/default/4.rom_ctrl_smoke.282500566 Jul 26 04:57:36 PM PDT 24 Jul 26 04:57:57 PM PDT 24 1382627604 ps
T366 /workspace/coverage/default/6.rom_ctrl_smoke.3501386443 Jul 26 04:57:45 PM PDT 24 Jul 26 04:58:04 PM PDT 24 1163544350 ps
T367 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2935853180 Jul 26 04:58:07 PM PDT 24 Jul 26 05:03:09 PM PDT 24 15605846246 ps
T368 /workspace/coverage/default/22.rom_ctrl_alert_test.3771400124 Jul 26 04:57:59 PM PDT 24 Jul 26 04:58:09 PM PDT 24 260249793 ps
T369 /workspace/coverage/default/42.rom_ctrl_smoke.3271118615 Jul 26 04:58:05 PM PDT 24 Jul 26 04:58:25 PM PDT 24 345587340 ps
T370 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.546257792 Jul 26 04:58:07 PM PDT 24 Jul 26 04:58:30 PM PDT 24 2055665324 ps
T56 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1331362000 Jul 26 04:58:41 PM PDT 24 Jul 26 04:58:52 PM PDT 24 356766220 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2165697173 Jul 26 04:58:43 PM PDT 24 Jul 26 04:58:53 PM PDT 24 758383647 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2684691493 Jul 26 04:58:18 PM PDT 24 Jul 26 04:58:28 PM PDT 24 1239398789 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.467854265 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:41 PM PDT 24 340649516 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3965051000 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:53 PM PDT 24 252491681 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2025978972 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:57 PM PDT 24 690164895 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.287374559 Jul 26 04:58:21 PM PDT 24 Jul 26 04:59:56 PM PDT 24 31287890729 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2155378908 Jul 26 04:58:34 PM PDT 24 Jul 26 04:58:42 PM PDT 24 176157382 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3782597914 Jul 26 04:58:42 PM PDT 24 Jul 26 04:58:56 PM PDT 24 2256763178 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2246335115 Jul 26 04:58:28 PM PDT 24 Jul 26 04:58:44 PM PDT 24 289943778 ps
T91 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3879369455 Jul 26 04:58:37 PM PDT 24 Jul 26 04:58:47 PM PDT 24 507176890 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.245695205 Jul 26 04:58:17 PM PDT 24 Jul 26 04:58:27 PM PDT 24 249788530 ps
T92 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1964039236 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:40 PM PDT 24 496720959 ps
T53 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.302435956 Jul 26 04:58:29 PM PDT 24 Jul 26 04:59:53 PM PDT 24 250491383 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2901358582 Jul 26 04:58:20 PM PDT 24 Jul 26 04:58:30 PM PDT 24 449357356 ps
T375 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3768514528 Jul 26 04:58:21 PM PDT 24 Jul 26 04:58:32 PM PDT 24 472619917 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1133974858 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:38 PM PDT 24 721119504 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3234213929 Jul 26 04:58:39 PM PDT 24 Jul 26 04:58:48 PM PDT 24 1032260203 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2828410228 Jul 26 04:58:26 PM PDT 24 Jul 26 04:58:40 PM PDT 24 691469522 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3879563562 Jul 26 04:58:40 PM PDT 24 Jul 26 04:59:18 PM PDT 24 691898478 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4165399341 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:52 PM PDT 24 750467346 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3325888811 Jul 26 04:58:29 PM PDT 24 Jul 26 04:58:40 PM PDT 24 4121076243 ps
T68 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2594812326 Jul 26 04:58:41 PM PDT 24 Jul 26 04:59:37 PM PDT 24 4290769362 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3325388795 Jul 26 04:58:19 PM PDT 24 Jul 26 04:58:31 PM PDT 24 354677158 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2634855738 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:38 PM PDT 24 340621301 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3516909715 Jul 26 04:58:39 PM PDT 24 Jul 26 05:01:16 PM PDT 24 444331610 ps
T94 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.172214470 Jul 26 04:58:46 PM PDT 24 Jul 26 04:58:56 PM PDT 24 514681862 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.487968093 Jul 26 04:58:17 PM PDT 24 Jul 26 04:58:25 PM PDT 24 751079174 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1301207765 Jul 26 04:58:15 PM PDT 24 Jul 26 04:59:41 PM PDT 24 477126783 ps
T95 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4121329719 Jul 26 04:58:23 PM PDT 24 Jul 26 04:58:33 PM PDT 24 2247835071 ps
T381 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3362532033 Jul 26 04:58:39 PM PDT 24 Jul 26 04:58:47 PM PDT 24 345881690 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.214382505 Jul 26 04:58:45 PM PDT 24 Jul 26 04:58:53 PM PDT 24 183931847 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3126353599 Jul 26 04:58:42 PM PDT 24 Jul 26 04:58:55 PM PDT 24 554814922 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.133283417 Jul 26 04:58:29 PM PDT 24 Jul 26 04:58:38 PM PDT 24 167773534 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1265013018 Jul 26 04:58:24 PM PDT 24 Jul 26 04:59:31 PM PDT 24 6617903482 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1416357710 Jul 26 04:58:33 PM PDT 24 Jul 26 04:58:42 PM PDT 24 663126502 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2798613145 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:46 PM PDT 24 265832717 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3893829130 Jul 26 04:58:47 PM PDT 24 Jul 26 04:58:56 PM PDT 24 257084668 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.255097698 Jul 26 04:58:34 PM PDT 24 Jul 26 04:59:11 PM PDT 24 2031789733 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1326486279 Jul 26 04:58:32 PM PDT 24 Jul 26 04:58:46 PM PDT 24 692302840 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3309062433 Jul 26 04:58:41 PM PDT 24 Jul 26 04:58:56 PM PDT 24 1035243183 ps
T104 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1478852117 Jul 26 04:58:35 PM PDT 24 Jul 26 04:59:55 PM PDT 24 814525092 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1848739677 Jul 26 04:58:28 PM PDT 24 Jul 26 04:58:37 PM PDT 24 169027513 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3587332130 Jul 26 04:58:43 PM PDT 24 Jul 26 05:01:18 PM PDT 24 786092399 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4072828759 Jul 26 04:58:34 PM PDT 24 Jul 26 04:58:51 PM PDT 24 516434305 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1650942312 Jul 26 04:58:22 PM PDT 24 Jul 26 04:58:30 PM PDT 24 687660970 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.799117894 Jul 26 04:58:22 PM PDT 24 Jul 26 05:00:56 PM PDT 24 1470931654 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2431543368 Jul 26 04:58:38 PM PDT 24 Jul 26 04:58:52 PM PDT 24 507806896 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2609775661 Jul 26 04:58:18 PM PDT 24 Jul 26 04:58:28 PM PDT 24 4957166173 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3565421947 Jul 26 04:58:46 PM PDT 24 Jul 26 05:01:21 PM PDT 24 1204659057 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1837752298 Jul 26 04:58:21 PM PDT 24 Jul 26 04:59:18 PM PDT 24 4122965844 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1550934067 Jul 26 04:58:14 PM PDT 24 Jul 26 04:58:22 PM PDT 24 533708601 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3143875341 Jul 26 04:58:22 PM PDT 24 Jul 26 04:58:33 PM PDT 24 1076079729 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2652532684 Jul 26 04:58:26 PM PDT 24 Jul 26 04:58:37 PM PDT 24 506460730 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2003567062 Jul 26 04:58:32 PM PDT 24 Jul 26 04:58:42 PM PDT 24 257466241 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3187534873 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:43 PM PDT 24 688035940 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.877221655 Jul 26 04:58:44 PM PDT 24 Jul 26 04:59:27 PM PDT 24 2896076937 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2284076606 Jul 26 04:58:57 PM PDT 24 Jul 26 05:01:30 PM PDT 24 429928417 ps
T396 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3429156552 Jul 26 04:58:31 PM PDT 24 Jul 26 04:58:43 PM PDT 24 1857210860 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.242578656 Jul 26 04:58:46 PM PDT 24 Jul 26 04:58:56 PM PDT 24 576970857 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1058042703 Jul 26 04:58:24 PM PDT 24 Jul 26 04:58:32 PM PDT 24 755971189 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3269235027 Jul 26 04:58:42 PM PDT 24 Jul 26 04:58:52 PM PDT 24 534061739 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4210604532 Jul 26 04:58:25 PM PDT 24 Jul 26 04:58:33 PM PDT 24 3299999764 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1655200186 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:43 PM PDT 24 172634149 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3491846467 Jul 26 04:58:46 PM PDT 24 Jul 26 04:58:55 PM PDT 24 1028671287 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2870999013 Jul 26 04:58:37 PM PDT 24 Jul 26 04:59:59 PM PDT 24 1300836140 ps
T402 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.392243474 Jul 26 04:58:33 PM PDT 24 Jul 26 04:58:51 PM PDT 24 4114407514 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1378871958 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:41 PM PDT 24 509447523 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.161924682 Jul 26 04:58:36 PM PDT 24 Jul 26 05:01:14 PM PDT 24 2243020641 ps
T404 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1296903730 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:54 PM PDT 24 3219529106 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2625930321 Jul 26 04:58:24 PM PDT 24 Jul 26 04:58:37 PM PDT 24 486701777 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.72997967 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:54 PM PDT 24 504794103 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3366879284 Jul 26 04:58:37 PM PDT 24 Jul 26 05:01:14 PM PDT 24 13559226189 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2141846680 Jul 26 04:58:29 PM PDT 24 Jul 26 04:58:38 PM PDT 24 169390916 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2957677562 Jul 26 04:58:36 PM PDT 24 Jul 26 04:58:48 PM PDT 24 1126047253 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2598427834 Jul 26 04:58:22 PM PDT 24 Jul 26 04:59:28 PM PDT 24 1589651686 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.331000091 Jul 26 04:58:36 PM PDT 24 Jul 26 04:58:44 PM PDT 24 569677842 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.721467349 Jul 26 04:58:33 PM PDT 24 Jul 26 04:58:48 PM PDT 24 1046065735 ps
T112 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4120752770 Jul 26 04:58:43 PM PDT 24 Jul 26 05:01:17 PM PDT 24 370382636 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4017553686 Jul 26 04:58:41 PM PDT 24 Jul 26 04:58:52 PM PDT 24 1063366330 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.223626923 Jul 26 04:58:18 PM PDT 24 Jul 26 04:58:26 PM PDT 24 718057530 ps
T414 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3829915244 Jul 26 04:58:44 PM PDT 24 Jul 26 04:58:54 PM PDT 24 3081575821 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2661506823 Jul 26 04:58:37 PM PDT 24 Jul 26 04:58:49 PM PDT 24 508649282 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1020321873 Jul 26 04:58:20 PM PDT 24 Jul 26 04:58:28 PM PDT 24 972215872 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2497712090 Jul 26 04:58:16 PM PDT 24 Jul 26 04:58:25 PM PDT 24 689624743 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3993572287 Jul 26 04:58:36 PM PDT 24 Jul 26 05:01:06 PM PDT 24 1447187216 ps
T82 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3774607741 Jul 26 04:58:31 PM PDT 24 Jul 26 04:58:41 PM PDT 24 1031206084 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2480143753 Jul 26 04:58:46 PM PDT 24 Jul 26 05:01:18 PM PDT 24 4605043579 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3915699995 Jul 26 04:58:34 PM PDT 24 Jul 26 04:58:48 PM PDT 24 347802267 ps
T421 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1907865253 Jul 26 04:58:39 PM PDT 24 Jul 26 04:58:55 PM PDT 24 258889743 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2627493248 Jul 26 04:58:37 PM PDT 24 Jul 26 04:58:47 PM PDT 24 497668800 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.282020159 Jul 26 04:58:41 PM PDT 24 Jul 26 04:58:56 PM PDT 24 9822889879 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4154602514 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:53 PM PDT 24 3530371779 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2623397808 Jul 26 04:58:31 PM PDT 24 Jul 26 04:59:09 PM PDT 24 2853803547 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.901800289 Jul 26 04:58:40 PM PDT 24 Jul 26 04:58:49 PM PDT 24 187123470 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1300507739 Jul 26 04:58:43 PM PDT 24 Jul 26 04:58:52 PM PDT 24 699149614 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2386884084 Jul 26 04:58:47 PM PDT 24 Jul 26 04:59:01 PM PDT 24 520644223 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2164342553 Jul 26 04:58:31 PM PDT 24 Jul 26 04:58:40 PM PDT 24 722233459 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2095688583 Jul 26 04:58:23 PM PDT 24 Jul 26 04:58:35 PM PDT 24 261413816 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4082459593 Jul 26 04:58:40 PM PDT 24 Jul 26 04:58:50 PM PDT 24 701215715 ps
T431 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2499945498 Jul 26 04:58:43 PM PDT 24 Jul 26 04:59:28 PM PDT 24 10088535891 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.154201341 Jul 26 04:58:21 PM PDT 24 Jul 26 04:58:29 PM PDT 24 611949450 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1853911981 Jul 26 04:58:32 PM PDT 24 Jul 26 04:59:38 PM PDT 24 1624596754 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4064421457 Jul 26 04:58:39 PM PDT 24 Jul 26 04:58:48 PM PDT 24 1963332713 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2055831603 Jul 26 04:58:30 PM PDT 24 Jul 26 04:58:43 PM PDT 24 259096198 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.692937199 Jul 26 04:58:47 PM PDT 24 Jul 26 04:58:58 PM PDT 24 660931882 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3605955494 Jul 26 04:58:27 PM PDT 24 Jul 26 04:58:38 PM PDT 24 1031990702 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3561728292 Jul 26 04:58:24 PM PDT 24 Jul 26 04:58:32 PM PDT 24 665378503 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2099735235 Jul 26 04:58:23 PM PDT 24 Jul 26 04:58:43 PM PDT 24 14075366070 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4077898938 Jul 26 04:58:49 PM PDT 24 Jul 26 04:59:00 PM PDT 24 168270922 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1876023029 Jul 26 04:58:37 PM PDT 24 Jul 26 04:58:45 PM PDT 24 174723977 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.431592689 Jul 26 04:58:17 PM PDT 24 Jul 26 04:58:30 PM PDT 24 486825961 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.634554439 Jul 26 04:58:38 PM PDT 24 Jul 26 04:59:20 PM PDT 24 7261909579 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2637372036 Jul 26 04:58:46 PM PDT 24 Jul 26 04:59:29 PM PDT 24 11274149969 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2314930096 Jul 26 04:58:24 PM PDT 24 Jul 26 04:58:38 PM PDT 24 950782516 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2839434192 Jul 26 04:58:19 PM PDT 24 Jul 26 04:58:35 PM PDT 24 707993439 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3047193850 Jul 26 04:58:47 PM PDT 24 Jul 26 04:58:57 PM PDT 24 254352124 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.225033430 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:45 PM PDT 24 1034033178 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4164406805 Jul 26 04:58:20 PM PDT 24 Jul 26 04:59:44 PM PDT 24 1275701222 ps
T113 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3129326078 Jul 26 04:58:19 PM PDT 24 Jul 26 05:00:56 PM PDT 24 789587744 ps
T88 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3498996024 Jul 26 04:58:39 PM PDT 24 Jul 26 04:59:35 PM PDT 24 7876295966 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1162307692 Jul 26 04:58:26 PM PDT 24 Jul 26 04:58:35 PM PDT 24 665231606 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.551784959 Jul 26 04:58:45 PM PDT 24 Jul 26 04:59:01 PM PDT 24 4166336071 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3330168056 Jul 26 04:58:36 PM PDT 24 Jul 26 04:59:43 PM PDT 24 6083260652 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.712171593 Jul 26 04:58:20 PM PDT 24 Jul 26 04:58:28 PM PDT 24 1835137097 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.645523743 Jul 26 04:58:25 PM PDT 24 Jul 26 04:58:33 PM PDT 24 660708937 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2866571573 Jul 26 04:58:16 PM PDT 24 Jul 26 04:58:26 PM PDT 24 4925281937 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.224858252 Jul 26 04:58:22 PM PDT 24 Jul 26 04:58:37 PM PDT 24 4093248590 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3917496547 Jul 26 04:58:29 PM PDT 24 Jul 26 04:59:50 PM PDT 24 373106847 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1640582922 Jul 26 04:58:30 PM PDT 24 Jul 26 04:59:50 PM PDT 24 334756946 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3157344410 Jul 26 04:58:35 PM PDT 24 Jul 26 04:58:46 PM PDT 24 1073185837 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.844647439 Jul 26 04:58:30 PM PDT 24 Jul 26 05:01:03 PM PDT 24 316831124 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1836531611 Jul 26 04:58:37 PM PDT 24 Jul 26 04:58:48 PM PDT 24 368293944 ps
T458 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1155817251 Jul 26 04:58:38 PM PDT 24 Jul 26 04:58:51 PM PDT 24 722122691 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3365816000 Jul 26 04:58:46 PM PDT 24 Jul 26 04:58:56 PM PDT 24 258528121 ps
T89 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3594897511 Jul 26 04:58:40 PM PDT 24 Jul 26 04:59:18 PM PDT 24 4278999602 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3562010376 Jul 26 04:58:39 PM PDT 24 Jul 26 04:59:17 PM PDT 24 3121541790 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4277040401 Jul 26 04:58:40 PM PDT 24 Jul 26 04:58:49 PM PDT 24 4956853584 ps
T462 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2723859047 Jul 26 04:58:39 PM PDT 24 Jul 26 04:58:49 PM PDT 24 517307985 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2514465151 Jul 26 04:58:29 PM PDT 24 Jul 26 04:58:40 PM PDT 24 506999553 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.361320170 Jul 26 04:58:36 PM PDT 24 Jul 26 04:58:52 PM PDT 24 707075904 ps
T465 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2952273410 Jul 26 04:58:38 PM PDT 24 Jul 26 05:01:15 PM PDT 24 506455906 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.873504130 Jul 26 04:58:32 PM PDT 24 Jul 26 04:59:38 PM PDT 24 2118072513 ps
T466 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3197809961 Jul 26 04:58:38 PM PDT 24 Jul 26 04:59:15 PM PDT 24 2743420984 ps
T467 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2707332099 Jul 26 04:58:42 PM PDT 24 Jul 26 04:59:48 PM PDT 24 3056260331 ps

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.17791050
Short name T9
Test name
Test status
Simulation time 2678312075 ps
CPU time 71.4 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:59:14 PM PDT 24
Peak memory 220308 kb
Host smart-340837a7-3e1e-4d02-a958-f81f7fa77124
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.rom_ctrl_stress_all.17791050
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.137816408
Short name T11
Test name
Test status
Simulation time 79902576512 ps
CPU time 759.49 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 05:10:21 PM PDT 24
Peak memory 233936 kb
Host smart-47b316e5-60cb-42c8-a290-66bb17edb770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137816408 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.137816408
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3550697321
Short name T21
Test name
Test status
Simulation time 13013666726 ps
CPU time 245.94 seconds
Started Jul 26 04:57:49 PM PDT 24
Finished Jul 26 05:01:55 PM PDT 24
Peak memory 240880 kb
Host smart-d54a8136-79dd-4c4b-a067-5da0b96b24b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550697321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3550697321
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2593181677
Short name T40
Test name
Test status
Simulation time 131907704724 ps
CPU time 628.52 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 05:08:07 PM PDT 24
Peak memory 235292 kb
Host smart-7e0ed0ec-600d-479d-863d-f9866a426c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593181677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2593181677
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1188915162
Short name T115
Test name
Test status
Simulation time 21805217931 ps
CPU time 285.63 seconds
Started Jul 26 04:57:57 PM PDT 24
Finished Jul 26 05:02:43 PM PDT 24
Peak memory 240576 kb
Host smart-5854e40b-d33f-493b-a811-bacd0055ff3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188915162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1188915162
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3516909715
Short name T54
Test name
Test status
Simulation time 444331610 ps
CPU time 157.25 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 05:01:16 PM PDT 24
Peak memory 215048 kb
Host smart-ddc42e3d-4d7e-49ae-be68-8f1a928e66da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516909715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3516909715
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1901893128
Short name T6
Test name
Test status
Simulation time 8574567090 ps
CPU time 32.79 seconds
Started Jul 26 04:58:03 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 219848 kb
Host smart-e3751946-1c9d-4ec0-893d-df5a67c3e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901893128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1901893128
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2623135487
Short name T25
Test name
Test status
Simulation time 700966891 ps
CPU time 120.17 seconds
Started Jul 26 04:57:31 PM PDT 24
Finished Jul 26 04:59:32 PM PDT 24
Peak memory 238688 kb
Host smart-6c9b275d-d481-43a7-9042-bae33567bbf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623135487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2623135487
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.161924682
Short name T105
Test name
Test status
Simulation time 2243020641 ps
CPU time 157.79 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 05:01:14 PM PDT 24
Peak memory 213876 kb
Host smart-221244db-d917-427f-b60c-d460cf330457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161924682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.161924682
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.207780766
Short name T2
Test name
Test status
Simulation time 227028299 ps
CPU time 11.52 seconds
Started Jul 26 04:58:23 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 219168 kb
Host smart-9cbde398-9010-4208-95d1-09aea6a027ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207780766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.207780766
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.877221655
Short name T80
Test name
Test status
Simulation time 2896076937 ps
CPU time 43.15 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:59:27 PM PDT 24
Peak memory 218596 kb
Host smart-3f80e1b5-1549-4e27-bb10-519f64b71d88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877221655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.877221655
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2767919719
Short name T60
Test name
Test status
Simulation time 615018332 ps
CPU time 8.29 seconds
Started Jul 26 04:57:20 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 218768 kb
Host smart-2162da6e-75f3-404f-88d0-b341707a73b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767919719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2767919719
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.245695205
Short name T66
Test name
Test status
Simulation time 249788530 ps
CPU time 9.66 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:27 PM PDT 24
Peak memory 211148 kb
Host smart-d48ce620-8fe0-4f75-992d-ed3b8cb1b687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245695205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.245695205
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3929176554
Short name T37
Test name
Test status
Simulation time 661198345 ps
CPU time 19.09 seconds
Started Jul 26 04:57:54 PM PDT 24
Finished Jul 26 04:58:13 PM PDT 24
Peak memory 219728 kb
Host smart-3cba2588-d130-4159-a275-222af2e53bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929176554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3929176554
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3286467771
Short name T31
Test name
Test status
Simulation time 4015072632 ps
CPU time 31.4 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 219256 kb
Host smart-1cdcf3fc-74d9-4759-8850-15f23336e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286467771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3286467771
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3565421947
Short name T109
Test name
Test status
Simulation time 1204659057 ps
CPU time 154.61 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 05:01:21 PM PDT 24
Peak memory 212756 kb
Host smart-183aee0d-fca5-458c-a93c-459e9a1617d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565421947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3565421947
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1265013018
Short name T70
Test name
Test status
Simulation time 6617903482 ps
CPU time 66.32 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 04:59:31 PM PDT 24
Peak memory 214216 kb
Host smart-74dee3b5-cb76-4162-a7c3-0e8a042cd447
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265013018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1265013018
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1640582922
Short name T110
Test name
Test status
Simulation time 334756946 ps
CPU time 80.41 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:59:50 PM PDT 24
Peak memory 213280 kb
Host smart-ecdc4c7c-e2a9-4e26-9219-72e0fee2b21c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640582922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1640582922
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1648092366
Short name T32
Test name
Test status
Simulation time 8805379427 ps
CPU time 31.52 seconds
Started Jul 26 04:57:43 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 220580 kb
Host smart-8b99c5ec-1cab-4d56-83a6-a6e8a0f95c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648092366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1648092366
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1550934067
Short name T79
Test name
Test status
Simulation time 533708601 ps
CPU time 7.83 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 210604 kb
Host smart-0599f1a4-d1d9-4ae7-b117-37fb00ac5f42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550934067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1550934067
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2497712090
Short name T417
Test name
Test status
Simulation time 689624743 ps
CPU time 8.35 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 210968 kb
Host smart-2d36c9fe-e05d-4b32-ad7f-9b2c1f3e1d44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497712090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2497712090
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2839434192
Short name T444
Test name
Test status
Simulation time 707993439 ps
CPU time 15.25 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 211948 kb
Host smart-f615cfdb-dee4-4594-8b8b-cdc9b483eecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839434192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2839434192
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.214382505
Short name T382
Test name
Test status
Simulation time 183931847 ps
CPU time 8.6 seconds
Started Jul 26 04:58:45 PM PDT 24
Finished Jul 26 04:58:53 PM PDT 24
Peak memory 215164 kb
Host smart-3413457d-0c6e-4e36-ae0b-cbb97b488d81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214382505 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.214382505
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2866571573
Short name T85
Test name
Test status
Simulation time 4925281937 ps
CPU time 9.81 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 211416 kb
Host smart-0dd33e69-5bfd-41ff-9559-a6345559683a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866571573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2866571573
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.712171593
Short name T451
Test name
Test status
Simulation time 1835137097 ps
CPU time 8.08 seconds
Started Jul 26 04:58:20 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 210292 kb
Host smart-df31c92c-8aa4-4819-9d88-9184fa101481
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712171593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.712171593
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.487968093
Short name T380
Test name
Test status
Simulation time 751079174 ps
CPU time 7.93 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 210456 kb
Host smart-6ba26a46-ddf5-4511-a216-ecf2cf0250c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487968093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
487968093
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.431592689
Short name T440
Test name
Test status
Simulation time 486825961 ps
CPU time 12.78 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 217152 kb
Host smart-c59cdf24-1562-4a74-94c3-fa4cd6e09a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431592689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.431592689
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1301207765
Short name T55
Test name
Test status
Simulation time 477126783 ps
CPU time 85.73 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:59:41 PM PDT 24
Peak memory 213640 kb
Host smart-5927775a-d1db-4db6-9db2-3d0aaec4022f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301207765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1301207765
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3561728292
Short name T437
Test name
Test status
Simulation time 665378503 ps
CPU time 8.43 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 04:58:32 PM PDT 24
Peak memory 210860 kb
Host smart-791c6b82-bd8e-4e8f-8ae0-95c7367d3a72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561728292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3561728292
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2652532684
Short name T393
Test name
Test status
Simulation time 506460730 ps
CPU time 9.93 seconds
Started Jul 26 04:58:26 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 210552 kb
Host smart-80ddd600-987f-4d9d-9825-1300b9803442
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652532684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2652532684
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4072828759
Short name T72
Test name
Test status
Simulation time 516434305 ps
CPU time 16.86 seconds
Started Jul 26 04:58:34 PM PDT 24
Finished Jul 26 04:58:51 PM PDT 24
Peak memory 211776 kb
Host smart-e4619c3c-6562-4d17-b867-85d2afcbec63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072828759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4072828759
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1378871958
Short name T403
Test name
Test status
Simulation time 509447523 ps
CPU time 10.27 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 216420 kb
Host smart-de14b95a-b239-4109-a278-afde67b80503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378871958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1378871958
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.645523743
Short name T452
Test name
Test status
Simulation time 660708937 ps
CPU time 8 seconds
Started Jul 26 04:58:25 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 210864 kb
Host smart-d74c7b4e-d88c-4865-a828-4d82ed310047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645523743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.645523743
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2514465151
Short name T463
Test name
Test status
Simulation time 506999553 ps
CPU time 9.74 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 210460 kb
Host smart-0b1b58fe-e652-41f5-8fae-8db1a78acd8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514465151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2514465151
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.224858252
Short name T453
Test name
Test status
Simulation time 4093248590 ps
CPU time 14.66 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 210764 kb
Host smart-73b4180f-d13d-4936-beed-9375f2683abb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224858252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
224858252
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.255097698
Short name T71
Test name
Test status
Simulation time 2031789733 ps
CPU time 37.24 seconds
Started Jul 26 04:58:34 PM PDT 24
Finished Jul 26 04:59:11 PM PDT 24
Peak memory 213988 kb
Host smart-826f5a03-fb0a-4070-85b5-af617749781a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255097698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.255097698
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2141846680
Short name T407
Test name
Test status
Simulation time 169390916 ps
CPU time 8.11 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 211160 kb
Host smart-4498a397-d94b-4969-865d-fa9316c2ca2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141846680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2141846680
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4154602514
Short name T424
Test name
Test status
Simulation time 3530371779 ps
CPU time 17.63 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:53 PM PDT 24
Peak memory 218340 kb
Host smart-fc9da0e0-8e3d-450a-99dc-7934bad3aace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154602514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4154602514
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4164406805
Short name T447
Test name
Test status
Simulation time 1275701222 ps
CPU time 84 seconds
Started Jul 26 04:58:20 PM PDT 24
Finished Jul 26 04:59:44 PM PDT 24
Peak memory 213728 kb
Host smart-c99bde59-762f-4d0e-807c-f09f23e0ac78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164406805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4164406805
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.242578656
Short name T397
Test name
Test status
Simulation time 576970857 ps
CPU time 10.16 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 216744 kb
Host smart-5f6bf87a-36c2-4366-b767-7c8d2fe64ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242578656 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.242578656
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3325888811
Short name T378
Test name
Test status
Simulation time 4121076243 ps
CPU time 10.01 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 210792 kb
Host smart-eccffb1a-5c95-4c80-92ea-2f0979f32cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325888811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3325888811
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2707332099
Short name T467
Test name
Test status
Simulation time 3056260331 ps
CPU time 65.6 seconds
Started Jul 26 04:58:42 PM PDT 24
Finished Jul 26 04:59:48 PM PDT 24
Peak memory 214200 kb
Host smart-213c8854-e290-4620-bff2-616ce52c9dae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707332099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2707332099
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1155817251
Short name T458
Test name
Test status
Simulation time 722122691 ps
CPU time 12.29 seconds
Started Jul 26 04:58:38 PM PDT 24
Finished Jul 26 04:58:51 PM PDT 24
Peak memory 212280 kb
Host smart-655d4f1e-2bc7-443c-bc71-66aa45985202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155817251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1155817251
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2099735235
Short name T438
Test name
Test status
Simulation time 14075366070 ps
CPU time 19.83 seconds
Started Jul 26 04:58:23 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 218984 kb
Host smart-96b836b7-5de4-475e-8e83-87a96895d0de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099735235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2099735235
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4017553686
Short name T412
Test name
Test status
Simulation time 1063366330 ps
CPU time 10.55 seconds
Started Jul 26 04:58:41 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 215216 kb
Host smart-d64f6d7d-b06b-4933-896b-fdf8d9f04ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017553686 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4017553686
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3362532033
Short name T381
Test name
Test status
Simulation time 345881690 ps
CPU time 8.22 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 210508 kb
Host smart-83082c79-7ed5-4c74-bf94-4b89e1c24db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362532033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3362532033
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1853911981
Short name T84
Test name
Test status
Simulation time 1624596754 ps
CPU time 66.21 seconds
Started Jul 26 04:58:32 PM PDT 24
Finished Jul 26 04:59:38 PM PDT 24
Peak memory 213752 kb
Host smart-fd00a55b-8291-4d33-a1ee-c9ddd012ad65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853911981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1853911981
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2723859047
Short name T462
Test name
Test status
Simulation time 517307985 ps
CPU time 10.16 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 211512 kb
Host smart-57c38df0-32e2-4129-b4f6-379695dfca5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723859047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2723859047
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2957677562
Short name T408
Test name
Test status
Simulation time 1126047253 ps
CPU time 12.28 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 217116 kb
Host smart-130bc55a-24e0-408d-8c53-9b02f0ea3956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957677562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2957677562
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3366879284
Short name T111
Test name
Test status
Simulation time 13559226189 ps
CPU time 156.86 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 05:01:14 PM PDT 24
Peak memory 214284 kb
Host smart-0224466d-1ce4-4918-84f0-64e405044eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366879284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3366879284
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.901800289
Short name T425
Test name
Test status
Simulation time 187123470 ps
CPU time 9 seconds
Started Jul 26 04:58:40 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 217120 kb
Host smart-b5807a4e-ccbe-4345-8dc3-0cfb6a0574c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901800289 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.901800289
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3879369455
Short name T91
Test name
Test status
Simulation time 507176890 ps
CPU time 9.78 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 210612 kb
Host smart-a521f14c-a121-44cd-af10-8f696420c4ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879369455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3879369455
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.873504130
Short name T86
Test name
Test status
Simulation time 2118072513 ps
CPU time 66.01 seconds
Started Jul 26 04:58:32 PM PDT 24
Finished Jul 26 04:59:38 PM PDT 24
Peak memory 218688 kb
Host smart-22a6de69-8f1b-4619-b861-761419756cc3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873504130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.873504130
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.392243474
Short name T402
Test name
Test status
Simulation time 4114407514 ps
CPU time 18.64 seconds
Started Jul 26 04:58:33 PM PDT 24
Finished Jul 26 04:58:51 PM PDT 24
Peak memory 212464 kb
Host smart-78943dd9-8467-4fbe-aa17-5296d02b45d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392243474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.392243474
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3126353599
Short name T383
Test name
Test status
Simulation time 554814922 ps
CPU time 12.38 seconds
Started Jul 26 04:58:42 PM PDT 24
Finished Jul 26 04:58:55 PM PDT 24
Peak memory 218524 kb
Host smart-703316da-c10a-42e3-afcb-7ab97049e437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126353599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3126353599
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3917496547
Short name T454
Test name
Test status
Simulation time 373106847 ps
CPU time 81.47 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:59:50 PM PDT 24
Peak memory 213500 kb
Host smart-288f4036-a9a1-4540-be76-d9206dc2d69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917496547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3917496547
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3157344410
Short name T455
Test name
Test status
Simulation time 1073185837 ps
CPU time 10.96 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:46 PM PDT 24
Peak memory 216964 kb
Host smart-32112fa9-7b10-41df-9e05-e1705d185eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157344410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3157344410
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1876023029
Short name T87
Test name
Test status
Simulation time 174723977 ps
CPU time 8.22 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:58:45 PM PDT 24
Peak memory 210472 kb
Host smart-093be143-e319-452b-a049-2d052094ae51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876023029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1876023029
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2637372036
Short name T442
Test name
Test status
Simulation time 11274149969 ps
CPU time 42.55 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 04:59:29 PM PDT 24
Peak memory 213884 kb
Host smart-834269cf-7c02-492b-a821-495efb7a209e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637372036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2637372036
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2431543368
Short name T390
Test name
Test status
Simulation time 507806896 ps
CPU time 13.87 seconds
Started Jul 26 04:58:38 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 212548 kb
Host smart-48961a97-e6a4-4a12-ac0c-32334df792bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431543368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2431543368
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3309062433
Short name T388
Test name
Test status
Simulation time 1035243183 ps
CPU time 14.34 seconds
Started Jul 26 04:58:41 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 217436 kb
Host smart-b552c457-c688-45ce-8214-be82fb7ee6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309062433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3309062433
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.302435956
Short name T53
Test name
Test status
Simulation time 250491383 ps
CPU time 82.9 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:59:53 PM PDT 24
Peak memory 213552 kb
Host smart-05d27d8a-3fbb-4030-b7e9-a2f181c688ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302435956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.302435956
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4064421457
Short name T433
Test name
Test status
Simulation time 1963332713 ps
CPU time 8.91 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 216540 kb
Host smart-7139408e-e441-4bc3-9f6e-11d660856e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064421457 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4064421457
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4277040401
Short name T461
Test name
Test status
Simulation time 4956853584 ps
CPU time 9.75 seconds
Started Jul 26 04:58:40 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 211300 kb
Host smart-924f5605-79f5-4a8e-8a77-9745415bb619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277040401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4277040401
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2594812326
Short name T68
Test name
Test status
Simulation time 4290769362 ps
CPU time 55.99 seconds
Started Jul 26 04:58:41 PM PDT 24
Finished Jul 26 04:59:37 PM PDT 24
Peak memory 211432 kb
Host smart-2bfd1ec6-194d-4fb3-ad85-95eea5b7d695
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594812326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2594812326
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1964039236
Short name T92
Test name
Test status
Simulation time 496720959 ps
CPU time 9.85 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 211688 kb
Host smart-1fc52e0a-87a7-4cf4-893f-573d6672d445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964039236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1964039236
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1326486279
Short name T387
Test name
Test status
Simulation time 692302840 ps
CPU time 13.1 seconds
Started Jul 26 04:58:32 PM PDT 24
Finished Jul 26 04:58:46 PM PDT 24
Peak memory 217448 kb
Host smart-d34776c0-b043-4062-92e0-f064e231f009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326486279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1326486279
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1300507739
Short name T426
Test name
Test status
Simulation time 699149614 ps
CPU time 8.62 seconds
Started Jul 26 04:58:43 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 215668 kb
Host smart-fca8063d-7711-4b49-ab0d-fc801f0ac4c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300507739 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1300507739
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1416357710
Short name T384
Test name
Test status
Simulation time 663126502 ps
CPU time 8.21 seconds
Started Jul 26 04:58:33 PM PDT 24
Finished Jul 26 04:58:42 PM PDT 24
Peak memory 210784 kb
Host smart-ae76f768-b3ed-4c97-af05-9c0c5aa62217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416357710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1416357710
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3594897511
Short name T89
Test name
Test status
Simulation time 4278999602 ps
CPU time 38.55 seconds
Started Jul 26 04:58:40 PM PDT 24
Finished Jul 26 04:59:18 PM PDT 24
Peak memory 213968 kb
Host smart-ca7345c3-6b30-4790-8685-750441911d61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594897511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3594897511
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.331000091
Short name T410
Test name
Test status
Simulation time 569677842 ps
CPU time 8.26 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 04:58:44 PM PDT 24
Peak memory 211424 kb
Host smart-a5caacc8-71c3-4612-b670-ddb201b2ec2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331000091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.331000091
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.467854265
Short name T371
Test name
Test status
Simulation time 340649516 ps
CPU time 11.45 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 216736 kb
Host smart-fc378e74-98f3-4968-9af6-732bef06e6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467854265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.467854265
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2952273410
Short name T465
Test name
Test status
Simulation time 506455906 ps
CPU time 157.2 seconds
Started Jul 26 04:58:38 PM PDT 24
Finished Jul 26 05:01:15 PM PDT 24
Peak memory 213980 kb
Host smart-68dbf266-6534-4b67-afd2-facdf079bc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952273410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2952273410
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4082459593
Short name T430
Test name
Test status
Simulation time 701215715 ps
CPU time 8.72 seconds
Started Jul 26 04:58:40 PM PDT 24
Finished Jul 26 04:58:50 PM PDT 24
Peak memory 215652 kb
Host smart-8cf49e31-2c8f-4ee4-b57c-b190d7078239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082459593 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4082459593
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3774607741
Short name T82
Test name
Test status
Simulation time 1031206084 ps
CPU time 9.75 seconds
Started Jul 26 04:58:31 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 210904 kb
Host smart-5f6b3f40-9bd7-4b00-adbd-d703a9ad53aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774607741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3774607741
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3197809961
Short name T466
Test name
Test status
Simulation time 2743420984 ps
CPU time 37.03 seconds
Started Jul 26 04:58:38 PM PDT 24
Finished Jul 26 04:59:15 PM PDT 24
Peak memory 213836 kb
Host smart-04ec8a32-601b-420b-b42b-3d4824252e50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197809961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3197809961
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2164342553
Short name T428
Test name
Test status
Simulation time 722233459 ps
CPU time 8.1 seconds
Started Jul 26 04:58:31 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 211180 kb
Host smart-f92f9c67-76c4-4c45-b150-0fd0dbac8f5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164342553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2164342553
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1836531611
Short name T457
Test name
Test status
Simulation time 368293944 ps
CPU time 10.92 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 218128 kb
Host smart-ebb0b9c5-d57f-4cd3-8921-38a947400128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836531611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1836531611
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2870999013
Short name T108
Test name
Test status
Simulation time 1300836140 ps
CPU time 81.14 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:59:59 PM PDT 24
Peak memory 213616 kb
Host smart-3c475f86-cd1b-4adb-8305-e923ec8312c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870999013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2870999013
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2165697173
Short name T57
Test name
Test status
Simulation time 758383647 ps
CPU time 9.97 seconds
Started Jul 26 04:58:43 PM PDT 24
Finished Jul 26 04:58:53 PM PDT 24
Peak memory 213988 kb
Host smart-abbe445d-ef89-4a7e-85af-86d8ef2621d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165697173 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2165697173
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4165399341
Short name T67
Test name
Test status
Simulation time 750467346 ps
CPU time 8.25 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 210992 kb
Host smart-34b667f2-ec9b-4185-b60f-364c98e1127f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165399341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4165399341
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3562010376
Short name T460
Test name
Test status
Simulation time 3121541790 ps
CPU time 37.88 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:59:17 PM PDT 24
Peak memory 214068 kb
Host smart-2da5f288-b326-4f14-a0b0-f54a0cdf1dfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562010376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3562010376
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3047193850
Short name T445
Test name
Test status
Simulation time 254352124 ps
CPU time 9.87 seconds
Started Jul 26 04:58:47 PM PDT 24
Finished Jul 26 04:58:57 PM PDT 24
Peak memory 210800 kb
Host smart-62785fe2-0535-4c4e-aca0-7c197fb105bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047193850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3047193850
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2386884084
Short name T427
Test name
Test status
Simulation time 520644223 ps
CPU time 14.09 seconds
Started Jul 26 04:58:47 PM PDT 24
Finished Jul 26 04:59:01 PM PDT 24
Peak memory 217644 kb
Host smart-df3555b1-15aa-4133-97fd-03b9e2b1f869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386884084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2386884084
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4120752770
Short name T112
Test name
Test status
Simulation time 370382636 ps
CPU time 153.66 seconds
Started Jul 26 04:58:43 PM PDT 24
Finished Jul 26 05:01:17 PM PDT 24
Peak memory 214032 kb
Host smart-89322817-4f14-4eec-96f6-d8cec2993c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120752770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4120752770
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1331362000
Short name T56
Test name
Test status
Simulation time 356766220 ps
CPU time 10.73 seconds
Started Jul 26 04:58:41 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 217460 kb
Host smart-a876d48f-68df-4eae-a780-4d2d464e611f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331362000 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1331362000
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3491846467
Short name T401
Test name
Test status
Simulation time 1028671287 ps
CPU time 9.57 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 04:58:55 PM PDT 24
Peak memory 210836 kb
Host smart-28fb8d5b-5bfb-4d71-ae57-4ea31c205e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491846467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3491846467
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3879563562
Short name T99
Test name
Test status
Simulation time 691898478 ps
CPU time 38.06 seconds
Started Jul 26 04:58:40 PM PDT 24
Finished Jul 26 04:59:18 PM PDT 24
Peak memory 218708 kb
Host smart-82ee081e-2c13-48ee-8637-42f13e655597
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879563562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3879563562
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.172214470
Short name T94
Test name
Test status
Simulation time 514681862 ps
CPU time 9.76 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 211280 kb
Host smart-7175773a-2e3d-4552-8508-347f64149056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172214470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.172214470
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.692937199
Short name T435
Test name
Test status
Simulation time 660931882 ps
CPU time 11.19 seconds
Started Jul 26 04:58:47 PM PDT 24
Finished Jul 26 04:58:58 PM PDT 24
Peak memory 218368 kb
Host smart-044d4080-815c-4a5b-9f27-22a75563f02e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692937199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.692937199
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2480143753
Short name T419
Test name
Test status
Simulation time 4605043579 ps
CPU time 152.34 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 05:01:18 PM PDT 24
Peak memory 214152 kb
Host smart-cac25e4f-8979-4dc3-9bee-6282ba271896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480143753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2480143753
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.551784959
Short name T449
Test name
Test status
Simulation time 4166336071 ps
CPU time 15.71 seconds
Started Jul 26 04:58:45 PM PDT 24
Finished Jul 26 04:59:01 PM PDT 24
Peak memory 218404 kb
Host smart-60859a9e-2c05-4f11-a7b3-f905995cbca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551784959 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.551784959
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3893829130
Short name T386
Test name
Test status
Simulation time 257084668 ps
CPU time 9.61 seconds
Started Jul 26 04:58:47 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 210720 kb
Host smart-ac032826-fcaa-4756-8933-66abaa53d89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893829130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3893829130
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2499945498
Short name T431
Test name
Test status
Simulation time 10088535891 ps
CPU time 44.48 seconds
Started Jul 26 04:58:43 PM PDT 24
Finished Jul 26 04:59:28 PM PDT 24
Peak memory 211776 kb
Host smart-4698b457-dff6-4c7e-8791-845b3db30182
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499945498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2499945498
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3365816000
Short name T459
Test name
Test status
Simulation time 258528121 ps
CPU time 9.67 seconds
Started Jul 26 04:58:46 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 211044 kb
Host smart-d1f652e8-5e31-40c2-8e9d-f3b33af4350b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365816000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3365816000
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4077898938
Short name T439
Test name
Test status
Simulation time 168270922 ps
CPU time 11.35 seconds
Started Jul 26 04:58:49 PM PDT 24
Finished Jul 26 04:59:00 PM PDT 24
Peak memory 217400 kb
Host smart-8b5f508e-4a45-4eb7-8aca-a9d3fd4692cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077898938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4077898938
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1650942312
Short name T73
Test name
Test status
Simulation time 687660970 ps
CPU time 7.87 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 210396 kb
Host smart-8a8a074e-ae47-47ae-8049-d4f08cb4c2b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650942312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1650942312
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2609775661
Short name T391
Test name
Test status
Simulation time 4957166173 ps
CPU time 10.14 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 211196 kb
Host smart-77c6ba9d-9906-4aeb-983e-7b3a51b7e873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609775661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2609775661
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.361320170
Short name T464
Test name
Test status
Simulation time 707075904 ps
CPU time 15.3 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 211912 kb
Host smart-2bb8d537-5b10-4e26-ac85-fa52e722afee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361320170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.361320170
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2901358582
Short name T374
Test name
Test status
Simulation time 449357356 ps
CPU time 10.26 seconds
Started Jul 26 04:58:20 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 216320 kb
Host smart-360ffe95-a684-43f0-9b8b-b67d39d73f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901358582 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2901358582
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2634855738
Short name T69
Test name
Test status
Simulation time 340621301 ps
CPU time 8.28 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 210556 kb
Host smart-d3a36ea5-1cfe-4e95-8072-f3b156675dde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634855738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2634855738
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1058042703
Short name T398
Test name
Test status
Simulation time 755971189 ps
CPU time 8.07 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 04:58:32 PM PDT 24
Peak memory 210432 kb
Host smart-8fee94a6-d259-4f1c-bb9f-d20c66425ea4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058042703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1058042703
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1020321873
Short name T416
Test name
Test status
Simulation time 972215872 ps
CPU time 8.05 seconds
Started Jul 26 04:58:20 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 210308 kb
Host smart-b57f3648-c7d2-4f32-a87b-5194252eab23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020321873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1020321873
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2623397808
Short name T83
Test name
Test status
Simulation time 2853803547 ps
CPU time 37.43 seconds
Started Jul 26 04:58:31 PM PDT 24
Finished Jul 26 04:59:09 PM PDT 24
Peak memory 213824 kb
Host smart-92f5a197-cb3d-4b51-9b77-34498000945c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623397808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2623397808
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2627493248
Short name T422
Test name
Test status
Simulation time 497668800 ps
CPU time 9.84 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 211372 kb
Host smart-589c7892-4f01-43ad-9ec2-2835d1af7636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627493248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2627493248
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2095688583
Short name T429
Test name
Test status
Simulation time 261413816 ps
CPU time 12.4 seconds
Started Jul 26 04:58:23 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 217412 kb
Host smart-3cfd0268-ba1a-4cfb-b4cb-f1ec57283e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095688583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2095688583
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3187534873
Short name T395
Test name
Test status
Simulation time 688035940 ps
CPU time 8.05 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 210876 kb
Host smart-ab2618cf-dff6-409a-9ed9-e2e4da836194
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187534873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3187534873
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2684691493
Short name T58
Test name
Test status
Simulation time 1239398789 ps
CPU time 9.68 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 210480 kb
Host smart-4b43eafd-6563-43aa-8a31-c32ec46dd76c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684691493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2684691493
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3325388795
Short name T379
Test name
Test status
Simulation time 354677158 ps
CPU time 11.49 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:31 PM PDT 24
Peak memory 210400 kb
Host smart-aa22d481-8b19-44cd-9232-7bc189f85dec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325388795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3325388795
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3269235027
Short name T399
Test name
Test status
Simulation time 534061739 ps
CPU time 10.28 seconds
Started Jul 26 04:58:42 PM PDT 24
Finished Jul 26 04:58:52 PM PDT 24
Peak memory 217296 kb
Host smart-5de0e21a-f2b5-4e56-8ac7-9ed1efe7c827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269235027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3269235027
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1162307692
Short name T448
Test name
Test status
Simulation time 665231606 ps
CPU time 8.23 seconds
Started Jul 26 04:58:26 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 210380 kb
Host smart-38a68b7b-f8fc-4d22-a45a-1366dd02ba96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162307692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1162307692
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1655200186
Short name T400
Test name
Test status
Simulation time 172634149 ps
CPU time 7.95 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 210372 kb
Host smart-0cc3feb6-283e-4fe5-b6dd-a25b768e3757
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655200186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1655200186
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.282020159
Short name T423
Test name
Test status
Simulation time 9822889879 ps
CPU time 13.98 seconds
Started Jul 26 04:58:41 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 210384 kb
Host smart-b10f052e-3a85-42e9-80e9-b3081c0795da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282020159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
282020159
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2598427834
Short name T409
Test name
Test status
Simulation time 1589651686 ps
CPU time 66.08 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:59:28 PM PDT 24
Peak memory 219028 kb
Host smart-6047b149-7d23-48d7-9e0a-0d30fbd472d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598427834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2598427834
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3915699995
Short name T420
Test name
Test status
Simulation time 347802267 ps
CPU time 13.58 seconds
Started Jul 26 04:58:34 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 212488 kb
Host smart-77693a97-60a8-4139-b6d9-b8cd82c2262a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915699995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3915699995
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2314930096
Short name T443
Test name
Test status
Simulation time 950782516 ps
CPU time 13.14 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 218588 kb
Host smart-221e8cd5-d01f-4c51-8198-aef236aebfeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314930096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2314930096
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3993572287
Short name T418
Test name
Test status
Simulation time 1447187216 ps
CPU time 149.6 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 05:01:06 PM PDT 24
Peak memory 213808 kb
Host smart-18d1db7c-4dc6-4558-9c7d-0642c1089e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993572287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3993572287
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3605955494
Short name T436
Test name
Test status
Simulation time 1031990702 ps
CPU time 9.85 seconds
Started Jul 26 04:58:27 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 210512 kb
Host smart-4adcaf53-9bbe-4aa0-97c7-3961a6e4ab2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605955494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3605955494
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.223626923
Short name T413
Test name
Test status
Simulation time 718057530 ps
CPU time 8.18 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 210472 kb
Host smart-0aef8139-d1f7-4ab0-ba31-1684a2dff851
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223626923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.223626923
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2246335115
Short name T98
Test name
Test status
Simulation time 289943778 ps
CPU time 15.43 seconds
Started Jul 26 04:58:28 PM PDT 24
Finished Jul 26 04:58:44 PM PDT 24
Peak memory 211776 kb
Host smart-7eedb0fa-272a-4e7c-a4ae-e66830303682
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246335115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2246335115
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.721467349
Short name T411
Test name
Test status
Simulation time 1046065735 ps
CPU time 14.87 seconds
Started Jul 26 04:58:33 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 216280 kb
Host smart-f309d1d9-d63b-437b-afd6-fdac2b9192e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721467349 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.721467349
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4210604532
Short name T81
Test name
Test status
Simulation time 3299999764 ps
CPU time 8.14 seconds
Started Jul 26 04:58:25 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 210984 kb
Host smart-60234807-5d7f-401c-9b0a-0c40447759b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210604532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4210604532
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.225033430
Short name T446
Test name
Test status
Simulation time 1034033178 ps
CPU time 9.53 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:45 PM PDT 24
Peak memory 210284 kb
Host smart-828a2887-030c-4265-a3fa-05b014a31ed6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225033430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.225033430
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1133974858
Short name T376
Test name
Test status
Simulation time 721119504 ps
CPU time 7.83 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 210368 kb
Host smart-23ba1db2-8381-46ea-8d14-fa9c45d0eac7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133974858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1133974858
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.287374559
Short name T97
Test name
Test status
Simulation time 31287890729 ps
CPU time 94.3 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:59:56 PM PDT 24
Peak memory 215008 kb
Host smart-7c492e0b-ec4a-48c5-bcd0-8dc59761ecf5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287374559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.287374559
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2661506823
Short name T415
Test name
Test status
Simulation time 508649282 ps
CPU time 11.95 seconds
Started Jul 26 04:58:37 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 212560 kb
Host smart-948df6bd-f165-4198-ae7b-afd244ad5696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661506823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2661506823
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2625930321
Short name T405
Test name
Test status
Simulation time 486701777 ps
CPU time 12.48 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 217276 kb
Host smart-a96c319a-ca15-4cac-beeb-66223975b613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625930321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2625930321
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3129326078
Short name T113
Test name
Test status
Simulation time 789587744 ps
CPU time 156.24 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 05:00:56 PM PDT 24
Peak memory 214052 kb
Host smart-9184fa72-902b-4f3c-8432-00c4994d9375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129326078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3129326078
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3429156552
Short name T396
Test name
Test status
Simulation time 1857210860 ps
CPU time 11.15 seconds
Started Jul 26 04:58:31 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 217472 kb
Host smart-b7615cbe-fb1e-4285-a8cb-010d4ab2c061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429156552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3429156552
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.154201341
Short name T432
Test name
Test status
Simulation time 611949450 ps
CPU time 8.1 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 210392 kb
Host smart-eeffd250-c423-4af6-b34c-8ecd8d00a45b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154201341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.154201341
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1837752298
Short name T74
Test name
Test status
Simulation time 4122965844 ps
CPU time 56.28 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:59:18 PM PDT 24
Peak memory 219092 kb
Host smart-0c79cb33-f6d5-4542-9fe0-2a4de73ed1af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837752298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1837752298
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.133283417
Short name T96
Test name
Test status
Simulation time 167773534 ps
CPU time 8.23 seconds
Started Jul 26 04:58:29 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 210952 kb
Host smart-f826b940-3359-4738-91ca-e17eda9066eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133283417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.133283417
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3782597914
Short name T373
Test name
Test status
Simulation time 2256763178 ps
CPU time 14.34 seconds
Started Jul 26 04:58:42 PM PDT 24
Finished Jul 26 04:58:56 PM PDT 24
Peak memory 217512 kb
Host smart-79af1bbc-ec69-48a3-9ccb-134c44dabd30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782597914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3782597914
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.844647439
Short name T456
Test name
Test status
Simulation time 316831124 ps
CPU time 152.61 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 05:01:03 PM PDT 24
Peak memory 213900 kb
Host smart-92cf3430-2f15-46f1-bf9c-b38f91c7c359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844647439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.844647439
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3768514528
Short name T375
Test name
Test status
Simulation time 472619917 ps
CPU time 10.72 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:58:32 PM PDT 24
Peak memory 216688 kb
Host smart-97496db2-4d43-463c-9374-e276c44a45ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768514528 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3768514528
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.72997967
Short name T406
Test name
Test status
Simulation time 504794103 ps
CPU time 9.52 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:54 PM PDT 24
Peak memory 210776 kb
Host smart-022de386-11ec-4476-abfb-5d5cbd28d9e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72997967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.72997967
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3498996024
Short name T88
Test name
Test status
Simulation time 7876295966 ps
CPU time 55.81 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:59:35 PM PDT 24
Peak memory 214160 kb
Host smart-f9b95bde-c5ae-4522-bcd6-dbd984134411
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498996024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3498996024
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4121329719
Short name T95
Test name
Test status
Simulation time 2247835071 ps
CPU time 9.86 seconds
Started Jul 26 04:58:23 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 211376 kb
Host smart-bab056ad-b222-4236-9990-9b3cfbb76b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121329719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4121329719
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1907865253
Short name T421
Test name
Test status
Simulation time 258889743 ps
CPU time 14.98 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:58:55 PM PDT 24
Peak memory 217580 kb
Host smart-ace20135-5059-4811-8582-077d72df3ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907865253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1907865253
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3587332130
Short name T103
Test name
Test status
Simulation time 786092399 ps
CPU time 154.36 seconds
Started Jul 26 04:58:43 PM PDT 24
Finished Jul 26 05:01:18 PM PDT 24
Peak memory 213848 kb
Host smart-2ad24d48-986f-4ff8-bbdf-46910ccf3686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587332130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3587332130
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3143875341
Short name T392
Test name
Test status
Simulation time 1076079729 ps
CPU time 11.14 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 217368 kb
Host smart-e684483a-5727-4d02-bd58-7a63c98db33f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143875341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3143875341
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1848739677
Short name T389
Test name
Test status
Simulation time 169027513 ps
CPU time 8.26 seconds
Started Jul 26 04:58:28 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 210516 kb
Host smart-fdcd321e-3675-4765-ab52-8f053b309720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848739677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1848739677
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3234213929
Short name T93
Test name
Test status
Simulation time 1032260203 ps
CPU time 9.72 seconds
Started Jul 26 04:58:39 PM PDT 24
Finished Jul 26 04:58:48 PM PDT 24
Peak memory 211444 kb
Host smart-602fe098-4c3b-4afc-ba75-099904dbe6ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234213929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3234213929
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2055831603
Short name T434
Test name
Test status
Simulation time 259096198 ps
CPU time 13.21 seconds
Started Jul 26 04:58:30 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 218688 kb
Host smart-58ce7365-7688-42e5-b7db-066bbbee6293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055831603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2055831603
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.799117894
Short name T107
Test name
Test status
Simulation time 1470931654 ps
CPU time 153.23 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 05:00:56 PM PDT 24
Peak memory 214040 kb
Host smart-33981c3a-edee-4f85-8649-d4eed508bd50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799117894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.799117894
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1296903730
Short name T404
Test name
Test status
Simulation time 3219529106 ps
CPU time 9.86 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:54 PM PDT 24
Peak memory 216108 kb
Host smart-bdc6f495-382b-4905-986f-554181e31b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296903730 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1296903730
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3965051000
Short name T65
Test name
Test status
Simulation time 252491681 ps
CPU time 9.31 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:53 PM PDT 24
Peak memory 210680 kb
Host smart-81e0ce6b-415e-4d7b-bc4c-ec5c05ced49d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965051000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3965051000
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.634554439
Short name T441
Test name
Test status
Simulation time 7261909579 ps
CPU time 42.26 seconds
Started Jul 26 04:58:38 PM PDT 24
Finished Jul 26 04:59:20 PM PDT 24
Peak memory 214844 kb
Host smart-b7a0c9da-8e74-4c17-bc95-27d7defc6441
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634554439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.634554439
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2155378908
Short name T90
Test name
Test status
Simulation time 176157382 ps
CPU time 8.2 seconds
Started Jul 26 04:58:34 PM PDT 24
Finished Jul 26 04:58:42 PM PDT 24
Peak memory 211188 kb
Host smart-cde82899-5c8c-4751-bbce-40794af29303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155378908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2155378908
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2025978972
Short name T372
Test name
Test status
Simulation time 690164895 ps
CPU time 12.64 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:57 PM PDT 24
Peak memory 218384 kb
Host smart-f902c0f2-720f-4f47-8a42-12780a8ca881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025978972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2025978972
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1478852117
Short name T104
Test name
Test status
Simulation time 814525092 ps
CPU time 79.26 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:59:55 PM PDT 24
Peak memory 213652 kb
Host smart-604e7498-45f5-4771-bb80-f62cbc1672d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478852117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1478852117
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2798613145
Short name T385
Test name
Test status
Simulation time 265832717 ps
CPU time 9.65 seconds
Started Jul 26 04:58:35 PM PDT 24
Finished Jul 26 04:58:46 PM PDT 24
Peak memory 214000 kb
Host smart-79391fb4-c3f6-49ce-84ea-55081a4c5a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798613145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2798613145
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3829915244
Short name T414
Test name
Test status
Simulation time 3081575821 ps
CPU time 9.61 seconds
Started Jul 26 04:58:44 PM PDT 24
Finished Jul 26 04:58:54 PM PDT 24
Peak memory 210280 kb
Host smart-8f63e985-e026-401f-8e5f-0d7652c63171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829915244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3829915244
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3330168056
Short name T450
Test name
Test status
Simulation time 6083260652 ps
CPU time 66.13 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 04:59:43 PM PDT 24
Peak memory 218740 kb
Host smart-406b716d-c572-425d-92f7-97ed108efe50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330168056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3330168056
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2003567062
Short name T394
Test name
Test status
Simulation time 257466241 ps
CPU time 9.82 seconds
Started Jul 26 04:58:32 PM PDT 24
Finished Jul 26 04:58:42 PM PDT 24
Peak memory 211028 kb
Host smart-bfc078bc-099b-48f0-87f9-c381018cec2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003567062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2003567062
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2828410228
Short name T377
Test name
Test status
Simulation time 691469522 ps
CPU time 13.24 seconds
Started Jul 26 04:58:26 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 217644 kb
Host smart-8cbdb994-d306-4423-bdf3-82d8dfe32d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828410228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2828410228
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2284076606
Short name T106
Test name
Test status
Simulation time 429928417 ps
CPU time 152.78 seconds
Started Jul 26 04:58:57 PM PDT 24
Finished Jul 26 05:01:30 PM PDT 24
Peak memory 214032 kb
Host smart-650e49fb-e819-4d8d-91fe-077a652a246c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284076606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2284076606
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.25631199
Short name T36
Test name
Test status
Simulation time 19334054196 ps
CPU time 311.11 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 05:02:34 PM PDT 24
Peak memory 229092 kb
Host smart-34d3f966-98f3-4873-901d-43401d73bd60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25631199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_cor
rupt_sig_fatal_chk.25631199
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.234464669
Short name T123
Test name
Test status
Simulation time 503557038 ps
CPU time 23.01 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 219808 kb
Host smart-3b8c5890-51cd-4e67-b135-36bacac32581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234464669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.234464669
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2239301645
Short name T321
Test name
Test status
Simulation time 270361854 ps
CPU time 12.25 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 04:57:54 PM PDT 24
Peak memory 219736 kb
Host smart-9aeb9c55-2ca8-4d50-af8b-6af3ca7c714d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239301645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2239301645
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1350637889
Short name T133
Test name
Test status
Simulation time 2045210839 ps
CPU time 24.67 seconds
Started Jul 26 04:57:27 PM PDT 24
Finished Jul 26 04:57:52 PM PDT 24
Peak memory 218604 kb
Host smart-b0d3f25c-6b0d-4408-a547-32dd42020a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350637889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1350637889
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2787456671
Short name T204
Test name
Test status
Simulation time 1075593251 ps
CPU time 31.13 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 04:58:05 PM PDT 24
Peak memory 218444 kb
Host smart-18ecae72-ee80-4070-9715-d240e90b02cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787456671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2787456671
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1506342565
Short name T140
Test name
Test status
Simulation time 260344353 ps
CPU time 10.04 seconds
Started Jul 26 04:57:32 PM PDT 24
Finished Jul 26 04:57:42 PM PDT 24
Peak memory 218696 kb
Host smart-5fd9ef75-ec8f-47cd-84d3-440c47378ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506342565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1506342565
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.42313207
Short name T33
Test name
Test status
Simulation time 7551169784 ps
CPU time 199.41 seconds
Started Jul 26 04:57:40 PM PDT 24
Finished Jul 26 05:01:00 PM PDT 24
Peak memory 237164 kb
Host smart-65127df1-cee3-4c72-a681-b70566024ca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42313207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.42313207
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.494739781
Short name T333
Test name
Test status
Simulation time 513452920 ps
CPU time 22.5 seconds
Started Jul 26 04:57:24 PM PDT 24
Finished Jul 26 04:57:46 PM PDT 24
Peak memory 219748 kb
Host smart-c56d0d70-006e-4c8a-ad96-7960256d0af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494739781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.494739781
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.812499995
Short name T149
Test name
Test status
Simulation time 698992016 ps
CPU time 10.08 seconds
Started Jul 26 04:57:22 PM PDT 24
Finished Jul 26 04:57:32 PM PDT 24
Peak memory 219780 kb
Host smart-60e36571-5524-4c5d-8448-5feb86c9f41f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812499995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.812499995
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2093620465
Short name T27
Test name
Test status
Simulation time 5975674265 ps
CPU time 119.2 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 04:59:41 PM PDT 24
Peak memory 234100 kb
Host smart-cb0ef722-430f-475e-80a2-70726ee90c95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093620465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2093620465
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2917548373
Short name T244
Test name
Test status
Simulation time 360226170 ps
CPU time 20.94 seconds
Started Jul 26 04:57:23 PM PDT 24
Finished Jul 26 04:57:44 PM PDT 24
Peak memory 219232 kb
Host smart-5579298c-e1cd-407d-bc51-d3c5ba38d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917548373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2917548373
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2019225539
Short name T354
Test name
Test status
Simulation time 1122789078 ps
CPU time 23.54 seconds
Started Jul 26 04:57:21 PM PDT 24
Finished Jul 26 04:57:44 PM PDT 24
Peak memory 219384 kb
Host smart-3360df44-0868-4d32-b26c-216340cd1173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019225539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2019225539
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3480314378
Short name T221
Test name
Test status
Simulation time 249905842 ps
CPU time 10.1 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:57:56 PM PDT 24
Peak memory 218796 kb
Host smart-fa4490c6-7ff8-44d5-926b-ceab63da3d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480314378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3480314378
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.780098571
Short name T22
Test name
Test status
Simulation time 2336547140 ps
CPU time 167.92 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 05:00:36 PM PDT 24
Peak memory 241644 kb
Host smart-09e3d50a-641e-4c74-9c3e-c467dd9d280a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780098571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.780098571
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3027371739
Short name T217
Test name
Test status
Simulation time 1012731699 ps
CPU time 22.13 seconds
Started Jul 26 04:57:45 PM PDT 24
Finished Jul 26 04:58:07 PM PDT 24
Peak memory 219744 kb
Host smart-44a6922f-1cbe-4c3a-92c8-f99a0f6c3831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027371739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3027371739
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3760377620
Short name T227
Test name
Test status
Simulation time 177075093 ps
CPU time 10.07 seconds
Started Jul 26 04:57:43 PM PDT 24
Finished Jul 26 04:57:53 PM PDT 24
Peak memory 219684 kb
Host smart-7e4f78fe-7d16-424c-bdcf-55c3e4185f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760377620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3760377620
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.493487160
Short name T289
Test name
Test status
Simulation time 531911861 ps
CPU time 24.24 seconds
Started Jul 26 04:57:44 PM PDT 24
Finished Jul 26 04:58:08 PM PDT 24
Peak memory 219160 kb
Host smart-f7a88282-d27e-4976-a1ea-fefbf2271c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493487160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.493487160
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.735941970
Short name T180
Test name
Test status
Simulation time 705910675 ps
CPU time 41.57 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 220080 kb
Host smart-fd6586f8-188f-4a3d-8882-10bed0a22808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735941970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.735941970
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.991060950
Short name T327
Test name
Test status
Simulation time 504287777 ps
CPU time 10.09 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:46 PM PDT 24
Peak memory 218824 kb
Host smart-7af4c892-e075-4fbb-ba77-29717076f757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991060950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.991060950
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2503010075
Short name T223
Test name
Test status
Simulation time 1325444615 ps
CPU time 19.42 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 04:57:53 PM PDT 24
Peak memory 219780 kb
Host smart-293718a8-ca2f-4746-96e3-428ae08f1119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503010075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2503010075
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2516374574
Short name T196
Test name
Test status
Simulation time 457977416 ps
CPU time 10.73 seconds
Started Jul 26 04:58:04 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 219700 kb
Host smart-9376f213-5baf-4ca6-89be-e1e11851a227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516374574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2516374574
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.835087555
Short name T261
Test name
Test status
Simulation time 1442154063 ps
CPU time 20.83 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:57 PM PDT 24
Peak memory 219168 kb
Host smart-1cfeb73b-ffa1-4434-a771-b70c9d27e4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835087555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.835087555
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.956361247
Short name T260
Test name
Test status
Simulation time 743208133 ps
CPU time 23.6 seconds
Started Jul 26 04:57:39 PM PDT 24
Finished Jul 26 04:58:02 PM PDT 24
Peak memory 219264 kb
Host smart-748de56d-8a38-4898-86b2-eba041380a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956361247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.956361247
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2229648339
Short name T274
Test name
Test status
Simulation time 69005078683 ps
CPU time 712.61 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 05:09:58 PM PDT 24
Peak memory 234096 kb
Host smart-534b47f2-0e17-49a8-b66a-df715c8d0771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229648339 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2229648339
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3430755027
Short name T294
Test name
Test status
Simulation time 413613882 ps
CPU time 10.27 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:27 PM PDT 24
Peak memory 218872 kb
Host smart-0e347329-01a0-4935-a950-6cf854275287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430755027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3430755027
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1593773892
Short name T306
Test name
Test status
Simulation time 8315724680 ps
CPU time 279.14 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 05:02:47 PM PDT 24
Peak memory 239260 kb
Host smart-a5691321-be75-45c0-8703-ed7f3079c3e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593773892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1593773892
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1234376215
Short name T20
Test name
Test status
Simulation time 3801067277 ps
CPU time 22.88 seconds
Started Jul 26 04:57:57 PM PDT 24
Finished Jul 26 04:58:20 PM PDT 24
Peak memory 219824 kb
Host smart-5627fa7a-70ee-47a5-ac60-feafddfee22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234376215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1234376215
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2700295244
Short name T243
Test name
Test status
Simulation time 1068767247 ps
CPU time 12.3 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:58:03 PM PDT 24
Peak memory 219768 kb
Host smart-435cbe18-6261-4200-94e5-5a57e94e7414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700295244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2700295244
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3801218788
Short name T281
Test name
Test status
Simulation time 2080351887 ps
CPU time 38.12 seconds
Started Jul 26 04:57:45 PM PDT 24
Finished Jul 26 04:58:23 PM PDT 24
Peak memory 219272 kb
Host smart-f2b8901c-70a0-431f-9a06-8a1a079ac8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801218788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3801218788
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1951520899
Short name T320
Test name
Test status
Simulation time 16237841566 ps
CPU time 7910.61 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 07:09:57 PM PDT 24
Peak memory 230684 kb
Host smart-733e47a2-f16b-4df7-9d7b-f257c3a7952c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951520899 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1951520899
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2678405301
Short name T312
Test name
Test status
Simulation time 986954885 ps
CPU time 14.76 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:17 PM PDT 24
Peak memory 218816 kb
Host smart-bcfdbcfe-a4c2-452d-8066-aaf5c6b2a0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678405301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2678405301
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3340897291
Short name T189
Test name
Test status
Simulation time 21464093010 ps
CPU time 326.72 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 05:03:42 PM PDT 24
Peak memory 236332 kb
Host smart-697aacd6-8849-41be-89a4-e33da8a99682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340897291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3340897291
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2299267342
Short name T231
Test name
Test status
Simulation time 523873039 ps
CPU time 22.87 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 219832 kb
Host smart-0ab51224-ca1b-4631-97ec-9777cc12ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299267342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2299267342
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.541109370
Short name T129
Test name
Test status
Simulation time 304861681 ps
CPU time 12 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:58:04 PM PDT 24
Peak memory 219748 kb
Host smart-f9e7aa35-98f8-429a-bf5c-f38e71c76384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541109370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.541109370
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2756246068
Short name T309
Test name
Test status
Simulation time 512972305 ps
CPU time 23.02 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 218544 kb
Host smart-d45f0fc8-71c4-4223-8a6a-9083b59b30c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756246068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2756246068
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1181841645
Short name T233
Test name
Test status
Simulation time 13040471267 ps
CPU time 49.37 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 220136 kb
Host smart-64f48d48-a993-4e6f-a86b-e47416f268af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181841645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1181841645
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.757302211
Short name T139
Test name
Test status
Simulation time 1031625623 ps
CPU time 9.96 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:10 PM PDT 24
Peak memory 218796 kb
Host smart-f9f98fa7-cb95-48fb-b06c-cdabf70a2591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757302211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.757302211
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.225808650
Short name T284
Test name
Test status
Simulation time 9269339995 ps
CPU time 162.88 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 05:00:45 PM PDT 24
Peak memory 219392 kb
Host smart-c5450a74-31e5-4889-944e-cf4cc6c43dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225808650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.225808650
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2398843086
Short name T10
Test name
Test status
Simulation time 497749938 ps
CPU time 22.83 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 219724 kb
Host smart-4686b340-5b03-4e6d-a0b3-2ef2e18057cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398843086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2398843086
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2466934462
Short name T134
Test name
Test status
Simulation time 186562118 ps
CPU time 10.65 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 219684 kb
Host smart-886bd95b-d6e8-47a8-9f12-9a2e7d36e77e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466934462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2466934462
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.715437561
Short name T188
Test name
Test status
Simulation time 511112202 ps
CPU time 23.25 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:58:15 PM PDT 24
Peak memory 219344 kb
Host smart-c0298647-bfdd-4210-a270-d26cf19575de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715437561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.715437561
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3175603198
Short name T77
Test name
Test status
Simulation time 2345765344 ps
CPU time 47.81 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 219764 kb
Host smart-bf043882-2c77-4957-b7f6-60d001ac6232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175603198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3175603198
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.493907347
Short name T329
Test name
Test status
Simulation time 692397889 ps
CPU time 8.38 seconds
Started Jul 26 04:57:49 PM PDT 24
Finished Jul 26 04:57:58 PM PDT 24
Peak memory 218724 kb
Host smart-c330ec6d-0ff8-4b0d-97b2-298ab0f8b76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493907347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.493907347
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3412788842
Short name T144
Test name
Test status
Simulation time 4869181009 ps
CPU time 255.14 seconds
Started Jul 26 04:57:49 PM PDT 24
Finished Jul 26 05:02:04 PM PDT 24
Peak memory 219928 kb
Host smart-6791fd33-ae34-45c3-856a-f6dd75d304e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412788842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3412788842
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.296988002
Short name T230
Test name
Test status
Simulation time 9913314704 ps
CPU time 23.32 seconds
Started Jul 26 04:57:53 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 219800 kb
Host smart-486b5b03-a9d3-4e78-955e-495df324c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296988002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.296988002
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1397471473
Short name T356
Test name
Test status
Simulation time 2164786524 ps
CPU time 10.4 seconds
Started Jul 26 04:58:03 PM PDT 24
Finished Jul 26 04:58:13 PM PDT 24
Peak memory 219744 kb
Host smart-38b0c805-761d-41da-97d3-49764b6abde4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397471473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1397471473
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.439388425
Short name T257
Test name
Test status
Simulation time 1378506350 ps
CPU time 19.66 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:08 PM PDT 24
Peak memory 219240 kb
Host smart-08fe97f6-da08-45fb-89fe-b9c083513194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439388425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.439388425
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2667144633
Short name T275
Test name
Test status
Simulation time 1066908898 ps
CPU time 54.78 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:59:00 PM PDT 24
Peak memory 220288 kb
Host smart-349654ce-c773-46f6-a77c-838be6822728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667144633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2667144633
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.277860294
Short name T351
Test name
Test status
Simulation time 5426367631 ps
CPU time 15.11 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219136 kb
Host smart-fedf1439-79bb-49ae-b7c7-6b5b20bda44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277860294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.277860294
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1278166156
Short name T43
Test name
Test status
Simulation time 6964892530 ps
CPU time 254.76 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 05:02:03 PM PDT 24
Peak memory 240692 kb
Host smart-86492ef1-7958-4628-a39c-877234257194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278166156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1278166156
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2579646460
Short name T126
Test name
Test status
Simulation time 4953834139 ps
CPU time 22.96 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:15 PM PDT 24
Peak memory 219788 kb
Host smart-b991df07-2059-478e-acdb-a1c1ccd6b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579646460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2579646460
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1463658933
Short name T268
Test name
Test status
Simulation time 186749497 ps
CPU time 10.55 seconds
Started Jul 26 04:58:01 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219780 kb
Host smart-89d26a8b-8ca8-4818-84ef-3df4d93f71c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463658933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1463658933
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2789064777
Short name T120
Test name
Test status
Simulation time 533150110 ps
CPU time 23.54 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 219088 kb
Host smart-4be1cee6-7ade-4c4f-8be6-7a297928d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789064777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2789064777
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2276366669
Short name T335
Test name
Test status
Simulation time 1108873561 ps
CPU time 31.35 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:20 PM PDT 24
Peak memory 219640 kb
Host smart-8a2f7a58-9072-448e-8a45-57bdaaf02288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276366669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2276366669
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3155776575
Short name T251
Test name
Test status
Simulation time 1374804191 ps
CPU time 8.33 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:57:58 PM PDT 24
Peak memory 218668 kb
Host smart-082caf1d-9d4c-4abc-b9a2-2c8102f8602f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155776575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3155776575
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.934332981
Short name T332
Test name
Test status
Simulation time 1805393630 ps
CPU time 114.45 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:59:45 PM PDT 24
Peak memory 219876 kb
Host smart-8d342d46-7341-47fa-9b5f-ec9d1ec69152
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934332981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.934332981
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2087444747
Short name T17
Test name
Test status
Simulation time 527777547 ps
CPU time 12.07 seconds
Started Jul 26 04:58:10 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 219700 kb
Host smart-5e546beb-f045-49cb-bfe4-ab573413cf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087444747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2087444747
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2858839433
Short name T255
Test name
Test status
Simulation time 345971759 ps
CPU time 20.01 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 219136 kb
Host smart-f426f489-94e6-43e1-904d-14852897dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858839433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2858839433
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.194360610
Short name T256
Test name
Test status
Simulation time 1444144903 ps
CPU time 24.24 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219372 kb
Host smart-8f3c6d3b-f37d-4963-9e49-757b651dc380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194360610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.194360610
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4090840852
Short name T317
Test name
Test status
Simulation time 953578982 ps
CPU time 9.96 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:00 PM PDT 24
Peak memory 218784 kb
Host smart-ef0e9337-9cef-4975-881b-edcc2441f3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090840852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4090840852
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.617077617
Short name T340
Test name
Test status
Simulation time 1376112055 ps
CPU time 19.55 seconds
Started Jul 26 04:58:13 PM PDT 24
Finished Jul 26 04:58:32 PM PDT 24
Peak memory 219784 kb
Host smart-8d7df6e7-9a1c-46e7-86e3-07a4caeaf5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617077617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.617077617
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1430729550
Short name T359
Test name
Test status
Simulation time 4148102412 ps
CPU time 16.68 seconds
Started Jul 26 04:57:47 PM PDT 24
Finished Jul 26 04:58:04 PM PDT 24
Peak memory 219524 kb
Host smart-36272724-c8f1-4a63-af9e-c547af5bd644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430729550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1430729550
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1700528879
Short name T219
Test name
Test status
Simulation time 352402048 ps
CPU time 20.57 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 219172 kb
Host smart-984c29bf-dfc7-467e-8397-e919433a9a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700528879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1700528879
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1593266752
Short name T240
Test name
Test status
Simulation time 553731657 ps
CPU time 31.46 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 219456 kb
Host smart-13b1489a-8175-450e-a763-4a09c10a3961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593266752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1593266752
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.208745862
Short name T158
Test name
Test status
Simulation time 997470238 ps
CPU time 10.02 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 218744 kb
Host smart-7210c642-83eb-4b97-8603-643cf97f2481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208745862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.208745862
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1315611515
Short name T353
Test name
Test status
Simulation time 11294785179 ps
CPU time 186.1 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 05:00:55 PM PDT 24
Peak memory 219956 kb
Host smart-06472958-a2b7-48ba-a57d-3991232d746d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315611515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1315611515
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1233996747
Short name T336
Test name
Test status
Simulation time 2208878725 ps
CPU time 18.98 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:07 PM PDT 24
Peak memory 219764 kb
Host smart-46d191d9-745c-4908-88e8-ac9df5eb819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233996747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1233996747
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1034571512
Short name T315
Test name
Test status
Simulation time 1025956283 ps
CPU time 12.02 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:02 PM PDT 24
Peak memory 219740 kb
Host smart-f5f16623-c7b1-4c78-aef7-8ec0f9605cfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034571512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1034571512
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3879966505
Short name T344
Test name
Test status
Simulation time 2046165716 ps
CPU time 23.62 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219156 kb
Host smart-87b2620a-c863-4491-9e78-63e6413f73ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879966505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3879966505
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1826881482
Short name T157
Test name
Test status
Simulation time 5712165132 ps
CPU time 56.97 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:46 PM PDT 24
Peak memory 221072 kb
Host smart-7c95929b-1137-4044-81c2-29e8fb97cca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826881482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1826881482
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1543849050
Short name T249
Test name
Test status
Simulation time 32459547458 ps
CPU time 9647.99 seconds
Started Jul 26 04:57:57 PM PDT 24
Finished Jul 26 07:38:46 PM PDT 24
Peak memory 234884 kb
Host smart-596117eb-ccca-4cf8-aad0-807522581e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543849050 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1543849050
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2930264289
Short name T203
Test name
Test status
Simulation time 250227966 ps
CPU time 10.4 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 218772 kb
Host smart-13f843b7-5560-43e0-bf09-2c8e9cdf1964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930264289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2930264289
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3013206079
Short name T325
Test name
Test status
Simulation time 11757603082 ps
CPU time 179.96 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 05:00:34 PM PDT 24
Peak memory 219876 kb
Host smart-fc0531de-1e93-4dd4-aee4-07d05936e74d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013206079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3013206079
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3808205016
Short name T207
Test name
Test status
Simulation time 517315288 ps
CPU time 23.36 seconds
Started Jul 26 04:57:32 PM PDT 24
Finished Jul 26 04:57:56 PM PDT 24
Peak memory 219780 kb
Host smart-cd5a5d62-4b31-43e3-9d6d-ebd32b30fa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808205016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3808205016
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2633309689
Short name T304
Test name
Test status
Simulation time 263791996 ps
CPU time 12.58 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:03 PM PDT 24
Peak memory 219744 kb
Host smart-f14de3ce-81cd-461c-a566-ec55b85783bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633309689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2633309689
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2761431944
Short name T28
Test name
Test status
Simulation time 365014549 ps
CPU time 227.17 seconds
Started Jul 26 04:57:44 PM PDT 24
Finished Jul 26 05:01:31 PM PDT 24
Peak memory 235136 kb
Host smart-4426b6a5-03fc-41ec-a7ce-4caa89980106
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761431944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2761431944
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3373726762
Short name T122
Test name
Test status
Simulation time 2265038551 ps
CPU time 20.37 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:58:06 PM PDT 24
Peak memory 218904 kb
Host smart-1205d2d3-6c10-4011-9a84-808428263c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373726762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3373726762
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3203166469
Short name T220
Test name
Test status
Simulation time 6150072396 ps
CPU time 56.54 seconds
Started Jul 26 04:57:30 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 220792 kb
Host smart-f4a46ab2-7100-4cb3-8ae1-a053fde9323a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203166469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3203166469
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.994560199
Short name T348
Test name
Test status
Simulation time 1454195405 ps
CPU time 9.91 seconds
Started Jul 26 04:58:10 PM PDT 24
Finished Jul 26 04:58:20 PM PDT 24
Peak memory 218828 kb
Host smart-596b6de3-7f9a-4d20-8162-dfd662077186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994560199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.994560199
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1993622427
Short name T35
Test name
Test status
Simulation time 4331252065 ps
CPU time 222.79 seconds
Started Jul 26 04:57:45 PM PDT 24
Finished Jul 26 05:01:28 PM PDT 24
Peak memory 234204 kb
Host smart-b236f6f3-095d-4aed-ab57-a7d34a378435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993622427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1993622427
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3503719357
Short name T3
Test name
Test status
Simulation time 529635931 ps
CPU time 22.69 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 219744 kb
Host smart-dbe2b43c-98c0-487a-bb32-8db5a270b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503719357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3503719357
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3631050432
Short name T279
Test name
Test status
Simulation time 510983637 ps
CPU time 11.59 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:00 PM PDT 24
Peak memory 219684 kb
Host smart-88657328-989e-4250-b08c-0ea0929975e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631050432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3631050432
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2920095106
Short name T245
Test name
Test status
Simulation time 2192092896 ps
CPU time 22.87 seconds
Started Jul 26 04:57:49 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219256 kb
Host smart-e1373819-672f-464d-8bb9-5ce244f6f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920095106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2920095106
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2880835223
Short name T101
Test name
Test status
Simulation time 558258877 ps
CPU time 31.25 seconds
Started Jul 26 04:58:09 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 219468 kb
Host smart-52565da1-5195-4a53-a5eb-9dd9bc73179c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880835223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2880835223
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.395703047
Short name T4
Test name
Test status
Simulation time 167651175 ps
CPU time 8.29 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:00 PM PDT 24
Peak memory 218860 kb
Host smart-86125fde-0e59-43a3-8947-5d19734a6489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395703047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.395703047
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4091822652
Short name T345
Test name
Test status
Simulation time 19293165739 ps
CPU time 357.19 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 05:03:55 PM PDT 24
Peak memory 238568 kb
Host smart-6b7dd8f5-bb9e-4d2d-a607-da674164122a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091822652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4091822652
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3730417569
Short name T346
Test name
Test status
Simulation time 1031987735 ps
CPU time 22.21 seconds
Started Jul 26 04:58:04 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 219772 kb
Host smart-584febfa-4d85-4c7f-8a90-71dd30a37d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730417569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3730417569
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3733551941
Short name T358
Test name
Test status
Simulation time 4118772944 ps
CPU time 16.63 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 219416 kb
Host smart-4d39943e-3fa4-41e2-ae54-8478404f0855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733551941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3733551941
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1994759568
Short name T166
Test name
Test status
Simulation time 1562334203 ps
CPU time 19.95 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219188 kb
Host smart-58551555-a28f-4e3c-bbe8-07f4231b376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994759568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1994759568
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2477829775
Short name T266
Test name
Test status
Simulation time 1952937500 ps
CPU time 12.93 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:03 PM PDT 24
Peak memory 219164 kb
Host smart-edebdec1-26b1-4223-8efb-91a090a2e299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477829775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2477829775
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.934034334
Short name T350
Test name
Test status
Simulation time 51606601900 ps
CPU time 750.05 seconds
Started Jul 26 04:57:53 PM PDT 24
Finished Jul 26 05:10:23 PM PDT 24
Peak memory 233312 kb
Host smart-8eb5222c-d74f-49e0-8587-401057bde470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934034334 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.934034334
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3771400124
Short name T368
Test name
Test status
Simulation time 260249793 ps
CPU time 10.15 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 218888 kb
Host smart-3bb11868-37ff-4c74-b660-eb2e89af6550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771400124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3771400124
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3985254571
Short name T224
Test name
Test status
Simulation time 8683941658 ps
CPU time 484.69 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 05:05:56 PM PDT 24
Peak memory 228572 kb
Host smart-49014391-dcdd-42ac-ac65-3f02bc33a92f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985254571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3985254571
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3954116635
Short name T215
Test name
Test status
Simulation time 3294789813 ps
CPU time 19.24 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 219828 kb
Host smart-5e7f7670-3c3c-49b7-876e-30b5e80a881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954116635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3954116635
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1402467974
Short name T100
Test name
Test status
Simulation time 362010470 ps
CPU time 10.37 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:03 PM PDT 24
Peak memory 219800 kb
Host smart-29ac5ebe-c2b1-4f67-a48d-9191abd19bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402467974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1402467974
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2502079974
Short name T160
Test name
Test status
Simulation time 1373523925 ps
CPU time 20.07 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 218752 kb
Host smart-f0de5b8d-978b-4cce-ad64-6f3ed41258c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502079974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2502079974
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.773640368
Short name T283
Test name
Test status
Simulation time 2892663833 ps
CPU time 39.21 seconds
Started Jul 26 04:57:52 PM PDT 24
Finished Jul 26 04:58:31 PM PDT 24
Peak memory 219984 kb
Host smart-62ca459a-8d2e-4225-a7ca-6036904c082d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773640368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.773640368
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3176897727
Short name T226
Test name
Test status
Simulation time 259888306 ps
CPU time 9.8 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 218784 kb
Host smart-f28f557a-c23c-4b64-be14-b4dbf94de18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176897727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3176897727
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1986415408
Short name T236
Test name
Test status
Simulation time 496149583 ps
CPU time 21.78 seconds
Started Jul 26 04:57:50 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219688 kb
Host smart-634d1ec9-5a60-4e24-8b14-900f44e3d4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986415408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1986415408
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2839661987
Short name T318
Test name
Test status
Simulation time 521797067 ps
CPU time 11.74 seconds
Started Jul 26 04:57:53 PM PDT 24
Finished Jul 26 04:58:05 PM PDT 24
Peak memory 219684 kb
Host smart-7614304d-e0b0-4633-9057-2b034cba3a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839661987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2839661987
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1859407644
Short name T187
Test name
Test status
Simulation time 396415959 ps
CPU time 20 seconds
Started Jul 26 04:57:54 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 219076 kb
Host smart-7a7559f3-2ec3-42ff-99ed-a065ebe99237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859407644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1859407644
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2438071498
Short name T277
Test name
Test status
Simulation time 4938767474 ps
CPU time 51.77 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 221396 kb
Host smart-3676a6be-a264-4bd9-bc8a-f3e5d0fb3f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438071498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2438071498
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2120786043
Short name T135
Test name
Test status
Simulation time 1036170574 ps
CPU time 10.2 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:09 PM PDT 24
Peak memory 218768 kb
Host smart-5baa506d-42c9-45ee-8e23-bb84a133e4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120786043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2120786043
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1683626494
Short name T334
Test name
Test status
Simulation time 19578831447 ps
CPU time 266.33 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 05:02:26 PM PDT 24
Peak memory 224992 kb
Host smart-a423aa6c-b300-4fa2-beeb-dde8eb2fbdb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683626494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1683626494
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1776826853
Short name T150
Test name
Test status
Simulation time 259849113 ps
CPU time 12.55 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 219728 kb
Host smart-a27793bf-4ed7-4ad6-9eef-8770ae38d21e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776826853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1776826853
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2510133189
Short name T159
Test name
Test status
Simulation time 1351232038 ps
CPU time 20.24 seconds
Started Jul 26 04:58:09 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 218692 kb
Host smart-eb24d4e1-c5fb-4e94-befb-74c89031e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510133189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2510133189
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.610112621
Short name T118
Test name
Test status
Simulation time 557418847 ps
CPU time 34.02 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 219776 kb
Host smart-0e2c893d-59fb-429d-9373-26181ab064fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610112621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.610112621
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1324209498
Short name T323
Test name
Test status
Simulation time 1901092315 ps
CPU time 10.3 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 218740 kb
Host smart-366e4f92-2e98-43a3-a6cd-eba12d4ff3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324209498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1324209498
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.800127532
Short name T259
Test name
Test status
Simulation time 11666900246 ps
CPU time 127.67 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 05:00:16 PM PDT 24
Peak memory 238972 kb
Host smart-ebb08401-4138-4581-8aa6-77f0af23709f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800127532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.800127532
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.66906784
Short name T125
Test name
Test status
Simulation time 1035851870 ps
CPU time 22.56 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:31 PM PDT 24
Peak memory 219764 kb
Host smart-9e6d0ffa-6246-4002-8a47-d72ec75bd91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66906784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.66906784
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.543427563
Short name T316
Test name
Test status
Simulation time 270420316 ps
CPU time 12.11 seconds
Started Jul 26 04:58:13 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219764 kb
Host smart-5bfa07ee-8ed5-4e6f-948c-8cbbe0c081f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543427563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.543427563
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4005577261
Short name T119
Test name
Test status
Simulation time 2265762273 ps
CPU time 22.66 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 218744 kb
Host smart-e0292f83-280e-445f-907a-bb98f0ba5e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005577261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4005577261
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1953683893
Short name T78
Test name
Test status
Simulation time 866405732 ps
CPU time 15.11 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:17 PM PDT 24
Peak memory 218392 kb
Host smart-2695c69e-628b-4042-a371-98678056a280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953683893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1953683893
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.244793154
Short name T307
Test name
Test status
Simulation time 1079177129 ps
CPU time 9.94 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 218740 kb
Host smart-5b6107b6-27c0-4e1d-9282-098d5ac52e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244793154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.244793154
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.888359261
Short name T278
Test name
Test status
Simulation time 46774018772 ps
CPU time 154.54 seconds
Started Jul 26 04:58:01 PM PDT 24
Finished Jul 26 05:00:36 PM PDT 24
Peak memory 219972 kb
Host smart-17510fe2-036d-4258-8cda-cfa92e070a01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888359261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.888359261
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2830835895
Short name T247
Test name
Test status
Simulation time 952504043 ps
CPU time 22.98 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 219700 kb
Host smart-72e84b5a-5769-40ca-aa0d-ab65f418f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830835895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2830835895
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2991942307
Short name T303
Test name
Test status
Simulation time 1836976295 ps
CPU time 11.93 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:17 PM PDT 24
Peak memory 219708 kb
Host smart-92b84c8b-fcdb-40f5-b91f-d2e4937d8940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991942307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2991942307
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1472233331
Short name T308
Test name
Test status
Simulation time 526955203 ps
CPU time 22.72 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:21 PM PDT 24
Peak memory 219164 kb
Host smart-0f0a71dc-7501-4543-a7f1-2a64c40e0a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472233331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1472233331
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2601572515
Short name T211
Test name
Test status
Simulation time 1043006528 ps
CPU time 54.59 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:59:10 PM PDT 24
Peak memory 220368 kb
Host smart-33b8cc55-1f2c-4db2-b395-c441887a4eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601572515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2601572515
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3297711150
Short name T15
Test name
Test status
Simulation time 916569114953 ps
CPU time 3208.28 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 05:51:28 PM PDT 24
Peak memory 246092 kb
Host smart-81ac9edb-5b34-4ac9-9763-4d241b2f907b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297711150 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3297711150
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1204307901
Short name T64
Test name
Test status
Simulation time 346649808 ps
CPU time 8.13 seconds
Started Jul 26 04:58:09 PM PDT 24
Finished Jul 26 04:58:17 PM PDT 24
Peak memory 218832 kb
Host smart-7c8dc66b-25a1-4653-aec1-3c5e976f85a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204307901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1204307901
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.453531755
Short name T44
Test name
Test status
Simulation time 12172751056 ps
CPU time 248.36 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 05:02:25 PM PDT 24
Peak memory 237368 kb
Host smart-0bae4e13-4993-4c13-996f-874736b73afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453531755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.453531755
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.546257792
Short name T370
Test name
Test status
Simulation time 2055665324 ps
CPU time 22.59 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 219736 kb
Host smart-cea75dcb-c9f6-483e-a228-1361adf04d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546257792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.546257792
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1893587982
Short name T237
Test name
Test status
Simulation time 736307943 ps
CPU time 10.53 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 219820 kb
Host smart-f1e4dcf8-3ca7-45b4-a189-d9993cee7613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893587982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1893587982
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1315551303
Short name T297
Test name
Test status
Simulation time 1048325664 ps
CPU time 23.04 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 218756 kb
Host smart-999e30d7-dddb-43c5-b938-ee057c7fc0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315551303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1315551303
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2531356432
Short name T121
Test name
Test status
Simulation time 4039987491 ps
CPU time 13.09 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:12 PM PDT 24
Peak memory 218312 kb
Host smart-dc90e427-f4ed-435d-93d6-0f60e6b34ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531356432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2531356432
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3648337161
Short name T208
Test name
Test status
Simulation time 2056363853 ps
CPU time 14.65 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:15 PM PDT 24
Peak memory 218416 kb
Host smart-58e6f1c2-2a2d-4782-b81d-e440c27f2c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648337161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3648337161
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3155944984
Short name T206
Test name
Test status
Simulation time 10065437039 ps
CPU time 162.39 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 05:00:42 PM PDT 24
Peak memory 239172 kb
Host smart-64bff817-1f0f-4989-a25e-71f961a1fb6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155944984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3155944984
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1088128759
Short name T272
Test name
Test status
Simulation time 501952050 ps
CPU time 22.47 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:23 PM PDT 24
Peak memory 219800 kb
Host smart-daf091d3-8054-4d30-88df-fd3a947275a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088128759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1088128759
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2077223111
Short name T18
Test name
Test status
Simulation time 719500145 ps
CPU time 10.18 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219700 kb
Host smart-e9f1957f-8651-439e-8034-42c57b2d2a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077223111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2077223111
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3779129464
Short name T117
Test name
Test status
Simulation time 3789301901 ps
CPU time 20.06 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219620 kb
Host smart-40e3054a-9cab-45ca-a537-7ad1d5c847f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779129464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3779129464
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2040818978
Short name T241
Test name
Test status
Simulation time 575809097 ps
CPU time 19.99 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 218524 kb
Host smart-accd7556-e1f8-4a7b-97ff-ec36a3eaefb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040818978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2040818978
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1236824744
Short name T305
Test name
Test status
Simulation time 514624179 ps
CPU time 9.96 seconds
Started Jul 26 04:58:03 PM PDT 24
Finished Jul 26 04:58:13 PM PDT 24
Peak memory 218720 kb
Host smart-a8264409-66c9-48ad-9aed-5d1614b94530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236824744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1236824744
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2146383560
Short name T225
Test name
Test status
Simulation time 4708945493 ps
CPU time 276.61 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:02:43 PM PDT 24
Peak memory 238668 kb
Host smart-4a165eba-f351-4ce8-8109-b4518457cc5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146383560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2146383560
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2147870029
Short name T29
Test name
Test status
Simulation time 2060230200 ps
CPU time 22.92 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219768 kb
Host smart-644a9e67-91c8-4be4-884f-d23b2e8bdf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147870029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2147870029
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2449565683
Short name T8
Test name
Test status
Simulation time 438102344 ps
CPU time 12.23 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:20 PM PDT 24
Peak memory 219760 kb
Host smart-557b9bef-dfab-4822-be4e-2201f5ca1bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449565683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2449565683
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4184079351
Short name T42
Test name
Test status
Simulation time 360404318 ps
CPU time 20.18 seconds
Started Jul 26 04:58:03 PM PDT 24
Finished Jul 26 04:58:23 PM PDT 24
Peak memory 219236 kb
Host smart-9ec621a8-0987-4d3e-ae07-78cd7d6ebf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184079351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4184079351
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3206518320
Short name T326
Test name
Test status
Simulation time 1095980745 ps
CPU time 34.4 seconds
Started Jul 26 04:57:56 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 219200 kb
Host smart-a94dd9a0-3415-46a8-a2c4-6b226ebb3488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206518320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3206518320
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2865739837
Short name T155
Test name
Test status
Simulation time 853535794 ps
CPU time 10.16 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 218740 kb
Host smart-7d440f57-74f5-4194-a3b5-413a3f7bcefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865739837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2865739837
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3020845830
Short name T195
Test name
Test status
Simulation time 14486927045 ps
CPU time 368.63 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 05:03:44 PM PDT 24
Peak memory 219924 kb
Host smart-296103a3-b205-4f3c-b6b1-e4eee1ecb2ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020845830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3020845830
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1458252930
Short name T258
Test name
Test status
Simulation time 688782801 ps
CPU time 19.12 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 04:58:02 PM PDT 24
Peak memory 219632 kb
Host smart-91ddbe4b-b436-46dc-8054-eae562f85dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458252930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1458252930
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2084993342
Short name T299
Test name
Test status
Simulation time 374227919 ps
CPU time 10.41 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 04:57:52 PM PDT 24
Peak memory 219668 kb
Host smart-ab6bae0d-2b7d-45ae-b2b5-941fbc56820d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084993342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2084993342
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3256470430
Short name T26
Test name
Test status
Simulation time 691858376 ps
CPU time 117.16 seconds
Started Jul 26 04:57:47 PM PDT 24
Finished Jul 26 04:59:44 PM PDT 24
Peak memory 238752 kb
Host smart-6776360f-7e5a-4488-aff5-d637b93d2710
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256470430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3256470430
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3970123492
Short name T298
Test name
Test status
Simulation time 352424353 ps
CPU time 20.73 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 219204 kb
Host smart-a28f7759-db8a-4731-a599-18d9b01b7d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970123492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3970123492
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3142300109
Short name T185
Test name
Test status
Simulation time 2735407757 ps
CPU time 60.79 seconds
Started Jul 26 04:57:49 PM PDT 24
Finished Jul 26 04:58:50 PM PDT 24
Peak memory 219708 kb
Host smart-14c4242d-30b9-4527-843b-4000b6f46291
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142300109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3142300109
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1472673068
Short name T14
Test name
Test status
Simulation time 16401600312 ps
CPU time 4994.11 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 06:20:48 PM PDT 24
Peak memory 229208 kb
Host smart-eb43fd80-a841-4600-84ec-bb0486ef21f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472673068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1472673068
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.380270080
Short name T61
Test name
Test status
Simulation time 915858839 ps
CPU time 9.88 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 218800 kb
Host smart-c6a062e4-b241-4a2b-8d70-dbb627bd8dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380270080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.380270080
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1426653661
Short name T192
Test name
Test status
Simulation time 22238223441 ps
CPU time 317.19 seconds
Started Jul 26 04:58:36 PM PDT 24
Finished Jul 26 05:03:53 PM PDT 24
Peak memory 235332 kb
Host smart-15cbb8d2-cf62-4473-b44c-9d79921de6f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426653661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1426653661
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3586494850
Short name T360
Test name
Test status
Simulation time 517785647 ps
CPU time 22.74 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 219856 kb
Host smart-7a65a86c-96d1-463f-a860-f478163f9d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586494850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3586494850
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2803064719
Short name T347
Test name
Test status
Simulation time 1037324765 ps
CPU time 16.56 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:23 PM PDT 24
Peak memory 219092 kb
Host smart-415f718e-2930-45b7-a4f3-745217d30308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803064719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2803064719
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3829328048
Short name T285
Test name
Test status
Simulation time 8239496193 ps
CPU time 32.71 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 219204 kb
Host smart-fe738090-7e9f-4880-90d1-839e4db23ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829328048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3829328048
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3806890737
Short name T248
Test name
Test status
Simulation time 19712262826 ps
CPU time 81.92 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:59:36 PM PDT 24
Peak memory 228352 kb
Host smart-ab179c73-b8bc-459d-a1d0-9f1557fc7a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806890737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3806890737
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.700753237
Short name T310
Test name
Test status
Simulation time 167867530 ps
CPU time 8.53 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:07 PM PDT 24
Peak memory 218808 kb
Host smart-785d37f9-0a7a-4b9b-91f6-33b1a5a25692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700753237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.700753237
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.989739068
Short name T34
Test name
Test status
Simulation time 5680269531 ps
CPU time 200.79 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:01:27 PM PDT 24
Peak memory 226024 kb
Host smart-e579b035-bf29-4bd7-a8aa-cd074cbb04d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989739068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.989739068
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2753820439
Short name T191
Test name
Test status
Simulation time 1179946595 ps
CPU time 19.3 seconds
Started Jul 26 04:58:11 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 219748 kb
Host smart-4a1a78af-b015-4d0e-b983-bb256dc5bc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753820439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2753820439
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2184623676
Short name T132
Test name
Test status
Simulation time 693690580 ps
CPU time 10.39 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219812 kb
Host smart-281eac5f-07ad-439f-a277-18012aa1f2b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184623676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2184623676
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1015394860
Short name T176
Test name
Test status
Simulation time 2216512677 ps
CPU time 23.78 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:58:45 PM PDT 24
Peak memory 218956 kb
Host smart-08671ea7-0226-4462-b057-a96ed7ab5d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015394860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1015394860
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1427067630
Short name T229
Test name
Test status
Simulation time 6352476517 ps
CPU time 43.78 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:50 PM PDT 24
Peak memory 219896 kb
Host smart-bae2f01f-028d-43fd-9964-600d8089d117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427067630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1427067630
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2497852097
Short name T51
Test name
Test status
Simulation time 87787487666 ps
CPU time 3471.72 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 05:55:58 PM PDT 24
Peak memory 248448 kb
Host smart-590bc2df-709c-455d-a7fd-0d9fb5bcbce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497852097 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2497852097
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.931032656
Short name T186
Test name
Test status
Simulation time 251967953 ps
CPU time 10.24 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 218692 kb
Host smart-9bfd0dcc-cf16-44f3-9d7c-26f8420283da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931032656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.931032656
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4106356961
Short name T232
Test name
Test status
Simulation time 5050738386 ps
CPU time 263.28 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:02:29 PM PDT 24
Peak memory 238764 kb
Host smart-a07d05d0-c340-4b99-a555-168f3b7ead2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106356961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4106356961
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3750305942
Short name T124
Test name
Test status
Simulation time 3542769233 ps
CPU time 22.98 seconds
Started Jul 26 04:58:10 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 219784 kb
Host smart-db2bfcad-fa79-4d97-95d6-5b073e59b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750305942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3750305942
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3731463636
Short name T178
Test name
Test status
Simulation time 372096083 ps
CPU time 10.6 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219792 kb
Host smart-c566d7aa-2549-4ab0-8efc-359f814d619d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731463636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3731463636
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2551020653
Short name T313
Test name
Test status
Simulation time 1017729366 ps
CPU time 23.75 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 219244 kb
Host smart-c12f19b8-e1f2-44fb-a76f-db1916596123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551020653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2551020653
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1323706159
Short name T161
Test name
Test status
Simulation time 1015913429 ps
CPU time 24.04 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:24 PM PDT 24
Peak memory 219044 kb
Host smart-534e1b56-3eed-48c8-b554-ff7c41f4c289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323706159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1323706159
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3904905390
Short name T63
Test name
Test status
Simulation time 3518967758 ps
CPU time 14.79 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:24 PM PDT 24
Peak memory 218744 kb
Host smart-86cccfef-a982-4790-8754-f1108ebbcea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904905390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3904905390
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4250113336
Short name T198
Test name
Test status
Simulation time 51650678814 ps
CPU time 504.15 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 05:06:33 PM PDT 24
Peak memory 219476 kb
Host smart-af7fe95e-752c-42d2-b8bb-ee797af638e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250113336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4250113336
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3593615696
Short name T169
Test name
Test status
Simulation time 993687182 ps
CPU time 21.96 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:24 PM PDT 24
Peak memory 219756 kb
Host smart-2b09a263-a0b8-41c8-874c-9bbd20ade49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593615696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3593615696
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1238638811
Short name T254
Test name
Test status
Simulation time 5537340261 ps
CPU time 17.25 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219908 kb
Host smart-699e5904-9806-4cde-b9f5-3515dc18625c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238638811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1238638811
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1466719706
Short name T164
Test name
Test status
Simulation time 1891517158 ps
CPU time 23.94 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:39 PM PDT 24
Peak memory 219144 kb
Host smart-4529c74c-c792-48ea-8648-fa828ad4cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466719706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1466719706
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2477271487
Short name T147
Test name
Test status
Simulation time 951180860 ps
CPU time 9.88 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 218784 kb
Host smart-0b3ccd8e-1175-4e8e-bf0c-879e59bd87e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477271487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2477271487
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1868039626
Short name T290
Test name
Test status
Simulation time 12657030751 ps
CPU time 452.85 seconds
Started Jul 26 04:58:24 PM PDT 24
Finished Jul 26 05:05:57 PM PDT 24
Peak memory 239444 kb
Host smart-da0d7160-45eb-48b9-90f8-3ac56f7e52a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868039626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1868039626
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3566465900
Short name T175
Test name
Test status
Simulation time 3086812245 ps
CPU time 22.69 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 219768 kb
Host smart-f024dd3b-1b1b-4c92-adea-249fd8a1a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566465900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3566465900
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1152597571
Short name T222
Test name
Test status
Simulation time 1070563713 ps
CPU time 11.63 seconds
Started Jul 26 04:58:12 PM PDT 24
Finished Jul 26 04:58:24 PM PDT 24
Peak memory 219728 kb
Host smart-48f7fa07-2d6d-4583-8a85-2470483a1aa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152597571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1152597571
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.398291554
Short name T52
Test name
Test status
Simulation time 362008785 ps
CPU time 20.05 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 219048 kb
Host smart-8c03b270-28a7-401a-816a-2ab314f433bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398291554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.398291554
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4130482791
Short name T212
Test name
Test status
Simulation time 1600136527 ps
CPU time 49.78 seconds
Started Jul 26 04:58:31 PM PDT 24
Finished Jul 26 04:59:21 PM PDT 24
Peak memory 219736 kb
Host smart-f55f4086-6989-44a4-bde2-798ab0df2592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130482791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4130482791
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1265104495
Short name T130
Test name
Test status
Simulation time 331923419 ps
CPU time 8.44 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 218204 kb
Host smart-05d7109a-d6db-437e-95a6-a9f113e99d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265104495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1265104495
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.667324615
Short name T262
Test name
Test status
Simulation time 2672802053 ps
CPU time 216.71 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 05:01:35 PM PDT 24
Peak memory 242728 kb
Host smart-ffdb60a9-43e2-400c-8484-f390ddac8363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667324615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.667324615
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3680609732
Short name T156
Test name
Test status
Simulation time 346145382 ps
CPU time 19.55 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219748 kb
Host smart-efe72146-a173-4616-9f48-65c2242545aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680609732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3680609732
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2956323915
Short name T216
Test name
Test status
Simulation time 189214950 ps
CPU time 10.58 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:10 PM PDT 24
Peak memory 219740 kb
Host smart-e0d244e9-36c2-4604-94b2-fb16cc66a1bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956323915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2956323915
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4097680500
Short name T30
Test name
Test status
Simulation time 534495191 ps
CPU time 23.69 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 219196 kb
Host smart-b4584e3a-537f-4b16-85a0-112ef68902ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097680500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4097680500
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3428886445
Short name T16
Test name
Test status
Simulation time 1486959305 ps
CPU time 44.74 seconds
Started Jul 26 04:58:00 PM PDT 24
Finished Jul 26 04:58:45 PM PDT 24
Peak memory 219668 kb
Host smart-4e1ee222-7f71-4665-bb6a-2d9836421e40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428886445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3428886445
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1728563215
Short name T47
Test name
Test status
Simulation time 37900525962 ps
CPU time 2144.88 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 05:33:47 PM PDT 24
Peak memory 236224 kb
Host smart-ea6e409c-19b1-4aa4-b543-1d5585898621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728563215 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1728563215
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.849427835
Short name T190
Test name
Test status
Simulation time 1027941504 ps
CPU time 9.84 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 218836 kb
Host smart-484e69db-88fc-407d-9d9a-305ebb71fccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849427835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.849427835
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.835350263
Short name T41
Test name
Test status
Simulation time 5269362138 ps
CPU time 327.24 seconds
Started Jul 26 04:58:04 PM PDT 24
Finished Jul 26 05:03:31 PM PDT 24
Peak memory 238120 kb
Host smart-1b976f34-9dfc-4be6-bde9-9dfbaffac0db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835350263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.835350263
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1697832641
Short name T280
Test name
Test status
Simulation time 518137618 ps
CPU time 22.66 seconds
Started Jul 26 04:58:02 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219716 kb
Host smart-4b0a802d-65db-46ac-8055-373c573706c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697832641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1697832641
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3014242705
Short name T265
Test name
Test status
Simulation time 864541115 ps
CPU time 10.34 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:08 PM PDT 24
Peak memory 219736 kb
Host smart-b444880c-f586-4f7b-8266-2705012d7cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014242705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3014242705
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1275359671
Short name T165
Test name
Test status
Simulation time 568792829 ps
CPU time 24.23 seconds
Started Jul 26 04:57:58 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 219120 kb
Host smart-576daf8c-1128-47c0-9007-fbe770a00b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275359671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1275359671
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1235126098
Short name T163
Test name
Test status
Simulation time 4033873653 ps
CPU time 45.64 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:45 PM PDT 24
Peak memory 219760 kb
Host smart-0671abf1-aae7-4ffa-a1ab-3d74bad26381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235126098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1235126098
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1596933960
Short name T50
Test name
Test status
Simulation time 55722863775 ps
CPU time 1614.03 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 05:25:11 PM PDT 24
Peak memory 237928 kb
Host smart-db145ac3-803c-441f-8585-16e9e3b88793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596933960 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1596933960
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2479329077
Short name T167
Test name
Test status
Simulation time 169405179 ps
CPU time 8 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 218784 kb
Host smart-befb49ca-97a8-4802-adc0-62f85a5460e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479329077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2479329077
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4123373233
Short name T23
Test name
Test status
Simulation time 6312994295 ps
CPU time 311.99 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:03:18 PM PDT 24
Peak memory 243544 kb
Host smart-dd0bd8c9-b572-4461-992d-af0d67be0b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123373233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4123373233
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.59792044
Short name T296
Test name
Test status
Simulation time 513484436 ps
CPU time 22.38 seconds
Started Jul 26 04:58:04 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 219684 kb
Host smart-3ab79a92-376e-4170-a94c-daeb0aa19fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59792044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.59792044
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.328306985
Short name T235
Test name
Test status
Simulation time 525115358 ps
CPU time 11.57 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 219820 kb
Host smart-a25ab2f4-855f-4238-b9b8-17ba39d04ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328306985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.328306985
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2551464853
Short name T342
Test name
Test status
Simulation time 3983090039 ps
CPU time 32.97 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:50 PM PDT 24
Peak memory 219288 kb
Host smart-99bbc3b1-284b-481d-9185-7f4360cd0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551464853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2551464853
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1526782778
Short name T343
Test name
Test status
Simulation time 2988539013 ps
CPU time 38.07 seconds
Started Jul 26 04:57:59 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 218556 kb
Host smart-d7405be0-e2c8-45e4-95c7-d7f0f0cbe898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526782778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1526782778
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.205435321
Short name T7
Test name
Test status
Simulation time 751404311 ps
CPU time 8.46 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 218788 kb
Host smart-61f272e9-eb95-4d7b-8dee-e124f4a79678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205435321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.205435321
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2603861905
Short name T201
Test name
Test status
Simulation time 14025349765 ps
CPU time 328.91 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:03:36 PM PDT 24
Peak memory 239228 kb
Host smart-e4646690-9e78-425e-b4c3-56ec5331cb1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603861905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2603861905
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3357602922
Short name T295
Test name
Test status
Simulation time 495257043 ps
CPU time 19.29 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:27 PM PDT 24
Peak memory 219776 kb
Host smart-fd27805e-2986-4c36-a473-7e275fa0401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357602922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3357602922
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2278488250
Short name T210
Test name
Test status
Simulation time 177234495 ps
CPU time 10.52 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 219736 kb
Host smart-89cd91f7-db57-4c7f-a1dc-584220a4751b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278488250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2278488250
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.812696985
Short name T76
Test name
Test status
Simulation time 526823823 ps
CPU time 24.87 seconds
Started Jul 26 04:58:09 PM PDT 24
Finished Jul 26 04:58:34 PM PDT 24
Peak memory 219188 kb
Host smart-64edd02b-5640-458b-9faf-6ed05180eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812696985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.812696985
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.286949101
Short name T142
Test name
Test status
Simulation time 4156477766 ps
CPU time 52.72 seconds
Started Jul 26 04:58:11 PM PDT 24
Finished Jul 26 04:59:03 PM PDT 24
Peak memory 221220 kb
Host smart-4f202121-0a35-4204-b334-ebd99766eba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286949101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.286949101
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2712058356
Short name T45
Test name
Test status
Simulation time 55331045310 ps
CPU time 2190.14 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 05:34:49 PM PDT 24
Peak memory 252600 kb
Host smart-64d3fe21-0441-4e2b-a228-4d2df59e4037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712058356 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2712058356
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.575630183
Short name T213
Test name
Test status
Simulation time 508255562 ps
CPU time 10.11 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 218824 kb
Host smart-2c47477f-869f-4fda-9166-779e634d0a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575630183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.575630183
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1728480198
Short name T352
Test name
Test status
Simulation time 23757944199 ps
CPU time 335.79 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 05:03:58 PM PDT 24
Peak memory 234364 kb
Host smart-60b9b7ce-365f-4369-bba9-89fcfe1f5909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728480198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1728480198
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3284066829
Short name T173
Test name
Test status
Simulation time 342193581 ps
CPU time 19.39 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219768 kb
Host smart-b9a57bc9-7e1c-4b88-9986-41528f105d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284066829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3284066829
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3969035326
Short name T152
Test name
Test status
Simulation time 364516198 ps
CPU time 10.33 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219724 kb
Host smart-f80bbca3-20af-461d-b4b5-2ca74bf01525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969035326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3969035326
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.613684413
Short name T193
Test name
Test status
Simulation time 535745798 ps
CPU time 23.02 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 219216 kb
Host smart-8ba10cc2-14d1-4b14-b4a2-53a53b8cdd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613684413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.613684413
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1311774661
Short name T263
Test name
Test status
Simulation time 432613763 ps
CPU time 15.25 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 219272 kb
Host smart-4525f88f-6df9-4cb7-afcd-423843c524b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311774661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1311774661
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4087608810
Short name T162
Test name
Test status
Simulation time 333615540 ps
CPU time 8.31 seconds
Started Jul 26 04:57:51 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 218720 kb
Host smart-76b0e895-0485-4eee-a425-78a7fd196e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087608810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4087608810
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.29604246
Short name T314
Test name
Test status
Simulation time 92141712400 ps
CPU time 198.96 seconds
Started Jul 26 04:57:38 PM PDT 24
Finished Jul 26 05:00:57 PM PDT 24
Peak memory 218468 kb
Host smart-7d47f5ac-6e6e-4393-89b4-a7633211aef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29604246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.29604246
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4135200032
Short name T131
Test name
Test status
Simulation time 349227140 ps
CPU time 19.47 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:53 PM PDT 24
Peak memory 219768 kb
Host smart-a5577c7e-799a-4637-a77e-d94fb7f3a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135200032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4135200032
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2130456343
Short name T287
Test name
Test status
Simulation time 402217802 ps
CPU time 12.47 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 219700 kb
Host smart-78ef43a3-f500-47e8-b46d-431bdce62fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130456343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2130456343
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1190843991
Short name T24
Test name
Test status
Simulation time 1153007928 ps
CPU time 226.44 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 05:01:23 PM PDT 24
Peak memory 234492 kb
Host smart-2ed163cd-3e5a-47f1-8ade-f5029bd0dd1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190843991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1190843991
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.282500566
Short name T365
Test name
Test status
Simulation time 1382627604 ps
CPU time 20.27 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:57 PM PDT 24
Peak memory 219220 kb
Host smart-4affc7a7-fb49-4d1e-a174-9baea351e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282500566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.282500566
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3215870099
Short name T153
Test name
Test status
Simulation time 538390205 ps
CPU time 29.36 seconds
Started Jul 26 04:57:40 PM PDT 24
Finished Jul 26 04:58:10 PM PDT 24
Peak memory 219716 kb
Host smart-881ce30a-7e76-409a-b563-35577dd8f27f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215870099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3215870099
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2203481097
Short name T172
Test name
Test status
Simulation time 257337945 ps
CPU time 10.06 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:18 PM PDT 24
Peak memory 218684 kb
Host smart-355c62b8-b477-4cd2-b8ed-253c79f7c46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203481097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2203481097
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1540289260
Short name T363
Test name
Test status
Simulation time 26458435327 ps
CPU time 332.5 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 05:03:40 PM PDT 24
Peak memory 229676 kb
Host smart-1f4f5d42-7489-44e5-9a7b-ba6b02fda444
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540289260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1540289260
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3544780839
Short name T337
Test name
Test status
Simulation time 498008151 ps
CPU time 22.59 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 219784 kb
Host smart-7298b93b-80fc-4cbd-9e73-0657a124ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544780839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3544780839
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3000004371
Short name T357
Test name
Test status
Simulation time 356342086 ps
CPU time 10.43 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:17 PM PDT 24
Peak memory 219700 kb
Host smart-870c2f75-570f-4e1f-8de2-463bec54a201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000004371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3000004371
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2525366097
Short name T301
Test name
Test status
Simulation time 2043998177 ps
CPU time 23.35 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:58:44 PM PDT 24
Peak memory 219040 kb
Host smart-67f6b51c-4425-4f78-8079-f5e919825a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525366097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2525366097
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1918007176
Short name T148
Test name
Test status
Simulation time 4069354167 ps
CPU time 50.44 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:59:08 PM PDT 24
Peak memory 220352 kb
Host smart-f0ed23d9-52f0-4f47-ba48-5f4dd81483bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918007176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1918007176
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3658806683
Short name T48
Test name
Test status
Simulation time 94394432578 ps
CPU time 1879.89 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 05:29:37 PM PDT 24
Peak memory 245256 kb
Host smart-ad3c2363-2a7c-4990-8388-7b60528cf104
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658806683 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3658806683
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.854848759
Short name T328
Test name
Test status
Simulation time 663724151 ps
CPU time 8.33 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 218704 kb
Host smart-f848a2c7-4e03-453a-b407-8a96b785ff96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854848759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.854848759
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2935853180
Short name T367
Test name
Test status
Simulation time 15605846246 ps
CPU time 301.57 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 05:03:09 PM PDT 24
Peak memory 244756 kb
Host smart-91a93da8-91e1-431a-9e28-60f2ea98c229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935853180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2935853180
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3736838759
Short name T151
Test name
Test status
Simulation time 1377708823 ps
CPU time 19 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:38 PM PDT 24
Peak memory 219780 kb
Host smart-d9f84040-7118-4fbf-b1b6-31bf4f3923fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736838759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3736838759
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3015886662
Short name T324
Test name
Test status
Simulation time 179172055 ps
CPU time 10.72 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219724 kb
Host smart-82683460-2fb2-49b3-b14b-e9f8ae41c808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015886662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3015886662
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.562802187
Short name T276
Test name
Test status
Simulation time 397747397 ps
CPU time 19.19 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 219168 kb
Host smart-8becc302-d91c-43ae-900b-8a097f602e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562802187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.562802187
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1871978667
Short name T171
Test name
Test status
Simulation time 1962180522 ps
CPU time 27.21 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 218396 kb
Host smart-dac7e345-782f-44ab-a51b-145899e0f5f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871978667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1871978667
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3503646457
Short name T46
Test name
Test status
Simulation time 35420395955 ps
CPU time 721.46 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 05:10:09 PM PDT 24
Peak memory 230552 kb
Host smart-0a2c12f4-de83-4c14-a2d0-7d4474a7f4e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503646457 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3503646457
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3557604355
Short name T1
Test name
Test status
Simulation time 2047433845 ps
CPU time 15.31 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 218872 kb
Host smart-651b60d8-6436-4306-bc45-3ce36531138b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557604355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3557604355
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3066809301
Short name T269
Test name
Test status
Simulation time 3190742695 ps
CPU time 206.73 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 05:01:35 PM PDT 24
Peak memory 226888 kb
Host smart-6f029e81-5ce9-46cf-9ea3-44a0dbba99fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066809301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3066809301
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2843117792
Short name T239
Test name
Test status
Simulation time 5512398354 ps
CPU time 19.09 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:34 PM PDT 24
Peak memory 219816 kb
Host smart-ec890041-da00-43f3-9e67-baec33bacaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843117792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2843117792
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3985887250
Short name T199
Test name
Test status
Simulation time 1070152214 ps
CPU time 12.15 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 219760 kb
Host smart-dfad0974-2308-48a5-b009-036869eefa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985887250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3985887250
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3271118615
Short name T369
Test name
Test status
Simulation time 345587340 ps
CPU time 19.13 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219252 kb
Host smart-0ef75d4b-79af-46e5-ae29-19fabb775303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271118615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3271118615
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1485853310
Short name T136
Test name
Test status
Simulation time 663733188 ps
CPU time 8.26 seconds
Started Jul 26 04:58:10 PM PDT 24
Finished Jul 26 04:58:19 PM PDT 24
Peak memory 218852 kb
Host smart-5f30b4cb-f837-44c0-9a21-d53231419622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485853310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1485853310
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3566412574
Short name T288
Test name
Test status
Simulation time 67478079612 ps
CPU time 296.23 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 05:03:12 PM PDT 24
Peak memory 234164 kb
Host smart-658a5608-0a1b-4fdb-a7b4-371bb199351a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566412574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3566412574
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.539645296
Short name T39
Test name
Test status
Simulation time 1650137116 ps
CPU time 18.82 seconds
Started Jul 26 04:58:05 PM PDT 24
Finished Jul 26 04:58:24 PM PDT 24
Peak memory 219752 kb
Host smart-23382318-42f1-4894-9f52-b4e5665464e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539645296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.539645296
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2297934750
Short name T362
Test name
Test status
Simulation time 542958507 ps
CPU time 12.45 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:21 PM PDT 24
Peak memory 219748 kb
Host smart-30b3e81d-9e03-4615-a36b-7d49ab6b4ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297934750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2297934750
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2665736380
Short name T19
Test name
Test status
Simulation time 362969282 ps
CPU time 19.74 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 219236 kb
Host smart-5f7ad531-c018-4987-b5e6-e001cc7b730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665736380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2665736380
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2997594706
Short name T143
Test name
Test status
Simulation time 6337291371 ps
CPU time 76.66 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:59:24 PM PDT 24
Peak memory 219768 kb
Host smart-ee9b623e-af5b-4032-8f21-4c886a18fe1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997594706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2997594706
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3051137149
Short name T62
Test name
Test status
Simulation time 987160110 ps
CPU time 10.11 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:19 PM PDT 24
Peak memory 217864 kb
Host smart-0c92c146-146b-4dbf-812c-bd0c5c12b4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051137149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3051137149
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2992025029
Short name T331
Test name
Test status
Simulation time 2787365623 ps
CPU time 164.95 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 05:01:03 PM PDT 24
Peak memory 219564 kb
Host smart-1882a6a6-06ad-4e25-b5ea-89fd5e89bf5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992025029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2992025029
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1967221347
Short name T330
Test name
Test status
Simulation time 261737277 ps
CPU time 12.3 seconds
Started Jul 26 04:58:12 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 220056 kb
Host smart-104111f4-27d3-4006-a8e4-79194de6fe6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967221347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1967221347
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2949706543
Short name T282
Test name
Test status
Simulation time 703414788 ps
CPU time 19.5 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:58:42 PM PDT 24
Peak memory 219140 kb
Host smart-acbd7c57-a565-4d41-b9d5-e6f3d31ee043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949706543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2949706543
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3874677480
Short name T116
Test name
Test status
Simulation time 823480303 ps
CPU time 34.84 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:53 PM PDT 24
Peak memory 219756 kb
Host smart-f7e29469-2a68-4c37-ae50-d619ebf6cfaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874677480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3874677480
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3450425022
Short name T12
Test name
Test status
Simulation time 84456643748 ps
CPU time 3131.66 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 05:50:28 PM PDT 24
Peak memory 237968 kb
Host smart-2d7bcf67-a255-4251-92fc-6dcd8273b7af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450425022 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3450425022
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3099155356
Short name T252
Test name
Test status
Simulation time 168718951 ps
CPU time 8.47 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:22 PM PDT 24
Peak memory 218740 kb
Host smart-74bfef07-af0d-49b7-94e2-15340ea7ca92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099155356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3099155356
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.958109773
Short name T341
Test name
Test status
Simulation time 4291218342 ps
CPU time 304.82 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 05:03:20 PM PDT 24
Peak memory 238264 kb
Host smart-565df2be-78d8-42f1-81a7-22198328d9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958109773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.958109773
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3137339095
Short name T349
Test name
Test status
Simulation time 661732751 ps
CPU time 19.11 seconds
Started Jul 26 04:58:21 PM PDT 24
Finished Jul 26 04:58:41 PM PDT 24
Peak memory 219664 kb
Host smart-ebe6a3a7-bc59-413c-a134-7ee8e5116b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137339095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3137339095
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4180936015
Short name T127
Test name
Test status
Simulation time 1025017743 ps
CPU time 11.94 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 219644 kb
Host smart-13490568-864d-4a0c-9b61-824ba7c91b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180936015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4180936015
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4190613517
Short name T197
Test name
Test status
Simulation time 4044082655 ps
CPU time 35.33 seconds
Started Jul 26 04:58:22 PM PDT 24
Finished Jul 26 04:58:57 PM PDT 24
Peak memory 219316 kb
Host smart-8c908754-4aba-4074-9fbc-d04a30e59273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190613517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4190613517
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.175800283
Short name T273
Test name
Test status
Simulation time 1145639566 ps
CPU time 19.36 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:36 PM PDT 24
Peak memory 219304 kb
Host smart-a437ff61-dbce-4a3e-bb33-d021a41eb849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175800283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.175800283
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.777379910
Short name T355
Test name
Test status
Simulation time 252590803 ps
CPU time 10.27 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 219156 kb
Host smart-874806b9-539a-49dc-b832-fb1f27cd2ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777379910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.777379910
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4288714892
Short name T218
Test name
Test status
Simulation time 11882108363 ps
CPU time 324.71 seconds
Started Jul 26 04:58:26 PM PDT 24
Finished Jul 26 05:03:51 PM PDT 24
Peak memory 229784 kb
Host smart-4ef3fd45-ee34-42db-93bb-2b035c9f84f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288714892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4288714892
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3114251473
Short name T59
Test name
Test status
Simulation time 9009017523 ps
CPU time 32.46 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 219784 kb
Host smart-b4028664-1503-43c8-93a8-ab8aa573f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114251473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3114251473
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1739573485
Short name T242
Test name
Test status
Simulation time 1715542472 ps
CPU time 11.9 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 219864 kb
Host smart-54839036-0144-405e-a36d-8234a9a423f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739573485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1739573485
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3087774507
Short name T5
Test name
Test status
Simulation time 363164963 ps
CPU time 19.92 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:35 PM PDT 24
Peak memory 219324 kb
Host smart-32bfc6f0-06f4-4954-8efa-d3ce97c83895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087774507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3087774507
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2745202973
Short name T271
Test name
Test status
Simulation time 1551793499 ps
CPU time 33.67 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:49 PM PDT 24
Peak memory 219796 kb
Host smart-8423c635-1326-4755-adca-b7b9e6af5cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745202973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2745202973
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3279528923
Short name T183
Test name
Test status
Simulation time 2059678402 ps
CPU time 8.16 seconds
Started Jul 26 04:58:08 PM PDT 24
Finished Jul 26 04:58:16 PM PDT 24
Peak memory 218784 kb
Host smart-235ff947-9e40-42c2-892b-e8d8e7f2ab87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279528923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3279528923
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2113003433
Short name T154
Test name
Test status
Simulation time 3346925089 ps
CPU time 138.04 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 05:00:32 PM PDT 24
Peak memory 238220 kb
Host smart-10bac691-c38f-4a24-ac1d-f5193a813345
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113003433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2113003433
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3530505403
Short name T364
Test name
Test status
Simulation time 517577914 ps
CPU time 21.69 seconds
Started Jul 26 04:58:15 PM PDT 24
Finished Jul 26 04:58:37 PM PDT 24
Peak memory 219844 kb
Host smart-e4b0b73b-0096-4d16-a546-2f2a4fcff648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530505403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3530505403
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1057958696
Short name T338
Test name
Test status
Simulation time 256793404 ps
CPU time 11.59 seconds
Started Jul 26 04:58:14 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 219864 kb
Host smart-a99f8942-16ac-4fdd-a4ef-b62255f977fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057958696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1057958696
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3278366142
Short name T311
Test name
Test status
Simulation time 510359889 ps
CPU time 23.42 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:31 PM PDT 24
Peak memory 219136 kb
Host smart-62a498d3-60bb-4124-a904-340f39241c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278366142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3278366142
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3124062186
Short name T293
Test name
Test status
Simulation time 1076395118 ps
CPU time 25.6 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:44 PM PDT 24
Peak memory 218312 kb
Host smart-dcfa0885-7fdf-4ef7-a1c8-78cdf53103f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124062186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3124062186
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2912728671
Short name T286
Test name
Test status
Simulation time 971214840 ps
CPU time 8.03 seconds
Started Jul 26 04:58:19 PM PDT 24
Finished Jul 26 04:58:27 PM PDT 24
Peak memory 218916 kb
Host smart-b3c1667c-69b4-4a34-a0c9-ffefb70f0df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912728671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2912728671
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3990872668
Short name T250
Test name
Test status
Simulation time 10539739180 ps
CPU time 312.6 seconds
Started Jul 26 04:58:06 PM PDT 24
Finished Jul 26 05:03:19 PM PDT 24
Peak memory 229040 kb
Host smart-70cd094e-7e4b-4a06-b5ac-ef2d05c7c820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990872668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3990872668
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.464645419
Short name T168
Test name
Test status
Simulation time 1704449075 ps
CPU time 22.66 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 219772 kb
Host smart-5b96428f-d592-4680-9bb6-cd2488794163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464645419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.464645419
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3888255423
Short name T145
Test name
Test status
Simulation time 221426293 ps
CPU time 9.96 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 04:58:27 PM PDT 24
Peak memory 219836 kb
Host smart-db7e4a2c-82ab-4299-8f47-9f08c5ffee77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888255423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3888255423
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.301320870
Short name T75
Test name
Test status
Simulation time 1456974390 ps
CPU time 23.56 seconds
Started Jul 26 04:58:18 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 219076 kb
Host smart-5e3cbe93-7db6-4363-b47f-548e55f7f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301320870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.301320870
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.498879964
Short name T102
Test name
Test status
Simulation time 921070014 ps
CPU time 59.05 seconds
Started Jul 26 04:58:27 PM PDT 24
Finished Jul 26 04:59:26 PM PDT 24
Peak memory 227964 kb
Host smart-4ea57f03-dfd6-44e2-b672-9cc01d7d6eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498879964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.498879964
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2077371813
Short name T234
Test name
Test status
Simulation time 249318946 ps
CPU time 9.82 seconds
Started Jul 26 04:58:16 PM PDT 24
Finished Jul 26 04:58:26 PM PDT 24
Peak memory 218232 kb
Host smart-9c566ced-7b24-4c5f-9bdb-fc2c0144e5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077371813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2077371813
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1772086029
Short name T270
Test name
Test status
Simulation time 14467772697 ps
CPU time 269.79 seconds
Started Jul 26 04:58:17 PM PDT 24
Finished Jul 26 05:02:47 PM PDT 24
Peak memory 228556 kb
Host smart-2033b649-4bf2-4f64-8d15-52d8b08435a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772086029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1772086029
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2736539800
Short name T267
Test name
Test status
Simulation time 2243017218 ps
CPU time 22.58 seconds
Started Jul 26 04:58:12 PM PDT 24
Finished Jul 26 04:58:34 PM PDT 24
Peak memory 219780 kb
Host smart-82be855a-6518-4ace-9a80-0f0d48b9cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736539800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2736539800
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1314620394
Short name T182
Test name
Test status
Simulation time 365621349 ps
CPU time 10.45 seconds
Started Jul 26 04:58:09 PM PDT 24
Finished Jul 26 04:58:19 PM PDT 24
Peak memory 219744 kb
Host smart-1bb64e74-9341-4351-9942-4995803f9ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314620394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1314620394
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3472171820
Short name T170
Test name
Test status
Simulation time 504200083 ps
CPU time 23.51 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:58:31 PM PDT 24
Peak memory 219172 kb
Host smart-d71a9cbf-0fad-4059-b105-1d414e6af6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472171820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3472171820
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1039067459
Short name T291
Test name
Test status
Simulation time 3066640531 ps
CPU time 75.58 seconds
Started Jul 26 04:58:07 PM PDT 24
Finished Jul 26 04:59:23 PM PDT 24
Peak memory 221052 kb
Host smart-2a52482a-cb7e-46ab-a3f9-24c8c8c8a659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039067459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1039067459
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1650850560
Short name T13
Test name
Test status
Simulation time 25846909339 ps
CPU time 944.49 seconds
Started Jul 26 04:58:11 PM PDT 24
Finished Jul 26 05:13:56 PM PDT 24
Peak memory 232060 kb
Host smart-98b7d3e5-a739-4459-99a2-51de92fbdcb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650850560 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1650850560
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1443060054
Short name T181
Test name
Test status
Simulation time 991041116 ps
CPU time 10.16 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:57:47 PM PDT 24
Peak memory 218712 kb
Host smart-9d173996-705a-4312-8c36-05b44642861b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443060054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1443060054
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.77073078
Short name T179
Test name
Test status
Simulation time 19573988005 ps
CPU time 182.99 seconds
Started Jul 26 04:57:40 PM PDT 24
Finished Jul 26 05:00:43 PM PDT 24
Peak memory 234244 kb
Host smart-c20b98ba-d2fe-4947-acf5-a6f670150468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77073078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_cor
rupt_sig_fatal_chk.77073078
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.22723867
Short name T300
Test name
Test status
Simulation time 2061668678 ps
CPU time 22.5 seconds
Started Jul 26 04:57:39 PM PDT 24
Finished Jul 26 04:58:01 PM PDT 24
Peak memory 219784 kb
Host smart-cd23d3af-739c-489d-b1ba-87532ec8710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22723867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.22723867
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.854926012
Short name T194
Test name
Test status
Simulation time 802748004 ps
CPU time 10.62 seconds
Started Jul 26 04:57:30 PM PDT 24
Finished Jul 26 04:57:40 PM PDT 24
Peak memory 219756 kb
Host smart-b17cd6f4-674d-4aa8-88ec-9878a57d73ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854926012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.854926012
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3832111575
Short name T361
Test name
Test status
Simulation time 517458111 ps
CPU time 23.68 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 04:57:57 PM PDT 24
Peak memory 219204 kb
Host smart-6a34c3c6-02e3-4382-88d0-804d013902d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832111575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3832111575
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3376050885
Short name T228
Test name
Test status
Simulation time 2709225257 ps
CPU time 39.21 seconds
Started Jul 26 04:57:36 PM PDT 24
Finished Jul 26 04:58:15 PM PDT 24
Peak memory 219768 kb
Host smart-1c55c424-c725-415d-bbc9-66e3b9ae48ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376050885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3376050885
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3725391610
Short name T184
Test name
Test status
Simulation time 1032941994 ps
CPU time 9.75 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 218780 kb
Host smart-bb7efabf-14bb-4024-8551-a9072069f246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725391610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3725391610
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3672451007
Short name T322
Test name
Test status
Simulation time 4325270796 ps
CPU time 245.16 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 05:01:53 PM PDT 24
Peak memory 225240 kb
Host smart-497c6364-650c-4ef4-930e-a0d9725ad1d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672451007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3672451007
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2053241843
Short name T138
Test name
Test status
Simulation time 496423028 ps
CPU time 23.18 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 219680 kb
Host smart-87c9c836-2f97-40a5-8a92-e32db9f0f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053241843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2053241843
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.997171265
Short name T137
Test name
Test status
Simulation time 524444071 ps
CPU time 12.16 seconds
Started Jul 26 04:57:42 PM PDT 24
Finished Jul 26 04:57:54 PM PDT 24
Peak memory 219720 kb
Host smart-94509c37-ec2b-439a-bfe9-a6422ee9b749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997171265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.997171265
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3501386443
Short name T366
Test name
Test status
Simulation time 1163544350 ps
CPU time 19.48 seconds
Started Jul 26 04:57:45 PM PDT 24
Finished Jul 26 04:58:04 PM PDT 24
Peak memory 219080 kb
Host smart-5ea05a88-d590-4375-8297-694058a8bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501386443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3501386443
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2295671999
Short name T174
Test name
Test status
Simulation time 2059022320 ps
CPU time 23.34 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:58 PM PDT 24
Peak memory 219144 kb
Host smart-caa6b332-aef9-47de-b635-67f7bf092ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295671999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2295671999
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.398092898
Short name T292
Test name
Test status
Simulation time 109055604283 ps
CPU time 2791.89 seconds
Started Jul 26 04:57:47 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 252532 kb
Host smart-1d1ea32a-b37b-4410-b78f-c4961d756d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398092898 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.398092898
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1105439379
Short name T302
Test name
Test status
Simulation time 249527008 ps
CPU time 10.07 seconds
Started Jul 26 04:57:48 PM PDT 24
Finished Jul 26 04:57:58 PM PDT 24
Peak memory 218772 kb
Host smart-2871bf52-20a7-49ab-befb-1a3fcf6a3f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105439379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1105439379
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.192709946
Short name T205
Test name
Test status
Simulation time 4077228759 ps
CPU time 169.48 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 05:00:25 PM PDT 24
Peak memory 245272 kb
Host smart-fd76e232-9b6e-4533-9492-29d10cfcb201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192709946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.192709946
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3193177511
Short name T38
Test name
Test status
Simulation time 345753533 ps
CPU time 19.58 seconds
Started Jul 26 04:57:34 PM PDT 24
Finished Jul 26 04:57:54 PM PDT 24
Peak memory 219676 kb
Host smart-fed9888f-5d5d-4560-bbaf-9d46b4b6d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193177511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3193177511
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.116283325
Short name T202
Test name
Test status
Simulation time 1103580430 ps
CPU time 11.98 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:47 PM PDT 24
Peak memory 219700 kb
Host smart-f8da0b0b-454a-48d1-bce2-547594eddeee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116283325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.116283325
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2065242096
Short name T200
Test name
Test status
Simulation time 2512856895 ps
CPU time 23.68 seconds
Started Jul 26 04:57:47 PM PDT 24
Finished Jul 26 04:58:10 PM PDT 24
Peak memory 219084 kb
Host smart-b60ade0f-715b-4981-b994-f1dc93061018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065242096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2065242096
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1244829388
Short name T128
Test name
Test status
Simulation time 2250092113 ps
CPU time 11.37 seconds
Started Jul 26 04:57:45 PM PDT 24
Finished Jul 26 04:57:56 PM PDT 24
Peak memory 219632 kb
Host smart-3a5d2b9f-67aa-44c4-b5ca-af69b72abfb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244829388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1244829388
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.414276994
Short name T49
Test name
Test status
Simulation time 33541103390 ps
CPU time 1302.18 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 05:19:15 PM PDT 24
Peak memory 234212 kb
Host smart-541e2166-8cc3-4e4c-b549-d2df141722dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414276994 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.414276994
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2140873206
Short name T319
Test name
Test status
Simulation time 174440013 ps
CPU time 8.14 seconds
Started Jul 26 04:57:41 PM PDT 24
Finished Jul 26 04:57:49 PM PDT 24
Peak memory 218724 kb
Host smart-99908019-3547-486f-9f5c-2f785a454516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140873206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2140873206
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4114775802
Short name T114
Test name
Test status
Simulation time 3325606196 ps
CPU time 170.7 seconds
Started Jul 26 04:57:37 PM PDT 24
Finished Jul 26 05:00:28 PM PDT 24
Peak memory 225400 kb
Host smart-21b94141-e0dd-4a22-a16d-1a1fd297177e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114775802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4114775802
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.669309892
Short name T209
Test name
Test status
Simulation time 8544210544 ps
CPU time 31.44 seconds
Started Jul 26 04:57:53 PM PDT 24
Finished Jul 26 04:58:25 PM PDT 24
Peak memory 219364 kb
Host smart-67c3fdb4-6627-4654-93c5-6df8ee405cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669309892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.669309892
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.542918191
Short name T141
Test name
Test status
Simulation time 695582682 ps
CPU time 10.15 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:45 PM PDT 24
Peak memory 219704 kb
Host smart-7788463d-1520-4cdf-a0b9-541758c74ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542918191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.542918191
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4191718639
Short name T246
Test name
Test status
Simulation time 1051651180 ps
CPU time 23.95 seconds
Started Jul 26 04:57:46 PM PDT 24
Finished Jul 26 04:58:15 PM PDT 24
Peak memory 219812 kb
Host smart-0d560121-9451-409a-b4c8-e399be06f63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191718639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4191718639
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3717077153
Short name T146
Test name
Test status
Simulation time 1092372420 ps
CPU time 38.97 seconds
Started Jul 26 04:57:41 PM PDT 24
Finished Jul 26 04:58:20 PM PDT 24
Peak memory 219652 kb
Host smart-f49ee518-f7c8-4a44-9b8f-b35073546ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717077153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3717077153
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3240947128
Short name T214
Test name
Test status
Simulation time 171124026 ps
CPU time 8.75 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:44 PM PDT 24
Peak memory 218780 kb
Host smart-d59265ea-2e16-4330-b732-aac0f9acf88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240947128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3240947128
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2956414154
Short name T264
Test name
Test status
Simulation time 23007872652 ps
CPU time 494.11 seconds
Started Jul 26 04:57:33 PM PDT 24
Finished Jul 26 05:05:47 PM PDT 24
Peak memory 238772 kb
Host smart-1bb6b0ac-9149-4c25-be3b-fc9b3d569552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956414154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2956414154
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3160309067
Short name T253
Test name
Test status
Simulation time 351847036 ps
CPU time 18.98 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:54 PM PDT 24
Peak memory 219704 kb
Host smart-8c2095af-daca-41b8-92cc-de86dbaf1717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160309067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3160309067
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3689522161
Short name T238
Test name
Test status
Simulation time 361869964 ps
CPU time 10.59 seconds
Started Jul 26 04:57:35 PM PDT 24
Finished Jul 26 04:57:46 PM PDT 24
Peak memory 219740 kb
Host smart-24d812e4-e556-476d-af2b-c1e9d096a4a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689522161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3689522161
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1155700270
Short name T339
Test name
Test status
Simulation time 485477701 ps
CPU time 20.74 seconds
Started Jul 26 04:57:32 PM PDT 24
Finished Jul 26 04:57:53 PM PDT 24
Peak memory 219336 kb
Host smart-9b0dee5f-f92d-4eb5-95f5-236890dc7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155700270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1155700270
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2174526145
Short name T177
Test name
Test status
Simulation time 9164271765 ps
CPU time 35.62 seconds
Started Jul 26 04:58:03 PM PDT 24
Finished Jul 26 04:58:39 PM PDT 24
Peak memory 219832 kb
Host smart-20f56154-4d7e-42ca-9574-3aec06786522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174526145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2174526145
Directory /workspace/9.rom_ctrl_stress_all/latest
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