Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 466
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T302 /workspace/coverage/default/40.rom_ctrl_smoke.1727974519 Jul 27 04:51:14 PM PDT 24 Jul 27 04:51:34 PM PDT 24 346057053 ps
T303 /workspace/coverage/default/47.rom_ctrl_stress_all.3252486757 Jul 27 04:51:24 PM PDT 24 Jul 27 04:52:20 PM PDT 24 879138421 ps
T304 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2086692702 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:24 PM PDT 24 759637303 ps
T305 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3761770102 Jul 27 04:50:51 PM PDT 24 Jul 27 04:54:50 PM PDT 24 19863593468 ps
T306 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3940235454 Jul 27 04:51:29 PM PDT 24 Jul 27 04:51:42 PM PDT 24 1073287264 ps
T307 /workspace/coverage/default/40.rom_ctrl_alert_test.2046506888 Jul 27 04:51:11 PM PDT 24 Jul 27 04:51:19 PM PDT 24 194594784 ps
T308 /workspace/coverage/default/0.rom_ctrl_stress_all.4256047149 Jul 27 04:50:24 PM PDT 24 Jul 27 04:51:19 PM PDT 24 1807225538 ps
T309 /workspace/coverage/default/14.rom_ctrl_alert_test.3189216490 Jul 27 04:50:48 PM PDT 24 Jul 27 04:50:58 PM PDT 24 248565731 ps
T310 /workspace/coverage/default/17.rom_ctrl_alert_test.2523352161 Jul 27 04:50:57 PM PDT 24 Jul 27 04:51:05 PM PDT 24 661976064 ps
T311 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3186538831 Jul 27 04:51:13 PM PDT 24 Jul 27 04:54:49 PM PDT 24 12357226913 ps
T312 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1989939244 Jul 27 04:50:53 PM PDT 24 Jul 27 04:51:13 PM PDT 24 4712182616 ps
T313 /workspace/coverage/default/46.rom_ctrl_smoke.52054724 Jul 27 04:51:35 PM PDT 24 Jul 27 04:52:01 PM PDT 24 707817369 ps
T314 /workspace/coverage/default/47.rom_ctrl_alert_test.1707610453 Jul 27 04:51:21 PM PDT 24 Jul 27 04:51:29 PM PDT 24 916789585 ps
T315 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1803526484 Jul 27 04:50:31 PM PDT 24 Jul 27 05:01:49 PM PDT 24 66327729294 ps
T316 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4173040803 Jul 27 04:50:42 PM PDT 24 Jul 27 04:56:05 PM PDT 24 12406335070 ps
T317 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1610076265 Jul 27 04:51:23 PM PDT 24 Jul 27 04:51:46 PM PDT 24 513379070 ps
T318 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3158133427 Jul 27 04:50:57 PM PDT 24 Jul 27 04:53:19 PM PDT 24 1974664512 ps
T319 /workspace/coverage/default/5.rom_ctrl_smoke.1223936728 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:56 PM PDT 24 28315687502 ps
T320 /workspace/coverage/default/41.rom_ctrl_smoke.1345015413 Jul 27 04:52:32 PM PDT 24 Jul 27 04:52:55 PM PDT 24 2976535633 ps
T321 /workspace/coverage/default/37.rom_ctrl_stress_all.3510623257 Jul 27 04:51:30 PM PDT 24 Jul 27 04:52:41 PM PDT 24 1268406943 ps
T322 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1473414073 Jul 27 04:50:49 PM PDT 24 Jul 27 04:51:01 PM PDT 24 269876709 ps
T24 /workspace/coverage/default/1.rom_ctrl_sec_cm.3441029188 Jul 27 04:50:17 PM PDT 24 Jul 27 04:54:17 PM PDT 24 3015169563 ps
T323 /workspace/coverage/default/25.rom_ctrl_alert_test.1506978024 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:22 PM PDT 24 174718512 ps
T324 /workspace/coverage/default/8.rom_ctrl_alert_test.4235807038 Jul 27 04:50:49 PM PDT 24 Jul 27 04:50:57 PM PDT 24 302565262 ps
T325 /workspace/coverage/default/36.rom_ctrl_stress_all.2073061324 Jul 27 04:51:15 PM PDT 24 Jul 27 04:51:56 PM PDT 24 564312633 ps
T326 /workspace/coverage/default/35.rom_ctrl_alert_test.2883486110 Jul 27 04:51:24 PM PDT 24 Jul 27 04:51:34 PM PDT 24 257307873 ps
T327 /workspace/coverage/default/46.rom_ctrl_alert_test.2610326184 Jul 27 04:51:33 PM PDT 24 Jul 27 04:51:44 PM PDT 24 250276380 ps
T328 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2211577968 Jul 27 04:50:49 PM PDT 24 Jul 27 05:25:53 PM PDT 24 101865382438 ps
T329 /workspace/coverage/default/6.rom_ctrl_alert_test.704860826 Jul 27 04:50:47 PM PDT 24 Jul 27 04:50:57 PM PDT 24 993064715 ps
T330 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3222656022 Jul 27 04:51:01 PM PDT 24 Jul 27 04:51:24 PM PDT 24 512702472 ps
T331 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.661394894 Jul 27 04:51:03 PM PDT 24 Jul 27 04:51:15 PM PDT 24 1021717544 ps
T332 /workspace/coverage/default/34.rom_ctrl_stress_all.367873323 Jul 27 04:51:27 PM PDT 24 Jul 27 04:52:03 PM PDT 24 1625078954 ps
T333 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3403745937 Jul 27 04:51:35 PM PDT 24 Jul 27 04:54:50 PM PDT 24 3659315095 ps
T334 /workspace/coverage/default/9.rom_ctrl_stress_all.3263771393 Jul 27 04:50:38 PM PDT 24 Jul 27 04:52:49 PM PDT 24 6942635208 ps
T335 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2845137647 Jul 27 04:51:24 PM PDT 24 Jul 27 04:51:35 PM PDT 24 351404385 ps
T336 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2416257560 Jul 27 04:51:12 PM PDT 24 Jul 27 04:55:30 PM PDT 24 56875447064 ps
T337 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.616409302 Jul 27 04:50:42 PM PDT 24 Jul 27 04:51:01 PM PDT 24 1837372649 ps
T338 /workspace/coverage/default/30.rom_ctrl_smoke.661145015 Jul 27 04:51:20 PM PDT 24 Jul 27 04:51:45 PM PDT 24 1130652140 ps
T339 /workspace/coverage/default/6.rom_ctrl_stress_all.806243359 Jul 27 04:50:50 PM PDT 24 Jul 27 04:51:31 PM PDT 24 800071783 ps
T340 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1910476409 Jul 27 04:51:31 PM PDT 24 Jul 27 04:51:54 PM PDT 24 1986533913 ps
T341 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1734887717 Jul 27 04:50:43 PM PDT 24 Jul 27 04:51:03 PM PDT 24 1224440699 ps
T342 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2817703486 Jul 27 04:50:48 PM PDT 24 Jul 27 04:51:12 PM PDT 24 497262459 ps
T343 /workspace/coverage/default/14.rom_ctrl_smoke.3068885012 Jul 27 04:50:52 PM PDT 24 Jul 27 04:51:12 PM PDT 24 343041108 ps
T344 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1548492081 Jul 27 04:50:40 PM PDT 24 Jul 27 04:54:58 PM PDT 24 4970037563 ps
T345 /workspace/coverage/default/49.rom_ctrl_smoke.121984752 Jul 27 04:51:11 PM PDT 24 Jul 27 04:51:36 PM PDT 24 8389443033 ps
T346 /workspace/coverage/default/38.rom_ctrl_stress_all.2748177862 Jul 27 04:51:32 PM PDT 24 Jul 27 04:51:56 PM PDT 24 1825819197 ps
T347 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2341686544 Jul 27 04:50:48 PM PDT 24 Jul 27 04:51:12 PM PDT 24 2069427543 ps
T348 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2133325544 Jul 27 04:50:57 PM PDT 24 Jul 27 04:51:07 PM PDT 24 790113803 ps
T349 /workspace/coverage/default/15.rom_ctrl_alert_test.2488875595 Jul 27 04:50:46 PM PDT 24 Jul 27 04:50:56 PM PDT 24 2243743741 ps
T350 /workspace/coverage/default/38.rom_ctrl_alert_test.1559771224 Jul 27 04:51:19 PM PDT 24 Jul 27 04:51:34 PM PDT 24 3935097032 ps
T351 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.433628872 Jul 27 04:52:12 PM PDT 24 Jul 27 04:52:23 PM PDT 24 176882060 ps
T352 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3472601192 Jul 27 04:51:19 PM PDT 24 Jul 27 04:51:40 PM PDT 24 496995207 ps
T353 /workspace/coverage/default/36.rom_ctrl_smoke.166315827 Jul 27 04:51:09 PM PDT 24 Jul 27 04:51:33 PM PDT 24 535947619 ps
T354 /workspace/coverage/default/35.rom_ctrl_stress_all.297706097 Jul 27 04:51:12 PM PDT 24 Jul 27 04:52:06 PM PDT 24 813995404 ps
T355 /workspace/coverage/default/31.rom_ctrl_smoke.2298756307 Jul 27 04:51:06 PM PDT 24 Jul 27 04:51:26 PM PDT 24 360218230 ps
T356 /workspace/coverage/default/28.rom_ctrl_alert_test.3534304524 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:21 PM PDT 24 169196235 ps
T25 /workspace/coverage/default/3.rom_ctrl_sec_cm.901515048 Jul 27 04:50:31 PM PDT 24 Jul 27 04:54:17 PM PDT 24 3205332900 ps
T357 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3830059794 Jul 27 04:51:22 PM PDT 24 Jul 27 04:51:32 PM PDT 24 186111735 ps
T358 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3101884309 Jul 27 04:51:17 PM PDT 24 Jul 27 04:54:06 PM PDT 24 2396826784 ps
T359 /workspace/coverage/default/13.rom_ctrl_alert_test.2638569648 Jul 27 04:50:45 PM PDT 24 Jul 27 04:50:58 PM PDT 24 2357773885 ps
T360 /workspace/coverage/default/42.rom_ctrl_alert_test.3483695822 Jul 27 04:51:35 PM PDT 24 Jul 27 04:51:44 PM PDT 24 339322305 ps
T361 /workspace/coverage/default/24.rom_ctrl_alert_test.271361036 Jul 27 04:51:03 PM PDT 24 Jul 27 04:51:14 PM PDT 24 1773721465 ps
T362 /workspace/coverage/default/42.rom_ctrl_stress_all.4108622365 Jul 27 04:51:24 PM PDT 24 Jul 27 04:52:29 PM PDT 24 1358484309 ps
T363 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3083109109 Jul 27 04:51:21 PM PDT 24 Jul 27 04:51:43 PM PDT 24 539316579 ps
T364 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3052468791 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:50 PM PDT 24 1148863028 ps
T365 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1591591874 Jul 27 04:51:01 PM PDT 24 Jul 27 04:51:20 PM PDT 24 1376452894 ps
T366 /workspace/coverage/default/18.rom_ctrl_smoke.1043987097 Jul 27 04:50:56 PM PDT 24 Jul 27 04:51:19 PM PDT 24 1735682816 ps
T367 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1177662776 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:35 PM PDT 24 1019203202 ps
T368 /workspace/coverage/default/15.rom_ctrl_stress_all.4013305247 Jul 27 04:50:44 PM PDT 24 Jul 27 04:51:16 PM PDT 24 2303789288 ps
T369 /workspace/coverage/default/40.rom_ctrl_stress_all.2483787851 Jul 27 04:51:33 PM PDT 24 Jul 27 04:52:15 PM PDT 24 555311562 ps
T370 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3087610045 Jul 27 04:51:08 PM PDT 24 Jul 27 04:51:30 PM PDT 24 517826114 ps
T54 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4279135222 Jul 27 04:50:50 PM PDT 24 Jul 27 04:51:00 PM PDT 24 496329312 ps
T51 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2426080969 Jul 27 04:50:17 PM PDT 24 Jul 27 04:52:57 PM PDT 24 2138034861 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1775829185 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:26 PM PDT 24 319511082 ps
T60 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1853690145 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:51 PM PDT 24 691664917 ps
T371 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.110578433 Jul 27 04:50:50 PM PDT 24 Jul 27 04:51:02 PM PDT 24 262656116 ps
T88 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2474069444 Jul 27 04:50:55 PM PDT 24 Jul 27 04:51:04 PM PDT 24 339059915 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2113122367 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:44 PM PDT 24 691816701 ps
T61 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2758777760 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:33 PM PDT 24 168438213 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.270784797 Jul 27 04:50:32 PM PDT 24 Jul 27 04:51:08 PM PDT 24 2543410266 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2882541125 Jul 27 04:51:02 PM PDT 24 Jul 27 04:51:10 PM PDT 24 1103695146 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1118024343 Jul 27 04:51:16 PM PDT 24 Jul 27 04:51:24 PM PDT 24 185186359 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2969414816 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:45 PM PDT 24 249156795 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.617244397 Jul 27 04:51:09 PM PDT 24 Jul 27 04:51:24 PM PDT 24 2053867129 ps
T373 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1331300115 Jul 27 04:50:58 PM PDT 24 Jul 27 04:51:06 PM PDT 24 358050570 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2590903732 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:51 PM PDT 24 486583367 ps
T52 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1369872427 Jul 27 04:50:32 PM PDT 24 Jul 27 04:51:55 PM PDT 24 381931257 ps
T53 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2808369923 Jul 27 04:51:03 PM PDT 24 Jul 27 04:53:38 PM PDT 24 1589323728 ps
T65 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3875722875 Jul 27 04:50:59 PM PDT 24 Jul 27 04:51:07 PM PDT 24 751255382 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1742297026 Jul 27 04:51:04 PM PDT 24 Jul 27 04:51:14 PM PDT 24 286237028 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1457011367 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:26 PM PDT 24 167366525 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2310350882 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:34 PM PDT 24 506162803 ps
T98 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4157142172 Jul 27 04:51:05 PM PDT 24 Jul 27 04:53:42 PM PDT 24 445329272 ps
T66 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2347443907 Jul 27 04:51:04 PM PDT 24 Jul 27 04:51:16 PM PDT 24 189336260 ps
T376 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1733721804 Jul 27 04:50:54 PM PDT 24 Jul 27 04:51:03 PM PDT 24 701431561 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.906312031 Jul 27 04:50:36 PM PDT 24 Jul 27 04:50:47 PM PDT 24 1086306729 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1077906121 Jul 27 04:50:56 PM PDT 24 Jul 27 04:51:09 PM PDT 24 661029450 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1496937219 Jul 27 04:50:41 PM PDT 24 Jul 27 04:50:51 PM PDT 24 477792766 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4236327566 Jul 27 04:51:07 PM PDT 24 Jul 27 04:51:17 PM PDT 24 506504443 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3054132216 Jul 27 04:50:55 PM PDT 24 Jul 27 04:51:05 PM PDT 24 358044872 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.804905361 Jul 27 04:50:50 PM PDT 24 Jul 27 04:52:13 PM PDT 24 366185913 ps
T381 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2520349866 Jul 27 04:50:51 PM PDT 24 Jul 27 04:51:01 PM PDT 24 249051456 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.414726680 Jul 27 04:50:33 PM PDT 24 Jul 27 04:50:44 PM PDT 24 385446756 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1595553586 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:48 PM PDT 24 174204946 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3175334669 Jul 27 04:50:48 PM PDT 24 Jul 27 04:50:56 PM PDT 24 174482396 ps
T68 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1735577856 Jul 27 04:50:58 PM PDT 24 Jul 27 04:51:08 PM PDT 24 257989370 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.155809555 Jul 27 04:50:26 PM PDT 24 Jul 27 04:51:32 PM PDT 24 1530984175 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2318994048 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:50 PM PDT 24 953765684 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.477204920 Jul 27 04:51:10 PM PDT 24 Jul 27 04:53:47 PM PDT 24 459337468 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2811199171 Jul 27 04:50:52 PM PDT 24 Jul 27 04:51:03 PM PDT 24 2579929239 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.560782743 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:45 PM PDT 24 262686742 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2455034298 Jul 27 04:50:49 PM PDT 24 Jul 27 04:52:10 PM PDT 24 1360393544 ps
T75 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1376174417 Jul 27 04:50:37 PM PDT 24 Jul 27 04:50:47 PM PDT 24 516612533 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.573465057 Jul 27 04:50:44 PM PDT 24 Jul 27 04:50:52 PM PDT 24 782896891 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.725239651 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:28 PM PDT 24 215333107 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1858599540 Jul 27 04:50:49 PM PDT 24 Jul 27 04:50:59 PM PDT 24 250368586 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3191022487 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:35 PM PDT 24 175983204 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2062062765 Jul 27 04:50:31 PM PDT 24 Jul 27 04:50:41 PM PDT 24 1035331968 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1857903756 Jul 27 04:50:34 PM PDT 24 Jul 27 04:50:46 PM PDT 24 340803961 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2014378974 Jul 27 04:50:48 PM PDT 24 Jul 27 04:51:00 PM PDT 24 670135583 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.468549086 Jul 27 04:50:57 PM PDT 24 Jul 27 04:51:53 PM PDT 24 2104890714 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.710227844 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:37 PM PDT 24 196586099 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.159352539 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:48 PM PDT 24 179637940 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1120189115 Jul 27 04:50:32 PM PDT 24 Jul 27 04:53:08 PM PDT 24 408474498 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1836342231 Jul 27 04:50:33 PM PDT 24 Jul 27 04:50:42 PM PDT 24 258629355 ps
T76 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1899309128 Jul 27 04:51:16 PM PDT 24 Jul 27 04:52:22 PM PDT 24 10143998020 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2109471977 Jul 27 04:50:43 PM PDT 24 Jul 27 04:50:53 PM PDT 24 1237007248 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3746503314 Jul 27 04:50:50 PM PDT 24 Jul 27 04:51:03 PM PDT 24 1036022351 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.350914263 Jul 27 04:51:06 PM PDT 24 Jul 27 04:51:19 PM PDT 24 261631307 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.382324357 Jul 27 04:50:22 PM PDT 24 Jul 27 04:51:18 PM PDT 24 1781985890 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3133712884 Jul 27 04:51:11 PM PDT 24 Jul 27 04:52:32 PM PDT 24 979409272 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.353509893 Jul 27 04:51:10 PM PDT 24 Jul 27 04:51:18 PM PDT 24 1101161479 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2670771782 Jul 27 04:51:17 PM PDT 24 Jul 27 04:51:27 PM PDT 24 498318767 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3226275750 Jul 27 04:50:38 PM PDT 24 Jul 27 04:50:46 PM PDT 24 974892271 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3775944355 Jul 27 04:51:12 PM PDT 24 Jul 27 04:51:25 PM PDT 24 688082995 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3006825995 Jul 27 04:51:22 PM PDT 24 Jul 27 04:51:34 PM PDT 24 528371324 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3353300059 Jul 27 04:50:29 PM PDT 24 Jul 27 04:50:37 PM PDT 24 664495288 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2682671258 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:26 PM PDT 24 1100170145 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3860352425 Jul 27 04:50:31 PM PDT 24 Jul 27 04:50:41 PM PDT 24 989198126 ps
T80 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3885063638 Jul 27 04:50:26 PM PDT 24 Jul 27 04:50:36 PM PDT 24 249946995 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2862091395 Jul 27 04:51:03 PM PDT 24 Jul 27 04:51:23 PM PDT 24 984300351 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3498462634 Jul 27 04:50:39 PM PDT 24 Jul 27 04:50:53 PM PDT 24 1036840864 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2524542316 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:22 PM PDT 24 257977051 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1417289474 Jul 27 04:50:35 PM PDT 24 Jul 27 04:51:11 PM PDT 24 2733331717 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2661654239 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:23 PM PDT 24 1335730305 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4151887938 Jul 27 04:50:57 PM PDT 24 Jul 27 04:53:29 PM PDT 24 2743255900 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2722537361 Jul 27 04:51:08 PM PDT 24 Jul 27 04:51:18 PM PDT 24 1077762821 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1835351813 Jul 27 04:51:38 PM PDT 24 Jul 27 04:51:48 PM PDT 24 990047661 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2190050784 Jul 27 04:51:08 PM PDT 24 Jul 27 04:51:18 PM PDT 24 251882913 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2365695813 Jul 27 04:51:02 PM PDT 24 Jul 27 04:51:10 PM PDT 24 169202315 ps
T416 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2350719160 Jul 27 04:50:37 PM PDT 24 Jul 27 04:50:55 PM PDT 24 259742600 ps
T417 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3824704287 Jul 27 04:51:16 PM PDT 24 Jul 27 04:52:28 PM PDT 24 1620676223 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3622711379 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:36 PM PDT 24 1033475953 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1941190872 Jul 27 04:51:06 PM PDT 24 Jul 27 04:51:50 PM PDT 24 5327312621 ps
T101 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.257832654 Jul 27 04:51:11 PM PDT 24 Jul 27 04:53:44 PM PDT 24 339127347 ps
T419 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.775005719 Jul 27 04:51:07 PM PDT 24 Jul 27 04:51:17 PM PDT 24 1051160330 ps
T420 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1948590866 Jul 27 04:51:05 PM PDT 24 Jul 27 04:51:16 PM PDT 24 2528123562 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4110742627 Jul 27 04:51:21 PM PDT 24 Jul 27 04:51:33 PM PDT 24 1029123829 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.945617417 Jul 27 04:51:05 PM PDT 24 Jul 27 04:52:01 PM PDT 24 5742254866 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2413854118 Jul 27 04:51:13 PM PDT 24 Jul 27 04:52:08 PM PDT 24 1035527335 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.49241769 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:30 PM PDT 24 249433506 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2644117801 Jul 27 04:51:18 PM PDT 24 Jul 27 04:53:51 PM PDT 24 1180642161 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4274515030 Jul 27 04:51:12 PM PDT 24 Jul 27 04:52:16 PM PDT 24 3039962369 ps
T84 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1212033376 Jul 27 04:50:54 PM PDT 24 Jul 27 04:51:59 PM PDT 24 6899850859 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.116194468 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:51 PM PDT 24 345851126 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1964849839 Jul 27 04:50:46 PM PDT 24 Jul 27 04:50:56 PM PDT 24 254806494 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2107959986 Jul 27 04:50:47 PM PDT 24 Jul 27 04:53:20 PM PDT 24 571105317 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3923952514 Jul 27 04:50:45 PM PDT 24 Jul 27 04:50:56 PM PDT 24 182255475 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.943773315 Jul 27 04:51:08 PM PDT 24 Jul 27 04:51:16 PM PDT 24 713760749 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1593738417 Jul 27 04:51:01 PM PDT 24 Jul 27 04:51:09 PM PDT 24 175996934 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1401704568 Jul 27 04:51:21 PM PDT 24 Jul 27 04:51:29 PM PDT 24 2066597230 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.626548990 Jul 27 04:50:43 PM PDT 24 Jul 27 04:52:03 PM PDT 24 231224465 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2408241992 Jul 27 04:51:10 PM PDT 24 Jul 27 04:51:19 PM PDT 24 865766131 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3884921654 Jul 27 04:50:43 PM PDT 24 Jul 27 04:50:57 PM PDT 24 260804434 ps
T110 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.507447870 Jul 27 04:51:14 PM PDT 24 Jul 27 04:53:53 PM PDT 24 1501342808 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.438153218 Jul 27 04:51:02 PM PDT 24 Jul 27 04:51:58 PM PDT 24 4491318467 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2622063968 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:53 PM PDT 24 282528012 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.512109342 Jul 27 04:51:11 PM PDT 24 Jul 27 04:52:17 PM PDT 24 5853495598 ps
T81 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1602316086 Jul 27 04:51:00 PM PDT 24 Jul 27 04:52:06 PM PDT 24 18976341373 ps
T106 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3267573703 Jul 27 04:50:59 PM PDT 24 Jul 27 04:52:24 PM PDT 24 469623248 ps
T436 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1861332946 Jul 27 04:51:06 PM PDT 24 Jul 27 04:52:30 PM PDT 24 358190717 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.855708919 Jul 27 04:51:12 PM PDT 24 Jul 27 04:51:22 PM PDT 24 686008875 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1997365167 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:33 PM PDT 24 184842429 ps
T439 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.555721801 Jul 27 04:51:08 PM PDT 24 Jul 27 04:51:23 PM PDT 24 256884700 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3457569999 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:44 PM PDT 24 361812009 ps
T86 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3390586595 Jul 27 04:50:48 PM PDT 24 Jul 27 04:51:32 PM PDT 24 2246617156 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2027052581 Jul 27 04:50:48 PM PDT 24 Jul 27 04:51:55 PM PDT 24 30563780600 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3387020712 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:50 PM PDT 24 986690306 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.165022612 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:39 PM PDT 24 255887780 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1764107488 Jul 27 04:50:40 PM PDT 24 Jul 27 04:50:57 PM PDT 24 253192962 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.875302128 Jul 27 04:50:58 PM PDT 24 Jul 27 04:51:11 PM PDT 24 176365430 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2630552638 Jul 27 04:50:43 PM PDT 24 Jul 27 04:51:39 PM PDT 24 1058356203 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.909130605 Jul 27 04:51:07 PM PDT 24 Jul 27 04:51:19 PM PDT 24 171796768 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.5889160 Jul 27 04:51:09 PM PDT 24 Jul 27 04:51:17 PM PDT 24 326531255 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3970845916 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:26 PM PDT 24 527188372 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3784529316 Jul 27 04:51:06 PM PDT 24 Jul 27 04:51:21 PM PDT 24 253193294 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1451742744 Jul 27 04:51:13 PM PDT 24 Jul 27 04:51:23 PM PDT 24 249296265 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3084376059 Jul 27 04:50:59 PM PDT 24 Jul 27 04:51:11 PM PDT 24 790103531 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3159957227 Jul 27 04:51:04 PM PDT 24 Jul 27 04:51:18 PM PDT 24 504948453 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1313727577 Jul 27 04:51:11 PM PDT 24 Jul 27 04:51:21 PM PDT 24 520566937 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1545673327 Jul 27 04:50:36 PM PDT 24 Jul 27 04:51:43 PM PDT 24 6085495809 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2681778689 Jul 27 04:51:14 PM PDT 24 Jul 27 04:51:26 PM PDT 24 508285634 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3403256131 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:51 PM PDT 24 2754064920 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.980512819 Jul 27 04:50:32 PM PDT 24 Jul 27 04:51:53 PM PDT 24 551411175 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4227560069 Jul 27 04:50:29 PM PDT 24 Jul 27 04:50:46 PM PDT 24 265545056 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1476009744 Jul 27 04:51:02 PM PDT 24 Jul 27 04:51:12 PM PDT 24 1301838110 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2503798153 Jul 27 04:50:25 PM PDT 24 Jul 27 04:53:00 PM PDT 24 380801287 ps
T109 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.138440777 Jul 27 04:51:09 PM PDT 24 Jul 27 04:53:52 PM PDT 24 470782509 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4272555295 Jul 27 04:50:26 PM PDT 24 Jul 27 04:50:34 PM PDT 24 174923762 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3641958115 Jul 27 04:51:10 PM PDT 24 Jul 27 04:51:18 PM PDT 24 665545766 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3160470453 Jul 27 04:50:59 PM PDT 24 Jul 27 04:51:10 PM PDT 24 690984477 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2813998475 Jul 27 04:50:22 PM PDT 24 Jul 27 04:50:31 PM PDT 24 873164119 ps
T464 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3926620917 Jul 27 04:51:01 PM PDT 24 Jul 27 04:51:09 PM PDT 24 176175520 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1375574917 Jul 27 04:50:36 PM PDT 24 Jul 27 04:50:45 PM PDT 24 347719743 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1048764039 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:43 PM PDT 24 167509632 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2757837261 Jul 27 04:51:02 PM PDT 24 Jul 27 04:51:16 PM PDT 24 253393959 ps

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.128670333
Short name T3
Test name
Test status
Simulation time 7942051743 ps
CPU time 349.86 seconds
Started Jul 27 04:50:52 PM PDT 24
Finished Jul 27 04:56:42 PM PDT 24
Peak memory 239376 kb
Host smart-42f6d599-8ef8-4be6-b4e6-dd221c8dac90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128670333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.128670333
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.237965526
Short name T11
Test name
Test status
Simulation time 39452134130 ps
CPU time 1552.21 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 05:17:02 PM PDT 24
Peak memory 244392 kb
Host smart-2c73ba93-5120-4c2a-b8d6-47e083a317aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237965526 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.237965526
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3393817729
Short name T12
Test name
Test status
Simulation time 101032876283 ps
CPU time 2019.72 seconds
Started Jul 27 04:51:31 PM PDT 24
Finished Jul 27 05:25:11 PM PDT 24
Peak memory 250684 kb
Host smart-9a431e5b-c436-482a-8bc5-845acd88c872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393817729 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3393817729
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2426080969
Short name T51
Test name
Test status
Simulation time 2138034861 ps
CPU time 158.79 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 213904 kb
Host smart-dcd062e2-3970-43aa-9757-420aed41339b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426080969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2426080969
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4108063093
Short name T119
Test name
Test status
Simulation time 19817840039 ps
CPU time 278.84 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:55:17 PM PDT 24
Peak memory 234368 kb
Host smart-099cfbb9-b22e-42fc-b026-614f58d36784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108063093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4108063093
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4267959732
Short name T35
Test name
Test status
Simulation time 10802042942 ps
CPU time 199.76 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:54:30 PM PDT 24
Peak memory 239696 kb
Host smart-619f902d-4eb2-499b-9c51-d98de2294c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267959732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4267959732
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2885633353
Short name T6
Test name
Test status
Simulation time 250524803 ps
CPU time 10.28 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:50:49 PM PDT 24
Peak memory 218732 kb
Host smart-829777bd-65c1-4f52-bd23-8a2a80f32b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885633353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2885633353
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3795207810
Short name T20
Test name
Test status
Simulation time 2383508150 ps
CPU time 243.1 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:54:30 PM PDT 24
Peak memory 239336 kb
Host smart-012ff7ed-a686-412b-a40a-ba9a6e7fc445
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795207810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3795207810
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.270784797
Short name T62
Test name
Test status
Simulation time 2543410266 ps
CPU time 35.88 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:51:08 PM PDT 24
Peak memory 213916 kb
Host smart-6cc98a1d-cb53-48a9-b0a8-1b52f5f64ed1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270784797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.270784797
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.138440777
Short name T109
Test name
Test status
Simulation time 470782509 ps
CPU time 157.76 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 214020 kb
Host smart-c1ce86a7-24b3-4b50-8fcc-9c210ab1602d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138440777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.138440777
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3919808968
Short name T27
Test name
Test status
Simulation time 10938739144 ps
CPU time 32.55 seconds
Started Jul 27 04:51:31 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 219824 kb
Host smart-ed9508c3-ee89-4db8-9a55-0a09cf3a982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919808968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3919808968
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1168500206
Short name T2
Test name
Test status
Simulation time 7886227833 ps
CPU time 50.06 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 220872 kb
Host smart-92c32a6b-2330-4ee0-8746-fb9c07276fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168500206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1168500206
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1326373625
Short name T222
Test name
Test status
Simulation time 349894547 ps
CPU time 18.95 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:51:04 PM PDT 24
Peak memory 219756 kb
Host smart-be80b605-f711-45b0-a91c-57968ec90835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326373625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1326373625
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.155809555
Short name T73
Test name
Test status
Simulation time 1530984175 ps
CPU time 65.68 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 218632 kb
Host smart-093ab695-88fb-4813-9412-f638fce3c70a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155809555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.155809555
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.507447870
Short name T110
Test name
Test status
Simulation time 1501342808 ps
CPU time 159.21 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 213976 kb
Host smart-1142dca6-ee72-4cd2-89ab-c8e55f201dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507447870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.507447870
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2097438191
Short name T183
Test name
Test status
Simulation time 560602514 ps
CPU time 24.16 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:30 PM PDT 24
Peak memory 218452 kb
Host smart-37d425f9-affa-4221-a283-d96040b09f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097438191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2097438191
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1496937219
Short name T67
Test name
Test status
Simulation time 477792766 ps
CPU time 9.66 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 211056 kb
Host smart-6cda7fd9-cac1-4e19-8e8d-1a63e144f793
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496937219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1496937219
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3860352425
Short name T406
Test name
Test status
Simulation time 989198126 ps
CPU time 9.71 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 04:50:41 PM PDT 24
Peak memory 210456 kb
Host smart-e5655c36-e7a9-4a41-bf6f-d3233109502e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860352425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3860352425
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.725239651
Short name T388
Test name
Test status
Simulation time 215333107 ps
CPU time 11.71 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:28 PM PDT 24
Peak memory 211828 kb
Host smart-bab9316d-247f-4bf8-a6cf-16c75ee95483
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725239651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.725239651
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1997365167
Short name T438
Test name
Test status
Simulation time 184842429 ps
CPU time 8.73 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 215632 kb
Host smart-f5aaaa5a-1c19-41c0-b2b8-e195cac0e5d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997365167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1997365167
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1457011367
Short name T90
Test name
Test status
Simulation time 167366525 ps
CPU time 8.16 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 211156 kb
Host smart-945ba193-64c9-4094-b3d0-7a1941e7c093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457011367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1457011367
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.49241769
Short name T424
Test name
Test status
Simulation time 249433506 ps
CPU time 9.71 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:30 PM PDT 24
Peak memory 210288 kb
Host smart-26024fe4-233f-4e2e-a2c8-b78eb1bf7af1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49241769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_
mem_partial_access.49241769
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3353300059
Short name T404
Test name
Test status
Simulation time 664495288 ps
CPU time 7.95 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:37 PM PDT 24
Peak memory 210328 kb
Host smart-d07c2bee-d99b-4b2c-a431-97b88e0ed892
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353300059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3353300059
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3403256131
Short name T456
Test name
Test status
Simulation time 2754064920 ps
CPU time 38.28 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 213644 kb
Host smart-63fc4534-4e78-4784-93cb-e6cc463d10b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403256131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3403256131
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1775829185
Short name T55
Test name
Test status
Simulation time 319511082 ps
CPU time 8.15 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 211556 kb
Host smart-ba42e492-5c79-4ce0-b748-69cf1bf7c582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775829185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1775829185
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3884921654
Short name T433
Test name
Test status
Simulation time 260804434 ps
CPU time 14.04 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 218372 kb
Host smart-5da30afe-3c30-46c1-9a6e-b8e67bb83f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884921654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3884921654
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2318994048
Short name T74
Test name
Test status
Simulation time 953765684 ps
CPU time 9.82 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:50 PM PDT 24
Peak memory 210456 kb
Host smart-adfb331d-2871-4ded-95f2-c7f1b412a9d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318994048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2318994048
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2310350882
Short name T375
Test name
Test status
Simulation time 506162803 ps
CPU time 9.91 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 210436 kb
Host smart-1cc7fa57-962e-4597-ad66-50ca12c9995b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310350882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2310350882
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4227560069
Short name T458
Test name
Test status
Simulation time 265545056 ps
CPU time 16.89 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:46 PM PDT 24
Peak memory 211560 kb
Host smart-0266729c-6a49-4005-877e-fd4dbcdf67fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227560069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4227560069
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.710227844
Short name T394
Test name
Test status
Simulation time 196586099 ps
CPU time 10.27 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:37 PM PDT 24
Peak memory 217640 kb
Host smart-c91b84ff-4c38-4264-b518-e8a98c63a1dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710227844 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.710227844
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1595553586
Short name T383
Test name
Test status
Simulation time 174204946 ps
CPU time 8.12 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:48 PM PDT 24
Peak memory 210408 kb
Host smart-1bae3941-f76b-4c52-9fda-65cf63cb28af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595553586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1595553586
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3191022487
Short name T390
Test name
Test status
Simulation time 175983204 ps
CPU time 7.82 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 210276 kb
Host smart-ee910522-abd0-4788-9cea-d74508762c45
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191022487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3191022487
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2813998475
Short name T463
Test name
Test status
Simulation time 873164119 ps
CPU time 8.25 seconds
Started Jul 27 04:50:22 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 210296 kb
Host smart-2d8a7d19-ac6e-4464-9537-04ad3a0514d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813998475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2813998475
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1417289474
Short name T410
Test name
Test status
Simulation time 2733331717 ps
CPU time 36.25 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:51:11 PM PDT 24
Peak memory 213712 kb
Host smart-4c196989-3742-46d6-b258-61e75e7eff9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417289474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1417289474
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2969414816
Short name T63
Test name
Test status
Simulation time 249156795 ps
CPU time 9.87 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:45 PM PDT 24
Peak memory 211472 kb
Host smart-e67224b6-4cb9-4762-8953-166b8f5e3adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969414816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2969414816
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.414726680
Short name T382
Test name
Test status
Simulation time 385446756 ps
CPU time 10.89 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 217084 kb
Host smart-68363dcd-969b-4975-af71-27745bf9e22b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414726680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.414726680
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2503798153
Short name T105
Test name
Test status
Simulation time 380801287 ps
CPU time 154.79 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 214000 kb
Host smart-5660620c-1042-4190-9ee7-94d1f4d5d000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503798153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2503798153
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3054132216
Short name T380
Test name
Test status
Simulation time 358044872 ps
CPU time 10.28 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 04:51:05 PM PDT 24
Peak memory 215172 kb
Host smart-d9bc7f3f-90a4-41bc-97b8-9bada8fc2dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054132216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3054132216
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4236327566
Short name T379
Test name
Test status
Simulation time 506504443 ps
CPU time 9.83 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:17 PM PDT 24
Peak memory 210416 kb
Host smart-bf11cdbe-46f0-44b3-bd05-978c1c3804ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236327566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4236327566
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.438153218
Short name T434
Test name
Test status
Simulation time 4491318467 ps
CPU time 55.64 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:58 PM PDT 24
Peak memory 218780 kb
Host smart-c3fcdbaf-dc95-4883-af5a-ff14660d35c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438153218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.438153218
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1735577856
Short name T68
Test name
Test status
Simulation time 257989370 ps
CPU time 9.85 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:08 PM PDT 24
Peak memory 211108 kb
Host smart-7e49749f-bce3-413d-a9ce-c05ae0ae229a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735577856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1735577856
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.110578433
Short name T371
Test name
Test status
Simulation time 262656116 ps
CPU time 12.67 seconds
Started Jul 27 04:50:50 PM PDT 24
Finished Jul 27 04:51:02 PM PDT 24
Peak memory 216756 kb
Host smart-0a23c3b7-ecff-4137-8a65-28741c886d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110578433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.110578433
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2107959986
Short name T104
Test name
Test status
Simulation time 571105317 ps
CPU time 153.11 seconds
Started Jul 27 04:50:47 PM PDT 24
Finished Jul 27 04:53:20 PM PDT 24
Peak memory 214088 kb
Host smart-1f50e405-875d-4a8d-8c9c-d81ca8946ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107959986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2107959986
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2811199171
Short name T385
Test name
Test status
Simulation time 2579929239 ps
CPU time 10.93 seconds
Started Jul 27 04:50:52 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 216960 kb
Host smart-cb36e2ad-798e-4224-acb6-a0c7b7262c51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811199171 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2811199171
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3875722875
Short name T65
Test name
Test status
Simulation time 751255382 ps
CPU time 7.97 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:07 PM PDT 24
Peak memory 210356 kb
Host smart-0d5d40f1-be80-4ceb-af86-d604a2c7f81e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875722875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3875722875
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.468549086
Short name T97
Test name
Test status
Simulation time 2104890714 ps
CPU time 55.48 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:53 PM PDT 24
Peak memory 215172 kb
Host smart-bdd06771-d286-4669-a36d-09698c4a6b07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468549086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.468549086
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2190050784
Short name T414
Test name
Test status
Simulation time 251882913 ps
CPU time 9.82 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 210744 kb
Host smart-e6ed3efb-cb9a-487a-b4bb-45d6b5660a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190050784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2190050784
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2757837261
Short name T466
Test name
Test status
Simulation time 253393959 ps
CPU time 13.36 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 218424 kb
Host smart-f692924d-37b2-4500-8cb1-5969e55d8cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757837261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2757837261
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1861332946
Short name T436
Test name
Test status
Simulation time 358190717 ps
CPU time 83.93 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:52:30 PM PDT 24
Peak memory 214828 kb
Host smart-71e020b0-b917-4efe-a3ad-4105e8fecc62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861332946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1861332946
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1733721804
Short name T376
Test name
Test status
Simulation time 701431561 ps
CPU time 8.76 seconds
Started Jul 27 04:50:54 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 215196 kb
Host smart-e745dd19-3ec7-4596-ab94-361e700c2ccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733721804 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1733721804
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1593738417
Short name T78
Test name
Test status
Simulation time 175996934 ps
CPU time 8.04 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 210628 kb
Host smart-2a6883c8-3ef3-4efe-9b7c-87db00d59cb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593738417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1593738417
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1212033376
Short name T84
Test name
Test status
Simulation time 6899850859 ps
CPU time 64.31 seconds
Started Jul 27 04:50:54 PM PDT 24
Finished Jul 27 04:51:59 PM PDT 24
Peak memory 218816 kb
Host smart-08c953d8-b0f8-4817-a657-e4bc048a8500
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212033376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1212033376
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.617244397
Short name T64
Test name
Test status
Simulation time 2053867129 ps
CPU time 14.93 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:24 PM PDT 24
Peak memory 211216 kb
Host smart-e9b76660-1d2a-4499-852a-f3dfec2fc6ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617244397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.617244397
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.875302128
Short name T444
Test name
Test status
Simulation time 176365430 ps
CPU time 13.16 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:11 PM PDT 24
Peak memory 218348 kb
Host smart-8203dfb9-5294-4c01-8fbe-5bd558f1cc40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875302128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.875302128
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4157142172
Short name T98
Test name
Test status
Simulation time 445329272 ps
CPU time 156.2 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:53:42 PM PDT 24
Peak memory 214180 kb
Host smart-11c2db04-5b62-42b1-a017-23c6a6fa65e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157142172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4157142172
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2661654239
Short name T411
Test name
Test status
Simulation time 1335730305 ps
CPU time 9.39 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 217180 kb
Host smart-32832eb2-c5d6-4c1e-b3d1-467968b367ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661654239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2661654239
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3926620917
Short name T464
Test name
Test status
Simulation time 176175520 ps
CPU time 8.12 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 210824 kb
Host smart-c6c282ea-bcb6-482c-b0b0-77a7f8114b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926620917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3926620917
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2413854118
Short name T423
Test name
Test status
Simulation time 1035527335 ps
CPU time 54.97 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 213996 kb
Host smart-037ac7a2-2d65-41bb-b1c7-b2854cf2dd54
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413854118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2413854118
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1451742744
Short name T450
Test name
Test status
Simulation time 249296265 ps
CPU time 9.74 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 211612 kb
Host smart-f19a8858-1520-4ece-8140-c9bdb7c16294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451742744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1451742744
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3159957227
Short name T452
Test name
Test status
Simulation time 504948453 ps
CPU time 13.94 seconds
Started Jul 27 04:51:04 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 217332 kb
Host smart-8a3f85c2-b86f-4062-b84a-6ce817a236a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159957227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3159957227
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3267573703
Short name T106
Test name
Test status
Simulation time 469623248 ps
CPU time 84.37 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 213680 kb
Host smart-215020ae-fca6-4193-8fa9-470a5df4c3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267573703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3267573703
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1476009744
Short name T459
Test name
Test status
Simulation time 1301838110 ps
CPU time 9.69 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:12 PM PDT 24
Peak memory 217392 kb
Host smart-093a0faa-ca05-4f98-8763-12d6a73e9aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476009744 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1476009744
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3775944355
Short name T402
Test name
Test status
Simulation time 688082995 ps
CPU time 8.16 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:25 PM PDT 24
Peak memory 210968 kb
Host smart-0cf3dccd-dfa4-40f8-ae78-17397ca37332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775944355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3775944355
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4274515030
Short name T426
Test name
Test status
Simulation time 3039962369 ps
CPU time 63.76 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 218756 kb
Host smart-3e6d3eee-4f3a-4c6d-9133-d5c8c0645537
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274515030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4274515030
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1742297026
Short name T89
Test name
Test status
Simulation time 286237028 ps
CPU time 9.87 seconds
Started Jul 27 04:51:04 PM PDT 24
Finished Jul 27 04:51:14 PM PDT 24
Peak memory 211104 kb
Host smart-11320f40-6a49-49e4-9b58-1f5dbf004906
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742297026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1742297026
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.350914263
Short name T399
Test name
Test status
Simulation time 261631307 ps
CPU time 13.37 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 217136 kb
Host smart-243a31d8-cd39-46eb-b8bd-9127008740b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350914263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.350914263
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2808369923
Short name T53
Test name
Test status
Simulation time 1589323728 ps
CPU time 154.85 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 213920 kb
Host smart-e5f1bfa2-b5c1-489a-bc72-4f3fffe3a311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808369923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2808369923
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.943773315
Short name T430
Test name
Test status
Simulation time 713760749 ps
CPU time 8.52 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 214524 kb
Host smart-a73941b1-ba38-4852-b292-380f5baad9da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943773315 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.943773315
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.5889160
Short name T447
Test name
Test status
Simulation time 326531255 ps
CPU time 8.31 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:17 PM PDT 24
Peak memory 210624 kb
Host smart-0278dd65-e493-4743-bb75-ea97bbfff374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5889160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.5889160
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1602316086
Short name T81
Test name
Test status
Simulation time 18976341373 ps
CPU time 65.06 seconds
Started Jul 27 04:51:00 PM PDT 24
Finished Jul 27 04:52:06 PM PDT 24
Peak memory 215340 kb
Host smart-9480d742-07dd-46ff-9c0c-7a9b4eee0633
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602316086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1602316086
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.855708919
Short name T437
Test name
Test status
Simulation time 686008875 ps
CPU time 9.99 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:22 PM PDT 24
Peak memory 211364 kb
Host smart-58f89cf9-1ae4-4bfe-a084-1a4e08cac70c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855708919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.855708919
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3970845916
Short name T448
Test name
Test status
Simulation time 527188372 ps
CPU time 12.62 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:26 PM PDT 24
Peak memory 217440 kb
Host smart-48396d71-4ebe-4dff-a4fb-cc6365bf774c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970845916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3970845916
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.477204920
Short name T99
Test name
Test status
Simulation time 459337468 ps
CPU time 156.12 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 213764 kb
Host smart-d4e192c9-0373-4150-8c48-b1ba94caa175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477204920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.477204920
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1118024343
Short name T372
Test name
Test status
Simulation time 185186359 ps
CPU time 8.54 seconds
Started Jul 27 04:51:16 PM PDT 24
Finished Jul 27 04:51:24 PM PDT 24
Peak memory 214820 kb
Host smart-aa17c7fb-d633-454d-860d-7d65e5525419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118024343 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1118024343
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1401704568
Short name T431
Test name
Test status
Simulation time 2066597230 ps
CPU time 8.1 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 211196 kb
Host smart-944bf979-f53d-4899-a0c2-656cd0e017a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401704568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1401704568
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1899309128
Short name T76
Test name
Test status
Simulation time 10143998020 ps
CPU time 65.83 seconds
Started Jul 27 04:51:16 PM PDT 24
Finished Jul 27 04:52:22 PM PDT 24
Peak memory 218720 kb
Host smart-1c015f35-808d-406b-8ff1-c7a70e4d620c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899309128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1899309128
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1313727577
Short name T453
Test name
Test status
Simulation time 520566937 ps
CPU time 9.97 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 211444 kb
Host smart-054e3f61-d999-4db6-bd55-4c89816d76c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313727577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1313727577
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3784529316
Short name T449
Test name
Test status
Simulation time 253193294 ps
CPU time 14.68 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 218476 kb
Host smart-b6e866eb-b3d0-4a56-b328-5973ae1ce182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784529316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3784529316
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2408241992
Short name T432
Test name
Test status
Simulation time 865766131 ps
CPU time 8.59 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 215224 kb
Host smart-064d7be9-03c8-457f-bc09-f5097d667808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408241992 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2408241992
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.353509893
Short name T79
Test name
Test status
Simulation time 1101161479 ps
CPU time 8.05 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 210888 kb
Host smart-362ffcc3-73c0-4fdc-b369-6640989bf4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353509893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.353509893
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1941190872
Short name T418
Test name
Test status
Simulation time 5327312621 ps
CPU time 43.79 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:50 PM PDT 24
Peak memory 211672 kb
Host smart-a6324d8b-7f42-4a7b-9b8c-83acb171a39e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941190872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1941190872
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2347443907
Short name T66
Test name
Test status
Simulation time 189336260 ps
CPU time 11.99 seconds
Started Jul 27 04:51:04 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 212324 kb
Host smart-abf08775-3a1c-470f-bb5f-8f024fb26c90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347443907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2347443907
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3084376059
Short name T451
Test name
Test status
Simulation time 790103531 ps
CPU time 11.17 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:11 PM PDT 24
Peak memory 218340 kb
Host smart-76d12ad4-1b3b-4576-ad3b-f24b0418d052
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084376059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3084376059
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2644117801
Short name T425
Test name
Test status
Simulation time 1180642161 ps
CPU time 153.39 seconds
Started Jul 27 04:51:18 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 213924 kb
Host smart-99219bc7-17e8-4d4e-bfc1-3b12deea29bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644117801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2644117801
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1331300115
Short name T373
Test name
Test status
Simulation time 358050570 ps
CPU time 8.67 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:06 PM PDT 24
Peak memory 215288 kb
Host smart-8e1b1d48-8545-4980-b436-b1cdca7e2df8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331300115 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1331300115
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2524542316
Short name T409
Test name
Test status
Simulation time 257977051 ps
CPU time 9.68 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:22 PM PDT 24
Peak memory 210340 kb
Host smart-067ad920-b0b2-485f-8e90-01f0fe92dd08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524542316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2524542316
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.945617417
Short name T422
Test name
Test status
Simulation time 5742254866 ps
CPU time 55.28 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:52:01 PM PDT 24
Peak memory 215732 kb
Host smart-b898e1fb-d58a-4152-a1b5-01d6e1d329cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945617417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.945617417
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2722537361
Short name T412
Test name
Test status
Simulation time 1077762821 ps
CPU time 9.75 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 211264 kb
Host smart-e3539f6d-7a63-47a8-9f52-1aeff8b0a1df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722537361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2722537361
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2681778689
Short name T455
Test name
Test status
Simulation time 508285634 ps
CPU time 12.06 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 04:51:26 PM PDT 24
Peak memory 217160 kb
Host smart-0cb1ebab-d46f-4c67-99dc-4894cae4e431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681778689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2681778689
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3133712884
Short name T107
Test name
Test status
Simulation time 979409272 ps
CPU time 80.67 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 213620 kb
Host smart-d375c19a-e441-4f33-bfab-b1b560edc044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133712884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3133712884
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3006825995
Short name T403
Test name
Test status
Simulation time 528371324 ps
CPU time 11.35 seconds
Started Jul 27 04:51:22 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 217628 kb
Host smart-fb8e6147-2b28-408e-ae31-f2f9343ef504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006825995 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3006825995
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2670771782
Short name T400
Test name
Test status
Simulation time 498318767 ps
CPU time 10 seconds
Started Jul 27 04:51:17 PM PDT 24
Finished Jul 27 04:51:27 PM PDT 24
Peak memory 210384 kb
Host smart-76fb2842-3803-409d-9c5a-ce8dba389c88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670771782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2670771782
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.512109342
Short name T85
Test name
Test status
Simulation time 5853495598 ps
CPU time 66.02 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:52:17 PM PDT 24
Peak memory 214920 kb
Host smart-3c0b818c-1bb8-4552-979a-00213d21522b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512109342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.512109342
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1835351813
Short name T413
Test name
Test status
Simulation time 990047661 ps
CPU time 9.74 seconds
Started Jul 27 04:51:38 PM PDT 24
Finished Jul 27 04:51:48 PM PDT 24
Peak memory 211324 kb
Host smart-da25c288-50fe-4b6b-bad5-0435d60e042c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835351813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1835351813
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4110742627
Short name T421
Test name
Test status
Simulation time 1029123829 ps
CPU time 12.71 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 217112 kb
Host smart-7172012d-d62e-465b-8566-7256b4b62b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110742627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4110742627
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1376174417
Short name T75
Test name
Test status
Simulation time 516612533 ps
CPU time 9.91 seconds
Started Jul 27 04:50:37 PM PDT 24
Finished Jul 27 04:50:47 PM PDT 24
Peak memory 210752 kb
Host smart-db8ad616-9aff-40e7-b3a8-c2da943194e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376174417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1376174417
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2590903732
Short name T374
Test name
Test status
Simulation time 486583367 ps
CPU time 8.34 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 210444 kb
Host smart-dffeed6a-633c-4360-aa31-136eca55fbb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590903732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2590903732
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3622711379
Short name T83
Test name
Test status
Simulation time 1033475953 ps
CPU time 13.52 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:36 PM PDT 24
Peak memory 211824 kb
Host smart-59f8dc2e-21f2-41ce-9304-47fbb93c20ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622711379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3622711379
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.906312031
Short name T377
Test name
Test status
Simulation time 1086306729 ps
CPU time 10.25 seconds
Started Jul 27 04:50:36 PM PDT 24
Finished Jul 27 04:50:47 PM PDT 24
Peak memory 215420 kb
Host smart-f4df4834-7d1a-456e-a311-2f3f5b91776a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906312031 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.906312031
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1375574917
Short name T82
Test name
Test status
Simulation time 347719743 ps
CPU time 8.35 seconds
Started Jul 27 04:50:36 PM PDT 24
Finished Jul 27 04:50:45 PM PDT 24
Peak memory 210512 kb
Host smart-16fc1179-c786-4d92-b5b1-5c9370a342ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375574917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1375574917
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1836342231
Short name T396
Test name
Test status
Simulation time 258629355 ps
CPU time 9.57 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 210324 kb
Host smart-2f07fd25-d5ae-46f7-926b-0b532dc9e28e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836342231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1836342231
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4272555295
Short name T460
Test name
Test status
Simulation time 174923762 ps
CPU time 8.17 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 210304 kb
Host smart-adcba846-b094-42f6-b768-feeb4b415f2d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272555295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4272555295
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.382324357
Short name T77
Test name
Test status
Simulation time 1781985890 ps
CPU time 55.91 seconds
Started Jul 27 04:50:22 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 214988 kb
Host smart-91c6658d-dfdc-4f83-886f-af7caa8ba53e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382324357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.382324357
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3923952514
Short name T429
Test name
Test status
Simulation time 182255475 ps
CPU time 11.75 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 212564 kb
Host smart-118debc7-2ae6-44ee-8ca0-0562540b77fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923952514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3923952514
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3498462634
Short name T408
Test name
Test status
Simulation time 1036840864 ps
CPU time 13.42 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:50:53 PM PDT 24
Peak memory 218188 kb
Host smart-cd2f7aa5-2225-43a3-bf3e-770d55595776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498462634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3498462634
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1120189115
Short name T100
Test name
Test status
Simulation time 408474498 ps
CPU time 155.39 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 213880 kb
Host smart-d68e0cae-738d-4b9a-b13b-c54844c0bad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120189115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1120189115
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2758777760
Short name T61
Test name
Test status
Simulation time 168438213 ps
CPU time 8.14 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 209508 kb
Host smart-f1135b64-435f-48a8-abde-6513d7185470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758777760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2758777760
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2109471977
Short name T397
Test name
Test status
Simulation time 1237007248 ps
CPU time 9.64 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:50:53 PM PDT 24
Peak memory 210412 kb
Host smart-0d053080-9df1-4955-be59-98483ed1fb4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109471977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2109471977
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1764107488
Short name T87
Test name
Test status
Simulation time 253192962 ps
CPU time 17.05 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 211880 kb
Host smart-433a2ca7-10a9-491e-bae4-295f7f72ef02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764107488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1764107488
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.560782743
Short name T386
Test name
Test status
Simulation time 262686742 ps
CPU time 9.96 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:45 PM PDT 24
Peak memory 214204 kb
Host smart-6a1563b8-c855-4fcc-9f22-cf6f6229ba4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560782743 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.560782743
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3885063638
Short name T80
Test name
Test status
Simulation time 249946995 ps
CPU time 9.73 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:50:36 PM PDT 24
Peak memory 210588 kb
Host smart-fca2ed6d-2314-4b75-845e-53a72917418f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885063638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3885063638
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2062062765
Short name T391
Test name
Test status
Simulation time 1035331968 ps
CPU time 9.76 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 04:50:41 PM PDT 24
Peak memory 210264 kb
Host smart-54a38755-d5a0-4059-9daf-e1fc93790950
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062062765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2062062765
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2682671258
Short name T405
Test name
Test status
Simulation time 1100170145 ps
CPU time 8.06 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 210276 kb
Host smart-cae78b0c-9a06-492d-80c7-3a5b04d564e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682671258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2682671258
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1048764039
Short name T465
Test name
Test status
Simulation time 167509632 ps
CPU time 7.93 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:43 PM PDT 24
Peak memory 211300 kb
Host smart-40d3daf6-9153-44f0-a2d3-7f04e77e0ee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048764039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1048764039
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.165022612
Short name T443
Test name
Test status
Simulation time 255887780 ps
CPU time 14.64 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:39 PM PDT 24
Peak memory 217552 kb
Host smart-a5d13abf-7ca8-48f1-801a-cf5475bb5bff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165022612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.165022612
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.980512819
Short name T457
Test name
Test status
Simulation time 551411175 ps
CPU time 80.29 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:51:53 PM PDT 24
Peak memory 213624 kb
Host smart-127a26e3-442b-45dd-b795-f0e02c50858d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980512819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.980512819
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2113122367
Short name T91
Test name
Test status
Simulation time 691816701 ps
CPU time 8.22 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 210548 kb
Host smart-16c09b85-15db-40a0-8438-260977e467d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113122367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2113122367
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3387020712
Short name T442
Test name
Test status
Simulation time 986690306 ps
CPU time 9.86 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:50 PM PDT 24
Peak memory 210408 kb
Host smart-939c98ad-304f-4ea4-b4ba-d7a2ee0cbaad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387020712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3387020712
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2014378974
Short name T393
Test name
Test status
Simulation time 670135583 ps
CPU time 11.88 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:00 PM PDT 24
Peak memory 211908 kb
Host smart-9d1dec98-fb1d-4562-861c-860e56a4da11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014378974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2014378974
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2622063968
Short name T435
Test name
Test status
Simulation time 282528012 ps
CPU time 9.96 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:53 PM PDT 24
Peak memory 213400 kb
Host smart-ca25e4c5-3e15-44d8-9bd3-07ab2d78bdc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622063968 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2622063968
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1858599540
Short name T389
Test name
Test status
Simulation time 250368586 ps
CPU time 9.67 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:50:59 PM PDT 24
Peak memory 210748 kb
Host smart-ac86b107-4baf-4eca-aeed-fd121fe602bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858599540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1858599540
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3457569999
Short name T440
Test name
Test status
Simulation time 361812009 ps
CPU time 9.79 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 210312 kb
Host smart-278fc7a8-f8a5-46b9-8edc-ace84f5adc73
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457569999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3457569999
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3175334669
Short name T384
Test name
Test status
Simulation time 174482396 ps
CPU time 8.04 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 210268 kb
Host smart-35c59c08-616c-479e-bbc7-8fe537c4fba7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175334669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3175334669
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.116194468
Short name T427
Test name
Test status
Simulation time 345851126 ps
CPU time 8.07 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 211144 kb
Host smart-28ead484-f2ce-42da-86d2-7a3df9eb3b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116194468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.116194468
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1077906121
Short name T378
Test name
Test status
Simulation time 661029450 ps
CPU time 12.61 seconds
Started Jul 27 04:50:56 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 217476 kb
Host smart-64ae5dbc-a446-4459-bcc8-1453f2d5ada6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077906121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1077906121
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.626548990
Short name T108
Test name
Test status
Simulation time 231224465 ps
CPU time 79.68 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:52:03 PM PDT 24
Peak memory 212580 kb
Host smart-bdef59f9-cad1-401a-afac-9cd09fa29de5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626548990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.626548990
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.159352539
Short name T395
Test name
Test status
Simulation time 179637940 ps
CPU time 8.48 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:48 PM PDT 24
Peak memory 216096 kb
Host smart-5ba67609-ad56-4373-aa2a-522f9265d0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159352539 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.159352539
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4279135222
Short name T54
Test name
Test status
Simulation time 496329312 ps
CPU time 9.58 seconds
Started Jul 27 04:50:50 PM PDT 24
Finished Jul 27 04:51:00 PM PDT 24
Peak memory 210752 kb
Host smart-ddbbd371-a8c6-45b4-a602-ccc738b2a5e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279135222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4279135222
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1545673327
Short name T454
Test name
Test status
Simulation time 6085495809 ps
CPU time 66.41 seconds
Started Jul 27 04:50:36 PM PDT 24
Finished Jul 27 04:51:43 PM PDT 24
Peak memory 215072 kb
Host smart-7b64ead2-adfd-4da0-b1b3-76a333b6fc3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545673327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1545673327
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3746503314
Short name T398
Test name
Test status
Simulation time 1036022351 ps
CPU time 13.5 seconds
Started Jul 27 04:50:50 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 212264 kb
Host smart-304560a4-d1ac-4db5-b4f1-ad4d00f665f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746503314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3746503314
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2350719160
Short name T416
Test name
Test status
Simulation time 259742600 ps
CPU time 12.87 seconds
Started Jul 27 04:50:37 PM PDT 24
Finished Jul 27 04:50:55 PM PDT 24
Peak memory 216960 kb
Host smart-9e6340b5-0f0b-4b01-943f-9b37cf77850d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350719160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2350719160
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1369872427
Short name T52
Test name
Test status
Simulation time 381931257 ps
CPU time 82.91 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 212224 kb
Host smart-0561a304-10c1-48d0-985a-95c1a19f5fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369872427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1369872427
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1948590866
Short name T420
Test name
Test status
Simulation time 2528123562 ps
CPU time 10.3 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 217432 kb
Host smart-86e36969-5db5-4184-a975-a30e967e8253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948590866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1948590866
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3226275750
Short name T401
Test name
Test status
Simulation time 974892271 ps
CPU time 8.01 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:50:46 PM PDT 24
Peak memory 211116 kb
Host smart-81ef5d53-15d5-435b-a2c6-031c90ed714c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226275750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3226275750
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3390586595
Short name T86
Test name
Test status
Simulation time 2246617156 ps
CPU time 43.73 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 213668 kb
Host smart-477abea2-188f-40b1-bfc7-9e023087736e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390586595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3390586595
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1853690145
Short name T60
Test name
Test status
Simulation time 691664917 ps
CPU time 7.99 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 210996 kb
Host smart-b7e3649e-9f51-47e8-b54b-6033564881f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853690145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1853690145
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1857903756
Short name T392
Test name
Test status
Simulation time 340803961 ps
CPU time 11.37 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:50:46 PM PDT 24
Peak memory 217292 kb
Host smart-937d1b3f-f07f-4159-8f18-419b92283062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857903756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1857903756
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2455034298
Short name T111
Test name
Test status
Simulation time 1360393544 ps
CPU time 80.64 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 213552 kb
Host smart-3b24df04-e562-4baa-a044-b9cfbe9acffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455034298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2455034298
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.573465057
Short name T387
Test name
Test status
Simulation time 782896891 ps
CPU time 8.47 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 214884 kb
Host smart-d2024e2c-1b90-49e1-99d6-bced548d054b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573465057 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.573465057
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2882541125
Short name T92
Test name
Test status
Simulation time 1103695146 ps
CPU time 8.13 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:10 PM PDT 24
Peak memory 210600 kb
Host smart-aa8e4fcf-ae5b-4d6d-bdad-cb84fc45d95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882541125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2882541125
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2630552638
Short name T445
Test name
Test status
Simulation time 1058356203 ps
CPU time 55.81 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:51:39 PM PDT 24
Peak memory 218796 kb
Host smart-30d7b7b1-8587-4d92-8fb1-301f525fe0fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630552638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2630552638
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2520349866
Short name T381
Test name
Test status
Simulation time 249051456 ps
CPU time 9.88 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:51:01 PM PDT 24
Peak memory 211096 kb
Host smart-8f5f3910-5a69-4719-9ef6-3b8a34ad6eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520349866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2520349866
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2862091395
Short name T407
Test name
Test status
Simulation time 984300351 ps
CPU time 20.16 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 218528 kb
Host smart-fb70f9c3-70bd-41e0-b395-eab6c6620bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862091395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2862091395
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4151887938
Short name T103
Test name
Test status
Simulation time 2743255900 ps
CPU time 151.62 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 214016 kb
Host smart-09090b40-5f5b-4ff4-a04d-9a54e36ea874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151887938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4151887938
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3160470453
Short name T462
Test name
Test status
Simulation time 690984477 ps
CPU time 10.27 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:10 PM PDT 24
Peak memory 215128 kb
Host smart-9e0ab0cd-eadd-436b-85fb-accdf4fdd4b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160470453 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3160470453
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1964849839
Short name T428
Test name
Test status
Simulation time 254806494 ps
CPU time 9.87 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 210812 kb
Host smart-35a7c946-ad34-47d6-85a0-7bf6d09135ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964849839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1964849839
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3824704287
Short name T417
Test name
Test status
Simulation time 1620676223 ps
CPU time 66.49 seconds
Started Jul 27 04:51:16 PM PDT 24
Finished Jul 27 04:52:28 PM PDT 24
Peak memory 218676 kb
Host smart-edbcf4e4-6971-424f-87cb-56f326ed7493
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824704287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3824704287
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2365695813
Short name T415
Test name
Test status
Simulation time 169202315 ps
CPU time 7.99 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:10 PM PDT 24
Peak memory 210836 kb
Host smart-7b9cb97b-6269-4b27-b423-a762a0144102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365695813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2365695813
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.909130605
Short name T446
Test name
Test status
Simulation time 171796768 ps
CPU time 12.16 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 218504 kb
Host smart-69a98cc1-904a-4325-bc78-ceb462fc03b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909130605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.909130605
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.257832654
Short name T101
Test name
Test status
Simulation time 339127347 ps
CPU time 152.99 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 213956 kb
Host smart-67e78762-a426-4f8e-8f9a-016ace6f3d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257832654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.257832654
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.775005719
Short name T419
Test name
Test status
Simulation time 1051160330 ps
CPU time 10.5 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:17 PM PDT 24
Peak memory 216672 kb
Host smart-0216d82b-c301-46bf-8207-1da29680d9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775005719 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.775005719
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2474069444
Short name T88
Test name
Test status
Simulation time 339059915 ps
CPU time 8.16 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 04:51:04 PM PDT 24
Peak memory 210840 kb
Host smart-909f894f-6bd5-41ff-82db-9f7a3f902c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474069444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2474069444
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2027052581
Short name T441
Test name
Test status
Simulation time 30563780600 ps
CPU time 66.22 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 218780 kb
Host smart-d5b7cb78-c3ec-4978-a6f5-68398ac811a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027052581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2027052581
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3641958115
Short name T461
Test name
Test status
Simulation time 665545766 ps
CPU time 8.12 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 210948 kb
Host smart-29e2c532-cbf8-41fa-a5d9-c1fb1ddd9de4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641958115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3641958115
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.555721801
Short name T439
Test name
Test status
Simulation time 256884700 ps
CPU time 14.26 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 218396 kb
Host smart-3d45d2b8-568d-453d-9724-70bcb53dfa25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555721801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.555721801
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.804905361
Short name T102
Test name
Test status
Simulation time 366185913 ps
CPU time 82.81 seconds
Started Jul 27 04:50:50 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 213360 kb
Host smart-223cab80-4668-4500-ab9f-b976445fc574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804905361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.804905361
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4277709575
Short name T115
Test name
Test status
Simulation time 660768811 ps
CPU time 8.4 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:37 PM PDT 24
Peak memory 218708 kb
Host smart-1cc84735-b8b3-430b-9bea-ed3ec9eec0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277709575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4277709575
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4173040803
Short name T316
Test name
Test status
Simulation time 12406335070 ps
CPU time 321.99 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:56:05 PM PDT 24
Peak memory 219888 kb
Host smart-72207519-e1b9-4345-8fdd-84816f40ef4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173040803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4173040803
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3316263351
Short name T173
Test name
Test status
Simulation time 184597219 ps
CPU time 10.75 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 219720 kb
Host smart-5b7e7bf1-c730-4796-960a-4ef9d3d5e0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316263351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3316263351
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3411294967
Short name T163
Test name
Test status
Simulation time 566800746 ps
CPU time 23.98 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:50:58 PM PDT 24
Peak memory 219112 kb
Host smart-4ad02a8a-4bea-439d-baab-8ba332c6964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411294967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3411294967
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4256047149
Short name T308
Test name
Test status
Simulation time 1807225538 ps
CPU time 49.51 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 219656 kb
Host smart-a167a6d0-1ce5-461a-9110-a85ff25c9de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256047149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4256047149
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2990030812
Short name T229
Test name
Test status
Simulation time 16035388349 ps
CPU time 120.63 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 225188 kb
Host smart-ed5a1586-2802-4be7-a64f-42bd2d9a449c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990030812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2990030812
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.591104267
Short name T21
Test name
Test status
Simulation time 343863685 ps
CPU time 19.14 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 219672 kb
Host smart-7d26f85e-2221-4a4b-ba85-0046f8e72775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591104267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.591104267
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1177662776
Short name T367
Test name
Test status
Simulation time 1019203202 ps
CPU time 11.92 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 219920 kb
Host smart-4a62ae14-4c93-4603-b3df-c5ce6b8b41fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177662776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1177662776
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3441029188
Short name T24
Test name
Test status
Simulation time 3015169563 ps
CPU time 238.7 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 237404 kb
Host smart-72966b40-b2bf-4ffb-861d-48412066303b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441029188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3441029188
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1401098515
Short name T117
Test name
Test status
Simulation time 2100037345 ps
CPU time 22.8 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:43 PM PDT 24
Peak memory 218668 kb
Host smart-89e51739-c502-4852-aec0-82b8c61321d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401098515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1401098515
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3097604022
Short name T176
Test name
Test status
Simulation time 5822405510 ps
CPU time 47.3 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 219804 kb
Host smart-35349415-c353-46c4-b50b-ad7e69a105d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097604022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3097604022
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.8051152
Short name T240
Test name
Test status
Simulation time 249368033 ps
CPU time 10.29 seconds
Started Jul 27 04:50:37 PM PDT 24
Finished Jul 27 04:50:47 PM PDT 24
Peak memory 218232 kb
Host smart-e0302e77-9119-4624-9177-672001e194f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8051152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.8051152
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3016545157
Short name T207
Test name
Test status
Simulation time 9466018582 ps
CPU time 148.31 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 228112 kb
Host smart-8d1a8b03-1e33-4e92-93c2-3529504c8f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016545157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3016545157
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3382004349
Short name T34
Test name
Test status
Simulation time 344129614 ps
CPU time 19.22 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:51:02 PM PDT 24
Peak memory 219732 kb
Host smart-3ef6cb55-55fe-42f2-975e-a4b3fc891421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382004349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3382004349
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2133325544
Short name T348
Test name
Test status
Simulation time 790113803 ps
CPU time 10.35 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:07 PM PDT 24
Peak memory 219732 kb
Host smart-af59b793-43e4-4548-80a4-90265c2c035e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133325544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2133325544
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.251780117
Short name T118
Test name
Test status
Simulation time 693710235 ps
CPU time 19.9 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:08 PM PDT 24
Peak memory 219184 kb
Host smart-00f652db-f8a2-497c-8a32-d202eb716618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251780117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.251780117
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3478065192
Short name T231
Test name
Test status
Simulation time 6354680276 ps
CPU time 77.48 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:51:57 PM PDT 24
Peak memory 221148 kb
Host smart-08154858-a722-42a9-9739-048ca4dcaf43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478065192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3478065192
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3595210277
Short name T299
Test name
Test status
Simulation time 346710018 ps
CPU time 8.4 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:49 PM PDT 24
Peak memory 218668 kb
Host smart-3154751d-45e0-4eaa-9309-f9285442cbdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595210277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3595210277
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3288439368
Short name T205
Test name
Test status
Simulation time 519906205 ps
CPU time 23 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:51:02 PM PDT 24
Peak memory 219696 kb
Host smart-ad70e438-cef7-4a50-96f5-b2a8752f2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288439368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3288439368
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.323608594
Short name T164
Test name
Test status
Simulation time 915638319 ps
CPU time 10.56 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:50:54 PM PDT 24
Peak memory 219756 kb
Host smart-f84edb50-e5b1-4ddf-beae-b80daf178f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323608594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.323608594
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3396856866
Short name T210
Test name
Test status
Simulation time 2017836328 ps
CPU time 23.97 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:51:08 PM PDT 24
Peak memory 219260 kb
Host smart-d85f93be-6211-48af-ba36-171858404b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396856866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3396856866
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2498989877
Short name T40
Test name
Test status
Simulation time 3124577902 ps
CPU time 43.33 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:51:24 PM PDT 24
Peak memory 220360 kb
Host smart-ed9c9e3b-ed30-4798-893d-ba99184b67e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498989877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2498989877
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2609604126
Short name T130
Test name
Test status
Simulation time 174514838 ps
CPU time 8.31 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:50:59 PM PDT 24
Peak memory 218772 kb
Host smart-043f2fb6-77fd-4e35-98f7-200fe70c6fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609604126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2609604126
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3158133427
Short name T318
Test name
Test status
Simulation time 1974664512 ps
CPU time 142.1 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 219804 kb
Host smart-ee23ee24-de27-4973-9f2e-946bd834b43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158133427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3158133427
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3345521211
Short name T239
Test name
Test status
Simulation time 1974682362 ps
CPU time 22.5 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:51:04 PM PDT 24
Peak memory 219836 kb
Host smart-7be662b8-885e-4799-a9a1-85a1a4c6687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345521211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3345521211
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.704776501
Short name T289
Test name
Test status
Simulation time 269648681 ps
CPU time 12.26 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:48 PM PDT 24
Peak memory 219732 kb
Host smart-a0c34306-c1da-4843-985a-f33bfaaa1cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704776501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.704776501
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.596664293
Short name T291
Test name
Test status
Simulation time 340110568 ps
CPU time 20.14 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:51:05 PM PDT 24
Peak memory 219200 kb
Host smart-6dc28a9e-bb0d-47da-8162-6e7fd76b465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596664293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.596664293
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1373303876
Short name T208
Test name
Test status
Simulation time 532180300 ps
CPU time 23.16 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 219076 kb
Host smart-18ec0b12-02de-491d-bc0f-999cb19db2b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373303876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1373303876
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2638569648
Short name T359
Test name
Test status
Simulation time 2357773885 ps
CPU time 8.21 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:50:58 PM PDT 24
Peak memory 218860 kb
Host smart-d9fc4665-f36d-4dde-b479-6c6b92abcaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638569648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2638569648
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1254426133
Short name T188
Test name
Test status
Simulation time 7096006370 ps
CPU time 197.62 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 228936 kb
Host smart-515d7312-54ee-4b3b-b273-4170f63957f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254426133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1254426133
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3370533865
Short name T38
Test name
Test status
Simulation time 1378249675 ps
CPU time 18.97 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:51:02 PM PDT 24
Peak memory 219712 kb
Host smart-3041cde6-90a2-45ce-a258-ce3fcc8092ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370533865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3370533865
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3819536409
Short name T14
Test name
Test status
Simulation time 187224538 ps
CPU time 10.15 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 219732 kb
Host smart-5997a9c5-cab3-4740-ba30-99f7edf1db23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819536409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3819536409
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.599115782
Short name T217
Test name
Test status
Simulation time 1440286107 ps
CPU time 19.77 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:51:00 PM PDT 24
Peak memory 218648 kb
Host smart-edae2e28-e04b-4d25-bd62-9d4a9658eef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599115782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.599115782
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3870599237
Short name T248
Test name
Test status
Simulation time 2311839294 ps
CPU time 48.96 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219748 kb
Host smart-160f650d-361b-4f5f-9ae1-1f054986115c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870599237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3870599237
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3189216490
Short name T309
Test name
Test status
Simulation time 248565731 ps
CPU time 10.09 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:50:58 PM PDT 24
Peak memory 219076 kb
Host smart-abd3ec1e-5fa2-4ef6-ad2f-ffcc7ab36151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189216490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3189216490
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3987817553
Short name T277
Test name
Test status
Simulation time 13196580420 ps
CPU time 181.25 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:53:43 PM PDT 24
Peak memory 242124 kb
Host smart-5d93c548-1b43-4722-9197-d4c82f72e92e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987817553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3987817553
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1989939244
Short name T312
Test name
Test status
Simulation time 4712182616 ps
CPU time 19.65 seconds
Started Jul 27 04:50:53 PM PDT 24
Finished Jul 27 04:51:13 PM PDT 24
Peak memory 219808 kb
Host smart-9db0b7a1-0820-421b-8966-1403e6c3a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989939244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1989939244
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1679977611
Short name T113
Test name
Test status
Simulation time 2907470471 ps
CPU time 16.53 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:59 PM PDT 24
Peak memory 219376 kb
Host smart-d26dca9c-d35a-40db-a431-0af02f0cf5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679977611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1679977611
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3068885012
Short name T343
Test name
Test status
Simulation time 343041108 ps
CPU time 19.4 seconds
Started Jul 27 04:50:52 PM PDT 24
Finished Jul 27 04:51:12 PM PDT 24
Peak memory 219216 kb
Host smart-7141ce47-5e52-4d78-92dc-6871181c877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068885012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3068885012
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1776033162
Short name T201
Test name
Test status
Simulation time 811397188 ps
CPU time 15.03 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:50:54 PM PDT 24
Peak memory 219468 kb
Host smart-68b61e0d-2c5d-492a-9001-88bbe1dab724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776033162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1776033162
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3830900584
Short name T46
Test name
Test status
Simulation time 30160029329 ps
CPU time 6262.01 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 06:35:18 PM PDT 24
Peak memory 231764 kb
Host smart-5f42bc89-3b3b-46d2-b5dc-69b5a1ec1a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830900584 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3830900584
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2488875595
Short name T349
Test name
Test status
Simulation time 2243743741 ps
CPU time 10.07 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 218784 kb
Host smart-db3d8d3e-7d4f-4747-98ab-4f0949d0ba2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488875595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2488875595
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1734887717
Short name T341
Test name
Test status
Simulation time 1224440699 ps
CPU time 19.53 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 219720 kb
Host smart-594a58cd-607b-41f6-8b0d-eef11c801a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734887717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1734887717
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3094790054
Short name T146
Test name
Test status
Simulation time 367377792 ps
CPU time 10.54 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:18 PM PDT 24
Peak memory 219708 kb
Host smart-f84af1cc-c6ee-4696-bf44-29a5293eda2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094790054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3094790054
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3126862424
Short name T192
Test name
Test status
Simulation time 730214827 ps
CPU time 19.6 seconds
Started Jul 27 04:51:00 PM PDT 24
Finished Jul 27 04:51:20 PM PDT 24
Peak memory 219176 kb
Host smart-c2295b7d-ed32-4928-aa2f-66fe061c819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126862424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3126862424
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4013305247
Short name T368
Test name
Test status
Simulation time 2303789288 ps
CPU time 32.18 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 219436 kb
Host smart-c59ab6b3-1087-48d4-9360-db934b1404e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013305247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4013305247
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1851638857
Short name T279
Test name
Test status
Simulation time 1081380957 ps
CPU time 10.19 seconds
Started Jul 27 04:50:56 PM PDT 24
Finished Jul 27 04:51:06 PM PDT 24
Peak memory 217680 kb
Host smart-5ba13350-8636-4759-b350-f7e3b266face
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851638857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1851638857
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1454704673
Short name T236
Test name
Test status
Simulation time 3034411070 ps
CPU time 211.96 seconds
Started Jul 27 04:50:47 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 239312 kb
Host smart-66e74937-5045-4737-a118-457787a88e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454704673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1454704673
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3087610045
Short name T370
Test name
Test status
Simulation time 517826114 ps
CPU time 22.84 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:30 PM PDT 24
Peak memory 219712 kb
Host smart-f38dd975-f771-4451-988e-7ff0efe3e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087610045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3087610045
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4004040672
Short name T127
Test name
Test status
Simulation time 1038835535 ps
CPU time 11.95 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:10 PM PDT 24
Peak memory 219692 kb
Host smart-ef43f660-6c2c-4c8c-94d9-bdcb7c948664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004040672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4004040672
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4197992940
Short name T31
Test name
Test status
Simulation time 2112390343 ps
CPU time 24.11 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:51:05 PM PDT 24
Peak memory 218708 kb
Host smart-0dfbfdf4-79ea-4367-bb8b-1b1772c47b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197992940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4197992940
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.337693352
Short name T168
Test name
Test status
Simulation time 5428857547 ps
CPU time 44.25 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:43 PM PDT 24
Peak memory 219716 kb
Host smart-e4caf4dd-69a6-435e-99bf-85c9e3799b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337693352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.337693352
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2211577968
Short name T328
Test name
Test status
Simulation time 101865382438 ps
CPU time 2103.05 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 05:25:53 PM PDT 24
Peak memory 252628 kb
Host smart-6c77c05e-e19d-45dd-ae16-5eae09559da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211577968 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2211577968
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2523352161
Short name T310
Test name
Test status
Simulation time 661976064 ps
CPU time 8.38 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:05 PM PDT 24
Peak memory 218788 kb
Host smart-604c6563-ddcc-4af1-ade3-cd5b95fcc260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523352161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2523352161
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.162217609
Short name T237
Test name
Test status
Simulation time 2143378099 ps
CPU time 123.93 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 237144 kb
Host smart-e053d0b8-d0ca-415f-8a73-bad2b097e239
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162217609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.162217609
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.994187206
Short name T122
Test name
Test status
Simulation time 503461836 ps
CPU time 23.42 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 219740 kb
Host smart-e4fb683a-bbf9-4309-8602-f6a94a8a4d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994187206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.994187206
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1473414073
Short name T322
Test name
Test status
Simulation time 269876709 ps
CPU time 12.05 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:51:01 PM PDT 24
Peak memory 219680 kb
Host smart-8373ab4e-6b8a-43ab-ac10-2b544642940d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473414073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1473414073
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3075255803
Short name T297
Test name
Test status
Simulation time 2286803188 ps
CPU time 23.06 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:51:14 PM PDT 24
Peak memory 218580 kb
Host smart-be3ce88d-50e1-4fb7-9e35-8dd611be7cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075255803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3075255803
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2552248792
Short name T253
Test name
Test status
Simulation time 2372346016 ps
CPU time 69.79 seconds
Started Jul 27 04:50:46 PM PDT 24
Finished Jul 27 04:51:56 PM PDT 24
Peak memory 220232 kb
Host smart-e01b2e32-33c5-4047-a001-0459dd4f54aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552248792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2552248792
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4243321447
Short name T13
Test name
Test status
Simulation time 155855336311 ps
CPU time 3240.83 seconds
Started Jul 27 04:50:52 PM PDT 24
Finished Jul 27 05:44:53 PM PDT 24
Peak memory 249300 kb
Host smart-743e70c7-f7fb-46bd-89e4-f1f145315aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243321447 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4243321447
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2620033508
Short name T271
Test name
Test status
Simulation time 475691395 ps
CPU time 9.97 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:50 PM PDT 24
Peak memory 218776 kb
Host smart-dfe74a68-bc42-4cf6-bf45-cccd6b484a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620033508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2620033508
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3761770102
Short name T305
Test name
Test status
Simulation time 19863593468 ps
CPU time 238.95 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:54:50 PM PDT 24
Peak memory 240912 kb
Host smart-21320554-e5d5-4cb5-969a-06685b5ab5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761770102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3761770102
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.728968382
Short name T226
Test name
Test status
Simulation time 2153396358 ps
CPU time 22.81 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 219812 kb
Host smart-6f4aed76-725f-441b-bbb1-ebd48aa7d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728968382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.728968382
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3052468791
Short name T364
Test name
Test status
Simulation time 1148863028 ps
CPU time 10.13 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:50:50 PM PDT 24
Peak memory 219704 kb
Host smart-b07d660c-bd23-454a-8345-3042cddd9412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052468791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3052468791
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1043987097
Short name T366
Test name
Test status
Simulation time 1735682816 ps
CPU time 22.85 seconds
Started Jul 27 04:50:56 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 219156 kb
Host smart-0290c43f-6131-4e9e-8012-319c4975f3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043987097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1043987097
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2080476608
Short name T247
Test name
Test status
Simulation time 912243439 ps
CPU time 53.16 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:51:35 PM PDT 24
Peak memory 220428 kb
Host smart-272cd663-0f87-4995-b049-e366cda94cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080476608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2080476608
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3034133119
Short name T227
Test name
Test status
Simulation time 1077631486 ps
CPU time 10 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:10 PM PDT 24
Peak memory 218808 kb
Host smart-a4238ef2-d385-4ea1-a38c-702d5b8583d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034133119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3034133119
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.317080814
Short name T219
Test name
Test status
Simulation time 10614087871 ps
CPU time 300.77 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:55:58 PM PDT 24
Peak memory 234104 kb
Host smart-6e0d5ea2-6241-4a5c-be5d-2462df42580f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317080814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.317080814
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1591591874
Short name T365
Test name
Test status
Simulation time 1376452894 ps
CPU time 19.01 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:20 PM PDT 24
Peak memory 219732 kb
Host smart-46a2671c-0297-4160-af92-f89ec6d2f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591591874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1591591874
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1063839945
Short name T252
Test name
Test status
Simulation time 606067932 ps
CPU time 12.34 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:53 PM PDT 24
Peak memory 219680 kb
Host smart-149a16e2-b0d2-4984-84b9-369c4a8b227e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063839945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1063839945
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2766478222
Short name T298
Test name
Test status
Simulation time 8236597974 ps
CPU time 32.61 seconds
Started Jul 27 04:50:47 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 219428 kb
Host smart-8bb7a52b-4f3f-42a6-a65f-2c9cbf06a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766478222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2766478222
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4076313391
Short name T194
Test name
Test status
Simulation time 563030831 ps
CPU time 34.59 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219644 kb
Host smart-e3093d6f-c535-4b65-a44c-45af9fcbeacd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076313391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4076313391
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3826845350
Short name T112
Test name
Test status
Simulation time 3925326911 ps
CPU time 14.21 seconds
Started Jul 27 04:50:28 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 218496 kb
Host smart-8da03512-3a6d-47dc-a54f-61161bc2f088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826845350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3826845350
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.416489047
Short name T255
Test name
Test status
Simulation time 4849742391 ps
CPU time 313.26 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:55:55 PM PDT 24
Peak memory 219928 kb
Host smart-8259c90f-e334-402f-b75c-46070e200d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416489047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.416489047
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.522098429
Short name T266
Test name
Test status
Simulation time 332401994 ps
CPU time 19.11 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 219660 kb
Host smart-893008a4-f94b-4f82-8f37-d8b124543aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522098429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.522098429
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2772025953
Short name T4
Test name
Test status
Simulation time 400665238 ps
CPU time 10.64 seconds
Started Jul 27 04:50:39 PM PDT 24
Finished Jul 27 04:50:50 PM PDT 24
Peak memory 219660 kb
Host smart-cefa7d25-94e1-4bf6-bbea-ba852b942ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772025953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2772025953
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1327281928
Short name T19
Test name
Test status
Simulation time 2692001701 ps
CPU time 228.2 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:54:47 PM PDT 24
Peak memory 238544 kb
Host smart-0f818e31-994d-4a73-b385-474aab9f785a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327281928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1327281928
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4244452767
Short name T258
Test name
Test status
Simulation time 500387463 ps
CPU time 19.31 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:39 PM PDT 24
Peak memory 219120 kb
Host smart-cbe3e57b-235d-47ae-ad33-8101ad56acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244452767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4244452767
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.888723029
Short name T213
Test name
Test status
Simulation time 810680703 ps
CPU time 24.28 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 219272 kb
Host smart-4213832c-878a-4913-a0c0-626160fb427c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888723029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.888723029
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1803526484
Short name T315
Test name
Test status
Simulation time 66327729294 ps
CPU time 677.56 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 05:01:49 PM PDT 24
Peak memory 234708 kb
Host smart-b551ada1-decc-4588-b390-af50bc38c159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803526484 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1803526484
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3908935763
Short name T228
Test name
Test status
Simulation time 1653812623 ps
CPU time 8.23 seconds
Started Jul 27 04:51:25 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 218812 kb
Host smart-a4c2f7f6-83ac-485d-886e-0d76bbb4a24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908935763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3908935763
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.485364810
Short name T152
Test name
Test status
Simulation time 7603227132 ps
CPU time 109.55 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 228952 kb
Host smart-95d459b9-50c1-473c-adc1-fcbf8ac9dee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485364810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.485364810
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1509196625
Short name T8
Test name
Test status
Simulation time 705040289 ps
CPU time 19.15 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 219768 kb
Host smart-efccf36e-ce2c-45bf-8825-96367723dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509196625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1509196625
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.567095450
Short name T251
Test name
Test status
Simulation time 2857798033 ps
CPU time 11.77 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:11 PM PDT 24
Peak memory 219752 kb
Host smart-3434ac43-b36f-4277-aebf-eea7af76f5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567095450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.567095450
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.518530278
Short name T49
Test name
Test status
Simulation time 1032246200 ps
CPU time 23.65 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 219168 kb
Host smart-52630855-8595-4c13-93db-8ccc1caae7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518530278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.518530278
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1262184890
Short name T296
Test name
Test status
Simulation time 547757914 ps
CPU time 24.36 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:51:27 PM PDT 24
Peak memory 219084 kb
Host smart-df8dc7a9-d8d2-4a93-8bd7-b5011885d71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262184890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1262184890
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1166608493
Short name T128
Test name
Test status
Simulation time 333311460 ps
CPU time 8.13 seconds
Started Jul 27 04:50:47 PM PDT 24
Finished Jul 27 04:50:55 PM PDT 24
Peak memory 218836 kb
Host smart-abdbad2f-3567-42c7-a2b4-80e266a4b377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166608493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1166608493
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.287559308
Short name T249
Test name
Test status
Simulation time 18042950771 ps
CPU time 227.04 seconds
Started Jul 27 04:50:53 PM PDT 24
Finished Jul 27 04:54:40 PM PDT 24
Peak memory 228244 kb
Host smart-ba0cea4e-994b-449f-a58e-b07f41b8224b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287559308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.287559308
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3941341516
Short name T278
Test name
Test status
Simulation time 1013327256 ps
CPU time 22.79 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:36 PM PDT 24
Peak memory 219844 kb
Host smart-93adc055-bd92-41f2-81c8-127487d7e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941341516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3941341516
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.661394894
Short name T331
Test name
Test status
Simulation time 1021717544 ps
CPU time 11.81 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:51:15 PM PDT 24
Peak memory 219756 kb
Host smart-04832244-19f9-4521-8394-c9ebc43fe3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661394894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.661394894
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2907230133
Short name T149
Test name
Test status
Simulation time 1044229501 ps
CPU time 23.51 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 219224 kb
Host smart-b1a79292-e8e9-4375-86fc-4dd68d94c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907230133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2907230133
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1697011400
Short name T167
Test name
Test status
Simulation time 249357620 ps
CPU time 9.98 seconds
Started Jul 27 04:50:59 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 218688 kb
Host smart-4b121058-f3bc-4274-b7c9-d7b319fef1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697011400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1697011400
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1992471256
Short name T95
Test name
Test status
Simulation time 11691085611 ps
CPU time 157.64 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:53:43 PM PDT 24
Peak memory 238680 kb
Host smart-7151047f-3f17-4ef4-a614-a9b2fd0107d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992471256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1992471256
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2960451768
Short name T245
Test name
Test status
Simulation time 498309436 ps
CPU time 23.32 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 219748 kb
Host smart-fdedd3c4-d6bb-4d45-8687-eaa8dcb12300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960451768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2960451768
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4183824676
Short name T155
Test name
Test status
Simulation time 731482219 ps
CPU time 10.58 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:11 PM PDT 24
Peak memory 219708 kb
Host smart-eff0abd2-dfb5-40f5-94b8-79675c84f242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183824676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4183824676
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1584871790
Short name T10
Test name
Test status
Simulation time 515188236 ps
CPU time 22.6 seconds
Started Jul 27 04:51:04 PM PDT 24
Finished Jul 27 04:51:27 PM PDT 24
Peak memory 219112 kb
Host smart-f63945cf-f457-4e45-92b6-7ec5ced2005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584871790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1584871790
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3511163497
Short name T137
Test name
Test status
Simulation time 2064020337 ps
CPU time 20.73 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:27 PM PDT 24
Peak memory 219248 kb
Host smart-c685b7e9-7f5c-4a7b-906c-ef9f6fa0c2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511163497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3511163497
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4213687389
Short name T209
Test name
Test status
Simulation time 176195745 ps
CPU time 8.41 seconds
Started Jul 27 04:51:15 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 218804 kb
Host smart-c675174f-ec1a-420a-9a35-ee7cecfa2910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213687389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4213687389
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.97561087
Short name T135
Test name
Test status
Simulation time 3535074494 ps
CPU time 221.87 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 242232 kb
Host smart-5c1461c6-27a0-43c0-a712-c2b22d356f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97561087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_co
rrupt_sig_fatal_chk.97561087
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3931095579
Short name T147
Test name
Test status
Simulation time 690259607 ps
CPU time 19.53 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:27 PM PDT 24
Peak memory 219740 kb
Host smart-dfee213e-03eb-49f4-818e-7bff79a80420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931095579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3931095579
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1085699474
Short name T202
Test name
Test status
Simulation time 1043771162 ps
CPU time 16.66 seconds
Started Jul 27 04:51:02 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 219704 kb
Host smart-a7c41d28-4876-47e8-9cda-bfe9495f9837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085699474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1085699474
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4193000831
Short name T1
Test name
Test status
Simulation time 2117014729 ps
CPU time 23.41 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219172 kb
Host smart-9aaaa428-05c9-4b8b-af6c-cfe9d6745043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193000831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4193000831
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1340778952
Short name T265
Test name
Test status
Simulation time 380631475 ps
CPU time 10.84 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 218616 kb
Host smart-d84fe927-8427-4fd6-b2f1-83db107a6ec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340778952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1340778952
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3528900090
Short name T43
Test name
Test status
Simulation time 242811106246 ps
CPU time 2099.99 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 05:26:10 PM PDT 24
Peak memory 236192 kb
Host smart-e38a7805-d769-49f2-aa95-1fc1fe9a3c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528900090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3528900090
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.271361036
Short name T361
Test name
Test status
Simulation time 1773721465 ps
CPU time 10.16 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:51:14 PM PDT 24
Peak memory 218744 kb
Host smart-a37345f2-5d77-4a2f-864d-98d9d11bbd44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271361036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.271361036
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4200943444
Short name T123
Test name
Test status
Simulation time 5397460164 ps
CPU time 272.4 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:55:40 PM PDT 24
Peak memory 229860 kb
Host smart-728472bf-8c96-4a6b-978a-83855e09fbdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200943444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4200943444
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2341686544
Short name T347
Test name
Test status
Simulation time 2069427543 ps
CPU time 23.29 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:12 PM PDT 24
Peak memory 219768 kb
Host smart-abdf9811-9f07-4c68-a06e-cafe75db024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341686544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2341686544
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.80504795
Short name T148
Test name
Test status
Simulation time 519722901 ps
CPU time 11.91 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 04:51:07 PM PDT 24
Peak memory 219716 kb
Host smart-b6002594-b74f-4d8f-8701-e9ccc53278b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80504795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.80504795
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1769029746
Short name T295
Test name
Test status
Simulation time 6186284675 ps
CPU time 35.21 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:51:41 PM PDT 24
Peak memory 219320 kb
Host smart-f42ca5fe-3254-4437-ad06-6caf4ba4e24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769029746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1769029746
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1506978024
Short name T323
Test name
Test status
Simulation time 174718512 ps
CPU time 8.53 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:22 PM PDT 24
Peak memory 218788 kb
Host smart-ac463ff2-f2c3-4d40-8d6c-017d61243185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506978024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1506978024
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.149754955
Short name T195
Test name
Test status
Simulation time 3985565948 ps
CPU time 283.56 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:55:45 PM PDT 24
Peak memory 234352 kb
Host smart-632bdaa0-9bf3-48d2-9713-fda4abd0ca29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149754955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.149754955
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3643680839
Short name T175
Test name
Test status
Simulation time 1103640418 ps
CPU time 22.46 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219748 kb
Host smart-ab08c17a-b664-4fa7-9fd7-4e64de491ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643680839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3643680839
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3355908303
Short name T190
Test name
Test status
Simulation time 721001578 ps
CPU time 10.08 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:50:54 PM PDT 24
Peak memory 219728 kb
Host smart-9ed7439c-3cce-450f-92ec-92b996dbd404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355908303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3355908303
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3244730438
Short name T154
Test name
Test status
Simulation time 510800003 ps
CPU time 23.57 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219196 kb
Host smart-86819e50-cfdd-4e67-b015-82541b4a7712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244730438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3244730438
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4174969472
Short name T70
Test name
Test status
Simulation time 1544717627 ps
CPU time 77.15 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:52:22 PM PDT 24
Peak memory 220224 kb
Host smart-7fe618ce-a6b9-4f51-9344-315de058470f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174969472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4174969472
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3337787627
Short name T182
Test name
Test status
Simulation time 592294778 ps
CPU time 8.24 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:14 PM PDT 24
Peak memory 218684 kb
Host smart-3ea19792-e6de-40c9-b626-256786aa3eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337787627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3337787627
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3980881136
Short name T142
Test name
Test status
Simulation time 2758625499 ps
CPU time 201.09 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:54:24 PM PDT 24
Peak memory 240204 kb
Host smart-d9347062-3f2e-4c6d-8f93-98258b575cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980881136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3980881136
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1658906172
Short name T257
Test name
Test status
Simulation time 1980137751 ps
CPU time 22.85 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219172 kb
Host smart-5c9a8f27-b2fb-4f8c-b0fb-0fc127fbcb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658906172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1658906172
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4226599556
Short name T94
Test name
Test status
Simulation time 827782502 ps
CPU time 10.55 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:50:59 PM PDT 24
Peak memory 219768 kb
Host smart-e07d3a00-1097-405a-a534-605236b99590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226599556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4226599556
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1112083516
Short name T211
Test name
Test status
Simulation time 2797244296 ps
CPU time 36.83 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 218816 kb
Host smart-020a572c-2174-4378-9252-c84f7ab73982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112083516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1112083516
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4117641655
Short name T15
Test name
Test status
Simulation time 3082086225 ps
CPU time 41.04 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:47 PM PDT 24
Peak memory 219480 kb
Host smart-9fa8e87b-d894-4830-a94e-447515a7dc8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117641655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4117641655
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3152079139
Short name T96
Test name
Test status
Simulation time 31306063298 ps
CPU time 1223.37 seconds
Started Jul 27 04:51:04 PM PDT 24
Finished Jul 27 05:11:28 PM PDT 24
Peak memory 234692 kb
Host smart-29be700e-c3fc-481f-adc8-a4b4ca1d45b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152079139 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3152079139
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2554415067
Short name T58
Test name
Test status
Simulation time 1276114099 ps
CPU time 8.44 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:22 PM PDT 24
Peak memory 218696 kb
Host smart-4c6ec1a3-5d00-4d75-9b81-8c6bc796d167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554415067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2554415067
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1585950002
Short name T300
Test name
Test status
Simulation time 22224026501 ps
CPU time 307.96 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:56:09 PM PDT 24
Peak memory 230072 kb
Host smart-ddd211ce-736a-4070-a725-5250f8c3211b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585950002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1585950002
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3222656022
Short name T330
Test name
Test status
Simulation time 512702472 ps
CPU time 22.59 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:24 PM PDT 24
Peak memory 219700 kb
Host smart-cc7cf572-86ab-4b71-b956-be17b333b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222656022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3222656022
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1850185938
Short name T232
Test name
Test status
Simulation time 747379851 ps
CPU time 9.99 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:22 PM PDT 24
Peak memory 219704 kb
Host smart-a81c55c3-5a07-48e5-88c2-683609458884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850185938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1850185938
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3160761597
Short name T243
Test name
Test status
Simulation time 2207113943 ps
CPU time 24.36 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 219248 kb
Host smart-98ee77f5-ee30-4521-b215-9bae32a042d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160761597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3160761597
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3596347126
Short name T215
Test name
Test status
Simulation time 1057323571 ps
CPU time 46.05 seconds
Started Jul 27 04:50:58 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 219356 kb
Host smart-ac031cb8-083b-4cd0-8b4a-3375faeb3958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596347126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3596347126
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3534304524
Short name T356
Test name
Test status
Simulation time 169196235 ps
CPU time 8.54 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 218904 kb
Host smart-32e494c8-4783-4a4a-8ab2-3815c7aeacb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534304524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3534304524
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2288688220
Short name T283
Test name
Test status
Simulation time 8019670524 ps
CPU time 190.92 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 219900 kb
Host smart-32809f83-7bb5-4ba6-8531-161f5320ca9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288688220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2288688220
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1911449049
Short name T161
Test name
Test status
Simulation time 661220478 ps
CPU time 22.99 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219744 kb
Host smart-f666bd9b-15f1-48fd-9a15-d5f345ab3d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911449049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1911449049
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2699110929
Short name T93
Test name
Test status
Simulation time 267870477 ps
CPU time 12.55 seconds
Started Jul 27 04:51:03 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 219716 kb
Host smart-62a96e95-58de-48a3-a991-1ae2e594bfe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699110929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2699110929
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2150452333
Short name T50
Test name
Test status
Simulation time 1023378377 ps
CPU time 23.38 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219136 kb
Host smart-7d7c828a-9285-4535-a53d-69af97df648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150452333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2150452333
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1942253396
Short name T293
Test name
Test status
Simulation time 2487901613 ps
CPU time 29.63 seconds
Started Jul 27 04:51:01 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219716 kb
Host smart-1906a61f-47c4-452d-a6a6-901a7f2a00ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942253396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1942253396
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4000818759
Short name T153
Test name
Test status
Simulation time 168037466 ps
CPU time 8.26 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:51:13 PM PDT 24
Peak memory 218856 kb
Host smart-b38260b9-f615-44ad-b3c6-4901cc552516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000818759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4000818759
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3371602186
Short name T235
Test name
Test status
Simulation time 21774627250 ps
CPU time 287.71 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:55:57 PM PDT 24
Peak memory 234292 kb
Host smart-fb8f6e2d-a776-48ba-8fb3-bd17f885bc74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371602186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3371602186
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1959962727
Short name T264
Test name
Test status
Simulation time 346555696 ps
CPU time 18.81 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 219724 kb
Host smart-dd468a7a-22fd-43fe-b638-81145cca192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959962727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1959962727
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2957753016
Short name T238
Test name
Test status
Simulation time 1919541048 ps
CPU time 10.46 seconds
Started Jul 27 04:51:28 PM PDT 24
Finished Jul 27 04:51:39 PM PDT 24
Peak memory 219740 kb
Host smart-4654818e-99e3-4103-9967-82a851bd7d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957753016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2957753016
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1360837860
Short name T69
Test name
Test status
Simulation time 534968431 ps
CPU time 24.28 seconds
Started Jul 27 04:51:28 PM PDT 24
Finished Jul 27 04:51:52 PM PDT 24
Peak memory 219212 kb
Host smart-1efcc7ae-4805-42e8-be78-ab25db766c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360837860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1360837860
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2742538223
Short name T5
Test name
Test status
Simulation time 2958035741 ps
CPU time 24.34 seconds
Started Jul 27 04:50:57 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 218556 kb
Host smart-cae4fc63-fd6d-4f5a-8234-dd74393b8ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742538223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2742538223
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.950316403
Short name T196
Test name
Test status
Simulation time 172947911 ps
CPU time 8.37 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 218804 kb
Host smart-32c7b3b5-f879-4088-8cba-fd79bacc0380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950316403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.950316403
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2442165064
Short name T281
Test name
Test status
Simulation time 4031148175 ps
CPU time 178.55 seconds
Started Jul 27 04:50:30 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 233024 kb
Host smart-f6a67ab0-ec62-4354-af9f-345e1f9e4e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442165064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2442165064
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.883450013
Short name T275
Test name
Test status
Simulation time 517449743 ps
CPU time 22.2 seconds
Started Jul 27 04:50:37 PM PDT 24
Finished Jul 27 04:50:59 PM PDT 24
Peak memory 219708 kb
Host smart-ac495e85-a579-4235-bc6e-5fa908e7e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883450013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.883450013
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4264658908
Short name T179
Test name
Test status
Simulation time 2202442194 ps
CPU time 10.57 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 219780 kb
Host smart-a4add891-5873-4f20-8162-4981ecca09cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264658908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4264658908
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.901515048
Short name T25
Test name
Test status
Simulation time 3205332900 ps
CPU time 225.77 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 239468 kb
Host smart-f4cdf31e-d56f-4256-b6a1-7c7db5ad28fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901515048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.901515048
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.278704807
Short name T186
Test name
Test status
Simulation time 1364710862 ps
CPU time 19.77 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 218140 kb
Host smart-6de00607-5578-4cbc-a086-c4f85d77e23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278704807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.278704807
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.771955343
Short name T234
Test name
Test status
Simulation time 4933469563 ps
CPU time 19.62 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:50:51 PM PDT 24
Peak memory 218832 kb
Host smart-06f33758-7de0-4591-b190-49eeec9c2cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771955343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.771955343
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.920770303
Short name T187
Test name
Test status
Simulation time 1101422048 ps
CPU time 8.36 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:21 PM PDT 24
Peak memory 218796 kb
Host smart-50f1a269-73a1-42fc-9b73-d18b4f686708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920770303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.920770303
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1346218845
Short name T274
Test name
Test status
Simulation time 6131772533 ps
CPU time 333.25 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:56:55 PM PDT 24
Peak memory 238232 kb
Host smart-d69b92b3-3a93-4064-80ca-0a28b0f0e54d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346218845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1346218845
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.863036411
Short name T288
Test name
Test status
Simulation time 8530618405 ps
CPU time 31.85 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:51:37 PM PDT 24
Peak memory 219800 kb
Host smart-d85ad1c2-4f5c-4658-a79c-e39f5c6aaeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863036411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.863036411
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.99982525
Short name T221
Test name
Test status
Simulation time 697058111 ps
CPU time 10.37 seconds
Started Jul 27 04:51:05 PM PDT 24
Finished Jul 27 04:51:15 PM PDT 24
Peak memory 219700 kb
Host smart-bab0f1c6-2557-4374-981d-5c987d4d1d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99982525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.99982525
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.661145015
Short name T338
Test name
Test status
Simulation time 1130652140 ps
CPU time 24.02 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 219200 kb
Host smart-4ee60f82-f4bd-40df-8550-e92e3c014c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661145015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.661145015
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4072916579
Short name T254
Test name
Test status
Simulation time 1100763993 ps
CPU time 35.2 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:47 PM PDT 24
Peak memory 219452 kb
Host smart-a63998c8-16f9-42fe-9d71-774a282c9776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072916579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4072916579
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2711033078
Short name T301
Test name
Test status
Simulation time 56281218794 ps
CPU time 3482.03 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 05:49:10 PM PDT 24
Peak memory 231344 kb
Host smart-5d9d9ac0-265a-4f98-b34f-71ccf3ddeff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711033078 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2711033078
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1535402314
Short name T199
Test name
Test status
Simulation time 6533250632 ps
CPU time 15.24 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 218804 kb
Host smart-f1c99a3c-de9a-484b-898a-ad79da1de940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535402314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1535402314
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.896401427
Short name T185
Test name
Test status
Simulation time 2251621714 ps
CPU time 120.61 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 241348 kb
Host smart-4940ee22-19d1-46f7-b39b-f410461564af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896401427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.896401427
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.316128218
Short name T284
Test name
Test status
Simulation time 1986220060 ps
CPU time 22.74 seconds
Started Jul 27 04:51:08 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219728 kb
Host smart-a20bb175-3b69-4988-9832-e3b827cfba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316128218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.316128218
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1252179440
Short name T180
Test name
Test status
Simulation time 1062123292 ps
CPU time 12.32 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:25 PM PDT 24
Peak memory 219664 kb
Host smart-1f82d206-337f-45f5-b5b8-172b73466119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252179440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1252179440
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2298756307
Short name T355
Test name
Test status
Simulation time 360218230 ps
CPU time 20.13 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:26 PM PDT 24
Peak memory 219308 kb
Host smart-b0ef0e11-ee60-403a-bc74-eb6140797212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298756307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2298756307
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3336509414
Short name T282
Test name
Test status
Simulation time 4980773755 ps
CPU time 89.41 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 221736 kb
Host smart-56621362-41fc-4b8f-b4a0-e3a80567a998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336509414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3336509414
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1100616517
Short name T144
Test name
Test status
Simulation time 688718369 ps
CPU time 8.23 seconds
Started Jul 27 04:51:07 PM PDT 24
Finished Jul 27 04:51:16 PM PDT 24
Peak memory 218788 kb
Host smart-2b86e307-9d31-4cd7-97e5-d165fc56dcfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100616517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1100616517
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3403745937
Short name T333
Test name
Test status
Simulation time 3659315095 ps
CPU time 194.46 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:54:50 PM PDT 24
Peak memory 238252 kb
Host smart-96267456-44d3-4529-a159-3b40cdbbfac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403745937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3403745937
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.717339659
Short name T171
Test name
Test status
Simulation time 512837218 ps
CPU time 23.14 seconds
Started Jul 27 04:51:15 PM PDT 24
Finished Jul 27 04:51:38 PM PDT 24
Peak memory 219756 kb
Host smart-a18bc80e-3eeb-4943-a407-37d7beb0ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717339659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.717339659
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2508656446
Short name T132
Test name
Test status
Simulation time 728073616 ps
CPU time 10.35 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 219716 kb
Host smart-b641222c-85a1-416f-b409-a76aef230661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508656446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2508656446
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2422000386
Short name T72
Test name
Test status
Simulation time 707295662 ps
CPU time 20.6 seconds
Started Jul 27 04:51:19 PM PDT 24
Finished Jul 27 04:51:40 PM PDT 24
Peak memory 218800 kb
Host smart-f4124a9c-3700-42e8-bebb-0da7213cf62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422000386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2422000386
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2028952222
Short name T71
Test name
Test status
Simulation time 796084297 ps
CPU time 38.22 seconds
Started Jul 27 04:51:30 PM PDT 24
Finished Jul 27 04:52:09 PM PDT 24
Peak memory 219592 kb
Host smart-740c1d4d-0da8-4e53-8f00-431b9d0a5e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028952222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2028952222
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2132116556
Short name T22
Test name
Test status
Simulation time 256949974 ps
CPU time 10.05 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 217724 kb
Host smart-5e66216a-baa2-4fc6-b725-2372384592c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132116556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2132116556
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.49956073
Short name T16
Test name
Test status
Simulation time 8074839322 ps
CPU time 276.94 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:55:57 PM PDT 24
Peak memory 235224 kb
Host smart-f915340a-b6bd-4824-b0bd-704bee28c1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49956073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_co
rrupt_sig_fatal_chk.49956073
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1610076265
Short name T317
Test name
Test status
Simulation time 513379070 ps
CPU time 22.66 seconds
Started Jul 27 04:51:23 PM PDT 24
Finished Jul 27 04:51:46 PM PDT 24
Peak memory 219736 kb
Host smart-d1d3c380-6a2f-46b9-84c4-c34e3499b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610076265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1610076265
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1303234457
Short name T286
Test name
Test status
Simulation time 268774971 ps
CPU time 12.19 seconds
Started Jul 27 04:51:33 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 219688 kb
Host smart-db267115-e840-43d7-92b1-e01ccca51fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303234457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1303234457
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1494605829
Short name T212
Test name
Test status
Simulation time 7214568889 ps
CPU time 23.87 seconds
Started Jul 27 04:51:33 PM PDT 24
Finished Jul 27 04:51:57 PM PDT 24
Peak memory 219268 kb
Host smart-5957a8e5-48e2-49bc-aaae-48153b2b7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494605829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1494605829
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.188486340
Short name T256
Test name
Test status
Simulation time 4161413747 ps
CPU time 22.86 seconds
Started Jul 27 04:51:26 PM PDT 24
Finished Jul 27 04:51:49 PM PDT 24
Peak memory 219612 kb
Host smart-99004080-be30-42f7-b009-605547b0f3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188486340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.188486340
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2793261862
Short name T246
Test name
Test status
Simulation time 870931454 ps
CPU time 8.33 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 218832 kb
Host smart-cfe05428-7a00-4f48-b345-b9a26a70c2bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793261862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2793261862
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2416257560
Short name T336
Test name
Test status
Simulation time 56875447064 ps
CPU time 257.05 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:55:30 PM PDT 24
Peak memory 240240 kb
Host smart-8b25c55a-6683-4d48-9e05-9d06f314df00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416257560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2416257560
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.481879011
Short name T203
Test name
Test status
Simulation time 1013987402 ps
CPU time 22.34 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 217916 kb
Host smart-308ecbba-401d-42b7-aca5-a6bbbbe443c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481879011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.481879011
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2006716952
Short name T280
Test name
Test status
Simulation time 535607328 ps
CPU time 12.06 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:23 PM PDT 24
Peak memory 219736 kb
Host smart-c936ba2e-6fda-4111-aa9b-217910307c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006716952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2006716952
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.878502083
Short name T120
Test name
Test status
Simulation time 350504927 ps
CPU time 19.99 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 219248 kb
Host smart-c8256d08-7704-4185-a9f3-5cb31b527618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878502083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.878502083
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.367873323
Short name T332
Test name
Test status
Simulation time 1625078954 ps
CPU time 35.89 seconds
Started Jul 27 04:51:27 PM PDT 24
Finished Jul 27 04:52:03 PM PDT 24
Peak memory 219636 kb
Host smart-9d0c8520-5d40-4eb9-88d2-c44c2330ed3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367873323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.367873323
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2801083254
Short name T263
Test name
Test status
Simulation time 107599767193 ps
CPU time 2201.22 seconds
Started Jul 27 04:52:35 PM PDT 24
Finished Jul 27 05:29:17 PM PDT 24
Peak memory 238892 kb
Host smart-4c07f3ef-b661-4d83-bdc8-73d340d470d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801083254 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2801083254
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2883486110
Short name T326
Test name
Test status
Simulation time 257307873 ps
CPU time 10.03 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 218768 kb
Host smart-e8d23b69-b4a3-415b-a814-edb972d17cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883486110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2883486110
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3101884309
Short name T358
Test name
Test status
Simulation time 2396826784 ps
CPU time 169.38 seconds
Started Jul 27 04:51:17 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 239372 kb
Host smart-909c42f2-2559-43c2-826e-e7a545873bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101884309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3101884309
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3472601192
Short name T352
Test name
Test status
Simulation time 496995207 ps
CPU time 21.58 seconds
Started Jul 27 04:51:19 PM PDT 24
Finished Jul 27 04:51:40 PM PDT 24
Peak memory 219712 kb
Host smart-829175a8-303d-4394-8c67-ec9be4f5461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472601192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3472601192
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3376820286
Short name T198
Test name
Test status
Simulation time 511032785 ps
CPU time 11.63 seconds
Started Jul 27 04:52:13 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 219280 kb
Host smart-3220dcc3-13f2-4381-998a-24424919be75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376820286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3376820286
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4036932261
Short name T139
Test name
Test status
Simulation time 524118565 ps
CPU time 23.04 seconds
Started Jul 27 04:51:32 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 219152 kb
Host smart-a58607b5-5e7b-4af8-b790-2f75afc73ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036932261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4036932261
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.297706097
Short name T354
Test name
Test status
Simulation time 813995404 ps
CPU time 49.24 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:52:06 PM PDT 24
Peak memory 219444 kb
Host smart-e2b4dd46-32a2-4a3a-842d-93a093c84408
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297706097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.297706097
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2199479171
Short name T44
Test name
Test status
Simulation time 29729417343 ps
CPU time 5285.45 seconds
Started Jul 27 04:51:17 PM PDT 24
Finished Jul 27 06:19:23 PM PDT 24
Peak memory 230788 kb
Host smart-6952bb0a-4b15-4e53-a7da-11910ee6e86a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199479171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2199479171
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.321940611
Short name T157
Test name
Test status
Simulation time 1034357711 ps
CPU time 10.09 seconds
Started Jul 27 04:51:34 PM PDT 24
Finished Jul 27 04:51:44 PM PDT 24
Peak memory 218812 kb
Host smart-1a6b0f31-9718-4439-b870-cf74734ea0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321940611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.321940611
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1870297382
Short name T160
Test name
Test status
Simulation time 5766724623 ps
CPU time 325.17 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:57:01 PM PDT 24
Peak memory 240128 kb
Host smart-ed38f9f8-ff13-4f5b-939e-09c43ba2287d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870297382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1870297382
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2254717069
Short name T158
Test name
Test status
Simulation time 497690228 ps
CPU time 22.53 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:35 PM PDT 24
Peak memory 219764 kb
Host smart-00c45045-b026-4ab3-a071-b0986a7d810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254717069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2254717069
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.433628872
Short name T351
Test name
Test status
Simulation time 176882060 ps
CPU time 10.29 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:23 PM PDT 24
Peak memory 217556 kb
Host smart-76d09ccf-d7c5-42d4-9b7d-39ad11f76774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433628872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.433628872
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.166315827
Short name T353
Test name
Test status
Simulation time 535947619 ps
CPU time 23.71 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 219180 kb
Host smart-4988e45d-b43e-4539-9a46-c58cd5dd8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166315827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.166315827
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2073061324
Short name T325
Test name
Test status
Simulation time 564312633 ps
CPU time 41.35 seconds
Started Jul 27 04:51:15 PM PDT 24
Finished Jul 27 04:51:56 PM PDT 24
Peak memory 219656 kb
Host smart-b3ba3a06-53d0-4ed1-8dd6-f5a54a7e2e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073061324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2073061324
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2445843838
Short name T273
Test name
Test status
Simulation time 618932960064 ps
CPU time 2159.31 seconds
Started Jul 27 04:51:32 PM PDT 24
Finished Jul 27 05:27:32 PM PDT 24
Peak memory 248292 kb
Host smart-fdfe5650-6cf9-4264-9a0f-eee1dd476a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445843838 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2445843838
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2920081323
Short name T57
Test name
Test status
Simulation time 250357572 ps
CPU time 10.11 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 218708 kb
Host smart-c53b8b2e-f85d-428a-be12-63e19ddd0422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920081323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2920081323
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2595802123
Short name T36
Test name
Test status
Simulation time 8582777209 ps
CPU time 242.74 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:56:16 PM PDT 24
Peak memory 231776 kb
Host smart-317f63c2-7c81-4946-9847-8079c33cfe83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595802123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2595802123
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3083109109
Short name T363
Test name
Test status
Simulation time 539316579 ps
CPU time 22.65 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:51:43 PM PDT 24
Peak memory 219780 kb
Host smart-17a00fd8-dcdc-43be-a447-860e397e6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083109109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3083109109
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3965271308
Short name T241
Test name
Test status
Simulation time 719325360 ps
CPU time 10.12 seconds
Started Jul 27 04:52:13 PM PDT 24
Finished Jul 27 04:52:23 PM PDT 24
Peak memory 218464 kb
Host smart-416331cf-54fe-47dd-8a34-0f253538f63e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965271308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3965271308
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1243423262
Short name T126
Test name
Test status
Simulation time 2095519757 ps
CPU time 22.44 seconds
Started Jul 27 04:51:26 PM PDT 24
Finished Jul 27 04:51:48 PM PDT 24
Peak memory 219140 kb
Host smart-d4467fd5-6d33-4cea-8152-fe6955bf46b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243423262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1243423262
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3510623257
Short name T321
Test name
Test status
Simulation time 1268406943 ps
CPU time 70.44 seconds
Started Jul 27 04:51:30 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 222368 kb
Host smart-1bdb6417-e3d6-4dc9-96c1-b7054c076f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510623257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3510623257
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1091213032
Short name T276
Test name
Test status
Simulation time 89196542545 ps
CPU time 8138.8 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 07:06:53 PM PDT 24
Peak memory 238124 kb
Host smart-f0907843-b5dd-4c47-9420-12b2ee7beaa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091213032 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1091213032
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1559771224
Short name T350
Test name
Test status
Simulation time 3935097032 ps
CPU time 15.33 seconds
Started Jul 27 04:51:19 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 218780 kb
Host smart-2812d2c9-ea52-4891-a403-99ce208186d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559771224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1559771224
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.135309593
Short name T129
Test name
Test status
Simulation time 498779933 ps
CPU time 23.1 seconds
Started Jul 27 04:51:23 PM PDT 24
Finished Jul 27 04:51:46 PM PDT 24
Peak memory 219712 kb
Host smart-dc97749d-5413-4625-a935-fe148f418008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135309593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.135309593
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.707230657
Short name T189
Test name
Test status
Simulation time 264177328 ps
CPU time 11.95 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219732 kb
Host smart-2c6e778d-295a-4954-944d-e0cd0406fe34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707230657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.707230657
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2980951105
Short name T116
Test name
Test status
Simulation time 693191910 ps
CPU time 19.86 seconds
Started Jul 27 04:51:15 PM PDT 24
Finished Jul 27 04:51:35 PM PDT 24
Peak memory 218512 kb
Host smart-b52573df-876b-4bf6-9467-b5114ea4c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980951105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2980951105
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2748177862
Short name T346
Test name
Test status
Simulation time 1825819197 ps
CPU time 23.71 seconds
Started Jul 27 04:51:32 PM PDT 24
Finished Jul 27 04:51:56 PM PDT 24
Peak memory 219168 kb
Host smart-dfe229d4-47a0-4ba3-8930-49cd7d0f82e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748177862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2748177862
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.851090241
Short name T242
Test name
Test status
Simulation time 507775414 ps
CPU time 10 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:20 PM PDT 24
Peak memory 218304 kb
Host smart-ce8c4e39-af1b-41f2-a586-a53cd2ccf8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851090241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.851090241
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2056866667
Short name T29
Test name
Test status
Simulation time 20237637468 ps
CPU time 216.65 seconds
Started Jul 27 04:51:23 PM PDT 24
Finished Jul 27 04:55:00 PM PDT 24
Peak memory 229616 kb
Host smart-8b3b8d36-d332-4a8d-a28a-13d1ee1e654a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056866667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2056866667
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.70407527
Short name T23
Test name
Test status
Simulation time 1319650766 ps
CPU time 18.91 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 219680 kb
Host smart-836429f9-b548-4c20-859c-036126e53791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70407527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.70407527
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2086692702
Short name T304
Test name
Test status
Simulation time 759637303 ps
CPU time 10.53 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:24 PM PDT 24
Peak memory 219764 kb
Host smart-d313869a-1f4f-45ab-b727-7abf311cc9e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086692702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2086692702
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2847843260
Short name T250
Test name
Test status
Simulation time 550664363 ps
CPU time 24.1 seconds
Started Jul 27 04:51:17 PM PDT 24
Finished Jul 27 04:51:41 PM PDT 24
Peak memory 219208 kb
Host smart-984d7379-4152-4b64-874f-b2cf74163933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847843260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2847843260
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2344819501
Short name T294
Test name
Test status
Simulation time 2251978413 ps
CPU time 48.51 seconds
Started Jul 27 04:51:26 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 219816 kb
Host smart-1ef064a9-ea34-493d-94f5-578749b1b869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344819501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2344819501
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.983443929
Short name T42
Test name
Test status
Simulation time 119876376204 ps
CPU time 2244.35 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 05:28:35 PM PDT 24
Peak memory 240652 kb
Host smart-85393368-abcf-40fd-b8d7-3b53346adac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983443929 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.983443929
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4063469455
Short name T165
Test name
Test status
Simulation time 1372241720 ps
CPU time 8.44 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:32 PM PDT 24
Peak memory 218484 kb
Host smart-1df0fcfc-9a0e-4eea-965c-6f7f1d998c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063469455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4063469455
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1463287466
Short name T33
Test name
Test status
Simulation time 5466062342 ps
CPU time 271.58 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:55:01 PM PDT 24
Peak memory 219916 kb
Host smart-a079c408-eae2-4d82-b2eb-a74e32e0e011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463287466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1463287466
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1474561040
Short name T141
Test name
Test status
Simulation time 1381684138 ps
CPU time 18.89 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:46 PM PDT 24
Peak memory 219764 kb
Host smart-c8fef173-10e5-4743-99a3-a79817c50d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474561040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1474561040
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.894581178
Short name T166
Test name
Test status
Simulation time 269215240 ps
CPU time 11.96 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:30 PM PDT 24
Peak memory 219708 kb
Host smart-e59d4e2f-4fce-4c43-8c3e-f71391ba4b03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894581178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.894581178
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1985364915
Short name T18
Test name
Test status
Simulation time 600977409 ps
CPU time 115.71 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:52:44 PM PDT 24
Peak memory 238964 kb
Host smart-f9ca1b88-d65e-47d0-afa3-d8195828be0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985364915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1985364915
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4182922176
Short name T178
Test name
Test status
Simulation time 1568487965 ps
CPU time 19.66 seconds
Started Jul 27 04:50:22 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 219180 kb
Host smart-48633a5c-33c7-4ac9-8dc8-df44a0b60137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182922176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4182922176
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1327057648
Short name T162
Test name
Test status
Simulation time 1091357248 ps
CPU time 53.1 seconds
Started Jul 27 04:50:15 PM PDT 24
Finished Jul 27 04:51:08 PM PDT 24
Peak memory 219696 kb
Host smart-a7c49035-f13f-4358-98d8-4bc6c148ec94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327057648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1327057648
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2046506888
Short name T307
Test name
Test status
Simulation time 194594784 ps
CPU time 8.52 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:19 PM PDT 24
Peak memory 218772 kb
Host smart-c5bf5079-39e2-4674-880d-b434a7572ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046506888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2046506888
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2920579939
Short name T39
Test name
Test status
Simulation time 2757834250 ps
CPU time 18.75 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 219740 kb
Host smart-74923ad6-8571-485a-99ed-d407e582d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920579939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2920579939
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.671504731
Short name T136
Test name
Test status
Simulation time 526128094 ps
CPU time 11.72 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 219652 kb
Host smart-c6369133-748a-4145-be41-374de91df63e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671504731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.671504731
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1727974519
Short name T302
Test name
Test status
Simulation time 346057053 ps
CPU time 19.85 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 04:51:34 PM PDT 24
Peak memory 219488 kb
Host smart-9286e663-31e0-4f6c-a977-20ba066f146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727974519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1727974519
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2483787851
Short name T369
Test name
Test status
Simulation time 555311562 ps
CPU time 42.37 seconds
Started Jul 27 04:51:33 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 219080 kb
Host smart-ed5c2066-1d74-4291-9090-f45c8d7a4b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483787851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2483787851
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3004303808
Short name T56
Test name
Test status
Simulation time 511261718 ps
CPU time 9.99 seconds
Started Jul 27 04:51:22 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 218724 kb
Host smart-1fcabeb6-a1f5-4373-bed2-7cee1e12bd1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004303808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3004303808
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.76524590
Short name T17
Test name
Test status
Simulation time 23489305278 ps
CPU time 388.59 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:57:40 PM PDT 24
Peak memory 226280 kb
Host smart-9ef85223-ed8a-46cb-9760-f38eea0c2a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76524590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.76524590
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3845754666
Short name T170
Test name
Test status
Simulation time 268940165 ps
CPU time 11.94 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:51:48 PM PDT 24
Peak memory 219736 kb
Host smart-b28f88de-fb91-4898-80bf-d2db0059e349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845754666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3845754666
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1345015413
Short name T320
Test name
Test status
Simulation time 2976535633 ps
CPU time 22.61 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 219180 kb
Host smart-3ef64c4b-92cc-4800-8f93-e75e3c312dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345015413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1345015413
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1209193467
Short name T140
Test name
Test status
Simulation time 6312351577 ps
CPU time 70.93 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:52:22 PM PDT 24
Peak memory 222096 kb
Host smart-0c004b9e-c594-4aac-afb3-cdde5d2ae178
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209193467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1209193467
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3448317202
Short name T47
Test name
Test status
Simulation time 166895516226 ps
CPU time 1681.05 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 05:19:13 PM PDT 24
Peak memory 252060 kb
Host smart-51e0e623-b56c-47f7-8aad-c7f205680ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448317202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3448317202
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3483695822
Short name T360
Test name
Test status
Simulation time 339322305 ps
CPU time 8.26 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:51:44 PM PDT 24
Peak memory 218760 kb
Host smart-047fe298-acb7-41c5-9bd5-1ebc9d041f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483695822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3483695822
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1049176254
Short name T259
Test name
Test status
Simulation time 33984798520 ps
CPU time 236.56 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:55:16 PM PDT 24
Peak memory 235344 kb
Host smart-4bd5940c-0d7b-4cf6-a851-99b279dc7d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049176254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1049176254
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2747630646
Short name T150
Test name
Test status
Simulation time 2253408418 ps
CPU time 22.68 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:51:43 PM PDT 24
Peak memory 219720 kb
Host smart-6f858566-fbe2-40ef-b4ae-529682562984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747630646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2747630646
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3830059794
Short name T357
Test name
Test status
Simulation time 186111735 ps
CPU time 10.65 seconds
Started Jul 27 04:51:22 PM PDT 24
Finished Jul 27 04:51:32 PM PDT 24
Peak memory 219740 kb
Host smart-e37642bb-6831-4ede-9e2b-294d261d97ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830059794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3830059794
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.340397228
Short name T287
Test name
Test status
Simulation time 521129244 ps
CPU time 22.93 seconds
Started Jul 27 04:51:09 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 219188 kb
Host smart-5e9fd69d-9c34-4230-8573-46eb08dd806a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340397228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.340397228
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4108622365
Short name T362
Test name
Test status
Simulation time 1358484309 ps
CPU time 64.92 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:52:29 PM PDT 24
Peak memory 219804 kb
Host smart-6eeb644f-a999-446f-bbf7-567d8ff411e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108622365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4108622365
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2880486514
Short name T159
Test name
Test status
Simulation time 170665369 ps
CPU time 8.24 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:51:44 PM PDT 24
Peak memory 218668 kb
Host smart-c04ee773-b7ec-456c-924b-d63136003333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880486514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2880486514
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.934511261
Short name T28
Test name
Test status
Simulation time 11537848483 ps
CPU time 376.25 seconds
Started Jul 27 04:51:38 PM PDT 24
Finished Jul 27 04:57:54 PM PDT 24
Peak memory 226048 kb
Host smart-f021d720-f41c-486b-a326-57e09ac6d259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934511261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.934511261
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4175902782
Short name T197
Test name
Test status
Simulation time 1984967191 ps
CPU time 23.03 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:51:59 PM PDT 24
Peak memory 219704 kb
Host smart-1d0ec5bc-bf16-44eb-96b5-7d56a69f064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175902782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4175902782
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3940235454
Short name T306
Test name
Test status
Simulation time 1073287264 ps
CPU time 12.32 seconds
Started Jul 27 04:51:29 PM PDT 24
Finished Jul 27 04:51:42 PM PDT 24
Peak memory 219716 kb
Host smart-98ad1270-3074-4a0f-af46-6e8da173f1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940235454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3940235454
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2769655874
Short name T138
Test name
Test status
Simulation time 351160733 ps
CPU time 19.8 seconds
Started Jul 27 04:51:28 PM PDT 24
Finished Jul 27 04:51:47 PM PDT 24
Peak memory 219104 kb
Host smart-e65322f7-194f-40c6-88b7-03346c92cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769655874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2769655874
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3808851776
Short name T26
Test name
Test status
Simulation time 1617770435 ps
CPU time 24.69 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 219216 kb
Host smart-5f62ab9a-3351-4671-8a58-372dcf30452b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808851776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3808851776
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.552823636
Short name T59
Test name
Test status
Simulation time 2359999637 ps
CPU time 8.43 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:51:33 PM PDT 24
Peak memory 218868 kb
Host smart-82611a8c-4984-4908-8354-bc71a497a303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552823636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.552823636
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1006727853
Short name T269
Test name
Test status
Simulation time 2827773102 ps
CPU time 194.11 seconds
Started Jul 27 04:51:32 PM PDT 24
Finished Jul 27 04:54:46 PM PDT 24
Peak memory 243304 kb
Host smart-00a60216-15b0-401b-bdeb-c4a9ee6c0dc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006727853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1006727853
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3318311997
Short name T220
Test name
Test status
Simulation time 517174023 ps
CPU time 23.02 seconds
Started Jul 27 04:51:42 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 219732 kb
Host smart-607322f0-cca2-49f3-bb27-74da9a53c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318311997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3318311997
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2018308815
Short name T191
Test name
Test status
Simulation time 275863195 ps
CPU time 12.21 seconds
Started Jul 27 04:51:31 PM PDT 24
Finished Jul 27 04:51:43 PM PDT 24
Peak memory 219784 kb
Host smart-fb29d2ad-a5fa-4ccb-aab3-7da79d87744c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018308815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2018308815
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2242328204
Short name T260
Test name
Test status
Simulation time 1028482112 ps
CPU time 24.22 seconds
Started Jul 27 04:51:12 PM PDT 24
Finished Jul 27 04:51:37 PM PDT 24
Peak memory 218612 kb
Host smart-9acd2dd7-dcbb-4bab-bc54-75989a0b1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242328204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2242328204
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.857706870
Short name T125
Test name
Test status
Simulation time 1762636009 ps
CPU time 28.06 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:51:41 PM PDT 24
Peak memory 219508 kb
Host smart-81311a64-c106-4932-a058-23f4a06c75e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857706870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.857706870
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3151222034
Short name T285
Test name
Test status
Simulation time 1122673396 ps
CPU time 9.77 seconds
Started Jul 27 04:51:37 PM PDT 24
Finished Jul 27 04:51:47 PM PDT 24
Peak memory 218768 kb
Host smart-31a298d9-1271-4a08-af76-e6869a4d95d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151222034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3151222034
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4012227457
Short name T272
Test name
Test status
Simulation time 13637974484 ps
CPU time 212.61 seconds
Started Jul 27 04:51:20 PM PDT 24
Finished Jul 27 04:54:53 PM PDT 24
Peak memory 228968 kb
Host smart-c7bce28a-c624-4b9a-83ea-d1c112050f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012227457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4012227457
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2621554815
Short name T134
Test name
Test status
Simulation time 332864067 ps
CPU time 19.1 seconds
Started Jul 27 04:51:19 PM PDT 24
Finished Jul 27 04:51:38 PM PDT 24
Peak memory 219660 kb
Host smart-047a4cf7-dc77-431f-ae00-a7ddb5f2e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621554815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2621554815
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2192902310
Short name T218
Test name
Test status
Simulation time 267666757 ps
CPU time 11.84 seconds
Started Jul 27 04:51:17 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 219668 kb
Host smart-362c27e5-a736-40a3-863c-5a7cd2cdc3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192902310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2192902310
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1344416455
Short name T267
Test name
Test status
Simulation time 737382156 ps
CPU time 20.31 seconds
Started Jul 27 04:51:19 PM PDT 24
Finished Jul 27 04:51:40 PM PDT 24
Peak memory 218752 kb
Host smart-e4d50a55-71dc-4d30-819d-af53e3223593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344416455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1344416455
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3536019253
Short name T124
Test name
Test status
Simulation time 1707113999 ps
CPU time 70.04 seconds
Started Jul 27 04:51:28 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 221452 kb
Host smart-b0ef4326-caec-4ce5-9ba6-410cc6d461ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536019253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3536019253
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2610326184
Short name T327
Test name
Test status
Simulation time 250276380 ps
CPU time 10.38 seconds
Started Jul 27 04:51:33 PM PDT 24
Finished Jul 27 04:51:44 PM PDT 24
Peak memory 218724 kb
Host smart-18202622-fbe1-48c8-93d9-06fb50a7dd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610326184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2610326184
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2317176845
Short name T230
Test name
Test status
Simulation time 20968862720 ps
CPU time 303.75 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 04:56:18 PM PDT 24
Peak memory 238220 kb
Host smart-3fc19372-ee3d-41c1-8fce-6a7b45cf3cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317176845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2317176845
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1206502655
Short name T233
Test name
Test status
Simulation time 2061494742 ps
CPU time 22.68 seconds
Started Jul 27 04:51:14 PM PDT 24
Finished Jul 27 04:51:37 PM PDT 24
Peak memory 219740 kb
Host smart-96f6a035-9f68-4623-ba22-25b40fe2f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206502655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1206502655
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.951772704
Short name T177
Test name
Test status
Simulation time 1121458023 ps
CPU time 12.45 seconds
Started Jul 27 04:51:36 PM PDT 24
Finished Jul 27 04:51:49 PM PDT 24
Peak memory 219756 kb
Host smart-a3beec6e-2fad-405a-baff-1890affb70f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951772704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.951772704
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.52054724
Short name T313
Test name
Test status
Simulation time 707817369 ps
CPU time 24.85 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 04:52:01 PM PDT 24
Peak memory 219232 kb
Host smart-8d6033b2-9345-479a-a060-2ca0703b345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52054724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.52054724
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1010075001
Short name T184
Test name
Test status
Simulation time 1094470043 ps
CPU time 52.16 seconds
Started Jul 27 04:51:10 PM PDT 24
Finished Jul 27 04:52:03 PM PDT 24
Peak memory 220524 kb
Host smart-3992bdd9-0ed1-410f-98a7-b69ffdf92143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010075001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1010075001
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1707610453
Short name T314
Test name
Test status
Simulation time 916789585 ps
CPU time 8.36 seconds
Started Jul 27 04:51:21 PM PDT 24
Finished Jul 27 04:51:29 PM PDT 24
Peak memory 218768 kb
Host smart-21bc0b41-3699-4500-8ead-11146f251deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707610453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1707610453
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3186538831
Short name T311
Test name
Test status
Simulation time 12357226913 ps
CPU time 215.13 seconds
Started Jul 27 04:51:13 PM PDT 24
Finished Jul 27 04:54:49 PM PDT 24
Peak memory 219952 kb
Host smart-ed659fa1-2ae1-4616-a719-2b86c00c7abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186538831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3186538831
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2079193546
Short name T143
Test name
Test status
Simulation time 1327487234 ps
CPU time 18.88 seconds
Started Jul 27 04:51:30 PM PDT 24
Finished Jul 27 04:51:49 PM PDT 24
Peak memory 219840 kb
Host smart-6b7eb6f2-9b7c-4375-b8ca-d6738210d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079193546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2079193546
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4197739244
Short name T121
Test name
Test status
Simulation time 333687259 ps
CPU time 10.43 seconds
Started Jul 27 04:51:30 PM PDT 24
Finished Jul 27 04:51:41 PM PDT 24
Peak memory 219748 kb
Host smart-8db3c72d-0d9e-421e-af3f-55fc8f18bea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197739244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4197739244
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2371321790
Short name T145
Test name
Test status
Simulation time 1383481874 ps
CPU time 20.26 seconds
Started Jul 27 04:51:29 PM PDT 24
Finished Jul 27 04:51:50 PM PDT 24
Peak memory 219184 kb
Host smart-720db204-6e25-4bef-91fb-577b6b2b5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371321790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2371321790
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3252486757
Short name T303
Test name
Test status
Simulation time 879138421 ps
CPU time 55.85 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:52:20 PM PDT 24
Peak memory 222552 kb
Host smart-68678d30-ea3d-4db5-afc2-346f658f02da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252486757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3252486757
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.527471590
Short name T45
Test name
Test status
Simulation time 77078782464 ps
CPU time 800.97 seconds
Started Jul 27 04:51:35 PM PDT 24
Finished Jul 27 05:04:57 PM PDT 24
Peak memory 236236 kb
Host smart-680c31ad-e729-455d-bac7-23c006946aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527471590 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.527471590
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1300859260
Short name T223
Test name
Test status
Simulation time 663175028 ps
CPU time 8.37 seconds
Started Jul 27 04:51:38 PM PDT 24
Finished Jul 27 04:51:46 PM PDT 24
Peak memory 218724 kb
Host smart-d40e9741-9805-4fda-858d-84c20b86e927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300859260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1300859260
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2842471051
Short name T37
Test name
Test status
Simulation time 7699404965 ps
CPU time 232.85 seconds
Started Jul 27 04:51:18 PM PDT 24
Finished Jul 27 04:55:11 PM PDT 24
Peak memory 219868 kb
Host smart-c7538a60-6bc1-46c5-aacf-d4a9ed2203f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842471051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2842471051
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2493461544
Short name T216
Test name
Test status
Simulation time 1970550365 ps
CPU time 32.55 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:51:57 PM PDT 24
Peak memory 219144 kb
Host smart-4fddc16a-db44-47c8-99ed-2b7271ae7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493461544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2493461544
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3201927427
Short name T268
Test name
Test status
Simulation time 4143200885 ps
CPU time 17.28 seconds
Started Jul 27 04:51:27 PM PDT 24
Finished Jul 27 04:51:44 PM PDT 24
Peak memory 219796 kb
Host smart-6a2dd3c1-be96-4035-ac71-2d2496915a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201927427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3201927427
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2290396670
Short name T292
Test name
Test status
Simulation time 2095602651 ps
CPU time 24.05 seconds
Started Jul 27 04:51:25 PM PDT 24
Finished Jul 27 04:51:50 PM PDT 24
Peak memory 219720 kb
Host smart-73016ebe-4d34-4829-9a48-addae0385ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290396670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2290396670
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.191795491
Short name T244
Test name
Test status
Simulation time 5968948062 ps
CPU time 107.51 seconds
Started Jul 27 04:51:34 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 222116 kb
Host smart-f5d1f430-4ded-472b-ac6d-617df297c0d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191795491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.191795491
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1050672283
Short name T30
Test name
Test status
Simulation time 260956894 ps
CPU time 10.22 seconds
Started Jul 27 04:51:29 PM PDT 24
Finished Jul 27 04:51:40 PM PDT 24
Peak memory 219048 kb
Host smart-08c45964-69e4-4493-851e-53e579518777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050672283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1050672283
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3087683256
Short name T181
Test name
Test status
Simulation time 7010001466 ps
CPU time 222.77 seconds
Started Jul 27 04:51:23 PM PDT 24
Finished Jul 27 04:55:06 PM PDT 24
Peak memory 238336 kb
Host smart-29c11eb1-4c8b-47eb-82ca-a998e7240a5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087683256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3087683256
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1910476409
Short name T340
Test name
Test status
Simulation time 1986533913 ps
CPU time 23.11 seconds
Started Jul 27 04:51:31 PM PDT 24
Finished Jul 27 04:51:54 PM PDT 24
Peak memory 219724 kb
Host smart-479d6812-91c7-446f-8113-60f625b4126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910476409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1910476409
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2845137647
Short name T335
Test name
Test status
Simulation time 351404385 ps
CPU time 10.2 seconds
Started Jul 27 04:51:24 PM PDT 24
Finished Jul 27 04:51:35 PM PDT 24
Peak memory 219724 kb
Host smart-034fa4a2-aa56-4928-9bb3-8ace116fe7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845137647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2845137647
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.121984752
Short name T345
Test name
Test status
Simulation time 8389443033 ps
CPU time 24.9 seconds
Started Jul 27 04:51:11 PM PDT 24
Finished Jul 27 04:51:36 PM PDT 24
Peak memory 219284 kb
Host smart-abd56fbc-e18a-4754-8ad4-c0c02f92a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121984752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.121984752
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1521302500
Short name T169
Test name
Test status
Simulation time 290208871 ps
CPU time 12.77 seconds
Started Jul 27 04:51:32 PM PDT 24
Finished Jul 27 04:51:45 PM PDT 24
Peak memory 219080 kb
Host smart-681fab93-39c9-4453-89fe-2e5479d0c0f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521302500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1521302500
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3280496810
Short name T174
Test name
Test status
Simulation time 688529091 ps
CPU time 8.51 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 218820 kb
Host smart-8bd26c83-62a4-432c-ac3f-a025edd9f48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280496810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3280496810
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2144378659
Short name T214
Test name
Test status
Simulation time 2946629003 ps
CPU time 205.52 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 242712 kb
Host smart-78aa8099-0f30-48c5-b6b3-ff6de5f15429
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144378659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2144378659
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3975272010
Short name T32
Test name
Test status
Simulation time 383527812 ps
CPU time 19.34 seconds
Started Jul 27 04:50:33 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 219688 kb
Host smart-f3f0518f-6096-4c6c-a350-0633524b6236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975272010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3975272010
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2112261569
Short name T262
Test name
Test status
Simulation time 724989568 ps
CPU time 10.15 seconds
Started Jul 27 04:50:28 PM PDT 24
Finished Jul 27 04:50:38 PM PDT 24
Peak memory 219728 kb
Host smart-6f9e5792-dd7a-4386-97f6-1e6886db5969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112261569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2112261569
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1223936728
Short name T319
Test name
Test status
Simulation time 28315687502 ps
CPU time 32.54 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 218936 kb
Host smart-af848639-d4b5-4b68-b0be-19820c08a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223936728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1223936728
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.591016652
Short name T270
Test name
Test status
Simulation time 2338307555 ps
CPU time 29.17 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:51:01 PM PDT 24
Peak memory 219452 kb
Host smart-ad6c1e80-4438-42ae-bcc7-7f82574c2621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591016652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.591016652
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.370770692
Short name T48
Test name
Test status
Simulation time 53445209010 ps
CPU time 2073.74 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 05:25:14 PM PDT 24
Peak memory 237604 kb
Host smart-32dd42be-50cd-4244-a2b4-739cfe514070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370770692 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.370770692
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.704860826
Short name T329
Test name
Test status
Simulation time 993064715 ps
CPU time 9.78 seconds
Started Jul 27 04:50:47 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 219392 kb
Host smart-47981ae4-9b21-45c1-a361-0f8802146fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704860826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.704860826
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1399750979
Short name T151
Test name
Test status
Simulation time 19894984210 ps
CPU time 368.28 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:56:49 PM PDT 24
Peak memory 239256 kb
Host smart-d3c6e408-b365-4992-b3e4-ef495213c434
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399750979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1399750979
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2306691959
Short name T261
Test name
Test status
Simulation time 1447037194 ps
CPU time 19.72 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:51:03 PM PDT 24
Peak memory 219724 kb
Host smart-e0893e00-d13f-4b7f-b147-fdc148204be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306691959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2306691959
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.885293859
Short name T133
Test name
Test status
Simulation time 1271637451 ps
CPU time 11.65 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:50:56 PM PDT 24
Peak memory 219732 kb
Host smart-31480389-23c4-4f50-a259-c44d881bf8ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885293859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.885293859
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2628624132
Short name T156
Test name
Test status
Simulation time 2147925547 ps
CPU time 19.56 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:50:53 PM PDT 24
Peak memory 219304 kb
Host smart-7107f700-2608-4be9-9ac9-d8f8c03a7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628624132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2628624132
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.806243359
Short name T339
Test name
Test status
Simulation time 800071783 ps
CPU time 40.71 seconds
Started Jul 27 04:50:50 PM PDT 24
Finished Jul 27 04:51:31 PM PDT 24
Peak memory 219688 kb
Host smart-2c77e7cc-9070-4cd9-a0dc-9c58400d254b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806243359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.806243359
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.239058695
Short name T225
Test name
Test status
Simulation time 635057008 ps
CPU time 8.13 seconds
Started Jul 27 04:50:44 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 218688 kb
Host smart-7bcbba17-ab9d-468b-9127-38b34f70ae84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239058695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.239058695
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1548492081
Short name T344
Test name
Test status
Simulation time 4970037563 ps
CPU time 257.91 seconds
Started Jul 27 04:50:40 PM PDT 24
Finished Jul 27 04:54:58 PM PDT 24
Peak memory 219924 kb
Host smart-9ca6c4b2-55eb-4331-bf42-d77d19237229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548492081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1548492081
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.423400676
Short name T224
Test name
Test status
Simulation time 347527180 ps
CPU time 19.44 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:51:05 PM PDT 24
Peak memory 219732 kb
Host smart-3880fe1d-72df-4d15-9a22-ecccd3c0bcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423400676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.423400676
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1484166619
Short name T131
Test name
Test status
Simulation time 535205295 ps
CPU time 12.3 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:00 PM PDT 24
Peak memory 219736 kb
Host smart-a4898c48-964e-4e0d-934f-37d47b9b2a57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484166619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1484166619
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4115232427
Short name T206
Test name
Test status
Simulation time 2039957843 ps
CPU time 23.35 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:51:06 PM PDT 24
Peak memory 218660 kb
Host smart-7267138f-27f0-4b8f-86b3-38d74de78f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115232427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4115232427
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2606909085
Short name T193
Test name
Test status
Simulation time 1778497364 ps
CPU time 39.02 seconds
Started Jul 27 04:50:36 PM PDT 24
Finished Jul 27 04:51:15 PM PDT 24
Peak memory 219652 kb
Host smart-4c319d52-f16c-4f5b-83f8-25d02b03b0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606909085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2606909085
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4235807038
Short name T324
Test name
Test status
Simulation time 302565262 ps
CPU time 8.32 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 218728 kb
Host smart-df3b2b2d-5f19-4734-99bc-7994675592ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235807038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4235807038
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2186385921
Short name T200
Test name
Test status
Simulation time 4204091356 ps
CPU time 232.22 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:54:35 PM PDT 24
Peak memory 229936 kb
Host smart-de09057a-667c-4494-8889-f2227b86da80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186385921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2186385921
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.616409302
Short name T337
Test name
Test status
Simulation time 1837372649 ps
CPU time 19.06 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:51:01 PM PDT 24
Peak memory 219756 kb
Host smart-1b52e8ff-a7af-4b3a-b98d-6c51387f600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616409302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.616409302
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1534969445
Short name T290
Test name
Test status
Simulation time 264100722 ps
CPU time 11.65 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:47 PM PDT 24
Peak memory 219664 kb
Host smart-02146631-fddb-4e00-b80c-bce5cf6ea7fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534969445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1534969445
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1119431104
Short name T172
Test name
Test status
Simulation time 6357454950 ps
CPU time 31.9 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:51:13 PM PDT 24
Peak memory 219116 kb
Host smart-09c162bf-9054-49ab-923c-55cb6012e718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119431104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1119431104
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1178627581
Short name T114
Test name
Test status
Simulation time 2305139572 ps
CPU time 38.68 seconds
Started Jul 27 04:50:51 PM PDT 24
Finished Jul 27 04:51:30 PM PDT 24
Peak memory 219368 kb
Host smart-d921a7c5-6322-43d7-8733-14d666f6d36e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178627581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1178627581
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3171483262
Short name T9
Test name
Test status
Simulation time 262884519 ps
CPU time 10.38 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:52 PM PDT 24
Peak memory 218764 kb
Host smart-6c524396-177b-4d50-98e5-337f6702601a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171483262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3171483262
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4269576694
Short name T204
Test name
Test status
Simulation time 2035336759 ps
CPU time 156.18 seconds
Started Jul 27 04:50:45 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 225336 kb
Host smart-f3acaf61-b3b3-4773-8886-d41c32985a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269576694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4269576694
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2817703486
Short name T342
Test name
Test status
Simulation time 497262459 ps
CPU time 23.6 seconds
Started Jul 27 04:50:48 PM PDT 24
Finished Jul 27 04:51:12 PM PDT 24
Peak memory 219744 kb
Host smart-59ed5005-45b2-45fd-a778-dcecc6d0d74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817703486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2817703486
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1384958217
Short name T41
Test name
Test status
Simulation time 271859904 ps
CPU time 12.54 seconds
Started Jul 27 04:50:55 PM PDT 24
Finished Jul 27 04:51:07 PM PDT 24
Peak memory 219732 kb
Host smart-da2e2e2a-d6c0-48e8-9b52-6a12ae28cd5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384958217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1384958217
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2717201561
Short name T7
Test name
Test status
Simulation time 692949745 ps
CPU time 19.65 seconds
Started Jul 27 04:50:49 PM PDT 24
Finished Jul 27 04:51:09 PM PDT 24
Peak memory 219208 kb
Host smart-133e0be7-136f-4db0-920e-bcb8b09681d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717201561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2717201561
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3263771393
Short name T334
Test name
Test status
Simulation time 6942635208 ps
CPU time 130.63 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 219868 kb
Host smart-9156899f-4d7d-496d-ad16-e14c657c6e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263771393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3263771393
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%