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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.68 100.00 98.28 97.45 99.07


Total test records in report: 470
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T298 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.56361201 Jul 28 04:57:13 PM PDT 24 Jul 28 04:57:26 PM PDT 24 1235528329 ps
T299 /workspace/coverage/default/30.rom_ctrl_alert_test.604340872 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:27 PM PDT 24 519873261 ps
T300 /workspace/coverage/default/25.rom_ctrl_alert_test.2335825459 Jul 28 04:57:14 PM PDT 24 Jul 28 04:57:23 PM PDT 24 175037887 ps
T301 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1502667311 Jul 28 04:56:56 PM PDT 24 Jul 28 05:22:43 PM PDT 24 42337024052 ps
T302 /workspace/coverage/default/15.rom_ctrl_stress_all.4215134946 Jul 28 04:57:08 PM PDT 24 Jul 28 04:57:44 PM PDT 24 3276638631 ps
T303 /workspace/coverage/default/11.rom_ctrl_stress_all.511625561 Jul 28 04:56:52 PM PDT 24 Jul 28 04:57:28 PM PDT 24 7688865909 ps
T304 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1650807851 Jul 28 04:57:31 PM PDT 24 Jul 28 04:57:42 PM PDT 24 227409462 ps
T305 /workspace/coverage/default/27.rom_ctrl_stress_all.3229355770 Jul 28 04:57:13 PM PDT 24 Jul 28 04:57:50 PM PDT 24 2236947909 ps
T306 /workspace/coverage/default/7.rom_ctrl_smoke.663731558 Jul 28 04:56:52 PM PDT 24 Jul 28 04:57:17 PM PDT 24 1021257998 ps
T307 /workspace/coverage/default/36.rom_ctrl_smoke.1888722024 Jul 28 04:57:14 PM PDT 24 Jul 28 04:57:34 PM PDT 24 677104297 ps
T308 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.343232010 Jul 28 04:57:19 PM PDT 24 Jul 28 04:57:38 PM PDT 24 347083318 ps
T309 /workspace/coverage/default/48.rom_ctrl_smoke.2793802723 Jul 28 04:58:02 PM PDT 24 Jul 28 04:58:38 PM PDT 24 2047120919 ps
T310 /workspace/coverage/default/49.rom_ctrl_stress_all.2811429595 Jul 28 04:57:38 PM PDT 24 Jul 28 04:58:14 PM PDT 24 801716299 ps
T311 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3085753910 Jul 28 04:57:02 PM PDT 24 Jul 28 04:59:15 PM PDT 24 1972309133 ps
T312 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.444143509 Jul 28 04:57:13 PM PDT 24 Jul 28 05:14:04 PM PDT 24 486716660124 ps
T96 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2714815509 Jul 28 04:56:48 PM PDT 24 Jul 28 04:56:58 PM PDT 24 688658143 ps
T313 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3141919536 Jul 28 04:57:22 PM PDT 24 Jul 28 04:57:41 PM PDT 24 690011682 ps
T314 /workspace/coverage/default/33.rom_ctrl_smoke.1108172920 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:36 PM PDT 24 347883552 ps
T315 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2209194261 Jul 28 04:57:24 PM PDT 24 Jul 28 04:57:47 PM PDT 24 1988269916 ps
T316 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3175474920 Jul 28 04:57:33 PM PDT 24 Jul 28 04:57:43 PM PDT 24 176764376 ps
T317 /workspace/coverage/default/7.rom_ctrl_stress_all.3447364972 Jul 28 04:56:52 PM PDT 24 Jul 28 04:57:35 PM PDT 24 5199264498 ps
T318 /workspace/coverage/default/17.rom_ctrl_alert_test.1142995658 Jul 28 04:57:03 PM PDT 24 Jul 28 04:57:13 PM PDT 24 495778178 ps
T319 /workspace/coverage/default/36.rom_ctrl_stress_all.1558311151 Jul 28 04:57:30 PM PDT 24 Jul 28 04:58:04 PM PDT 24 1057914692 ps
T320 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.502534484 Jul 28 04:57:28 PM PDT 24 Jul 28 05:02:10 PM PDT 24 5121415401 ps
T321 /workspace/coverage/default/20.rom_ctrl_alert_test.386242816 Jul 28 04:57:13 PM PDT 24 Jul 28 04:57:21 PM PDT 24 1499088024 ps
T322 /workspace/coverage/default/24.rom_ctrl_alert_test.3867642646 Jul 28 04:57:07 PM PDT 24 Jul 28 04:57:17 PM PDT 24 1544155489 ps
T323 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2996858173 Jul 28 04:57:10 PM PDT 24 Jul 28 04:57:33 PM PDT 24 529573890 ps
T101 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3523345806 Jul 28 04:56:50 PM PDT 24 Jul 28 05:38:44 PM PDT 24 66779597004 ps
T324 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2664679507 Jul 28 04:57:26 PM PDT 24 Jul 28 04:57:37 PM PDT 24 383108186 ps
T325 /workspace/coverage/default/29.rom_ctrl_smoke.3811854273 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:37 PM PDT 24 1257648675 ps
T326 /workspace/coverage/default/47.rom_ctrl_alert_test.2193573858 Jul 28 04:57:50 PM PDT 24 Jul 28 04:58:01 PM PDT 24 1029487818 ps
T327 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1225512780 Jul 28 04:56:54 PM PDT 24 Jul 28 04:57:07 PM PDT 24 296527771 ps
T328 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.5863811 Jul 28 04:56:52 PM PDT 24 Jul 28 05:00:25 PM PDT 24 13368083005 ps
T329 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.313234433 Jul 28 04:56:57 PM PDT 24 Jul 28 04:57:08 PM PDT 24 186673452 ps
T330 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2128059136 Jul 28 04:57:15 PM PDT 24 Jul 28 04:57:31 PM PDT 24 2068116339 ps
T331 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4223657118 Jul 28 04:56:51 PM PDT 24 Jul 28 04:57:13 PM PDT 24 512750617 ps
T332 /workspace/coverage/default/31.rom_ctrl_smoke.1783700078 Jul 28 04:57:14 PM PDT 24 Jul 28 04:57:47 PM PDT 24 2030202927 ps
T333 /workspace/coverage/default/20.rom_ctrl_stress_all.1109025998 Jul 28 04:57:01 PM PDT 24 Jul 28 04:57:40 PM PDT 24 1043628630 ps
T334 /workspace/coverage/default/31.rom_ctrl_alert_test.895109766 Jul 28 04:57:32 PM PDT 24 Jul 28 04:57:40 PM PDT 24 339510454 ps
T24 /workspace/coverage/default/3.rom_ctrl_sec_cm.1599620965 Jul 28 04:56:45 PM PDT 24 Jul 28 05:00:31 PM PDT 24 369404856 ps
T335 /workspace/coverage/default/46.rom_ctrl_alert_test.2248341042 Jul 28 04:57:24 PM PDT 24 Jul 28 04:57:32 PM PDT 24 281507717 ps
T336 /workspace/coverage/default/39.rom_ctrl_alert_test.301456347 Jul 28 04:57:21 PM PDT 24 Jul 28 04:57:30 PM PDT 24 662083130 ps
T337 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3169171829 Jul 28 04:56:44 PM PDT 24 Jul 28 04:56:55 PM PDT 24 723830620 ps
T338 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2620288258 Jul 28 04:56:53 PM PDT 24 Jul 28 04:57:13 PM PDT 24 346129633 ps
T339 /workspace/coverage/default/45.rom_ctrl_alert_test.2661827784 Jul 28 04:57:49 PM PDT 24 Jul 28 04:58:05 PM PDT 24 2109548394 ps
T340 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2682381683 Jul 28 04:57:12 PM PDT 24 Jul 28 05:00:31 PM PDT 24 22855637519 ps
T341 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1110944491 Jul 28 04:57:20 PM PDT 24 Jul 28 04:57:39 PM PDT 24 674511270 ps
T342 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3373749371 Jul 28 04:56:45 PM PDT 24 Jul 28 04:57:05 PM PDT 24 410549563 ps
T343 /workspace/coverage/default/12.rom_ctrl_smoke.3629619531 Jul 28 04:56:52 PM PDT 24 Jul 28 04:57:12 PM PDT 24 703579707 ps
T344 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.882898993 Jul 28 04:57:13 PM PDT 24 Jul 28 04:57:24 PM PDT 24 3472627009 ps
T345 /workspace/coverage/default/2.rom_ctrl_alert_test.3074315163 Jul 28 04:56:48 PM PDT 24 Jul 28 04:56:57 PM PDT 24 691740454 ps
T346 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2919622731 Jul 28 04:57:01 PM PDT 24 Jul 28 04:57:20 PM PDT 24 1325193771 ps
T347 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1244193263 Jul 28 04:56:51 PM PDT 24 Jul 28 04:57:04 PM PDT 24 260784861 ps
T348 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4019808966 Jul 28 04:57:05 PM PDT 24 Jul 28 04:57:17 PM PDT 24 324850436 ps
T349 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3848358855 Jul 28 04:56:57 PM PDT 24 Jul 28 04:57:10 PM PDT 24 3674643096 ps
T350 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3663313208 Jul 28 04:57:29 PM PDT 24 Jul 28 04:57:48 PM PDT 24 332564591 ps
T351 /workspace/coverage/default/37.rom_ctrl_smoke.1552515598 Jul 28 04:57:29 PM PDT 24 Jul 28 04:57:50 PM PDT 24 346111574 ps
T352 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1762762744 Jul 28 04:57:00 PM PDT 24 Jul 28 04:57:10 PM PDT 24 698832666 ps
T353 /workspace/coverage/default/14.rom_ctrl_smoke.2174483683 Jul 28 04:56:58 PM PDT 24 Jul 28 04:57:21 PM PDT 24 531519932 ps
T354 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1794872370 Jul 28 04:57:26 PM PDT 24 Jul 28 04:59:15 PM PDT 24 1245369215 ps
T355 /workspace/coverage/default/42.rom_ctrl_smoke.720242032 Jul 28 04:57:32 PM PDT 24 Jul 28 04:57:55 PM PDT 24 507664144 ps
T356 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1941669328 Jul 28 04:57:26 PM PDT 24 Jul 28 04:57:38 PM PDT 24 1065329454 ps
T357 /workspace/coverage/default/31.rom_ctrl_stress_all.2259558294 Jul 28 04:57:12 PM PDT 24 Jul 28 04:57:47 PM PDT 24 770182767 ps
T358 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3844535944 Jul 28 04:57:04 PM PDT 24 Jul 28 04:57:26 PM PDT 24 1150061508 ps
T359 /workspace/coverage/default/9.rom_ctrl_stress_all.2774931295 Jul 28 04:56:57 PM PDT 24 Jul 28 04:57:13 PM PDT 24 1165402554 ps
T360 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.683860724 Jul 28 04:57:35 PM PDT 24 Jul 28 04:58:08 PM PDT 24 1974964418 ps
T104 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2413641361 Jul 28 04:57:14 PM PDT 24 Jul 28 06:37:53 PM PDT 24 87916939579 ps
T361 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3141622108 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:28 PM PDT 24 260119009 ps
T362 /workspace/coverage/default/9.rom_ctrl_alert_test.1048705235 Jul 28 04:56:57 PM PDT 24 Jul 28 04:57:06 PM PDT 24 569786147 ps
T363 /workspace/coverage/default/0.rom_ctrl_smoke.444618343 Jul 28 04:56:51 PM PDT 24 Jul 28 04:57:11 PM PDT 24 717610561 ps
T364 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2359455367 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:26 PM PDT 24 698624783 ps
T25 /workspace/coverage/default/4.rom_ctrl_sec_cm.1356910839 Jul 28 04:56:46 PM PDT 24 Jul 28 04:58:45 PM PDT 24 353427612 ps
T365 /workspace/coverage/default/27.rom_ctrl_alert_test.2533325496 Jul 28 04:57:16 PM PDT 24 Jul 28 04:57:24 PM PDT 24 171045999 ps
T366 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1758158053 Jul 28 04:57:37 PM PDT 24 Jul 28 04:57:47 PM PDT 24 210713806 ps
T367 /workspace/coverage/default/13.rom_ctrl_stress_all.377626817 Jul 28 04:56:59 PM PDT 24 Jul 28 04:57:31 PM PDT 24 1594578280 ps
T54 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3453884235 Jul 28 04:56:40 PM PDT 24 Jul 28 04:57:37 PM PDT 24 1090121728 ps
T55 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3327444028 Jul 28 04:56:41 PM PDT 24 Jul 28 04:56:50 PM PDT 24 197359656 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1260966296 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:39 PM PDT 24 993137718 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2714399536 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:43 PM PDT 24 1031885135 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.277596291 Jul 28 04:56:19 PM PDT 24 Jul 28 04:56:28 PM PDT 24 176509851 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.763150471 Jul 28 04:56:25 PM PDT 24 Jul 28 04:56:34 PM PDT 24 676961299 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4116576017 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:48 PM PDT 24 174657972 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1026646501 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:33 PM PDT 24 1123815153 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.348742402 Jul 28 04:56:14 PM PDT 24 Jul 28 04:56:23 PM PDT 24 174224786 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1219029355 Jul 28 04:56:30 PM PDT 24 Jul 28 04:57:24 PM PDT 24 2007128038 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1656818296 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:43 PM PDT 24 253667750 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1784567319 Jul 28 04:56:29 PM PDT 24 Jul 28 04:56:38 PM PDT 24 674982498 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.674768539 Jul 28 04:56:16 PM PDT 24 Jul 28 04:57:12 PM PDT 24 1341666923 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2545849473 Jul 28 04:56:27 PM PDT 24 Jul 28 04:57:22 PM PDT 24 11334695934 ps
T63 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3991877746 Jul 28 04:56:28 PM PDT 24 Jul 28 04:57:33 PM PDT 24 6059153949 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3428158085 Jul 28 04:56:21 PM PDT 24 Jul 28 04:56:39 PM PDT 24 3148443412 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3939247898 Jul 28 04:56:36 PM PDT 24 Jul 28 04:56:46 PM PDT 24 189407576 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3174288519 Jul 28 04:56:30 PM PDT 24 Jul 28 04:56:38 PM PDT 24 174939255 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3452535726 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:41 PM PDT 24 1989402204 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1886646870 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:44 PM PDT 24 261898784 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4122983516 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:30 PM PDT 24 690328302 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2636564949 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:43 PM PDT 24 1020568762 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2093185821 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:42 PM PDT 24 276636101 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2372154197 Jul 28 04:56:34 PM PDT 24 Jul 28 04:56:44 PM PDT 24 517399082 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1128023461 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:37 PM PDT 24 662072908 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2546769313 Jul 28 04:56:43 PM PDT 24 Jul 28 04:56:55 PM PDT 24 180373673 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3672603679 Jul 28 04:56:21 PM PDT 24 Jul 28 04:57:26 PM PDT 24 1523795836 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1101262523 Jul 28 04:56:27 PM PDT 24 Jul 28 04:56:39 PM PDT 24 338002808 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4257823563 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 995277621 ps
T51 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.554380041 Jul 28 04:56:22 PM PDT 24 Jul 28 04:57:42 PM PDT 24 240331015 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2764782917 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:50 PM PDT 24 992074947 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.683688508 Jul 28 04:56:39 PM PDT 24 Jul 28 04:56:50 PM PDT 24 688215770 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2807621228 Jul 28 04:56:38 PM PDT 24 Jul 28 04:56:51 PM PDT 24 661167290 ps
T52 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2942812522 Jul 28 04:56:28 PM PDT 24 Jul 28 04:59:01 PM PDT 24 312233476 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2254192113 Jul 28 04:56:34 PM PDT 24 Jul 28 04:57:56 PM PDT 24 4019600838 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4157467822 Jul 28 04:56:42 PM PDT 24 Jul 28 04:56:52 PM PDT 24 251504460 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3963123201 Jul 28 04:56:38 PM PDT 24 Jul 28 04:56:53 PM PDT 24 990868798 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1202243641 Jul 28 04:56:23 PM PDT 24 Jul 28 04:56:59 PM PDT 24 2761087186 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2393066580 Jul 28 04:56:43 PM PDT 24 Jul 28 04:56:51 PM PDT 24 1035446955 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.226449288 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:53 PM PDT 24 250485088 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1396920949 Jul 28 04:56:38 PM PDT 24 Jul 28 04:59:12 PM PDT 24 1554216686 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1111298026 Jul 28 04:56:24 PM PDT 24 Jul 28 04:56:34 PM PDT 24 2756190756 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.160433121 Jul 28 04:56:27 PM PDT 24 Jul 28 04:57:49 PM PDT 24 1311782829 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3628664665 Jul 28 04:56:24 PM PDT 24 Jul 28 04:57:08 PM PDT 24 1094862319 ps
T389 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2218091301 Jul 28 04:56:36 PM PDT 24 Jul 28 04:56:49 PM PDT 24 688570708 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3817220595 Jul 28 04:56:33 PM PDT 24 Jul 28 04:59:11 PM PDT 24 784918085 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.530108212 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:36 PM PDT 24 1032928855 ps
T391 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2520496804 Jul 28 04:56:41 PM PDT 24 Jul 28 04:56:50 PM PDT 24 183755085 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1248383563 Jul 28 04:56:28 PM PDT 24 Jul 28 04:59:10 PM PDT 24 629236616 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4240664274 Jul 28 04:56:43 PM PDT 24 Jul 28 04:56:53 PM PDT 24 953014053 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2500362146 Jul 28 04:56:41 PM PDT 24 Jul 28 04:56:51 PM PDT 24 706806315 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4229001955 Jul 28 04:56:21 PM PDT 24 Jul 28 04:56:29 PM PDT 24 690399277 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2546706244 Jul 28 04:56:27 PM PDT 24 Jul 28 04:56:35 PM PDT 24 843355939 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1153924635 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 1178578404 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1820092167 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:31 PM PDT 24 1496964856 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3569828351 Jul 28 04:56:25 PM PDT 24 Jul 28 04:56:39 PM PDT 24 257714837 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.168997231 Jul 28 04:56:16 PM PDT 24 Jul 28 04:56:24 PM PDT 24 332795108 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3822540237 Jul 28 04:56:39 PM PDT 24 Jul 28 04:56:47 PM PDT 24 692128033 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1214710220 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:37 PM PDT 24 988089657 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.254804746 Jul 28 04:56:38 PM PDT 24 Jul 28 04:57:44 PM PDT 24 1589502451 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3671260297 Jul 28 04:56:23 PM PDT 24 Jul 28 04:56:35 PM PDT 24 670126182 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3237542896 Jul 28 04:56:17 PM PDT 24 Jul 28 04:56:29 PM PDT 24 341452186 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.652116007 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:46 PM PDT 24 253156277 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3003034588 Jul 28 04:56:37 PM PDT 24 Jul 28 04:56:52 PM PDT 24 254497103 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3715017687 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:47 PM PDT 24 1767060509 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.177673083 Jul 28 04:56:33 PM PDT 24 Jul 28 04:57:29 PM PDT 24 1039018620 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3853188606 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:44 PM PDT 24 504781835 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2947890706 Jul 28 04:56:37 PM PDT 24 Jul 28 04:58:00 PM PDT 24 1387509093 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1195681448 Jul 28 04:56:23 PM PDT 24 Jul 28 04:56:33 PM PDT 24 495429088 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.914900863 Jul 28 04:56:42 PM PDT 24 Jul 28 04:56:51 PM PDT 24 713348590 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2686869690 Jul 28 04:56:38 PM PDT 24 Jul 28 04:56:48 PM PDT 24 991396970 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2401435764 Jul 28 04:56:29 PM PDT 24 Jul 28 04:56:42 PM PDT 24 256270070 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3315425967 Jul 28 04:56:34 PM PDT 24 Jul 28 04:57:36 PM PDT 24 21953209687 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3890536004 Jul 28 04:56:29 PM PDT 24 Jul 28 04:56:39 PM PDT 24 2058591597 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.252508041 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:42 PM PDT 24 250372487 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1284644256 Jul 28 04:56:33 PM PDT 24 Jul 28 04:57:54 PM PDT 24 246994340 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1078271170 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:34 PM PDT 24 333150683 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2300348448 Jul 28 04:56:34 PM PDT 24 Jul 28 04:56:42 PM PDT 24 340606025 ps
T417 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.136416890 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:42 PM PDT 24 512420263 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.735262580 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:37 PM PDT 24 212701776 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1175342702 Jul 28 04:56:41 PM PDT 24 Jul 28 04:56:50 PM PDT 24 185598380 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3909833252 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 496469117 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3499138792 Jul 28 04:56:22 PM PDT 24 Jul 28 04:57:07 PM PDT 24 20257255720 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1011918496 Jul 28 04:56:30 PM PDT 24 Jul 28 04:57:51 PM PDT 24 294392783 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1272076139 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:50 PM PDT 24 263466106 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3680873011 Jul 28 04:56:39 PM PDT 24 Jul 28 04:56:47 PM PDT 24 175102203 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1208989148 Jul 28 04:56:38 PM PDT 24 Jul 28 04:58:03 PM PDT 24 3730235089 ps
T424 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2277036962 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:41 PM PDT 24 169197551 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.936482117 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:32 PM PDT 24 1900860698 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1088309838 Jul 28 04:56:41 PM PDT 24 Jul 28 04:57:47 PM PDT 24 1572315971 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3360886229 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:45 PM PDT 24 1055800521 ps
T427 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4098130394 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:40 PM PDT 24 176614181 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1440200695 Jul 28 04:56:38 PM PDT 24 Jul 28 04:58:01 PM PDT 24 323432988 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1373044342 Jul 28 04:56:36 PM PDT 24 Jul 28 04:58:01 PM PDT 24 404101817 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3616773127 Jul 28 04:56:27 PM PDT 24 Jul 28 04:56:35 PM PDT 24 1104409324 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.40779416 Jul 28 04:56:43 PM PDT 24 Jul 28 04:57:27 PM PDT 24 1078633424 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2929264381 Jul 28 04:56:40 PM PDT 24 Jul 28 04:58:02 PM PDT 24 312230594 ps
T111 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2195551503 Jul 28 04:56:39 PM PDT 24 Jul 28 04:59:14 PM PDT 24 486240899 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2082822805 Jul 28 04:56:16 PM PDT 24 Jul 28 04:57:36 PM PDT 24 249323152 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3994016604 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:49 PM PDT 24 347528514 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3357781929 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:52 PM PDT 24 789596133 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3705335937 Jul 28 04:56:40 PM PDT 24 Jul 28 04:57:18 PM PDT 24 3274977756 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.993715817 Jul 28 04:56:20 PM PDT 24 Jul 28 04:56:34 PM PDT 24 2091306138 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2363399295 Jul 28 04:56:20 PM PDT 24 Jul 28 04:58:56 PM PDT 24 416583837 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.813061881 Jul 28 04:56:38 PM PDT 24 Jul 28 04:56:51 PM PDT 24 4142755998 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3473192530 Jul 28 04:56:32 PM PDT 24 Jul 28 04:56:41 PM PDT 24 726945823 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4155385961 Jul 28 04:56:21 PM PDT 24 Jul 28 04:56:32 PM PDT 24 263263192 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1355770028 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 1229579227 ps
T438 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1818117462 Jul 28 04:56:43 PM PDT 24 Jul 28 04:56:56 PM PDT 24 172532753 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1695930305 Jul 28 04:56:41 PM PDT 24 Jul 28 04:56:51 PM PDT 24 258809299 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1591568772 Jul 28 04:56:34 PM PDT 24 Jul 28 04:56:43 PM PDT 24 365046106 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1378067818 Jul 28 04:56:41 PM PDT 24 Jul 28 04:57:46 PM PDT 24 1563696278 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1050262509 Jul 28 04:56:42 PM PDT 24 Jul 28 04:56:57 PM PDT 24 996730971 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3519959398 Jul 28 04:56:32 PM PDT 24 Jul 28 04:57:15 PM PDT 24 1021278798 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2582196948 Jul 28 04:56:30 PM PDT 24 Jul 28 04:57:52 PM PDT 24 689846372 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2149988432 Jul 28 04:56:40 PM PDT 24 Jul 28 04:59:15 PM PDT 24 2118599124 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3941683931 Jul 28 04:56:20 PM PDT 24 Jul 28 04:56:39 PM PDT 24 1227159213 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3774646646 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:30 PM PDT 24 174417604 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2156713714 Jul 28 04:56:17 PM PDT 24 Jul 28 04:56:29 PM PDT 24 745023685 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3553407989 Jul 28 04:56:20 PM PDT 24 Jul 28 04:56:36 PM PDT 24 178669901 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.523667004 Jul 28 04:56:31 PM PDT 24 Jul 28 04:56:40 PM PDT 24 495950646 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1228999446 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:50 PM PDT 24 507726621 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2268917781 Jul 28 04:56:33 PM PDT 24 Jul 28 04:56:42 PM PDT 24 505685652 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2888297575 Jul 28 04:56:37 PM PDT 24 Jul 28 04:57:20 PM PDT 24 1096365426 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2370953535 Jul 28 04:56:36 PM PDT 24 Jul 28 04:56:45 PM PDT 24 690491428 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.656557950 Jul 28 04:56:27 PM PDT 24 Jul 28 04:56:37 PM PDT 24 249709617 ps
T454 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.465811372 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:44 PM PDT 24 999841983 ps
T455 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.137463716 Jul 28 04:56:42 PM PDT 24 Jul 28 04:56:54 PM PDT 24 272208855 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1143193853 Jul 28 04:56:38 PM PDT 24 Jul 28 04:56:48 PM PDT 24 495876363 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.182963952 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:32 PM PDT 24 540636313 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1157940284 Jul 28 04:56:26 PM PDT 24 Jul 28 04:56:36 PM PDT 24 987009688 ps
T459 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.588060385 Jul 28 04:56:34 PM PDT 24 Jul 28 04:56:46 PM PDT 24 260708009 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.761195757 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:33 PM PDT 24 1071415996 ps
T461 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1471543111 Jul 28 04:56:42 PM PDT 24 Jul 28 04:56:53 PM PDT 24 334699071 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3249066796 Jul 28 04:56:21 PM PDT 24 Jul 28 04:56:31 PM PDT 24 2755440521 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3450395557 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 258340405 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.919502366 Jul 28 04:56:28 PM PDT 24 Jul 28 04:56:38 PM PDT 24 261698399 ps
T464 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1854798940 Jul 28 04:56:40 PM PDT 24 Jul 28 04:56:50 PM PDT 24 264120788 ps
T465 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1979524434 Jul 28 04:56:39 PM PDT 24 Jul 28 04:56:55 PM PDT 24 262701800 ps
T466 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3404890886 Jul 28 04:56:19 PM PDT 24 Jul 28 04:56:30 PM PDT 24 515193209 ps
T467 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.934409088 Jul 28 04:56:22 PM PDT 24 Jul 28 04:56:34 PM PDT 24 360785922 ps
T468 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.293605 Jul 28 04:56:40 PM PDT 24 Jul 28 04:58:03 PM PDT 24 393881856 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3321083054 Jul 28 04:56:40 PM PDT 24 Jul 28 04:58:18 PM PDT 24 66039383424 ps
T469 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3650411768 Jul 28 04:56:42 PM PDT 24 Jul 28 04:57:39 PM PDT 24 2116137426 ps
T470 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2330683600 Jul 28 04:56:27 PM PDT 24 Jul 28 04:56:41 PM PDT 24 260885858 ps

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3955600898
Short name T5
Test name
Test status
Simulation time 36964062886 ps
CPU time 703.35 seconds
Started Jul 28 04:56:54 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 230784 kb
Host smart-738b2ddf-6736-48c6-9b25-c9aaccffa6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955600898 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3955600898
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1648551983
Short name T9
Test name
Test status
Simulation time 57463623916 ps
CPU time 227.63 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 05:00:50 PM PDT 24
Peak memory 231060 kb
Host smart-93d94161-3e7a-49cf-9c0f-4d16132cf3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648551983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1648551983
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3253200085
Short name T44
Test name
Test status
Simulation time 8607349876 ps
CPU time 393.49 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 05:03:20 PM PDT 24
Peak memory 225876 kb
Host smart-0972a3c6-a758-4c0e-beb4-1facc94c6abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253200085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3253200085
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1396920949
Short name T105
Test name
Test status
Simulation time 1554216686 ps
CPU time 154.37 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:59:12 PM PDT 24
Peak memory 213732 kb
Host smart-11c335b5-3d37-4e3e-a883-4b07f1682876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396920949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1396920949
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.664220325
Short name T18
Test name
Test status
Simulation time 876769094 ps
CPU time 119.56 seconds
Started Jul 28 04:56:49 PM PDT 24
Finished Jul 28 04:58:48 PM PDT 24
Peak memory 239052 kb
Host smart-726174ee-11db-4522-939b-53dc89f59d8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664220325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.664220325
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1847811833
Short name T3
Test name
Test status
Simulation time 2055537609 ps
CPU time 10.23 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 218908 kb
Host smart-187c6730-8482-4926-8766-8ccd839c4788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847811833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1847811833
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3991877746
Short name T63
Test name
Test status
Simulation time 6059153949 ps
CPU time 65.67 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:57:33 PM PDT 24
Peak memory 218792 kb
Host smart-48743be8-441c-4612-8cd6-f0cbe8ccf8ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991877746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3991877746
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1284644256
Short name T106
Test name
Test status
Simulation time 246994340 ps
CPU time 80.24 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:57:54 PM PDT 24
Peak memory 212696 kb
Host smart-810367c8-48a6-4bd4-802c-61c22eed43a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284644256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1284644256
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.419014339
Short name T22
Test name
Test status
Simulation time 6596734791 ps
CPU time 32.96 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:53 PM PDT 24
Peak memory 219444 kb
Host smart-ccbab81e-71e7-4000-92e6-ffa7883abd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419014339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.419014339
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3534597862
Short name T11
Test name
Test status
Simulation time 18244638162 ps
CPU time 7995.72 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 07:10:29 PM PDT 24
Peak memory 236232 kb
Host smart-6ffce6f2-8e0f-4bd1-87db-beda60f5a8a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534597862 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3534597862
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.556537492
Short name T8
Test name
Test status
Simulation time 87624518149 ps
CPU time 3406.2 seconds
Started Jul 28 04:57:01 PM PDT 24
Finished Jul 28 05:53:48 PM PDT 24
Peak memory 247716 kb
Host smart-fb3f073f-a315-46cf-96c0-3c6d0eebbcae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556537492 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.556537492
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2620288258
Short name T338
Test name
Test status
Simulation time 346129633 ps
CPU time 19.25 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 219776 kb
Host smart-093c0d48-4ec8-4664-b07b-aa61119fda52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620288258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2620288258
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2149988432
Short name T113
Test name
Test status
Simulation time 2118599124 ps
CPU time 155.1 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:59:15 PM PDT 24
Peak memory 214312 kb
Host smart-c0dc3470-e9f6-4345-b754-215b4ef4532d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149988432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2149988432
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3945631068
Short name T13
Test name
Test status
Simulation time 36269928469 ps
CPU time 1374.81 seconds
Started Jul 28 04:57:10 PM PDT 24
Finished Jul 28 05:20:05 PM PDT 24
Peak memory 234256 kb
Host smart-ad560e5d-3348-4089-b78f-e493a4ab775d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945631068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3945631068
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1277929471
Short name T39
Test name
Test status
Simulation time 516532774 ps
CPU time 37.45 seconds
Started Jul 28 04:57:00 PM PDT 24
Finished Jul 28 04:57:38 PM PDT 24
Peak memory 219396 kb
Host smart-a0f50d40-2868-4a98-9756-7e7cdab99ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277929471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1277929471
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.674768539
Short name T61
Test name
Test status
Simulation time 1341666923 ps
CPU time 56.28 seconds
Started Jul 28 04:56:16 PM PDT 24
Finished Jul 28 04:57:12 PM PDT 24
Peak memory 214764 kb
Host smart-5e8928f4-53e1-403c-a935-0739b64b3478
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674768539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.674768539
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2714815509
Short name T96
Test name
Test status
Simulation time 688658143 ps
CPU time 10.34 seconds
Started Jul 28 04:56:48 PM PDT 24
Finished Jul 28 04:56:58 PM PDT 24
Peak memory 219744 kb
Host smart-e45e9cb4-f893-4162-bb0f-0c0c335c1940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714815509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2714815509
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.277596291
Short name T97
Test name
Test status
Simulation time 176509851 ps
CPU time 8.24 seconds
Started Jul 28 04:56:19 PM PDT 24
Finished Jul 28 04:56:28 PM PDT 24
Peak memory 210484 kb
Host smart-a6b401f5-d59c-4d9a-85d6-58d2fdf2cb8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277596291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.277596291
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3404890886
Short name T466
Test name
Test status
Simulation time 515193209 ps
CPU time 10.29 seconds
Started Jul 28 04:56:19 PM PDT 24
Finished Jul 28 04:56:30 PM PDT 24
Peak memory 210536 kb
Host smart-b741eaa8-b9bf-4d9c-9eb6-0c9b94e63f46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404890886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3404890886
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3237542896
Short name T403
Test name
Test status
Simulation time 341452186 ps
CPU time 11.67 seconds
Started Jul 28 04:56:17 PM PDT 24
Finished Jul 28 04:56:29 PM PDT 24
Peak memory 211608 kb
Host smart-837e4f0d-3466-4f6e-a81f-8f75a925b174
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237542896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3237542896
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3452535726
Short name T373
Test name
Test status
Simulation time 1989402204 ps
CPU time 15.02 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:41 PM PDT 24
Peak memory 217224 kb
Host smart-67aad6d2-3cc5-47ee-bf8e-54815e20873b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452535726 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3452535726
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.168997231
Short name T399
Test name
Test status
Simulation time 332795108 ps
CPU time 8.17 seconds
Started Jul 28 04:56:16 PM PDT 24
Finished Jul 28 04:56:24 PM PDT 24
Peak memory 210924 kb
Host smart-e882a9cd-91dc-4409-be75-30f57dc45724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168997231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.168997231
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3774646646
Short name T446
Test name
Test status
Simulation time 174417604 ps
CPU time 7.95 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:30 PM PDT 24
Peak memory 210296 kb
Host smart-e4263133-ee1c-436e-9331-1da76b5721ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774646646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3774646646
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.348742402
Short name T370
Test name
Test status
Simulation time 174224786 ps
CPU time 8.08 seconds
Started Jul 28 04:56:14 PM PDT 24
Finished Jul 28 04:56:23 PM PDT 24
Peak memory 210320 kb
Host smart-0da5fb43-72ee-4bd4-8d98-0a4404b73f15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348742402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
348742402
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2156713714
Short name T447
Test name
Test status
Simulation time 745023685 ps
CPU time 12.18 seconds
Started Jul 28 04:56:17 PM PDT 24
Finished Jul 28 04:56:29 PM PDT 24
Peak memory 212272 kb
Host smart-bd29beee-29d7-4803-bd56-46cd1eb8882c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156713714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2156713714
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3941683931
Short name T445
Test name
Test status
Simulation time 1227159213 ps
CPU time 19.38 seconds
Started Jul 28 04:56:20 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 218424 kb
Host smart-5b53f998-c4a6-4dce-bc62-ed8baf7c1167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941683931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3941683931
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2082822805
Short name T107
Test name
Test status
Simulation time 249323152 ps
CPU time 79.85 seconds
Started Jul 28 04:56:16 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 213560 kb
Host smart-f08e42d3-8820-405e-b3b6-6936866e86e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082822805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2082822805
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1128023461
Short name T66
Test name
Test status
Simulation time 662072908 ps
CPU time 8.02 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:37 PM PDT 24
Peak memory 210668 kb
Host smart-59bbfdad-7c12-4d90-8b98-06502c442b97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128023461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1128023461
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4257823563
Short name T380
Test name
Test status
Simulation time 995277621 ps
CPU time 9.96 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210408 kb
Host smart-84c8e1a4-d1ea-44a6-bb84-b906f394ce7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257823563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4257823563
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3428158085
Short name T64
Test name
Test status
Simulation time 3148443412 ps
CPU time 17.72 seconds
Started Jul 28 04:56:21 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 211896 kb
Host smart-701cd343-7650-41ce-84e8-4a572200bd67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428158085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3428158085
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.761195757
Short name T460
Test name
Test status
Simulation time 1071415996 ps
CPU time 10.64 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:33 PM PDT 24
Peak memory 217284 kb
Host smart-7511dbd8-938b-4acf-91b0-b1572d3b463f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761195757 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.761195757
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2636564949
Short name T376
Test name
Test status
Simulation time 1020568762 ps
CPU time 15.13 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:43 PM PDT 24
Peak memory 210404 kb
Host smart-affd4a79-9218-4822-9f10-9f0d32de9ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636564949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2636564949
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4229001955
Short name T394
Test name
Test status
Simulation time 690399277 ps
CPU time 8.07 seconds
Started Jul 28 04:56:21 PM PDT 24
Finished Jul 28 04:56:29 PM PDT 24
Peak memory 210356 kb
Host smart-93f141ef-3ffe-40cc-95fd-2ce251677609
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229001955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4229001955
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.936482117
Short name T425
Test name
Test status
Simulation time 1900860698 ps
CPU time 9.88 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:32 PM PDT 24
Peak memory 210240 kb
Host smart-83d4b927-19ad-4803-8985-9f0dd13606ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936482117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
936482117
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3499138792
Short name T78
Test name
Test status
Simulation time 20257255720 ps
CPU time 44.18 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:57:07 PM PDT 24
Peak memory 212084 kb
Host smart-441a238d-c470-4f49-8d95-49f8c2c87175
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499138792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3499138792
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.993715817
Short name T433
Test name
Test status
Simulation time 2091306138 ps
CPU time 13.9 seconds
Started Jul 28 04:56:20 PM PDT 24
Finished Jul 28 04:56:34 PM PDT 24
Peak memory 212452 kb
Host smart-bac33c51-c32c-4267-967c-f83d388444ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993715817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.993715817
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.934409088
Short name T467
Test name
Test status
Simulation time 360785922 ps
CPU time 11.29 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:34 PM PDT 24
Peak memory 218176 kb
Host smart-4f482ac7-e6a6-44e2-b1dd-68d9a4b96233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934409088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.934409088
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2942812522
Short name T52
Test name
Test status
Simulation time 312233476 ps
CPU time 152.86 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:59:01 PM PDT 24
Peak memory 214116 kb
Host smart-eefe4d06-eebf-4e51-a713-38b0727a8b39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942812522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2942812522
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1591568772
Short name T440
Test name
Test status
Simulation time 365046106 ps
CPU time 8.92 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:56:43 PM PDT 24
Peak memory 215616 kb
Host smart-b7054e34-ee54-4681-931b-fa872ddb6a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591568772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1591568772
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4116576017
Short name T59
Test name
Test status
Simulation time 174657972 ps
CPU time 8.09 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:48 PM PDT 24
Peak memory 210872 kb
Host smart-1aadb685-a25f-4d68-b187-7a5e08470f95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116576017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4116576017
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3315425967
Short name T413
Test name
Test status
Simulation time 21953209687 ps
CPU time 61.28 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 213676 kb
Host smart-013d3637-e37b-4315-b550-16311eaae87a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315425967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3315425967
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1656818296
Short name T60
Test name
Test status
Simulation time 253667750 ps
CPU time 10.08 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:43 PM PDT 24
Peak memory 211152 kb
Host smart-5bf58dd4-3ee1-4be4-873e-53d52d2e8137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656818296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1656818296
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.652116007
Short name T404
Test name
Test status
Simulation time 253156277 ps
CPU time 13.36 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:46 PM PDT 24
Peak memory 218260 kb
Host smart-64b38f91-1594-4805-af9c-df4f70565246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652116007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.652116007
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1208989148
Short name T423
Test name
Test status
Simulation time 3730235089 ps
CPU time 85.52 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:58:03 PM PDT 24
Peak memory 212456 kb
Host smart-18517d28-081d-460f-be64-e23d6a76128f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208989148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1208989148
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3939247898
Short name T372
Test name
Test status
Simulation time 189407576 ps
CPU time 9.6 seconds
Started Jul 28 04:56:36 PM PDT 24
Finished Jul 28 04:56:46 PM PDT 24
Peak memory 217724 kb
Host smart-e03a02b1-15b0-4c7a-874a-e990d9b01e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939247898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3939247898
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2300348448
Short name T82
Test name
Test status
Simulation time 340606025 ps
CPU time 8.04 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 210408 kb
Host smart-2c3c862b-6012-4394-9563-a92c1823203f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300348448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2300348448
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3519959398
Short name T443
Test name
Test status
Simulation time 1021278798 ps
CPU time 42.99 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:57:15 PM PDT 24
Peak memory 213928 kb
Host smart-5b08f7f1-8067-44ed-b9b8-f97b5ecee168
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519959398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3519959398
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2277036962
Short name T424
Test name
Test status
Simulation time 169197551 ps
CPU time 8.23 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:41 PM PDT 24
Peak memory 211212 kb
Host smart-f0f8c0b4-6e02-4fb3-9186-c60984cd01dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277036962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2277036962
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3715017687
Short name T406
Test name
Test status
Simulation time 1767060509 ps
CPU time 14.21 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:47 PM PDT 24
Peak memory 217284 kb
Host smart-4313b504-4616-4bf7-9dd1-9dc6ee6e3875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715017687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3715017687
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3817220595
Short name T108
Test name
Test status
Simulation time 784918085 ps
CPU time 157.13 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:59:11 PM PDT 24
Peak memory 213868 kb
Host smart-afa46782-1280-4719-b24c-d8e221bba009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817220595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3817220595
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2093185821
Short name T377
Test name
Test status
Simulation time 276636101 ps
CPU time 8.92 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 216956 kb
Host smart-1081fe9b-9718-46ab-84b5-18759e4001fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093185821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2093185821
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.252508041
Short name T415
Test name
Test status
Simulation time 250372487 ps
CPU time 9.83 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 210508 kb
Host smart-9e5f1d6a-d029-477b-9710-c0dff8b620bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252508041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.252508041
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.177673083
Short name T407
Test name
Test status
Simulation time 1039018620 ps
CPU time 55.85 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 215100 kb
Host smart-0771d0be-c1b2-46ad-ba79-687bdfc192a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177673083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.177673083
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1854798940
Short name T464
Test name
Test status
Simulation time 264120788 ps
CPU time 9.99 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 211508 kb
Host smart-e802a9b6-22f5-4c30-8c10-7225716d9ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854798940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1854798940
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2218091301
Short name T389
Test name
Test status
Simulation time 688570708 ps
CPU time 12.15 seconds
Started Jul 28 04:56:36 PM PDT 24
Finished Jul 28 04:56:49 PM PDT 24
Peak memory 218764 kb
Host smart-3bc742bd-b101-4b2c-bf1e-bdf445966468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218091301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2218091301
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2947890706
Short name T409
Test name
Test status
Simulation time 1387509093 ps
CPU time 82.63 seconds
Started Jul 28 04:56:37 PM PDT 24
Finished Jul 28 04:58:00 PM PDT 24
Peak memory 213520 kb
Host smart-aa2f0cf4-d564-4a4b-b84a-b175ec4566c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947890706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2947890706
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.914900863
Short name T411
Test name
Test status
Simulation time 713348590 ps
CPU time 8.96 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 216920 kb
Host smart-8717bf3a-aca5-457b-a49d-f1ef957bd4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914900863 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.914900863
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3680873011
Short name T422
Test name
Test status
Simulation time 175102203 ps
CPU time 8.02 seconds
Started Jul 28 04:56:39 PM PDT 24
Finished Jul 28 04:56:47 PM PDT 24
Peak memory 210456 kb
Host smart-32da1471-0263-4b4c-a3df-5117fc5d6277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680873011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3680873011
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2888297575
Short name T79
Test name
Test status
Simulation time 1096365426 ps
CPU time 43.13 seconds
Started Jul 28 04:56:37 PM PDT 24
Finished Jul 28 04:57:20 PM PDT 24
Peak memory 210636 kb
Host smart-537562ee-1340-4194-a7d4-ab5206edcda9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888297575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2888297575
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1695930305
Short name T439
Test name
Test status
Simulation time 258809299 ps
CPU time 9.81 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 211312 kb
Host smart-c4260447-7381-41b6-bb0b-ebb8cf9850af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695930305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1695930305
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3357781929
Short name T432
Test name
Test status
Simulation time 789596133 ps
CPU time 11.55 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:52 PM PDT 24
Peak memory 217372 kb
Host smart-acdfd53d-b760-491a-ac2d-abf36290665e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357781929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3357781929
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1373044342
Short name T428
Test name
Test status
Simulation time 404101817 ps
CPU time 84.22 seconds
Started Jul 28 04:56:36 PM PDT 24
Finished Jul 28 04:58:01 PM PDT 24
Peak memory 214480 kb
Host smart-6abed9fc-14f5-419d-8c7b-5a1dae1a45b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373044342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1373044342
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2500362146
Short name T393
Test name
Test status
Simulation time 706806315 ps
CPU time 10.55 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 216516 kb
Host smart-8ef4959b-cee4-4446-bccb-63db26e0647b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500362146 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2500362146
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1228999446
Short name T450
Test name
Test status
Simulation time 507726621 ps
CPU time 9.95 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 210964 kb
Host smart-ca9a1c6d-993b-4393-bc58-be80a1fb123b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228999446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1228999446
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1378067818
Short name T441
Test name
Test status
Simulation time 1563696278 ps
CPU time 65.05 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:57:46 PM PDT 24
Peak memory 213932 kb
Host smart-ba12b069-2d44-41e6-976e-73ce4eaa41cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378067818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1378067818
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1272076139
Short name T421
Test name
Test status
Simulation time 263466106 ps
CPU time 9.81 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 211340 kb
Host smart-177c1bfc-3fba-469c-aa85-72b6c5dc57b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272076139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1272076139
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1050262509
Short name T442
Test name
Test status
Simulation time 996730971 ps
CPU time 14.74 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:56:57 PM PDT 24
Peak memory 218296 kb
Host smart-ccaa4960-c1bf-4fe2-a567-97a4d65d8292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050262509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1050262509
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.293605
Short name T468
Test name
Test status
Simulation time 393881856 ps
CPU time 83.13 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:58:03 PM PDT 24
Peak memory 214824 kb
Host smart-1053a217-9e3a-4f1b-bbca-e140acab4ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_
err.293605
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3327444028
Short name T55
Test name
Test status
Simulation time 197359656 ps
CPU time 9.59 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 217236 kb
Host smart-f3f18552-0f2d-496c-acbc-c06530dd13b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327444028 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3327444028
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4157467822
Short name T383
Test name
Test status
Simulation time 251504460 ps
CPU time 9.98 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:56:52 PM PDT 24
Peak memory 210408 kb
Host smart-b98119f3-2ae8-4d26-b6c9-e0c8e44b7fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157467822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4157467822
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1088309838
Short name T85
Test name
Test status
Simulation time 1572315971 ps
CPU time 66.35 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 218768 kb
Host smart-70a8ef36-9ab8-4d25-8050-780fecebcde2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088309838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1088309838
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.813061881
Short name T434
Test name
Test status
Simulation time 4142755998 ps
CPU time 13.42 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 212304 kb
Host smart-b0ab6a8f-cb03-4b96-b6a4-1b2f94dcf2a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813061881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.813061881
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3963123201
Short name T384
Test name
Test status
Simulation time 990868798 ps
CPU time 14.31 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:56:53 PM PDT 24
Peak memory 217624 kb
Host smart-77abc7cc-36e5-483d-afad-ba6693de0706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963123201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3963123201
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.137463716
Short name T455
Test name
Test status
Simulation time 272208855 ps
CPU time 11.35 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:56:54 PM PDT 24
Peak memory 217432 kb
Host smart-b37c40da-c2e7-4a6d-b6ec-26a9ca571b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137463716 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.137463716
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1143193853
Short name T456
Test name
Test status
Simulation time 495876363 ps
CPU time 9.99 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:56:48 PM PDT 24
Peak memory 210812 kb
Host smart-78c11e06-a841-40bc-9689-4e5685f62de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143193853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1143193853
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.40779416
Short name T430
Test name
Test status
Simulation time 1078633424 ps
CPU time 43.45 seconds
Started Jul 28 04:56:43 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 213664 kb
Host smart-3e93e67f-4327-465d-8430-a524da57b33e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40779416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.40779416
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4240664274
Short name T392
Test name
Test status
Simulation time 953014053 ps
CPU time 9.92 seconds
Started Jul 28 04:56:43 PM PDT 24
Finished Jul 28 04:56:53 PM PDT 24
Peak memory 211300 kb
Host smart-9e2a49c1-29ed-4794-96d7-0d5c8d096bb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240664274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4240664274
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2807621228
Short name T382
Test name
Test status
Simulation time 661167290 ps
CPU time 13.48 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 217336 kb
Host smart-d2fb1d76-fe2a-4b8c-b166-e2f35e1c9f12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807621228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2807621228
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2929264381
Short name T110
Test name
Test status
Simulation time 312230594 ps
CPU time 81.4 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:58:02 PM PDT 24
Peak memory 212700 kb
Host smart-111c9373-1a02-46cc-9248-4dfa004196d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929264381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2929264381
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1979524434
Short name T465
Test name
Test status
Simulation time 262701800 ps
CPU time 10.45 seconds
Started Jul 28 04:56:39 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 215432 kb
Host smart-3492aedb-37c0-4c64-ae11-1b3da315e3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979524434 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1979524434
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2686869690
Short name T81
Test name
Test status
Simulation time 991396970 ps
CPU time 9.64 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:56:48 PM PDT 24
Peak memory 210860 kb
Host smart-512647ff-7254-4693-9944-0a84ea96b672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686869690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2686869690
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3321083054
Short name T84
Test name
Test status
Simulation time 66039383424 ps
CPU time 98 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:58:18 PM PDT 24
Peak memory 218724 kb
Host smart-ae547423-9e5a-4071-a4c2-f82f233e392a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321083054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3321083054
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2520496804
Short name T391
Test name
Test status
Simulation time 183755085 ps
CPU time 8.54 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 211472 kb
Host smart-9d106c0a-64aa-4498-a6a0-2824694567f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520496804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2520496804
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1818117462
Short name T438
Test name
Test status
Simulation time 172532753 ps
CPU time 12.9 seconds
Started Jul 28 04:56:43 PM PDT 24
Finished Jul 28 04:56:56 PM PDT 24
Peak memory 218436 kb
Host smart-4ee24671-19c0-4d78-8e89-4aea5c6a4f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818117462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1818117462
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1471543111
Short name T461
Test name
Test status
Simulation time 334699071 ps
CPU time 10.54 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:56:53 PM PDT 24
Peak memory 216508 kb
Host smart-14026a32-404b-42aa-8474-41495d02557b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471543111 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1471543111
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3822540237
Short name T400
Test name
Test status
Simulation time 692128033 ps
CPU time 8.09 seconds
Started Jul 28 04:56:39 PM PDT 24
Finished Jul 28 04:56:47 PM PDT 24
Peak memory 210772 kb
Host smart-46e9f4c7-49d5-4a98-b9b9-7eca9924f2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822540237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3822540237
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3650411768
Short name T469
Test name
Test status
Simulation time 2116137426 ps
CPU time 56.5 seconds
Started Jul 28 04:56:42 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 218680 kb
Host smart-db4bbc34-ee2e-4659-9e1b-32966aded270
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650411768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3650411768
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2393066580
Short name T385
Test name
Test status
Simulation time 1035446955 ps
CPU time 8.34 seconds
Started Jul 28 04:56:43 PM PDT 24
Finished Jul 28 04:56:51 PM PDT 24
Peak memory 211464 kb
Host smart-11d6eb30-e6ac-4ee5-982c-64283ddf8f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393066580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2393066580
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.683688508
Short name T381
Test name
Test status
Simulation time 688215770 ps
CPU time 11.43 seconds
Started Jul 28 04:56:39 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 217300 kb
Host smart-a4d8809c-e640-45a0-871a-11c930cf5513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683688508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.683688508
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1440200695
Short name T115
Test name
Test status
Simulation time 323432988 ps
CPU time 82.48 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:58:01 PM PDT 24
Peak memory 213456 kb
Host smart-a16a36b7-8ef5-4ac6-aeb4-d8e4ca9353f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440200695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1440200695
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1175342702
Short name T418
Test name
Test status
Simulation time 185598380 ps
CPU time 8.76 seconds
Started Jul 28 04:56:41 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 215292 kb
Host smart-d3583181-66fb-4935-8cf9-f5ab0bbca74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175342702 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1175342702
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2764782917
Short name T74
Test name
Test status
Simulation time 992074947 ps
CPU time 9.68 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:50 PM PDT 24
Peak memory 210388 kb
Host smart-644fd09b-d780-4754-82e2-5eda3f5bf8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764782917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2764782917
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3453884235
Short name T54
Test name
Test status
Simulation time 1090121728 ps
CPU time 56.72 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 214324 kb
Host smart-a5a2aaf8-45c5-40d9-bdb0-93c95aae212a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453884235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3453884235
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2546769313
Short name T95
Test name
Test status
Simulation time 180373673 ps
CPU time 12.09 seconds
Started Jul 28 04:56:43 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 212704 kb
Host smart-7bcde414-3915-43f4-ac93-3eeeb8da77af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546769313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2546769313
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.226449288
Short name T386
Test name
Test status
Simulation time 250485088 ps
CPU time 12.96 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:53 PM PDT 24
Peak memory 218080 kb
Host smart-e4acab19-3439-44f2-b646-e1198ab33c28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226449288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.226449288
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2195551503
Short name T111
Test name
Test status
Simulation time 486240899 ps
CPU time 154.53 seconds
Started Jul 28 04:56:39 PM PDT 24
Finished Jul 28 04:59:14 PM PDT 24
Peak memory 213844 kb
Host smart-e9029b86-d102-464f-b277-2e9e3467d159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195551503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2195551503
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3249066796
Short name T80
Test name
Test status
Simulation time 2755440521 ps
CPU time 10.1 seconds
Started Jul 28 04:56:21 PM PDT 24
Finished Jul 28 04:56:31 PM PDT 24
Peak memory 211004 kb
Host smart-545cd683-8755-400c-b92a-e7d2fe86da51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249066796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3249066796
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3909833252
Short name T419
Test name
Test status
Simulation time 496469117 ps
CPU time 10.19 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210580 kb
Host smart-924c9e0b-23d0-4cea-92bf-dce10798a536
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909833252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3909833252
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3553407989
Short name T448
Test name
Test status
Simulation time 178669901 ps
CPU time 15.78 seconds
Started Jul 28 04:56:20 PM PDT 24
Finished Jul 28 04:56:36 PM PDT 24
Peak memory 210420 kb
Host smart-d12ab8f3-6e69-4eaa-be8a-2f2eec8e6946
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553407989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3553407989
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4155385961
Short name T436
Test name
Test status
Simulation time 263263192 ps
CPU time 10.22 seconds
Started Jul 28 04:56:21 PM PDT 24
Finished Jul 28 04:56:32 PM PDT 24
Peak memory 214564 kb
Host smart-5a449e57-2fe9-4713-a265-147af66b144c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155385961 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4155385961
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1153924635
Short name T396
Test name
Test status
Simulation time 1178578404 ps
CPU time 9.89 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210828 kb
Host smart-d423d430-3113-41df-912a-807f8c09e181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153924635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1153924635
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4122983516
Short name T375
Test name
Test status
Simulation time 690328302 ps
CPU time 8 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:30 PM PDT 24
Peak memory 210312 kb
Host smart-27f674f4-b2b8-4834-b792-1ffb1d68711a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122983516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4122983516
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.919502366
Short name T463
Test name
Test status
Simulation time 261698399 ps
CPU time 9.77 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210328 kb
Host smart-b1d2440d-ad73-428e-9e0a-6291776ecc1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919502366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
919502366
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3672603679
Short name T73
Test name
Test status
Simulation time 1523795836 ps
CPU time 64.93 seconds
Started Jul 28 04:56:21 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 218856 kb
Host smart-bc0cef40-a1c4-4a02-ba25-e198a0085490
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672603679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3672603679
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1820092167
Short name T397
Test name
Test status
Simulation time 1496964856 ps
CPU time 8.39 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:31 PM PDT 24
Peak memory 210692 kb
Host smart-a6df6534-9f8a-4a04-af30-7f430697e3e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820092167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1820092167
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1214710220
Short name T401
Test name
Test status
Simulation time 988089657 ps
CPU time 14.42 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:37 PM PDT 24
Peak memory 217340 kb
Host smart-c1afcdb0-d950-4e29-b5ad-770758b898f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214710220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1214710220
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.554380041
Short name T51
Test name
Test status
Simulation time 240331015 ps
CPU time 79.91 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:57:42 PM PDT 24
Peak memory 213216 kb
Host smart-e086bfb6-bfde-416f-b476-1eb7293089f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554380041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.554380041
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3174288519
Short name T65
Test name
Test status
Simulation time 174939255 ps
CPU time 8.24 seconds
Started Jul 28 04:56:30 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210396 kb
Host smart-c2555b05-ee64-4b4d-aa91-1b69b431c5df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174288519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3174288519
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1026646501
Short name T369
Test name
Test status
Simulation time 1123815153 ps
CPU time 10.35 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:33 PM PDT 24
Peak memory 210496 kb
Host smart-809feb8d-6ee0-4090-bee9-f48375a50eb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026646501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1026646501
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3671260297
Short name T402
Test name
Test status
Simulation time 670126182 ps
CPU time 11.87 seconds
Started Jul 28 04:56:23 PM PDT 24
Finished Jul 28 04:56:35 PM PDT 24
Peak memory 211936 kb
Host smart-3d71835a-1492-4d7c-963a-4144e36f9467
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671260297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3671260297
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.182963952
Short name T457
Test name
Test status
Simulation time 540636313 ps
CPU time 10.28 seconds
Started Jul 28 04:56:22 PM PDT 24
Finished Jul 28 04:56:32 PM PDT 24
Peak memory 216124 kb
Host smart-ff1d79c8-15e4-49ca-873d-25aa04e1e484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182963952 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.182963952
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1195681448
Short name T410
Test name
Test status
Simulation time 495429088 ps
CPU time 9.75 seconds
Started Jul 28 04:56:23 PM PDT 24
Finished Jul 28 04:56:33 PM PDT 24
Peak memory 210828 kb
Host smart-0d284782-5ffe-466d-926c-387115bcb554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195681448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1195681448
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3450395557
Short name T462
Test name
Test status
Simulation time 258340405 ps
CPU time 9.91 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210332 kb
Host smart-76a2b533-6069-4571-82e4-f8995f854790
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450395557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3450395557
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1078271170
Short name T416
Test name
Test status
Simulation time 333150683 ps
CPU time 8.05 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:34 PM PDT 24
Peak memory 210344 kb
Host smart-1d20c77a-ee51-4a25-80dd-19d946de31ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078271170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1078271170
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3628664665
Short name T388
Test name
Test status
Simulation time 1094862319 ps
CPU time 43.34 seconds
Started Jul 28 04:56:24 PM PDT 24
Finished Jul 28 04:57:08 PM PDT 24
Peak memory 218688 kb
Host smart-1401cdc6-efac-4b68-a716-9d612177fea6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628664665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3628664665
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1111298026
Short name T387
Test name
Test status
Simulation time 2756190756 ps
CPU time 9.94 seconds
Started Jul 28 04:56:24 PM PDT 24
Finished Jul 28 04:56:34 PM PDT 24
Peak memory 211344 kb
Host smart-d6a8f7a9-9d34-482d-867d-53b66d6c6353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111298026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1111298026
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3569828351
Short name T398
Test name
Test status
Simulation time 257714837 ps
CPU time 14.08 seconds
Started Jul 28 04:56:25 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 217352 kb
Host smart-aa852410-775b-45e3-8bf5-933d4be935ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569828351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3569828351
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2363399295
Short name T112
Test name
Test status
Simulation time 416583837 ps
CPU time 156.21 seconds
Started Jul 28 04:56:20 PM PDT 24
Finished Jul 28 04:58:56 PM PDT 24
Peak memory 213888 kb
Host smart-96eadc30-c37f-47ca-ba48-b51c6aca10d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363399295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2363399295
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.735262580
Short name T77
Test name
Test status
Simulation time 212701776 ps
CPU time 8.51 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:37 PM PDT 24
Peak memory 210756 kb
Host smart-444d2fae-5904-49c5-bafc-fa86afc0e54a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735262580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.735262580
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2370953535
Short name T452
Test name
Test status
Simulation time 690491428 ps
CPU time 8.36 seconds
Started Jul 28 04:56:36 PM PDT 24
Finished Jul 28 04:56:45 PM PDT 24
Peak memory 210480 kb
Host smart-f397ae11-e633-455d-ac6e-7e0fedc05d07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370953535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2370953535
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1101262523
Short name T379
Test name
Test status
Simulation time 338002808 ps
CPU time 11.92 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 210436 kb
Host smart-a559bfae-6a22-4963-9f65-15154c399f23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101262523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1101262523
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2546706244
Short name T395
Test name
Test status
Simulation time 843355939 ps
CPU time 8.74 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:56:35 PM PDT 24
Peak memory 216496 kb
Host smart-59c8b8fb-80b0-4702-810b-045d7d2785f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546706244 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2546706244
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.523667004
Short name T449
Test name
Test status
Simulation time 495950646 ps
CPU time 9.39 seconds
Started Jul 28 04:56:31 PM PDT 24
Finished Jul 28 04:56:40 PM PDT 24
Peak memory 210536 kb
Host smart-478f3fc5-e046-4de4-bd27-0adbeab137f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523667004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.523667004
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.656557950
Short name T453
Test name
Test status
Simulation time 249709617 ps
CPU time 10.02 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:56:37 PM PDT 24
Peak memory 210296 kb
Host smart-1f592688-c03c-42f0-aac8-d9a874b0d1e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656557950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.656557950
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.530108212
Short name T390
Test name
Test status
Simulation time 1032928855 ps
CPU time 9.95 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:36 PM PDT 24
Peak memory 210268 kb
Host smart-5c10eb10-86cb-4cd0-8d80-0d6c733bb006
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530108212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
530108212
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1202243641
Short name T75
Test name
Test status
Simulation time 2761087186 ps
CPU time 36.2 seconds
Started Jul 28 04:56:23 PM PDT 24
Finished Jul 28 04:56:59 PM PDT 24
Peak memory 218740 kb
Host smart-b4d0aec1-f8ae-4564-b4b7-9d3901d40c93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202243641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1202243641
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3890536004
Short name T414
Test name
Test status
Simulation time 2058591597 ps
CPU time 9.88 seconds
Started Jul 28 04:56:29 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 211460 kb
Host smart-b06bdc8a-0e65-4712-94f1-bee79a46555c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890536004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3890536004
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2330683600
Short name T470
Test name
Test status
Simulation time 260885858 ps
CPU time 13.75 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:56:41 PM PDT 24
Peak memory 218500 kb
Host smart-6283cc9a-b6f1-4f43-9605-d7239c869457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330683600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2330683600
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1248383563
Short name T109
Test name
Test status
Simulation time 629236616 ps
CPU time 161.52 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:59:10 PM PDT 24
Peak memory 215220 kb
Host smart-0e9175a5-57d8-494b-ab10-3c56ff4eba3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248383563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1248383563
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.763150471
Short name T368
Test name
Test status
Simulation time 676961299 ps
CPU time 8.9 seconds
Started Jul 28 04:56:25 PM PDT 24
Finished Jul 28 04:56:34 PM PDT 24
Peak memory 216084 kb
Host smart-c9f8208b-7ed6-40e1-8eb3-5ef6fd8b4c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763150471 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.763150471
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3616773127
Short name T429
Test name
Test status
Simulation time 1104409324 ps
CPU time 8.43 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:56:35 PM PDT 24
Peak memory 210760 kb
Host smart-c7cbc3a4-46fb-4cf7-8197-198ee8ac8d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616773127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3616773127
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1157940284
Short name T458
Test name
Test status
Simulation time 987009688 ps
CPU time 9.64 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:36 PM PDT 24
Peak memory 210972 kb
Host smart-1db2ef7f-a60a-40b7-9e59-4d69af4a9432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157940284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1157940284
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2401435764
Short name T412
Test name
Test status
Simulation time 256270070 ps
CPU time 13 seconds
Started Jul 28 04:56:29 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 217304 kb
Host smart-895567c0-6f87-4702-82ec-1dd68dc86907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401435764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2401435764
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2582196948
Short name T444
Test name
Test status
Simulation time 689846372 ps
CPU time 82.34 seconds
Started Jul 28 04:56:30 PM PDT 24
Finished Jul 28 04:57:52 PM PDT 24
Peak memory 213684 kb
Host smart-f84f801b-7fc1-4dd1-b3a4-5ce39a21ab51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582196948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2582196948
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1784567319
Short name T371
Test name
Test status
Simulation time 674982498 ps
CPU time 9.21 seconds
Started Jul 28 04:56:29 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 216856 kb
Host smart-9cc81296-9763-4fe3-a476-aecc9e9ade19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784567319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1784567319
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1260966296
Short name T56
Test name
Test status
Simulation time 993137718 ps
CPU time 10.05 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:39 PM PDT 24
Peak memory 210836 kb
Host smart-c6cfd734-25b9-4585-a72e-205b4d7d5436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260966296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1260966296
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2545849473
Short name T62
Test name
Test status
Simulation time 11334695934 ps
CPU time 55.57 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 215464 kb
Host smart-8745c49c-0ab9-4560-a5f4-a6e4804566b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545849473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2545849473
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.136416890
Short name T417
Test name
Test status
Simulation time 512420263 ps
CPU time 13.36 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 212376 kb
Host smart-434faefa-31a8-4848-b3cd-0c2a6aa28375
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136416890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.136416890
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4098130394
Short name T427
Test name
Test status
Simulation time 176614181 ps
CPU time 13.09 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:40 PM PDT 24
Peak memory 217356 kb
Host smart-03ee85a3-d24b-43fc-a7eb-e244c99b01c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098130394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4098130394
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.160433121
Short name T114
Test name
Test status
Simulation time 1311782829 ps
CPU time 82.18 seconds
Started Jul 28 04:56:27 PM PDT 24
Finished Jul 28 04:57:49 PM PDT 24
Peak memory 213676 kb
Host smart-46a2194c-297f-4ac4-bfbe-180df3f6b9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160433121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.160433121
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1886646870
Short name T374
Test name
Test status
Simulation time 261898784 ps
CPU time 10.89 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:44 PM PDT 24
Peak memory 217060 kb
Host smart-84a2865a-4d33-4713-8d0f-481ac5f90011
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886646870 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1886646870
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1355770028
Short name T437
Test name
Test status
Simulation time 1229579227 ps
CPU time 9.79 seconds
Started Jul 28 04:56:28 PM PDT 24
Finished Jul 28 04:56:38 PM PDT 24
Peak memory 210412 kb
Host smart-6a413d98-d7e3-4663-bd07-d8a16f4c683c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355770028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1355770028
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1219029355
Short name T94
Test name
Test status
Simulation time 2007128038 ps
CPU time 54.26 seconds
Started Jul 28 04:56:30 PM PDT 24
Finished Jul 28 04:57:24 PM PDT 24
Peak memory 218648 kb
Host smart-8e7420be-e80c-477e-b3c6-c3a28625a91e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219029355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1219029355
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3994016604
Short name T431
Test name
Test status
Simulation time 347528514 ps
CPU time 8.21 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:56:49 PM PDT 24
Peak memory 210924 kb
Host smart-cfaf7703-017f-4d6e-bab5-bed01a5b4c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994016604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3994016604
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.465811372
Short name T454
Test name
Test status
Simulation time 999841983 ps
CPU time 18.31 seconds
Started Jul 28 04:56:26 PM PDT 24
Finished Jul 28 04:56:44 PM PDT 24
Peak memory 216880 kb
Host smart-a3171fdb-6066-41ab-abe5-81cf97c512bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465811372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.465811372
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1011918496
Short name T420
Test name
Test status
Simulation time 294392783 ps
CPU time 81.67 seconds
Started Jul 28 04:56:30 PM PDT 24
Finished Jul 28 04:57:51 PM PDT 24
Peak memory 213644 kb
Host smart-4551915d-1a92-4020-be94-7feece33e924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011918496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1011918496
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3473192530
Short name T435
Test name
Test status
Simulation time 726945823 ps
CPU time 9.09 seconds
Started Jul 28 04:56:32 PM PDT 24
Finished Jul 28 04:56:41 PM PDT 24
Peak memory 217004 kb
Host smart-0c9ce88c-e91b-49d2-ad30-8d4cc2ab791b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473192530 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3473192530
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2372154197
Short name T378
Test name
Test status
Simulation time 517399082 ps
CPU time 9.82 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:56:44 PM PDT 24
Peak memory 210704 kb
Host smart-fba0fdb0-c70e-4487-831c-79e5e5a252a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372154197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2372154197
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3705335937
Short name T83
Test name
Test status
Simulation time 3274977756 ps
CPU time 37.65 seconds
Started Jul 28 04:56:40 PM PDT 24
Finished Jul 28 04:57:18 PM PDT 24
Peak memory 211712 kb
Host smart-3f7587b0-2f17-4dd9-8e60-fefa4bfc04b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705335937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3705335937
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2268917781
Short name T451
Test name
Test status
Simulation time 505685652 ps
CPU time 9.77 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:42 PM PDT 24
Peak memory 211016 kb
Host smart-ad3655ec-7283-4547-855d-33118ddd3373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268917781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2268917781
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.588060385
Short name T459
Test name
Test status
Simulation time 260708009 ps
CPU time 12.6 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:56:46 PM PDT 24
Peak memory 217216 kb
Host smart-59c02f9c-9c32-4778-83d1-4c7a6f2843b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588060385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.588060385
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3853188606
Short name T408
Test name
Test status
Simulation time 504781835 ps
CPU time 10.07 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:44 PM PDT 24
Peak memory 214264 kb
Host smart-dc464406-c828-4943-9272-70f5bc39bfe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853188606 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3853188606
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2714399536
Short name T58
Test name
Test status
Simulation time 1031885135 ps
CPU time 9.85 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:43 PM PDT 24
Peak memory 211004 kb
Host smart-c36c9aa3-d316-4192-b419-24198c7e514d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714399536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2714399536
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.254804746
Short name T76
Test name
Test status
Simulation time 1589502451 ps
CPU time 65.83 seconds
Started Jul 28 04:56:38 PM PDT 24
Finished Jul 28 04:57:44 PM PDT 24
Peak memory 214704 kb
Host smart-86bf47ef-d4b8-498f-b2cc-45163147fa17
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254804746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.254804746
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3360886229
Short name T426
Test name
Test status
Simulation time 1055800521 ps
CPU time 11.88 seconds
Started Jul 28 04:56:33 PM PDT 24
Finished Jul 28 04:56:45 PM PDT 24
Peak memory 211520 kb
Host smart-e6ea7e36-12c3-4b7a-a4de-9b46cd59b7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360886229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3360886229
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3003034588
Short name T405
Test name
Test status
Simulation time 254497103 ps
CPU time 14.28 seconds
Started Jul 28 04:56:37 PM PDT 24
Finished Jul 28 04:56:52 PM PDT 24
Peak memory 217468 kb
Host smart-47cb9f3c-c866-4a32-b700-5b4923cdabd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003034588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3003034588
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2254192113
Short name T53
Test name
Test status
Simulation time 4019600838 ps
CPU time 81.16 seconds
Started Jul 28 04:56:34 PM PDT 24
Finished Jul 28 04:57:56 PM PDT 24
Peak memory 213584 kb
Host smart-a10f38e8-490d-4131-b8e2-969c910cb1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254192113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2254192113
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2462893236
Short name T241
Test name
Test status
Simulation time 287335732 ps
CPU time 9.82 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 218820 kb
Host smart-07d88e88-80fa-4b26-a722-a8a928a0176b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462893236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2462893236
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.456961185
Short name T146
Test name
Test status
Simulation time 2269709658 ps
CPU time 156.73 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 04:59:23 PM PDT 24
Peak memory 225672 kb
Host smart-add66acd-4941-42ba-bc64-441644ba9344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456961185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.456961185
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3793312310
Short name T234
Test name
Test status
Simulation time 1326714080 ps
CPU time 19.93 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:57:06 PM PDT 24
Peak memory 219716 kb
Host smart-614f3293-2a52-4058-8c95-67e26cda3b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793312310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3793312310
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2762533461
Short name T17
Test name
Test status
Simulation time 620916550 ps
CPU time 263.75 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 05:01:17 PM PDT 24
Peak memory 244844 kb
Host smart-fcad18d3-33a4-4239-a15c-97759adcf3ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762533461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2762533461
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.444618343
Short name T363
Test name
Test status
Simulation time 717610561 ps
CPU time 19.99 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:11 PM PDT 24
Peak memory 219220 kb
Host smart-90eba7fc-d351-45d0-942f-7154ba3c0c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444618343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.444618343
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2376528991
Short name T129
Test name
Test status
Simulation time 2876824936 ps
CPU time 31.19 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 219856 kb
Host smart-e6861316-815a-4512-b112-0907c0b6ae7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376528991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2376528991
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.170323077
Short name T46
Test name
Test status
Simulation time 94100907017 ps
CPU time 7648.18 seconds
Started Jul 28 04:56:44 PM PDT 24
Finished Jul 28 07:04:14 PM PDT 24
Peak memory 233308 kb
Host smart-147a8d47-fb6b-4677-be99-c31665a84478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170323077 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.170323077
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4082241207
Short name T225
Test name
Test status
Simulation time 260471027 ps
CPU time 10.23 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 218736 kb
Host smart-276ea388-aad9-45bb-ae6c-c77499d1122a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082241207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4082241207
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2073182131
Short name T134
Test name
Test status
Simulation time 27345321837 ps
CPU time 200.04 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 229256 kb
Host smart-6f607ff1-856b-4034-afd3-f95719cb5c61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073182131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2073182131
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.918209966
Short name T226
Test name
Test status
Simulation time 516747057 ps
CPU time 23.15 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 04:57:11 PM PDT 24
Peak memory 219756 kb
Host smart-d3c8d802-1a04-4692-a946-7b83aa054f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918209966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.918209966
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3169171829
Short name T337
Test name
Test status
Simulation time 723830620 ps
CPU time 10.42 seconds
Started Jul 28 04:56:44 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 219664 kb
Host smart-f6fef7d2-e2b1-4bd8-b6a8-92fd5934e599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169171829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3169171829
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1223615594
Short name T19
Test name
Test status
Simulation time 904126083 ps
CPU time 115.56 seconds
Started Jul 28 04:56:46 PM PDT 24
Finished Jul 28 04:58:42 PM PDT 24
Peak memory 238644 kb
Host smart-8957ce87-a799-4adc-8f31-3a693cd975f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223615594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1223615594
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2226359400
Short name T147
Test name
Test status
Simulation time 528681030 ps
CPU time 24.49 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 218840 kb
Host smart-73fe5931-7221-4ca9-bb49-69d670869c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226359400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2226359400
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2046591384
Short name T218
Test name
Test status
Simulation time 2825022065 ps
CPU time 75.76 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 04:58:09 PM PDT 24
Peak memory 220548 kb
Host smart-f341dddf-3c99-4137-bf85-f0b2e4fa515f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046591384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2046591384
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3218436944
Short name T268
Test name
Test status
Simulation time 258932732 ps
CPU time 10.32 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:07 PM PDT 24
Peak memory 218796 kb
Host smart-c035a87b-1679-4920-a42f-5538f10a5e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218436944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3218436944
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3114160916
Short name T262
Test name
Test status
Simulation time 15725314258 ps
CPU time 168.7 seconds
Started Jul 28 04:57:01 PM PDT 24
Finished Jul 28 04:59:53 PM PDT 24
Peak memory 238316 kb
Host smart-e316e33a-86de-48c4-9607-7ae6ba5dd88f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114160916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3114160916
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2529019833
Short name T291
Test name
Test status
Simulation time 2153995186 ps
CPU time 22.69 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219888 kb
Host smart-bf785318-c462-4b0f-bf87-893f681dba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529019833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2529019833
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1244193263
Short name T347
Test name
Test status
Simulation time 260784861 ps
CPU time 12.54 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:04 PM PDT 24
Peak memory 219704 kb
Host smart-c93c8ba1-1a43-459e-97cd-240a6ad74de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244193263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1244193263
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3437687072
Short name T136
Test name
Test status
Simulation time 690175895 ps
CPU time 19.69 seconds
Started Jul 28 04:56:54 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 219176 kb
Host smart-042f35b5-0e0b-498c-9d5a-ca4bec02a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437687072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3437687072
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1245421972
Short name T273
Test name
Test status
Simulation time 288964191 ps
CPU time 16.23 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 219144 kb
Host smart-52674c55-e170-4384-a3d0-534a17ef3501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245421972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1245421972
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3523345806
Short name T101
Test name
Test status
Simulation time 66779597004 ps
CPU time 2513.43 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 05:38:44 PM PDT 24
Peak memory 244452 kb
Host smart-7998bb06-a788-4855-a751-c267c48038d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523345806 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3523345806
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2220254574
Short name T228
Test name
Test status
Simulation time 991947897 ps
CPU time 15.01 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 04:57:08 PM PDT 24
Peak memory 218780 kb
Host smart-fd284965-486e-4b74-b79e-3cf86544f1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220254574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2220254574
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2677849057
Short name T251
Test name
Test status
Simulation time 8787421375 ps
CPU time 235.25 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 05:00:46 PM PDT 24
Peak memory 236096 kb
Host smart-15e117c4-a405-4b0a-8905-2adb46d6d5d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677849057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2677849057
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.445256562
Short name T205
Test name
Test status
Simulation time 2060230485 ps
CPU time 22.39 seconds
Started Jul 28 04:56:55 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 219764 kb
Host smart-d693e660-b905-4d7f-8d3e-68c72b0ace8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445256562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.445256562
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3848358855
Short name T349
Test name
Test status
Simulation time 3674643096 ps
CPU time 12.4 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:10 PM PDT 24
Peak memory 219804 kb
Host smart-3e0868ea-6edc-46e3-9ca1-3405a0440eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848358855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3848358855
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.788787869
Short name T91
Test name
Test status
Simulation time 527789091 ps
CPU time 22.97 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:20 PM PDT 24
Peak memory 219220 kb
Host smart-deb1c1b7-57bf-403d-9f24-c8fa60488af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788787869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.788787869
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.511625561
Short name T303
Test name
Test status
Simulation time 7688865909 ps
CPU time 35.27 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:28 PM PDT 24
Peak memory 219736 kb
Host smart-aca86e4f-374b-4c79-ba57-3cce48e30740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511625561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.511625561
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1171698451
Short name T128
Test name
Test status
Simulation time 1031546709 ps
CPU time 10.25 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:02 PM PDT 24
Peak memory 218304 kb
Host smart-100c0dad-fab6-4270-a5fa-f126cae8c9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171698451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1171698451
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2889170050
Short name T36
Test name
Test status
Simulation time 19912859511 ps
CPU time 233.06 seconds
Started Jul 28 04:56:55 PM PDT 24
Finished Jul 28 05:00:48 PM PDT 24
Peak memory 240904 kb
Host smart-8fc96319-50cb-4ce4-ba92-1dc95d50222b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889170050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2889170050
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1762762744
Short name T352
Test name
Test status
Simulation time 698832666 ps
CPU time 10.22 seconds
Started Jul 28 04:57:00 PM PDT 24
Finished Jul 28 04:57:10 PM PDT 24
Peak memory 219780 kb
Host smart-cbac0e0e-e165-4f79-afa5-2b563b6dc88a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762762744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1762762744
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3629619531
Short name T343
Test name
Test status
Simulation time 703579707 ps
CPU time 19.61 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:12 PM PDT 24
Peak memory 219496 kb
Host smart-9b621789-5c1d-4fef-a79f-a797c56e60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629619531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3629619531
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2362838915
Short name T68
Test name
Test status
Simulation time 395511295 ps
CPU time 21.49 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 04:57:12 PM PDT 24
Peak memory 219028 kb
Host smart-e0129635-1c6f-4071-b38d-118afca1f928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362838915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2362838915
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2011856660
Short name T260
Test name
Test status
Simulation time 14813574712 ps
CPU time 4701.05 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 06:15:20 PM PDT 24
Peak memory 231932 kb
Host smart-16fdfea1-74dd-45b1-bc00-365d706e6d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011856660 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2011856660
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3270890635
Short name T278
Test name
Test status
Simulation time 172739185 ps
CPU time 8.44 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 218820 kb
Host smart-2c22468b-adf4-4197-8ff7-56322c2d4c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270890635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3270890635
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3085753910
Short name T311
Test name
Test status
Simulation time 1972309133 ps
CPU time 130.77 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 04:59:15 PM PDT 24
Peak memory 234168 kb
Host smart-95e693c0-2e5b-4df2-b5a2-62bfb58159e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085753910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3085753910
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3084725462
Short name T167
Test name
Test status
Simulation time 1382090463 ps
CPU time 18.71 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 219592 kb
Host smart-7f71f2ef-2b8f-43d7-a459-f4c07c17b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084725462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3084725462
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1866850290
Short name T174
Test name
Test status
Simulation time 3988609405 ps
CPU time 16.82 seconds
Started Jul 28 04:57:08 PM PDT 24
Finished Jul 28 04:57:25 PM PDT 24
Peak memory 220060 kb
Host smart-abdc1b94-b053-4699-859d-628c78761d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866850290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1866850290
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4119338763
Short name T181
Test name
Test status
Simulation time 3977122018 ps
CPU time 32.61 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:25 PM PDT 24
Peak memory 218896 kb
Host smart-25fce132-ad89-47d5-9093-02b1c45e3ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119338763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4119338763
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.377626817
Short name T367
Test name
Test status
Simulation time 1594578280 ps
CPU time 31.93 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:31 PM PDT 24
Peak memory 219444 kb
Host smart-8dac4613-a6ab-4436-a8de-026976491739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377626817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.377626817
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3496724185
Short name T102
Test name
Test status
Simulation time 57888335118 ps
CPU time 550 seconds
Started Jul 28 04:57:10 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 232020 kb
Host smart-556e18e9-263f-4c45-9610-2d17a804f67f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496724185 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3496724185
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1886336330
Short name T21
Test name
Test status
Simulation time 167577904 ps
CPU time 8.45 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 218772 kb
Host smart-17d40d8a-dd72-43b7-abbd-dd03b842f81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886336330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1886336330
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1975714417
Short name T279
Test name
Test status
Simulation time 12179220105 ps
CPU time 199.58 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 05:00:26 PM PDT 24
Peak memory 231112 kb
Host smart-ebde0327-95c8-44e5-8757-e179702a6157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975714417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1975714417
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1263631833
Short name T258
Test name
Test status
Simulation time 1031685023 ps
CPU time 21.98 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219744 kb
Host smart-400fe017-c426-4ca3-b114-413891f0a5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263631833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1263631833
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2223326054
Short name T189
Test name
Test status
Simulation time 538462020 ps
CPU time 12.08 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 04:57:14 PM PDT 24
Peak memory 219680 kb
Host smart-69d6cb3c-e7f4-45b0-9c9b-2e38b9d66b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223326054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2223326054
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2174483683
Short name T353
Test name
Test status
Simulation time 531519932 ps
CPU time 23.38 seconds
Started Jul 28 04:56:58 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219180 kb
Host smart-65f1d4d2-1f1c-40f1-a10d-cd6a734f1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174483683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2174483683
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2929411642
Short name T257
Test name
Test status
Simulation time 1619962980 ps
CPU time 76.33 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:58:28 PM PDT 24
Peak memory 220360 kb
Host smart-cec94171-d880-4158-b61b-b9d228b8be6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929411642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2929411642
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3119385969
Short name T43
Test name
Test status
Simulation time 301079447747 ps
CPU time 2327.66 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 05:35:47 PM PDT 24
Peak memory 246980 kb
Host smart-56761ff6-5c12-4fd8-8330-cbbe4d3dc423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119385969 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3119385969
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.398833144
Short name T281
Test name
Test status
Simulation time 508034946 ps
CPU time 10.2 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:08 PM PDT 24
Peak memory 218696 kb
Host smart-8e158273-65ce-448c-be64-88dee81bd7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398833144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.398833144
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.11454082
Short name T288
Test name
Test status
Simulation time 5350715594 ps
CPU time 304.37 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 05:02:09 PM PDT 24
Peak memory 240968 kb
Host smart-88979b33-afb9-43fc-9fdd-d461fbbcf626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11454082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_co
rrupt_sig_fatal_chk.11454082
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3936221783
Short name T275
Test name
Test status
Simulation time 4937333774 ps
CPU time 22.66 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 219796 kb
Host smart-08e5f488-ccf8-47db-aff3-e2db6125bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936221783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3936221783
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1501467874
Short name T173
Test name
Test status
Simulation time 785151221 ps
CPU time 12.33 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 04:57:15 PM PDT 24
Peak memory 219836 kb
Host smart-0dbee21d-6112-4530-ace9-95522fdd7fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501467874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1501467874
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3465356205
Short name T14
Test name
Test status
Simulation time 523329526 ps
CPU time 23.26 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:43 PM PDT 24
Peak memory 219196 kb
Host smart-012c3110-b823-44a1-889c-7c259c39a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465356205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3465356205
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4215134946
Short name T302
Test name
Test status
Simulation time 3276638631 ps
CPU time 36.1 seconds
Started Jul 28 04:57:08 PM PDT 24
Finished Jul 28 04:57:44 PM PDT 24
Peak memory 220004 kb
Host smart-ac18fb92-d0a4-4219-9048-de01f8625a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215134946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4215134946
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3642196147
Short name T283
Test name
Test status
Simulation time 225363827 ps
CPU time 8.56 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 217740 kb
Host smart-7dfb57d7-b301-486a-99d5-a33576bed450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642196147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3642196147
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4240474034
Short name T124
Test name
Test status
Simulation time 6658015716 ps
CPU time 130.12 seconds
Started Jul 28 04:57:00 PM PDT 24
Finished Jul 28 04:59:10 PM PDT 24
Peak memory 225444 kb
Host smart-9ef15d6f-b815-4c8b-9a2e-866adee13eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240474034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4240474034
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3535945623
Short name T206
Test name
Test status
Simulation time 496846182 ps
CPU time 22.26 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219756 kb
Host smart-dbfacb3e-dd95-4f44-86f5-8942b9e8e785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535945623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3535945623
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3582131246
Short name T297
Test name
Test status
Simulation time 832392604 ps
CPU time 10.59 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 04:57:07 PM PDT 24
Peak memory 219744 kb
Host smart-e516a23a-ea02-4c1a-8ebb-9c632ea46bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582131246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3582131246
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1449856563
Short name T211
Test name
Test status
Simulation time 1381034042 ps
CPU time 19.85 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 219172 kb
Host smart-8fa46e30-125d-43ed-a653-f3f89e6d82a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449856563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1449856563
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1550466241
Short name T187
Test name
Test status
Simulation time 5558050440 ps
CPU time 39.06 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:43 PM PDT 24
Peak memory 220476 kb
Host smart-b60135e3-7b03-4507-88c2-b94c59820dce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550466241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1550466241
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1142995658
Short name T318
Test name
Test status
Simulation time 495778178 ps
CPU time 10.07 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 218864 kb
Host smart-4837a96d-2dd8-4f96-864f-bf870ef984e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142995658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1142995658
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2583559278
Short name T150
Test name
Test status
Simulation time 498292641 ps
CPU time 22.48 seconds
Started Jul 28 04:57:00 PM PDT 24
Finished Jul 28 04:57:23 PM PDT 24
Peak memory 219716 kb
Host smart-5124984a-6df5-4141-b5a1-94154cb9b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583559278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2583559278
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.56361201
Short name T298
Test name
Test status
Simulation time 1235528329 ps
CPU time 12.34 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219736 kb
Host smart-75fc0961-3f8c-406a-84c9-d0893a7fea99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56361201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.56361201
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4039991535
Short name T154
Test name
Test status
Simulation time 2110927319 ps
CPU time 23.71 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 04:57:23 PM PDT 24
Peak memory 219200 kb
Host smart-91037b31-03fe-4783-bc09-fbea7cf6e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039991535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4039991535
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2555070068
Short name T224
Test name
Test status
Simulation time 554523440 ps
CPU time 30.31 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 219692 kb
Host smart-80b3b5c6-816c-42c7-b150-1eb7d7ae7490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555070068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2555070068
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.647659526
Short name T152
Test name
Test status
Simulation time 169420744 ps
CPU time 8.28 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:23 PM PDT 24
Peak memory 218748 kb
Host smart-2fe62cd1-b5c3-4e02-9388-ba8b178f6cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647659526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.647659526
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2448110238
Short name T294
Test name
Test status
Simulation time 6175085705 ps
CPU time 255.45 seconds
Started Jul 28 04:56:59 PM PDT 24
Finished Jul 28 05:01:15 PM PDT 24
Peak memory 226340 kb
Host smart-b4fa6e3b-f7e2-455f-9d32-cbb55b9394c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448110238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2448110238
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.461686950
Short name T88
Test name
Test status
Simulation time 333685588 ps
CPU time 19.78 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 219740 kb
Host smart-5a7e9773-6d4d-4c9e-986d-856f804a4d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461686950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.461686950
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4019808966
Short name T348
Test name
Test status
Simulation time 324850436 ps
CPU time 12.37 seconds
Started Jul 28 04:57:05 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 219724 kb
Host smart-787da33f-e3a6-415b-aeac-6427508cec24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019808966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4019808966
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4136757377
Short name T153
Test name
Test status
Simulation time 2305774316 ps
CPU time 23.37 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219388 kb
Host smart-9ebe9d5a-8f45-409c-b3ea-53edd4cbf3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136757377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4136757377
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1284738249
Short name T284
Test name
Test status
Simulation time 368464805 ps
CPU time 13.24 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 219064 kb
Host smart-a10bfc50-08f6-4ba7-949f-256f9dcd5dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284738249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1284738249
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1058004453
Short name T243
Test name
Test status
Simulation time 689409765 ps
CPU time 8.11 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:28 PM PDT 24
Peak memory 218712 kb
Host smart-cf3d70ba-16a7-49ab-a21a-f47be3c6da53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058004453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1058004453
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.502534484
Short name T320
Test name
Test status
Simulation time 5121415401 ps
CPU time 282.03 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 05:02:10 PM PDT 24
Peak memory 239292 kb
Host smart-2139c635-7704-48a8-af5a-d995bf58b397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502534484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.502534484
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3844535944
Short name T358
Test name
Test status
Simulation time 1150061508 ps
CPU time 22.82 seconds
Started Jul 28 04:57:04 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219696 kb
Host smart-d23fe4a5-76cd-4d42-a1d8-e0c1cd67f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844535944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3844535944
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1767333346
Short name T138
Test name
Test status
Simulation time 2324338427 ps
CPU time 12.14 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 219776 kb
Host smart-f8602a44-ad6f-4aeb-aaa4-8dae2f084c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767333346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1767333346
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2884544871
Short name T131
Test name
Test status
Simulation time 925883157 ps
CPU time 19.88 seconds
Started Jul 28 04:57:17 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219236 kb
Host smart-454d0ebd-3f0b-4696-ac13-74dbaf3ba7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884544871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2884544871
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3074315163
Short name T345
Test name
Test status
Simulation time 691740454 ps
CPU time 8.47 seconds
Started Jul 28 04:56:48 PM PDT 24
Finished Jul 28 04:56:57 PM PDT 24
Peak memory 218828 kb
Host smart-6166b5b1-5442-4d0a-8821-cec1b820c3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074315163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3074315163
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.5863811
Short name T328
Test name
Test status
Simulation time 13368083005 ps
CPU time 212.86 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 234712 kb
Host smart-01500f6f-de0b-4d47-86c7-9745d44ccb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5863811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corr
upt_sig_fatal_chk.5863811
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.129432787
Short name T40
Test name
Test status
Simulation time 349878203 ps
CPU time 19.49 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 219712 kb
Host smart-415b8d93-7cc3-43aa-8792-ee7df80f7c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129432787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.129432787
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.313234433
Short name T329
Test name
Test status
Simulation time 186673452 ps
CPU time 10.71 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:08 PM PDT 24
Peak memory 219736 kb
Host smart-d4bc481d-9de4-4f4f-b847-ebec106d383e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313234433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.313234433
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3842639531
Short name T93
Test name
Test status
Simulation time 1313606849 ps
CPU time 20.41 seconds
Started Jul 28 04:56:44 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 219240 kb
Host smart-70ff5949-9d38-4470-aa90-013e63bc6b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842639531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3842639531
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2448705094
Short name T149
Test name
Test status
Simulation time 3109962895 ps
CPU time 24.5 seconds
Started Jul 28 04:56:49 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 219144 kb
Host smart-c8aab3f1-2f9e-4724-920f-cb5b5d8b07fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448705094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2448705094
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.386242816
Short name T321
Test name
Test status
Simulation time 1499088024 ps
CPU time 8.48 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 218760 kb
Host smart-ac154c09-2193-40d9-beb6-b1c661456e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386242816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.386242816
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3753461430
Short name T16
Test name
Test status
Simulation time 7856608868 ps
CPU time 128.72 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:59:31 PM PDT 24
Peak memory 241268 kb
Host smart-3ac9d644-b1dd-48b3-9193-8fa63dbcdda4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753461430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3753461430
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1657888674
Short name T144
Test name
Test status
Simulation time 2061456038 ps
CPU time 22.84 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 219744 kb
Host smart-b4414d9b-8f97-48fc-a41f-1047aa86fe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657888674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1657888674
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2087406799
Short name T29
Test name
Test status
Simulation time 1030143550 ps
CPU time 12.79 seconds
Started Jul 28 04:57:04 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 219700 kb
Host smart-b8e9c8c4-cd09-4428-bccd-6e14b47e89dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087406799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2087406799
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1274746628
Short name T1
Test name
Test status
Simulation time 2009017813 ps
CPU time 22.51 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 219208 kb
Host smart-c19f7e2a-e5ed-42d1-8102-0e386b0cf82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274746628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1274746628
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1109025998
Short name T333
Test name
Test status
Simulation time 1043628630 ps
CPU time 39.32 seconds
Started Jul 28 04:57:01 PM PDT 24
Finished Jul 28 04:57:40 PM PDT 24
Peak memory 219648 kb
Host smart-1a00fd1e-8585-407f-b78c-459ea84fba8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109025998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1109025998
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.782159268
Short name T50
Test name
Test status
Simulation time 33377306743 ps
CPU time 9490.46 seconds
Started Jul 28 04:57:04 PM PDT 24
Finished Jul 28 07:35:16 PM PDT 24
Peak memory 235056 kb
Host smart-fa3d64ee-fa64-4458-8bd3-bd8f35b66d6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782159268 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.782159268
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3336984416
Short name T236
Test name
Test status
Simulation time 249385339 ps
CPU time 10.52 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 218788 kb
Host smart-cf1db7b6-4c7a-466b-bfb0-9de94b85c05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336984416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3336984416
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3530152654
Short name T161
Test name
Test status
Simulation time 36757576835 ps
CPU time 352.85 seconds
Started Jul 28 04:57:01 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 232724 kb
Host smart-b222e0c3-cbb0-4df0-b57f-9e0c8098bb73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530152654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3530152654
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1652702956
Short name T213
Test name
Test status
Simulation time 2055336924 ps
CPU time 23.37 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219720 kb
Host smart-ac45ef3a-e9fc-4b48-8822-1e51fbf919b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652702956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1652702956
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2418538802
Short name T185
Test name
Test status
Simulation time 180476275 ps
CPU time 10.57 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 219812 kb
Host smart-89221eb5-25bb-4574-8f2b-6344b1a52800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418538802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2418538802
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.924478755
Short name T177
Test name
Test status
Simulation time 1886848123 ps
CPU time 23.45 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 218668 kb
Host smart-d5204926-921a-4ab1-a99d-7befb89ed6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924478755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.924478755
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2230972506
Short name T197
Test name
Test status
Simulation time 2138824675 ps
CPU time 36.34 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:56 PM PDT 24
Peak memory 219396 kb
Host smart-b38834a8-b835-4148-bd7b-970382c6a830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230972506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2230972506
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3933630730
Short name T274
Test name
Test status
Simulation time 507700366 ps
CPU time 10.04 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 218692 kb
Host smart-2abd3069-80b3-4c42-bfd0-981347cfae2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933630730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3933630730
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2935972973
Short name T199
Test name
Test status
Simulation time 3164257916 ps
CPU time 193.53 seconds
Started Jul 28 04:57:02 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 219908 kb
Host smart-97c1db00-1076-4117-86f7-880b3dbd1dc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935972973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2935972973
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4265449810
Short name T289
Test name
Test status
Simulation time 991690174 ps
CPU time 22.52 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:25 PM PDT 24
Peak memory 219760 kb
Host smart-949bb53d-e30c-4271-a6a5-d80855a5111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265449810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4265449810
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3906437994
Short name T223
Test name
Test status
Simulation time 269772485 ps
CPU time 12.28 seconds
Started Jul 28 04:57:03 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 219804 kb
Host smart-e27c8088-13df-496c-b166-ce1e838fbee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906437994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3906437994
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2479043730
Short name T254
Test name
Test status
Simulation time 534815158 ps
CPU time 22.98 seconds
Started Jul 28 04:57:05 PM PDT 24
Finished Jul 28 04:57:28 PM PDT 24
Peak memory 219176 kb
Host smart-13528270-82a0-4694-bd44-c0d68b76a675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479043730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2479043730
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4152454068
Short name T200
Test name
Test status
Simulation time 1947923475 ps
CPU time 57.16 seconds
Started Jul 28 04:57:04 PM PDT 24
Finished Jul 28 04:58:02 PM PDT 24
Peak memory 220120 kb
Host smart-6932376f-0f7d-4745-ac4d-27c14f0309b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152454068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4152454068
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3478110759
Short name T47
Test name
Test status
Simulation time 15212885706 ps
CPU time 3182.71 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 05:50:09 PM PDT 24
Peak memory 230124 kb
Host smart-0d277adc-740c-4785-b61e-b1a08075b7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478110759 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3478110759
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1836683272
Short name T133
Test name
Test status
Simulation time 664291903 ps
CPU time 8.11 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 218544 kb
Host smart-db1ec778-b472-435e-84e4-b12815ef15ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836683272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1836683272
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.696140391
Short name T10
Test name
Test status
Simulation time 2550576041 ps
CPU time 205.6 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 05:00:33 PM PDT 24
Peak memory 242604 kb
Host smart-d3f2189f-af05-42c4-942e-436574988ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696140391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.696140391
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2514624368
Short name T41
Test name
Test status
Simulation time 2746591235 ps
CPU time 18.88 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 219812 kb
Host smart-21abb01f-949c-4dc5-8c70-5dda3d81be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514624368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2514624368
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.882898993
Short name T344
Test name
Test status
Simulation time 3472627009 ps
CPU time 10.36 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:24 PM PDT 24
Peak memory 219776 kb
Host smart-437935a7-3bd8-4158-99f7-fb8bb35be871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882898993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.882898993
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2328475818
Short name T207
Test name
Test status
Simulation time 1443100200 ps
CPU time 19.96 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 219240 kb
Host smart-d4e4bc8e-18ef-4107-b197-f5156f38da6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328475818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2328475818
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2815750668
Short name T143
Test name
Test status
Simulation time 370799398 ps
CPU time 26.71 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:49 PM PDT 24
Peak memory 219332 kb
Host smart-46757050-e381-496a-b5d7-c07f8e0c2f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815750668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2815750668
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3867642646
Short name T322
Test name
Test status
Simulation time 1544155489 ps
CPU time 10.15 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 218760 kb
Host smart-61b02472-769b-4a08-9861-67bd19fad7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867642646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3867642646
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1515090988
Short name T227
Test name
Test status
Simulation time 6524347151 ps
CPU time 246.04 seconds
Started Jul 28 04:57:07 PM PDT 24
Finished Jul 28 05:01:13 PM PDT 24
Peak memory 238848 kb
Host smart-ca9a5fa3-e4a2-4e12-a46e-81d5d17e6e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515090988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1515090988
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1030337354
Short name T122
Test name
Test status
Simulation time 1975941275 ps
CPU time 22.21 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 219748 kb
Host smart-03c4a087-f9b0-4b3b-9cdf-8b94c2d59c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030337354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1030337354
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3141622108
Short name T361
Test name
Test status
Simulation time 260119009 ps
CPU time 12.14 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:28 PM PDT 24
Peak memory 219720 kb
Host smart-54961fa5-c742-49b2-a948-24370f80cd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141622108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3141622108
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1388522309
Short name T121
Test name
Test status
Simulation time 2099744850 ps
CPU time 22.61 seconds
Started Jul 28 04:57:09 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 219180 kb
Host smart-f1404c1a-07c6-4474-b7dd-f25470d053fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388522309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1388522309
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3608561443
Short name T165
Test name
Test status
Simulation time 713743337 ps
CPU time 27.01 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:41 PM PDT 24
Peak memory 219672 kb
Host smart-bfd3bbd3-99dc-4c1d-ad42-a99f79db9770
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608561443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3608561443
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.444143509
Short name T312
Test name
Test status
Simulation time 486716660124 ps
CPU time 1010.2 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 237784 kb
Host smart-85dec128-1863-4691-b491-b76cb85edb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444143509 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.444143509
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2335825459
Short name T300
Test name
Test status
Simulation time 175037887 ps
CPU time 8.34 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:23 PM PDT 24
Peak memory 218852 kb
Host smart-d0217bd0-6f68-4178-a6a1-64ef5ecbda29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335825459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2335825459
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1356601352
Short name T33
Test name
Test status
Simulation time 4166771592 ps
CPU time 241.21 seconds
Started Jul 28 04:57:25 PM PDT 24
Finished Jul 28 05:01:31 PM PDT 24
Peak memory 230080 kb
Host smart-e2be182b-dafe-40c6-993f-df38f047c948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356601352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1356601352
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.787383327
Short name T229
Test name
Test status
Simulation time 627312277 ps
CPU time 22.86 seconds
Started Jul 28 04:57:08 PM PDT 24
Finished Jul 28 04:57:31 PM PDT 24
Peak memory 219712 kb
Host smart-a73494e1-3d6e-4bbc-9394-559b61b03f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787383327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.787383327
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2359455367
Short name T364
Test name
Test status
Simulation time 698624783 ps
CPU time 10.11 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219688 kb
Host smart-07f9696f-c97a-4493-b8b9-55dad6c4d704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359455367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2359455367
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1338139337
Short name T72
Test name
Test status
Simulation time 2015355165 ps
CPU time 23.44 seconds
Started Jul 28 04:57:11 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 219284 kb
Host smart-9ca900ad-a4b4-4ab8-94b4-ee7730b63c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338139337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1338139337
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.305138443
Short name T166
Test name
Test status
Simulation time 2129635814 ps
CPU time 68.78 seconds
Started Jul 28 04:57:11 PM PDT 24
Finished Jul 28 04:58:19 PM PDT 24
Peak memory 220892 kb
Host smart-d9a7b428-0b4f-4e27-8bd3-870011afe7ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305138443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.305138443
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2091687208
Short name T203
Test name
Test status
Simulation time 250026247 ps
CPU time 10.16 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 218656 kb
Host smart-17134c4a-d49b-440c-9bd5-c81b1e0bf462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091687208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2091687208
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2487758362
Short name T261
Test name
Test status
Simulation time 13746017564 ps
CPU time 168.63 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 224988 kb
Host smart-69e7b299-1525-4594-9cb5-099c0aca8219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487758362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2487758362
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2996858173
Short name T323
Test name
Test status
Simulation time 529573890 ps
CPU time 22.8 seconds
Started Jul 28 04:57:10 PM PDT 24
Finished Jul 28 04:57:33 PM PDT 24
Peak memory 219764 kb
Host smart-d80a04b3-7582-4919-bd87-e8eee464e1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996858173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2996858173
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2664679507
Short name T324
Test name
Test status
Simulation time 383108186 ps
CPU time 10.59 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219700 kb
Host smart-081b7982-be1e-462c-9583-b2f53c1974f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664679507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2664679507
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1705191034
Short name T293
Test name
Test status
Simulation time 1932609493 ps
CPU time 23.09 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 218624 kb
Host smart-04d9f7a4-02f1-4739-a771-ed1ad7b39013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705191034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1705191034
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1892381294
Short name T220
Test name
Test status
Simulation time 1528272809 ps
CPU time 37.34 seconds
Started Jul 28 04:57:09 PM PDT 24
Finished Jul 28 04:57:46 PM PDT 24
Peak memory 219684 kb
Host smart-a9367b69-f102-4dce-89f1-6807023c0d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892381294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1892381294
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2533325496
Short name T365
Test name
Test status
Simulation time 171045999 ps
CPU time 8.25 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:24 PM PDT 24
Peak memory 218796 kb
Host smart-9390ad78-349f-439d-be84-012e3049a0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533325496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2533325496
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2116888299
Short name T248
Test name
Test status
Simulation time 14454950122 ps
CPU time 371.35 seconds
Started Jul 28 04:57:09 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 236708 kb
Host smart-fe2a5743-4392-4916-bac3-749d8254db0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116888299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2116888299
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4066129108
Short name T184
Test name
Test status
Simulation time 507600774 ps
CPU time 22.74 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219692 kb
Host smart-6e692862-705d-48f8-854e-24f6510dec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066129108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4066129108
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.474941491
Short name T240
Test name
Test status
Simulation time 801540558 ps
CPU time 10.25 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 219740 kb
Host smart-85c074d1-65f4-4863-bebd-34b2e06acbb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474941491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.474941491
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.455071633
Short name T137
Test name
Test status
Simulation time 2159824289 ps
CPU time 20.09 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:41 PM PDT 24
Peak memory 218652 kb
Host smart-b485ed8c-dc82-4026-b926-e7e2c5625bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455071633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.455071633
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3229355770
Short name T305
Test name
Test status
Simulation time 2236947909 ps
CPU time 37.37 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219708 kb
Host smart-217d5782-55f7-43aa-aeaf-00726740c065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229355770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3229355770
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1900134370
Short name T168
Test name
Test status
Simulation time 1174791391 ps
CPU time 10.09 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 218796 kb
Host smart-33959fd3-99ce-4377-a954-f3725fac798b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900134370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1900134370
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2682381683
Short name T340
Test name
Test status
Simulation time 22855637519 ps
CPU time 199.05 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 219016 kb
Host smart-76f1b7ac-b9f2-4d72-8fdd-255a4b714a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682381683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2682381683
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3141919536
Short name T313
Test name
Test status
Simulation time 690011682 ps
CPU time 18.7 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:41 PM PDT 24
Peak memory 219756 kb
Host smart-4b79ccea-0d6c-48d7-8e92-7f2df85387ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141919536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3141919536
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1536630656
Short name T204
Test name
Test status
Simulation time 950302816 ps
CPU time 12.68 seconds
Started Jul 28 04:57:09 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 219748 kb
Host smart-8b41795c-25e1-49c2-a59b-faf8d38f1c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536630656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1536630656
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1167015349
Short name T233
Test name
Test status
Simulation time 516642902 ps
CPU time 23.23 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:35 PM PDT 24
Peak memory 219160 kb
Host smart-a291fcfd-1995-47ea-956e-cb8c84075293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167015349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1167015349
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2144612003
Short name T266
Test name
Test status
Simulation time 273478401 ps
CPU time 15.78 seconds
Started Jul 28 04:57:06 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 219312 kb
Host smart-1f15e738-0b2f-4dbe-97b3-45237f00e816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144612003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2144612003
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3625864710
Short name T103
Test name
Test status
Simulation time 42235927555 ps
CPU time 787.96 seconds
Started Jul 28 04:57:25 PM PDT 24
Finished Jul 28 05:10:34 PM PDT 24
Peak memory 231624 kb
Host smart-9a43b938-c8ef-41d4-a7cc-72bf767944c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625864710 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3625864710
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2291183723
Short name T57
Test name
Test status
Simulation time 345431709 ps
CPU time 8.23 seconds
Started Jul 28 04:57:18 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 218716 kb
Host smart-d7649a80-6919-47cb-9ba8-28afe9dd7bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291183723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2291183723
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2258421886
Short name T42
Test name
Test status
Simulation time 12164306483 ps
CPU time 360.44 seconds
Started Jul 28 04:57:18 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 231168 kb
Host smart-ce4ae5ae-e5ae-4507-bd03-05343ff9598d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258421886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2258421886
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4213981322
Short name T172
Test name
Test status
Simulation time 2605218282 ps
CPU time 22.43 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:52 PM PDT 24
Peak memory 219776 kb
Host smart-b623af53-b70f-4cf0-b332-52066ea03029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213981322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4213981322
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2128059136
Short name T330
Test name
Test status
Simulation time 2068116339 ps
CPU time 16.26 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:31 PM PDT 24
Peak memory 219720 kb
Host smart-60088a04-4f53-4937-8f21-7fc28e432de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128059136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2128059136
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3811854273
Short name T325
Test name
Test status
Simulation time 1257648675 ps
CPU time 20.68 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219172 kb
Host smart-e8ec920b-4a87-4605-a0e8-80063e8c4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811854273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3811854273
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2260120108
Short name T286
Test name
Test status
Simulation time 539325779 ps
CPU time 34.75 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219328 kb
Host smart-e849ff84-b82b-48fa-9f0f-5b9bf6b3c714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260120108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2260120108
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3416073905
Short name T28
Test name
Test status
Simulation time 259442358 ps
CPU time 9.92 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 218724 kb
Host smart-76618da3-599c-4d53-98e3-a6968c0aae3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416073905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3416073905
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3237465222
Short name T27
Test name
Test status
Simulation time 6435992817 ps
CPU time 249.78 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 05:00:59 PM PDT 24
Peak memory 239364 kb
Host smart-3a6ac852-8b31-4dba-a5d5-f910d642e93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237465222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3237465222
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3373749371
Short name T342
Test name
Test status
Simulation time 410549563 ps
CPU time 19.63 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 219728 kb
Host smart-71ac5adf-2358-43a4-aca2-e3d97bac8245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373749371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3373749371
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2839527943
Short name T100
Test name
Test status
Simulation time 697349061 ps
CPU time 10.82 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:03 PM PDT 24
Peak memory 219712 kb
Host smart-b7322515-672c-41c1-a55d-cb04b8a4696a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839527943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2839527943
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1599620965
Short name T24
Test name
Test status
Simulation time 369404856 ps
CPU time 226.32 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 239352 kb
Host smart-d9720fe6-7f6d-4d4e-975b-b333abb00342
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599620965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1599620965
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1935135221
Short name T186
Test name
Test status
Simulation time 361396957 ps
CPU time 20.56 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 04:57:10 PM PDT 24
Peak memory 219292 kb
Host smart-8f9ffff2-462e-4e73-98e0-9c94d7ee61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935135221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1935135221
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.770791560
Short name T188
Test name
Test status
Simulation time 1044125183 ps
CPU time 55.33 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 04:57:43 PM PDT 24
Peak memory 220536 kb
Host smart-baf07402-0a22-4086-8820-f5a12416de02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770791560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.770791560
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.604340872
Short name T299
Test name
Test status
Simulation time 519873261 ps
CPU time 10.17 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 218784 kb
Host smart-b24331f5-f301-44e0-8db8-1ad6b08c77ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604340872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.604340872
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1794872370
Short name T354
Test name
Test status
Simulation time 1245369215 ps
CPU time 109.76 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:59:15 PM PDT 24
Peak memory 238000 kb
Host smart-f078938a-8eaa-4859-bf8f-45cd4e57df68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794872370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1794872370
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3663313208
Short name T350
Test name
Test status
Simulation time 332564591 ps
CPU time 18.84 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:48 PM PDT 24
Peak memory 219732 kb
Host smart-c2626700-1ce1-4126-ac70-3c6f61da870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663313208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3663313208
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1941669328
Short name T356
Test name
Test status
Simulation time 1065329454 ps
CPU time 11.64 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:38 PM PDT 24
Peak memory 219320 kb
Host smart-97296bd0-8559-4f03-8392-5847d80c7cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941669328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1941669328
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3567904254
Short name T71
Test name
Test status
Simulation time 2385779747 ps
CPU time 23.33 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 219248 kb
Host smart-a50beb20-aaab-4b81-ad5b-3d9d9a0bc3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567904254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3567904254
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2413641361
Short name T104
Test name
Test status
Simulation time 87916939579 ps
CPU time 6037.73 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 06:37:53 PM PDT 24
Peak memory 236224 kb
Host smart-5efa24c6-9ac7-4c2e-84b5-d43a1820c10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413641361 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2413641361
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.895109766
Short name T334
Test name
Test status
Simulation time 339510454 ps
CPU time 8.09 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:40 PM PDT 24
Peak memory 218792 kb
Host smart-985f1045-39a2-46a3-a321-b15e3bfd3cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895109766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.895109766
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.952120501
Short name T164
Test name
Test status
Simulation time 3287970777 ps
CPU time 226.23 seconds
Started Jul 28 04:57:38 PM PDT 24
Finished Jul 28 05:01:25 PM PDT 24
Peak memory 238372 kb
Host smart-1da611ac-bda1-43a4-9dd1-8a8a606cda0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952120501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.952120501
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.278948732
Short name T119
Test name
Test status
Simulation time 346929708 ps
CPU time 18.87 seconds
Started Jul 28 04:57:37 PM PDT 24
Finished Jul 28 04:57:56 PM PDT 24
Peak memory 219764 kb
Host smart-e94f290c-6315-45a0-bbbd-283da553f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278948732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.278948732
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.931423161
Short name T194
Test name
Test status
Simulation time 350780132 ps
CPU time 10.47 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:24 PM PDT 24
Peak memory 219712 kb
Host smart-4973e701-52c3-4373-b920-95953b4f3f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931423161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.931423161
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1783700078
Short name T332
Test name
Test status
Simulation time 2030202927 ps
CPU time 32.97 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 219272 kb
Host smart-4ec729f0-d2c4-40d7-86ed-090670426c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783700078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1783700078
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2259558294
Short name T357
Test name
Test status
Simulation time 770182767 ps
CPU time 34.71 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 219816 kb
Host smart-60550b9a-2bc5-44a8-9fd6-cf81d95e2f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259558294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2259558294
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2291999903
Short name T49
Test name
Test status
Simulation time 93829499408 ps
CPU time 1046.34 seconds
Started Jul 28 04:57:12 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 236812 kb
Host smart-c361dcbe-4779-4951-b58b-f2cd8750ffa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291999903 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2291999903
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3980559252
Short name T20
Test name
Test status
Simulation time 4258488875 ps
CPU time 14.77 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:41 PM PDT 24
Peak memory 218828 kb
Host smart-0de16cf5-4201-4e18-9a9b-2da53226c486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980559252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3980559252
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3030363009
Short name T191
Test name
Test status
Simulation time 71157108485 ps
CPU time 403.32 seconds
Started Jul 28 04:57:25 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 240908 kb
Host smart-1ce45933-a277-4bb9-9f6f-49cd2643770c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030363009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3030363009
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.862488964
Short name T23
Test name
Test status
Simulation time 8229026431 ps
CPU time 22.84 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:57:53 PM PDT 24
Peak memory 219776 kb
Host smart-794d910c-20ff-49d5-8389-107b4dc54005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862488964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.862488964
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3175474920
Short name T316
Test name
Test status
Simulation time 176764376 ps
CPU time 10.25 seconds
Started Jul 28 04:57:33 PM PDT 24
Finished Jul 28 04:57:43 PM PDT 24
Peak memory 219712 kb
Host smart-9976f262-f875-46d7-a54f-8b23e2310224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175474920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3175474920
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3747477909
Short name T259
Test name
Test status
Simulation time 514122721 ps
CPU time 23.42 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:57:51 PM PDT 24
Peak memory 219220 kb
Host smart-c9896641-f2e1-4311-a9ba-5e77df2fc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747477909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3747477909
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3347444801
Short name T265
Test name
Test status
Simulation time 9745415560 ps
CPU time 59.65 seconds
Started Jul 28 04:57:18 PM PDT 24
Finished Jul 28 04:58:18 PM PDT 24
Peak memory 221924 kb
Host smart-105d2d7f-d213-477e-b59f-4e76c7bb5ab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347444801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3347444801
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3118229715
Short name T253
Test name
Test status
Simulation time 2248291513 ps
CPU time 9.76 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 218816 kb
Host smart-028b6d98-9bf6-4bdd-9a9c-823439d3f4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118229715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3118229715
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1504119919
Short name T90
Test name
Test status
Simulation time 4504047131 ps
CPU time 233.39 seconds
Started Jul 28 04:57:17 PM PDT 24
Finished Jul 28 05:01:10 PM PDT 24
Peak memory 243936 kb
Host smart-73f46e29-d2ba-4eaf-afb7-9b636fd52c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504119919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1504119919
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.126327293
Short name T276
Test name
Test status
Simulation time 496977775 ps
CPU time 22.81 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219800 kb
Host smart-f2b9c904-02c7-472f-89d4-82bf1c8a2e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126327293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.126327293
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2163022723
Short name T98
Test name
Test status
Simulation time 361130897 ps
CPU time 10.28 seconds
Started Jul 28 04:57:17 PM PDT 24
Finished Jul 28 04:57:28 PM PDT 24
Peak memory 219732 kb
Host smart-349056d0-574a-4c5e-983e-7f108d6db5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163022723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2163022723
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1108172920
Short name T314
Test name
Test status
Simulation time 347883552 ps
CPU time 20.22 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:36 PM PDT 24
Peak memory 219188 kb
Host smart-71192a64-92fb-43db-bece-55c11853e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108172920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1108172920
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3355808049
Short name T169
Test name
Test status
Simulation time 368548428 ps
CPU time 28.85 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:44 PM PDT 24
Peak memory 219372 kb
Host smart-e345e3df-0726-4668-a292-0c3dd78561cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355808049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3355808049
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2191933945
Short name T242
Test name
Test status
Simulation time 86411531266 ps
CPU time 3460.78 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 05:55:09 PM PDT 24
Peak memory 233100 kb
Host smart-afd7ce36-6928-4e11-b42f-95f46c3a8504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191933945 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2191933945
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.172592249
Short name T280
Test name
Test status
Simulation time 324153294 ps
CPU time 10.01 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 218760 kb
Host smart-8cc0faaf-c85c-4643-989d-ac8629cbe9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172592249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.172592249
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4055124265
Short name T170
Test name
Test status
Simulation time 2230253436 ps
CPU time 177.23 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 05:00:19 PM PDT 24
Peak memory 238468 kb
Host smart-30fa4f17-8a62-4333-8982-a343dc586148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055124265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4055124265
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2209194261
Short name T315
Test name
Test status
Simulation time 1988269916 ps
CPU time 22.98 seconds
Started Jul 28 04:57:24 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 219760 kb
Host smart-dc6617ec-2d5a-46da-902e-86c7438c5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209194261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2209194261
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1496144977
Short name T120
Test name
Test status
Simulation time 769881256 ps
CPU time 10.82 seconds
Started Jul 28 04:57:15 PM PDT 24
Finished Jul 28 04:57:26 PM PDT 24
Peak memory 219744 kb
Host smart-cf20676f-9750-4373-ab33-937584d2527f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496144977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1496144977
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4293874270
Short name T118
Test name
Test status
Simulation time 532530607 ps
CPU time 22.78 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:49 PM PDT 24
Peak memory 218928 kb
Host smart-4a587d95-0366-4356-ae8c-26094f8b494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293874270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4293874270
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2260939518
Short name T245
Test name
Test status
Simulation time 11477610823 ps
CPU time 46.27 seconds
Started Jul 28 04:57:17 PM PDT 24
Finished Jul 28 04:58:03 PM PDT 24
Peak memory 220452 kb
Host smart-04768f19-32e6-4ecb-a253-a433ce333574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260939518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2260939518
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3276993325
Short name T180
Test name
Test status
Simulation time 1076201012 ps
CPU time 9.96 seconds
Started Jul 28 04:57:17 PM PDT 24
Finished Jul 28 04:57:27 PM PDT 24
Peak memory 218764 kb
Host smart-7c0ece28-9556-4caa-91a7-4e8f3043e80f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276993325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3276993325
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.385696320
Short name T34
Test name
Test status
Simulation time 9316769050 ps
CPU time 295.04 seconds
Started Jul 28 04:57:38 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 234888 kb
Host smart-8f322d43-eca2-4c7e-b318-b11615c94660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385696320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.385696320
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.683860724
Short name T360
Test name
Test status
Simulation time 1974964418 ps
CPU time 32.79 seconds
Started Jul 28 04:57:35 PM PDT 24
Finished Jul 28 04:58:08 PM PDT 24
Peak memory 219664 kb
Host smart-61d97686-18cd-458e-a26a-bce180ffba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683860724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.683860724
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.695150567
Short name T38
Test name
Test status
Simulation time 350413665 ps
CPU time 10.66 seconds
Started Jul 28 04:57:18 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 219740 kb
Host smart-ac5a5705-da51-4755-9ed0-77c352314d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695150567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.695150567
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2058042885
Short name T255
Test name
Test status
Simulation time 2113183677 ps
CPU time 23.99 seconds
Started Jul 28 04:57:13 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219180 kb
Host smart-53ba1213-a217-4769-9ad4-f8f2b2f457e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058042885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2058042885
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1191038763
Short name T264
Test name
Test status
Simulation time 667459403 ps
CPU time 28.3 seconds
Started Jul 28 04:57:16 PM PDT 24
Finished Jul 28 04:57:45 PM PDT 24
Peak memory 218348 kb
Host smart-79cb40b0-837d-45dc-8e9f-ed9bd55a3777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191038763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1191038763
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.75804939
Short name T183
Test name
Test status
Simulation time 1010861336 ps
CPU time 14.78 seconds
Started Jul 28 04:57:19 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 218720 kb
Host smart-fb6a59f8-c986-4534-ac9e-c2d4d594254b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75804939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.75804939
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3509132363
Short name T130
Test name
Test status
Simulation time 6347197400 ps
CPU time 183.53 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 225248 kb
Host smart-8b63bc89-b992-44c7-9804-f2bb41e04ca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509132363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3509132363
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.343232010
Short name T308
Test name
Test status
Simulation time 347083318 ps
CPU time 19.15 seconds
Started Jul 28 04:57:19 PM PDT 24
Finished Jul 28 04:57:38 PM PDT 24
Peak memory 219720 kb
Host smart-484c2653-0eb4-4fc9-ae88-9a2731fc5138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343232010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.343232010
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3410018867
Short name T141
Test name
Test status
Simulation time 449710459 ps
CPU time 12.4 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 219696 kb
Host smart-e1cb3f5d-4671-426a-9546-5a2b6218790c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410018867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3410018867
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1888722024
Short name T307
Test name
Test status
Simulation time 677104297 ps
CPU time 20.18 seconds
Started Jul 28 04:57:14 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 219112 kb
Host smart-d829bc73-58b9-46b9-8c93-bff4c6555a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888722024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1888722024
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1558311151
Short name T319
Test name
Test status
Simulation time 1057914692 ps
CPU time 34.12 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:58:04 PM PDT 24
Peak memory 219784 kb
Host smart-b1552bb3-7b93-4db0-9a19-05d74d8e4038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558311151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1558311151
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2992449025
Short name T26
Test name
Test status
Simulation time 269554519 ps
CPU time 10.13 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:42 PM PDT 24
Peak memory 218888 kb
Host smart-0015559c-62c5-4f96-b2f0-c470d5d9c772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992449025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2992449025
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2247246161
Short name T176
Test name
Test status
Simulation time 5369227518 ps
CPU time 292.52 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 05:02:13 PM PDT 24
Peak memory 234364 kb
Host smart-6bc1c9b9-82d9-424e-a053-84d4dd38ed78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247246161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2247246161
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1110944491
Short name T341
Test name
Test status
Simulation time 674511270 ps
CPU time 18.75 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 219736 kb
Host smart-bc0511e3-3394-47e4-8146-49af04b5aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110944491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1110944491
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1919854770
Short name T123
Test name
Test status
Simulation time 360120776 ps
CPU time 10.43 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:31 PM PDT 24
Peak memory 219748 kb
Host smart-d5a6b8ab-a071-4a50-a3ea-7828cac45356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919854770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1919854770
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1552515598
Short name T351
Test name
Test status
Simulation time 346111574 ps
CPU time 20.51 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219068 kb
Host smart-9aba72a3-da2f-4f41-b6e3-1e7b760c1f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552515598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1552515598
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.406651948
Short name T182
Test name
Test status
Simulation time 6614929471 ps
CPU time 54.78 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:58:15 PM PDT 24
Peak memory 221064 kb
Host smart-bda6abb1-c7ba-4b7c-aed5-b1b400d08935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406651948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.406651948
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1198431858
Short name T219
Test name
Test status
Simulation time 173915699 ps
CPU time 8.38 seconds
Started Jul 28 04:57:34 PM PDT 24
Finished Jul 28 04:57:42 PM PDT 24
Peak memory 218848 kb
Host smart-21edb734-6e37-4016-9b13-f4f0a6c9547d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198431858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1198431858
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1699162212
Short name T216
Test name
Test status
Simulation time 5000531116 ps
CPU time 141.56 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:59:42 PM PDT 24
Peak memory 234204 kb
Host smart-6c88d352-b011-476c-b87f-1ffb021183db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699162212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1699162212
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3903996158
Short name T192
Test name
Test status
Simulation time 344195003 ps
CPU time 19.71 seconds
Started Jul 28 04:57:19 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 219824 kb
Host smart-9b5063e3-5160-4318-9af6-75701f550698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903996158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3903996158
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.835262755
Short name T89
Test name
Test status
Simulation time 1355508754 ps
CPU time 12.22 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 219760 kb
Host smart-a4296466-3265-4013-b7d7-74b581009354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835262755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.835262755
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4251626273
Short name T263
Test name
Test status
Simulation time 535897605 ps
CPU time 22.72 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:52 PM PDT 24
Peak memory 219196 kb
Host smart-8ee5f6e4-e0ce-4d4c-b3e4-bcb07902a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251626273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4251626273
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.952139070
Short name T139
Test name
Test status
Simulation time 521502839 ps
CPU time 30.07 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:51 PM PDT 24
Peak memory 219404 kb
Host smart-c0594942-0c4a-4a23-8954-4cf5b5fe25e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952139070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.952139070
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1774435757
Short name T12
Test name
Test status
Simulation time 32849979997 ps
CPU time 986.22 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 05:13:53 PM PDT 24
Peak memory 232012 kb
Host smart-1d5cc4a4-4f89-45f5-a151-d743cdb3a2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774435757 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1774435757
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.301456347
Short name T336
Test name
Test status
Simulation time 662083130 ps
CPU time 8.51 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:30 PM PDT 24
Peak memory 218720 kb
Host smart-3916c05f-3376-4628-b4a8-1259b2732502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301456347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.301456347
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3945312958
Short name T202
Test name
Test status
Simulation time 24519337857 ps
CPU time 318.42 seconds
Started Jul 28 04:57:35 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 219876 kb
Host smart-33a40bfd-f949-40e6-a421-147b2713666e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945312958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3945312958
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3978573750
Short name T256
Test name
Test status
Simulation time 186547803 ps
CPU time 10.33 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:40 PM PDT 24
Peak memory 219796 kb
Host smart-24829c27-65ae-4957-b92b-0b0451acabc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978573750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3978573750
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2523869206
Short name T15
Test name
Test status
Simulation time 10099731907 ps
CPU time 25.05 seconds
Started Jul 28 04:57:31 PM PDT 24
Finished Jul 28 04:57:56 PM PDT 24
Peak memory 219584 kb
Host smart-10d25af6-b277-4efd-8387-f0dc843f4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523869206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2523869206
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2490494250
Short name T99
Test name
Test status
Simulation time 4094414388 ps
CPU time 39.34 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:59 PM PDT 24
Peak memory 220524 kb
Host smart-e5e2c4c9-2a64-4394-81ab-92400d1aa19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490494250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2490494250
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2852197636
Short name T127
Test name
Test status
Simulation time 1100303868 ps
CPU time 8.72 seconds
Started Jul 28 04:56:46 PM PDT 24
Finished Jul 28 04:56:55 PM PDT 24
Peak memory 218696 kb
Host smart-972c95d4-52ae-4cc6-907a-dede3aaa145b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852197636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2852197636
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1519690421
Short name T148
Test name
Test status
Simulation time 522823483 ps
CPU time 22.92 seconds
Started Jul 28 04:56:46 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 219748 kb
Host smart-4e47c581-1ae4-4685-930e-b46408be6966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519690421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1519690421
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.484386321
Short name T116
Test name
Test status
Simulation time 990896972 ps
CPU time 16.52 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 219716 kb
Host smart-e76e92e9-274e-47c9-92b8-58c89a92e79a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484386321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.484386321
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1356910839
Short name T25
Test name
Test status
Simulation time 353427612 ps
CPU time 118.83 seconds
Started Jul 28 04:56:46 PM PDT 24
Finished Jul 28 04:58:45 PM PDT 24
Peak memory 238864 kb
Host smart-11d32784-293e-4a39-bd15-82550338c9dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356910839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1356910839
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.33437469
Short name T125
Test name
Test status
Simulation time 1499753652 ps
CPU time 19.73 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 04:57:06 PM PDT 24
Peak memory 219128 kb
Host smart-6547a512-9b09-4a57-8803-d568f6051614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33437469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.33437469
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2537897517
Short name T208
Test name
Test status
Simulation time 7404278943 ps
CPU time 24.47 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 219364 kb
Host smart-1d071194-9ee7-4f82-a23e-ac10431a7562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537897517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2537897517
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3266742959
Short name T48
Test name
Test status
Simulation time 70054111891 ps
CPU time 2682.18 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 05:41:35 PM PDT 24
Peak memory 246324 kb
Host smart-072254b2-39f6-4272-86c2-8747167e383c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266742959 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3266742959
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2450961621
Short name T209
Test name
Test status
Simulation time 346553129 ps
CPU time 8.37 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:29 PM PDT 24
Peak memory 218784 kb
Host smart-6bf7bed6-f09b-4ff4-a990-10ae641778ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450961621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2450961621
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1400708424
Short name T271
Test name
Test status
Simulation time 74588512183 ps
CPU time 336.06 seconds
Started Jul 28 04:57:40 PM PDT 24
Finished Jul 28 05:03:16 PM PDT 24
Peak memory 219212 kb
Host smart-d4a72c66-b5ce-48be-9652-a5ffc5ffbc27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400708424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1400708424
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1923259897
Short name T287
Test name
Test status
Simulation time 4725112840 ps
CPU time 18.9 seconds
Started Jul 28 04:57:35 PM PDT 24
Finished Jul 28 04:57:54 PM PDT 24
Peak memory 219816 kb
Host smart-302b8dff-05ac-4d26-b113-b5f5a7f4e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923259897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1923259897
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1738536858
Short name T195
Test name
Test status
Simulation time 1085301824 ps
CPU time 12.1 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:57:40 PM PDT 24
Peak memory 219712 kb
Host smart-97b31948-3bcf-4901-bac9-82c22e616571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738536858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1738536858
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3261231107
Short name T69
Test name
Test status
Simulation time 534266069 ps
CPU time 23.49 seconds
Started Jul 28 04:57:48 PM PDT 24
Finished Jul 28 04:58:12 PM PDT 24
Peak memory 219216 kb
Host smart-e4561ed9-98fc-45dd-8310-51f9a4c1e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261231107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3261231107
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2902045152
Short name T285
Test name
Test status
Simulation time 858977378 ps
CPU time 49.8 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:58:24 PM PDT 24
Peak memory 219996 kb
Host smart-0b893eed-989b-498d-a0b1-82fe5e4b4345
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902045152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2902045152
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.397346438
Short name T190
Test name
Test status
Simulation time 249622942 ps
CPU time 9.9 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 218176 kb
Host smart-8b409d04-bc3c-4234-8d52-f00c27c3b2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397346438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.397346438
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3677451706
Short name T232
Test name
Test status
Simulation time 3111506235 ps
CPU time 216.89 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 05:01:07 PM PDT 24
Peak memory 240184 kb
Host smart-32b81a1e-d0f7-4257-b0f4-df139cd9d29f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677451706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3677451706
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2041258219
Short name T31
Test name
Test status
Simulation time 1323079143 ps
CPU time 19.04 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 219768 kb
Host smart-5ebc76ee-f88d-475e-b156-d87e2318101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041258219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2041258219
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3266732862
Short name T246
Test name
Test status
Simulation time 250194275 ps
CPU time 10.4 seconds
Started Jul 28 04:57:21 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 219732 kb
Host smart-01c6297d-a4ff-4713-9d0a-e931a34a2643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266732862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3266732862
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3547086419
Short name T142
Test name
Test status
Simulation time 1380836442 ps
CPU time 20.09 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219156 kb
Host smart-898e34bc-548d-41e9-9e3c-d1d88087cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547086419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3547086419
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.219921614
Short name T67
Test name
Test status
Simulation time 554588751 ps
CPU time 32.92 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:58:00 PM PDT 24
Peak memory 219360 kb
Host smart-06c4cf65-98a8-4095-b9c0-51622a81c3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219921614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.219921614
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.494185500
Short name T214
Test name
Test status
Simulation time 495600192 ps
CPU time 10.19 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 218692 kb
Host smart-88dd017e-c28a-4124-aacc-87403bc8f9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494185500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.494185500
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3249079859
Short name T231
Test name
Test status
Simulation time 19886066272 ps
CPU time 294.24 seconds
Started Jul 28 04:57:23 PM PDT 24
Finished Jul 28 05:02:17 PM PDT 24
Peak memory 238168 kb
Host smart-d7eb4576-0d82-448b-aa76-4e86424b515d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249079859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3249079859
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1120216562
Short name T158
Test name
Test status
Simulation time 3297548330 ps
CPU time 22.33 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219812 kb
Host smart-7b23dac0-d5f9-4388-84bc-9298572f91a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120216562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1120216562
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1650807851
Short name T304
Test name
Test status
Simulation time 227409462 ps
CPU time 10.83 seconds
Started Jul 28 04:57:31 PM PDT 24
Finished Jul 28 04:57:42 PM PDT 24
Peak memory 220000 kb
Host smart-2fac3bfe-6252-427b-bb4b-b7badf03c42c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650807851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1650807851
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.720242032
Short name T355
Test name
Test status
Simulation time 507664144 ps
CPU time 23 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:55 PM PDT 24
Peak memory 219176 kb
Host smart-8d0199e0-0639-4fb0-8ad1-0b1ae60ab978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720242032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.720242032
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.998245989
Short name T135
Test name
Test status
Simulation time 284862866 ps
CPU time 16.73 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 219188 kb
Host smart-3ffc7502-bea8-4a8e-b838-62f6d3214ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998245989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.998245989
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1552452884
Short name T217
Test name
Test status
Simulation time 1123329368 ps
CPU time 10.09 seconds
Started Jul 28 04:57:34 PM PDT 24
Finished Jul 28 04:57:44 PM PDT 24
Peak memory 218880 kb
Host smart-65fa2809-8863-4293-9795-fb61b3edcba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552452884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1552452884
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3288309022
Short name T35
Test name
Test status
Simulation time 12591127854 ps
CPU time 218.76 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 05:01:07 PM PDT 24
Peak memory 219876 kb
Host smart-6bb2bdd6-a169-483f-a0d3-86cf29e2fd4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288309022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3288309022
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1933936833
Short name T2
Test name
Test status
Simulation time 495666355 ps
CPU time 22.02 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:57:58 PM PDT 24
Peak memory 219712 kb
Host smart-60b2fc6d-9541-4680-93ed-6712ee23ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933936833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1933936833
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.234805807
Short name T210
Test name
Test status
Simulation time 1149273826 ps
CPU time 10.14 seconds
Started Jul 28 04:57:27 PM PDT 24
Finished Jul 28 04:57:37 PM PDT 24
Peak memory 219712 kb
Host smart-65533e01-bcca-4395-ab7e-ce25fb03d9a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234805807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.234805807
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.929790762
Short name T32
Test name
Test status
Simulation time 769728647 ps
CPU time 20.86 seconds
Started Jul 28 04:57:42 PM PDT 24
Finished Jul 28 04:58:03 PM PDT 24
Peak memory 219420 kb
Host smart-ec866744-bffd-4558-853a-ff93ad583b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929790762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.929790762
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.441561075
Short name T212
Test name
Test status
Simulation time 566471618 ps
CPU time 29.63 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:58:00 PM PDT 24
Peak memory 219648 kb
Host smart-1940efe1-fddc-4852-b133-19c27a803eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441561075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.441561075
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.919252728
Short name T175
Test name
Test status
Simulation time 249706963 ps
CPU time 10.08 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 218800 kb
Host smart-d43f376e-50c8-40a5-b9f7-81238a63d907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919252728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.919252728
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3411060783
Short name T230
Test name
Test status
Simulation time 12976140327 ps
CPU time 148.61 seconds
Started Jul 28 04:57:34 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 219876 kb
Host smart-dfe94dd7-0593-4a56-8b3c-6ab89c228c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411060783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3411060783
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3344682544
Short name T30
Test name
Test status
Simulation time 518200023 ps
CPU time 22.97 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:55 PM PDT 24
Peak memory 219744 kb
Host smart-b84cb3ba-1a96-4728-9958-e8667a02cf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344682544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3344682544
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.896572544
Short name T295
Test name
Test status
Simulation time 2120890323 ps
CPU time 11.96 seconds
Started Jul 28 04:57:22 PM PDT 24
Finished Jul 28 04:57:34 PM PDT 24
Peak memory 219972 kb
Host smart-82815b05-09b5-476a-b8be-d5317a66fc65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896572544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.896572544
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3823830812
Short name T247
Test name
Test status
Simulation time 2083972239 ps
CPU time 23.04 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:55 PM PDT 24
Peak memory 218600 kb
Host smart-d7c0dc0f-4b08-4cae-9822-a41a4bfc839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823830812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3823830812
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2596357855
Short name T193
Test name
Test status
Simulation time 1983748537 ps
CPU time 65.04 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:58:34 PM PDT 24
Peak memory 219880 kb
Host smart-c040390c-126e-4885-aba7-b80aa6f985ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596357855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2596357855
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2661827784
Short name T339
Test name
Test status
Simulation time 2109548394 ps
CPU time 15.2 seconds
Started Jul 28 04:57:49 PM PDT 24
Finished Jul 28 04:58:05 PM PDT 24
Peak memory 217728 kb
Host smart-464c78df-8c37-4020-af27-8051c57dc327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661827784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2661827784
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3436241893
Short name T37
Test name
Test status
Simulation time 13871380501 ps
CPU time 237.69 seconds
Started Jul 28 04:57:20 PM PDT 24
Finished Jul 28 05:01:18 PM PDT 24
Peak memory 240272 kb
Host smart-0571b63f-4864-4b27-8c32-ba184bf11b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436241893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3436241893
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.603195803
Short name T249
Test name
Test status
Simulation time 8188791808 ps
CPU time 31.44 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 04:57:59 PM PDT 24
Peak memory 219776 kb
Host smart-4fba8552-9332-4091-9154-758f7ca2f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603195803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.603195803
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.476634777
Short name T179
Test name
Test status
Simulation time 1013324458 ps
CPU time 17.18 seconds
Started Jul 28 04:57:48 PM PDT 24
Finished Jul 28 04:58:05 PM PDT 24
Peak memory 219688 kb
Host smart-51dc0e95-d882-4df6-b680-d7eb79f98b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476634777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.476634777
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2323830916
Short name T4
Test name
Test status
Simulation time 1888490508 ps
CPU time 23.71 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:53 PM PDT 24
Peak memory 219276 kb
Host smart-746e8d1c-0611-4f0c-9c56-e12573ebe1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323830916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2323830916
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3974680553
Short name T282
Test name
Test status
Simulation time 630940621 ps
CPU time 17.58 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 04:57:44 PM PDT 24
Peak memory 218484 kb
Host smart-4c67b477-e7a3-46b5-a26d-b0e3072e9650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974680553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3974680553
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2248341042
Short name T335
Test name
Test status
Simulation time 281507717 ps
CPU time 8.32 seconds
Started Jul 28 04:57:24 PM PDT 24
Finished Jul 28 04:57:32 PM PDT 24
Peak memory 218840 kb
Host smart-8754e769-2af8-4eff-ad10-32d835d8aa51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248341042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2248341042
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4125898333
Short name T221
Test name
Test status
Simulation time 3987349711 ps
CPU time 172 seconds
Started Jul 28 04:57:26 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 233616 kb
Host smart-cb49c188-5c0a-4aa6-9c69-976e6ac60cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125898333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4125898333
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3497680366
Short name T155
Test name
Test status
Simulation time 502042444 ps
CPU time 22.8 seconds
Started Jul 28 04:57:48 PM PDT 24
Finished Jul 28 04:58:11 PM PDT 24
Peak memory 219808 kb
Host smart-1f9e4236-2b26-454c-8363-00e2fd9b1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497680366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3497680366
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1758158053
Short name T366
Test name
Test status
Simulation time 210713806 ps
CPU time 10.61 seconds
Started Jul 28 04:57:37 PM PDT 24
Finished Jul 28 04:57:47 PM PDT 24
Peak memory 219712 kb
Host smart-66145a82-accf-4cf3-b9ec-93bf1e47e6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758158053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1758158053
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2953578175
Short name T160
Test name
Test status
Simulation time 707520193 ps
CPU time 20.27 seconds
Started Jul 28 04:57:42 PM PDT 24
Finished Jul 28 04:58:02 PM PDT 24
Peak memory 219220 kb
Host smart-35d78197-3280-40de-9fef-b0da2b5ab3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953578175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2953578175
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2542505107
Short name T70
Test name
Test status
Simulation time 855053314 ps
CPU time 21.83 seconds
Started Jul 28 04:57:28 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 219344 kb
Host smart-8dfc96cf-ebaa-4483-b41a-51e34d21b7a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542505107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2542505107
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2193573858
Short name T326
Test name
Test status
Simulation time 1029487818 ps
CPU time 10.12 seconds
Started Jul 28 04:57:50 PM PDT 24
Finished Jul 28 04:58:01 PM PDT 24
Peak memory 218740 kb
Host smart-8da12a6e-931b-48ee-96e8-c797ff859ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193573858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2193573858
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1914866019
Short name T132
Test name
Test status
Simulation time 6751403686 ps
CPU time 340.39 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 240468 kb
Host smart-31b1e1f4-1979-4fb5-8c63-5c2bc04d63b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914866019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1914866019
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.869433217
Short name T267
Test name
Test status
Simulation time 2902976922 ps
CPU time 22.9 seconds
Started Jul 28 04:57:46 PM PDT 24
Finished Jul 28 04:58:09 PM PDT 24
Peak memory 219812 kb
Host smart-71b0d806-e07e-4db5-b7e6-e113a7205547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869433217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.869433217
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.450481810
Short name T7
Test name
Test status
Simulation time 1082469253 ps
CPU time 12.22 seconds
Started Jul 28 04:57:48 PM PDT 24
Finished Jul 28 04:58:00 PM PDT 24
Peak memory 219756 kb
Host smart-4955da08-ad8f-4007-be76-7887b278ce8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450481810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.450481810
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3490961704
Short name T237
Test name
Test status
Simulation time 701961504 ps
CPU time 20.28 seconds
Started Jul 28 04:57:36 PM PDT 24
Finished Jul 28 04:57:56 PM PDT 24
Peak memory 219176 kb
Host smart-72a28685-904c-4895-9bbd-5af5dbe170c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490961704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3490961704
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1521378629
Short name T6
Test name
Test status
Simulation time 878740355 ps
CPU time 48.58 seconds
Started Jul 28 04:57:36 PM PDT 24
Finished Jul 28 04:58:25 PM PDT 24
Peak memory 219660 kb
Host smart-6b3a349e-e0cf-4674-8357-db88b9885df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521378629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1521378629
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3593571015
Short name T140
Test name
Test status
Simulation time 516831298 ps
CPU time 9.96 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:39 PM PDT 24
Peak memory 218804 kb
Host smart-c9ea837a-e3ad-4fde-b2c9-fc17cb6ba964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593571015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3593571015
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3375314042
Short name T244
Test name
Test status
Simulation time 3982618205 ps
CPU time 204.98 seconds
Started Jul 28 04:57:35 PM PDT 24
Finished Jul 28 05:01:00 PM PDT 24
Peak memory 219904 kb
Host smart-c656d99b-25a0-4f00-982f-d3ad9d05f60a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375314042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3375314042
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.718804399
Short name T157
Test name
Test status
Simulation time 496104782 ps
CPU time 22.86 seconds
Started Jul 28 04:57:36 PM PDT 24
Finished Jul 28 04:57:59 PM PDT 24
Peak memory 219712 kb
Host smart-1c3a7f79-5287-4751-b1cc-482125569a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718804399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.718804399
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1171677663
Short name T196
Test name
Test status
Simulation time 513851081 ps
CPU time 11.82 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 04:57:41 PM PDT 24
Peak memory 219816 kb
Host smart-d4566d43-9c7e-4d87-96d2-905c00e0b790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171677663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1171677663
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2793802723
Short name T309
Test name
Test status
Simulation time 2047120919 ps
CPU time 36.47 seconds
Started Jul 28 04:58:02 PM PDT 24
Finished Jul 28 04:58:38 PM PDT 24
Peak memory 219276 kb
Host smart-7fbd7611-b093-444c-bd8c-eb29390e44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793802723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2793802723
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.977729811
Short name T239
Test name
Test status
Simulation time 2488554676 ps
CPU time 31.88 seconds
Started Jul 28 04:57:44 PM PDT 24
Finished Jul 28 04:58:16 PM PDT 24
Peak memory 219740 kb
Host smart-510ef214-9f94-4917-b891-714fe2dc5536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977729811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.977729811
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2605187360
Short name T162
Test name
Test status
Simulation time 689294259 ps
CPU time 8.39 seconds
Started Jul 28 04:57:49 PM PDT 24
Finished Jul 28 04:57:57 PM PDT 24
Peak memory 218824 kb
Host smart-d562db41-f8d7-4c35-b173-a19de659df7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605187360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2605187360
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3467659477
Short name T92
Test name
Test status
Simulation time 11332155038 ps
CPU time 171.25 seconds
Started Jul 28 04:57:29 PM PDT 24
Finished Jul 28 05:00:21 PM PDT 24
Peak memory 219864 kb
Host smart-84416a82-29b7-45c6-858d-d74860835a8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467659477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3467659477
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1003439830
Short name T272
Test name
Test status
Simulation time 334862138 ps
CPU time 19.51 seconds
Started Jul 28 04:57:43 PM PDT 24
Finished Jul 28 04:58:02 PM PDT 24
Peak memory 219772 kb
Host smart-ac14f240-3d87-42c8-b172-60c49d5f2ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003439830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1003439830
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2302082234
Short name T163
Test name
Test status
Simulation time 730394621 ps
CPU time 10.4 seconds
Started Jul 28 04:57:32 PM PDT 24
Finished Jul 28 04:57:42 PM PDT 24
Peak memory 219712 kb
Host smart-50d01533-df4c-4209-a973-f0e59eb17eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302082234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2302082234
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3451516621
Short name T87
Test name
Test status
Simulation time 1388272159 ps
CPU time 19.82 seconds
Started Jul 28 04:57:30 PM PDT 24
Finished Jul 28 04:57:50 PM PDT 24
Peak memory 218564 kb
Host smart-7840a8f3-80c2-40e5-9d3f-c1ea99406477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451516621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3451516621
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2811429595
Short name T310
Test name
Test status
Simulation time 801716299 ps
CPU time 35.95 seconds
Started Jul 28 04:57:38 PM PDT 24
Finished Jul 28 04:58:14 PM PDT 24
Peak memory 219676 kb
Host smart-75c30c6b-3445-44ad-ae54-d9291527c7fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811429595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2811429595
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3460604553
Short name T277
Test name
Test status
Simulation time 7327261145 ps
CPU time 1311.8 seconds
Started Jul 28 04:57:31 PM PDT 24
Finished Jul 28 05:19:23 PM PDT 24
Peak memory 234724 kb
Host smart-4630568d-c7d1-413d-aa51-b2813f82fe35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460604553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3460604553
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.966048515
Short name T171
Test name
Test status
Simulation time 1496637643 ps
CPU time 8.26 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 218808 kb
Host smart-6b6bcefe-56a4-4873-a8d6-772578e290e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966048515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.966048515
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2673486611
Short name T290
Test name
Test status
Simulation time 7126788630 ps
CPU time 232.69 seconds
Started Jul 28 04:56:48 PM PDT 24
Finished Jul 28 05:00:41 PM PDT 24
Peak memory 239152 kb
Host smart-4bb64ea9-7d79-4003-a0ac-2ecee1d3eca5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673486611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2673486611
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.26395890
Short name T215
Test name
Test status
Simulation time 1982814464 ps
CPU time 23.13 seconds
Started Jul 28 04:56:46 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 219716 kb
Host smart-6b538ebe-082a-4350-9537-06be05610fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26395890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.26395890
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.967109245
Short name T252
Test name
Test status
Simulation time 183057207 ps
CPU time 10.63 seconds
Started Jul 28 04:56:49 PM PDT 24
Finished Jul 28 04:57:00 PM PDT 24
Peak memory 219736 kb
Host smart-e7570320-f9a5-4aa8-988c-026ab91ab870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967109245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.967109245
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3872705954
Short name T198
Test name
Test status
Simulation time 357676020 ps
CPU time 19.52 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:57:05 PM PDT 24
Peak memory 219200 kb
Host smart-e63e78fb-8a98-4f37-b9f1-569f862da746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872705954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3872705954
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1480081076
Short name T117
Test name
Test status
Simulation time 191479364 ps
CPU time 14.02 seconds
Started Jul 28 04:56:45 PM PDT 24
Finished Jul 28 04:57:00 PM PDT 24
Peak memory 219440 kb
Host smart-22d11926-7d51-417b-a6d3-61229bd3a696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480081076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1480081076
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1502667311
Short name T301
Test name
Test status
Simulation time 42337024052 ps
CPU time 1546.95 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 05:22:43 PM PDT 24
Peak memory 232284 kb
Host smart-201e4ee4-b8ce-4f18-a92a-ae6467e02b6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502667311 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1502667311
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2346346794
Short name T145
Test name
Test status
Simulation time 258208724 ps
CPU time 10.15 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 04:57:04 PM PDT 24
Peak memory 218152 kb
Host smart-1c6cae8f-460f-4f31-93a8-f53c05b07688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346346794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2346346794
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.407749423
Short name T178
Test name
Test status
Simulation time 4535232492 ps
CPU time 317.71 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 05:02:14 PM PDT 24
Peak memory 240408 kb
Host smart-cc306a80-51d6-4eda-83ee-5816256bddae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407749423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.407749423
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1657822478
Short name T238
Test name
Test status
Simulation time 333251906 ps
CPU time 18.97 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 04:57:09 PM PDT 24
Peak memory 219780 kb
Host smart-2a1936eb-0355-449d-bdc6-270ae49b1453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657822478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1657822478
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2540712772
Short name T86
Test name
Test status
Simulation time 184189419 ps
CPU time 11.18 seconds
Started Jul 28 04:56:48 PM PDT 24
Finished Jul 28 04:57:00 PM PDT 24
Peak memory 219720 kb
Host smart-9e6c733e-6a76-47da-92fd-340d9f087e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540712772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2540712772
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3659631572
Short name T159
Test name
Test status
Simulation time 3840283401 ps
CPU time 19.79 seconds
Started Jul 28 04:56:48 PM PDT 24
Finished Jul 28 04:57:08 PM PDT 24
Peak memory 218928 kb
Host smart-8df9f15e-68f8-474d-84a8-fa4349b81600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659631572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3659631572
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.959547258
Short name T201
Test name
Test status
Simulation time 529493865 ps
CPU time 34.3 seconds
Started Jul 28 04:56:47 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219092 kb
Host smart-4229cca6-1eaf-483b-accd-9bf8f04a2026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959547258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.959547258
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.204836140
Short name T156
Test name
Test status
Simulation time 8629924463 ps
CPU time 448.2 seconds
Started Jul 28 04:56:49 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 237152 kb
Host smart-fe61c2ff-4a99-4922-91cb-a927dd64e3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204836140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.204836140
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4223657118
Short name T331
Test name
Test status
Simulation time 512750617 ps
CPU time 22.42 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 219736 kb
Host smart-77b6f3cb-1488-45b6-b211-646a6cd80207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223657118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4223657118
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1225512780
Short name T327
Test name
Test status
Simulation time 296527771 ps
CPU time 12.58 seconds
Started Jul 28 04:56:54 PM PDT 24
Finished Jul 28 04:57:07 PM PDT 24
Peak memory 219740 kb
Host smart-18ebf39b-41a8-423d-9a55-bce1b5f4d1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225512780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1225512780
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.663731558
Short name T306
Test name
Test status
Simulation time 1021257998 ps
CPU time 24.41 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:17 PM PDT 24
Peak memory 218712 kb
Host smart-7bf6caef-fb92-4307-86f7-4b9bff57f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663731558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.663731558
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3447364972
Short name T317
Test name
Test status
Simulation time 5199264498 ps
CPU time 42.88 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:35 PM PDT 24
Peak memory 220488 kb
Host smart-f8914e1f-9c59-4a26-8197-146290d99828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447364972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3447364972
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3188943317
Short name T222
Test name
Test status
Simulation time 996541578 ps
CPU time 10.15 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:02 PM PDT 24
Peak memory 217688 kb
Host smart-823c8935-bd97-493c-8fdb-3613cdd454c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188943317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3188943317
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2301664692
Short name T45
Test name
Test status
Simulation time 4972124910 ps
CPU time 275.8 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 05:01:26 PM PDT 24
Peak memory 234856 kb
Host smart-7e28fb4e-e27b-4798-8184-fc2a8f181c54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301664692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2301664692
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2919622731
Short name T346
Test name
Test status
Simulation time 1325193771 ps
CPU time 19.29 seconds
Started Jul 28 04:57:01 PM PDT 24
Finished Jul 28 04:57:20 PM PDT 24
Peak memory 219768 kb
Host smart-29a564d8-1526-4d38-bf04-4a5cf6059127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919622731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2919622731
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2672227627
Short name T270
Test name
Test status
Simulation time 375082083 ps
CPU time 10.8 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:02 PM PDT 24
Peak memory 219760 kb
Host smart-b4b2fadd-2eb3-47fb-bafb-d07374b82fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672227627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2672227627
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1126111231
Short name T250
Test name
Test status
Simulation time 518764263 ps
CPU time 23.69 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 04:57:16 PM PDT 24
Peak memory 219184 kb
Host smart-ec495832-a86e-400b-aae3-1c5fa50d877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126111231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1126111231
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3597716400
Short name T126
Test name
Test status
Simulation time 2312253792 ps
CPU time 19.49 seconds
Started Jul 28 04:56:51 PM PDT 24
Finished Jul 28 04:57:11 PM PDT 24
Peak memory 219688 kb
Host smart-2d2e201b-8b84-4ffb-808f-09eda8a4fd63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597716400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3597716400
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.346567842
Short name T269
Test name
Test status
Simulation time 51138396698 ps
CPU time 3686.65 seconds
Started Jul 28 04:56:52 PM PDT 24
Finished Jul 28 05:58:19 PM PDT 24
Peak memory 230268 kb
Host smart-d8344b63-b2d8-4659-98ba-5f380b3e668b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346567842 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.346567842
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1048705235
Short name T362
Test name
Test status
Simulation time 569786147 ps
CPU time 8.71 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:06 PM PDT 24
Peak memory 218764 kb
Host smart-6f0b18a7-e43b-4d2c-a01a-80924e23e8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048705235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1048705235
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2885400736
Short name T151
Test name
Test status
Simulation time 44515215192 ps
CPU time 285.62 seconds
Started Jul 28 04:56:50 PM PDT 24
Finished Jul 28 05:01:36 PM PDT 24
Peak memory 234592 kb
Host smart-dce8bd71-df45-467c-abbc-56c45d386a31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885400736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2885400736
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1144499874
Short name T235
Test name
Test status
Simulation time 1054047749 ps
CPU time 22.95 seconds
Started Jul 28 04:56:58 PM PDT 24
Finished Jul 28 04:57:21 PM PDT 24
Peak memory 219856 kb
Host smart-e44e8563-d9e3-4001-a51a-8722d1e7f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144499874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1144499874
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1602989724
Short name T292
Test name
Test status
Simulation time 349425165 ps
CPU time 10.24 seconds
Started Jul 28 04:56:56 PM PDT 24
Finished Jul 28 04:57:06 PM PDT 24
Peak memory 219516 kb
Host smart-f987a48b-77fd-4226-afd2-c35ba1d97661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602989724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1602989724
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3194519090
Short name T296
Test name
Test status
Simulation time 1929078028 ps
CPU time 24.21 seconds
Started Jul 28 04:56:53 PM PDT 24
Finished Jul 28 04:57:18 PM PDT 24
Peak memory 219204 kb
Host smart-a6707f58-9fc5-47ec-851f-6747ebf37b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194519090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3194519090
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2774931295
Short name T359
Test name
Test status
Simulation time 1165402554 ps
CPU time 15.78 seconds
Started Jul 28 04:56:57 PM PDT 24
Finished Jul 28 04:57:13 PM PDT 24
Peak memory 219196 kb
Host smart-b5de8962-5824-43f4-bc6b-724121300915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774931295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2774931295
Directory /workspace/9.rom_ctrl_stress_all/latest
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