Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.56 97.68 100.00 98.97 97.45 98.37


Total test records in report: 410
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T287 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2110020422 Jul 29 05:15:40 PM PDT 24 Jul 29 05:16:02 PM PDT 24 502612229 ps
T288 /workspace/coverage/default/5.rom_ctrl_smoke.3118856463 Jul 29 05:14:36 PM PDT 24 Jul 29 05:14:48 PM PDT 24 262153245 ps
T24 /workspace/coverage/default/1.rom_ctrl_sec_cm.2944534274 Jul 29 05:14:34 PM PDT 24 Jul 29 05:18:22 PM PDT 24 1480044479 ps
T289 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3782829284 Jul 29 05:15:18 PM PDT 24 Jul 29 05:15:41 PM PDT 24 497199493 ps
T290 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.201418583 Jul 29 05:16:06 PM PDT 24 Jul 29 05:16:18 PM PDT 24 1055501500 ps
T291 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4101482510 Jul 29 05:15:07 PM PDT 24 Jul 29 05:19:30 PM PDT 24 4800963184 ps
T292 /workspace/coverage/default/8.rom_ctrl_smoke.2617053483 Jul 29 05:14:48 PM PDT 24 Jul 29 05:14:59 PM PDT 24 178199682 ps
T293 /workspace/coverage/default/33.rom_ctrl_stress_all.1790490502 Jul 29 05:15:35 PM PDT 24 Jul 29 05:16:14 PM PDT 24 559167450 ps
T294 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1796152538 Jul 29 05:15:13 PM PDT 24 Jul 29 05:15:26 PM PDT 24 3177908807 ps
T295 /workspace/coverage/default/12.rom_ctrl_stress_all.1724565610 Jul 29 05:15:08 PM PDT 24 Jul 29 05:15:43 PM PDT 24 2702984382 ps
T296 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2384125741 Jul 29 05:14:49 PM PDT 24 Jul 29 05:14:59 PM PDT 24 368085498 ps
T297 /workspace/coverage/default/20.rom_ctrl_alert_test.3838250149 Jul 29 05:15:19 PM PDT 24 Jul 29 05:15:28 PM PDT 24 1182289059 ps
T298 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2708480272 Jul 29 05:16:10 PM PDT 24 Jul 29 05:16:30 PM PDT 24 343006601 ps
T299 /workspace/coverage/default/9.rom_ctrl_alert_test.4109244445 Jul 29 05:14:57 PM PDT 24 Jul 29 05:15:08 PM PDT 24 993144578 ps
T300 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.827988411 Jul 29 05:16:07 PM PDT 24 Jul 29 05:19:13 PM PDT 24 11263343151 ps
T301 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2423289432 Jul 29 05:14:41 PM PDT 24 Jul 29 05:20:19 PM PDT 24 11043884983 ps
T302 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3380894302 Jul 29 05:15:22 PM PDT 24 Jul 29 05:15:41 PM PDT 24 1376366140 ps
T303 /workspace/coverage/default/3.rom_ctrl_alert_test.3475762905 Jul 29 05:14:38 PM PDT 24 Jul 29 05:14:46 PM PDT 24 172976241 ps
T304 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1970420583 Jul 29 05:16:00 PM PDT 24 Jul 29 05:18:43 PM PDT 24 7385962910 ps
T305 /workspace/coverage/default/40.rom_ctrl_stress_all.888032455 Jul 29 05:15:47 PM PDT 24 Jul 29 05:16:15 PM PDT 24 2073117719 ps
T306 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1835001974 Jul 29 05:15:19 PM PDT 24 Jul 29 05:15:32 PM PDT 24 1060115825 ps
T307 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2913490735 Jul 29 05:15:01 PM PDT 24 Jul 29 05:15:12 PM PDT 24 2139047364 ps
T308 /workspace/coverage/default/29.rom_ctrl_alert_test.2944216863 Jul 29 05:20:57 PM PDT 24 Jul 29 05:21:08 PM PDT 24 259702424 ps
T309 /workspace/coverage/default/24.rom_ctrl_alert_test.2906153164 Jul 29 05:15:23 PM PDT 24 Jul 29 05:15:38 PM PDT 24 1026749529 ps
T310 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1136891146 Jul 29 05:15:01 PM PDT 24 Jul 29 05:15:13 PM PDT 24 1084410095 ps
T311 /workspace/coverage/default/1.rom_ctrl_smoke.2176227219 Jul 29 05:14:42 PM PDT 24 Jul 29 05:14:53 PM PDT 24 181045569 ps
T312 /workspace/coverage/default/10.rom_ctrl_stress_all.3066007902 Jul 29 05:15:01 PM PDT 24 Jul 29 05:15:23 PM PDT 24 686487964 ps
T313 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1254887750 Jul 29 05:14:48 PM PDT 24 Jul 29 05:15:11 PM PDT 24 498188296 ps
T58 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1105363872 Jul 29 05:14:41 PM PDT 24 Jul 29 05:14:51 PM PDT 24 506386983 ps
T59 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2157409274 Jul 29 05:14:27 PM PDT 24 Jul 29 05:14:38 PM PDT 24 581767313 ps
T314 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2916538576 Jul 29 05:14:29 PM PDT 24 Jul 29 05:14:40 PM PDT 24 332297266 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.536564725 Jul 29 05:14:46 PM PDT 24 Jul 29 05:15:23 PM PDT 24 2872092314 ps
T64 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.366407862 Jul 29 05:14:35 PM PDT 24 Jul 29 05:14:43 PM PDT 24 171480044 ps
T315 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3521416834 Jul 29 05:14:14 PM PDT 24 Jul 29 05:14:24 PM PDT 24 259986388 ps
T65 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2718689435 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:42 PM PDT 24 708317813 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1019200713 Jul 29 05:14:25 PM PDT 24 Jul 29 05:14:35 PM PDT 24 800771348 ps
T316 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.696459790 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:24 PM PDT 24 1380006297 ps
T317 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1020842004 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:45 PM PDT 24 1237869728 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2473957668 Jul 29 05:14:39 PM PDT 24 Jul 29 05:15:34 PM PDT 24 1067304140 ps
T318 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.80612231 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:18 PM PDT 24 347085737 ps
T319 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.493074127 Jul 29 05:14:08 PM PDT 24 Jul 29 05:14:18 PM PDT 24 1112645056 ps
T96 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3208140191 Jul 29 05:14:30 PM PDT 24 Jul 29 05:14:40 PM PDT 24 1077043612 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3335529746 Jul 29 05:14:44 PM PDT 24 Jul 29 05:17:22 PM PDT 24 1760233034 ps
T98 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2235224330 Jul 29 05:14:24 PM PDT 24 Jul 29 05:14:34 PM PDT 24 387125754 ps
T320 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3540465881 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:41 PM PDT 24 195007073 ps
T321 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3986203787 Jul 29 05:14:22 PM PDT 24 Jul 29 05:14:35 PM PDT 24 918747553 ps
T67 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.226200216 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:41 PM PDT 24 175169491 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3859037294 Jul 29 05:14:28 PM PDT 24 Jul 29 05:14:36 PM PDT 24 2058889334 ps
T69 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4087227236 Jul 29 05:14:33 PM PDT 24 Jul 29 05:15:11 PM PDT 24 3272349706 ps
T322 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.201217966 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:40 PM PDT 24 362064057 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.462054098 Jul 29 05:14:34 PM PDT 24 Jul 29 05:15:30 PM PDT 24 1053332933 ps
T323 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3826840066 Jul 29 05:14:40 PM PDT 24 Jul 29 05:14:49 PM PDT 24 317796675 ps
T324 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.117726747 Jul 29 05:14:24 PM PDT 24 Jul 29 05:14:39 PM PDT 24 2051298480 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2396455248 Jul 29 05:14:46 PM PDT 24 Jul 29 05:17:19 PM PDT 24 2570782588 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.192222364 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:18 PM PDT 24 1831532481 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4252790230 Jul 29 05:14:22 PM PDT 24 Jul 29 05:14:33 PM PDT 24 250328283 ps
T325 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1241151283 Jul 29 05:14:35 PM PDT 24 Jul 29 05:14:44 PM PDT 24 184998713 ps
T57 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1513368849 Jul 29 05:14:10 PM PDT 24 Jul 29 05:16:44 PM PDT 24 658294899 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2850425932 Jul 29 05:14:41 PM PDT 24 Jul 29 05:15:59 PM PDT 24 888579508 ps
T326 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1537032352 Jul 29 05:14:45 PM PDT 24 Jul 29 05:14:55 PM PDT 24 2241407774 ps
T327 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1649726888 Jul 29 05:14:11 PM PDT 24 Jul 29 05:14:19 PM PDT 24 1270493224 ps
T328 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1794473937 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:41 PM PDT 24 1177304779 ps
T329 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1330049748 Jul 29 05:14:23 PM PDT 24 Jul 29 05:14:33 PM PDT 24 993765849 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.39144388 Jul 29 05:14:09 PM PDT 24 Jul 29 05:14:26 PM PDT 24 2768747640 ps
T330 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.955440411 Jul 29 05:14:38 PM PDT 24 Jul 29 05:14:47 PM PDT 24 206770130 ps
T331 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3259284942 Jul 29 05:14:26 PM PDT 24 Jul 29 05:14:34 PM PDT 24 664226031 ps
T332 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4094281755 Jul 29 05:14:26 PM PDT 24 Jul 29 05:14:36 PM PDT 24 255527338 ps
T333 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3105447268 Jul 29 05:14:43 PM PDT 24 Jul 29 05:14:51 PM PDT 24 660826715 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1960604724 Jul 29 05:14:37 PM PDT 24 Jul 29 05:17:10 PM PDT 24 2922952463 ps
T334 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.984103647 Jul 29 05:14:24 PM PDT 24 Jul 29 05:14:34 PM PDT 24 994592208 ps
T335 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2827790424 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:43 PM PDT 24 1035244902 ps
T336 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.222611240 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:42 PM PDT 24 510286354 ps
T337 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1561723635 Jul 29 05:14:38 PM PDT 24 Jul 29 05:14:48 PM PDT 24 540929170 ps
T338 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.981743132 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:40 PM PDT 24 688125392 ps
T339 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2724807665 Jul 29 05:14:25 PM PDT 24 Jul 29 05:14:38 PM PDT 24 274312460 ps
T340 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1313859648 Jul 29 05:14:29 PM PDT 24 Jul 29 05:14:44 PM PDT 24 1236174438 ps
T341 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1080188653 Jul 29 05:14:07 PM PDT 24 Jul 29 05:14:16 PM PDT 24 534398485 ps
T342 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3602132922 Jul 29 05:14:23 PM PDT 24 Jul 29 05:14:31 PM PDT 24 660848477 ps
T343 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.902345923 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:26 PM PDT 24 263877124 ps
T344 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4275712392 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:20 PM PDT 24 168117063 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2903893927 Jul 29 05:14:24 PM PDT 24 Jul 29 05:17:00 PM PDT 24 1592481565 ps
T345 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2006688451 Jul 29 05:14:37 PM PDT 24 Jul 29 05:14:51 PM PDT 24 2067738691 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1241436416 Jul 29 05:14:40 PM PDT 24 Jul 29 05:14:51 PM PDT 24 344481239 ps
T346 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3152041975 Jul 29 05:14:05 PM PDT 24 Jul 29 05:14:14 PM PDT 24 402531183 ps
T347 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1064844973 Jul 29 05:14:40 PM PDT 24 Jul 29 05:14:49 PM PDT 24 664988126 ps
T348 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2498548308 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:45 PM PDT 24 173459644 ps
T349 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3107633380 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:39 PM PDT 24 172457859 ps
T350 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.853524358 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:45 PM PDT 24 261217174 ps
T351 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2401807031 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:44 PM PDT 24 721695666 ps
T352 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2609672823 Jul 29 05:14:27 PM PDT 24 Jul 29 05:14:36 PM PDT 24 353718638 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3299183711 Jul 29 05:14:25 PM PDT 24 Jul 29 05:16:58 PM PDT 24 804941092 ps
T353 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.628436411 Jul 29 05:14:28 PM PDT 24 Jul 29 05:14:45 PM PDT 24 720145192 ps
T354 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.826562537 Jul 29 05:14:36 PM PDT 24 Jul 29 05:14:50 PM PDT 24 339162720 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2521840504 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:42 PM PDT 24 689696418 ps
T355 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3425716315 Jul 29 05:14:41 PM PDT 24 Jul 29 05:16:00 PM PDT 24 1289377303 ps
T356 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.772606248 Jul 29 05:14:28 PM PDT 24 Jul 29 05:15:49 PM PDT 24 431763310 ps
T357 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3695027439 Jul 29 05:14:33 PM PDT 24 Jul 29 05:15:54 PM PDT 24 341589706 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1095055157 Jul 29 05:14:28 PM PDT 24 Jul 29 05:14:38 PM PDT 24 266734496 ps
T359 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.287957353 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:43 PM PDT 24 542088935 ps
T360 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1591068736 Jul 29 05:14:25 PM PDT 24 Jul 29 05:14:34 PM PDT 24 345693479 ps
T361 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.364721766 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:41 PM PDT 24 751717374 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3952685605 Jul 29 05:14:32 PM PDT 24 Jul 29 05:15:17 PM PDT 24 1033537256 ps
T362 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.710219259 Jul 29 05:14:26 PM PDT 24 Jul 29 05:14:36 PM PDT 24 1034992718 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1172068623 Jul 29 05:14:45 PM PDT 24 Jul 29 05:17:14 PM PDT 24 576862100 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.526975310 Jul 29 05:14:28 PM PDT 24 Jul 29 05:14:36 PM PDT 24 188850989 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.926934404 Jul 29 05:14:49 PM PDT 24 Jul 29 05:16:10 PM PDT 24 286770056 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1076936292 Jul 29 05:14:41 PM PDT 24 Jul 29 05:17:16 PM PDT 24 1536028138 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.214637163 Jul 29 05:14:26 PM PDT 24 Jul 29 05:14:36 PM PDT 24 508696311 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.396775969 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:25 PM PDT 24 669538610 ps
T366 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1399369037 Jul 29 05:14:34 PM PDT 24 Jul 29 05:14:44 PM PDT 24 1123469587 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1874423206 Jul 29 05:14:48 PM PDT 24 Jul 29 05:14:57 PM PDT 24 338525441 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1578989791 Jul 29 05:14:42 PM PDT 24 Jul 29 05:14:52 PM PDT 24 255236244 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2582693094 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:21 PM PDT 24 260771145 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3020815106 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:20 PM PDT 24 254764154 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2070173506 Jul 29 05:14:30 PM PDT 24 Jul 29 05:14:40 PM PDT 24 577593331 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3868014579 Jul 29 05:14:24 PM PDT 24 Jul 29 05:14:33 PM PDT 24 176007480 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1383919432 Jul 29 05:14:33 PM PDT 24 Jul 29 05:15:55 PM PDT 24 630811206 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2607711353 Jul 29 05:14:30 PM PDT 24 Jul 29 05:14:42 PM PDT 24 174921298 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2304878717 Jul 29 05:14:06 PM PDT 24 Jul 29 05:15:04 PM PDT 24 1821403559 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2574437160 Jul 29 05:14:40 PM PDT 24 Jul 29 05:14:54 PM PDT 24 167900934 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1743215948 Jul 29 05:14:40 PM PDT 24 Jul 29 05:14:51 PM PDT 24 514468006 ps
T376 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2869038162 Jul 29 05:14:41 PM PDT 24 Jul 29 05:14:52 PM PDT 24 1859260908 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1083161115 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:45 PM PDT 24 332380890 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4095296393 Jul 29 05:14:43 PM PDT 24 Jul 29 05:14:53 PM PDT 24 195828539 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1668521783 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:43 PM PDT 24 251516135 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2116353678 Jul 29 05:14:07 PM PDT 24 Jul 29 05:16:46 PM PDT 24 2159061777 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2554140545 Jul 29 05:14:30 PM PDT 24 Jul 29 05:14:40 PM PDT 24 257150528 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3280631898 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:42 PM PDT 24 2060298126 ps
T381 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4146264248 Jul 29 05:14:22 PM PDT 24 Jul 29 05:14:34 PM PDT 24 2414393330 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1402881457 Jul 29 05:14:27 PM PDT 24 Jul 29 05:14:37 PM PDT 24 1901271605 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.374358024 Jul 29 05:14:24 PM PDT 24 Jul 29 05:17:04 PM PDT 24 847899229 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.349378568 Jul 29 05:14:14 PM PDT 24 Jul 29 05:14:23 PM PDT 24 693041824 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3037277420 Jul 29 05:14:48 PM PDT 24 Jul 29 05:14:59 PM PDT 24 1035810036 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1104967403 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:30 PM PDT 24 6989649765 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4006536903 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:42 PM PDT 24 355414474 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1390922343 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:42 PM PDT 24 3535511845 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1440754278 Jul 29 05:14:33 PM PDT 24 Jul 29 05:14:45 PM PDT 24 176986756 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1415142625 Jul 29 05:14:35 PM PDT 24 Jul 29 05:15:54 PM PDT 24 326388987 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.763710084 Jul 29 05:14:31 PM PDT 24 Jul 29 05:14:40 PM PDT 24 179870227 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1870129360 Jul 29 05:14:27 PM PDT 24 Jul 29 05:15:05 PM PDT 24 1402773493 ps
T116 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2712668005 Jul 29 05:14:41 PM PDT 24 Jul 29 05:17:14 PM PDT 24 360230531 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2686388973 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:27 PM PDT 24 866754036 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3035202938 Jul 29 05:14:15 PM PDT 24 Jul 29 05:14:29 PM PDT 24 2064401115 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1308106622 Jul 29 05:14:11 PM PDT 24 Jul 29 05:14:19 PM PDT 24 688516710 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1181387733 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:46 PM PDT 24 495618917 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2082099421 Jul 29 05:14:10 PM PDT 24 Jul 29 05:14:20 PM PDT 24 1124556445 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3844740542 Jul 29 05:14:27 PM PDT 24 Jul 29 05:14:35 PM PDT 24 167693642 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4264988642 Jul 29 05:14:12 PM PDT 24 Jul 29 05:14:26 PM PDT 24 3095504327 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.159547026 Jul 29 05:14:20 PM PDT 24 Jul 29 05:14:30 PM PDT 24 257227289 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.207341418 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:50 PM PDT 24 1025819629 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3894165873 Jul 29 05:14:32 PM PDT 24 Jul 29 05:14:41 PM PDT 24 1370338480 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1823654800 Jul 29 05:14:38 PM PDT 24 Jul 29 05:14:48 PM PDT 24 1034391761 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1056269602 Jul 29 05:14:23 PM PDT 24 Jul 29 05:14:33 PM PDT 24 255131523 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2791406105 Jul 29 05:14:33 PM PDT 24 Jul 29 05:15:55 PM PDT 24 1313693177 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3313364679 Jul 29 05:14:38 PM PDT 24 Jul 29 05:14:57 PM PDT 24 997433524 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1338875192 Jul 29 05:14:42 PM PDT 24 Jul 29 05:14:55 PM PDT 24 332609915 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.548678386 Jul 29 05:14:36 PM PDT 24 Jul 29 05:14:46 PM PDT 24 672872860 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.280113112 Jul 29 05:14:05 PM PDT 24 Jul 29 05:14:14 PM PDT 24 174976904 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4226701245 Jul 29 05:14:16 PM PDT 24 Jul 29 05:14:24 PM PDT 24 174538716 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2254642009 Jul 29 05:14:47 PM PDT 24 Jul 29 05:16:09 PM PDT 24 858979448 ps

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.54165304
Short name T8
Test name
Test status
Simulation time 9790921439 ps
CPU time 378.19 seconds
Started Jul 29 05:15:31 PM PDT 24
Finished Jul 29 05:21:49 PM PDT 24
Peak memory 227416 kb
Host smart-4b6ba6c8-dc76-447b-8c2d-65896ea456d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54165304 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.54165304
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1815485942
Short name T34
Test name
Test status
Simulation time 10538956085 ps
CPU time 267.19 seconds
Started Jul 29 05:15:41 PM PDT 24
Finished Jul 29 05:20:09 PM PDT 24
Peak memory 238220 kb
Host smart-155b83eb-78b3-46fc-8877-e20477e87495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815485942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1815485942
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1960604724
Short name T112
Test name
Test status
Simulation time 2922952463 ps
CPU time 152.55 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:17:10 PM PDT 24
Peak memory 213160 kb
Host smart-6206c50a-7126-41c0-82ac-cf0edd36a363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960604724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1960604724
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3824262294
Short name T48
Test name
Test status
Simulation time 8131313474 ps
CPU time 246 seconds
Started Jul 29 05:15:03 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 238604 kb
Host smart-02344dd6-1883-4777-8b8b-93265860cfd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824262294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3824262294
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1642683708
Short name T1
Test name
Test status
Simulation time 1076977564 ps
CPU time 23.14 seconds
Started Jul 29 05:16:16 PM PDT 24
Finished Jul 29 05:16:39 PM PDT 24
Peak memory 220060 kb
Host smart-c9718a0d-d81a-4416-bb44-da0a850d1911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642683708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1642683708
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1299899700
Short name T19
Test name
Test status
Simulation time 1956993846 ps
CPU time 222.69 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 239584 kb
Host smart-8adf4349-e3b5-421a-877a-7e7def5451f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299899700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1299899700
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2473957668
Short name T66
Test name
Test status
Simulation time 1067304140 ps
CPU time 54.65 seconds
Started Jul 29 05:14:39 PM PDT 24
Finished Jul 29 05:15:34 PM PDT 24
Peak memory 215088 kb
Host smart-184c5233-5a1e-45f6-8cef-0764f0156f27
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473957668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2473957668
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2800829025
Short name T41
Test name
Test status
Simulation time 2132818422 ps
CPU time 38.55 seconds
Started Jul 29 05:14:47 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 219992 kb
Host smart-0ae9e6bb-4b64-4664-84ed-f58471cff5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800829025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2800829025
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2712668005
Short name T116
Test name
Test status
Simulation time 360230531 ps
CPU time 152.28 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:17:14 PM PDT 24
Peak memory 214300 kb
Host smart-c3fc8650-619d-4a42-8e1c-6140b6a6b996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712668005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2712668005
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.648042792
Short name T43
Test name
Test status
Simulation time 30072579043 ps
CPU time 583.34 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:25:23 PM PDT 24
Peak memory 232156 kb
Host smart-8de99403-bad8-47f3-99fd-6975cef785fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648042792 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.648042792
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2868354273
Short name T22
Test name
Test status
Simulation time 1301204014 ps
CPU time 10.38 seconds
Started Jul 29 05:14:59 PM PDT 24
Finished Jul 29 05:15:09 PM PDT 24
Peak memory 218952 kb
Host smart-24a74344-df58-4ff8-a2ec-4339c5dec9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868354273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2868354273
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2505973783
Short name T15
Test name
Test status
Simulation time 8312714456 ps
CPU time 146.75 seconds
Started Jul 29 05:15:21 PM PDT 24
Finished Jul 29 05:17:48 PM PDT 24
Peak memory 220340 kb
Host smart-e4309396-1db1-4170-a8f6-981f6f3252e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505973783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2505973783
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4023166598
Short name T158
Test name
Test status
Simulation time 496543337 ps
CPU time 23.5 seconds
Started Jul 29 05:14:47 PM PDT 24
Finished Jul 29 05:15:10 PM PDT 24
Peak memory 219964 kb
Host smart-3c13f022-26d9-462b-a143-6c829dec1954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023166598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4023166598
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1636900482
Short name T49
Test name
Test status
Simulation time 2062706509 ps
CPU time 22.85 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:35 PM PDT 24
Peak memory 220100 kb
Host smart-430c54dd-c3f5-45ed-8015-12e85b9d59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636900482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1636900482
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.287156067
Short name T51
Test name
Test status
Simulation time 193712990797 ps
CPU time 3737.08 seconds
Started Jul 29 05:15:49 PM PDT 24
Finished Jul 29 06:18:06 PM PDT 24
Peak memory 252960 kb
Host smart-ff22cfa1-0032-4702-85c7-9289b4690670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287156067 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.287156067
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3162796296
Short name T89
Test name
Test status
Simulation time 87471386977 ps
CPU time 318.44 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:19:56 PM PDT 24
Peak memory 240180 kb
Host smart-ee56f346-157f-4c65-95a5-af0bda8c846b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162796296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3162796296
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2372589285
Short name T13
Test name
Test status
Simulation time 2490101541 ps
CPU time 10.6 seconds
Started Jul 29 05:15:06 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 220152 kb
Host smart-752e1838-d58b-474e-9269-c8cc1b5cfea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372589285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2372589285
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3563736317
Short name T87
Test name
Test status
Simulation time 555522825 ps
CPU time 25.13 seconds
Started Jul 29 05:15:51 PM PDT 24
Finished Jul 29 05:16:16 PM PDT 24
Peak memory 219896 kb
Host smart-35197bcb-8cc4-452b-85d6-f226c1c9f1d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563736317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3563736317
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.192222364
Short name T71
Test name
Test status
Simulation time 1831532481 ps
CPU time 8.17 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:18 PM PDT 24
Peak memory 210820 kb
Host smart-78b3f540-35e9-487b-8773-7c86840d0923
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192222364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.192222364
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1080188653
Short name T341
Test name
Test status
Simulation time 534398485 ps
CPU time 8.57 seconds
Started Jul 29 05:14:07 PM PDT 24
Finished Jul 29 05:14:16 PM PDT 24
Peak memory 210908 kb
Host smart-57c21aa8-ab10-4983-94d1-17f425b923d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080188653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1080188653
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.902345923
Short name T343
Test name
Test status
Simulation time 263877124 ps
CPU time 13.68 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:26 PM PDT 24
Peak memory 210864 kb
Host smart-038aa2bf-b59a-401c-b5b3-b80ecdf635da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902345923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.902345923
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3152041975
Short name T346
Test name
Test status
Simulation time 402531183 ps
CPU time 8.83 seconds
Started Jul 29 05:14:05 PM PDT 24
Finished Jul 29 05:14:14 PM PDT 24
Peak memory 217840 kb
Host smart-2fef000a-efd6-404b-abda-cf9050ec0ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152041975 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3152041975
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2082099421
Short name T396
Test name
Test status
Simulation time 1124556445 ps
CPU time 9.87 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:20 PM PDT 24
Peak memory 210864 kb
Host smart-dc04de81-051e-4e39-ba79-eeece636284d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082099421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2082099421
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4226701245
Short name T409
Test name
Test status
Simulation time 174538716 ps
CPU time 8.15 seconds
Started Jul 29 05:14:16 PM PDT 24
Finished Jul 29 05:14:24 PM PDT 24
Peak memory 210760 kb
Host smart-1b37c63f-90b1-420e-96c3-65b771ec5786
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226701245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4226701245
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3020815106
Short name T369
Test name
Test status
Simulation time 254764154 ps
CPU time 9.93 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:20 PM PDT 24
Peak memory 210688 kb
Host smart-d55b74ca-ceeb-4242-9bb9-1b301695a8f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020815106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3020815106
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3868014579
Short name T371
Test name
Test status
Simulation time 176007480 ps
CPU time 8.33 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:14:33 PM PDT 24
Peak memory 211568 kb
Host smart-f4cfe25c-e5be-45f9-9b1f-f40c2018a062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868014579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3868014579
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1104967403
Short name T385
Test name
Test status
Simulation time 6989649765 ps
CPU time 17.98 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:30 PM PDT 24
Peak memory 219240 kb
Host smart-d80b8358-2889-4c07-bcd6-a14b78460d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104967403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1104967403
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1513368849
Short name T57
Test name
Test status
Simulation time 658294899 ps
CPU time 154.46 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:16:44 PM PDT 24
Peak memory 214488 kb
Host smart-16fe68d4-d689-4a91-82f3-70555bd51130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513368849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1513368849
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4275712392
Short name T344
Test name
Test status
Simulation time 168117063 ps
CPU time 8.2 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:20 PM PDT 24
Peak memory 210932 kb
Host smart-bf4a0f89-a0cb-401c-bafc-d75385a50388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275712392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4275712392
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2582693094
Short name T85
Test name
Test status
Simulation time 260771145 ps
CPU time 10.66 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:21 PM PDT 24
Peak memory 210896 kb
Host smart-aded91af-e9fd-4a0d-b0ad-a66735d0666e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582693094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2582693094
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.39144388
Short name T80
Test name
Test status
Simulation time 2768747640 ps
CPU time 17.13 seconds
Started Jul 29 05:14:09 PM PDT 24
Finished Jul 29 05:14:26 PM PDT 24
Peak memory 212436 kb
Host smart-7f8e8515-5d5b-462a-be1a-6149d0da1aed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.39144388
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.493074127
Short name T319
Test name
Test status
Simulation time 1112645056 ps
CPU time 10.53 seconds
Started Jul 29 05:14:08 PM PDT 24
Finished Jul 29 05:14:18 PM PDT 24
Peak memory 215220 kb
Host smart-82a37740-55ef-4170-860e-b32f4a240877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493074127 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.493074127
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1308106622
Short name T394
Test name
Test status
Simulation time 688516710 ps
CPU time 8.16 seconds
Started Jul 29 05:14:11 PM PDT 24
Finished Jul 29 05:14:19 PM PDT 24
Peak memory 210836 kb
Host smart-f1ab23cc-f223-4e9b-ab10-875f7f9d8151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308106622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1308106622
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.80612231
Short name T318
Test name
Test status
Simulation time 347085737 ps
CPU time 7.8 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:18 PM PDT 24
Peak memory 210752 kb
Host smart-c18caf8c-a64f-44d6-953f-0137497336e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80612231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_
mem_partial_access.80612231
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1591068736
Short name T360
Test name
Test status
Simulation time 345693479 ps
CPU time 8.32 seconds
Started Jul 29 05:14:25 PM PDT 24
Finished Jul 29 05:14:34 PM PDT 24
Peak memory 210792 kb
Host smart-8701f2b6-98ae-415c-9969-6e13fd884f65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591068736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1591068736
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2304878717
Short name T84
Test name
Test status
Simulation time 1821403559 ps
CPU time 57.37 seconds
Started Jul 29 05:14:06 PM PDT 24
Finished Jul 29 05:15:04 PM PDT 24
Peak memory 215124 kb
Host smart-95aa05a4-816a-4be9-acf4-4909a4d400d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304878717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2304878717
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.280113112
Short name T408
Test name
Test status
Simulation time 174976904 ps
CPU time 8.49 seconds
Started Jul 29 05:14:05 PM PDT 24
Finished Jul 29 05:14:14 PM PDT 24
Peak memory 211812 kb
Host smart-4e139ad9-d8d8-4761-8263-9de027ddea06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280113112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.280113112
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.696459790
Short name T316
Test name
Test status
Simulation time 1380006297 ps
CPU time 13.25 seconds
Started Jul 29 05:14:10 PM PDT 24
Finished Jul 29 05:14:24 PM PDT 24
Peak memory 219144 kb
Host smart-60631931-1d94-4a25-bf7d-d457d826e9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696459790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.696459790
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2116353678
Short name T118
Test name
Test status
Simulation time 2159061777 ps
CPU time 158.44 seconds
Started Jul 29 05:14:07 PM PDT 24
Finished Jul 29 05:16:46 PM PDT 24
Peak memory 214344 kb
Host smart-42eee079-e902-45fc-a71f-fcc3584cd280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116353678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2116353678
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2869038162
Short name T376
Test name
Test status
Simulation time 1859260908 ps
CPU time 10.34 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:14:52 PM PDT 24
Peak memory 216516 kb
Host smart-ee443b31-8602-4957-a1d8-1d249bf712c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869038162 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2869038162
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1399369037
Short name T366
Test name
Test status
Simulation time 1123469587 ps
CPU time 9.78 seconds
Started Jul 29 05:14:34 PM PDT 24
Finished Jul 29 05:14:44 PM PDT 24
Peak memory 211292 kb
Host smart-d53a86cc-c88c-4cbe-a3a5-63e9e3dcfef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399369037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1399369037
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2718689435
Short name T65
Test name
Test status
Simulation time 708317813 ps
CPU time 11.73 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 212668 kb
Host smart-ae58c09e-93ef-43f2-9a9e-dab788d1b17f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718689435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2718689435
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1020842004
Short name T317
Test name
Test status
Simulation time 1237869728 ps
CPU time 13.13 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 217636 kb
Host smart-478663cf-caca-46cf-921b-72811a0dbe68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020842004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1020842004
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1076936292
Short name T119
Test name
Test status
Simulation time 1536028138 ps
CPU time 155.05 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:17:16 PM PDT 24
Peak memory 214212 kb
Host smart-faa55c65-50bb-4f44-ac8f-d402ff88baeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076936292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1076936292
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3826840066
Short name T323
Test name
Test status
Simulation time 317796675 ps
CPU time 8.55 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:14:49 PM PDT 24
Peak memory 217436 kb
Host smart-abe0150a-26b2-4b65-a52b-e0da41288b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826840066 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3826840066
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3280631898
Short name T380
Test name
Test status
Simulation time 2060298126 ps
CPU time 9.85 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 211168 kb
Host smart-a602a2b5-f33d-456c-ab73-21866d766f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280631898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3280631898
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4252790230
Short name T97
Test name
Test status
Simulation time 250328283 ps
CPU time 9.96 seconds
Started Jul 29 05:14:22 PM PDT 24
Finished Jul 29 05:14:33 PM PDT 24
Peak memory 211440 kb
Host smart-9f8cf09f-415f-429c-9067-6ad2849bf307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252790230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4252790230
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1440754278
Short name T388
Test name
Test status
Simulation time 176986756 ps
CPU time 11.69 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 217712 kb
Host smart-80e8002f-5509-4c01-9762-db8921e83db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440754278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1440754278
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1415142625
Short name T389
Test name
Test status
Simulation time 326388987 ps
CPU time 78.95 seconds
Started Jul 29 05:14:35 PM PDT 24
Finished Jul 29 05:15:54 PM PDT 24
Peak memory 214196 kb
Host smart-0f7f044b-178b-46eb-8e58-741d4d6566bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415142625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1415142625
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.287957353
Short name T359
Test name
Test status
Simulation time 542088935 ps
CPU time 10.37 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:43 PM PDT 24
Peak memory 217448 kb
Host smart-c4b822c4-0b3e-4002-b811-a4712ecde3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287957353 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.287957353
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1402881457
Short name T382
Test name
Test status
Simulation time 1901271605 ps
CPU time 9.81 seconds
Started Jul 29 05:14:27 PM PDT 24
Finished Jul 29 05:14:37 PM PDT 24
Peak memory 211324 kb
Host smart-cf8b3427-5a02-42a4-9238-df1c664af717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402881457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1402881457
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.853524358
Short name T350
Test name
Test status
Simulation time 261217174 ps
CPU time 13.31 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 212680 kb
Host smart-84dd3500-2af7-4ec4-bff3-df17fee8c68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853524358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.853524358
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.207341418
Short name T400
Test name
Test status
Simulation time 1025819629 ps
CPU time 17.7 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:50 PM PDT 24
Peak memory 218740 kb
Host smart-e2203480-7ff7-4afc-b434-48136ac1f67d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207341418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.207341418
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2791406105
Short name T404
Test name
Test status
Simulation time 1313693177 ps
CPU time 81.14 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:15:55 PM PDT 24
Peak memory 212876 kb
Host smart-1dff3c41-5875-4d8a-855f-165cd1f92474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791406105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2791406105
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1561723635
Short name T337
Test name
Test status
Simulation time 540929170 ps
CPU time 10.24 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:14:48 PM PDT 24
Peak memory 217224 kb
Host smart-86d4b207-54ae-49aa-8d81-43c42ca2d78a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561723635 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1561723635
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3107633380
Short name T349
Test name
Test status
Simulation time 172457859 ps
CPU time 8.33 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:39 PM PDT 24
Peak memory 211136 kb
Host smart-b0f21a69-a4c1-4176-a7da-fb91ac261cc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107633380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3107633380
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.536564725
Short name T60
Test name
Test status
Simulation time 2872092314 ps
CPU time 37.05 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:15:23 PM PDT 24
Peak memory 214256 kb
Host smart-91f11b4f-e34c-4f4f-a7dc-9b4128057911
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536564725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.536564725
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1874423206
Short name T367
Test name
Test status
Simulation time 338525441 ps
CPU time 8.27 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:14:57 PM PDT 24
Peak memory 211508 kb
Host smart-75342454-5480-40e3-943b-2c9bf6866b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874423206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1874423206
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2401807031
Short name T351
Test name
Test status
Simulation time 721695666 ps
CPU time 11.26 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:44 PM PDT 24
Peak memory 217620 kb
Host smart-81da484a-6e04-4cf2-a5ac-af8e6c7c5807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401807031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2401807031
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2396455248
Short name T56
Test name
Test status
Simulation time 2570782588 ps
CPU time 152.19 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:17:19 PM PDT 24
Peak memory 215444 kb
Host smart-e85fc501-884b-44c1-a51a-f3b65d7a6257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396455248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2396455248
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4095296393
Short name T378
Test name
Test status
Simulation time 195828539 ps
CPU time 9.2 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:53 PM PDT 24
Peak memory 217608 kb
Host smart-ff4ff2c0-9514-4333-b1dd-aa3f30af1741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095296393 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4095296393
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2235224330
Short name T98
Test name
Test status
Simulation time 387125754 ps
CPU time 9.83 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:14:34 PM PDT 24
Peak memory 210852 kb
Host smart-623f6644-2421-4b86-aca3-54fb5961f53a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235224330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2235224330
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1105363872
Short name T58
Test name
Test status
Simulation time 506386983 ps
CPU time 9.99 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:14:51 PM PDT 24
Peak memory 211552 kb
Host smart-83dc061d-d5e9-4d62-a77b-215bf24d9985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105363872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1105363872
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2006688451
Short name T345
Test name
Test status
Simulation time 2067738691 ps
CPU time 14.13 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:14:51 PM PDT 24
Peak memory 217640 kb
Host smart-80966a83-7a71-48db-a756-bc05acdf00b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006688451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2006688451
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2254642009
Short name T410
Test name
Test status
Simulation time 858979448 ps
CPU time 81.3 seconds
Started Jul 29 05:14:47 PM PDT 24
Finished Jul 29 05:16:09 PM PDT 24
Peak memory 212976 kb
Host smart-84af7df7-f6ed-450c-8858-b67d58707719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254642009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2254642009
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2609672823
Short name T352
Test name
Test status
Simulation time 353718638 ps
CPU time 8.05 seconds
Started Jul 29 05:14:27 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 213940 kb
Host smart-cb570e17-bb76-4432-8a3f-cadb02d8d91f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609672823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2609672823
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3105447268
Short name T333
Test name
Test status
Simulation time 660826715 ps
CPU time 8.12 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:51 PM PDT 24
Peak memory 210896 kb
Host smart-01af7cd3-4304-4fee-a4fc-99b8c8dae1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105447268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3105447268
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.710219259
Short name T362
Test name
Test status
Simulation time 1034992718 ps
CPU time 10.31 seconds
Started Jul 29 05:14:26 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 211624 kb
Host smart-0f463a26-8842-485c-b001-a4e4162b4032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710219259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.710219259
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2574437160
Short name T374
Test name
Test status
Simulation time 167900934 ps
CPU time 13.3 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:14:54 PM PDT 24
Peak memory 217868 kb
Host smart-d14b31c4-27da-48cd-b051-828e4f120694
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574437160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2574437160
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1172068623
Short name T117
Test name
Test status
Simulation time 576862100 ps
CPU time 148.76 seconds
Started Jul 29 05:14:45 PM PDT 24
Finished Jul 29 05:17:14 PM PDT 24
Peak memory 214428 kb
Host smart-96d87382-5327-4a21-93ca-e73eb2c21b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172068623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1172068623
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4006536903
Short name T386
Test name
Test status
Simulation time 355414474 ps
CPU time 8.88 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 219064 kb
Host smart-e62faddc-498a-40b0-a105-5135c7d4053e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006536903 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4006536903
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1578989791
Short name T368
Test name
Test status
Simulation time 255236244 ps
CPU time 9.57 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:14:52 PM PDT 24
Peak memory 211032 kb
Host smart-2711b4e9-15b1-41f7-a0df-d025922e2966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578989791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1578989791
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1537032352
Short name T326
Test name
Test status
Simulation time 2241407774 ps
CPU time 9.59 seconds
Started Jul 29 05:14:45 PM PDT 24
Finished Jul 29 05:14:55 PM PDT 24
Peak memory 211436 kb
Host smart-4f7a33af-1251-4a7f-93f1-c6105a20bdf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537032352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1537032352
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.826562537
Short name T354
Test name
Test status
Simulation time 339162720 ps
CPU time 13.54 seconds
Started Jul 29 05:14:36 PM PDT 24
Finished Jul 29 05:14:50 PM PDT 24
Peak memory 219060 kb
Host smart-482b7f09-9a9d-467f-b208-667c5821575a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826562537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.826562537
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2157409274
Short name T59
Test name
Test status
Simulation time 581767313 ps
CPU time 11.23 seconds
Started Jul 29 05:14:27 PM PDT 24
Finished Jul 29 05:14:38 PM PDT 24
Peak memory 217640 kb
Host smart-a8aab8d5-7eb8-4b2f-9d3c-f80ded912e3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157409274 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2157409274
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.214637163
Short name T364
Test name
Test status
Simulation time 508696311 ps
CPU time 9.92 seconds
Started Jul 29 05:14:26 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 211300 kb
Host smart-15a5618a-d6a1-4ffb-9ccb-103a4f9051a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214637163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.214637163
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.366407862
Short name T64
Test name
Test status
Simulation time 171480044 ps
CPU time 8.08 seconds
Started Jul 29 05:14:35 PM PDT 24
Finished Jul 29 05:14:43 PM PDT 24
Peak memory 211144 kb
Host smart-b45e31f8-fb7a-4e11-9331-ff51645bbb19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366407862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.366407862
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2916538576
Short name T314
Test name
Test status
Simulation time 332297266 ps
CPU time 11.04 seconds
Started Jul 29 05:14:29 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 217680 kb
Host smart-814dac44-a6f8-41e6-aa22-25fb76bd9d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916538576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2916538576
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3425716315
Short name T355
Test name
Test status
Simulation time 1289377303 ps
CPU time 79.14 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:16:00 PM PDT 24
Peak memory 214076 kb
Host smart-47f781cc-253e-4cff-b5b1-59e5e7fc002b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425716315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3425716315
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.955440411
Short name T330
Test name
Test status
Simulation time 206770130 ps
CPU time 9.13 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:14:47 PM PDT 24
Peak memory 216904 kb
Host smart-6edc8c82-0c8d-4195-b5ff-b9d38e8e370d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955440411 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.955440411
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1823654800
Short name T402
Test name
Test status
Simulation time 1034391761 ps
CPU time 9.93 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:14:48 PM PDT 24
Peak memory 210840 kb
Host smart-1239cc91-b5ec-489b-92f4-7fc156096e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823654800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1823654800
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2070173506
Short name T370
Test name
Test status
Simulation time 577593331 ps
CPU time 10.01 seconds
Started Jul 29 05:14:30 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 211460 kb
Host smart-02b88a96-7efd-422c-a7dc-e9710b1a0bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070173506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2070173506
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1338875192
Short name T406
Test name
Test status
Simulation time 332609915 ps
CPU time 13.22 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:14:55 PM PDT 24
Peak memory 219080 kb
Host smart-3c7ae599-dca8-44aa-a167-492ee005bd1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338875192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1338875192
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3335529746
Short name T55
Test name
Test status
Simulation time 1760233034 ps
CPU time 158.05 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:17:22 PM PDT 24
Peak memory 214300 kb
Host smart-d8e50f07-ecb8-452a-8aa1-5bd6af5a4e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335529746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3335529746
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.763710084
Short name T390
Test name
Test status
Simulation time 179870227 ps
CPU time 8.86 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 216760 kb
Host smart-31632bdc-d545-4ca3-8e00-412361db04c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763710084 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.763710084
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.548678386
Short name T407
Test name
Test status
Simulation time 672872860 ps
CPU time 9.69 seconds
Started Jul 29 05:14:36 PM PDT 24
Finished Jul 29 05:14:46 PM PDT 24
Peak memory 210912 kb
Host smart-eb07771e-db9c-48dc-875d-43db45206111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548678386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.548678386
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4087227236
Short name T69
Test name
Test status
Simulation time 3272349706 ps
CPU time 37.54 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:15:11 PM PDT 24
Peak memory 214144 kb
Host smart-5740e96e-dc65-4831-9d6d-04678299ac26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087227236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4087227236
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1743215948
Short name T375
Test name
Test status
Simulation time 514468006 ps
CPU time 10.02 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:14:51 PM PDT 24
Peak memory 211580 kb
Host smart-2fdfd45f-f66d-4bbd-8ae7-6dbd5caa7e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743215948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1743215948
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1083161115
Short name T377
Test name
Test status
Simulation time 332380890 ps
CPU time 11.17 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 217704 kb
Host smart-cc0af225-6ad1-4d45-b8e0-4b7268f713bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083161115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1083161115
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1390922343
Short name T387
Test name
Test status
Simulation time 3535511845 ps
CPU time 9.67 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 211104 kb
Host smart-38468361-0294-4b1b-88f2-34fff8db4bdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390922343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1390922343
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1794473937
Short name T328
Test name
Test status
Simulation time 1177304779 ps
CPU time 8.74 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 211132 kb
Host smart-54a215cf-67a0-4e2a-96ff-04408b4ce895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794473937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1794473937
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1241436416
Short name T81
Test name
Test status
Simulation time 344481239 ps
CPU time 11.38 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:14:51 PM PDT 24
Peak memory 210864 kb
Host smart-c6b3e604-672d-4870-bbb7-780fb8dc82de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241436416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1241436416
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1095055157
Short name T358
Test name
Test status
Simulation time 266734496 ps
CPU time 10.5 seconds
Started Jul 29 05:14:28 PM PDT 24
Finished Jul 29 05:14:38 PM PDT 24
Peak memory 216748 kb
Host smart-58e75251-9af2-449d-b522-2aeee8435c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095055157 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1095055157
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.159547026
Short name T399
Test name
Test status
Simulation time 257227289 ps
CPU time 9.86 seconds
Started Jul 29 05:14:20 PM PDT 24
Finished Jul 29 05:14:30 PM PDT 24
Peak memory 210924 kb
Host smart-54900482-90b1-4307-9985-66deb5a18895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159547026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.159547026
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3259284942
Short name T331
Test name
Test status
Simulation time 664226031 ps
CPU time 8.2 seconds
Started Jul 29 05:14:26 PM PDT 24
Finished Jul 29 05:14:34 PM PDT 24
Peak memory 210748 kb
Host smart-d458aab5-b0aa-46b7-96df-5d38b686450a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259284942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3259284942
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.117726747
Short name T324
Test name
Test status
Simulation time 2051298480 ps
CPU time 15.14 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:14:39 PM PDT 24
Peak memory 210856 kb
Host smart-5f8c4653-9fbf-4261-be3c-0aef7a45360a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117726747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
117726747
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.222611240
Short name T336
Test name
Test status
Simulation time 510286354 ps
CPU time 10.16 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 211584 kb
Host smart-289b9021-8463-461c-b21e-5a94b4b024bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222611240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.222611240
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4264988642
Short name T398
Test name
Test status
Simulation time 3095504327 ps
CPU time 13.39 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:26 PM PDT 24
Peak memory 217628 kb
Host smart-478dc7fc-392a-4449-9a02-1fa0d3cd9962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264988642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4264988642
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3299183711
Short name T114
Test name
Test status
Simulation time 804941092 ps
CPU time 153.4 seconds
Started Jul 29 05:14:25 PM PDT 24
Finished Jul 29 05:16:58 PM PDT 24
Peak memory 214496 kb
Host smart-c3d83e9d-a8f6-496b-9915-6b0954200c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299183711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3299183711
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3602132922
Short name T342
Test name
Test status
Simulation time 660848477 ps
CPU time 8.19 seconds
Started Jul 29 05:14:23 PM PDT 24
Finished Jul 29 05:14:31 PM PDT 24
Peak memory 211168 kb
Host smart-19baf7cc-1c1b-4b22-b7fd-de395dbf31d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602132922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3602132922
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3540465881
Short name T320
Test name
Test status
Simulation time 195007073 ps
CPU time 8.14 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 210780 kb
Host smart-65e44f6c-aeb8-41b1-bfd6-fbc17d5f499a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540465881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3540465881
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.396775969
Short name T365
Test name
Test status
Simulation time 669538610 ps
CPU time 11.95 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:25 PM PDT 24
Peak memory 210836 kb
Host smart-adf61a98-51aa-4342-912b-cff35543f5dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396775969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.396775969
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.349378568
Short name T383
Test name
Test status
Simulation time 693041824 ps
CPU time 9.21 seconds
Started Jul 29 05:14:14 PM PDT 24
Finished Jul 29 05:14:23 PM PDT 24
Peak memory 217648 kb
Host smart-2b961d10-f6a2-454f-8572-860ea7206f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349378568 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.349378568
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1056269602
Short name T403
Test name
Test status
Simulation time 255131523 ps
CPU time 9.9 seconds
Started Jul 29 05:14:23 PM PDT 24
Finished Jul 29 05:14:33 PM PDT 24
Peak memory 211576 kb
Host smart-dc99344d-827a-4843-ae18-2fdbe2115376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056269602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1056269602
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2827790424
Short name T335
Test name
Test status
Simulation time 1035244902 ps
CPU time 9.51 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:43 PM PDT 24
Peak memory 210792 kb
Host smart-8fbe9c41-458c-4d29-a0d6-5128f4ce2315
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827790424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2827790424
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3521416834
Short name T315
Test name
Test status
Simulation time 259986388 ps
CPU time 10.23 seconds
Started Jul 29 05:14:14 PM PDT 24
Finished Jul 29 05:14:24 PM PDT 24
Peak memory 210776 kb
Host smart-bb8a491f-67d6-46b9-87ac-666c0087e735
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521416834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3521416834
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1019200713
Short name T95
Test name
Test status
Simulation time 800771348 ps
CPU time 10.06 seconds
Started Jul 29 05:14:25 PM PDT 24
Finished Jul 29 05:14:35 PM PDT 24
Peak memory 211692 kb
Host smart-34eb8b94-0d42-4a76-9a85-8b710f6fd218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019200713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1019200713
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3035202938
Short name T393
Test name
Test status
Simulation time 2064401115 ps
CPU time 13.82 seconds
Started Jul 29 05:14:15 PM PDT 24
Finished Jul 29 05:14:29 PM PDT 24
Peak memory 217752 kb
Host smart-166e888b-9629-405a-8b47-2fe2150bc335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035202938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3035202938
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.374358024
Short name T111
Test name
Test status
Simulation time 847899229 ps
CPU time 159.59 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:17:04 PM PDT 24
Peak memory 215748 kb
Host smart-00276ee3-d62d-47e9-8fd1-efdc26e171b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374358024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.374358024
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.364721766
Short name T361
Test name
Test status
Simulation time 751717374 ps
CPU time 8.08 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 211112 kb
Host smart-a7760c39-9c13-4759-b21d-fe7e710ba29f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364721766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.364721766
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1064844973
Short name T347
Test name
Test status
Simulation time 664988126 ps
CPU time 8.61 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:14:49 PM PDT 24
Peak memory 210992 kb
Host smart-57ea6666-825d-4e9a-9621-55215a291e6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064844973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1064844973
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.628436411
Short name T353
Test name
Test status
Simulation time 720145192 ps
CPU time 17.06 seconds
Started Jul 29 05:14:28 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 212172 kb
Host smart-f1b87913-0a86-4959-871d-4fa6e84350ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628436411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.628436411
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.526975310
Short name T363
Test name
Test status
Simulation time 188850989 ps
CPU time 8.77 seconds
Started Jul 29 05:14:28 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 216564 kb
Host smart-0110aaa2-bb44-4dee-b8e4-6538ffab049b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526975310 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.526975310
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2554140545
Short name T379
Test name
Test status
Simulation time 257150528 ps
CPU time 10.05 seconds
Started Jul 29 05:14:30 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 210820 kb
Host smart-cf7cdbfe-995e-4b58-9365-0cff310ef0f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554140545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2554140545
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1649726888
Short name T327
Test name
Test status
Simulation time 1270493224 ps
CPU time 8.25 seconds
Started Jul 29 05:14:11 PM PDT 24
Finished Jul 29 05:14:19 PM PDT 24
Peak memory 210756 kb
Host smart-8542ac31-2e08-4144-be18-38b507e70f1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649726888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1649726888
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1330049748
Short name T329
Test name
Test status
Simulation time 993765849 ps
CPU time 9.59 seconds
Started Jul 29 05:14:23 PM PDT 24
Finished Jul 29 05:14:33 PM PDT 24
Peak memory 210780 kb
Host smart-cf697926-837b-449f-9795-dfc409524dfb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330049748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1330049748
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.462054098
Short name T70
Test name
Test status
Simulation time 1053332933 ps
CPU time 56.16 seconds
Started Jul 29 05:14:34 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 219140 kb
Host smart-0599b0d2-e41b-4761-8c4d-2b63a6ed3def
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462054098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.462054098
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3859037294
Short name T68
Test name
Test status
Simulation time 2058889334 ps
CPU time 8.28 seconds
Started Jul 29 05:14:28 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 211608 kb
Host smart-e45d56a9-9746-485b-89a6-68159847cfb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859037294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3859037294
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2498548308
Short name T348
Test name
Test status
Simulation time 173459644 ps
CPU time 12.74 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:45 PM PDT 24
Peak memory 217788 kb
Host smart-3910fc80-f2f6-4052-9638-3ab6698dbed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498548308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2498548308
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2903893927
Short name T110
Test name
Test status
Simulation time 1592481565 ps
CPU time 156.09 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:17:00 PM PDT 24
Peak memory 214552 kb
Host smart-55c07ee7-3de2-412a-bb2e-09f20dc33537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903893927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2903893927
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.201217966
Short name T322
Test name
Test status
Simulation time 362064057 ps
CPU time 9.09 seconds
Started Jul 29 05:14:31 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 216372 kb
Host smart-b5c0be42-8d74-44e9-940b-771fb6622e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201217966 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.201217966
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.981743132
Short name T338
Test name
Test status
Simulation time 688125392 ps
CPU time 8.11 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 210868 kb
Host smart-2e4042f9-0380-4b65-abe7-1c5cc1a88368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981743132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.981743132
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1870129360
Short name T391
Test name
Test status
Simulation time 1402773493 ps
CPU time 37.62 seconds
Started Jul 29 05:14:27 PM PDT 24
Finished Jul 29 05:15:05 PM PDT 24
Peak memory 214300 kb
Host smart-ae16251c-bc75-4932-9bd8-8b52eb573671
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870129360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1870129360
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3844740542
Short name T397
Test name
Test status
Simulation time 167693642 ps
CPU time 8.17 seconds
Started Jul 29 05:14:27 PM PDT 24
Finished Jul 29 05:14:35 PM PDT 24
Peak memory 211476 kb
Host smart-6a558aba-b688-4bbb-8303-afed5b33c251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844740542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3844740542
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1181387733
Short name T395
Test name
Test status
Simulation time 495618917 ps
CPU time 13.79 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:46 PM PDT 24
Peak memory 217560 kb
Host smart-d4e92cb8-d81d-4913-a501-6c00c4a0b25d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181387733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1181387733
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.772606248
Short name T356
Test name
Test status
Simulation time 431763310 ps
CPU time 80.93 seconds
Started Jul 29 05:14:28 PM PDT 24
Finished Jul 29 05:15:49 PM PDT 24
Peak memory 214028 kb
Host smart-ffe73a89-1589-48ed-af1a-8e2aa5514f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772606248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.772606248
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4094281755
Short name T332
Test name
Test status
Simulation time 255527338 ps
CPU time 10.37 seconds
Started Jul 29 05:14:26 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 215132 kb
Host smart-6a21c45e-143d-49f5-9d66-0039502ba387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094281755 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4094281755
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.984103647
Short name T334
Test name
Test status
Simulation time 994592208 ps
CPU time 9.7 seconds
Started Jul 29 05:14:24 PM PDT 24
Finished Jul 29 05:14:34 PM PDT 24
Peak memory 211180 kb
Host smart-7b772caf-04ed-4d9b-b52d-b263a05ac70a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984103647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.984103647
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3952685605
Short name T83
Test name
Test status
Simulation time 1033537256 ps
CPU time 44.89 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 213944 kb
Host smart-1ce578b3-317d-45c1-bb22-6796c7b63b88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952685605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3952685605
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4146264248
Short name T381
Test name
Test status
Simulation time 2414393330 ps
CPU time 11.93 seconds
Started Jul 29 05:14:22 PM PDT 24
Finished Jul 29 05:14:34 PM PDT 24
Peak memory 212944 kb
Host smart-a7cee2b9-5e38-4ef0-b0d8-bef41c29edda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146264248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4146264248
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2686388973
Short name T392
Test name
Test status
Simulation time 866754036 ps
CPU time 14.79 seconds
Started Jul 29 05:14:12 PM PDT 24
Finished Jul 29 05:14:27 PM PDT 24
Peak memory 217856 kb
Host smart-7412d6ca-8727-4f81-bf5b-6c1ff54ae3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686388973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2686388973
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3695027439
Short name T357
Test name
Test status
Simulation time 341589706 ps
CPU time 80.96 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:15:54 PM PDT 24
Peak memory 213704 kb
Host smart-6b0023c5-07c4-4baa-bc89-31e859e49d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695027439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3695027439
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3894165873
Short name T401
Test name
Test status
Simulation time 1370338480 ps
CPU time 8.89 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 216756 kb
Host smart-441014fc-4cad-470f-a0af-686cec714349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894165873 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3894165873
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2521840504
Short name T82
Test name
Test status
Simulation time 689696418 ps
CPU time 8.01 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 210968 kb
Host smart-a4afd372-3d2d-4150-9cfb-a3c064802d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521840504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2521840504
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3037277420
Short name T384
Test name
Test status
Simulation time 1035810036 ps
CPU time 10 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:14:59 PM PDT 24
Peak memory 211528 kb
Host smart-63ade76f-eb7f-4e91-8e6f-071755688e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037277420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3037277420
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2607711353
Short name T373
Test name
Test status
Simulation time 174921298 ps
CPU time 11.52 seconds
Started Jul 29 05:14:30 PM PDT 24
Finished Jul 29 05:14:42 PM PDT 24
Peak memory 219144 kb
Host smart-e916bc31-2bd7-4ebb-bfcb-783f6a6becd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607711353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2607711353
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1383919432
Short name T372
Test name
Test status
Simulation time 630811206 ps
CPU time 81.76 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:15:55 PM PDT 24
Peak memory 213068 kb
Host smart-2e5456ea-8530-481f-8941-7af7a2d2fc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383919432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1383919432
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2724807665
Short name T339
Test name
Test status
Simulation time 274312460 ps
CPU time 11.94 seconds
Started Jul 29 05:14:25 PM PDT 24
Finished Jul 29 05:14:38 PM PDT 24
Peak memory 218064 kb
Host smart-99e50e4f-835f-4e7b-a111-6663cd2b220d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724807665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2724807665
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.226200216
Short name T67
Test name
Test status
Simulation time 175169491 ps
CPU time 8.26 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 211292 kb
Host smart-45bdacfe-07f7-42ae-9f18-8c31564fd446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226200216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.226200216
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3208140191
Short name T96
Test name
Test status
Simulation time 1077043612 ps
CPU time 9.78 seconds
Started Jul 29 05:14:30 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 210944 kb
Host smart-48e872ab-e28e-4b03-8422-cb1ae764a8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208140191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3208140191
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1313859648
Short name T340
Test name
Test status
Simulation time 1236174438 ps
CPU time 14.92 seconds
Started Jul 29 05:14:29 PM PDT 24
Finished Jul 29 05:14:44 PM PDT 24
Peak memory 219164 kb
Host smart-f7c737d8-6826-486d-9788-52bd9aeaa32a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313859648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1313859648
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.926934404
Short name T115
Test name
Test status
Simulation time 286770056 ps
CPU time 81.23 seconds
Started Jul 29 05:14:49 PM PDT 24
Finished Jul 29 05:16:10 PM PDT 24
Peak memory 214028 kb
Host smart-1e82f91f-b475-4ccc-a336-2284ba279223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926934404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.926934404
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1241151283
Short name T325
Test name
Test status
Simulation time 184998713 ps
CPU time 9.42 seconds
Started Jul 29 05:14:35 PM PDT 24
Finished Jul 29 05:14:44 PM PDT 24
Peak memory 217432 kb
Host smart-214332bb-6ac1-4be1-87ac-0facc2426a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241151283 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1241151283
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1668521783
Short name T86
Test name
Test status
Simulation time 251516135 ps
CPU time 9.88 seconds
Started Jul 29 05:14:32 PM PDT 24
Finished Jul 29 05:14:43 PM PDT 24
Peak memory 211112 kb
Host smart-d9c89995-56a7-4367-a212-66b1a14a7352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668521783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1668521783
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3313364679
Short name T405
Test name
Test status
Simulation time 997433524 ps
CPU time 18.37 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:14:57 PM PDT 24
Peak memory 212676 kb
Host smart-496a5179-3779-4791-99f2-66bfb3f74652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313364679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3313364679
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3986203787
Short name T321
Test name
Test status
Simulation time 918747553 ps
CPU time 13.76 seconds
Started Jul 29 05:14:22 PM PDT 24
Finished Jul 29 05:14:35 PM PDT 24
Peak memory 218800 kb
Host smart-a66242e9-aad4-4ec8-a52e-b09992e3b85e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986203787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3986203787
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2850425932
Short name T113
Test name
Test status
Simulation time 888579508 ps
CPU time 78.8 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:15:59 PM PDT 24
Peak memory 213788 kb
Host smart-8e16e01d-c715-48e1-8e4e-5def35d3d5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850425932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2850425932
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4204250264
Short name T284
Test name
Test status
Simulation time 178079852 ps
CPU time 8.22 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:14:41 PM PDT 24
Peak memory 219000 kb
Host smart-ba02cea6-983a-4865-b87e-9fb583a56117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204250264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4204250264
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2275634471
Short name T5
Test name
Test status
Simulation time 665196069 ps
CPU time 19.45 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:15:06 PM PDT 24
Peak memory 219960 kb
Host smart-d0e2a17b-28c5-4206-8a81-104d747c1dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275634471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2275634471
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.60377015
Short name T216
Test name
Test status
Simulation time 1062405880 ps
CPU time 12.17 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 220012 kb
Host smart-2d937e05-8b1b-4990-839e-de1f603bb7ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60377015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.60377015
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2937590536
Short name T21
Test name
Test status
Simulation time 1349470112 ps
CPU time 116.88 seconds
Started Jul 29 05:14:39 PM PDT 24
Finished Jul 29 05:16:36 PM PDT 24
Peak memory 235864 kb
Host smart-edaf52c8-fe15-4e03-bf0b-3620cde4db28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937590536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2937590536
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3509237389
Short name T188
Test name
Test status
Simulation time 182518414 ps
CPU time 10.26 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:14:47 PM PDT 24
Peak memory 219896 kb
Host smart-62bd271a-a0c0-4e44-8b6a-3c8896d74d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509237389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3509237389
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3221612178
Short name T231
Test name
Test status
Simulation time 1069211913 ps
CPU time 30.45 seconds
Started Jul 29 05:14:33 PM PDT 24
Finished Jul 29 05:15:04 PM PDT 24
Peak memory 219960 kb
Host smart-cdf5b3f4-f646-48ae-8025-820b270ca1ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221612178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3221612178
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2199924901
Short name T168
Test name
Test status
Simulation time 174780899 ps
CPU time 8.25 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:14:46 PM PDT 24
Peak memory 219128 kb
Host smart-92ee4d00-0c6b-4c49-b851-73d951f75a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199924901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2199924901
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2423289432
Short name T301
Test name
Test status
Simulation time 11043884983 ps
CPU time 337.88 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:20:19 PM PDT 24
Peak memory 243720 kb
Host smart-2c5efa25-64c8-4b04-885d-25b8160f6366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423289432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2423289432
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2057053968
Short name T246
Test name
Test status
Simulation time 258241360 ps
CPU time 12.28 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 220004 kb
Host smart-5c85b3fd-4839-4486-8a93-c1c0df6c8308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057053968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2057053968
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2944534274
Short name T24
Test name
Test status
Simulation time 1480044479 ps
CPU time 227.69 seconds
Started Jul 29 05:14:34 PM PDT 24
Finished Jul 29 05:18:22 PM PDT 24
Peak memory 239456 kb
Host smart-859a301d-34a8-4403-bd36-350ece2c0158
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944534274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2944534274
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2176227219
Short name T311
Test name
Test status
Simulation time 181045569 ps
CPU time 10.56 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:14:53 PM PDT 24
Peak memory 219992 kb
Host smart-50d4d9bc-b3b0-45d9-8c75-9a5d85f01514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176227219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2176227219
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2615782709
Short name T79
Test name
Test status
Simulation time 2107665569 ps
CPU time 43.59 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:15:28 PM PDT 24
Peak memory 219956 kb
Host smart-90ffa799-f60a-4744-93b7-3c7155c55d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615782709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2615782709
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.859574303
Short name T286
Test name
Test status
Simulation time 4161042853 ps
CPU time 283 seconds
Started Jul 29 05:15:04 PM PDT 24
Finished Jul 29 05:19:47 PM PDT 24
Peak memory 238576 kb
Host smart-86fe0f11-2516-454b-ab40-780a897d5081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859574303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.859574303
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1770353588
Short name T262
Test name
Test status
Simulation time 666208263 ps
CPU time 19.84 seconds
Started Jul 29 05:15:01 PM PDT 24
Finished Jul 29 05:15:21 PM PDT 24
Peak memory 220020 kb
Host smart-9fba120f-4527-4744-8c82-c013128d7347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770353588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1770353588
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2913490735
Short name T307
Test name
Test status
Simulation time 2139047364 ps
CPU time 10.18 seconds
Started Jul 29 05:15:01 PM PDT 24
Finished Jul 29 05:15:12 PM PDT 24
Peak memory 219712 kb
Host smart-98e848c0-80b3-401d-b494-26c88c00d66a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913490735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2913490735
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3066007902
Short name T312
Test name
Test status
Simulation time 686487964 ps
CPU time 21.48 seconds
Started Jul 29 05:15:01 PM PDT 24
Finished Jul 29 05:15:23 PM PDT 24
Peak memory 219884 kb
Host smart-0570ee0d-6719-46c0-8e08-073ea5253c65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066007902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3066007902
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.58461763
Short name T204
Test name
Test status
Simulation time 995283860 ps
CPU time 9.92 seconds
Started Jul 29 05:15:07 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 219108 kb
Host smart-2e01f61a-6c81-4ea0-ac81-0de539621aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58461763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.58461763
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.874217253
Short name T247
Test name
Test status
Simulation time 425717666 ps
CPU time 19.24 seconds
Started Jul 29 05:15:01 PM PDT 24
Finished Jul 29 05:15:21 PM PDT 24
Peak memory 219744 kb
Host smart-c9b043a9-b8ba-4a63-8123-ff4b2f808c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874217253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.874217253
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1136891146
Short name T310
Test name
Test status
Simulation time 1084410095 ps
CPU time 12.61 seconds
Started Jul 29 05:15:01 PM PDT 24
Finished Jul 29 05:15:13 PM PDT 24
Peak memory 220036 kb
Host smart-674613e7-2768-42f4-9921-cc3e05ff2870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136891146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1136891146
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.807335600
Short name T76
Test name
Test status
Simulation time 406166499 ps
CPU time 32.74 seconds
Started Jul 29 05:14:59 PM PDT 24
Finished Jul 29 05:15:32 PM PDT 24
Peak memory 219884 kb
Host smart-3a59e7b6-b9cf-41a9-9734-cbcc02a547b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807335600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.807335600
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3595282326
Short name T214
Test name
Test status
Simulation time 688882447 ps
CPU time 8.22 seconds
Started Jul 29 05:15:07 PM PDT 24
Finished Jul 29 05:15:15 PM PDT 24
Peak memory 219148 kb
Host smart-d31b2287-5cf5-452d-88a9-2f20b8dae18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595282326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3595282326
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4101482510
Short name T291
Test name
Test status
Simulation time 4800963184 ps
CPU time 262.24 seconds
Started Jul 29 05:15:07 PM PDT 24
Finished Jul 29 05:19:30 PM PDT 24
Peak memory 234572 kb
Host smart-e6099ba4-6c4a-4c6a-a374-f04d7b739b50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101482510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4101482510
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3753661646
Short name T160
Test name
Test status
Simulation time 344771425 ps
CPU time 19.71 seconds
Started Jul 29 05:15:06 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 220048 kb
Host smart-f3bea17c-db18-4286-ad7d-c8fad1fe4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753661646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3753661646
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1724565610
Short name T295
Test name
Test status
Simulation time 2702984382 ps
CPU time 35.16 seconds
Started Jul 29 05:15:08 PM PDT 24
Finished Jul 29 05:15:43 PM PDT 24
Peak memory 220112 kb
Host smart-c030e052-3f35-41e8-9f34-84a08b220f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724565610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1724565610
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3566689539
Short name T196
Test name
Test status
Simulation time 250290002 ps
CPU time 10.25 seconds
Started Jul 29 05:15:06 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 219012 kb
Host smart-aaee6f8f-2132-4d8c-a0c9-cb9161899409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566689539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3566689539
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4227332259
Short name T145
Test name
Test status
Simulation time 3016422559 ps
CPU time 210.8 seconds
Started Jul 29 05:15:08 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 234608 kb
Host smart-fd4186ae-b427-4643-952a-9c9f24b479d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227332259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4227332259
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1864051064
Short name T178
Test name
Test status
Simulation time 513145150 ps
CPU time 22.25 seconds
Started Jul 29 05:15:05 PM PDT 24
Finished Jul 29 05:15:28 PM PDT 24
Peak memory 220056 kb
Host smart-4913b1fc-6d76-4276-b3cd-69d56b4ef2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864051064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1864051064
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2713720862
Short name T238
Test name
Test status
Simulation time 181746608 ps
CPU time 10.55 seconds
Started Jul 29 05:15:07 PM PDT 24
Finished Jul 29 05:15:18 PM PDT 24
Peak memory 220032 kb
Host smart-2adb6d89-03d7-4e85-983e-c8510ddb69d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713720862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2713720862
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1970747224
Short name T93
Test name
Test status
Simulation time 1061012915 ps
CPU time 24.03 seconds
Started Jul 29 05:15:08 PM PDT 24
Finished Jul 29 05:15:32 PM PDT 24
Peak memory 219992 kb
Host smart-8cb7a541-7834-463d-b605-03e6c01e0bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970747224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1970747224
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.323845574
Short name T90
Test name
Test status
Simulation time 1030099579 ps
CPU time 10.1 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:15:24 PM PDT 24
Peak memory 219036 kb
Host smart-50b2cf26-5fcd-4ffb-9dac-db57e9ad4dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323845574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.323845574
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.756591364
Short name T17
Test name
Test status
Simulation time 26710044146 ps
CPU time 144.6 seconds
Started Jul 29 05:15:11 PM PDT 24
Finished Jul 29 05:17:36 PM PDT 24
Peak memory 229204 kb
Host smart-3efe1050-4741-4de4-ab31-fe3b5f4f7cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756591364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.756591364
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.638590845
Short name T137
Test name
Test status
Simulation time 516526003 ps
CPU time 22.78 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:35 PM PDT 24
Peak memory 220232 kb
Host smart-d4d2bc20-be66-4b74-a7ce-c2199de99e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638590845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.638590845
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1796152538
Short name T294
Test name
Test status
Simulation time 3177908807 ps
CPU time 12.27 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 220168 kb
Host smart-1b2d937c-50e3-441e-a43b-c8b95eede822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796152538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1796152538
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1981360740
Short name T191
Test name
Test status
Simulation time 891153168 ps
CPU time 40.04 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:15:53 PM PDT 24
Peak memory 220020 kb
Host smart-42653476-97e6-4f4e-b2ce-b456aaa8ccba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981360740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1981360740
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1219940265
Short name T229
Test name
Test status
Simulation time 989809371 ps
CPU time 10.26 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:22 PM PDT 24
Peak memory 219048 kb
Host smart-c354b4bd-bae0-4c23-ad00-dc871085219d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219940265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1219940265
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.740310598
Short name T256
Test name
Test status
Simulation time 11976369565 ps
CPU time 249.01 seconds
Started Jul 29 05:15:11 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 240484 kb
Host smart-126c6ec0-6854-48b5-a53a-151647835d12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740310598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.740310598
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2103885134
Short name T139
Test name
Test status
Simulation time 508581834 ps
CPU time 22.22 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:34 PM PDT 24
Peak memory 220052 kb
Host smart-1a36b259-609e-44f9-aad3-3c33223baadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103885134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2103885134
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1087463213
Short name T198
Test name
Test status
Simulation time 997065363 ps
CPU time 16.87 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:29 PM PDT 24
Peak memory 219444 kb
Host smart-7eedb231-50a1-42db-bc74-35755dd89ba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087463213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1087463213
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.218081514
Short name T107
Test name
Test status
Simulation time 1484915900 ps
CPU time 24.16 seconds
Started Jul 29 05:15:14 PM PDT 24
Finished Jul 29 05:15:38 PM PDT 24
Peak memory 219960 kb
Host smart-2273c17c-9508-42d4-8683-11d2d41e13c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218081514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.218081514
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3828124963
Short name T218
Test name
Test status
Simulation time 170846888 ps
CPU time 8.37 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:20 PM PDT 24
Peak memory 219152 kb
Host smart-5232977e-ff65-4001-9904-00e733a5fc74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828124963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3828124963
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.123830455
Short name T228
Test name
Test status
Simulation time 1862572342 ps
CPU time 115.32 seconds
Started Jul 29 05:15:15 PM PDT 24
Finished Jul 29 05:17:10 PM PDT 24
Peak memory 219488 kb
Host smart-cfc687e4-13e9-4efb-bde2-5c661d67ae6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123830455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.123830455
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4117870821
Short name T255
Test name
Test status
Simulation time 689295998 ps
CPU time 19.19 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:15:32 PM PDT 24
Peak memory 220044 kb
Host smart-26dc9bf2-7fe9-4ab5-bf54-dd6bbdc51450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117870821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4117870821
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1767264705
Short name T186
Test name
Test status
Simulation time 185057855 ps
CPU time 10.27 seconds
Started Jul 29 05:15:14 PM PDT 24
Finished Jul 29 05:15:24 PM PDT 24
Peak memory 220032 kb
Host smart-48934116-e937-495d-bd0d-06ca1928aa5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767264705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1767264705
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1995573401
Short name T72
Test name
Test status
Simulation time 1287790681 ps
CPU time 34.7 seconds
Started Jul 29 05:15:15 PM PDT 24
Finished Jul 29 05:15:50 PM PDT 24
Peak memory 219876 kb
Host smart-312f2506-b21f-45aa-a126-d94f034d3d35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995573401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1995573401
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1656138957
Short name T223
Test name
Test status
Simulation time 1038617277 ps
CPU time 9.74 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:22 PM PDT 24
Peak memory 219144 kb
Host smart-7fced1b9-ba06-450e-bb07-cc71db90a5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656138957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1656138957
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2971956338
Short name T151
Test name
Test status
Simulation time 5683349658 ps
CPU time 282.96 seconds
Started Jul 29 05:15:15 PM PDT 24
Finished Jul 29 05:19:58 PM PDT 24
Peak memory 219876 kb
Host smart-faa36207-2bd6-4a32-9853-064b18c2b09f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971956338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2971956338
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1949374907
Short name T217
Test name
Test status
Simulation time 1340547196 ps
CPU time 12.04 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:15:25 PM PDT 24
Peak memory 219964 kb
Host smart-981170ee-7756-4295-8e2d-b0032f1d87f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949374907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1949374907
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1808921666
Short name T10
Test name
Test status
Simulation time 2251716132 ps
CPU time 29.73 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:41 PM PDT 24
Peak memory 220104 kb
Host smart-a264cce0-88f9-4c01-82b3-8a44d7391d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808921666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1808921666
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2099579350
Short name T53
Test name
Test status
Simulation time 30811824641 ps
CPU time 630.72 seconds
Started Jul 29 05:15:13 PM PDT 24
Finished Jul 29 05:25:43 PM PDT 24
Peak memory 231860 kb
Host smart-f0851603-8714-45ac-8650-dbf3b38ad19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099579350 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2099579350
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2529845478
Short name T264
Test name
Test status
Simulation time 853512176 ps
CPU time 10.21 seconds
Started Jul 29 05:15:20 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 219136 kb
Host smart-f8e83ce1-6006-4db4-922d-dcc17b34460b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529845478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2529845478
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3611477612
Short name T271
Test name
Test status
Simulation time 4119980855 ps
CPU time 220.89 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 242700 kb
Host smart-105e8d34-8735-4823-9f42-e9c8af4e53c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611477612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3611477612
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2249826764
Short name T152
Test name
Test status
Simulation time 664550468 ps
CPU time 19.51 seconds
Started Jul 29 05:15:11 PM PDT 24
Finished Jul 29 05:15:31 PM PDT 24
Peak memory 220076 kb
Host smart-6552961e-2f31-4550-b277-9d0d4ad3b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249826764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2249826764
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.423404595
Short name T102
Test name
Test status
Simulation time 182794314 ps
CPU time 9.97 seconds
Started Jul 29 05:15:12 PM PDT 24
Finished Jul 29 05:15:22 PM PDT 24
Peak memory 220088 kb
Host smart-8b257820-f9f4-4f7d-94fa-1e5e4deded16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423404595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.423404595
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1505657516
Short name T92
Test name
Test status
Simulation time 1125295694 ps
CPU time 35.27 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:52 PM PDT 24
Peak memory 219964 kb
Host smart-9c1bdec6-e454-4745-9ed8-0f5d95a9f35c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505657516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1505657516
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3798284036
Short name T221
Test name
Test status
Simulation time 988276478 ps
CPU time 10.11 seconds
Started Jul 29 05:15:20 PM PDT 24
Finished Jul 29 05:15:31 PM PDT 24
Peak memory 219064 kb
Host smart-ff42a651-5f00-4419-9409-b10ee34d061d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798284036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3798284036
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3698478071
Short name T166
Test name
Test status
Simulation time 4732577249 ps
CPU time 199.38 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 239640 kb
Host smart-e6ee1727-9208-4d1f-9cb2-d6aa01f4b7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698478071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3698478071
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4097827274
Short name T211
Test name
Test status
Simulation time 2063973270 ps
CPU time 22.39 seconds
Started Jul 29 05:15:24 PM PDT 24
Finished Jul 29 05:15:46 PM PDT 24
Peak memory 219956 kb
Host smart-4162e0a4-d01d-4805-a8bc-9349555b919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097827274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4097827274
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3842061731
Short name T219
Test name
Test status
Simulation time 268075462 ps
CPU time 11.83 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 220032 kb
Host smart-6671ba69-4bc9-468a-8dc8-0c85f0174873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842061731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3842061731
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4264756041
Short name T215
Test name
Test status
Simulation time 1562683471 ps
CPU time 26.45 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:15:45 PM PDT 24
Peak memory 219924 kb
Host smart-d9eb564b-88ad-40f5-84c4-829314ba879f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264756041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4264756041
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1637432135
Short name T249
Test name
Test status
Simulation time 989696667 ps
CPU time 9.83 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 218976 kb
Host smart-367558d4-5c47-4895-a920-af07a7fb9cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637432135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1637432135
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3126318842
Short name T147
Test name
Test status
Simulation time 19330551156 ps
CPU time 254.8 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:18:52 PM PDT 24
Peak memory 234088 kb
Host smart-15103fb6-6b83-4382-8f31-d9f68be0f008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126318842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3126318842
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.116890006
Short name T251
Test name
Test status
Simulation time 507593011 ps
CPU time 22.23 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:15:08 PM PDT 24
Peak memory 220080 kb
Host smart-14a1fb9b-c9b6-4468-b304-67877f82e7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116890006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.116890006
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1663448599
Short name T124
Test name
Test status
Simulation time 364969792 ps
CPU time 12.38 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:14:57 PM PDT 24
Peak memory 219936 kb
Host smart-1d2e929d-78eb-410d-a3d8-d1e38b3ae519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663448599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1663448599
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.747810883
Short name T23
Test name
Test status
Simulation time 685024307 ps
CPU time 118.8 seconds
Started Jul 29 05:14:39 PM PDT 24
Finished Jul 29 05:16:38 PM PDT 24
Peak memory 236060 kb
Host smart-719a4525-df94-47fe-916a-d4941b76e496
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747810883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.747810883
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3449150968
Short name T240
Test name
Test status
Simulation time 2129089365 ps
CPU time 11.41 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:14:55 PM PDT 24
Peak memory 219940 kb
Host smart-08f3b7ab-9706-4e75-bd9c-c923e068c4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449150968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3449150968
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2539952312
Short name T155
Test name
Test status
Simulation time 356750820 ps
CPU time 19.92 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:15:08 PM PDT 24
Peak memory 219948 kb
Host smart-e4136f29-0e24-4046-a15e-cc50844c2b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539952312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2539952312
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3450786715
Short name T46
Test name
Test status
Simulation time 245480118169 ps
CPU time 2464.27 seconds
Started Jul 29 05:14:40 PM PDT 24
Finished Jul 29 05:55:44 PM PDT 24
Peak memory 252972 kb
Host smart-59b61ff3-0d48-4e0c-ae69-a6ea3ce1f5eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450786715 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3450786715
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3838250149
Short name T297
Test name
Test status
Simulation time 1182289059 ps
CPU time 8.29 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:28 PM PDT 24
Peak memory 218684 kb
Host smart-cefeab0c-cbab-4239-a2a3-84ae0947944f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838250149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3838250149
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.85617545
Short name T244
Test name
Test status
Simulation time 3385727681 ps
CPU time 199.82 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 240648 kb
Host smart-29a4abeb-0637-4548-90ae-1e0a82d02943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85617545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.85617545
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3782829284
Short name T289
Test name
Test status
Simulation time 497199493 ps
CPU time 22.96 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:15:41 PM PDT 24
Peak memory 220024 kb
Host smart-f2ea7201-5059-4574-934a-6534743f7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782829284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3782829284
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1835001974
Short name T306
Test name
Test status
Simulation time 1060115825 ps
CPU time 12.27 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:32 PM PDT 24
Peak memory 219964 kb
Host smart-7dc324b1-12fd-46a7-903f-93de3236fb6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835001974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1835001974
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.364932611
Short name T277
Test name
Test status
Simulation time 3152942348 ps
CPU time 23.9 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:43 PM PDT 24
Peak memory 220044 kb
Host smart-d531ac60-c001-436a-baac-f5efdff76f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364932611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.364932611
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1186950835
Short name T257
Test name
Test status
Simulation time 1841644280 ps
CPU time 8.52 seconds
Started Jul 29 05:15:20 PM PDT 24
Finished Jul 29 05:15:29 PM PDT 24
Peak memory 219016 kb
Host smart-70b39fc3-9692-4fd2-9240-c93f3137ec8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186950835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1186950835
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2954016610
Short name T32
Test name
Test status
Simulation time 21851716957 ps
CPU time 337.55 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:20:57 PM PDT 24
Peak memory 237432 kb
Host smart-ad4922a5-883b-4f08-b2be-1c7891398469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954016610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2954016610
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3160464489
Short name T26
Test name
Test status
Simulation time 994429100 ps
CPU time 23.05 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:40 PM PDT 24
Peak memory 220280 kb
Host smart-8f75102f-a284-4d17-9d29-904c340a8b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160464489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3160464489
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.16901248
Short name T63
Test name
Test status
Simulation time 180420930 ps
CPU time 10.94 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 219920 kb
Host smart-c1d11b15-dfd2-4bd4-8746-d4fee6bfecba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16901248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.16901248
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3967748110
Short name T206
Test name
Test status
Simulation time 522308809 ps
CPU time 33.12 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:15:51 PM PDT 24
Peak memory 219992 kb
Host smart-66c41405-abfa-4509-894b-e831a01b82a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967748110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3967748110
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3446019709
Short name T167
Test name
Test status
Simulation time 171697341 ps
CPU time 8.43 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 219000 kb
Host smart-33a07757-4be0-40c5-94ff-54b98bfc307a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446019709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3446019709
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2910007356
Short name T209
Test name
Test status
Simulation time 3799689283 ps
CPU time 245.89 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:19:24 PM PDT 24
Peak memory 220312 kb
Host smart-0f396845-e37b-4b2a-b345-93a11ec025b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910007356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2910007356
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1356395276
Short name T274
Test name
Test status
Simulation time 387115519 ps
CPU time 18.65 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:36 PM PDT 24
Peak memory 220020 kb
Host smart-9278014b-9bdb-49f1-b133-30e97581bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356395276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1356395276
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.628549525
Short name T103
Test name
Test status
Simulation time 1040582458 ps
CPU time 12.27 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:31 PM PDT 24
Peak memory 220048 kb
Host smart-906cdf88-ac46-42b5-bca2-a9590e1d73f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628549525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.628549525
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3499830216
Short name T141
Test name
Test status
Simulation time 1724205580 ps
CPU time 30.84 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:50 PM PDT 24
Peak memory 219980 kb
Host smart-74110c80-dffa-4f39-bbc6-9f3e382d8918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499830216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3499830216
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3548377323
Short name T40
Test name
Test status
Simulation time 386775306 ps
CPU time 8.48 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 219148 kb
Host smart-ef176fd7-1300-4022-81aa-8548fd56e0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548377323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3548377323
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1993169516
Short name T222
Test name
Test status
Simulation time 10497276442 ps
CPU time 192.07 seconds
Started Jul 29 05:15:20 PM PDT 24
Finished Jul 29 05:18:32 PM PDT 24
Peak memory 239704 kb
Host smart-9e9cf4bc-4ff5-47bc-9a4d-d948af6c2017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993169516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1993169516
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4128117473
Short name T207
Test name
Test status
Simulation time 612152023 ps
CPU time 22.28 seconds
Started Jul 29 05:15:16 PM PDT 24
Finished Jul 29 05:15:38 PM PDT 24
Peak memory 220076 kb
Host smart-aa8bc4f2-756d-4aa6-aee6-b9732e2763e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128117473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4128117473
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2612808882
Short name T208
Test name
Test status
Simulation time 362421703 ps
CPU time 10.59 seconds
Started Jul 29 05:15:19 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 220060 kb
Host smart-7d033734-1e2a-432f-a4b2-d3eb666feee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612808882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2612808882
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.891495140
Short name T272
Test name
Test status
Simulation time 3823771696 ps
CPU time 12.54 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 220116 kb
Host smart-f75f31b8-f74e-4335-b9dc-804802aa7de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891495140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.891495140
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2906153164
Short name T309
Test name
Test status
Simulation time 1026749529 ps
CPU time 14.97 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:38 PM PDT 24
Peak memory 219060 kb
Host smart-16b32dfa-2b89-48cd-b09d-6c6201d863f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906153164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2906153164
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3988097158
Short name T242
Test name
Test status
Simulation time 18669056975 ps
CPU time 391.21 seconds
Started Jul 29 05:15:18 PM PDT 24
Finished Jul 29 05:21:50 PM PDT 24
Peak memory 219940 kb
Host smart-16c66c13-d5bc-494f-a11a-53df7592625d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988097158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3988097158
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3010073438
Short name T210
Test name
Test status
Simulation time 2063574427 ps
CPU time 22.56 seconds
Started Jul 29 05:15:20 PM PDT 24
Finished Jul 29 05:15:42 PM PDT 24
Peak memory 219968 kb
Host smart-e6389c1a-861f-401e-9fd2-85d5a56b464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010073438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3010073438
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.583600890
Short name T189
Test name
Test status
Simulation time 527306244 ps
CPU time 12.86 seconds
Started Jul 29 05:15:17 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 219968 kb
Host smart-6b522fdf-f6e3-46a7-b77c-bd7cce7eda1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583600890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.583600890
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.754457017
Short name T88
Test name
Test status
Simulation time 795300257 ps
CPU time 25.34 seconds
Started Jul 29 05:15:21 PM PDT 24
Finished Jul 29 05:15:46 PM PDT 24
Peak memory 219960 kb
Host smart-5b0de1c6-2dc3-4754-9289-52db98ca042b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754457017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.754457017
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3256595089
Short name T11
Test name
Test status
Simulation time 195216799959 ps
CPU time 1854.29 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:46:18 PM PDT 24
Peak memory 240084 kb
Host smart-e97a06d7-0beb-4b28-8633-dffb390b89cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256595089 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3256595089
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2853706810
Short name T185
Test name
Test status
Simulation time 1765182746 ps
CPU time 10.02 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:33 PM PDT 24
Peak memory 219076 kb
Host smart-6f16f0df-384c-4414-9cb0-97af7a813977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853706810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2853706810
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1513451051
Short name T201
Test name
Test status
Simulation time 2938568823 ps
CPU time 208.26 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 239708 kb
Host smart-cf118efc-df3c-4482-ba76-8a115eb3464f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513451051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1513451051
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3637594242
Short name T267
Test name
Test status
Simulation time 15099604446 ps
CPU time 32.57 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:56 PM PDT 24
Peak memory 220064 kb
Host smart-dfa04185-b295-4bce-97f5-a4bd2965c044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637594242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3637594242
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1830208997
Short name T138
Test name
Test status
Simulation time 523326400 ps
CPU time 11.94 seconds
Started Jul 29 05:15:24 PM PDT 24
Finished Jul 29 05:15:36 PM PDT 24
Peak memory 220052 kb
Host smart-1e1d762e-5e5f-4f23-8820-08c12be07234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830208997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1830208997
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2193120369
Short name T197
Test name
Test status
Simulation time 2000168066 ps
CPU time 34.57 seconds
Started Jul 29 05:15:24 PM PDT 24
Finished Jul 29 05:15:58 PM PDT 24
Peak memory 220092 kb
Host smart-ebc8ebe2-1e6d-4bd7-8628-00ad595d4b66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193120369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2193120369
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2923439852
Short name T125
Test name
Test status
Simulation time 691737070 ps
CPU time 8.41 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:32 PM PDT 24
Peak memory 218984 kb
Host smart-0d1ebd56-a2fa-4c90-baf8-3443fdd1eead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923439852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2923439852
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.409426513
Short name T236
Test name
Test status
Simulation time 21963220355 ps
CPU time 270.14 seconds
Started Jul 29 05:15:22 PM PDT 24
Finished Jul 29 05:19:53 PM PDT 24
Peak memory 239704 kb
Host smart-8a77fb76-6688-42a2-94e4-3e0017c84f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409426513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.409426513
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4254909648
Short name T121
Test name
Test status
Simulation time 738494943 ps
CPU time 21.63 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:44 PM PDT 24
Peak memory 220028 kb
Host smart-e37af03f-74c2-4e63-bcd3-351fdd6c7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254909648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4254909648
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2725303986
Short name T173
Test name
Test status
Simulation time 1058889956 ps
CPU time 11.85 seconds
Started Jul 29 05:15:22 PM PDT 24
Finished Jul 29 05:15:34 PM PDT 24
Peak memory 219940 kb
Host smart-6b55ff04-77b4-4b5c-92eb-3ad7be1ffca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725303986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2725303986
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3122642520
Short name T193
Test name
Test status
Simulation time 10237207996 ps
CPU time 34.25 seconds
Started Jul 29 05:15:22 PM PDT 24
Finished Jul 29 05:15:56 PM PDT 24
Peak memory 220040 kb
Host smart-f490e34b-f63f-41ad-9ed6-48235e4b3497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122642520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3122642520
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2402826915
Short name T2
Test name
Test status
Simulation time 4122191830 ps
CPU time 10.14 seconds
Started Jul 29 05:15:21 PM PDT 24
Finished Jul 29 05:15:31 PM PDT 24
Peak memory 219128 kb
Host smart-67375465-d79e-4f66-93de-5b35fe2b1ddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402826915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2402826915
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2779265345
Short name T259
Test name
Test status
Simulation time 13127354182 ps
CPU time 241.38 seconds
Started Jul 29 05:15:22 PM PDT 24
Finished Jul 29 05:19:24 PM PDT 24
Peak memory 239568 kb
Host smart-320f8b0d-a9d5-4ab1-84b3-3874d9ae5fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779265345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2779265345
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3380894302
Short name T302
Test name
Test status
Simulation time 1376366140 ps
CPU time 18.98 seconds
Started Jul 29 05:15:22 PM PDT 24
Finished Jul 29 05:15:41 PM PDT 24
Peak memory 220072 kb
Host smart-2d82ffe9-c901-4795-8bb1-98d48686871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380894302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3380894302
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1488194151
Short name T99
Test name
Test status
Simulation time 278459880 ps
CPU time 11.8 seconds
Started Jul 29 05:15:23 PM PDT 24
Finished Jul 29 05:15:35 PM PDT 24
Peak memory 220072 kb
Host smart-575bb3ee-8ba8-4e9d-b37c-fbd9d3aec695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488194151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1488194151
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2731119160
Short name T73
Test name
Test status
Simulation time 538779348 ps
CPU time 27.21 seconds
Started Jul 29 05:15:25 PM PDT 24
Finished Jul 29 05:15:52 PM PDT 24
Peak memory 219884 kb
Host smart-539a36ff-3e27-42c8-b290-7aa61b39d404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731119160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2731119160
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3034660210
Short name T275
Test name
Test status
Simulation time 869166024 ps
CPU time 8.21 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:15:37 PM PDT 24
Peak memory 219240 kb
Host smart-543403e3-88a3-48e0-9c4c-a1f35bb46252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034660210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3034660210
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2975418870
Short name T234
Test name
Test status
Simulation time 954878991 ps
CPU time 22.53 seconds
Started Jul 29 05:15:33 PM PDT 24
Finished Jul 29 05:15:55 PM PDT 24
Peak memory 219980 kb
Host smart-4e231692-f27c-4981-b6f3-b567da111788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975418870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2975418870
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.422720318
Short name T31
Test name
Test status
Simulation time 1068874674 ps
CPU time 12.15 seconds
Started Jul 29 05:15:24 PM PDT 24
Finished Jul 29 05:15:37 PM PDT 24
Peak memory 219984 kb
Host smart-81c92035-40d2-4d57-8c7c-ca62b1570323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422720318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.422720318
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1625077607
Short name T245
Test name
Test status
Simulation time 281816272 ps
CPU time 19.77 seconds
Started Jul 29 05:15:26 PM PDT 24
Finished Jul 29 05:15:46 PM PDT 24
Peak memory 219952 kb
Host smart-4f0c2ed4-49be-41ba-b849-c2d449887918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625077607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1625077607
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2944216863
Short name T308
Test name
Test status
Simulation time 259702424 ps
CPU time 10.03 seconds
Started Jul 29 05:20:57 PM PDT 24
Finished Jul 29 05:21:08 PM PDT 24
Peak memory 219116 kb
Host smart-52354f71-3577-4e65-8937-1a7483a3c416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944216863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2944216863
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2362782745
Short name T248
Test name
Test status
Simulation time 6982458524 ps
CPU time 121.05 seconds
Started Jul 29 05:15:30 PM PDT 24
Finished Jul 29 05:17:31 PM PDT 24
Peak memory 238228 kb
Host smart-83ff7aeb-4bf5-4f75-aab9-ae7a8197dcb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362782745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2362782745
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1589422927
Short name T261
Test name
Test status
Simulation time 650207481 ps
CPU time 19.29 seconds
Started Jul 29 05:15:31 PM PDT 24
Finished Jul 29 05:15:50 PM PDT 24
Peak memory 220232 kb
Host smart-b39c567e-14ba-462d-a650-e41929b29b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589422927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1589422927
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4042940201
Short name T283
Test name
Test status
Simulation time 514920359 ps
CPU time 11.76 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:15:41 PM PDT 24
Peak memory 220072 kb
Host smart-af8857a6-991b-422d-abe2-4f2950637c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042940201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4042940201
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4223013714
Short name T233
Test name
Test status
Simulation time 506642151 ps
CPU time 14.53 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:15:43 PM PDT 24
Peak memory 219908 kb
Host smart-e388163b-1b35-4519-9a96-70828d51b5e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223013714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4223013714
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3475762905
Short name T303
Test name
Test status
Simulation time 172976241 ps
CPU time 8.33 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:14:46 PM PDT 24
Peak memory 218620 kb
Host smart-9c80f4e7-0e18-4017-9300-bc9335ecb464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475762905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3475762905
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1609251901
Short name T192
Test name
Test status
Simulation time 4717202681 ps
CPU time 240.73 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 220312 kb
Host smart-795d5a5c-4165-41b6-873d-b1ebfd34a477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609251901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1609251901
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3473798115
Short name T159
Test name
Test status
Simulation time 510964753 ps
CPU time 22.73 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:15:00 PM PDT 24
Peak memory 220064 kb
Host smart-37631c45-1699-4788-a574-2b229ea4412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473798115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3473798115
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2384125741
Short name T296
Test name
Test status
Simulation time 368085498 ps
CPU time 10.35 seconds
Started Jul 29 05:14:49 PM PDT 24
Finished Jul 29 05:14:59 PM PDT 24
Peak memory 220048 kb
Host smart-d5b97707-60d4-4ee2-8072-9bbc413b15ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384125741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2384125741
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1577070132
Short name T169
Test name
Test status
Simulation time 728433522 ps
CPU time 10.39 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:14:52 PM PDT 24
Peak memory 220044 kb
Host smart-f325d50f-b618-4e0c-b64d-dc4596d8649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577070132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1577070132
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4110113065
Short name T165
Test name
Test status
Simulation time 1486925286 ps
CPU time 12.36 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 219996 kb
Host smart-2c094755-dd32-4092-a09f-48ec4fbb6952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110113065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4110113065
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3549095079
Short name T203
Test name
Test status
Simulation time 264678628 ps
CPU time 8.5 seconds
Started Jul 29 05:15:28 PM PDT 24
Finished Jul 29 05:15:37 PM PDT 24
Peak memory 219008 kb
Host smart-a155ba40-d854-422a-afa5-deeed24e62ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549095079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3549095079
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2072099246
Short name T140
Test name
Test status
Simulation time 3223687160 ps
CPU time 180.72 seconds
Started Jul 29 05:15:30 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 243896 kb
Host smart-3d5a9905-575c-4035-b6b7-e9eb7cabbf27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072099246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2072099246
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1297468228
Short name T128
Test name
Test status
Simulation time 6144534672 ps
CPU time 32.16 seconds
Started Jul 29 05:21:01 PM PDT 24
Finished Jul 29 05:21:33 PM PDT 24
Peak memory 219576 kb
Host smart-ecbbcc86-d946-4f51-9223-fa3bb0e9d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297468228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1297468228
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4170085098
Short name T100
Test name
Test status
Simulation time 522242539 ps
CPU time 11.46 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:15:40 PM PDT 24
Peak memory 219952 kb
Host smart-b3122cac-896f-40c5-a621-3ac33f0cbdab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170085098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4170085098
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3396630702
Short name T157
Test name
Test status
Simulation time 3912319058 ps
CPU time 40.27 seconds
Started Jul 29 05:15:32 PM PDT 24
Finished Jul 29 05:16:12 PM PDT 24
Peak memory 220048 kb
Host smart-546436c1-d5ff-4c4c-9e82-442d9fcf0ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396630702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3396630702
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3484587923
Short name T205
Test name
Test status
Simulation time 519038417 ps
CPU time 9.92 seconds
Started Jul 29 05:15:33 PM PDT 24
Finished Jul 29 05:15:43 PM PDT 24
Peak memory 219056 kb
Host smart-475304cd-9760-4a06-aabb-f55cbe056e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484587923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3484587923
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1462136384
Short name T36
Test name
Test status
Simulation time 3074350538 ps
CPU time 207.74 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 238568 kb
Host smart-af599a39-8d15-4be5-a493-6df2fb93231c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462136384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1462136384
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3441917633
Short name T282
Test name
Test status
Simulation time 1378413619 ps
CPU time 23.21 seconds
Started Jul 29 05:15:30 PM PDT 24
Finished Jul 29 05:15:54 PM PDT 24
Peak memory 220060 kb
Host smart-a86a6855-09cc-4713-9c77-40e0a0cc3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441917633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3441917633
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.268163409
Short name T235
Test name
Test status
Simulation time 1075777810 ps
CPU time 11.8 seconds
Started Jul 29 05:15:29 PM PDT 24
Finished Jul 29 05:15:41 PM PDT 24
Peak memory 219956 kb
Host smart-99491afd-9556-4e29-9531-6af7590022da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268163409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.268163409
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2018037781
Short name T75
Test name
Test status
Simulation time 542528433 ps
CPU time 24.04 seconds
Started Jul 29 05:15:31 PM PDT 24
Finished Jul 29 05:15:55 PM PDT 24
Peak memory 219960 kb
Host smart-a135818d-55d6-4feb-bc92-d265be02505c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018037781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2018037781
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1942696205
Short name T61
Test name
Test status
Simulation time 174635896 ps
CPU time 8.02 seconds
Started Jul 29 05:15:36 PM PDT 24
Finished Jul 29 05:15:44 PM PDT 24
Peak memory 219184 kb
Host smart-5210a775-041d-4128-b735-63d2346a7ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942696205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1942696205
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1818268281
Short name T253
Test name
Test status
Simulation time 51055507529 ps
CPU time 418.74 seconds
Started Jul 29 05:15:36 PM PDT 24
Finished Jul 29 05:22:35 PM PDT 24
Peak memory 237108 kb
Host smart-b56a5a38-70ee-40c6-ac44-291adc13311a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818268281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1818268281
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2110020422
Short name T287
Test name
Test status
Simulation time 502612229 ps
CPU time 22.5 seconds
Started Jul 29 05:15:40 PM PDT 24
Finished Jul 29 05:16:02 PM PDT 24
Peak memory 220096 kb
Host smart-09438d94-9e26-40b8-90fd-f481f0baedff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110020422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2110020422
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3730855092
Short name T104
Test name
Test status
Simulation time 183953254 ps
CPU time 10.37 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:48 PM PDT 24
Peak memory 219984 kb
Host smart-874dfb59-0cb3-4152-8e22-c3c350b4a78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730855092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3730855092
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3427526613
Short name T131
Test name
Test status
Simulation time 537449652 ps
CPU time 22.82 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:16:02 PM PDT 24
Peak memory 219904 kb
Host smart-b4354c35-0dbd-446d-80a1-a3c3f71a73a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427526613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3427526613
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.62720566
Short name T130
Test name
Test status
Simulation time 249978009 ps
CPU time 10.11 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:48 PM PDT 24
Peak memory 219196 kb
Host smart-b54c3761-136c-4022-bfc6-c0ed3cfa37f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62720566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.62720566
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2182649215
Short name T243
Test name
Test status
Simulation time 10183491539 ps
CPU time 154.21 seconds
Started Jul 29 05:15:35 PM PDT 24
Finished Jul 29 05:18:10 PM PDT 24
Peak memory 228540 kb
Host smart-d30f05e7-c1b9-4327-a327-ede34640a791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182649215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2182649215
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.343324753
Short name T268
Test name
Test status
Simulation time 978104411 ps
CPU time 22.26 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:16:01 PM PDT 24
Peak memory 219988 kb
Host smart-60901993-b476-4633-830f-9243ae12841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343324753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.343324753
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2654781023
Short name T241
Test name
Test status
Simulation time 268249121 ps
CPU time 11.83 seconds
Started Jul 29 05:15:35 PM PDT 24
Finished Jul 29 05:15:47 PM PDT 24
Peak memory 220012 kb
Host smart-d2c509fc-472d-4711-914e-ea170960f3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654781023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2654781023
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1790490502
Short name T293
Test name
Test status
Simulation time 559167450 ps
CPU time 38.19 seconds
Started Jul 29 05:15:35 PM PDT 24
Finished Jul 29 05:16:14 PM PDT 24
Peak memory 220008 kb
Host smart-5e9eedf7-3d85-4232-8735-c9c6a0e6e6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790490502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1790490502
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4028307459
Short name T154
Test name
Test status
Simulation time 251285843 ps
CPU time 10.3 seconds
Started Jul 29 05:21:04 PM PDT 24
Finished Jul 29 05:21:15 PM PDT 24
Peak memory 219080 kb
Host smart-d2eddc36-bf51-44c8-bdb9-43342fed64da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028307459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4028307459
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3920088300
Short name T39
Test name
Test status
Simulation time 10207377686 ps
CPU time 168.49 seconds
Started Jul 29 05:15:35 PM PDT 24
Finished Jul 29 05:18:23 PM PDT 24
Peak memory 239664 kb
Host smart-acab72df-35a2-4612-937e-9f47d6ab3ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920088300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3920088300
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.173307894
Short name T45
Test name
Test status
Simulation time 346353685 ps
CPU time 18.93 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:57 PM PDT 24
Peak memory 219960 kb
Host smart-1fafe485-bfb8-4ff8-9c29-8d6d3123693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173307894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.173307894
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.17054836
Short name T162
Test name
Test status
Simulation time 185351484 ps
CPU time 10.48 seconds
Started Jul 29 05:15:37 PM PDT 24
Finished Jul 29 05:15:48 PM PDT 24
Peak memory 219944 kb
Host smart-80915fdf-3705-40bb-b0b6-af914b984ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17054836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.17054836
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1155170345
Short name T7
Test name
Test status
Simulation time 823201505 ps
CPU time 39.25 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:16:17 PM PDT 24
Peak memory 219952 kb
Host smart-83311fe9-da31-4314-819f-f87c4572a198
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155170345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1155170345
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.232203456
Short name T177
Test name
Test status
Simulation time 260548092 ps
CPU time 10.05 seconds
Started Jul 29 05:15:36 PM PDT 24
Finished Jul 29 05:15:46 PM PDT 24
Peak memory 219020 kb
Host smart-3e3a27c7-ddfe-43e9-b634-bc2fcb57dacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232203456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.232203456
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3900142962
Short name T144
Test name
Test status
Simulation time 3077716668 ps
CPU time 191.69 seconds
Started Jul 29 05:15:37 PM PDT 24
Finished Jul 29 05:18:49 PM PDT 24
Peak memory 238572 kb
Host smart-d3aa4925-908a-4357-ae39-8c241a94ea18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900142962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3900142962
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2479731652
Short name T29
Test name
Test status
Simulation time 689285465 ps
CPU time 18.97 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:57 PM PDT 24
Peak memory 220076 kb
Host smart-942083f0-1b3e-4695-a474-bfcd3dbc5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479731652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2479731652
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4194350426
Short name T170
Test name
Test status
Simulation time 184770268 ps
CPU time 10.28 seconds
Started Jul 29 05:15:36 PM PDT 24
Finished Jul 29 05:15:47 PM PDT 24
Peak memory 220132 kb
Host smart-bc19a15c-ac88-4cd1-a472-a5bc86a75e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194350426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4194350426
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1131957429
Short name T200
Test name
Test status
Simulation time 1675925372 ps
CPU time 35.51 seconds
Started Jul 29 05:15:36 PM PDT 24
Finished Jul 29 05:16:12 PM PDT 24
Peak memory 219968 kb
Host smart-af151762-cac0-4513-b899-a9803f6d1c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131957429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1131957429
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.776175375
Short name T30
Test name
Test status
Simulation time 2754550787 ps
CPU time 10.43 seconds
Started Jul 29 05:15:44 PM PDT 24
Finished Jul 29 05:15:54 PM PDT 24
Peak memory 219172 kb
Host smart-c030cc9e-c253-433b-b644-a537a605e030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776175375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.776175375
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3563006201
Short name T38
Test name
Test status
Simulation time 20787406936 ps
CPU time 271.89 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:20:11 PM PDT 24
Peak memory 226288 kb
Host smart-b20c1f6f-8dfd-42c4-9096-829031e543ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563006201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3563006201
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3411160198
Short name T174
Test name
Test status
Simulation time 467868910 ps
CPU time 18.91 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:15:58 PM PDT 24
Peak memory 220028 kb
Host smart-5d874d8e-bee8-4c49-b81b-c8bed71d129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411160198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3411160198
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4077830914
Short name T101
Test name
Test status
Simulation time 267937474 ps
CPU time 11.87 seconds
Started Jul 29 05:15:35 PM PDT 24
Finished Jul 29 05:15:47 PM PDT 24
Peak memory 219988 kb
Host smart-afdfab14-b53c-4a24-ae6b-ad939619eddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077830914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4077830914
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3206790615
Short name T77
Test name
Test status
Simulation time 193035656 ps
CPU time 11.11 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:49 PM PDT 24
Peak memory 219944 kb
Host smart-dc7881d7-8e48-471d-8dca-85d1381242f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206790615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3206790615
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.861589173
Short name T62
Test name
Test status
Simulation time 167968630 ps
CPU time 8.5 seconds
Started Jul 29 05:15:41 PM PDT 24
Finished Jul 29 05:15:50 PM PDT 24
Peak memory 219048 kb
Host smart-9d559d4a-0cdd-4823-8044-aa3d4c31ce34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861589173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.861589173
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2497438650
Short name T122
Test name
Test status
Simulation time 5502813702 ps
CPU time 22.29 seconds
Started Jul 29 05:15:40 PM PDT 24
Finished Jul 29 05:16:02 PM PDT 24
Peak memory 220124 kb
Host smart-c8f578dd-df15-4323-9b34-4ed5f7499b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497438650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2497438650
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1733592083
Short name T153
Test name
Test status
Simulation time 830783413 ps
CPU time 12.2 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:15:51 PM PDT 24
Peak memory 220068 kb
Host smart-70278f29-1f51-49f0-8291-3bd79cbace74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733592083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1733592083
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.819461630
Short name T161
Test name
Test status
Simulation time 227865148 ps
CPU time 18.8 seconds
Started Jul 29 05:15:41 PM PDT 24
Finished Jul 29 05:16:00 PM PDT 24
Peak memory 219976 kb
Host smart-5800178b-7fce-41c5-9664-adbf0cd24ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819461630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.819461630
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2279666218
Short name T180
Test name
Test status
Simulation time 1774074167 ps
CPU time 9.92 seconds
Started Jul 29 05:15:46 PM PDT 24
Finished Jul 29 05:15:56 PM PDT 24
Peak memory 219060 kb
Host smart-1be6a73e-291c-407b-be53-c7997d775b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279666218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2279666218
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4036468126
Short name T37
Test name
Test status
Simulation time 32471893478 ps
CPU time 200.01 seconds
Started Jul 29 05:15:41 PM PDT 24
Finished Jul 29 05:19:01 PM PDT 24
Peak memory 220276 kb
Host smart-251dc072-0b61-402f-b115-96a3ca1c54f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036468126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4036468126
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3862187572
Short name T42
Test name
Test status
Simulation time 1376401793 ps
CPU time 19.35 seconds
Started Jul 29 05:15:38 PM PDT 24
Finished Jul 29 05:15:58 PM PDT 24
Peak memory 219988 kb
Host smart-5ccdc006-0fe5-4912-b114-2a380bf407eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862187572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3862187572
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.748597788
Short name T4
Test name
Test status
Simulation time 2854735614 ps
CPU time 11.6 seconds
Started Jul 29 05:15:41 PM PDT 24
Finished Jul 29 05:15:53 PM PDT 24
Peak memory 220084 kb
Host smart-ce91973f-2e99-4964-b9fa-2a5cfcc0b25d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748597788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.748597788
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1276279560
Short name T181
Test name
Test status
Simulation time 1558323627 ps
CPU time 27.22 seconds
Started Jul 29 05:15:39 PM PDT 24
Finished Jul 29 05:16:07 PM PDT 24
Peak memory 220004 kb
Host smart-c5081844-7d89-4f11-81cd-d215f43e53f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276279560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1276279560
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2514785631
Short name T123
Test name
Test status
Simulation time 1101762432 ps
CPU time 8.17 seconds
Started Jul 29 05:15:47 PM PDT 24
Finished Jul 29 05:15:56 PM PDT 24
Peak memory 218980 kb
Host smart-e829668c-d7f3-47ec-a595-e6c7c85380d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514785631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2514785631
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.272155953
Short name T172
Test name
Test status
Simulation time 22212629744 ps
CPU time 214.74 seconds
Started Jul 29 05:15:47 PM PDT 24
Finished Jul 29 05:19:22 PM PDT 24
Peak memory 235496 kb
Host smart-eaafb718-f63a-47ca-8aa7-5e1cba8c448e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272155953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.272155953
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3195654278
Short name T258
Test name
Test status
Simulation time 2545033270 ps
CPU time 19.49 seconds
Started Jul 29 05:15:48 PM PDT 24
Finished Jul 29 05:16:07 PM PDT 24
Peak memory 220084 kb
Host smart-576539c1-1343-4f01-a01f-079db99abe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195654278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3195654278
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4224219105
Short name T213
Test name
Test status
Simulation time 677304330 ps
CPU time 12.45 seconds
Started Jul 29 05:15:46 PM PDT 24
Finished Jul 29 05:15:58 PM PDT 24
Peak memory 220044 kb
Host smart-2f5733f3-b101-454e-bc65-197669d37689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224219105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4224219105
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1858701931
Short name T164
Test name
Test status
Simulation time 916234585 ps
CPU time 11 seconds
Started Jul 29 05:15:49 PM PDT 24
Finished Jul 29 05:16:00 PM PDT 24
Peak memory 219924 kb
Host smart-483c2fe9-494e-4037-8871-b68f75f9a644
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858701931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1858701931
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.173303624
Short name T226
Test name
Test status
Simulation time 260105205 ps
CPU time 10.1 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:14:47 PM PDT 24
Peak memory 219056 kb
Host smart-d027c5f0-d343-46fa-bc8e-8a62748dd6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173303624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.173303624
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3093539849
Short name T18
Test name
Test status
Simulation time 5586156454 ps
CPU time 178.57 seconds
Started Jul 29 05:14:41 PM PDT 24
Finished Jul 29 05:17:40 PM PDT 24
Peak memory 243616 kb
Host smart-583501b1-a2da-4ee5-aa96-a5b95fa15787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093539849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3093539849
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1996242703
Short name T179
Test name
Test status
Simulation time 1972091921 ps
CPU time 22.65 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:15:05 PM PDT 24
Peak memory 219964 kb
Host smart-7a51537f-9f96-4b19-b024-05a6cf27df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996242703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1996242703
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3834085706
Short name T133
Test name
Test status
Simulation time 273410662 ps
CPU time 12.28 seconds
Started Jul 29 05:14:45 PM PDT 24
Finished Jul 29 05:14:57 PM PDT 24
Peak memory 219940 kb
Host smart-bb1eb46b-0f65-4ccc-bbfa-20de217f1263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834085706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3834085706
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.171983508
Short name T20
Test name
Test status
Simulation time 624119690 ps
CPU time 225.21 seconds
Started Jul 29 05:14:38 PM PDT 24
Finished Jul 29 05:18:23 PM PDT 24
Peak memory 239836 kb
Host smart-0d5ea8b0-0325-4f0c-a64b-f6b7e8628081
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171983508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.171983508
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3167713821
Short name T190
Test name
Test status
Simulation time 702699157 ps
CPU time 10.3 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:14:54 PM PDT 24
Peak memory 220032 kb
Host smart-9c04a1f1-7953-4689-bc4f-bca9ab213d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167713821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3167713821
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1959735734
Short name T106
Test name
Test status
Simulation time 810370338 ps
CPU time 38.92 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:15:22 PM PDT 24
Peak memory 220080 kb
Host smart-3d488e88-d08a-458c-8315-febb1d3f344a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959735734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1959735734
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.251495086
Short name T199
Test name
Test status
Simulation time 168780364 ps
CPU time 8.58 seconds
Started Jul 29 05:15:47 PM PDT 24
Finished Jul 29 05:15:56 PM PDT 24
Peak memory 219016 kb
Host smart-71f9bf6d-4cb9-45eb-8a6f-04f8f2822dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251495086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.251495086
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3516396920
Short name T143
Test name
Test status
Simulation time 7956997824 ps
CPU time 211.86 seconds
Started Jul 29 05:15:48 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 234468 kb
Host smart-dc4b19d8-f905-4a49-b5c6-82538f26526b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516396920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3516396920
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2905225665
Short name T232
Test name
Test status
Simulation time 512270835 ps
CPU time 22.28 seconds
Started Jul 29 05:15:48 PM PDT 24
Finished Jul 29 05:16:11 PM PDT 24
Peak memory 220060 kb
Host smart-e66bbd53-c8ae-4526-a28d-10a8fa7dac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905225665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2905225665
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3297458940
Short name T273
Test name
Test status
Simulation time 371461974 ps
CPU time 10.47 seconds
Started Jul 29 05:15:48 PM PDT 24
Finished Jul 29 05:15:59 PM PDT 24
Peak memory 220012 kb
Host smart-9b09f73e-a068-4cff-95ad-2ad301b1d4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297458940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3297458940
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.888032455
Short name T305
Test name
Test status
Simulation time 2073117719 ps
CPU time 27.19 seconds
Started Jul 29 05:15:47 PM PDT 24
Finished Jul 29 05:16:15 PM PDT 24
Peak memory 219940 kb
Host smart-ede2be68-9e72-4b30-93d5-c5e120259bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888032455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.888032455
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3263701517
Short name T91
Test name
Test status
Simulation time 1180672744 ps
CPU time 10 seconds
Started Jul 29 05:15:55 PM PDT 24
Finished Jul 29 05:16:05 PM PDT 24
Peak memory 219236 kb
Host smart-1168b3f3-975c-4f9d-a0f7-26d35b4ac48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263701517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3263701517
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3838294002
Short name T120
Test name
Test status
Simulation time 26715012458 ps
CPU time 347.45 seconds
Started Jul 29 05:15:54 PM PDT 24
Finished Jul 29 05:21:42 PM PDT 24
Peak memory 219684 kb
Host smart-b1f4cec2-a327-4acf-8f0a-053d5d011571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838294002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3838294002
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.737152368
Short name T129
Test name
Test status
Simulation time 1375298026 ps
CPU time 19.38 seconds
Started Jul 29 05:15:54 PM PDT 24
Finished Jul 29 05:16:14 PM PDT 24
Peak memory 220044 kb
Host smart-54e966ec-2bf4-4092-a01e-302aff982822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737152368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.737152368
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3971427449
Short name T254
Test name
Test status
Simulation time 773017470 ps
CPU time 11.74 seconds
Started Jul 29 05:15:53 PM PDT 24
Finished Jul 29 05:16:05 PM PDT 24
Peak memory 220048 kb
Host smart-1694603a-7bc3-4b90-a8d5-3a20650bf282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971427449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3971427449
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2587459262
Short name T285
Test name
Test status
Simulation time 1623887041 ps
CPU time 21.74 seconds
Started Jul 29 05:15:47 PM PDT 24
Finished Jul 29 05:16:09 PM PDT 24
Peak memory 219892 kb
Host smart-a4d71e54-6574-4b45-b62c-4b6e86a81fe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587459262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2587459262
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2255274033
Short name T108
Test name
Test status
Simulation time 91446784715 ps
CPU time 922.77 seconds
Started Jul 29 05:15:55 PM PDT 24
Finished Jul 29 05:31:17 PM PDT 24
Peak memory 233372 kb
Host smart-a7d36bba-4cea-49bd-b13b-dccdeb4d910c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255274033 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2255274033
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3581066271
Short name T202
Test name
Test status
Simulation time 921294462 ps
CPU time 9.56 seconds
Started Jul 29 05:15:53 PM PDT 24
Finished Jul 29 05:16:03 PM PDT 24
Peak memory 219088 kb
Host smart-c8b4748a-a017-4a2e-8660-6ca3afc5861a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581066271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3581066271
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1763869080
Short name T237
Test name
Test status
Simulation time 4425295967 ps
CPU time 230.92 seconds
Started Jul 29 05:15:53 PM PDT 24
Finished Jul 29 05:19:44 PM PDT 24
Peak memory 220340 kb
Host smart-e58a95cc-b835-40da-98b5-c9725a5d137d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763869080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1763869080
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2030354537
Short name T3
Test name
Test status
Simulation time 1010260141 ps
CPU time 22.93 seconds
Started Jul 29 05:15:52 PM PDT 24
Finished Jul 29 05:16:15 PM PDT 24
Peak memory 220032 kb
Host smart-0165bbeb-883b-4338-b703-4a17eecb4bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030354537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2030354537
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3395935215
Short name T149
Test name
Test status
Simulation time 1292736909 ps
CPU time 11.93 seconds
Started Jul 29 05:15:54 PM PDT 24
Finished Jul 29 05:16:06 PM PDT 24
Peak memory 220052 kb
Host smart-725e88ec-0896-4b72-b859-2b114f89d9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395935215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3395935215
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1656262739
Short name T136
Test name
Test status
Simulation time 566922922 ps
CPU time 27.73 seconds
Started Jul 29 05:15:52 PM PDT 24
Finished Jul 29 05:16:20 PM PDT 24
Peak memory 219968 kb
Host smart-5d2c89e2-cf4f-4c5a-afb5-d979e9d9a838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656262739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1656262739
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2441752229
Short name T109
Test name
Test status
Simulation time 76747488385 ps
CPU time 2926.34 seconds
Started Jul 29 05:15:53 PM PDT 24
Finished Jul 29 06:04:40 PM PDT 24
Peak memory 245592 kb
Host smart-6074cb76-ad6b-4132-af04-8fe7cb287fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441752229 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2441752229
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2916414199
Short name T127
Test name
Test status
Simulation time 250346541 ps
CPU time 9.98 seconds
Started Jul 29 05:16:19 PM PDT 24
Finished Jul 29 05:16:30 PM PDT 24
Peak memory 219952 kb
Host smart-5985fea5-9bd4-4b41-b24b-17a7485e2766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916414199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2916414199
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1322323359
Short name T47
Test name
Test status
Simulation time 43698873442 ps
CPU time 210.49 seconds
Started Jul 29 05:15:59 PM PDT 24
Finished Jul 29 05:19:29 PM PDT 24
Peak memory 238596 kb
Host smart-5bfd2648-96e7-4415-8382-894dd89ae523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322323359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1322323359
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3011075624
Short name T280
Test name
Test status
Simulation time 2070026986 ps
CPU time 22.44 seconds
Started Jul 29 05:15:59 PM PDT 24
Finished Jul 29 05:16:22 PM PDT 24
Peak memory 220044 kb
Host smart-477b66ed-56d8-4dd7-aca6-feb740d26f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011075624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3011075624
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3348842074
Short name T266
Test name
Test status
Simulation time 183885763 ps
CPU time 10.33 seconds
Started Jul 29 05:15:52 PM PDT 24
Finished Jul 29 05:16:03 PM PDT 24
Peak memory 220056 kb
Host smart-4adc54ff-64c9-4180-9b99-aca58d018db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348842074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3348842074
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3950690838
Short name T134
Test name
Test status
Simulation time 505756412 ps
CPU time 10.57 seconds
Started Jul 29 05:16:00 PM PDT 24
Finished Jul 29 05:16:10 PM PDT 24
Peak memory 219000 kb
Host smart-08376e5e-bb69-4e74-b554-3be4f22d0995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950690838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3950690838
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4077733569
Short name T183
Test name
Test status
Simulation time 13377284104 ps
CPU time 141.12 seconds
Started Jul 29 05:16:05 PM PDT 24
Finished Jul 29 05:18:27 PM PDT 24
Peak memory 220364 kb
Host smart-241d72c8-0468-4f8f-acc0-f03dac210ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077733569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4077733569
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4278765069
Short name T94
Test name
Test status
Simulation time 1016496495 ps
CPU time 11.82 seconds
Started Jul 29 05:16:23 PM PDT 24
Finished Jul 29 05:16:35 PM PDT 24
Peak memory 220088 kb
Host smart-4ee66cb2-84d0-4192-b9bd-f9ec133b7819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278765069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4278765069
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2797918257
Short name T227
Test name
Test status
Simulation time 591583123 ps
CPU time 23.7 seconds
Started Jul 29 05:16:02 PM PDT 24
Finished Jul 29 05:16:26 PM PDT 24
Peak memory 219952 kb
Host smart-f5e9ebee-5627-44b9-b0f6-ae7b212f0b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797918257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2797918257
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2320255995
Short name T250
Test name
Test status
Simulation time 692236562 ps
CPU time 8.53 seconds
Started Jul 29 05:16:13 PM PDT 24
Finished Jul 29 05:16:22 PM PDT 24
Peak memory 219120 kb
Host smart-d0c234d4-f225-4414-9ee1-4cfd3b174428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320255995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2320255995
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1970420583
Short name T304
Test name
Test status
Simulation time 7385962910 ps
CPU time 163.29 seconds
Started Jul 29 05:16:00 PM PDT 24
Finished Jul 29 05:18:43 PM PDT 24
Peak memory 236288 kb
Host smart-edf8d126-7f46-4565-86b1-9eb5bf7bd391
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970420583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1970420583
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.22252366
Short name T156
Test name
Test status
Simulation time 1321398249 ps
CPU time 19.54 seconds
Started Jul 29 05:16:10 PM PDT 24
Finished Jul 29 05:16:29 PM PDT 24
Peak memory 220052 kb
Host smart-27e8765a-ac9d-4539-96b8-9fad64b64ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22252366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.22252366
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1854981035
Short name T142
Test name
Test status
Simulation time 1208900286 ps
CPU time 12.15 seconds
Started Jul 29 05:16:03 PM PDT 24
Finished Jul 29 05:16:15 PM PDT 24
Peak memory 219964 kb
Host smart-20ae965e-61f0-4b40-b115-793d43eba994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854981035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1854981035
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1797314573
Short name T182
Test name
Test status
Simulation time 381036797 ps
CPU time 24.73 seconds
Started Jul 29 05:16:02 PM PDT 24
Finished Jul 29 05:16:27 PM PDT 24
Peak memory 219972 kb
Host smart-6ad69950-438c-49d2-8af7-f17b338a361a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797314573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1797314573
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1174128811
Short name T14
Test name
Test status
Simulation time 249159029391 ps
CPU time 2439.27 seconds
Started Jul 29 05:16:14 PM PDT 24
Finished Jul 29 05:56:54 PM PDT 24
Peak memory 247740 kb
Host smart-5e5e1a85-66a3-469d-a795-3e0fdd3e9a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174128811 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1174128811
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3017600843
Short name T230
Test name
Test status
Simulation time 4103380862 ps
CPU time 10.47 seconds
Started Jul 29 05:16:15 PM PDT 24
Finished Jul 29 05:16:26 PM PDT 24
Peak memory 219200 kb
Host smart-d9a7a4f5-8e6a-40fc-a1d1-09307ac7848f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017600843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3017600843
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3786301332
Short name T184
Test name
Test status
Simulation time 2521195771 ps
CPU time 146.77 seconds
Started Jul 29 05:16:20 PM PDT 24
Finished Jul 29 05:18:47 PM PDT 24
Peak memory 233980 kb
Host smart-bb559ee1-7b41-42f9-89a3-674667b33763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786301332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3786301332
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4164274506
Short name T146
Test name
Test status
Simulation time 1329856069 ps
CPU time 22.52 seconds
Started Jul 29 05:16:07 PM PDT 24
Finished Jul 29 05:16:29 PM PDT 24
Peak memory 219968 kb
Host smart-c0b6cf02-70b1-497e-ae3f-b91860512741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164274506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4164274506
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.201418583
Short name T290
Test name
Test status
Simulation time 1055501500 ps
CPU time 12.25 seconds
Started Jul 29 05:16:06 PM PDT 24
Finished Jul 29 05:16:18 PM PDT 24
Peak memory 219996 kb
Host smart-a6d3e562-83ac-47f8-a38b-a4e41d7f5542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201418583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.201418583
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.909715135
Short name T175
Test name
Test status
Simulation time 303759610 ps
CPU time 20.87 seconds
Started Jul 29 05:16:11 PM PDT 24
Finished Jul 29 05:16:32 PM PDT 24
Peak memory 219984 kb
Host smart-b2a31657-839e-4179-977d-f3479852b39f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909715135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.909715135
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2397320951
Short name T50
Test name
Test status
Simulation time 20633965561 ps
CPU time 6172.09 seconds
Started Jul 29 05:16:25 PM PDT 24
Finished Jul 29 06:59:18 PM PDT 24
Peak memory 220968 kb
Host smart-05bf584e-51c0-4161-bfb1-e0c18b406301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397320951 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2397320951
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2663858446
Short name T135
Test name
Test status
Simulation time 662892784 ps
CPU time 8.45 seconds
Started Jul 29 05:16:06 PM PDT 24
Finished Jul 29 05:16:15 PM PDT 24
Peak memory 218980 kb
Host smart-54acdd22-c563-4a16-acf2-9c77ad5d1e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663858446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2663858446
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3727343855
Short name T276
Test name
Test status
Simulation time 23724722876 ps
CPU time 330.55 seconds
Started Jul 29 05:21:01 PM PDT 24
Finished Jul 29 05:26:31 PM PDT 24
Peak memory 235640 kb
Host smart-92aa3fe3-516a-441b-8e38-215bf99d0f0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727343855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3727343855
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2708480272
Short name T298
Test name
Test status
Simulation time 343006601 ps
CPU time 19.48 seconds
Started Jul 29 05:16:10 PM PDT 24
Finished Jul 29 05:16:30 PM PDT 24
Peak memory 220008 kb
Host smart-2e38d0db-4f34-4dc5-ae4a-cfde8de3cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708480272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2708480272
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2968563452
Short name T281
Test name
Test status
Simulation time 1076159207 ps
CPU time 12.41 seconds
Started Jul 29 05:16:05 PM PDT 24
Finished Jul 29 05:16:18 PM PDT 24
Peak memory 220016 kb
Host smart-67cbc628-748e-47f5-b7f1-42eb873f205f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968563452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2968563452
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.106700581
Short name T187
Test name
Test status
Simulation time 2249562251 ps
CPU time 23.33 seconds
Started Jul 29 05:16:06 PM PDT 24
Finished Jul 29 05:16:30 PM PDT 24
Peak memory 220064 kb
Host smart-d7ba19e6-a996-4f0f-84de-9e8afbf96fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106700581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.106700581
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2249788158
Short name T263
Test name
Test status
Simulation time 990637778 ps
CPU time 9.81 seconds
Started Jul 29 05:16:06 PM PDT 24
Finished Jul 29 05:16:15 PM PDT 24
Peak memory 219080 kb
Host smart-193f832e-ad78-4433-969c-f9ce879978c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249788158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2249788158
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.827988411
Short name T300
Test name
Test status
Simulation time 11263343151 ps
CPU time 186.56 seconds
Started Jul 29 05:16:07 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 220324 kb
Host smart-5e35d1c7-87c7-414e-afab-56d845de5b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827988411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.827988411
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2128366041
Short name T44
Test name
Test status
Simulation time 1377146079 ps
CPU time 19.53 seconds
Started Jul 29 05:16:08 PM PDT 24
Finished Jul 29 05:16:28 PM PDT 24
Peak memory 220008 kb
Host smart-7fe46ae1-833f-4052-b3dc-a9449b1cac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128366041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2128366041
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.644294582
Short name T6
Test name
Test status
Simulation time 508484210 ps
CPU time 11.44 seconds
Started Jul 29 05:16:14 PM PDT 24
Finished Jul 29 05:16:25 PM PDT 24
Peak memory 220032 kb
Host smart-7be455d1-ec09-43f7-a048-37b86b3e7f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=644294582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.644294582
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4199702058
Short name T105
Test name
Test status
Simulation time 1125932025 ps
CPU time 27.55 seconds
Started Jul 29 05:16:08 PM PDT 24
Finished Jul 29 05:16:35 PM PDT 24
Peak memory 220004 kb
Host smart-d7ea9c59-be9d-4c88-b70e-faa2a966a707
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199702058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4199702058
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4018832994
Short name T54
Test name
Test status
Simulation time 103933699553 ps
CPU time 671.68 seconds
Started Jul 29 05:16:10 PM PDT 24
Finished Jul 29 05:27:22 PM PDT 24
Peak memory 236212 kb
Host smart-2939ad9a-f049-4bab-9f11-fb7fa29730bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018832994 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4018832994
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.465848762
Short name T148
Test name
Test status
Simulation time 505685692 ps
CPU time 10.22 seconds
Started Jul 29 05:16:07 PM PDT 24
Finished Jul 29 05:16:18 PM PDT 24
Peak memory 219120 kb
Host smart-0bd24a2f-fc13-42a4-966f-de672b4c668e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465848762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.465848762
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.713261415
Short name T270
Test name
Test status
Simulation time 3773175500 ps
CPU time 125.83 seconds
Started Jul 29 05:16:05 PM PDT 24
Finished Jul 29 05:18:11 PM PDT 24
Peak memory 237100 kb
Host smart-8f1e0279-d812-4b8e-a45f-ebe528dd82a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713261415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.713261415
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2909066690
Short name T176
Test name
Test status
Simulation time 1970177388 ps
CPU time 32.95 seconds
Started Jul 29 05:16:20 PM PDT 24
Finished Jul 29 05:16:53 PM PDT 24
Peak memory 219452 kb
Host smart-a166eb33-2f43-4198-97b1-069ef1fbf273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909066690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2909066690
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.132059730
Short name T195
Test name
Test status
Simulation time 179536169 ps
CPU time 10.1 seconds
Started Jul 29 05:21:00 PM PDT 24
Finished Jul 29 05:21:11 PM PDT 24
Peak memory 219840 kb
Host smart-d3467cd1-f2f2-48e8-a051-448206b2d4af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132059730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.132059730
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.509388060
Short name T12
Test name
Test status
Simulation time 5414321951 ps
CPU time 33.43 seconds
Started Jul 29 05:16:16 PM PDT 24
Finished Jul 29 05:16:49 PM PDT 24
Peak memory 220096 kb
Host smart-7e1690fb-5d02-4f3f-bc41-425d481e92a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509388060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.509388060
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2721991277
Short name T16
Test name
Test status
Simulation time 1546153640 ps
CPU time 10.14 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:54 PM PDT 24
Peak memory 219144 kb
Host smart-2b58baf9-5988-4212-adb6-9e0c45d2e6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721991277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2721991277
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1068493697
Short name T171
Test name
Test status
Simulation time 15190238009 ps
CPU time 254.9 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:19:01 PM PDT 24
Peak memory 239056 kb
Host smart-ec585b98-6fe6-41a4-a361-9d7b9ab1ade9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068493697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1068493697
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3823883504
Short name T150
Test name
Test status
Simulation time 755702073 ps
CPU time 18.93 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:15:03 PM PDT 24
Peak memory 219984 kb
Host smart-0d27707f-d601-4257-9c87-fbc236ad9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823883504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3823883504
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2181464779
Short name T220
Test name
Test status
Simulation time 975109025 ps
CPU time 10.45 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:14:58 PM PDT 24
Peak memory 219992 kb
Host smart-10e7646c-9ce8-4378-a59c-88bdc6f660d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181464779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2181464779
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3118856463
Short name T288
Test name
Test status
Simulation time 262153245 ps
CPU time 12.28 seconds
Started Jul 29 05:14:36 PM PDT 24
Finished Jul 29 05:14:48 PM PDT 24
Peak memory 220020 kb
Host smart-8cc6b62c-03e4-4407-9d2f-e1f18ebc8328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118856463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3118856463
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1484314407
Short name T163
Test name
Test status
Simulation time 370715682 ps
CPU time 23.33 seconds
Started Jul 29 05:14:37 PM PDT 24
Finished Jul 29 05:15:01 PM PDT 24
Peak memory 219960 kb
Host smart-71a3117d-ed70-458f-bfa2-01d6e1ee63fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484314407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1484314407
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3131248253
Short name T225
Test name
Test status
Simulation time 249277074 ps
CPU time 10.15 seconds
Started Jul 29 05:14:46 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 219172 kb
Host smart-c85e9318-9795-473d-b458-047e63a76989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131248253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3131248253
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.785385362
Short name T35
Test name
Test status
Simulation time 24808493722 ps
CPU time 434.96 seconds
Started Jul 29 05:14:44 PM PDT 24
Finished Jul 29 05:22:00 PM PDT 24
Peak memory 220292 kb
Host smart-419f98ea-bc41-41f2-bd2c-00eeeb62f859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785385362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.785385362
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.119937722
Short name T9
Test name
Test status
Simulation time 7869736661 ps
CPU time 32.11 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:15:14 PM PDT 24
Peak memory 220172 kb
Host smart-c216b836-11a6-4969-a5f6-627fbc0fb358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119937722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.119937722
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1932990733
Short name T25
Test name
Test status
Simulation time 270298428 ps
CPU time 12.22 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:55 PM PDT 24
Peak memory 219976 kb
Host smart-2ef0449a-fcd2-4dbc-991c-2c58badf8d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932990733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1932990733
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4016467833
Short name T74
Test name
Test status
Simulation time 653938560 ps
CPU time 10.74 seconds
Started Jul 29 05:14:49 PM PDT 24
Finished Jul 29 05:15:00 PM PDT 24
Peak memory 219964 kb
Host smart-6c8fcf29-dde2-4446-8c9f-ab1f99ce9018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016467833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4016467833
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1472221460
Short name T239
Test name
Test status
Simulation time 2996177621 ps
CPU time 51.75 seconds
Started Jul 29 05:14:42 PM PDT 24
Finished Jul 29 05:15:34 PM PDT 24
Peak memory 220044 kb
Host smart-b3874e81-397a-4c9a-80c7-07967c68bdc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472221460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1472221460
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.722630094
Short name T278
Test name
Test status
Simulation time 888476725 ps
CPU time 9.96 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:14:59 PM PDT 24
Peak memory 219052 kb
Host smart-de6e2426-bb39-43ca-8fcb-b49f0a711dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722630094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.722630094
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3957706461
Short name T224
Test name
Test status
Simulation time 14826230684 ps
CPU time 239.38 seconds
Started Jul 29 05:14:49 PM PDT 24
Finished Jul 29 05:18:48 PM PDT 24
Peak memory 235608 kb
Host smart-0246ebeb-cb5e-4c19-ad59-3f88ed9be6ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957706461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3957706461
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1254887750
Short name T313
Test name
Test status
Simulation time 498188296 ps
CPU time 22.6 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:15:11 PM PDT 24
Peak memory 220076 kb
Host smart-d8abf468-9978-4e58-8203-c8a5b3d5c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254887750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1254887750
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.713389062
Short name T33
Test name
Test status
Simulation time 366814025 ps
CPU time 10.87 seconds
Started Jul 29 05:14:50 PM PDT 24
Finished Jul 29 05:15:01 PM PDT 24
Peak memory 220076 kb
Host smart-d38761f6-005c-4f53-bfdf-cf16ddac422d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713389062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.713389062
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.396276502
Short name T265
Test name
Test status
Simulation time 720612884 ps
CPU time 10.4 seconds
Started Jul 29 05:14:43 PM PDT 24
Finished Jul 29 05:14:54 PM PDT 24
Peak memory 219996 kb
Host smart-802d5038-1175-4d76-ac63-9fa6fb62b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396276502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.396276502
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.922127185
Short name T252
Test name
Test status
Simulation time 250576349 ps
CPU time 9.85 seconds
Started Jul 29 05:14:56 PM PDT 24
Finished Jul 29 05:15:06 PM PDT 24
Peak memory 219048 kb
Host smart-ce4c125f-93e1-4457-8289-f34e1c8900fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922127185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.922127185
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3946180925
Short name T212
Test name
Test status
Simulation time 3623935252 ps
CPU time 179.22 seconds
Started Jul 29 05:14:56 PM PDT 24
Finished Jul 29 05:17:56 PM PDT 24
Peak memory 238424 kb
Host smart-0264d975-a6f8-45d3-ae82-fc4ef2fe5dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946180925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3946180925
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.491366191
Short name T269
Test name
Test status
Simulation time 1835892480 ps
CPU time 19.04 seconds
Started Jul 29 05:14:58 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 220268 kb
Host smart-ca8a71d4-e50a-4d7a-9407-decc70db91ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491366191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.491366191
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.309104174
Short name T27
Test name
Test status
Simulation time 267406767 ps
CPU time 12.62 seconds
Started Jul 29 05:14:57 PM PDT 24
Finished Jul 29 05:15:09 PM PDT 24
Peak memory 220008 kb
Host smart-26cd2bff-5f61-4e9c-ada7-d2c0d18ab28b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309104174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.309104174
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2617053483
Short name T292
Test name
Test status
Simulation time 178199682 ps
CPU time 10.15 seconds
Started Jul 29 05:14:48 PM PDT 24
Finished Jul 29 05:14:59 PM PDT 24
Peak memory 220048 kb
Host smart-6c507326-1c8f-45d9-82f6-d0e55bd3d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617053483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2617053483
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1656772783
Short name T78
Test name
Test status
Simulation time 2227904088 ps
CPU time 52.73 seconds
Started Jul 29 05:14:50 PM PDT 24
Finished Jul 29 05:15:43 PM PDT 24
Peak memory 228296 kb
Host smart-4788bf4a-4c0f-4e2d-8f5a-f34b7ffafeee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656772783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1656772783
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3948764907
Short name T52
Test name
Test status
Simulation time 51786208874 ps
CPU time 2134.45 seconds
Started Jul 29 05:14:56 PM PDT 24
Finished Jul 29 05:50:31 PM PDT 24
Peak memory 247136 kb
Host smart-1ca508bc-066f-4573-a681-7ef665ca9d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948764907 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3948764907
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4109244445
Short name T299
Test name
Test status
Simulation time 993144578 ps
CPU time 10.22 seconds
Started Jul 29 05:14:57 PM PDT 24
Finished Jul 29 05:15:08 PM PDT 24
Peak memory 219024 kb
Host smart-4b9fe8a7-be33-4578-abf0-2d3fce9558d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109244445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4109244445
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2864813098
Short name T194
Test name
Test status
Simulation time 1834357681 ps
CPU time 139.79 seconds
Started Jul 29 05:14:57 PM PDT 24
Finished Jul 29 05:17:17 PM PDT 24
Peak memory 236992 kb
Host smart-7fad59f9-7d94-4cdb-9bd1-3b6fc7469bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864813098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2864813098
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2530541719
Short name T126
Test name
Test status
Simulation time 6608898057 ps
CPU time 19.69 seconds
Started Jul 29 05:14:56 PM PDT 24
Finished Jul 29 05:15:15 PM PDT 24
Peak memory 220084 kb
Host smart-21bebc83-492d-4757-b5cf-a4ab596194a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530541719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2530541719
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1494234158
Short name T28
Test name
Test status
Simulation time 3178511893 ps
CPU time 12.39 seconds
Started Jul 29 05:14:58 PM PDT 24
Finished Jul 29 05:15:11 PM PDT 24
Peak memory 220152 kb
Host smart-cbcb5955-b8d8-4d22-ab9b-47ba11006e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494234158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1494234158
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2888450736
Short name T132
Test name
Test status
Simulation time 1028165089 ps
CPU time 16.79 seconds
Started Jul 29 05:14:55 PM PDT 24
Finished Jul 29 05:15:12 PM PDT 24
Peak memory 220064 kb
Host smart-ab627d74-01ee-4389-88c5-28e94bd4c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888450736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2888450736
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.228563408
Short name T279
Test name
Test status
Simulation time 10316515969 ps
CPU time 47.54 seconds
Started Jul 29 05:14:58 PM PDT 24
Finished Jul 29 05:15:46 PM PDT 24
Peak memory 220684 kb
Host smart-94d5169c-458b-4fd7-a239-1061af3c8ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228563408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.228563408
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3859694223
Short name T260
Test name
Test status
Simulation time 39454467687 ps
CPU time 749.85 seconds
Started Jul 29 05:14:56 PM PDT 24
Finished Jul 29 05:27:26 PM PDT 24
Peak memory 232384 kb
Host smart-51fd55d3-7a87-4d1d-a264-aba07a02961a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859694223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3859694223
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%