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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 96.89 92.28 97.68 100.00 98.62 97.30 98.37


Total test records in report: 410
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T291 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2707251187 Jul 30 05:26:59 PM PDT 24 Jul 30 05:27:18 PM PDT 24 2362915264 ps
T292 /workspace/coverage/default/5.rom_ctrl_stress_all.1898622213 Jul 30 05:26:56 PM PDT 24 Jul 30 05:27:17 PM PDT 24 1742337798 ps
T293 /workspace/coverage/default/35.rom_ctrl_stress_all.2449186410 Jul 30 05:27:48 PM PDT 24 Jul 30 05:28:06 PM PDT 24 359135193 ps
T294 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4211674613 Jul 30 05:26:54 PM PDT 24 Jul 30 05:27:16 PM PDT 24 502652617 ps
T295 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2068903806 Jul 30 05:27:26 PM PDT 24 Jul 30 05:33:04 PM PDT 24 5658702438 ps
T296 /workspace/coverage/default/20.rom_ctrl_alert_test.2929706425 Jul 30 05:27:14 PM PDT 24 Jul 30 05:27:25 PM PDT 24 987694840 ps
T297 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1156863677 Jul 30 05:27:33 PM PDT 24 Jul 30 05:27:52 PM PDT 24 1377629616 ps
T298 /workspace/coverage/default/1.rom_ctrl_stress_all.1880934670 Jul 30 05:26:58 PM PDT 24 Jul 30 05:27:46 PM PDT 24 1039159150 ps
T299 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2552047304 Jul 30 05:27:55 PM PDT 24 Jul 30 05:28:05 PM PDT 24 183190943 ps
T300 /workspace/coverage/default/20.rom_ctrl_stress_all.2252653986 Jul 30 05:27:15 PM PDT 24 Jul 30 05:27:34 PM PDT 24 231294897 ps
T301 /workspace/coverage/default/27.rom_ctrl_stress_all.3923515870 Jul 30 05:27:28 PM PDT 24 Jul 30 05:28:09 PM PDT 24 3053837473 ps
T302 /workspace/coverage/default/21.rom_ctrl_alert_test.3118973875 Jul 30 05:27:20 PM PDT 24 Jul 30 05:27:29 PM PDT 24 171348075 ps
T303 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3162689284 Jul 30 05:28:08 PM PDT 24 Jul 30 05:28:19 PM PDT 24 276544628 ps
T304 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.403109941 Jul 30 05:28:14 PM PDT 24 Jul 30 05:28:24 PM PDT 24 1748866128 ps
T305 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.815078582 Jul 30 05:27:01 PM PDT 24 Jul 30 05:31:31 PM PDT 24 3957071747 ps
T306 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.668771247 Jul 30 05:28:10 PM PDT 24 Jul 30 05:30:05 PM PDT 24 3888937174 ps
T307 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2648547603 Jul 30 05:27:55 PM PDT 24 Jul 30 05:30:52 PM PDT 24 35894202509 ps
T308 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.178748394 Jul 30 05:27:23 PM PDT 24 Jul 30 05:34:37 PM PDT 24 8193910830 ps
T309 /workspace/coverage/default/23.rom_ctrl_stress_all.3644775341 Jul 30 05:27:19 PM PDT 24 Jul 30 05:28:00 PM PDT 24 3120790445 ps
T310 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2345304742 Jul 30 05:26:59 PM PDT 24 Jul 30 05:27:23 PM PDT 24 506376883 ps
T311 /workspace/coverage/default/1.rom_ctrl_alert_test.285698750 Jul 30 05:26:59 PM PDT 24 Jul 30 05:27:09 PM PDT 24 1031463443 ps
T312 /workspace/coverage/default/45.rom_ctrl_stress_all.24684322 Jul 30 05:28:05 PM PDT 24 Jul 30 05:28:40 PM PDT 24 3551070607 ps
T313 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.970603477 Jul 30 05:27:10 PM PDT 24 Jul 30 05:30:05 PM PDT 24 5032577144 ps
T314 /workspace/coverage/default/42.rom_ctrl_alert_test.2646612817 Jul 30 05:28:01 PM PDT 24 Jul 30 05:28:09 PM PDT 24 180140008 ps
T315 /workspace/coverage/default/47.rom_ctrl_stress_all.2622858798 Jul 30 05:28:10 PM PDT 24 Jul 30 05:28:44 PM PDT 24 518988718 ps
T316 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3381588068 Jul 30 05:27:27 PM PDT 24 Jul 30 05:34:05 PM PDT 24 36376075329 ps
T317 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3444020795 Jul 30 05:27:49 PM PDT 24 Jul 30 05:32:10 PM PDT 24 4593998993 ps
T318 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2142769185 Jul 30 05:27:27 PM PDT 24 Jul 30 05:27:50 PM PDT 24 1011621381 ps
T319 /workspace/coverage/default/7.rom_ctrl_stress_all.2387165482 Jul 30 05:27:00 PM PDT 24 Jul 30 05:27:31 PM PDT 24 1095960813 ps
T320 /workspace/coverage/default/10.rom_ctrl_stress_all.623461123 Jul 30 05:27:02 PM PDT 24 Jul 30 05:27:26 PM PDT 24 362798894 ps
T321 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1646201432 Jul 30 05:26:55 PM PDT 24 Jul 30 05:27:06 PM PDT 24 692936340 ps
T55 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3170954737 Jul 30 05:29:09 PM PDT 24 Jul 30 05:29:18 PM PDT 24 346305343 ps
T56 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1780937180 Jul 30 05:28:40 PM PDT 24 Jul 30 05:28:48 PM PDT 24 174654720 ps
T322 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.558785260 Jul 30 05:28:20 PM PDT 24 Jul 30 05:28:30 PM PDT 24 259949357 ps
T52 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.911788198 Jul 30 05:28:42 PM PDT 24 Jul 30 05:30:02 PM PDT 24 335706249 ps
T323 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3747987006 Jul 30 05:28:35 PM PDT 24 Jul 30 05:28:45 PM PDT 24 253231731 ps
T324 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1213595694 Jul 30 05:28:37 PM PDT 24 Jul 30 05:28:47 PM PDT 24 1129023804 ps
T53 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1218393347 Jul 30 05:29:01 PM PDT 24 Jul 30 05:30:26 PM PDT 24 1227368742 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2753987677 Jul 30 05:28:25 PM PDT 24 Jul 30 05:28:39 PM PDT 24 1976809248 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2835515240 Jul 30 05:28:52 PM PDT 24 Jul 30 05:29:30 PM PDT 24 2846124010 ps
T325 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.981048698 Jul 30 05:28:34 PM PDT 24 Jul 30 05:28:46 PM PDT 24 661449806 ps
T326 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.45663698 Jul 30 05:28:37 PM PDT 24 Jul 30 05:28:47 PM PDT 24 509492583 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3913427925 Jul 30 05:28:22 PM PDT 24 Jul 30 05:28:38 PM PDT 24 171157531 ps
T78 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2482612339 Jul 30 05:28:32 PM PDT 24 Jul 30 05:29:18 PM PDT 24 1041007940 ps
T79 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4279970487 Jul 30 05:28:49 PM PDT 24 Jul 30 05:29:03 PM PDT 24 262086089 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3206329506 Jul 30 05:28:55 PM PDT 24 Jul 30 05:29:05 PM PDT 24 497944942 ps
T327 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2613479345 Jul 30 05:28:29 PM PDT 24 Jul 30 05:28:40 PM PDT 24 1038931128 ps
T59 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3523349546 Jul 30 05:28:49 PM PDT 24 Jul 30 05:28:59 PM PDT 24 249527878 ps
T80 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.840603631 Jul 30 05:28:46 PM PDT 24 Jul 30 05:28:54 PM PDT 24 720046824 ps
T54 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1463695450 Jul 30 05:29:09 PM PDT 24 Jul 30 05:30:29 PM PDT 24 1495142980 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2443105615 Jul 30 05:28:32 PM PDT 24 Jul 30 05:28:42 PM PDT 24 825049379 ps
T60 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1435931911 Jul 30 05:28:37 PM PDT 24 Jul 30 05:28:46 PM PDT 24 209954846 ps
T329 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3214912127 Jul 30 05:28:25 PM PDT 24 Jul 30 05:28:34 PM PDT 24 692695825 ps
T330 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2687642425 Jul 30 05:28:38 PM PDT 24 Jul 30 05:28:51 PM PDT 24 661626166 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.610625789 Jul 30 05:28:37 PM PDT 24 Jul 30 05:28:47 PM PDT 24 514811893 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3852192066 Jul 30 05:29:06 PM PDT 24 Jul 30 05:29:16 PM PDT 24 983790498 ps
T331 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1484214491 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:09 PM PDT 24 250490991 ps
T332 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.278349503 Jul 30 05:28:21 PM PDT 24 Jul 30 05:28:29 PM PDT 24 194926724 ps
T333 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4219236713 Jul 30 05:29:04 PM PDT 24 Jul 30 05:29:17 PM PDT 24 995773802 ps
T334 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.388294080 Jul 30 05:28:23 PM PDT 24 Jul 30 05:28:38 PM PDT 24 4115067996 ps
T335 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.231864588 Jul 30 05:28:37 PM PDT 24 Jul 30 05:28:47 PM PDT 24 766744777 ps
T336 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3024037111 Jul 30 05:29:15 PM PDT 24 Jul 30 05:29:25 PM PDT 24 1183002303 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.646152381 Jul 30 05:28:45 PM PDT 24 Jul 30 05:29:00 PM PDT 24 4085615515 ps
T337 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.562069870 Jul 30 05:28:40 PM PDT 24 Jul 30 05:28:51 PM PDT 24 2352000386 ps
T338 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1200861061 Jul 30 05:28:46 PM PDT 24 Jul 30 05:28:54 PM PDT 24 701050493 ps
T339 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2141230410 Jul 30 05:28:40 PM PDT 24 Jul 30 05:28:51 PM PDT 24 269578339 ps
T340 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2987137416 Jul 30 05:29:10 PM PDT 24 Jul 30 05:29:24 PM PDT 24 251676972 ps
T341 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3550688984 Jul 30 05:29:07 PM PDT 24 Jul 30 05:29:18 PM PDT 24 2007482476 ps
T62 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2188127819 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:14 PM PDT 24 2052797672 ps
T342 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2345393764 Jul 30 05:28:53 PM PDT 24 Jul 30 05:29:03 PM PDT 24 493843290 ps
T343 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.702730 Jul 30 05:28:31 PM PDT 24 Jul 30 05:28:41 PM PDT 24 915670233 ps
T344 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2504001863 Jul 30 05:28:58 PM PDT 24 Jul 30 05:29:11 PM PDT 24 169073944 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2514445903 Jul 30 05:28:56 PM PDT 24 Jul 30 05:30:17 PM PDT 24 452317227 ps
T345 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3565306116 Jul 30 05:28:18 PM PDT 24 Jul 30 05:28:26 PM PDT 24 190036526 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2233749901 Jul 30 05:28:43 PM PDT 24 Jul 30 05:30:03 PM PDT 24 339757511 ps
T346 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4112247605 Jul 30 05:28:34 PM PDT 24 Jul 30 05:28:51 PM PDT 24 1928150828 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3849754549 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:07 PM PDT 24 688296706 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2143927048 Jul 30 05:28:34 PM PDT 24 Jul 30 05:28:42 PM PDT 24 2060482919 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.778990402 Jul 30 05:28:32 PM PDT 24 Jul 30 05:29:56 PM PDT 24 1176632721 ps
T92 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3353931698 Jul 30 05:28:59 PM PDT 24 Jul 30 05:30:20 PM PDT 24 642754190 ps
T348 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2347603788 Jul 30 05:29:10 PM PDT 24 Jul 30 05:29:19 PM PDT 24 919854879 ps
T63 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.260062839 Jul 30 05:28:50 PM PDT 24 Jul 30 05:28:59 PM PDT 24 172532009 ps
T349 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1921140859 Jul 30 05:28:46 PM PDT 24 Jul 30 05:28:54 PM PDT 24 177375302 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2321708747 Jul 30 05:28:38 PM PDT 24 Jul 30 05:31:13 PM PDT 24 1756438653 ps
T350 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2079875297 Jul 30 05:28:41 PM PDT 24 Jul 30 05:28:56 PM PDT 24 249739185 ps
T351 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2850131227 Jul 30 05:28:50 PM PDT 24 Jul 30 05:29:05 PM PDT 24 255879274 ps
T352 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.746437535 Jul 30 05:28:49 PM PDT 24 Jul 30 05:28:58 PM PDT 24 167483472 ps
T353 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2569067264 Jul 30 05:28:34 PM PDT 24 Jul 30 05:28:42 PM PDT 24 921963040 ps
T354 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.595934729 Jul 30 05:28:53 PM PDT 24 Jul 30 05:29:09 PM PDT 24 989218724 ps
T355 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2538718069 Jul 30 05:28:55 PM PDT 24 Jul 30 05:29:07 PM PDT 24 2907610937 ps
T64 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1358072311 Jul 30 05:28:58 PM PDT 24 Jul 30 05:29:08 PM PDT 24 506085508 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3102589152 Jul 30 05:28:22 PM PDT 24 Jul 30 05:29:47 PM PDT 24 5960144513 ps
T356 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.802398518 Jul 30 05:28:49 PM PDT 24 Jul 30 05:31:23 PM PDT 24 1709388312 ps
T357 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.539736802 Jul 30 05:28:26 PM PDT 24 Jul 30 05:28:34 PM PDT 24 1098486961 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2464686001 Jul 30 05:28:45 PM PDT 24 Jul 30 05:30:07 PM PDT 24 923923939 ps
T65 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3625609969 Jul 30 05:29:09 PM PDT 24 Jul 30 05:29:17 PM PDT 24 168548406 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1455247925 Jul 30 05:28:24 PM PDT 24 Jul 30 05:28:34 PM PDT 24 250275606 ps
T359 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2210627941 Jul 30 05:29:04 PM PDT 24 Jul 30 05:29:14 PM PDT 24 3140184876 ps
T360 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.829346436 Jul 30 05:29:14 PM PDT 24 Jul 30 05:29:24 PM PDT 24 250531885 ps
T66 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3091226050 Jul 30 05:28:46 PM PDT 24 Jul 30 05:28:54 PM PDT 24 192953773 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2755245122 Jul 30 05:28:22 PM PDT 24 Jul 30 05:28:36 PM PDT 24 263679254 ps
T361 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4178501098 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:14 PM PDT 24 1985553514 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.640136341 Jul 30 05:28:20 PM PDT 24 Jul 30 05:30:53 PM PDT 24 304321581 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2381087534 Jul 30 05:29:07 PM PDT 24 Jul 30 05:31:41 PM PDT 24 886340913 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3163488922 Jul 30 05:28:17 PM PDT 24 Jul 30 05:28:27 PM PDT 24 3529444540 ps
T363 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2915072623 Jul 30 05:28:49 PM PDT 24 Jul 30 05:29:34 PM PDT 24 14355887126 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2440263714 Jul 30 05:28:26 PM PDT 24 Jul 30 05:28:36 PM PDT 24 259374685 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.934316687 Jul 30 05:28:36 PM PDT 24 Jul 30 05:28:46 PM PDT 24 261277033 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1946914091 Jul 30 05:28:26 PM PDT 24 Jul 30 05:28:42 PM PDT 24 174554780 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2318855290 Jul 30 05:29:00 PM PDT 24 Jul 30 05:29:08 PM PDT 24 386836384 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2105685156 Jul 30 05:29:04 PM PDT 24 Jul 30 05:30:25 PM PDT 24 323454207 ps
T369 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3773770026 Jul 30 05:28:56 PM PDT 24 Jul 30 05:29:06 PM PDT 24 2063032940 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2294528827 Jul 30 05:28:44 PM PDT 24 Jul 30 05:28:54 PM PDT 24 542122911 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3331721007 Jul 30 05:29:02 PM PDT 24 Jul 30 05:29:12 PM PDT 24 255045829 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2347920700 Jul 30 05:29:10 PM PDT 24 Jul 30 05:29:19 PM PDT 24 184548660 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1983408118 Jul 30 05:29:08 PM PDT 24 Jul 30 05:29:21 PM PDT 24 1652297226 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1926645607 Jul 30 05:28:48 PM PDT 24 Jul 30 05:28:58 PM PDT 24 1054385914 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3242939548 Jul 30 05:28:44 PM PDT 24 Jul 30 05:29:00 PM PDT 24 259850907 ps
T376 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3187061181 Jul 30 05:29:16 PM PDT 24 Jul 30 05:29:23 PM PDT 24 167801145 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2870125385 Jul 30 05:29:07 PM PDT 24 Jul 30 05:29:16 PM PDT 24 735420795 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3307392508 Jul 30 05:28:47 PM PDT 24 Jul 30 05:29:03 PM PDT 24 268832575 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3897649920 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:09 PM PDT 24 482109978 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1537224155 Jul 30 05:28:25 PM PDT 24 Jul 30 05:28:35 PM PDT 24 1010431564 ps
T381 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3010319525 Jul 30 05:28:47 PM PDT 24 Jul 30 05:28:55 PM PDT 24 689846248 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2926136055 Jul 30 05:28:45 PM PDT 24 Jul 30 05:28:55 PM PDT 24 189067909 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1734549844 Jul 30 05:28:54 PM PDT 24 Jul 30 05:29:07 PM PDT 24 4962684125 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.710527011 Jul 30 05:29:14 PM PDT 24 Jul 30 05:29:28 PM PDT 24 168221493 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2295282689 Jul 30 05:28:34 PM PDT 24 Jul 30 05:31:25 PM PDT 24 4414270112 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.826010607 Jul 30 05:28:32 PM PDT 24 Jul 30 05:28:40 PM PDT 24 662036721 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1486031233 Jul 30 05:29:07 PM PDT 24 Jul 30 05:29:20 PM PDT 24 178173032 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1284655954 Jul 30 05:29:00 PM PDT 24 Jul 30 05:29:10 PM PDT 24 517526492 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3224328208 Jul 30 05:29:08 PM PDT 24 Jul 30 05:29:16 PM PDT 24 174463869 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.779438442 Jul 30 05:28:29 PM PDT 24 Jul 30 05:28:40 PM PDT 24 992662737 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.415110319 Jul 30 05:28:57 PM PDT 24 Jul 30 05:30:20 PM PDT 24 458668674 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.483883040 Jul 30 05:28:40 PM PDT 24 Jul 30 05:28:52 PM PDT 24 1383060504 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4169413805 Jul 30 05:28:12 PM PDT 24 Jul 30 05:28:51 PM PDT 24 713269044 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.959537938 Jul 30 05:28:42 PM PDT 24 Jul 30 05:28:52 PM PDT 24 1460200784 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2723949515 Jul 30 05:28:36 PM PDT 24 Jul 30 05:28:46 PM PDT 24 1027661574 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2921558233 Jul 30 05:28:57 PM PDT 24 Jul 30 05:29:07 PM PDT 24 1373341502 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.359641665 Jul 30 05:28:19 PM PDT 24 Jul 30 05:28:29 PM PDT 24 4933799530 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3334055585 Jul 30 05:28:38 PM PDT 24 Jul 30 05:28:48 PM PDT 24 383102169 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1329751575 Jul 30 05:28:30 PM PDT 24 Jul 30 05:28:48 PM PDT 24 527665658 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3503917429 Jul 30 05:28:26 PM PDT 24 Jul 30 05:28:35 PM PDT 24 196585162 ps
T398 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1416335921 Jul 30 05:28:59 PM PDT 24 Jul 30 05:29:12 PM PDT 24 338903371 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.459030672 Jul 30 05:29:09 PM PDT 24 Jul 30 05:29:19 PM PDT 24 383292832 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.810871196 Jul 30 05:28:23 PM PDT 24 Jul 30 05:28:31 PM PDT 24 341169617 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1710072655 Jul 30 05:28:52 PM PDT 24 Jul 30 05:31:25 PM PDT 24 1489170445 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.784642736 Jul 30 05:28:38 PM PDT 24 Jul 30 05:28:46 PM PDT 24 173301959 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1621623595 Jul 30 05:29:16 PM PDT 24 Jul 30 05:30:38 PM PDT 24 557156167 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1072148442 Jul 30 05:28:46 PM PDT 24 Jul 30 05:30:08 PM PDT 24 1273070704 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1359341852 Jul 30 05:28:56 PM PDT 24 Jul 30 05:29:07 PM PDT 24 831875456 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3754053753 Jul 30 05:28:41 PM PDT 24 Jul 30 05:28:49 PM PDT 24 313371879 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1499350393 Jul 30 05:29:05 PM PDT 24 Jul 30 05:30:25 PM PDT 24 992427644 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2555037941 Jul 30 05:28:32 PM PDT 24 Jul 30 05:28:45 PM PDT 24 1550414658 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1242321209 Jul 30 05:29:10 PM PDT 24 Jul 30 05:29:20 PM PDT 24 944456469 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.647269570 Jul 30 05:28:53 PM PDT 24 Jul 30 05:29:06 PM PDT 24 260451123 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.135182049 Jul 30 05:28:33 PM PDT 24 Jul 30 05:28:41 PM PDT 24 534588121 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1669233365 Jul 30 05:28:30 PM PDT 24 Jul 30 05:28:39 PM PDT 24 170033516 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3840322064 Jul 30 05:28:36 PM PDT 24 Jul 30 05:28:44 PM PDT 24 332818634 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3592635317 Jul 30 05:28:22 PM PDT 24 Jul 30 05:28:35 PM PDT 24 1036190628 ps

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.758748270
Short name T3
Test name
Test status
Simulation time 120828249698 ps
CPU time 1177.53 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:46:34 PM PDT 24
Peak memory 238932 kb
Host smart-58f94742-5e65-4d69-9e58-5f4fd6329a87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758748270 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.758748270
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2593352286
Short name T1
Test name
Test status
Simulation time 3700489734 ps
CPU time 194.19 seconds
Started Jul 30 05:27:43 PM PDT 24
Finished Jul 30 05:30:58 PM PDT 24
Peak memory 225548 kb
Host smart-f185ee0e-07be-4ce0-a22f-ddcf6a551b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593352286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2593352286
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3604790433
Short name T43
Test name
Test status
Simulation time 10027864635 ps
CPU time 233.91 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:31:04 PM PDT 24
Peak memory 220340 kb
Host smart-7cbf72cd-dbb7-47be-bd76-1d0aaf6ccdb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604790433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3604790433
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2461630069
Short name T141
Test name
Test status
Simulation time 22094162320 ps
CPU time 300.18 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:32:01 PM PDT 24
Peak memory 235436 kb
Host smart-31cb184a-5bfd-4f31-84a9-7d1a3a2b2367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461630069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2461630069
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1463695450
Short name T54
Test name
Test status
Simulation time 1495142980 ps
CPU time 79.61 seconds
Started Jul 30 05:29:09 PM PDT 24
Finished Jul 30 05:30:29 PM PDT 24
Peak memory 213020 kb
Host smart-909900b0-d1a9-47f6-a3cb-b957e7697894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463695450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1463695450
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1736988099
Short name T11
Test name
Test status
Simulation time 7686539623 ps
CPU time 32.56 seconds
Started Jul 30 05:27:17 PM PDT 24
Finished Jul 30 05:27:49 PM PDT 24
Peak memory 220080 kb
Host smart-a030bf40-aae1-4d19-8674-60efaa0ca92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736988099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1736988099
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1025579185
Short name T19
Test name
Test status
Simulation time 492584010 ps
CPU time 229.39 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:30:45 PM PDT 24
Peak memory 239760 kb
Host smart-f7465d6c-9d23-4eb0-828c-6544be23ccc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025579185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1025579185
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2381087534
Short name T99
Test name
Test status
Simulation time 886340913 ps
CPU time 153.68 seconds
Started Jul 30 05:29:07 PM PDT 24
Finished Jul 30 05:31:41 PM PDT 24
Peak memory 214548 kb
Host smart-1abc390f-c417-4e35-9eb0-2d0195abf905
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381087534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2381087534
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3523349546
Short name T59
Test name
Test status
Simulation time 249527878 ps
CPU time 9.83 seconds
Started Jul 30 05:28:49 PM PDT 24
Finished Jul 30 05:28:59 PM PDT 24
Peak memory 210800 kb
Host smart-5d19cd37-7214-4cb9-a7e7-184b9a7fc4e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523349546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3523349546
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.7958088
Short name T26
Test name
Test status
Simulation time 773604219 ps
CPU time 10.13 seconds
Started Jul 30 05:28:00 PM PDT 24
Finished Jul 30 05:28:10 PM PDT 24
Peak memory 219200 kb
Host smart-2e0e91b6-3565-4a57-a0a0-aa9f897eeb0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7958088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.7958088
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.619631547
Short name T41
Test name
Test status
Simulation time 58126833763 ps
CPU time 1710.71 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:55:33 PM PDT 24
Peak memory 236668 kb
Host smart-908369ea-f8e8-42b0-aff9-cd232a7bece8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619631547 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.619631547
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4105056161
Short name T28
Test name
Test status
Simulation time 4575329114 ps
CPU time 32.34 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:27 PM PDT 24
Peak memory 220236 kb
Host smart-eeba7bd7-7369-4477-b938-aeb01d3e3faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105056161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4105056161
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2670414142
Short name T112
Test name
Test status
Simulation time 674642676 ps
CPU time 19.47 seconds
Started Jul 30 05:28:09 PM PDT 24
Finished Jul 30 05:28:29 PM PDT 24
Peak memory 220096 kb
Host smart-bb1bced5-a8ab-4630-ae8e-92e28e79a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670414142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2670414142
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1621623595
Short name T97
Test name
Test status
Simulation time 557156167 ps
CPU time 82.64 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:30:38 PM PDT 24
Peak memory 214016 kb
Host smart-4a51fb95-0344-4223-851e-227f75a14f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621623595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1621623595
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2270627717
Short name T6
Test name
Test status
Simulation time 320318613 ps
CPU time 10.82 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 220056 kb
Host smart-3a8392e7-434e-47c1-a57c-85dfda10a27e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270627717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2270627717
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2482612339
Short name T78
Test name
Test status
Simulation time 1041007940 ps
CPU time 45.12 seconds
Started Jul 30 05:28:32 PM PDT 24
Finished Jul 30 05:29:18 PM PDT 24
Peak memory 214124 kb
Host smart-bd1d1be8-be17-4917-ad33-bfdd5e2cb3ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482612339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2482612339
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3102589152
Short name T95
Test name
Test status
Simulation time 5960144513 ps
CPU time 84.31 seconds
Started Jul 30 05:28:22 PM PDT 24
Finished Jul 30 05:29:47 PM PDT 24
Peak memory 215276 kb
Host smart-e8b604b8-0543-48c7-a6a4-62c7b2a512ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102589152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3102589152
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2514445903
Short name T96
Test name
Test status
Simulation time 452317227 ps
CPU time 81.17 seconds
Started Jul 30 05:28:56 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 214220 kb
Host smart-a5f30204-21bf-44c3-8350-b12cd3411ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514445903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2514445903
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1499350393
Short name T103
Test name
Test status
Simulation time 992427644 ps
CPU time 80.7 seconds
Started Jul 30 05:29:05 PM PDT 24
Finished Jul 30 05:30:25 PM PDT 24
Peak memory 212728 kb
Host smart-4b1a0e83-e30d-4238-987f-c595632101c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499350393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1499350393
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2321708747
Short name T93
Test name
Test status
Simulation time 1756438653 ps
CPU time 154.99 seconds
Started Jul 30 05:28:38 PM PDT 24
Finished Jul 30 05:31:13 PM PDT 24
Peak memory 214572 kb
Host smart-31796608-50f1-4419-9cf3-9be2e12752ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321708747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2321708747
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4169413805
Short name T75
Test name
Test status
Simulation time 713269044 ps
CPU time 38.73 seconds
Started Jul 30 05:28:12 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 214000 kb
Host smart-2a7d11bf-3a57-4975-b67d-b90922175ad6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169413805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4169413805
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.278349503
Short name T332
Test name
Test status
Simulation time 194926724 ps
CPU time 8.1 seconds
Started Jul 30 05:28:21 PM PDT 24
Finished Jul 30 05:28:29 PM PDT 24
Peak memory 210856 kb
Host smart-6fc248d3-3af9-45fa-8fe3-dc1ac6e920e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278349503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.278349503
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.359641665
Short name T394
Test name
Test status
Simulation time 4933799530 ps
CPU time 10.11 seconds
Started Jul 30 05:28:19 PM PDT 24
Finished Jul 30 05:28:29 PM PDT 24
Peak memory 211132 kb
Host smart-59b2e849-480b-4118-9e8f-9f5cbee8e55d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359641665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.359641665
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3913427925
Short name T85
Test name
Test status
Simulation time 171157531 ps
CPU time 15.07 seconds
Started Jul 30 05:28:22 PM PDT 24
Finished Jul 30 05:28:38 PM PDT 24
Peak memory 212256 kb
Host smart-e3c648a0-88c1-417d-b885-2cec5da91870
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913427925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3913427925
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.810871196
Short name T400
Test name
Test status
Simulation time 341169617 ps
CPU time 8.53 seconds
Started Jul 30 05:28:23 PM PDT 24
Finished Jul 30 05:28:31 PM PDT 24
Peak memory 216784 kb
Host smart-c44347da-3bdf-4ea8-8351-84bbcb0057ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810871196 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.810871196
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3163488922
Short name T362
Test name
Test status
Simulation time 3529444540 ps
CPU time 9.66 seconds
Started Jul 30 05:28:17 PM PDT 24
Finished Jul 30 05:28:27 PM PDT 24
Peak memory 211248 kb
Host smart-57b874f9-8c40-4715-97df-067763381d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163488922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3163488922
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3565306116
Short name T345
Test name
Test status
Simulation time 190036526 ps
CPU time 8.13 seconds
Started Jul 30 05:28:18 PM PDT 24
Finished Jul 30 05:28:26 PM PDT 24
Peak memory 210760 kb
Host smart-650f3a68-3972-4d50-aa38-03a7e6211aac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565306116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3565306116
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.558785260
Short name T322
Test name
Test status
Simulation time 259949357 ps
CPU time 10.08 seconds
Started Jul 30 05:28:20 PM PDT 24
Finished Jul 30 05:28:30 PM PDT 24
Peak memory 210816 kb
Host smart-9d74ba90-c986-4b60-8333-0057985877b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558785260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
558785260
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2755245122
Short name T67
Test name
Test status
Simulation time 263679254 ps
CPU time 13.82 seconds
Started Jul 30 05:28:22 PM PDT 24
Finished Jul 30 05:28:36 PM PDT 24
Peak memory 212916 kb
Host smart-edc174ba-25c1-4214-8585-a75e55c027f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755245122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2755245122
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3592635317
Short name T410
Test name
Test status
Simulation time 1036190628 ps
CPU time 12.86 seconds
Started Jul 30 05:28:22 PM PDT 24
Finished Jul 30 05:28:35 PM PDT 24
Peak memory 219180 kb
Host smart-02eeac54-37a0-424b-99e3-69e4fb7dba7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592635317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3592635317
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.640136341
Short name T98
Test name
Test status
Simulation time 304321581 ps
CPU time 153.04 seconds
Started Jul 30 05:28:20 PM PDT 24
Finished Jul 30 05:30:53 PM PDT 24
Peak memory 215632 kb
Host smart-cd0f5f20-e6e9-4b8f-9ae6-dfad127a39d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640136341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.640136341
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3214912127
Short name T329
Test name
Test status
Simulation time 692695825 ps
CPU time 8.43 seconds
Started Jul 30 05:28:25 PM PDT 24
Finished Jul 30 05:28:34 PM PDT 24
Peak memory 211120 kb
Host smart-845a2db4-c496-467e-bbc3-8acd509a8a08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214912127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3214912127
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1455247925
Short name T358
Test name
Test status
Simulation time 250275606 ps
CPU time 9.95 seconds
Started Jul 30 05:28:24 PM PDT 24
Finished Jul 30 05:28:34 PM PDT 24
Peak memory 210880 kb
Host smart-8f04fa4d-f37d-498d-844a-298f1f2fd839
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455247925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1455247925
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1946914091
Short name T366
Test name
Test status
Simulation time 174554780 ps
CPU time 15.21 seconds
Started Jul 30 05:28:26 PM PDT 24
Finished Jul 30 05:28:42 PM PDT 24
Peak memory 212264 kb
Host smart-56b4b020-fe8e-4ecb-905d-f5e7755ac0e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946914091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1946914091
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1537224155
Short name T380
Test name
Test status
Simulation time 1010431564 ps
CPU time 10.41 seconds
Started Jul 30 05:28:25 PM PDT 24
Finished Jul 30 05:28:35 PM PDT 24
Peak memory 217324 kb
Host smart-c7f2cc5d-0800-4244-ad72-52670de807fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537224155 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1537224155
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.826010607
Short name T74
Test name
Test status
Simulation time 662036721 ps
CPU time 8.27 seconds
Started Jul 30 05:28:32 PM PDT 24
Finished Jul 30 05:28:40 PM PDT 24
Peak memory 211188 kb
Host smart-7fd938a0-b7c5-463b-b51a-54f68c6e5463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826010607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.826010607
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2440263714
Short name T364
Test name
Test status
Simulation time 259374685 ps
CPU time 10.02 seconds
Started Jul 30 05:28:26 PM PDT 24
Finished Jul 30 05:28:36 PM PDT 24
Peak memory 210884 kb
Host smart-9fde3167-4dde-4673-828b-f15fae1becc3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440263714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2440263714
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2443105615
Short name T328
Test name
Test status
Simulation time 825049379 ps
CPU time 10.03 seconds
Started Jul 30 05:28:32 PM PDT 24
Finished Jul 30 05:28:42 PM PDT 24
Peak memory 210840 kb
Host smart-d70ee99c-f600-400e-a19d-d70d1ec1fd99
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443105615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2443105615
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2753987677
Short name T77
Test name
Test status
Simulation time 1976809248 ps
CPU time 13.63 seconds
Started Jul 30 05:28:25 PM PDT 24
Finished Jul 30 05:28:39 PM PDT 24
Peak memory 212640 kb
Host smart-b90426ef-5396-4316-9806-5141c50acb34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753987677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2753987677
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.388294080
Short name T334
Test name
Test status
Simulation time 4115067996 ps
CPU time 14.7 seconds
Started Jul 30 05:28:23 PM PDT 24
Finished Jul 30 05:28:38 PM PDT 24
Peak memory 216764 kb
Host smart-4a27dd30-af6e-45c6-8cbf-47f7f6507ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388294080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.388294080
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2345393764
Short name T342
Test name
Test status
Simulation time 493843290 ps
CPU time 10.09 seconds
Started Jul 30 05:28:53 PM PDT 24
Finished Jul 30 05:29:03 PM PDT 24
Peak memory 216996 kb
Host smart-f385f627-0bf7-4ad4-b549-a36d71a5ca26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345393764 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2345393764
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.260062839
Short name T63
Test name
Test status
Simulation time 172532009 ps
CPU time 8.31 seconds
Started Jul 30 05:28:50 PM PDT 24
Finished Jul 30 05:28:59 PM PDT 24
Peak memory 210992 kb
Host smart-efa27c68-a579-4304-ae8f-2017705a46ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260062839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.260062839
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2915072623
Short name T363
Test name
Test status
Simulation time 14355887126 ps
CPU time 44.5 seconds
Started Jul 30 05:28:49 PM PDT 24
Finished Jul 30 05:29:34 PM PDT 24
Peak memory 214312 kb
Host smart-b8e0b17f-b334-4465-9a52-91f5f4a89f81
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915072623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2915072623
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2538718069
Short name T355
Test name
Test status
Simulation time 2907610937 ps
CPU time 12.27 seconds
Started Jul 30 05:28:55 PM PDT 24
Finished Jul 30 05:29:07 PM PDT 24
Peak memory 212824 kb
Host smart-25a127ac-44f8-4e5f-8788-f54622847e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538718069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2538718069
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2850131227
Short name T351
Test name
Test status
Simulation time 255879274 ps
CPU time 14.64 seconds
Started Jul 30 05:28:50 PM PDT 24
Finished Jul 30 05:29:05 PM PDT 24
Peak memory 217776 kb
Host smart-8c1d1a75-087a-420e-86f0-8fcb6c0aa50a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850131227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2850131227
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.802398518
Short name T356
Test name
Test status
Simulation time 1709388312 ps
CPU time 153.7 seconds
Started Jul 30 05:28:49 PM PDT 24
Finished Jul 30 05:31:23 PM PDT 24
Peak memory 215412 kb
Host smart-38a5384f-8201-4146-8678-0583711c8b17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802398518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.802398518
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1359341852
Short name T403
Test name
Test status
Simulation time 831875456 ps
CPU time 10.65 seconds
Started Jul 30 05:28:56 PM PDT 24
Finished Jul 30 05:29:07 PM PDT 24
Peak memory 217952 kb
Host smart-3c20036e-3bdf-4827-b88b-2d6e908ecc0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359341852 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1359341852
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3206329506
Short name T86
Test name
Test status
Simulation time 497944942 ps
CPU time 9.9 seconds
Started Jul 30 05:28:55 PM PDT 24
Finished Jul 30 05:29:05 PM PDT 24
Peak memory 211336 kb
Host smart-f28790b2-0b6e-4ded-a9a0-0326d1a1d52f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206329506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3206329506
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2835515240
Short name T84
Test name
Test status
Simulation time 2846124010 ps
CPU time 37.78 seconds
Started Jul 30 05:28:52 PM PDT 24
Finished Jul 30 05:29:30 PM PDT 24
Peak memory 214088 kb
Host smart-d9e1750f-3907-430c-9156-0587a22d86f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835515240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2835515240
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3773770026
Short name T369
Test name
Test status
Simulation time 2063032940 ps
CPU time 10.03 seconds
Started Jul 30 05:28:56 PM PDT 24
Finished Jul 30 05:29:06 PM PDT 24
Peak memory 211416 kb
Host smart-b60b2c6e-f934-447c-8df0-7ad0b31d8e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773770026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3773770026
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.595934729
Short name T354
Test name
Test status
Simulation time 989218724 ps
CPU time 15.39 seconds
Started Jul 30 05:28:53 PM PDT 24
Finished Jul 30 05:29:09 PM PDT 24
Peak memory 219248 kb
Host smart-534afbd7-c80d-46e3-a95f-fb6d7af6586a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595934729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.595934729
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.415110319
Short name T389
Test name
Test status
Simulation time 458668674 ps
CPU time 83.6 seconds
Started Jul 30 05:28:57 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 214052 kb
Host smart-a058f1f1-0a63-4b06-80fc-debefc26f950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415110319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.415110319
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4178501098
Short name T361
Test name
Test status
Simulation time 1985553514 ps
CPU time 15.12 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:14 PM PDT 24
Peak memory 214012 kb
Host smart-b0e9f9b1-708b-475e-839f-6045283a3086
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178501098 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4178501098
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1358072311
Short name T64
Test name
Test status
Simulation time 506085508 ps
CPU time 9.7 seconds
Started Jul 30 05:28:58 PM PDT 24
Finished Jul 30 05:29:08 PM PDT 24
Peak memory 211192 kb
Host smart-9f6620b2-07bf-4aa3-8697-4693ed31d528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358072311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1358072311
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3849754549
Short name T83
Test name
Test status
Simulation time 688296706 ps
CPU time 8.33 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:07 PM PDT 24
Peak memory 211784 kb
Host smart-08cc7530-3390-4710-b224-9fd0ff1fe5b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849754549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3849754549
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1734549844
Short name T383
Test name
Test status
Simulation time 4962684125 ps
CPU time 12.58 seconds
Started Jul 30 05:28:54 PM PDT 24
Finished Jul 30 05:29:07 PM PDT 24
Peak memory 217872 kb
Host smart-f73cd4ad-9206-48e9-95ba-4b1078df1cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734549844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1734549844
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3897649920
Short name T379
Test name
Test status
Simulation time 482109978 ps
CPU time 9.69 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:09 PM PDT 24
Peak memory 217688 kb
Host smart-ff2e2a49-3fa8-4f62-b284-b477c8a4419a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897649920 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3897649920
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1484214491
Short name T331
Test name
Test status
Simulation time 250490991 ps
CPU time 10.17 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:09 PM PDT 24
Peak memory 210996 kb
Host smart-bc8442dd-1ea5-4f2c-af21-b32bace777df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484214491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1484214491
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2921558233
Short name T393
Test name
Test status
Simulation time 1373341502 ps
CPU time 9.89 seconds
Started Jul 30 05:28:57 PM PDT 24
Finished Jul 30 05:29:07 PM PDT 24
Peak memory 211756 kb
Host smart-e0001d74-7642-4fd9-996d-1b481ecb2b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921558233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2921558233
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2504001863
Short name T344
Test name
Test status
Simulation time 169073944 ps
CPU time 12.92 seconds
Started Jul 30 05:28:58 PM PDT 24
Finished Jul 30 05:29:11 PM PDT 24
Peak memory 219072 kb
Host smart-c3f5f2d6-ab5d-4fd7-82c3-731601e9cae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504001863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2504001863
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1218393347
Short name T53
Test name
Test status
Simulation time 1227368742 ps
CPU time 84.63 seconds
Started Jul 30 05:29:01 PM PDT 24
Finished Jul 30 05:30:26 PM PDT 24
Peak memory 214228 kb
Host smart-67014083-280c-4fe1-81b5-934bbeccf84e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218393347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1218393347
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2210627941
Short name T359
Test name
Test status
Simulation time 3140184876 ps
CPU time 9.98 seconds
Started Jul 30 05:29:04 PM PDT 24
Finished Jul 30 05:29:14 PM PDT 24
Peak memory 213708 kb
Host smart-11b736d0-57f6-4748-878c-8069e7de7310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210627941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2210627941
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2318855290
Short name T367
Test name
Test status
Simulation time 386836384 ps
CPU time 8.15 seconds
Started Jul 30 05:29:00 PM PDT 24
Finished Jul 30 05:29:08 PM PDT 24
Peak memory 211384 kb
Host smart-1a3129a5-407d-4c33-8901-4f37ddba08ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318855290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2318855290
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2188127819
Short name T62
Test name
Test status
Simulation time 2052797672 ps
CPU time 15.08 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:14 PM PDT 24
Peak memory 211616 kb
Host smart-d4de77db-735f-4985-b96c-cdcd2899c5a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188127819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2188127819
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1416335921
Short name T398
Test name
Test status
Simulation time 338903371 ps
CPU time 12.96 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:29:12 PM PDT 24
Peak memory 219204 kb
Host smart-0baea277-fe31-4935-8609-0170815e91a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416335921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1416335921
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3353931698
Short name T92
Test name
Test status
Simulation time 642754190 ps
CPU time 81.3 seconds
Started Jul 30 05:28:59 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 212812 kb
Host smart-b6b75008-bbd3-40b4-8c04-ce403c840611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353931698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3353931698
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2870125385
Short name T377
Test name
Test status
Simulation time 735420795 ps
CPU time 8.74 seconds
Started Jul 30 05:29:07 PM PDT 24
Finished Jul 30 05:29:16 PM PDT 24
Peak memory 216008 kb
Host smart-99326512-ced2-496b-825f-e58f5ac463a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870125385 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2870125385
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1284655954
Short name T386
Test name
Test status
Simulation time 517526492 ps
CPU time 9.76 seconds
Started Jul 30 05:29:00 PM PDT 24
Finished Jul 30 05:29:10 PM PDT 24
Peak memory 211020 kb
Host smart-4e4fde2f-d9f8-457f-8459-58e75879599c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284655954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1284655954
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3331721007
Short name T371
Test name
Test status
Simulation time 255045829 ps
CPU time 9.99 seconds
Started Jul 30 05:29:02 PM PDT 24
Finished Jul 30 05:29:12 PM PDT 24
Peak memory 211604 kb
Host smart-1a8f7e91-f8c1-4b83-b4c1-6a0d329ebbcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331721007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3331721007
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4219236713
Short name T333
Test name
Test status
Simulation time 995773802 ps
CPU time 13.04 seconds
Started Jul 30 05:29:04 PM PDT 24
Finished Jul 30 05:29:17 PM PDT 24
Peak memory 217232 kb
Host smart-ec7d0367-0332-4aa4-a1c0-e605f0061f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219236713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4219236713
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3550688984
Short name T341
Test name
Test status
Simulation time 2007482476 ps
CPU time 11.26 seconds
Started Jul 30 05:29:07 PM PDT 24
Finished Jul 30 05:29:18 PM PDT 24
Peak memory 218144 kb
Host smart-c03c9eb6-cbc4-4883-9d42-158798709a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550688984 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3550688984
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.459030672
Short name T399
Test name
Test status
Simulation time 383292832 ps
CPU time 9.85 seconds
Started Jul 30 05:29:09 PM PDT 24
Finished Jul 30 05:29:19 PM PDT 24
Peak memory 211020 kb
Host smart-24b57a9f-f34f-4ec3-aa8b-4ad6a8dcdc46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459030672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.459030672
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3224328208
Short name T387
Test name
Test status
Simulation time 174463869 ps
CPU time 8.43 seconds
Started Jul 30 05:29:08 PM PDT 24
Finished Jul 30 05:29:16 PM PDT 24
Peak memory 211516 kb
Host smart-ccdbf34b-803e-4eab-9331-b3674761d8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224328208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3224328208
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1983408118
Short name T373
Test name
Test status
Simulation time 1652297226 ps
CPU time 13.16 seconds
Started Jul 30 05:29:08 PM PDT 24
Finished Jul 30 05:29:21 PM PDT 24
Peak memory 217388 kb
Host smart-4c141c9f-3f6a-42a0-b486-3eb3416d91c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983408118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1983408118
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2105685156
Short name T368
Test name
Test status
Simulation time 323454207 ps
CPU time 80.52 seconds
Started Jul 30 05:29:04 PM PDT 24
Finished Jul 30 05:30:25 PM PDT 24
Peak memory 213760 kb
Host smart-d6e9df0b-a7d3-4f49-be18-792d474bd57d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105685156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2105685156
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2347920700
Short name T372
Test name
Test status
Simulation time 184548660 ps
CPU time 9.2 seconds
Started Jul 30 05:29:10 PM PDT 24
Finished Jul 30 05:29:19 PM PDT 24
Peak memory 218088 kb
Host smart-ed8780c1-08a9-48c8-b209-04a68c363342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347920700 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2347920700
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3170954737
Short name T55
Test name
Test status
Simulation time 346305343 ps
CPU time 8.04 seconds
Started Jul 30 05:29:09 PM PDT 24
Finished Jul 30 05:29:18 PM PDT 24
Peak memory 211116 kb
Host smart-b9075c3d-467f-497e-aacf-241308e12867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170954737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3170954737
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3852192066
Short name T81
Test name
Test status
Simulation time 983790498 ps
CPU time 9.79 seconds
Started Jul 30 05:29:06 PM PDT 24
Finished Jul 30 05:29:16 PM PDT 24
Peak memory 211960 kb
Host smart-76a1056e-7cc6-4f58-9b87-814c314275e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852192066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3852192066
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1486031233
Short name T385
Test name
Test status
Simulation time 178173032 ps
CPU time 13.28 seconds
Started Jul 30 05:29:07 PM PDT 24
Finished Jul 30 05:29:20 PM PDT 24
Peak memory 217764 kb
Host smart-81ec51b3-8755-4a07-966a-a83befa0f503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486031233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1486031233
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1242321209
Short name T406
Test name
Test status
Simulation time 944456469 ps
CPU time 10.53 seconds
Started Jul 30 05:29:10 PM PDT 24
Finished Jul 30 05:29:20 PM PDT 24
Peak memory 216552 kb
Host smart-0e0fae38-5865-4d44-9711-c040d4c0f6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242321209 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1242321209
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3625609969
Short name T65
Test name
Test status
Simulation time 168548406 ps
CPU time 8.42 seconds
Started Jul 30 05:29:09 PM PDT 24
Finished Jul 30 05:29:17 PM PDT 24
Peak memory 211336 kb
Host smart-94ca290c-7d42-4961-acb9-df1f0cd0da37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625609969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3625609969
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2347603788
Short name T348
Test name
Test status
Simulation time 919854879 ps
CPU time 8.22 seconds
Started Jul 30 05:29:10 PM PDT 24
Finished Jul 30 05:29:19 PM PDT 24
Peak memory 211324 kb
Host smart-fa554882-6c8f-4981-b6b3-1194f87832dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347603788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2347603788
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2987137416
Short name T340
Test name
Test status
Simulation time 251676972 ps
CPU time 14.67 seconds
Started Jul 30 05:29:10 PM PDT 24
Finished Jul 30 05:29:24 PM PDT 24
Peak memory 217820 kb
Host smart-49f2544a-12f7-4de8-99c8-458767b967d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987137416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2987137416
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3024037111
Short name T336
Test name
Test status
Simulation time 1183002303 ps
CPU time 9.24 seconds
Started Jul 30 05:29:15 PM PDT 24
Finished Jul 30 05:29:25 PM PDT 24
Peak memory 216916 kb
Host smart-1bafc3a3-54f9-41fb-a28a-2581aca01597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024037111 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3024037111
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.829346436
Short name T360
Test name
Test status
Simulation time 250531885 ps
CPU time 10.13 seconds
Started Jul 30 05:29:14 PM PDT 24
Finished Jul 30 05:29:24 PM PDT 24
Peak memory 210988 kb
Host smart-258e59fc-37ad-4632-9270-520c80d1f0cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829346436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.829346436
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3187061181
Short name T376
Test name
Test status
Simulation time 167801145 ps
CPU time 7.78 seconds
Started Jul 30 05:29:16 PM PDT 24
Finished Jul 30 05:29:23 PM PDT 24
Peak memory 211412 kb
Host smart-f48e996b-f5b1-47e2-a8e9-c6e3922b29ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187061181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3187061181
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.710527011
Short name T384
Test name
Test status
Simulation time 168221493 ps
CPU time 13.48 seconds
Started Jul 30 05:29:14 PM PDT 24
Finished Jul 30 05:29:28 PM PDT 24
Peak memory 219352 kb
Host smart-4686e311-2937-4699-b649-5c4e13aca423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710527011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.710527011
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.702730
Short name T343
Test name
Test status
Simulation time 915670233 ps
CPU time 9.84 seconds
Started Jul 30 05:28:31 PM PDT 24
Finished Jul 30 05:28:41 PM PDT 24
Peak memory 211084 kb
Host smart-0ac5a382-d8e3-4c46-9f40-dff0c6cd979a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.702730
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.779438442
Short name T388
Test name
Test status
Simulation time 992662737 ps
CPU time 10.42 seconds
Started Jul 30 05:28:29 PM PDT 24
Finished Jul 30 05:28:40 PM PDT 24
Peak memory 210996 kb
Host smart-cb9eb037-06db-432b-843e-6e02c7054eab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779438442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.779438442
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1329751575
Short name T396
Test name
Test status
Simulation time 527665658 ps
CPU time 17.69 seconds
Started Jul 30 05:28:30 PM PDT 24
Finished Jul 30 05:28:48 PM PDT 24
Peak memory 212420 kb
Host smart-081801ab-22af-48fb-8298-47c41238c9f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329751575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1329751575
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2613479345
Short name T327
Test name
Test status
Simulation time 1038931128 ps
CPU time 11.2 seconds
Started Jul 30 05:28:29 PM PDT 24
Finished Jul 30 05:28:40 PM PDT 24
Peak memory 217652 kb
Host smart-b48fb9d7-0e08-4985-8737-8b393fd29861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613479345 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2613479345
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.135182049
Short name T76
Test name
Test status
Simulation time 534588121 ps
CPU time 8.16 seconds
Started Jul 30 05:28:33 PM PDT 24
Finished Jul 30 05:28:41 PM PDT 24
Peak memory 211260 kb
Host smart-c534fda2-5f0b-4021-a51f-a46ff7a7db41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135182049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.135182049
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.539736802
Short name T357
Test name
Test status
Simulation time 1098486961 ps
CPU time 8.05 seconds
Started Jul 30 05:28:26 PM PDT 24
Finished Jul 30 05:28:34 PM PDT 24
Peak memory 210780 kb
Host smart-87f53299-ae81-4d54-b397-cc2a604c18de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539736802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.539736802
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3503917429
Short name T397
Test name
Test status
Simulation time 196585162 ps
CPU time 8.19 seconds
Started Jul 30 05:28:26 PM PDT 24
Finished Jul 30 05:28:35 PM PDT 24
Peak memory 210972 kb
Host smart-f4f5d2d1-18ec-4b6a-a999-e49608b2aff1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503917429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3503917429
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1669233365
Short name T408
Test name
Test status
Simulation time 170033516 ps
CPU time 8.41 seconds
Started Jul 30 05:28:30 PM PDT 24
Finished Jul 30 05:28:39 PM PDT 24
Peak memory 211364 kb
Host smart-aede962e-9e1c-446d-a832-e2f1d158bb1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669233365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1669233365
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2555037941
Short name T405
Test name
Test status
Simulation time 1550414658 ps
CPU time 12.79 seconds
Started Jul 30 05:28:32 PM PDT 24
Finished Jul 30 05:28:45 PM PDT 24
Peak memory 217708 kb
Host smart-b0b09238-50b1-4b29-9eb4-a5a11dc456d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555037941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2555037941
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.778990402
Short name T100
Test name
Test status
Simulation time 1176632721 ps
CPU time 83.04 seconds
Started Jul 30 05:28:32 PM PDT 24
Finished Jul 30 05:29:56 PM PDT 24
Peak memory 213948 kb
Host smart-1e2d1061-e144-4e06-9384-eb1855290326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778990402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.778990402
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1435931911
Short name T60
Test name
Test status
Simulation time 209954846 ps
CPU time 8.52 seconds
Started Jul 30 05:28:37 PM PDT 24
Finished Jul 30 05:28:46 PM PDT 24
Peak memory 211100 kb
Host smart-26fcb855-6241-4dff-98f7-d21e6b454337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435931911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1435931911
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2143927048
Short name T347
Test name
Test status
Simulation time 2060482919 ps
CPU time 8.48 seconds
Started Jul 30 05:28:34 PM PDT 24
Finished Jul 30 05:28:42 PM PDT 24
Peak memory 210896 kb
Host smart-26166ae1-3fbd-4fdd-a9ad-28f3c551fa81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143927048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2143927048
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4112247605
Short name T346
Test name
Test status
Simulation time 1928150828 ps
CPU time 17.2 seconds
Started Jul 30 05:28:34 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 212312 kb
Host smart-1c95d020-54a6-4b36-84a3-b909419b6173
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112247605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4112247605
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.45663698
Short name T326
Test name
Test status
Simulation time 509492583 ps
CPU time 10.1 seconds
Started Jul 30 05:28:37 PM PDT 24
Finished Jul 30 05:28:47 PM PDT 24
Peak memory 214960 kb
Host smart-46db5da8-e67c-4c49-aa5f-d1cb39d040d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45663698 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.45663698
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3840322064
Short name T409
Test name
Test status
Simulation time 332818634 ps
CPU time 8.2 seconds
Started Jul 30 05:28:36 PM PDT 24
Finished Jul 30 05:28:44 PM PDT 24
Peak memory 211372 kb
Host smart-e0bda104-4003-4f1d-858d-73f159983691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840322064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3840322064
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3747987006
Short name T323
Test name
Test status
Simulation time 253231731 ps
CPU time 9.76 seconds
Started Jul 30 05:28:35 PM PDT 24
Finished Jul 30 05:28:45 PM PDT 24
Peak memory 210804 kb
Host smart-723e8ebf-50b6-4f2d-9b91-65f63a66e8bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747987006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3747987006
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2569067264
Short name T353
Test name
Test status
Simulation time 921963040 ps
CPU time 8.08 seconds
Started Jul 30 05:28:34 PM PDT 24
Finished Jul 30 05:28:42 PM PDT 24
Peak memory 210836 kb
Host smart-1e9c4001-2409-4b4b-a1b4-c8924bf67178
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569067264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2569067264
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.784642736
Short name T401
Test name
Test status
Simulation time 173301959 ps
CPU time 8.23 seconds
Started Jul 30 05:28:38 PM PDT 24
Finished Jul 30 05:28:46 PM PDT 24
Peak memory 211612 kb
Host smart-7da06b11-7c5e-4fce-ac29-136eb19afb16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784642736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.784642736
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.981048698
Short name T325
Test name
Test status
Simulation time 661449806 ps
CPU time 12.16 seconds
Started Jul 30 05:28:34 PM PDT 24
Finished Jul 30 05:28:46 PM PDT 24
Peak memory 219220 kb
Host smart-b14f1173-b664-4da2-b6dc-288cc42e35c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981048698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.981048698
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2295282689
Short name T101
Test name
Test status
Simulation time 4414270112 ps
CPU time 170.67 seconds
Started Jul 30 05:28:34 PM PDT 24
Finished Jul 30 05:31:25 PM PDT 24
Peak memory 215136 kb
Host smart-79e495a7-89fc-47b3-b687-8136b17209a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295282689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2295282689
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.610625789
Short name T61
Test name
Test status
Simulation time 514811893 ps
CPU time 10.19 seconds
Started Jul 30 05:28:37 PM PDT 24
Finished Jul 30 05:28:47 PM PDT 24
Peak memory 211108 kb
Host smart-944dc47e-245d-4adf-affc-2c243c5e975c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610625789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.610625789
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3754053753
Short name T404
Test name
Test status
Simulation time 313371879 ps
CPU time 8.29 seconds
Started Jul 30 05:28:41 PM PDT 24
Finished Jul 30 05:28:49 PM PDT 24
Peak memory 210968 kb
Host smart-c7b57f22-9a5c-461c-a4c1-3225fbb4dbdd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754053753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3754053753
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.483883040
Short name T390
Test name
Test status
Simulation time 1383060504 ps
CPU time 11.81 seconds
Started Jul 30 05:28:40 PM PDT 24
Finished Jul 30 05:28:52 PM PDT 24
Peak memory 210944 kb
Host smart-a9863893-e195-4469-a7e7-e6c3ebadb367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483883040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.483883040
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.231864588
Short name T335
Test name
Test status
Simulation time 766744777 ps
CPU time 10.49 seconds
Started Jul 30 05:28:37 PM PDT 24
Finished Jul 30 05:28:47 PM PDT 24
Peak memory 216936 kb
Host smart-5d065359-6518-4001-bfc2-c229c7c7f780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231864588 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.231864588
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2723949515
Short name T392
Test name
Test status
Simulation time 1027661574 ps
CPU time 9.94 seconds
Started Jul 30 05:28:36 PM PDT 24
Finished Jul 30 05:28:46 PM PDT 24
Peak memory 211412 kb
Host smart-254df864-885c-411f-9c03-e9fa2cbfbc69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723949515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2723949515
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1213595694
Short name T324
Test name
Test status
Simulation time 1129023804 ps
CPU time 9.69 seconds
Started Jul 30 05:28:37 PM PDT 24
Finished Jul 30 05:28:47 PM PDT 24
Peak memory 210824 kb
Host smart-75c53275-2a1a-4102-a1aa-5bd4b52765d8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213595694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1213595694
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3334055585
Short name T395
Test name
Test status
Simulation time 383102169 ps
CPU time 9.77 seconds
Started Jul 30 05:28:38 PM PDT 24
Finished Jul 30 05:28:48 PM PDT 24
Peak memory 210840 kb
Host smart-6ce1c6fc-a098-4f53-9e0e-2cdc55d114bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334055585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3334055585
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.934316687
Short name T365
Test name
Test status
Simulation time 261277033 ps
CPU time 9.95 seconds
Started Jul 30 05:28:36 PM PDT 24
Finished Jul 30 05:28:46 PM PDT 24
Peak memory 211124 kb
Host smart-3d08d993-50bd-4db5-9f5c-968c4a8fac51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934316687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.934316687
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2079875297
Short name T350
Test name
Test status
Simulation time 249739185 ps
CPU time 14.57 seconds
Started Jul 30 05:28:41 PM PDT 24
Finished Jul 30 05:28:56 PM PDT 24
Peak memory 217820 kb
Host smart-2ab44edf-f309-4eac-9e9f-dbd0b9848664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079875297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2079875297
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2141230410
Short name T339
Test name
Test status
Simulation time 269578339 ps
CPU time 10.62 seconds
Started Jul 30 05:28:40 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 217184 kb
Host smart-b6488818-815f-4422-8ea8-d8ed136fe121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141230410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2141230410
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1780937180
Short name T56
Test name
Test status
Simulation time 174654720 ps
CPU time 8.1 seconds
Started Jul 30 05:28:40 PM PDT 24
Finished Jul 30 05:28:48 PM PDT 24
Peak memory 211152 kb
Host smart-f7cd89da-76dc-40bc-bbdf-7910abf57957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780937180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1780937180
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2294528827
Short name T370
Test name
Test status
Simulation time 542122911 ps
CPU time 9.9 seconds
Started Jul 30 05:28:44 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 211288 kb
Host smart-43b4f0cc-095b-4ae2-83ec-d13094138dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294528827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2294528827
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2687642425
Short name T330
Test name
Test status
Simulation time 661626166 ps
CPU time 12.01 seconds
Started Jul 30 05:28:38 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 217912 kb
Host smart-f1c132f5-fc26-46d5-9ed5-fe11ca95e264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687642425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2687642425
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.911788198
Short name T52
Test name
Test status
Simulation time 335706249 ps
CPU time 80.38 seconds
Started Jul 30 05:28:42 PM PDT 24
Finished Jul 30 05:30:02 PM PDT 24
Peak memory 213012 kb
Host smart-0626e96f-c11a-4185-aeef-b8704aa7b6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911788198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.911788198
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1921140859
Short name T349
Test name
Test status
Simulation time 177375302 ps
CPU time 8.69 seconds
Started Jul 30 05:28:46 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 216240 kb
Host smart-d74ec241-64dc-4755-81eb-9f6a2de6bf18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921140859 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1921140859
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.959537938
Short name T391
Test name
Test status
Simulation time 1460200784 ps
CPU time 10.17 seconds
Started Jul 30 05:28:42 PM PDT 24
Finished Jul 30 05:28:52 PM PDT 24
Peak memory 211116 kb
Host smart-1e9fb1ad-28e9-4631-9e39-43dbd048f1e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959537938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.959537938
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.840603631
Short name T80
Test name
Test status
Simulation time 720046824 ps
CPU time 8.54 seconds
Started Jul 30 05:28:46 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 211496 kb
Host smart-125e3bf8-8145-4b3b-b929-2ae8398dc521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840603631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.840603631
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.562069870
Short name T337
Test name
Test status
Simulation time 2352000386 ps
CPU time 10.93 seconds
Started Jul 30 05:28:40 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 217736 kb
Host smart-a5562973-f6a0-419e-a789-0a49f6be03cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562069870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.562069870
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2233749901
Short name T91
Test name
Test status
Simulation time 339757511 ps
CPU time 79.96 seconds
Started Jul 30 05:28:43 PM PDT 24
Finished Jul 30 05:30:03 PM PDT 24
Peak memory 213188 kb
Host smart-11f9c73b-3a67-4add-b054-feb6a37dd004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233749901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2233749901
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1200861061
Short name T338
Test name
Test status
Simulation time 701050493 ps
CPU time 7.99 seconds
Started Jul 30 05:28:46 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 215524 kb
Host smart-7bb0152a-9ea3-4b10-a12f-30b75ad768a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200861061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1200861061
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3010319525
Short name T381
Test name
Test status
Simulation time 689846248 ps
CPU time 7.94 seconds
Started Jul 30 05:28:47 PM PDT 24
Finished Jul 30 05:28:55 PM PDT 24
Peak memory 211364 kb
Host smart-d6959dc7-a3bc-438f-9251-6851bc81a920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010319525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3010319525
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.646152381
Short name T82
Test name
Test status
Simulation time 4085615515 ps
CPU time 14.58 seconds
Started Jul 30 05:28:45 PM PDT 24
Finished Jul 30 05:29:00 PM PDT 24
Peak memory 211712 kb
Host smart-212bcdd1-fc86-471d-b8df-1981768893fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646152381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.646152381
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3242939548
Short name T375
Test name
Test status
Simulation time 259850907 ps
CPU time 15.49 seconds
Started Jul 30 05:28:44 PM PDT 24
Finished Jul 30 05:29:00 PM PDT 24
Peak memory 219092 kb
Host smart-404a97bf-0d72-4a2f-bbc2-fcddaf85de18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242939548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3242939548
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1072148442
Short name T402
Test name
Test status
Simulation time 1273070704 ps
CPU time 82.07 seconds
Started Jul 30 05:28:46 PM PDT 24
Finished Jul 30 05:30:08 PM PDT 24
Peak memory 213048 kb
Host smart-cf2c4b97-fa45-4059-ba43-cef0afc69161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072148442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1072148442
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2926136055
Short name T382
Test name
Test status
Simulation time 189067909 ps
CPU time 9.56 seconds
Started Jul 30 05:28:45 PM PDT 24
Finished Jul 30 05:28:55 PM PDT 24
Peak memory 217492 kb
Host smart-c56073cf-3532-490d-b3d2-2b882dfb7ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926136055 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2926136055
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.746437535
Short name T352
Test name
Test status
Simulation time 167483472 ps
CPU time 8.13 seconds
Started Jul 30 05:28:49 PM PDT 24
Finished Jul 30 05:28:58 PM PDT 24
Peak memory 210800 kb
Host smart-5415abd7-c488-4008-8779-af0ecf069906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746437535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.746437535
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3091226050
Short name T66
Test name
Test status
Simulation time 192953773 ps
CPU time 8.58 seconds
Started Jul 30 05:28:46 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 211560 kb
Host smart-e9b2e0bb-dbc9-40bc-9729-9e2d957c7d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091226050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3091226050
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3307392508
Short name T378
Test name
Test status
Simulation time 268832575 ps
CPU time 15.1 seconds
Started Jul 30 05:28:47 PM PDT 24
Finished Jul 30 05:29:03 PM PDT 24
Peak memory 219120 kb
Host smart-7cfb4687-51ed-47d2-b0c4-6aa0fd1972e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307392508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3307392508
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2464686001
Short name T94
Test name
Test status
Simulation time 923923939 ps
CPU time 82.48 seconds
Started Jul 30 05:28:45 PM PDT 24
Finished Jul 30 05:30:07 PM PDT 24
Peak memory 214032 kb
Host smart-60df3f0e-f0d2-41bc-9559-ff398fc5285f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464686001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2464686001
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1926645607
Short name T374
Test name
Test status
Simulation time 1054385914 ps
CPU time 10.46 seconds
Started Jul 30 05:28:48 PM PDT 24
Finished Jul 30 05:28:58 PM PDT 24
Peak memory 217540 kb
Host smart-64b6f515-5fb4-4481-b018-dc7ea44b8e34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926645607 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1926645607
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4279970487
Short name T79
Test name
Test status
Simulation time 262086089 ps
CPU time 14.28 seconds
Started Jul 30 05:28:49 PM PDT 24
Finished Jul 30 05:29:03 PM PDT 24
Peak memory 212756 kb
Host smart-c3bfa8e5-3c10-45a4-a8e8-63e5e32c3923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279970487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4279970487
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.647269570
Short name T407
Test name
Test status
Simulation time 260451123 ps
CPU time 12.42 seconds
Started Jul 30 05:28:53 PM PDT 24
Finished Jul 30 05:29:06 PM PDT 24
Peak memory 217508 kb
Host smart-ad5b3386-d0aa-42be-8412-82e5cc77980d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647269570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.647269570
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1710072655
Short name T102
Test name
Test status
Simulation time 1489170445 ps
CPU time 153 seconds
Started Jul 30 05:28:52 PM PDT 24
Finished Jul 30 05:31:25 PM PDT 24
Peak memory 214472 kb
Host smart-626a5008-74c9-40f7-a382-4ef04d3c74c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710072655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1710072655
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3087132910
Short name T119
Test name
Test status
Simulation time 993355186 ps
CPU time 10.22 seconds
Started Jul 30 05:26:55 PM PDT 24
Finished Jul 30 05:27:05 PM PDT 24
Peak memory 219248 kb
Host smart-7179cc86-641d-4a1a-ba9c-1940dd86a512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087132910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3087132910
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3910466375
Short name T146
Test name
Test status
Simulation time 6121044560 ps
CPU time 140.75 seconds
Started Jul 30 05:26:50 PM PDT 24
Finished Jul 30 05:29:11 PM PDT 24
Peak memory 242664 kb
Host smart-6f4646b2-9ba2-46e2-91a1-1dfff0372fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910466375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3910466375
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3793157167
Short name T243
Test name
Test status
Simulation time 518538208 ps
CPU time 22.81 seconds
Started Jul 30 05:26:51 PM PDT 24
Finished Jul 30 05:27:14 PM PDT 24
Peak memory 220052 kb
Host smart-81c7ab83-7067-4b88-bd29-708414b2f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793157167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3793157167
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2905997457
Short name T89
Test name
Test status
Simulation time 1123117021 ps
CPU time 12.65 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:27:10 PM PDT 24
Peak memory 220152 kb
Host smart-5689018a-0a93-46c7-adf7-daa45bffe9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905997457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2905997457
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.420230330
Short name T25
Test name
Test status
Simulation time 732025773 ps
CPU time 225.04 seconds
Started Jul 30 05:26:50 PM PDT 24
Finished Jul 30 05:30:35 PM PDT 24
Peak memory 235664 kb
Host smart-de736a39-fb08-406f-bad6-dd3d55b984f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420230330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.420230330
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2847169437
Short name T201
Test name
Test status
Simulation time 2835484389 ps
CPU time 10.48 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:27:08 PM PDT 24
Peak memory 220216 kb
Host smart-de79ea23-fffc-429c-80da-b487c7e1028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847169437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2847169437
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1305317990
Short name T68
Test name
Test status
Simulation time 2081814589 ps
CPU time 37.02 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:27:30 PM PDT 24
Peak memory 219984 kb
Host smart-55f55f94-5ca8-400c-802b-36f882ded9b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305317990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1305317990
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3137739624
Short name T282
Test name
Test status
Simulation time 451230846267 ps
CPU time 4320.93 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 06:38:56 PM PDT 24
Peak memory 250816 kb
Host smart-d4e31063-d9d1-4286-8501-a6ca2acbd8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137739624 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3137739624
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.285698750
Short name T311
Test name
Test status
Simulation time 1031463443 ps
CPU time 10.58 seconds
Started Jul 30 05:26:59 PM PDT 24
Finished Jul 30 05:27:09 PM PDT 24
Peak memory 219188 kb
Host smart-129a4c0a-153d-4383-bf64-abb6e59b3347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285698750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.285698750
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3149054317
Short name T30
Test name
Test status
Simulation time 12481474315 ps
CPU time 108.73 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:28:47 PM PDT 24
Peak memory 225768 kb
Host smart-8f320403-c00c-4135-b1c7-35d66a65d013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149054317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3149054317
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1624676975
Short name T199
Test name
Test status
Simulation time 1380799165 ps
CPU time 19.61 seconds
Started Jul 30 05:26:49 PM PDT 24
Finished Jul 30 05:27:09 PM PDT 24
Peak memory 220112 kb
Host smart-db0d7d66-d2a2-4a60-b360-a6e4ee626dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624676975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1624676975
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3729398897
Short name T256
Test name
Test status
Simulation time 245934194 ps
CPU time 10.43 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:04 PM PDT 24
Peak memory 220016 kb
Host smart-0e8c5257-a607-4c8c-a69b-c416d520472d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729398897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3729398897
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3795186870
Short name T24
Test name
Test status
Simulation time 603602323 ps
CPU time 225.88 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:30:43 PM PDT 24
Peak memory 238776 kb
Host smart-8628692f-7579-46fd-b594-74cfbb755cda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795186870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3795186870
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.566290851
Short name T232
Test name
Test status
Simulation time 182424353 ps
CPU time 9.97 seconds
Started Jul 30 05:26:48 PM PDT 24
Finished Jul 30 05:26:58 PM PDT 24
Peak memory 220028 kb
Host smart-05956948-ace4-4035-8a00-b43c12354926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566290851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.566290851
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1880934670
Short name T298
Test name
Test status
Simulation time 1039159150 ps
CPU time 48.16 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:27:46 PM PDT 24
Peak memory 220064 kb
Host smart-9a80d4cb-0ce6-4c98-80d3-652a00bf99c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880934670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1880934670
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1454987474
Short name T219
Test name
Test status
Simulation time 1036659588 ps
CPU time 10.24 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:15 PM PDT 24
Peak memory 219188 kb
Host smart-1e9a7a3f-7a97-46c7-b4be-99de9048f8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454987474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1454987474
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1295520764
Short name T259
Test name
Test status
Simulation time 3883911833 ps
CPU time 214.83 seconds
Started Jul 30 05:27:04 PM PDT 24
Finished Jul 30 05:30:39 PM PDT 24
Peak memory 239372 kb
Host smart-58aeadf4-c295-48ac-b1c4-7c7441b50b3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295520764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1295520764
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3695991741
Short name T23
Test name
Test status
Simulation time 344422262 ps
CPU time 19.67 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 220008 kb
Host smart-a5407a16-88bf-4a6c-b947-49d55385e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695991741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3695991741
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.623461123
Short name T320
Test name
Test status
Simulation time 362798894 ps
CPU time 24.21 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:26 PM PDT 24
Peak memory 220028 kb
Host smart-57556fc2-31b8-4b1d-8e32-9fcafa6f6da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623461123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.623461123
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1672448919
Short name T35
Test name
Test status
Simulation time 459575294 ps
CPU time 8.4 seconds
Started Jul 30 05:27:08 PM PDT 24
Finished Jul 30 05:27:17 PM PDT 24
Peak memory 219092 kb
Host smart-78f6d80d-4138-4c10-ba22-f5601d946aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672448919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1672448919
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.970603477
Short name T313
Test name
Test status
Simulation time 5032577144 ps
CPU time 174.22 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:30:05 PM PDT 24
Peak memory 233060 kb
Host smart-0c6eb080-6985-4a62-9a79-fa2ce9faa581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970603477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.970603477
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4200663085
Short name T22
Test name
Test status
Simulation time 1222515883 ps
CPU time 19.57 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 220240 kb
Host smart-04d4184d-a93d-4b4b-a67a-e1dc0f18bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200663085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4200663085
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.473538302
Short name T140
Test name
Test status
Simulation time 915190558 ps
CPU time 12.24 seconds
Started Jul 30 05:27:08 PM PDT 24
Finished Jul 30 05:27:21 PM PDT 24
Peak memory 220088 kb
Host smart-ab10f0a9-88da-4d4b-afc0-b192fbadaa12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473538302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.473538302
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.166541620
Short name T180
Test name
Test status
Simulation time 291657771 ps
CPU time 23.38 seconds
Started Jul 30 05:27:07 PM PDT 24
Finished Jul 30 05:27:31 PM PDT 24
Peak memory 219936 kb
Host smart-58a23e6f-a284-4903-83ef-9a954d54d298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166541620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.166541620
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4234554376
Short name T226
Test name
Test status
Simulation time 167367443 ps
CPU time 8.43 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:13 PM PDT 24
Peak memory 219060 kb
Host smart-f4c6ab60-87ea-4fbd-ba91-78183c6019d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234554376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4234554376
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3680943848
Short name T249
Test name
Test status
Simulation time 18237126780 ps
CPU time 326.57 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:32:32 PM PDT 24
Peak memory 237960 kb
Host smart-cd7eab38-764b-4515-9048-a409ff0a2842
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680943848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3680943848
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3155331363
Short name T163
Test name
Test status
Simulation time 897893541 ps
CPU time 23.01 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 220120 kb
Host smart-e0259ebe-4524-4e49-a99c-5ec96febfdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155331363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3155331363
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1054004531
Short name T253
Test name
Test status
Simulation time 1329902702 ps
CPU time 10.11 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:16 PM PDT 24
Peak memory 220048 kb
Host smart-78f250b2-3195-471b-8b21-6bd8b65005c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054004531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1054004531
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1593488533
Short name T149
Test name
Test status
Simulation time 380195427 ps
CPU time 20.26 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:27 PM PDT 24
Peak memory 219984 kb
Host smart-f69dc7a0-a4da-41fe-8636-72b5cc4a68a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593488533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1593488533
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.307681934
Short name T126
Test name
Test status
Simulation time 172882229 ps
CPU time 8.28 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:14 PM PDT 24
Peak memory 219052 kb
Host smart-c1697071-9284-4afe-aee7-90031ef7d512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307681934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.307681934
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.362224330
Short name T156
Test name
Test status
Simulation time 32177010567 ps
CPU time 388.05 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:33:33 PM PDT 24
Peak memory 235564 kb
Host smart-e6dea821-feca-4be7-b963-93a390cdf757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362224330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.362224330
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4218636274
Short name T179
Test name
Test status
Simulation time 553659643 ps
CPU time 22.24 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:28 PM PDT 24
Peak memory 220072 kb
Host smart-56d15251-661f-4d2f-a0cd-b92aaabc7ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218636274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4218636274
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.440185651
Short name T228
Test name
Test status
Simulation time 185877660 ps
CPU time 10.94 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:17 PM PDT 24
Peak memory 220072 kb
Host smart-03a242eb-3c1c-440c-b1e2-62a9600b0adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440185651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.440185651
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2407264438
Short name T233
Test name
Test status
Simulation time 484029761 ps
CPU time 27.63 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 220100 kb
Host smart-0d92166b-38f5-416b-b9e9-123151bc64f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407264438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2407264438
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1525249740
Short name T7
Test name
Test status
Simulation time 168632513 ps
CPU time 8.51 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:27:19 PM PDT 24
Peak memory 219216 kb
Host smart-66561936-96c6-490b-8beb-c4bb385e1066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525249740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1525249740
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.301634268
Short name T195
Test name
Test status
Simulation time 496020035 ps
CPU time 22.27 seconds
Started Jul 30 05:27:11 PM PDT 24
Finished Jul 30 05:27:33 PM PDT 24
Peak memory 220108 kb
Host smart-00369c86-9dec-4198-b604-55c86cba50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301634268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.301634268
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1709225215
Short name T123
Test name
Test status
Simulation time 358537911 ps
CPU time 10.49 seconds
Started Jul 30 05:27:06 PM PDT 24
Finished Jul 30 05:27:17 PM PDT 24
Peak memory 220032 kb
Host smart-0286ef3b-437f-4ef5-8b05-af1701441353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709225215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1709225215
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.932782025
Short name T69
Test name
Test status
Simulation time 1068237063 ps
CPU time 27.03 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:33 PM PDT 24
Peak memory 219924 kb
Host smart-0810cbbd-7828-4fc2-b5e4-17c9178b30c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932782025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.932782025
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4240711956
Short name T278
Test name
Test status
Simulation time 167373251 ps
CPU time 8.25 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 219168 kb
Host smart-1ed71292-9e50-4aa0-b8b6-b6912da59129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240711956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4240711956
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2735632520
Short name T213
Test name
Test status
Simulation time 12945933606 ps
CPU time 214.93 seconds
Started Jul 30 05:27:12 PM PDT 24
Finished Jul 30 05:30:47 PM PDT 24
Peak memory 240812 kb
Host smart-2baf4b88-244a-43be-83b0-7944b83a60ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735632520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2735632520
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.956347476
Short name T2
Test name
Test status
Simulation time 332243456 ps
CPU time 19.04 seconds
Started Jul 30 05:27:09 PM PDT 24
Finished Jul 30 05:27:28 PM PDT 24
Peak memory 220060 kb
Host smart-4a018bce-789c-4f71-bde7-c3c418ae9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956347476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.956347476
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3252040060
Short name T288
Test name
Test status
Simulation time 269769822 ps
CPU time 12.32 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:27:22 PM PDT 24
Peak memory 220116 kb
Host smart-11874c4d-4989-4c9e-a9e4-47a7ec23a5eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252040060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3252040060
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3983823352
Short name T186
Test name
Test status
Simulation time 1719087137 ps
CPU time 33.27 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:27:44 PM PDT 24
Peak memory 220576 kb
Host smart-d9981d95-110f-4ae4-8c31-cd640fc6e028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983823352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3983823352
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.245522762
Short name T277
Test name
Test status
Simulation time 259572556 ps
CPU time 9.97 seconds
Started Jul 30 05:27:15 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 219128 kb
Host smart-fce6dfd4-a8e7-4812-b7fb-5b35282720f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245522762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.245522762
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1876875475
Short name T197
Test name
Test status
Simulation time 7140414991 ps
CPU time 212.78 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:30:42 PM PDT 24
Peak memory 219688 kb
Host smart-80465800-7e1a-4301-88c7-58051c08f6a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876875475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1876875475
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3786805739
Short name T128
Test name
Test status
Simulation time 350826673 ps
CPU time 18.56 seconds
Started Jul 30 05:27:13 PM PDT 24
Finished Jul 30 05:27:32 PM PDT 24
Peak memory 220124 kb
Host smart-4af95efd-15d3-4b4b-82f1-7d6aae7baf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786805739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3786805739
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2644346700
Short name T154
Test name
Test status
Simulation time 1017073781 ps
CPU time 12.16 seconds
Started Jul 30 05:27:16 PM PDT 24
Finished Jul 30 05:27:28 PM PDT 24
Peak memory 219976 kb
Host smart-b7b19a5a-c55a-4db9-b856-c071cf87e4aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644346700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2644346700
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2569292260
Short name T116
Test name
Test status
Simulation time 2039124985 ps
CPU time 32.66 seconds
Started Jul 30 05:27:11 PM PDT 24
Finished Jul 30 05:27:44 PM PDT 24
Peak memory 220084 kb
Host smart-b2527daa-913b-40ef-a8fe-9e4b11eb6cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569292260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2569292260
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3930531594
Short name T117
Test name
Test status
Simulation time 755683196 ps
CPU time 8.49 seconds
Started Jul 30 05:27:10 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 219208 kb
Host smart-c7325fd7-30cc-4ee5-94b1-073be159c34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930531594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3930531594
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3650364560
Short name T36
Test name
Test status
Simulation time 3755841371 ps
CPU time 217.74 seconds
Started Jul 30 05:27:16 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 226676 kb
Host smart-b8b9496c-8719-49ca-a675-513f7cc932f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650364560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3650364560
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3593945251
Short name T153
Test name
Test status
Simulation time 516798373 ps
CPU time 22.8 seconds
Started Jul 30 05:27:13 PM PDT 24
Finished Jul 30 05:27:36 PM PDT 24
Peak memory 220124 kb
Host smart-2c2d479c-aa01-479f-be5c-29e84a80d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593945251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3593945251
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1718834364
Short name T115
Test name
Test status
Simulation time 372259008 ps
CPU time 10.5 seconds
Started Jul 30 05:27:11 PM PDT 24
Finished Jul 30 05:27:22 PM PDT 24
Peak memory 220092 kb
Host smart-033e9ad8-7eff-4712-84e3-2573992c0451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718834364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1718834364
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.530808535
Short name T245
Test name
Test status
Simulation time 515470389 ps
CPU time 22.39 seconds
Started Jul 30 05:27:12 PM PDT 24
Finished Jul 30 05:27:35 PM PDT 24
Peak memory 220056 kb
Host smart-79036ad6-1578-402d-b457-c027fbfd6d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530808535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.530808535
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2294215160
Short name T108
Test name
Test status
Simulation time 173281519 ps
CPU time 8.29 seconds
Started Jul 30 05:27:17 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 219000 kb
Host smart-98364d81-afa9-4a9e-857e-8d4abf0da39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294215160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2294215160
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.215008040
Short name T200
Test name
Test status
Simulation time 21957662250 ps
CPU time 160.9 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:29:59 PM PDT 24
Peak memory 234540 kb
Host smart-ef183c79-77e0-41d2-aeef-46a73a7cf962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215008040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.215008040
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2463293825
Short name T42
Test name
Test status
Simulation time 661615604 ps
CPU time 19.35 seconds
Started Jul 30 05:27:14 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 220052 kb
Host smart-1d113616-ea8e-435f-bf65-69c8a398b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463293825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2463293825
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.967818152
Short name T192
Test name
Test status
Simulation time 518468672 ps
CPU time 12.34 seconds
Started Jul 30 05:27:15 PM PDT 24
Finished Jul 30 05:27:28 PM PDT 24
Peak memory 220072 kb
Host smart-db66c377-7771-42de-a062-a22f22ad54d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967818152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.967818152
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2888009888
Short name T51
Test name
Test status
Simulation time 14252283191 ps
CPU time 271.74 seconds
Started Jul 30 05:27:14 PM PDT 24
Finished Jul 30 05:31:46 PM PDT 24
Peak memory 229476 kb
Host smart-859dfa95-d7a1-4566-b44c-c00cfe856aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888009888 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2888009888
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1400686734
Short name T34
Test name
Test status
Simulation time 990983973 ps
CPU time 9.99 seconds
Started Jul 30 05:27:15 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 219216 kb
Host smart-d92d4ea6-656c-41e4-8c06-219fd636e647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400686734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1400686734
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2927835281
Short name T240
Test name
Test status
Simulation time 1631545662 ps
CPU time 118.27 seconds
Started Jul 30 05:27:15 PM PDT 24
Finished Jul 30 05:29:13 PM PDT 24
Peak memory 236804 kb
Host smart-47e7f7b4-4e2b-428c-a6ca-28a46e1e693f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927835281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2927835281
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1797752951
Short name T290
Test name
Test status
Simulation time 2750158439 ps
CPU time 22.74 seconds
Started Jul 30 05:27:16 PM PDT 24
Finished Jul 30 05:27:39 PM PDT 24
Peak memory 220244 kb
Host smart-bbbe7556-0adc-40d0-be51-b300562eeed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797752951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1797752951
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3132620102
Short name T172
Test name
Test status
Simulation time 1083839338 ps
CPU time 17.03 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:35 PM PDT 24
Peak memory 219752 kb
Host smart-fea22f76-968c-4fed-a3ea-37919d6b4d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132620102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3132620102
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2266093757
Short name T198
Test name
Test status
Simulation time 1524161269 ps
CPU time 20.94 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:39 PM PDT 24
Peak memory 219948 kb
Host smart-614cfb0a-bdb5-496c-9ecd-160a2c6bf8e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266093757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2266093757
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1546001603
Short name T107
Test name
Test status
Simulation time 167454029 ps
CPU time 8.32 seconds
Started Jul 30 05:27:00 PM PDT 24
Finished Jul 30 05:27:09 PM PDT 24
Peak memory 219024 kb
Host smart-e9459964-3701-41b7-8cbf-e49b7aff594c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546001603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1546001603
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3153939691
Short name T241
Test name
Test status
Simulation time 16805021245 ps
CPU time 177.79 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:29:51 PM PDT 24
Peak memory 230476 kb
Host smart-dab0a0b2-e4c3-4117-81e8-ea6bde4f9dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153939691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3153939691
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4211674613
Short name T294
Test name
Test status
Simulation time 502652617 ps
CPU time 22.65 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:16 PM PDT 24
Peak memory 220240 kb
Host smart-45ad7eab-7726-430a-9700-722bb7e78e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211674613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4211674613
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2428310664
Short name T169
Test name
Test status
Simulation time 283059987 ps
CPU time 11.47 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:05 PM PDT 24
Peak memory 220100 kb
Host smart-2dbaea3d-154e-4a1f-afe7-f9b05918fe23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428310664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2428310664
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4271640063
Short name T21
Test name
Test status
Simulation time 3132259651 ps
CPU time 118.17 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:28:51 PM PDT 24
Peak memory 239224 kb
Host smart-36099cf5-6de9-425e-8e7a-0519044498bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271640063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4271640063
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.572741745
Short name T124
Test name
Test status
Simulation time 339810239 ps
CPU time 10.5 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:27:04 PM PDT 24
Peak memory 220104 kb
Host smart-b9504805-9ba9-4ab2-9906-e4ae09a336ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572741745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.572741745
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2212103856
Short name T72
Test name
Test status
Simulation time 1515150533 ps
CPU time 38.31 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:32 PM PDT 24
Peak memory 219912 kb
Host smart-6a6cbf77-1fec-418c-a1af-67d9ac18a1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212103856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2212103856
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3088386824
Short name T255
Test name
Test status
Simulation time 67515353946 ps
CPU time 2654.88 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 06:11:09 PM PDT 24
Peak memory 244872 kb
Host smart-7432bf8a-89cd-45c2-8f04-70cbf3d8c94e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088386824 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3088386824
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2929706425
Short name T296
Test name
Test status
Simulation time 987694840 ps
CPU time 10.12 seconds
Started Jul 30 05:27:14 PM PDT 24
Finished Jul 30 05:27:25 PM PDT 24
Peak memory 219124 kb
Host smart-8546120a-f14f-4d39-ba26-03ca8e6abf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929706425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2929706425
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4272321576
Short name T251
Test name
Test status
Simulation time 17235673242 ps
CPU time 308.2 seconds
Started Jul 30 05:27:17 PM PDT 24
Finished Jul 30 05:32:26 PM PDT 24
Peak memory 238476 kb
Host smart-165a1133-021d-428d-8c1d-15afb476ef80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272321576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4272321576
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.364507231
Short name T230
Test name
Test status
Simulation time 1007774835 ps
CPU time 22.7 seconds
Started Jul 30 05:27:16 PM PDT 24
Finished Jul 30 05:27:39 PM PDT 24
Peak memory 220008 kb
Host smart-541a8a42-8062-483d-9bf6-cc788ebcae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364507231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.364507231
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2141310196
Short name T181
Test name
Test status
Simulation time 1018087542 ps
CPU time 12.18 seconds
Started Jul 30 05:27:19 PM PDT 24
Finished Jul 30 05:27:32 PM PDT 24
Peak memory 220056 kb
Host smart-f3a95701-7f7c-4ad3-909c-5db543bdfb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141310196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2141310196
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2252653986
Short name T300
Test name
Test status
Simulation time 231294897 ps
CPU time 18.87 seconds
Started Jul 30 05:27:15 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 220060 kb
Host smart-e5098f96-cdf6-427d-95d4-4d707ec31041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252653986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2252653986
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3118973875
Short name T302
Test name
Test status
Simulation time 171348075 ps
CPU time 8.71 seconds
Started Jul 30 05:27:20 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 219012 kb
Host smart-21a79f81-fb39-4751-83c2-91aaba892041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118973875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3118973875
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2974485160
Short name T287
Test name
Test status
Simulation time 3604511703 ps
CPU time 185.64 seconds
Started Jul 30 05:27:21 PM PDT 24
Finished Jul 30 05:30:27 PM PDT 24
Peak memory 226424 kb
Host smart-f0e7b6b8-52ee-4a6e-b69b-2fce3ed9be23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974485160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2974485160
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1950984368
Short name T144
Test name
Test status
Simulation time 1375151520 ps
CPU time 19.1 seconds
Started Jul 30 05:27:20 PM PDT 24
Finished Jul 30 05:27:39 PM PDT 24
Peak memory 220052 kb
Host smart-2aae91fb-3f12-4e30-8fdc-e6a91db8a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950984368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1950984368
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3951930817
Short name T189
Test name
Test status
Simulation time 1078543150 ps
CPU time 12.36 seconds
Started Jul 30 05:27:20 PM PDT 24
Finished Jul 30 05:27:32 PM PDT 24
Peak memory 220120 kb
Host smart-a8fbe716-cfce-4c33-951c-c79bf2632088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951930817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3951930817
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2616297634
Short name T285
Test name
Test status
Simulation time 285382705 ps
CPU time 16.27 seconds
Started Jul 30 05:27:17 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 219936 kb
Host smart-9d7f0556-a7ba-4054-afb5-ef61a6e0cc71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616297634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2616297634
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2671482403
Short name T134
Test name
Test status
Simulation time 986269006 ps
CPU time 9.96 seconds
Started Jul 30 05:27:20 PM PDT 24
Finished Jul 30 05:27:30 PM PDT 24
Peak memory 219232 kb
Host smart-a2115054-209d-4227-91be-c4944948b38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671482403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2671482403
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3561318511
Short name T151
Test name
Test status
Simulation time 3152234997 ps
CPU time 182.58 seconds
Started Jul 30 05:27:17 PM PDT 24
Finished Jul 30 05:30:20 PM PDT 24
Peak memory 220336 kb
Host smart-db1601d0-68b8-430f-8caf-868888aae14f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561318511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3561318511
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4267665524
Short name T280
Test name
Test status
Simulation time 664759360 ps
CPU time 19.59 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:38 PM PDT 24
Peak memory 220096 kb
Host smart-af9cb1c6-7d66-4bfe-b1f6-3bf1095a6c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267665524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4267665524
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2294143339
Short name T183
Test name
Test status
Simulation time 693586170 ps
CPU time 10.49 seconds
Started Jul 30 05:27:19 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 220080 kb
Host smart-4ba4816b-bb4f-4321-afec-e3b76146845c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294143339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2294143339
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3601784906
Short name T130
Test name
Test status
Simulation time 873159552 ps
CPU time 10.76 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 219920 kb
Host smart-75a7b899-a023-4cf5-b1cc-344f87c78090
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601784906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3601784906
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1083509321
Short name T50
Test name
Test status
Simulation time 100659953289 ps
CPU time 1033.69 seconds
Started Jul 30 05:27:21 PM PDT 24
Finished Jul 30 05:44:35 PM PDT 24
Peak memory 237692 kb
Host smart-ae9bc9ce-0a2f-4773-b168-d3114ec8ce3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083509321 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1083509321
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1641531957
Short name T261
Test name
Test status
Simulation time 257263172 ps
CPU time 9.77 seconds
Started Jul 30 05:27:19 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 219028 kb
Host smart-1e4828f6-d1c3-4525-bb13-55c75154d9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641531957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1641531957
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3131685694
Short name T159
Test name
Test status
Simulation time 6131311926 ps
CPU time 295.6 seconds
Started Jul 30 05:27:19 PM PDT 24
Finished Jul 30 05:32:15 PM PDT 24
Peak memory 220356 kb
Host smart-189c13b7-5413-49c1-9cd6-4f3c144d8aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131685694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3131685694
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2205534875
Short name T150
Test name
Test status
Simulation time 402202980 ps
CPU time 19.44 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:38 PM PDT 24
Peak memory 220108 kb
Host smart-b0e56bd2-3a81-4e3b-9726-0c241c166dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205534875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2205534875
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2648188155
Short name T120
Test name
Test status
Simulation time 5119971275 ps
CPU time 12.08 seconds
Started Jul 30 05:27:22 PM PDT 24
Finished Jul 30 05:27:35 PM PDT 24
Peak memory 220208 kb
Host smart-4d4dcfdb-79c3-4de4-b3b8-518c592fd524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648188155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2648188155
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3644775341
Short name T309
Test name
Test status
Simulation time 3120790445 ps
CPU time 40.04 seconds
Started Jul 30 05:27:19 PM PDT 24
Finished Jul 30 05:28:00 PM PDT 24
Peak memory 220200 kb
Host smart-5a90095a-3563-4d50-9d98-b5682f23dd59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644775341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3644775341
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.893434427
Short name T250
Test name
Test status
Simulation time 261060813 ps
CPU time 10.11 seconds
Started Jul 30 05:27:21 PM PDT 24
Finished Jul 30 05:27:31 PM PDT 24
Peak memory 219064 kb
Host smart-8c8f1e76-b4ce-4dcb-bece-4a3083c9da4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893434427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.893434427
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2088290484
Short name T208
Test name
Test status
Simulation time 110060485466 ps
CPU time 586.77 seconds
Started Jul 30 05:27:22 PM PDT 24
Finished Jul 30 05:37:09 PM PDT 24
Peak memory 227344 kb
Host smart-e5b742c9-e54e-4aeb-91ef-405d85d534ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088290484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2088290484
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1241368025
Short name T155
Test name
Test status
Simulation time 3954083771 ps
CPU time 33.17 seconds
Started Jul 30 05:27:18 PM PDT 24
Finished Jul 30 05:27:51 PM PDT 24
Peak memory 219664 kb
Host smart-1ee843de-2e91-4a0e-857c-ddaf0f14e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241368025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1241368025
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.877651563
Short name T105
Test name
Test status
Simulation time 262544375 ps
CPU time 12.57 seconds
Started Jul 30 05:27:21 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 219976 kb
Host smart-126e6e73-f2ff-4898-aa61-913fe4150643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877651563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.877651563
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2763603564
Short name T252
Test name
Test status
Simulation time 302866850 ps
CPU time 23.63 seconds
Started Jul 30 05:27:20 PM PDT 24
Finished Jul 30 05:27:44 PM PDT 24
Peak memory 219960 kb
Host smart-1bc73014-6a97-4e15-a9ec-f3d158b1fc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763603564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2763603564
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3281750214
Short name T238
Test name
Test status
Simulation time 1035401400 ps
CPU time 9.82 seconds
Started Jul 30 05:27:24 PM PDT 24
Finished Jul 30 05:27:34 PM PDT 24
Peak memory 219136 kb
Host smart-3941c8bc-5d9e-466a-a50a-cf195e22e101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281750214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3281750214
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.178748394
Short name T308
Test name
Test status
Simulation time 8193910830 ps
CPU time 434.36 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:34:37 PM PDT 24
Peak memory 241712 kb
Host smart-18c08418-4978-4b29-91b2-309e7a977cdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178748394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.178748394
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3855496231
Short name T265
Test name
Test status
Simulation time 1984743328 ps
CPU time 22.97 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:27:46 PM PDT 24
Peak memory 219980 kb
Host smart-1ed4a80b-f4e7-491f-871b-77892f8339a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855496231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3855496231
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2290058252
Short name T175
Test name
Test status
Simulation time 979689488 ps
CPU time 12.13 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:27:35 PM PDT 24
Peak memory 220016 kb
Host smart-f945bd3b-ba92-4feb-919f-175abbd083cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290058252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2290058252
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3878918896
Short name T248
Test name
Test status
Simulation time 530939779 ps
CPU time 33.89 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:27:57 PM PDT 24
Peak memory 219996 kb
Host smart-a7c0eda7-bc3a-4160-bc25-e575c2f42982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878918896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3878918896
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1426101861
Short name T46
Test name
Test status
Simulation time 176894108165 ps
CPU time 1715.72 seconds
Started Jul 30 05:27:22 PM PDT 24
Finished Jul 30 05:55:58 PM PDT 24
Peak memory 244856 kb
Host smart-ee92d097-b7e5-4a64-a2fa-050b26ab103f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426101861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1426101861
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.187144209
Short name T210
Test name
Test status
Simulation time 1033278843 ps
CPU time 9.92 seconds
Started Jul 30 05:27:26 PM PDT 24
Finished Jul 30 05:27:36 PM PDT 24
Peak memory 219072 kb
Host smart-6d346965-3eea-49d3-923c-dae6f88b3c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187144209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.187144209
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3226103166
Short name T139
Test name
Test status
Simulation time 26667036390 ps
CPU time 349.14 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:33:12 PM PDT 24
Peak memory 235628 kb
Host smart-7b0f796d-24f8-4e4c-8eb5-8a860225069e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226103166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3226103166
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2142769185
Short name T318
Test name
Test status
Simulation time 1011621381 ps
CPU time 22.47 seconds
Started Jul 30 05:27:27 PM PDT 24
Finished Jul 30 05:27:50 PM PDT 24
Peak memory 220072 kb
Host smart-59f8e172-78d2-4209-a552-f9cc0ed57ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142769185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2142769185
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2109894786
Short name T229
Test name
Test status
Simulation time 260736520 ps
CPU time 12.19 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:27:35 PM PDT 24
Peak memory 220060 kb
Host smart-5501fb28-1015-4028-8733-9bd4814a341d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109894786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2109894786
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4260164999
Short name T152
Test name
Test status
Simulation time 3259718296 ps
CPU time 41.59 seconds
Started Jul 30 05:27:23 PM PDT 24
Finished Jul 30 05:28:04 PM PDT 24
Peak memory 220148 kb
Host smart-1168e36f-140c-4831-ae22-6d13aa99a8ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260164999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4260164999
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3381588068
Short name T316
Test name
Test status
Simulation time 36376075329 ps
CPU time 397.41 seconds
Started Jul 30 05:27:27 PM PDT 24
Finished Jul 30 05:34:05 PM PDT 24
Peak memory 229596 kb
Host smart-67bf2318-0937-4de8-bde0-cc74b2e1e9fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381588068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3381588068
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.622210556
Short name T114
Test name
Test status
Simulation time 2060400749 ps
CPU time 8.25 seconds
Started Jul 30 05:27:30 PM PDT 24
Finished Jul 30 05:27:38 PM PDT 24
Peak memory 219260 kb
Host smart-efdd571f-0df3-4521-a032-6ed9908664d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622210556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.622210556
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2068903806
Short name T295
Test name
Test status
Simulation time 5658702438 ps
CPU time 337.55 seconds
Started Jul 30 05:27:26 PM PDT 24
Finished Jul 30 05:33:04 PM PDT 24
Peak memory 243300 kb
Host smart-770eecd2-d10e-4e79-bbe4-01719c0b6805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068903806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2068903806
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.873244330
Short name T216
Test name
Test status
Simulation time 2063827344 ps
CPU time 23.08 seconds
Started Jul 30 05:27:32 PM PDT 24
Finished Jul 30 05:27:56 PM PDT 24
Peak memory 220116 kb
Host smart-14b8c903-07cf-4dfd-b8bd-82c80aa7588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873244330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.873244330
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3536805131
Short name T268
Test name
Test status
Simulation time 268594207 ps
CPU time 12.28 seconds
Started Jul 30 05:27:26 PM PDT 24
Finished Jul 30 05:27:38 PM PDT 24
Peak memory 220064 kb
Host smart-caf3476c-25dd-4137-b737-7802425bd33d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536805131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3536805131
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3923515870
Short name T301
Test name
Test status
Simulation time 3053837473 ps
CPU time 40.37 seconds
Started Jul 30 05:27:28 PM PDT 24
Finished Jul 30 05:28:09 PM PDT 24
Peak memory 220156 kb
Host smart-064aefc3-70e4-4827-b97c-e49438831f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923515870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3923515870
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2766423863
Short name T176
Test name
Test status
Simulation time 258429639 ps
CPU time 10.09 seconds
Started Jul 30 05:27:33 PM PDT 24
Finished Jul 30 05:27:43 PM PDT 24
Peak memory 219000 kb
Host smart-6a8df1b3-7a23-4e64-a4cb-0d3ef721eb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766423863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2766423863
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.648373328
Short name T267
Test name
Test status
Simulation time 14266478433 ps
CPU time 199.95 seconds
Started Jul 30 05:27:34 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 240396 kb
Host smart-f2d01114-ffe8-40b3-967c-f8e03c247c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648373328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.648373328
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1156863677
Short name T297
Test name
Test status
Simulation time 1377629616 ps
CPU time 19.29 seconds
Started Jul 30 05:27:33 PM PDT 24
Finished Jul 30 05:27:52 PM PDT 24
Peak memory 220024 kb
Host smart-f68c1ce9-8cd2-45be-abf3-5c921561ef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156863677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1156863677
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2028101744
Short name T135
Test name
Test status
Simulation time 676489567 ps
CPU time 10.9 seconds
Started Jul 30 05:27:32 PM PDT 24
Finished Jul 30 05:27:43 PM PDT 24
Peak memory 219996 kb
Host smart-b76f9468-75a6-4da3-873f-5d9ebd436500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028101744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2028101744
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2613054899
Short name T132
Test name
Test status
Simulation time 264861682 ps
CPU time 15.43 seconds
Started Jul 30 05:27:33 PM PDT 24
Finished Jul 30 05:27:48 PM PDT 24
Peak memory 219960 kb
Host smart-78af2a9e-26f6-4744-a901-43d569835485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613054899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2613054899
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2248831202
Short name T47
Test name
Test status
Simulation time 94320960484 ps
CPU time 3538.25 seconds
Started Jul 30 05:27:34 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 248784 kb
Host smart-b229f119-78a9-49ac-b2ef-1c6b05b1687c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248831202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2248831202
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3148829015
Short name T8
Test name
Test status
Simulation time 261431242 ps
CPU time 10.1 seconds
Started Jul 30 05:27:41 PM PDT 24
Finished Jul 30 05:27:51 PM PDT 24
Peak memory 219112 kb
Host smart-9f702efb-a205-4822-b82f-93321b233898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148829015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3148829015
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3073520855
Short name T40
Test name
Test status
Simulation time 9902867107 ps
CPU time 298.16 seconds
Started Jul 30 05:27:35 PM PDT 24
Finished Jul 30 05:32:34 PM PDT 24
Peak memory 244336 kb
Host smart-d2ba0e21-9f61-45e7-97d7-9ea6795b6cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073520855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3073520855
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3384743824
Short name T217
Test name
Test status
Simulation time 1415210144 ps
CPU time 23.54 seconds
Started Jul 30 05:27:39 PM PDT 24
Finished Jul 30 05:28:03 PM PDT 24
Peak memory 220100 kb
Host smart-ba5daef6-69f3-42d3-89a7-b354ce0ead09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384743824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3384743824
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.868761197
Short name T234
Test name
Test status
Simulation time 514802020 ps
CPU time 11.78 seconds
Started Jul 30 05:27:35 PM PDT 24
Finished Jul 30 05:27:47 PM PDT 24
Peak memory 219988 kb
Host smart-3b9c7c65-3b58-4f1f-baf1-eaadc23a07a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868761197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.868761197
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.788442268
Short name T260
Test name
Test status
Simulation time 222813331 ps
CPU time 14.97 seconds
Started Jul 30 05:27:35 PM PDT 24
Finished Jul 30 05:27:51 PM PDT 24
Peak memory 220028 kb
Host smart-ab09e496-67bc-4e7e-b5c1-fe1a9c2fc877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788442268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.788442268
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1902950611
Short name T12
Test name
Test status
Simulation time 15448634422 ps
CPU time 592.07 seconds
Started Jul 30 05:27:39 PM PDT 24
Finished Jul 30 05:37:31 PM PDT 24
Peak memory 229916 kb
Host smart-32b5629d-cee4-48a2-a65e-a985a0a852a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902950611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1902950611
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1014032670
Short name T87
Test name
Test status
Simulation time 250461392 ps
CPU time 10.38 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:05 PM PDT 24
Peak memory 219220 kb
Host smart-5e0969b9-a578-41ed-92fe-1c75eadb1bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014032670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1014032670
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3150278552
Short name T9
Test name
Test status
Simulation time 877192926 ps
CPU time 11.97 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:27:06 PM PDT 24
Peak memory 220112 kb
Host smart-f1e36b42-d110-4c75-9f18-d23cf72d34dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150278552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3150278552
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.100023958
Short name T262
Test name
Test status
Simulation time 267854638 ps
CPU time 11.89 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:06 PM PDT 24
Peak memory 220008 kb
Host smart-20247b45-3e51-4b1d-9603-f37b18be06fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100023958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.100023958
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.675365800
Short name T168
Test name
Test status
Simulation time 6044007712 ps
CPU time 30.43 seconds
Started Jul 30 05:26:52 PM PDT 24
Finished Jul 30 05:27:23 PM PDT 24
Peak memory 220108 kb
Host smart-325ef58b-d8ae-4b55-8cd5-5d562e4737f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675365800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.675365800
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2655274110
Short name T257
Test name
Test status
Simulation time 3527093572 ps
CPU time 10.07 seconds
Started Jul 30 05:27:41 PM PDT 24
Finished Jul 30 05:27:51 PM PDT 24
Peak memory 219168 kb
Host smart-6dc8c9a6-9fbf-4afc-acfe-0c84cc8a567e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655274110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2655274110
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.169048199
Short name T215
Test name
Test status
Simulation time 6793592565 ps
CPU time 216.08 seconds
Started Jul 30 05:27:41 PM PDT 24
Finished Jul 30 05:31:17 PM PDT 24
Peak memory 220428 kb
Host smart-5cc30b46-1042-421b-901f-48bac8b8870c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169048199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.169048199
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1562883691
Short name T254
Test name
Test status
Simulation time 1973243189 ps
CPU time 22.94 seconds
Started Jul 30 05:27:38 PM PDT 24
Finished Jul 30 05:28:01 PM PDT 24
Peak memory 220144 kb
Host smart-a62b806d-25ad-470d-ac35-d3f182bd0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562883691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1562883691
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2531943096
Short name T273
Test name
Test status
Simulation time 305449970 ps
CPU time 10.59 seconds
Started Jul 30 05:27:39 PM PDT 24
Finished Jul 30 05:27:50 PM PDT 24
Peak memory 220048 kb
Host smart-24363f29-480d-4009-bb50-33401dd94235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531943096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2531943096
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1604433161
Short name T57
Test name
Test status
Simulation time 1000958881 ps
CPU time 23.54 seconds
Started Jul 30 05:27:42 PM PDT 24
Finished Jul 30 05:28:05 PM PDT 24
Peak memory 220040 kb
Host smart-a2bfe077-8d03-46aa-a090-aee9762a00bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604433161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1604433161
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2682073277
Short name T218
Test name
Test status
Simulation time 1182214556 ps
CPU time 8.52 seconds
Started Jul 30 05:27:42 PM PDT 24
Finished Jul 30 05:27:51 PM PDT 24
Peak memory 219184 kb
Host smart-c3788fe0-3763-4132-a917-b430b42bdd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682073277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2682073277
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.580273945
Short name T38
Test name
Test status
Simulation time 3695609358 ps
CPU time 209.6 seconds
Started Jul 30 05:27:40 PM PDT 24
Finished Jul 30 05:31:09 PM PDT 24
Peak memory 237808 kb
Host smart-58fce082-9006-4469-ac2c-93eadfb25ed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580273945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.580273945
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3001719857
Short name T171
Test name
Test status
Simulation time 1834810949 ps
CPU time 22.96 seconds
Started Jul 30 05:27:45 PM PDT 24
Finished Jul 30 05:28:08 PM PDT 24
Peak memory 220092 kb
Host smart-45269b3e-f3d4-48ad-b6d4-148697c5076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001719857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3001719857
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2355474074
Short name T194
Test name
Test status
Simulation time 402615401 ps
CPU time 11.94 seconds
Started Jul 30 05:27:38 PM PDT 24
Finished Jul 30 05:27:50 PM PDT 24
Peak memory 220104 kb
Host smart-6e2cae14-f777-4c28-a8b6-f84bb8fb8538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355474074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2355474074
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2401257660
Short name T143
Test name
Test status
Simulation time 547518144 ps
CPU time 27.44 seconds
Started Jul 30 05:27:38 PM PDT 24
Finished Jul 30 05:28:06 PM PDT 24
Peak memory 219992 kb
Host smart-3f0069bd-702b-4e1f-998c-e82f7839f603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401257660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2401257660
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.911859866
Short name T202
Test name
Test status
Simulation time 1035036210 ps
CPU time 9.95 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:27:58 PM PDT 24
Peak memory 218988 kb
Host smart-d043a7b7-8d8c-4268-823a-357a499653b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911859866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.911859866
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2770892994
Short name T164
Test name
Test status
Simulation time 1000380282 ps
CPU time 19.49 seconds
Started Jul 30 05:27:44 PM PDT 24
Finished Jul 30 05:28:04 PM PDT 24
Peak memory 220120 kb
Host smart-a2443664-52cc-4527-945b-986a6cb4af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770892994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2770892994
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2269986127
Short name T122
Test name
Test status
Simulation time 726380980 ps
CPU time 9.94 seconds
Started Jul 30 05:27:43 PM PDT 24
Finished Jul 30 05:27:53 PM PDT 24
Peak memory 220064 kb
Host smart-7c9f9508-1cf3-4561-9c54-db9c8e3dacd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269986127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2269986127
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.399710386
Short name T133
Test name
Test status
Simulation time 719052372 ps
CPU time 20.02 seconds
Started Jul 30 05:27:43 PM PDT 24
Finished Jul 30 05:28:03 PM PDT 24
Peak memory 220064 kb
Host smart-3d7e647a-610c-41be-8663-beee892b97fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399710386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.399710386
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.152705325
Short name T263
Test name
Test status
Simulation time 289785755739 ps
CPU time 2907.98 seconds
Started Jul 30 05:27:45 PM PDT 24
Finished Jul 30 06:16:13 PM PDT 24
Peak memory 253016 kb
Host smart-2d33b9bc-8f12-4ac7-b0fa-ffe45d1b0f47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152705325 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.152705325
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2984053464
Short name T244
Test name
Test status
Simulation time 266634557 ps
CPU time 9.79 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:27:58 PM PDT 24
Peak memory 219092 kb
Host smart-9926f6e8-57c9-4956-9573-1da2da156c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984053464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2984053464
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3705500793
Short name T125
Test name
Test status
Simulation time 10660246390 ps
CPU time 134.77 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:30:03 PM PDT 24
Peak memory 220256 kb
Host smart-b78d5dba-f73c-483e-a49d-b289c9b929b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705500793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3705500793
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3148646857
Short name T221
Test name
Test status
Simulation time 430712238 ps
CPU time 19.15 seconds
Started Jul 30 05:27:47 PM PDT 24
Finished Jul 30 05:28:06 PM PDT 24
Peak memory 220084 kb
Host smart-d7c51a2c-08b4-479c-98ed-aaadd3e8270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148646857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3148646857
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3436908034
Short name T203
Test name
Test status
Simulation time 433074600 ps
CPU time 10.69 seconds
Started Jul 30 05:27:42 PM PDT 24
Finished Jul 30 05:27:53 PM PDT 24
Peak memory 220088 kb
Host smart-2efcabc8-d46b-4ccb-a141-480d9045f24b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436908034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3436908034
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4266757301
Short name T270
Test name
Test status
Simulation time 4145547743 ps
CPU time 30.16 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:28:18 PM PDT 24
Peak memory 220052 kb
Host smart-e85be53c-88e3-4bce-9f94-d1ee89535ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266757301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4266757301
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4135891045
Short name T131
Test name
Test status
Simulation time 174543284 ps
CPU time 8.3 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:27:57 PM PDT 24
Peak memory 219080 kb
Host smart-831030eb-fa7e-4df8-a499-57c883ae1ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135891045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4135891045
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2010582881
Short name T266
Test name
Test status
Simulation time 6876265857 ps
CPU time 228.43 seconds
Started Jul 30 05:27:49 PM PDT 24
Finished Jul 30 05:31:37 PM PDT 24
Peak memory 226704 kb
Host smart-8363ff29-e84e-48f8-bc53-ad65fafe82bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010582881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2010582881
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.364347420
Short name T110
Test name
Test status
Simulation time 342832952 ps
CPU time 19.05 seconds
Started Jul 30 05:27:49 PM PDT 24
Finished Jul 30 05:28:08 PM PDT 24
Peak memory 219996 kb
Host smart-64fef94f-033c-4498-9cd3-11e64953adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364347420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.364347420
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1190914738
Short name T207
Test name
Test status
Simulation time 1039935998 ps
CPU time 16.91 seconds
Started Jul 30 05:27:47 PM PDT 24
Finished Jul 30 05:28:04 PM PDT 24
Peak memory 219368 kb
Host smart-03bda757-85c6-4eae-8e08-5370f0bd357a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190914738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1190914738
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.685109227
Short name T209
Test name
Test status
Simulation time 1479597756 ps
CPU time 27.06 seconds
Started Jul 30 05:27:47 PM PDT 24
Finished Jul 30 05:28:14 PM PDT 24
Peak memory 219916 kb
Host smart-a5b6afd4-a5cb-41ba-af0e-7657ccd18dd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685109227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.685109227
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2762655941
Short name T247
Test name
Test status
Simulation time 325619973 ps
CPU time 8.12 seconds
Started Jul 30 05:27:50 PM PDT 24
Finished Jul 30 05:27:58 PM PDT 24
Peak memory 219188 kb
Host smart-287103dc-e4aa-4ed2-a665-d9d9614f6303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762655941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2762655941
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3444020795
Short name T317
Test name
Test status
Simulation time 4593998993 ps
CPU time 261.1 seconds
Started Jul 30 05:27:49 PM PDT 24
Finished Jul 30 05:32:10 PM PDT 24
Peak memory 237096 kb
Host smart-e87cd1bd-ffd2-47d2-85cb-718434e579d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444020795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3444020795
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.112225815
Short name T27
Test name
Test status
Simulation time 2063449086 ps
CPU time 23.27 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:28:11 PM PDT 24
Peak memory 220084 kb
Host smart-0603069a-2265-4e31-90ce-d0d7550605c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112225815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.112225815
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2516088698
Short name T58
Test name
Test status
Simulation time 1008443291 ps
CPU time 16.82 seconds
Started Jul 30 05:27:47 PM PDT 24
Finished Jul 30 05:28:04 PM PDT 24
Peak memory 220120 kb
Host smart-b516cdc7-cda1-46da-8e12-016f2cc77116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516088698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2516088698
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2449186410
Short name T293
Test name
Test status
Simulation time 359135193 ps
CPU time 18.11 seconds
Started Jul 30 05:27:48 PM PDT 24
Finished Jul 30 05:28:06 PM PDT 24
Peak memory 219832 kb
Host smart-8bd238aa-a6ef-4ab1-9948-6c4cb58f15c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449186410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2449186410
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.465402258
Short name T121
Test name
Test status
Simulation time 996989907 ps
CPU time 10.04 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:02 PM PDT 24
Peak memory 219164 kb
Host smart-ce338fe1-d138-4a32-85de-197d79f394c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465402258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.465402258
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3674421027
Short name T17
Test name
Test status
Simulation time 11896398491 ps
CPU time 306.49 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:32:58 PM PDT 24
Peak memory 220364 kb
Host smart-ee6e7848-3370-4be5-a93e-bd592cb8a443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674421027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3674421027
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.373421884
Short name T111
Test name
Test status
Simulation time 332622072 ps
CPU time 19.87 seconds
Started Jul 30 05:27:55 PM PDT 24
Finished Jul 30 05:28:15 PM PDT 24
Peak memory 220116 kb
Host smart-e3b2a334-cc96-4347-9cb4-0797ba281e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373421884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.373421884
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1822548354
Short name T284
Test name
Test status
Simulation time 351665109 ps
CPU time 10.35 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:02 PM PDT 24
Peak memory 219960 kb
Host smart-d440575f-9ebb-4d63-bd59-faa714d17bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822548354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1822548354
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3784886320
Short name T231
Test name
Test status
Simulation time 205612658 ps
CPU time 14.38 seconds
Started Jul 30 05:27:54 PM PDT 24
Finished Jul 30 05:28:09 PM PDT 24
Peak memory 220092 kb
Host smart-1939f269-8ffb-403c-8bc4-e80474b961e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784886320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3784886320
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2955061464
Short name T127
Test name
Test status
Simulation time 174562548 ps
CPU time 8.22 seconds
Started Jul 30 05:27:53 PM PDT 24
Finished Jul 30 05:28:01 PM PDT 24
Peak memory 219168 kb
Host smart-f4cb4d0e-6e0f-48fe-8e31-a5c6895fa5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955061464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2955061464
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3629685773
Short name T242
Test name
Test status
Simulation time 3729878664 ps
CPU time 210.09 seconds
Started Jul 30 05:27:51 PM PDT 24
Finished Jul 30 05:31:21 PM PDT 24
Peak memory 229372 kb
Host smart-068b5430-67e9-40b8-ae98-9c3bf84ff56b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629685773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3629685773
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1373307649
Short name T188
Test name
Test status
Simulation time 338975667 ps
CPU time 18.83 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:11 PM PDT 24
Peak memory 220056 kb
Host smart-f458ebc1-8821-4922-9fe7-87646d02ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373307649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1373307649
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2330732983
Short name T104
Test name
Test status
Simulation time 696894252 ps
CPU time 10.52 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:03 PM PDT 24
Peak memory 220060 kb
Host smart-82e1ec0f-b399-4644-bf7e-ee1054f52b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330732983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2330732983
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.608092805
Short name T70
Test name
Test status
Simulation time 535272484 ps
CPU time 32.75 seconds
Started Jul 30 05:27:51 PM PDT 24
Finished Jul 30 05:28:24 PM PDT 24
Peak memory 220048 kb
Host smart-2d07dfe0-8c58-4aa8-954b-8955bd0fcede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608092805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.608092805
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1444956590
Short name T239
Test name
Test status
Simulation time 260397567 ps
CPU time 10.2 seconds
Started Jul 30 05:27:56 PM PDT 24
Finished Jul 30 05:28:07 PM PDT 24
Peak memory 218944 kb
Host smart-94a9a793-3908-474d-865b-9e3eb9cd40ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444956590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1444956590
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2648547603
Short name T307
Test name
Test status
Simulation time 35894202509 ps
CPU time 176.55 seconds
Started Jul 30 05:27:55 PM PDT 24
Finished Jul 30 05:30:52 PM PDT 24
Peak memory 230300 kb
Host smart-364ab420-6ae4-48e0-8751-8c4e6a61be48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648547603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2648547603
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2066602675
Short name T136
Test name
Test status
Simulation time 336821670 ps
CPU time 19.43 seconds
Started Jul 30 05:27:51 PM PDT 24
Finished Jul 30 05:28:11 PM PDT 24
Peak memory 220264 kb
Host smart-95a99072-8d7b-41a0-83bf-c7ac7a13193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066602675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2066602675
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1776838135
Short name T33
Test name
Test status
Simulation time 1714664544 ps
CPU time 12.37 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:04 PM PDT 24
Peak memory 220056 kb
Host smart-7cb46fb0-95f0-4913-88bb-b137052bac0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776838135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1776838135
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1619895390
Short name T138
Test name
Test status
Simulation time 721285949 ps
CPU time 23.2 seconds
Started Jul 30 05:27:52 PM PDT 24
Finished Jul 30 05:28:15 PM PDT 24
Peak memory 220000 kb
Host smart-ea042c4a-84b3-4849-8674-9109be5cf578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619895390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1619895390
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2712696935
Short name T237
Test name
Test status
Simulation time 991392457 ps
CPU time 9.85 seconds
Started Jul 30 05:27:56 PM PDT 24
Finished Jul 30 05:28:06 PM PDT 24
Peak memory 219216 kb
Host smart-ec3cbe75-2ab1-475d-b3f2-0938e910afed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712696935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2712696935
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.722119747
Short name T227
Test name
Test status
Simulation time 1456089165 ps
CPU time 130.1 seconds
Started Jul 30 05:27:57 PM PDT 24
Finished Jul 30 05:30:07 PM PDT 24
Peak memory 242428 kb
Host smart-dfcef327-2840-4c06-a062-a5c4863a52c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722119747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.722119747
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3117668577
Short name T214
Test name
Test status
Simulation time 1832071243 ps
CPU time 23.66 seconds
Started Jul 30 05:27:57 PM PDT 24
Finished Jul 30 05:28:21 PM PDT 24
Peak memory 220072 kb
Host smart-2ceb767f-af33-45a5-a25b-377d6a7f69f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117668577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3117668577
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1647035182
Short name T16
Test name
Test status
Simulation time 1227637025 ps
CPU time 16.84 seconds
Started Jul 30 05:27:55 PM PDT 24
Finished Jul 30 05:28:12 PM PDT 24
Peak memory 220052 kb
Host smart-0865d9ff-4693-41cf-859b-6a9f6e07d7df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647035182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1647035182
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1653594925
Short name T88
Test name
Test status
Simulation time 1843177124 ps
CPU time 19.97 seconds
Started Jul 30 05:27:58 PM PDT 24
Finished Jul 30 05:28:18 PM PDT 24
Peak memory 220016 kb
Host smart-08501637-01d1-4450-a0c6-75c1e7834ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653594925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1653594925
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3081643793
Short name T212
Test name
Test status
Simulation time 1031964194 ps
CPU time 10.1 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:27:08 PM PDT 24
Peak memory 219184 kb
Host smart-29f46284-d8e2-44c9-80ce-7ae518dcf8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081643793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3081643793
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.139889989
Short name T173
Test name
Test status
Simulation time 2612143073 ps
CPU time 203.77 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 226680 kb
Host smart-c66c7e07-4884-45a6-9f13-5578f11f97c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139889989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.139889989
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.270097717
Short name T190
Test name
Test status
Simulation time 2070198100 ps
CPU time 22.55 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:27:19 PM PDT 24
Peak memory 220112 kb
Host smart-7e302d87-18b5-450b-be61-8e8d08588c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270097717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.270097717
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1646201432
Short name T321
Test name
Test status
Simulation time 692936340 ps
CPU time 10.36 seconds
Started Jul 30 05:26:55 PM PDT 24
Finished Jul 30 05:27:06 PM PDT 24
Peak memory 220124 kb
Host smart-51d27170-4dee-49d0-ac75-70302be24534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646201432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1646201432
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.412848605
Short name T20
Test name
Test status
Simulation time 299605923 ps
CPU time 118.79 seconds
Started Jul 30 05:26:55 PM PDT 24
Finished Jul 30 05:28:54 PM PDT 24
Peak memory 233908 kb
Host smart-00cc95e3-ca47-4ecd-931b-31f4665c2f2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412848605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.412848605
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2060623062
Short name T71
Test name
Test status
Simulation time 3946388629 ps
CPU time 17.75 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:27:14 PM PDT 24
Peak memory 220160 kb
Host smart-f48880dd-2bf4-4d59-ae8f-9071849d5b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060623062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2060623062
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2112735508
Short name T31
Test name
Test status
Simulation time 1139233157 ps
CPU time 36.22 seconds
Started Jul 30 05:26:52 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 220040 kb
Host smart-841941f3-0090-456d-aab8-c6b645f39cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112735508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2112735508
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1296167780
Short name T15
Test name
Test status
Simulation time 26897316275 ps
CPU time 9705.96 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 08:08:41 PM PDT 24
Peak memory 236692 kb
Host smart-e491bba4-0d2f-488d-b8d5-5a11d6adba71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296167780 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1296167780
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1858795708
Short name T148
Test name
Test status
Simulation time 25691754136 ps
CPU time 368.15 seconds
Started Jul 30 05:27:55 PM PDT 24
Finished Jul 30 05:34:03 PM PDT 24
Peak memory 235628 kb
Host smart-218c819f-737a-4787-941f-41188bc56ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858795708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1858795708
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.886012344
Short name T196
Test name
Test status
Simulation time 512861151 ps
CPU time 23.2 seconds
Started Jul 30 05:27:58 PM PDT 24
Finished Jul 30 05:28:21 PM PDT 24
Peak memory 220128 kb
Host smart-4cf205d1-e893-4389-92cb-6bd63a2f5330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886012344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.886012344
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2552047304
Short name T299
Test name
Test status
Simulation time 183190943 ps
CPU time 10.36 seconds
Started Jul 30 05:27:55 PM PDT 24
Finished Jul 30 05:28:05 PM PDT 24
Peak memory 220072 kb
Host smart-3cb9c84d-61d2-4117-94c2-1a2e0cfa6262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552047304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2552047304
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2025866224
Short name T167
Test name
Test status
Simulation time 1035718766 ps
CPU time 26.59 seconds
Started Jul 30 05:27:54 PM PDT 24
Finished Jul 30 05:28:21 PM PDT 24
Peak memory 219976 kb
Host smart-c38e9471-8f29-40df-b5ef-c9d5e5ebf1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025866224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2025866224
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4129577514
Short name T10
Test name
Test status
Simulation time 1027085384 ps
CPU time 10.14 seconds
Started Jul 30 05:28:00 PM PDT 24
Finished Jul 30 05:28:10 PM PDT 24
Peak memory 219128 kb
Host smart-b52ac95c-209c-40f9-a5fa-ea7302dbd965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129577514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4129577514
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1332461302
Short name T206
Test name
Test status
Simulation time 2817189516 ps
CPU time 156.23 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:30:41 PM PDT 24
Peak memory 234568 kb
Host smart-6bd96b2f-1d0f-4a29-9901-c989232e25a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332461302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1332461302
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1532312506
Short name T161
Test name
Test status
Simulation time 496646962 ps
CPU time 22.77 seconds
Started Jul 30 05:28:00 PM PDT 24
Finished Jul 30 05:28:23 PM PDT 24
Peak memory 220064 kb
Host smart-8cb1c5a4-4e46-4b47-9830-245a2281170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532312506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1532312506
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1745735937
Short name T286
Test name
Test status
Simulation time 267308244 ps
CPU time 12.25 seconds
Started Jul 30 05:28:00 PM PDT 24
Finished Jul 30 05:28:12 PM PDT 24
Peak memory 220032 kb
Host smart-4c814d3b-bcad-459b-9a72-687581f2e724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1745735937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1745735937
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1802629851
Short name T142
Test name
Test status
Simulation time 1439011369 ps
CPU time 24.54 seconds
Started Jul 30 05:27:59 PM PDT 24
Finished Jul 30 05:28:24 PM PDT 24
Peak memory 219988 kb
Host smart-96681cac-704c-4b42-8a30-16274d7b8bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802629851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1802629851
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1234372289
Short name T90
Test name
Test status
Simulation time 101815742936 ps
CPU time 1486.57 seconds
Started Jul 30 05:27:58 PM PDT 24
Finished Jul 30 05:52:45 PM PDT 24
Peak memory 238828 kb
Host smart-e4bb9d16-addf-4006-aaf4-cce724c300b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234372289 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1234372289
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2646612817
Short name T314
Test name
Test status
Simulation time 180140008 ps
CPU time 8.25 seconds
Started Jul 30 05:28:01 PM PDT 24
Finished Jul 30 05:28:09 PM PDT 24
Peak memory 218600 kb
Host smart-b3705767-ac2a-4f1a-9ef7-99f515e1db15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646612817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2646612817
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1633911852
Short name T185
Test name
Test status
Simulation time 54689423785 ps
CPU time 341.13 seconds
Started Jul 30 05:27:59 PM PDT 24
Finished Jul 30 05:33:40 PM PDT 24
Peak memory 230404 kb
Host smart-94009fcb-909d-4e5d-8d2f-f1c5a5267b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633911852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1633911852
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1306965246
Short name T283
Test name
Test status
Simulation time 7051847728 ps
CPU time 22.55 seconds
Started Jul 30 05:28:04 PM PDT 24
Finished Jul 30 05:28:27 PM PDT 24
Peak memory 220188 kb
Host smart-26f1e29f-c010-401d-a259-d33ae841da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306965246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1306965246
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1075393379
Short name T118
Test name
Test status
Simulation time 723189880 ps
CPU time 10.39 seconds
Started Jul 30 05:27:59 PM PDT 24
Finished Jul 30 05:28:10 PM PDT 24
Peak memory 220104 kb
Host smart-4d8e5f71-1f37-47d8-a3c5-e9be53b369ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075393379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1075393379
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2986253204
Short name T157
Test name
Test status
Simulation time 3330562498 ps
CPU time 39.89 seconds
Started Jul 30 05:27:59 PM PDT 24
Finished Jul 30 05:28:39 PM PDT 24
Peak memory 220048 kb
Host smart-f4213063-6b96-4a5a-b76c-2052202a74da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986253204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2986253204
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4022899327
Short name T170
Test name
Test status
Simulation time 989359704 ps
CPU time 10.09 seconds
Started Jul 30 05:28:03 PM PDT 24
Finished Jul 30 05:28:13 PM PDT 24
Peak memory 219000 kb
Host smart-e5bc88a0-e044-45d1-b59a-afb8778d0e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022899327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4022899327
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.320540242
Short name T178
Test name
Test status
Simulation time 37677202824 ps
CPU time 204.67 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:31:29 PM PDT 24
Peak memory 238084 kb
Host smart-c8f9022b-05bd-44ff-b9d6-05a4c29a9972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320540242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.320540242
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1077349038
Short name T145
Test name
Test status
Simulation time 193413572 ps
CPU time 10.3 seconds
Started Jul 30 05:28:07 PM PDT 24
Finished Jul 30 05:28:17 PM PDT 24
Peak memory 220048 kb
Host smart-62adcd52-0b77-42e7-9acf-0ca08583f31f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077349038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1077349038
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2062705924
Short name T182
Test name
Test status
Simulation time 1127876644 ps
CPU time 16.54 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:28:22 PM PDT 24
Peak memory 220100 kb
Host smart-8e3132e2-1568-42b5-b280-e515372a7a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062705924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2062705924
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2593779169
Short name T211
Test name
Test status
Simulation time 504386361 ps
CPU time 10.09 seconds
Started Jul 30 05:28:04 PM PDT 24
Finished Jul 30 05:28:14 PM PDT 24
Peak memory 219096 kb
Host smart-c50ad465-95cd-4c62-87cc-9e66ddbacb17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593779169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2593779169
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2322928919
Short name T13
Test name
Test status
Simulation time 6809970615 ps
CPU time 179.41 seconds
Started Jul 30 05:28:04 PM PDT 24
Finished Jul 30 05:31:03 PM PDT 24
Peak memory 238688 kb
Host smart-e89f726f-99fd-403a-a4a9-6262484d7885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322928919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2322928919
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3840195291
Short name T274
Test name
Test status
Simulation time 1183188177 ps
CPU time 22.42 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:28:28 PM PDT 24
Peak memory 220076 kb
Host smart-6d2b2d45-7abf-4153-9ccd-dd7529638048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840195291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3840195291
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2303709713
Short name T14
Test name
Test status
Simulation time 700368715 ps
CPU time 10.44 seconds
Started Jul 30 05:28:09 PM PDT 24
Finished Jul 30 05:28:20 PM PDT 24
Peak memory 220072 kb
Host smart-2efbdc9a-898a-4f0e-a0e4-18c35fbff614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303709713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2303709713
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1760328274
Short name T4
Test name
Test status
Simulation time 361118388 ps
CPU time 19.94 seconds
Started Jul 30 05:28:07 PM PDT 24
Finished Jul 30 05:28:27 PM PDT 24
Peak memory 219976 kb
Host smart-ba3430ee-453b-4b5d-91df-084eb781ba8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760328274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1760328274
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.887799204
Short name T289
Test name
Test status
Simulation time 1106190424 ps
CPU time 8.42 seconds
Started Jul 30 05:28:03 PM PDT 24
Finished Jul 30 05:28:12 PM PDT 24
Peak memory 218992 kb
Host smart-d443e57e-449f-4e05-b62f-9a02793bab08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887799204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.887799204
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3711558521
Short name T191
Test name
Test status
Simulation time 7726988358 ps
CPU time 221.61 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:31:46 PM PDT 24
Peak memory 220380 kb
Host smart-312b760e-e972-42ef-a969-e8fc1b73c1dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711558521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3711558521
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.863653932
Short name T271
Test name
Test status
Simulation time 355003054 ps
CPU time 19.63 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:28:25 PM PDT 24
Peak memory 220084 kb
Host smart-6fa20bfa-5a83-42d4-839b-c6b0ca5685bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863653932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.863653932
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2662112041
Short name T174
Test name
Test status
Simulation time 5054878699 ps
CPU time 12.39 seconds
Started Jul 30 05:28:06 PM PDT 24
Finished Jul 30 05:28:18 PM PDT 24
Peak memory 220236 kb
Host smart-dbcc3bb1-f6a2-4aa8-9e44-0ae9146e2538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662112041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2662112041
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.24684322
Short name T312
Test name
Test status
Simulation time 3551070607 ps
CPU time 34.84 seconds
Started Jul 30 05:28:05 PM PDT 24
Finished Jul 30 05:28:40 PM PDT 24
Peak memory 220140 kb
Host smart-ba38691e-98e9-4d02-aa04-047ae50d92ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24684322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.rom_ctrl_stress_all.24684322
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1407991328
Short name T49
Test name
Test status
Simulation time 20203094707 ps
CPU time 4427.9 seconds
Started Jul 30 05:28:04 PM PDT 24
Finished Jul 30 06:41:53 PM PDT 24
Peak memory 236648 kb
Host smart-4f736e40-1b49-4a76-a4d8-9e5cc598a984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407991328 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1407991328
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.286702674
Short name T220
Test name
Test status
Simulation time 1178601179 ps
CPU time 8.61 seconds
Started Jul 30 05:28:10 PM PDT 24
Finished Jul 30 05:28:19 PM PDT 24
Peak memory 219220 kb
Host smart-e285f14d-d647-4b15-b660-e077295abf06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286702674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.286702674
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1125906442
Short name T193
Test name
Test status
Simulation time 41570583745 ps
CPU time 259.78 seconds
Started Jul 30 05:28:07 PM PDT 24
Finished Jul 30 05:32:27 PM PDT 24
Peak memory 236588 kb
Host smart-1075e3be-f347-4cf0-923d-269baadb82cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125906442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1125906442
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1324401931
Short name T106
Test name
Test status
Simulation time 1982502096 ps
CPU time 22.58 seconds
Started Jul 30 05:28:11 PM PDT 24
Finished Jul 30 05:28:34 PM PDT 24
Peak memory 219544 kb
Host smart-a4b0ee2c-0f9c-43fa-9f53-c61f269c1b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324401931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1324401931
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.965347487
Short name T166
Test name
Test status
Simulation time 179104101 ps
CPU time 10.12 seconds
Started Jul 30 05:28:07 PM PDT 24
Finished Jul 30 05:28:17 PM PDT 24
Peak memory 220060 kb
Host smart-f6c7b19a-07f9-460a-b1a6-d2607eb09c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965347487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.965347487
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3199798018
Short name T160
Test name
Test status
Simulation time 685245890 ps
CPU time 24.43 seconds
Started Jul 30 05:28:08 PM PDT 24
Finished Jul 30 05:28:33 PM PDT 24
Peak memory 219984 kb
Host smart-044cbc53-79b7-486b-9e88-dbd4543a1174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199798018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3199798018
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4244104897
Short name T48
Test name
Test status
Simulation time 24956171788 ps
CPU time 2526.12 seconds
Started Jul 30 05:28:10 PM PDT 24
Finished Jul 30 06:10:17 PM PDT 24
Peak memory 232748 kb
Host smart-44c71c04-a7c1-4c6a-8db1-97ffb8b61683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244104897 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4244104897
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4261375865
Short name T224
Test name
Test status
Simulation time 176330369 ps
CPU time 8.82 seconds
Started Jul 30 05:28:11 PM PDT 24
Finished Jul 30 05:28:20 PM PDT 24
Peak memory 219196 kb
Host smart-a243e350-f4b7-4f34-9468-ba988d4e817d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261375865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4261375865
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.668771247
Short name T306
Test name
Test status
Simulation time 3888937174 ps
CPU time 114.38 seconds
Started Jul 30 05:28:10 PM PDT 24
Finished Jul 30 05:30:05 PM PDT 24
Peak memory 229356 kb
Host smart-0aecc5ec-a719-4194-99a0-51155e9d45eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668771247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.668771247
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4116288529
Short name T129
Test name
Test status
Simulation time 1027138111 ps
CPU time 21.94 seconds
Started Jul 30 05:28:12 PM PDT 24
Finished Jul 30 05:28:34 PM PDT 24
Peak memory 220044 kb
Host smart-21928584-9a26-4431-a16d-11564c55cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116288529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4116288529
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.746673556
Short name T225
Test name
Test status
Simulation time 354555123 ps
CPU time 10.58 seconds
Started Jul 30 05:28:08 PM PDT 24
Finished Jul 30 05:28:19 PM PDT 24
Peak memory 220084 kb
Host smart-d7ade63e-8804-4ca3-a3d7-5ccb8ad796bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746673556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.746673556
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2622858798
Short name T315
Test name
Test status
Simulation time 518988718 ps
CPU time 33.17 seconds
Started Jul 30 05:28:10 PM PDT 24
Finished Jul 30 05:28:44 PM PDT 24
Peak memory 219932 kb
Host smart-6a5d9c60-8ed1-443a-bca7-2bdea8ce9cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622858798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2622858798
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2847378694
Short name T5
Test name
Test status
Simulation time 2469183274 ps
CPU time 9.72 seconds
Started Jul 30 05:28:13 PM PDT 24
Finished Jul 30 05:28:23 PM PDT 24
Peak memory 219172 kb
Host smart-ca1807cd-3771-4d66-99dc-d5ffb272c61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847378694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2847378694
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3242765066
Short name T269
Test name
Test status
Simulation time 19124859820 ps
CPU time 408.65 seconds
Started Jul 30 05:28:12 PM PDT 24
Finished Jul 30 05:35:00 PM PDT 24
Peak memory 220348 kb
Host smart-15069b57-0acc-4097-9215-e08db3807df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242765066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3242765066
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4117597428
Short name T205
Test name
Test status
Simulation time 2052661285 ps
CPU time 22.91 seconds
Started Jul 30 05:28:09 PM PDT 24
Finished Jul 30 05:28:32 PM PDT 24
Peak memory 220116 kb
Host smart-92657a21-1884-4b17-bf50-fa0d2cfb02cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117597428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4117597428
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3162689284
Short name T303
Test name
Test status
Simulation time 276544628 ps
CPU time 10.28 seconds
Started Jul 30 05:28:08 PM PDT 24
Finished Jul 30 05:28:19 PM PDT 24
Peak memory 219984 kb
Host smart-94fb4748-9268-42dc-8ab4-7bcee49012a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162689284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3162689284
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3745098212
Short name T235
Test name
Test status
Simulation time 832493513 ps
CPU time 43.13 seconds
Started Jul 30 05:28:11 PM PDT 24
Finished Jul 30 05:28:55 PM PDT 24
Peak memory 219508 kb
Host smart-a2f93739-b73b-49bf-9115-8464aff25e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745098212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3745098212
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1103966380
Short name T45
Test name
Test status
Simulation time 196154033359 ps
CPU time 1840.38 seconds
Started Jul 30 05:28:14 PM PDT 24
Finished Jul 30 05:58:54 PM PDT 24
Peak memory 240948 kb
Host smart-fef0f4b4-58aa-4e52-abf6-ebb79ae593aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103966380 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1103966380
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3424313802
Short name T165
Test name
Test status
Simulation time 2742470480 ps
CPU time 8.11 seconds
Started Jul 30 05:28:14 PM PDT 24
Finished Jul 30 05:28:22 PM PDT 24
Peak memory 219244 kb
Host smart-1ed3275c-235b-4aca-b5ed-8dceb3b91db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424313802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3424313802
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1525309169
Short name T44
Test name
Test status
Simulation time 30832701283 ps
CPU time 269.84 seconds
Started Jul 30 05:28:11 PM PDT 24
Finished Jul 30 05:32:41 PM PDT 24
Peak memory 225480 kb
Host smart-f6c2811a-a322-428a-bad5-bd144dc27bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525309169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1525309169
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3359446108
Short name T258
Test name
Test status
Simulation time 1142954498 ps
CPU time 19.68 seconds
Started Jul 30 05:28:13 PM PDT 24
Finished Jul 30 05:28:33 PM PDT 24
Peak memory 220116 kb
Host smart-5d4b1782-863d-4aed-9787-643e4ef293b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359446108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3359446108
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.403109941
Short name T304
Test name
Test status
Simulation time 1748866128 ps
CPU time 10.3 seconds
Started Jul 30 05:28:14 PM PDT 24
Finished Jul 30 05:28:24 PM PDT 24
Peak memory 220064 kb
Host smart-bcd1b3f5-f7fb-40a4-9bb0-19a3342d978c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403109941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.403109941
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2507091265
Short name T73
Test name
Test status
Simulation time 1339219314 ps
CPU time 28.91 seconds
Started Jul 30 05:28:13 PM PDT 24
Finished Jul 30 05:28:42 PM PDT 24
Peak memory 220044 kb
Host smart-857d2836-0d49-46e6-a0dc-2e3b50cc815d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507091265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2507091265
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.62119712
Short name T272
Test name
Test status
Simulation time 487648300 ps
CPU time 8.44 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:27:05 PM PDT 24
Peak memory 219120 kb
Host smart-a8b3d81b-9680-430c-a67f-163689f56315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62119712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.62119712
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3115613344
Short name T37
Test name
Test status
Simulation time 9530671328 ps
CPU time 354.9 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:32:53 PM PDT 24
Peak memory 227436 kb
Host smart-68532fa2-10fb-4ca4-a131-0227187f2140
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115613344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3115613344
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2707251187
Short name T291
Test name
Test status
Simulation time 2362915264 ps
CPU time 19 seconds
Started Jul 30 05:26:59 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 220180 kb
Host smart-2840a3ed-eca8-4d25-8b41-01fada3d0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707251187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2707251187
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.327248889
Short name T276
Test name
Test status
Simulation time 1018276680 ps
CPU time 12.02 seconds
Started Jul 30 05:26:59 PM PDT 24
Finished Jul 30 05:27:11 PM PDT 24
Peak memory 219980 kb
Host smart-35f1ae4a-d508-421c-babd-03067dd2bcf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327248889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.327248889
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3906560441
Short name T177
Test name
Test status
Simulation time 1007605273 ps
CPU time 17.92 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:27:16 PM PDT 24
Peak memory 220132 kb
Host smart-55809d2f-47ae-4b31-8d0a-76b4f3d1d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906560441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3906560441
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1898622213
Short name T292
Test name
Test status
Simulation time 1742337798 ps
CPU time 20.45 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:27:17 PM PDT 24
Peak memory 220000 kb
Host smart-e2a52113-3b19-4ae2-84de-760e1a304d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898622213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1898622213
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.363147642
Short name T137
Test name
Test status
Simulation time 254280655 ps
CPU time 9.92 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:27:11 PM PDT 24
Peak memory 219112 kb
Host smart-5a85e4d3-abd4-46f3-adf0-773ac17b9d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363147642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.363147642
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3944335050
Short name T39
Test name
Test status
Simulation time 4574638468 ps
CPU time 152.7 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:29:34 PM PDT 24
Peak memory 220352 kb
Host smart-77ae14fc-a841-42bc-8798-a87ec8077276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944335050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3944335050
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3719020285
Short name T275
Test name
Test status
Simulation time 1033482853 ps
CPU time 19.44 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:22 PM PDT 24
Peak memory 220136 kb
Host smart-726dd27d-0365-44ed-8d83-d78d9e2017b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719020285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3719020285
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2843316689
Short name T147
Test name
Test status
Simulation time 265505929 ps
CPU time 12.48 seconds
Started Jul 30 05:27:00 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 220056 kb
Host smart-005ddde2-0a90-43a9-b19a-71deaa07fce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843316689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2843316689
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.52380636
Short name T281
Test name
Test status
Simulation time 265029424 ps
CPU time 12.11 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:27:09 PM PDT 24
Peak memory 220080 kb
Host smart-22ed7f4e-6ce1-495c-a61b-ef7e6bd44515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52380636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.52380636
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1231755532
Short name T236
Test name
Test status
Simulation time 944882819 ps
CPU time 19.87 seconds
Started Jul 30 05:26:57 PM PDT 24
Finished Jul 30 05:27:17 PM PDT 24
Peak memory 220016 kb
Host smart-12233598-17af-4ba2-9272-f5b821e29e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231755532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1231755532
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.563067930
Short name T264
Test name
Test status
Simulation time 1297797312 ps
CPU time 10.1 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:27:08 PM PDT 24
Peak memory 219208 kb
Host smart-a2426626-400a-497c-8083-50ae8510f059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563067930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.563067930
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.815078582
Short name T305
Test name
Test status
Simulation time 3957071747 ps
CPU time 270.3 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:31:31 PM PDT 24
Peak memory 239484 kb
Host smart-cb3552ff-2ae2-46bb-8fb8-d13414382e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815078582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.815078582
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2345304742
Short name T310
Test name
Test status
Simulation time 506376883 ps
CPU time 23.12 seconds
Started Jul 30 05:26:59 PM PDT 24
Finished Jul 30 05:27:23 PM PDT 24
Peak memory 220092 kb
Host smart-e2ee7cd8-203b-4ff1-9a26-b39450b5d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345304742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2345304742
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1815897873
Short name T187
Test name
Test status
Simulation time 179333069 ps
CPU time 10.23 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 219984 kb
Host smart-bd52c3e4-cae7-43f0-bd84-d507a6fa1477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815897873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1815897873
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2504431934
Short name T279
Test name
Test status
Simulation time 987172877 ps
CPU time 12.72 seconds
Started Jul 30 05:26:59 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 220036 kb
Host smart-be3eb2cf-4cb0-4660-859d-49488a509f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504431934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2504431934
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2387165482
Short name T319
Test name
Test status
Simulation time 1095960813 ps
CPU time 31.19 seconds
Started Jul 30 05:27:00 PM PDT 24
Finished Jul 30 05:27:31 PM PDT 24
Peak memory 219988 kb
Host smart-eb89a9ad-ee64-4e20-926f-b04d23bbd1c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387165482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2387165482
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1562167533
Short name T223
Test name
Test status
Simulation time 168407038 ps
CPU time 8.33 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:27:09 PM PDT 24
Peak memory 218980 kb
Host smart-7907613f-e91e-401f-b4d3-e7adae6ba40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562167533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1562167533
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2688024798
Short name T184
Test name
Test status
Simulation time 19615045444 ps
CPU time 296.41 seconds
Started Jul 30 05:27:03 PM PDT 24
Finished Jul 30 05:32:00 PM PDT 24
Peak memory 240764 kb
Host smart-e1161af0-95fe-44ed-854e-efb5f84d0dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688024798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2688024798
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1231322818
Short name T113
Test name
Test status
Simulation time 640138279 ps
CPU time 19.6 seconds
Started Jul 30 05:27:04 PM PDT 24
Finished Jul 30 05:27:24 PM PDT 24
Peak memory 219996 kb
Host smart-3e1f12d4-66fd-4008-9dfc-d648e1e02f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231322818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1231322818
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.237755518
Short name T109
Test name
Test status
Simulation time 4534626671 ps
CPU time 16.21 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 220160 kb
Host smart-26ebe5dd-90ff-459d-b7ba-83772f9618e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237755518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.237755518
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.226518254
Short name T158
Test name
Test status
Simulation time 261264399 ps
CPU time 12.2 seconds
Started Jul 30 05:26:56 PM PDT 24
Finished Jul 30 05:27:08 PM PDT 24
Peak memory 220004 kb
Host smart-2f1be6fb-6bd3-4149-aa1b-a065843e3e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226518254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.226518254
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2709695453
Short name T204
Test name
Test status
Simulation time 2455974107 ps
CPU time 30.76 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:27:30 PM PDT 24
Peak memory 220156 kb
Host smart-3446d659-95d2-4ca8-b45b-bc51433cce31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709695453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2709695453
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.922265906
Short name T29
Test name
Test status
Simulation time 505168942 ps
CPU time 9.84 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:12 PM PDT 24
Peak memory 219056 kb
Host smart-150872fa-b678-4a88-a4fe-e67a4e04e2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922265906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.922265906
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2885826593
Short name T18
Test name
Test status
Simulation time 16371503563 ps
CPU time 215.27 seconds
Started Jul 30 05:27:01 PM PDT 24
Finished Jul 30 05:30:36 PM PDT 24
Peak memory 225408 kb
Host smart-4c61ed73-012a-46d9-a91d-75b1f49fd04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885826593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2885826593
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3212124562
Short name T222
Test name
Test status
Simulation time 338877008 ps
CPU time 19.16 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:21 PM PDT 24
Peak memory 220112 kb
Host smart-189a536a-bfd2-4b47-a6a6-c22a9e4ce972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212124562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3212124562
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3240045182
Short name T246
Test name
Test status
Simulation time 539622520 ps
CPU time 12.64 seconds
Started Jul 30 05:27:03 PM PDT 24
Finished Jul 30 05:27:16 PM PDT 24
Peak memory 220080 kb
Host smart-ad64a6ee-4a7f-40f3-abb7-66f64e070f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240045182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3240045182
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.582648880
Short name T162
Test name
Test status
Simulation time 524454121 ps
CPU time 12.14 seconds
Started Jul 30 05:27:05 PM PDT 24
Finished Jul 30 05:27:18 PM PDT 24
Peak memory 219980 kb
Host smart-2f92ec63-0f77-48f2-bdbe-052bf3e331ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582648880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.582648880
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2506300441
Short name T32
Test name
Test status
Simulation time 829700968 ps
CPU time 39.92 seconds
Started Jul 30 05:27:02 PM PDT 24
Finished Jul 30 05:27:42 PM PDT 24
Peak memory 219912 kb
Host smart-c4c77dc0-f135-4b9f-a695-60e2d0d7b2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506300441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2506300441
Directory /workspace/9.rom_ctrl_stress_all/latest
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