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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.68 100.00 98.62 97.30 98.37


Total test records in report: 408
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T285 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.867920524 Jul 31 05:03:48 PM PDT 24 Jul 31 05:03:58 PM PDT 24 722377664 ps
T286 /workspace/coverage/default/25.rom_ctrl_stress_all.3610015817 Jul 31 05:04:05 PM PDT 24 Jul 31 05:04:32 PM PDT 24 283561469 ps
T287 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3214610230 Jul 31 05:04:04 PM PDT 24 Jul 31 05:04:27 PM PDT 24 989252676 ps
T288 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2012609554 Jul 31 05:03:52 PM PDT 24 Jul 31 05:04:04 PM PDT 24 266442964 ps
T289 /workspace/coverage/default/10.rom_ctrl_stress_all.2289575186 Jul 31 05:03:45 PM PDT 24 Jul 31 05:04:16 PM PDT 24 1084231928 ps
T290 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.989609482 Jul 31 05:03:49 PM PDT 24 Jul 31 05:08:24 PM PDT 24 5001169303 ps
T291 /workspace/coverage/default/49.rom_ctrl_alert_test.3169689927 Jul 31 05:04:06 PM PDT 24 Jul 31 05:04:24 PM PDT 24 174736766 ps
T292 /workspace/coverage/default/29.rom_ctrl_alert_test.2476808770 Jul 31 05:03:58 PM PDT 24 Jul 31 05:04:09 PM PDT 24 254031716 ps
T293 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2442478404 Jul 31 05:04:00 PM PDT 24 Jul 31 05:08:31 PM PDT 24 11422247869 ps
T294 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.292580237 Jul 31 05:04:04 PM PDT 24 Jul 31 05:04:14 PM PDT 24 683538237 ps
T295 /workspace/coverage/default/48.rom_ctrl_alert_test.1049030015 Jul 31 05:04:22 PM PDT 24 Jul 31 05:04:31 PM PDT 24 1648083181 ps
T296 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.975072432 Jul 31 05:04:01 PM PDT 24 Jul 31 05:04:13 PM PDT 24 1221159271 ps
T297 /workspace/coverage/default/33.rom_ctrl_alert_test.4223597799 Jul 31 05:03:59 PM PDT 24 Jul 31 05:04:09 PM PDT 24 993357156 ps
T298 /workspace/coverage/default/1.rom_ctrl_stress_all.3185547409 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:29 PM PDT 24 1020584319 ps
T299 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3015182427 Jul 31 05:04:01 PM PDT 24 Jul 31 05:04:12 PM PDT 24 183390883 ps
T300 /workspace/coverage/default/16.rom_ctrl_stress_all.1442847751 Jul 31 05:03:43 PM PDT 24 Jul 31 05:04:18 PM PDT 24 2245335994 ps
T301 /workspace/coverage/default/19.rom_ctrl_alert_test.291906646 Jul 31 05:04:01 PM PDT 24 Jul 31 05:04:11 PM PDT 24 956051716 ps
T302 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2617723840 Jul 31 05:03:46 PM PDT 24 Jul 31 05:05:36 PM PDT 24 2223680501 ps
T303 /workspace/coverage/default/12.rom_ctrl_stress_all.3924884215 Jul 31 05:03:29 PM PDT 24 Jul 31 05:04:21 PM PDT 24 3131723341 ps
T304 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.346788050 Jul 31 05:03:54 PM PDT 24 Jul 31 05:07:19 PM PDT 24 15369197621 ps
T305 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3327938272 Jul 31 05:03:58 PM PDT 24 Jul 31 05:07:48 PM PDT 24 3199100093 ps
T306 /workspace/coverage/default/16.rom_ctrl_alert_test.832429710 Jul 31 05:03:49 PM PDT 24 Jul 31 05:03:59 PM PDT 24 824332208 ps
T307 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3221619236 Jul 31 05:03:52 PM PDT 24 Jul 31 05:04:03 PM PDT 24 731453470 ps
T308 /workspace/coverage/default/27.rom_ctrl_alert_test.2360492643 Jul 31 05:04:11 PM PDT 24 Jul 31 05:04:22 PM PDT 24 514264604 ps
T309 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1968458918 Jul 31 05:04:07 PM PDT 24 Jul 31 05:04:19 PM PDT 24 261130974 ps
T310 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.207457410 Jul 31 05:04:14 PM PDT 24 Jul 31 05:04:37 PM PDT 24 2053090903 ps
T311 /workspace/coverage/default/38.rom_ctrl_alert_test.1929689106 Jul 31 05:04:08 PM PDT 24 Jul 31 05:04:18 PM PDT 24 986514064 ps
T312 /workspace/coverage/default/34.rom_ctrl_stress_all.416891158 Jul 31 05:04:02 PM PDT 24 Jul 31 05:04:51 PM PDT 24 1045392933 ps
T313 /workspace/coverage/default/28.rom_ctrl_stress_all.2405460465 Jul 31 05:03:59 PM PDT 24 Jul 31 05:04:26 PM PDT 24 368731644 ps
T314 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4011776284 Jul 31 05:04:06 PM PDT 24 Jul 31 05:04:26 PM PDT 24 332311888 ps
T59 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.114977066 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:53 PM PDT 24 2750835747 ps
T60 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3653882650 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:20 PM PDT 24 661982476 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1499351447 Jul 31 05:03:31 PM PDT 24 Jul 31 05:06:09 PM PDT 24 390884312 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.855304505 Jul 31 05:03:39 PM PDT 24 Jul 31 05:03:49 PM PDT 24 251126243 ps
T315 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1786807594 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:29 PM PDT 24 1504954929 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3552395762 Jul 31 05:03:09 PM PDT 24 Jul 31 05:04:31 PM PDT 24 496446433 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.880041492 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:32 PM PDT 24 167409242 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.260898231 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:26 PM PDT 24 700284151 ps
T316 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3366623535 Jul 31 05:03:29 PM PDT 24 Jul 31 05:03:41 PM PDT 24 176025145 ps
T317 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1532098772 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:23 PM PDT 24 298596450 ps
T318 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1072585715 Jul 31 05:03:10 PM PDT 24 Jul 31 05:03:18 PM PDT 24 173029665 ps
T319 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3583001737 Jul 31 05:03:10 PM PDT 24 Jul 31 05:03:19 PM PDT 24 193476590 ps
T83 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1388366109 Jul 31 05:03:31 PM PDT 24 Jul 31 05:03:41 PM PDT 24 496665579 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.884398548 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:26 PM PDT 24 179658522 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1467403763 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:21 PM PDT 24 662120339 ps
T320 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3082213097 Jul 31 05:03:55 PM PDT 24 Jul 31 05:04:06 PM PDT 24 275465331 ps
T321 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1720793987 Jul 31 05:03:24 PM PDT 24 Jul 31 05:03:37 PM PDT 24 515708219 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1917586697 Jul 31 05:03:36 PM PDT 24 Jul 31 05:05:01 PM PDT 24 1454372919 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2766088802 Jul 31 05:03:11 PM PDT 24 Jul 31 05:04:34 PM PDT 24 1294690628 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2943193458 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:21 PM PDT 24 261129896 ps
T84 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.944106437 Jul 31 05:03:23 PM PDT 24 Jul 31 05:03:38 PM PDT 24 5752237722 ps
T322 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1742509408 Jul 31 05:03:19 PM PDT 24 Jul 31 05:03:29 PM PDT 24 262573233 ps
T323 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2848716533 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:21 PM PDT 24 517158034 ps
T324 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1025485108 Jul 31 05:03:23 PM PDT 24 Jul 31 05:03:35 PM PDT 24 662526381 ps
T325 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1122209224 Jul 31 05:03:27 PM PDT 24 Jul 31 05:03:38 PM PDT 24 279261976 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1878142 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:23 PM PDT 24 172489789 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2586303542 Jul 31 05:03:20 PM PDT 24 Jul 31 05:04:18 PM PDT 24 1069027735 ps
T326 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4149617676 Jul 31 05:03:41 PM PDT 24 Jul 31 05:03:54 PM PDT 24 347953324 ps
T327 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2178367891 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:23 PM PDT 24 167347374 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2850704066 Jul 31 05:03:43 PM PDT 24 Jul 31 05:03:53 PM PDT 24 1030746235 ps
T328 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.433524125 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:27 PM PDT 24 1031478378 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.930110133 Jul 31 05:03:34 PM PDT 24 Jul 31 05:06:12 PM PDT 24 940230916 ps
T329 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2726931858 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:26 PM PDT 24 171714649 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3781691283 Jul 31 05:03:14 PM PDT 24 Jul 31 05:05:45 PM PDT 24 1292581992 ps
T330 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1147718945 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:21 PM PDT 24 174558028 ps
T68 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1403559130 Jul 31 05:03:22 PM PDT 24 Jul 31 05:03:33 PM PDT 24 514714878 ps
T331 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3773167583 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:22 PM PDT 24 1203826361 ps
T332 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3263946915 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:24 PM PDT 24 331722071 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.834783897 Jul 31 05:03:18 PM PDT 24 Jul 31 05:05:52 PM PDT 24 3350108745 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.148500713 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:23 PM PDT 24 753475508 ps
T333 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2324762717 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:26 PM PDT 24 661078957 ps
T334 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.408038872 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:22 PM PDT 24 507158174 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1076699679 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:21 PM PDT 24 660996950 ps
T335 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1950467025 Jul 31 05:03:08 PM PDT 24 Jul 31 05:03:19 PM PDT 24 187485365 ps
T336 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.133179642 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:26 PM PDT 24 174479775 ps
T337 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.436871650 Jul 31 05:03:25 PM PDT 24 Jul 31 05:03:34 PM PDT 24 185264981 ps
T338 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.20773792 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:26 PM PDT 24 530426648 ps
T339 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.479873342 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:28 PM PDT 24 278345514 ps
T340 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.884991047 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:23 PM PDT 24 259675755 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3248217828 Jul 31 05:03:11 PM PDT 24 Jul 31 05:04:36 PM PDT 24 1213611408 ps
T341 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1938455957 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:29 PM PDT 24 1012927612 ps
T342 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4216819410 Jul 31 05:03:34 PM PDT 24 Jul 31 05:03:46 PM PDT 24 345931709 ps
T343 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.239107540 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:26 PM PDT 24 172577585 ps
T71 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2103363510 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:26 PM PDT 24 231330691 ps
T344 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4026423751 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:22 PM PDT 24 172589756 ps
T345 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2404338926 Jul 31 05:03:22 PM PDT 24 Jul 31 05:03:37 PM PDT 24 4113425621 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2465694752 Jul 31 05:03:16 PM PDT 24 Jul 31 05:04:35 PM PDT 24 2128845783 ps
T346 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2692270558 Jul 31 05:03:24 PM PDT 24 Jul 31 05:03:34 PM PDT 24 332238351 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2972814088 Jul 31 05:03:29 PM PDT 24 Jul 31 05:03:37 PM PDT 24 661816225 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1461543583 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:25 PM PDT 24 989732682 ps
T348 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1710611856 Jul 31 05:03:08 PM PDT 24 Jul 31 05:03:16 PM PDT 24 872067353 ps
T349 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.290195174 Jul 31 05:03:20 PM PDT 24 Jul 31 05:03:30 PM PDT 24 275175162 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3705547811 Jul 31 05:03:09 PM PDT 24 Jul 31 05:05:48 PM PDT 24 787218774 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2185469058 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:30 PM PDT 24 214187478 ps
T350 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.589768664 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:22 PM PDT 24 183203741 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1287509362 Jul 31 05:03:23 PM PDT 24 Jul 31 05:04:07 PM PDT 24 4417630511 ps
T351 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3861874328 Jul 31 05:03:23 PM PDT 24 Jul 31 05:05:58 PM PDT 24 1963551242 ps
T352 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3647707035 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:23 PM PDT 24 248096269 ps
T353 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2219480519 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:24 PM PDT 24 1030443329 ps
T354 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3939069449 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:26 PM PDT 24 332020530 ps
T355 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2431207580 Jul 31 05:03:13 PM PDT 24 Jul 31 05:04:34 PM PDT 24 482630015 ps
T356 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4201636634 Jul 31 05:03:45 PM PDT 24 Jul 31 05:03:54 PM PDT 24 168384149 ps
T357 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1059083072 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:25 PM PDT 24 267775925 ps
T358 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2836173566 Jul 31 05:03:30 PM PDT 24 Jul 31 05:03:42 PM PDT 24 346031664 ps
T359 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3118866540 Jul 31 05:03:22 PM PDT 24 Jul 31 05:03:30 PM PDT 24 612059207 ps
T360 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1847728072 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:27 PM PDT 24 989396575 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.120244734 Jul 31 05:03:10 PM PDT 24 Jul 31 05:05:37 PM PDT 24 308293711 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.12899770 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:24 PM PDT 24 169347812 ps
T362 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.779314228 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:22 PM PDT 24 711791953 ps
T363 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3693305673 Jul 31 05:03:22 PM PDT 24 Jul 31 05:03:30 PM PDT 24 172697834 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.334627034 Jul 31 05:03:30 PM PDT 24 Jul 31 05:04:55 PM PDT 24 2161408788 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1704139739 Jul 31 05:03:11 PM PDT 24 Jul 31 05:03:28 PM PDT 24 1166519669 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3736704482 Jul 31 05:03:43 PM PDT 24 Jul 31 05:03:51 PM PDT 24 171740874 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.870041894 Jul 31 05:03:32 PM PDT 24 Jul 31 05:03:44 PM PDT 24 167627866 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1348146668 Jul 31 05:03:34 PM PDT 24 Jul 31 05:03:42 PM PDT 24 332593869 ps
T368 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.163683362 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:24 PM PDT 24 2187253687 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.205651789 Jul 31 05:03:35 PM PDT 24 Jul 31 05:03:44 PM PDT 24 662075854 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.845472961 Jul 31 05:03:23 PM PDT 24 Jul 31 05:03:32 PM PDT 24 702856553 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3476933551 Jul 31 05:03:28 PM PDT 24 Jul 31 05:03:41 PM PDT 24 281056541 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.53351372 Jul 31 05:03:37 PM PDT 24 Jul 31 05:03:48 PM PDT 24 264315818 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4076936479 Jul 31 05:03:16 PM PDT 24 Jul 31 05:03:24 PM PDT 24 615678349 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3735147337 Jul 31 05:03:32 PM PDT 24 Jul 31 05:03:42 PM PDT 24 259964736 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3204265386 Jul 31 05:03:32 PM PDT 24 Jul 31 05:04:54 PM PDT 24 987572877 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2935584663 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:22 PM PDT 24 176620292 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2682525151 Jul 31 05:03:31 PM PDT 24 Jul 31 05:03:42 PM PDT 24 543086464 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.465852235 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:27 PM PDT 24 2015239010 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1364880562 Jul 31 05:03:14 PM PDT 24 Jul 31 05:03:25 PM PDT 24 980113197 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2444434809 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:23 PM PDT 24 948771412 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.447531757 Jul 31 05:03:14 PM PDT 24 Jul 31 05:04:37 PM PDT 24 653702850 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1043834328 Jul 31 05:03:20 PM PDT 24 Jul 31 05:03:30 PM PDT 24 508253433 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2124814972 Jul 31 05:03:31 PM PDT 24 Jul 31 05:06:06 PM PDT 24 625627189 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2625318337 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:23 PM PDT 24 1800107069 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1737691182 Jul 31 05:03:11 PM PDT 24 Jul 31 05:05:45 PM PDT 24 426921881 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1278061095 Jul 31 05:03:13 PM PDT 24 Jul 31 05:03:23 PM PDT 24 249118615 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2150412559 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:26 PM PDT 24 340288861 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2939654595 Jul 31 05:03:20 PM PDT 24 Jul 31 05:03:37 PM PDT 24 752684514 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3806530957 Jul 31 05:03:39 PM PDT 24 Jul 31 05:03:49 PM PDT 24 254802112 ps
T389 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2829970220 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:25 PM PDT 24 260934062 ps
T390 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1378972393 Jul 31 05:03:16 PM PDT 24 Jul 31 05:03:29 PM PDT 24 1027783404 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4084116220 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:31 PM PDT 24 1027675693 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3905796211 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:28 PM PDT 24 167787670 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1762104939 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:27 PM PDT 24 225507953 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1319562675 Jul 31 05:03:18 PM PDT 24 Jul 31 05:03:28 PM PDT 24 517764730 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3626746035 Jul 31 05:03:41 PM PDT 24 Jul 31 05:05:04 PM PDT 24 840619531 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.95033008 Jul 31 05:03:21 PM PDT 24 Jul 31 05:05:53 PM PDT 24 293690119 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2759836625 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:24 PM PDT 24 515074948 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.220832651 Jul 31 05:03:16 PM PDT 24 Jul 31 05:03:24 PM PDT 24 169222845 ps
T399 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3627019273 Jul 31 05:03:25 PM PDT 24 Jul 31 05:03:39 PM PDT 24 1383437897 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4258820491 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:26 PM PDT 24 3091150192 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.660589113 Jul 31 05:03:10 PM PDT 24 Jul 31 05:03:25 PM PDT 24 259201407 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.857188236 Jul 31 05:03:10 PM PDT 24 Jul 31 05:03:18 PM PDT 24 665652064 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2113383426 Jul 31 05:03:10 PM PDT 24 Jul 31 05:03:19 PM PDT 24 370542084 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1635708661 Jul 31 05:03:23 PM PDT 24 Jul 31 05:03:33 PM PDT 24 169521021 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.606657586 Jul 31 05:03:17 PM PDT 24 Jul 31 05:03:26 PM PDT 24 641107326 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3675824740 Jul 31 05:03:09 PM PDT 24 Jul 31 05:03:24 PM PDT 24 10887582355 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.407167403 Jul 31 05:03:15 PM PDT 24 Jul 31 05:03:25 PM PDT 24 992618284 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3371333630 Jul 31 05:03:12 PM PDT 24 Jul 31 05:03:28 PM PDT 24 1542572488 ps
T408 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.304360885 Jul 31 05:03:28 PM PDT 24 Jul 31 05:03:38 PM PDT 24 1029138984 ps

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3292492913
Short name T7
Test name
Test status
Simulation time 222008477787 ps
CPU time 2164.84 seconds
Started Jul 31 05:03:56 PM PDT 24
Finished Jul 31 05:40:01 PM PDT 24
Peak memory 244740 kb
Host smart-55e8f15b-dcf9-48fe-bb27-283513a5e057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292492913 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3292492913
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4014067255
Short name T16
Test name
Test status
Simulation time 4908088092 ps
CPU time 335.83 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:09:42 PM PDT 24
Peak memory 240636 kb
Host smart-57de24f6-bce1-4d01-8ca1-c4e37ae4b4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014067255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4014067255
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1499351447
Short name T56
Test name
Test status
Simulation time 390884312 ps
CPU time 157.69 seconds
Started Jul 31 05:03:31 PM PDT 24
Finished Jul 31 05:06:09 PM PDT 24
Peak memory 219016 kb
Host smart-c00a23b3-ddaa-4912-bf5f-156fb26a862a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499351447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1499351447
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1376316220
Short name T44
Test name
Test status
Simulation time 5084936346 ps
CPU time 240.39 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:07:25 PM PDT 24
Peak memory 236600 kb
Host smart-4d6d8171-b56d-45e5-ba27-6e2439084d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376316220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1376316220
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3921582322
Short name T11
Test name
Test status
Simulation time 255813959516 ps
CPU time 2966.37 seconds
Started Jul 31 05:03:36 PM PDT 24
Finished Jul 31 05:53:03 PM PDT 24
Peak memory 248108 kb
Host smart-3b39e076-60cd-4173-8102-b00708c9f26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921582322 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3921582322
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.161961037
Short name T15
Test name
Test status
Simulation time 36450682844 ps
CPU time 204.68 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:07:03 PM PDT 24
Peak memory 238368 kb
Host smart-39486bd2-469d-4644-b699-1edb23e9615d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161961037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.161961037
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3269744226
Short name T21
Test name
Test status
Simulation time 612768827 ps
CPU time 117.37 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:05:31 PM PDT 24
Peak memory 240096 kb
Host smart-a071cb7d-5273-4004-80f2-545c137be773
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269744226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3269744226
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3705547811
Short name T101
Test name
Test status
Simulation time 787218774 ps
CPU time 158.9 seconds
Started Jul 31 05:03:09 PM PDT 24
Finished Jul 31 05:05:48 PM PDT 24
Peak memory 215572 kb
Host smart-5a78d604-5178-4661-ba2e-5530e5139e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705547811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3705547811
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.114977066
Short name T59
Test name
Test status
Simulation time 2750835747 ps
CPU time 37.78 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:53 PM PDT 24
Peak memory 214044 kb
Host smart-b47c544a-7d02-435d-80c9-e559c09aac14
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114977066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.114977066
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2972814088
Short name T79
Test name
Test status
Simulation time 661816225 ps
CPU time 8.01 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 211004 kb
Host smart-38a0f221-f00e-4e73-a07d-4eed33312393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972814088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2972814088
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1487977057
Short name T9
Test name
Test status
Simulation time 259671069 ps
CPU time 9.94 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:03:38 PM PDT 24
Peak memory 218960 kb
Host smart-16053334-fe57-4a7c-97e1-b8166e8ac674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487977057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1487977057
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2550509102
Short name T25
Test name
Test status
Simulation time 2026983557 ps
CPU time 33.53 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 219428 kb
Host smart-e8f49845-bcac-40aa-8479-c4bba223be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550509102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2550509102
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2411128176
Short name T41
Test name
Test status
Simulation time 342954122 ps
CPU time 19.2 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:36 PM PDT 24
Peak memory 220040 kb
Host smart-20d6304d-a909-47c4-bceb-f8d7915003a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411128176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2411128176
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3947210286
Short name T47
Test name
Test status
Simulation time 2023081154 ps
CPU time 31.67 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 219944 kb
Host smart-b0b76181-fd32-40c8-9069-fe75dd2b165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947210286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3947210286
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.95033008
Short name T396
Test name
Test status
Simulation time 293690119 ps
CPU time 152.47 seconds
Started Jul 31 05:03:21 PM PDT 24
Finished Jul 31 05:05:53 PM PDT 24
Peak memory 213416 kb
Host smart-aba05418-a0ec-413b-a44c-0d711d839c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95033008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.95033008
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3211317040
Short name T10
Test name
Test status
Simulation time 794652709 ps
CPU time 10.73 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:03:56 PM PDT 24
Peak memory 220004 kb
Host smart-95320cfc-2006-4adb-92bd-fcae2ae2dac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211317040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3211317040
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3185689711
Short name T77
Test name
Test status
Simulation time 206866018 ps
CPU time 11.46 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 219952 kb
Host smart-e9885230-c6ae-4775-bea4-30ea7e195b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185689711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3185689711
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2404338926
Short name T345
Test name
Test status
Simulation time 4113425621 ps
CPU time 14.92 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 211116 kb
Host smart-41c4d951-b238-4bd4-9396-934ec32242d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404338926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2404338926
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2444434809
Short name T380
Test name
Test status
Simulation time 948771412 ps
CPU time 10.12 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210776 kb
Host smart-05bc3a15-ec4a-4a86-9cc8-15ee081760c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444434809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2444434809
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1704139739
Short name T364
Test name
Test status
Simulation time 1166519669 ps
CPU time 16.7 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 210812 kb
Host smart-fa73e9ac-7ec4-4a2e-b0f6-ec23610c923f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704139739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1704139739
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2625318337
Short name T383
Test name
Test status
Simulation time 1800107069 ps
CPU time 10.06 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 214272 kb
Host smart-4e27f349-e1b5-436a-b488-2e29d09457bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625318337 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2625318337
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1742509408
Short name T322
Test name
Test status
Simulation time 262573233 ps
CPU time 10.05 seconds
Started Jul 31 05:03:19 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 210980 kb
Host smart-aec8f109-b3b5-4bf9-9833-5d2228343909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742509408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1742509408
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3647707035
Short name T352
Test name
Test status
Simulation time 248096269 ps
CPU time 9.65 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210620 kb
Host smart-c591b2b4-bb21-4aa9-904f-30624f7ca734
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647707035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3647707035
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.884991047
Short name T340
Test name
Test status
Simulation time 259675755 ps
CPU time 9.61 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210636 kb
Host smart-e8f75228-7dbb-4743-81fc-5105edc4ffab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884991047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
884991047
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2113383426
Short name T403
Test name
Test status
Simulation time 370542084 ps
CPU time 8.45 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 211668 kb
Host smart-2f055e1a-e824-4927-9c92-0413bcbaa89b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113383426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2113383426
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.12899770
Short name T361
Test name
Test status
Simulation time 169347812 ps
CPU time 11.75 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 217584 kb
Host smart-738c662c-ecc1-47f9-8d23-0026ac470cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.12899770
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2848716533
Short name T323
Test name
Test status
Simulation time 517158034 ps
CPU time 9.8 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 211056 kb
Host smart-738431d5-b41e-43f0-b974-269c8e54dd8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848716533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2848716533
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3735147337
Short name T374
Test name
Test status
Simulation time 259964736 ps
CPU time 10.45 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:03:42 PM PDT 24
Peak memory 210824 kb
Host smart-f9385392-e60c-4004-81e5-097940ea9c06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735147337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3735147337
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3371333630
Short name T407
Test name
Test status
Simulation time 1542572488 ps
CPU time 15.2 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 212408 kb
Host smart-6db670fd-0df1-45fe-9a36-56729669832d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371333630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3371333630
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.20773792
Short name T338
Test name
Test status
Simulation time 530426648 ps
CPU time 10.75 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 217580 kb
Host smart-20ffd1ca-229d-487d-8e3a-97edbd05a4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20773792 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.20773792
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1467403763
Short name T88
Test name
Test status
Simulation time 662120339 ps
CPU time 8.14 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 210764 kb
Host smart-c297ec93-5cc7-4068-beef-d247ffb10027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467403763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1467403763
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1072585715
Short name T318
Test name
Test status
Simulation time 173029665 ps
CPU time 8.17 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:18 PM PDT 24
Peak memory 210660 kb
Host smart-32eed579-9d96-41c8-af17-dcf5d200ef21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072585715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1072585715
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.220832651
Short name T398
Test name
Test status
Simulation time 169222845 ps
CPU time 8.01 seconds
Started Jul 31 05:03:16 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 210644 kb
Host smart-a43e2d36-8685-4e06-a5e1-fa0ab3df5d05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220832651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
220832651
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.53351372
Short name T372
Test name
Test status
Simulation time 264315818 ps
CPU time 10.09 seconds
Started Jul 31 05:03:37 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 211656 kb
Host smart-256c299e-1f86-438f-a9ea-73dbc016bfa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53351372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.53351372
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4216819410
Short name T342
Test name
Test status
Simulation time 345931709 ps
CPU time 12.46 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 219044 kb
Host smart-849b63d3-b72d-456b-8185-8b5301910bde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216819410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4216819410
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3552395762
Short name T57
Test name
Test status
Simulation time 496446433 ps
CPU time 81.17 seconds
Started Jul 31 05:03:09 PM PDT 24
Finished Jul 31 05:04:31 PM PDT 24
Peak memory 213036 kb
Host smart-f019251c-6f8b-40b7-bb75-ec74248ecdb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552395762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3552395762
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3773167583
Short name T331
Test name
Test status
Simulation time 1203826361 ps
CPU time 10.05 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 215248 kb
Host smart-933a5cf2-c27a-4ddf-9d78-256def06dad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773167583 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3773167583
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.304360885
Short name T408
Test name
Test status
Simulation time 1029138984 ps
CPU time 10.24 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:03:38 PM PDT 24
Peak memory 210980 kb
Host smart-d879f0ee-53ed-44ad-9e60-cb73c934fef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304360885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.304360885
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.944106437
Short name T84
Test name
Test status
Simulation time 5752237722 ps
CPU time 14.53 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:38 PM PDT 24
Peak memory 211612 kb
Host smart-10fffbb5-cfc4-4a8f-ab6f-a2f1f19ff482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944106437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.944106437
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.660589113
Short name T401
Test name
Test status
Simulation time 259201407 ps
CPU time 14.7 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 217824 kb
Host smart-4749535e-79e4-4abd-96cc-b7623a004c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660589113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.660589113
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2431207580
Short name T355
Test name
Test status
Simulation time 482630015 ps
CPU time 80.64 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:04:34 PM PDT 24
Peak memory 213980 kb
Host smart-97a1ea69-75b2-4d59-b4a1-98e3dc5365b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431207580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2431207580
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.845472961
Short name T370
Test name
Test status
Simulation time 702856553 ps
CPU time 8.67 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:32 PM PDT 24
Peak memory 216212 kb
Host smart-19134870-9396-4b02-af0a-2eeada486d59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845472961 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.845472961
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.855304505
Short name T63
Test name
Test status
Simulation time 251126243 ps
CPU time 9.99 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:03:49 PM PDT 24
Peak memory 211364 kb
Host smart-eb4166ed-b53f-4f6f-81fe-0dbc4ac3fe63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855304505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.855304505
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1878142
Short name T66
Test name
Test status
Simulation time 172489789 ps
CPU time 11.57 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 211472 kb
Host smart-9c155cb9-7dd0-4656-8dbf-084cdd0a7804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctr
l_same_csr_outstanding.1878142
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3476933551
Short name T371
Test name
Test status
Simulation time 281056541 ps
CPU time 12.92 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:03:41 PM PDT 24
Peak memory 217620 kb
Host smart-609f4629-51a5-4640-828e-243a8788403c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476933551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3476933551
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2124814972
Short name T382
Test name
Test status
Simulation time 625627189 ps
CPU time 155.18 seconds
Started Jul 31 05:03:31 PM PDT 24
Finished Jul 31 05:06:06 PM PDT 24
Peak memory 214380 kb
Host smart-c21617ec-c773-44ef-a94f-08b199dfb1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124814972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2124814972
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.606657586
Short name T405
Test name
Test status
Simulation time 641107326 ps
CPU time 8.64 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 217052 kb
Host smart-4e81cd62-ea8b-40be-a999-8c221fd41fd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606657586 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.606657586
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.148500713
Short name T69
Test name
Test status
Simulation time 753475508 ps
CPU time 8.2 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210948 kb
Host smart-dc64f1a1-0174-41e0-814a-ecde6e8c09a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148500713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.148500713
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.465852235
Short name T378
Test name
Test status
Simulation time 2015239010 ps
CPU time 14.69 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:27 PM PDT 24
Peak memory 211692 kb
Host smart-c908cc02-6796-420f-8520-8924823276b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465852235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.465852235
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.870041894
Short name T366
Test name
Test status
Simulation time 167627866 ps
CPU time 12.61 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 219060 kb
Host smart-a5ab2f5e-7cd2-4861-9bb1-23bb0991beb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870041894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.870041894
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3248217828
Short name T99
Test name
Test status
Simulation time 1213611408 ps
CPU time 84.12 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:04:36 PM PDT 24
Peak memory 213820 kb
Host smart-a7d1e828-6bb1-4ba4-8252-c2ff8dcbd3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248217828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3248217828
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.205651789
Short name T369
Test name
Test status
Simulation time 662075854 ps
CPU time 8.96 seconds
Started Jul 31 05:03:35 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 217268 kb
Host smart-6feb8912-f38a-45cb-8a85-d3f828157656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205651789 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.205651789
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3939069449
Short name T354
Test name
Test status
Simulation time 332020530 ps
CPU time 8.12 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 210864 kb
Host smart-323645d8-2eba-4bc4-bab1-60b54522227a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939069449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3939069449
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.407167403
Short name T406
Test name
Test status
Simulation time 992618284 ps
CPU time 9.9 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 211704 kb
Host smart-66854181-3a16-4ff1-9191-798822233e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407167403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.407167403
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2692270558
Short name T346
Test name
Test status
Simulation time 332238351 ps
CPU time 10.67 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:03:34 PM PDT 24
Peak memory 219012 kb
Host smart-b22c3d4d-8c6e-4b29-9333-8eb43a5c4e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692270558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2692270558
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2465694752
Short name T102
Test name
Test status
Simulation time 2128845783 ps
CPU time 78.64 seconds
Started Jul 31 05:03:16 PM PDT 24
Finished Jul 31 05:04:35 PM PDT 24
Peak memory 212888 kb
Host smart-8720b174-779f-4b13-b262-e353316301c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465694752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2465694752
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.589768664
Short name T350
Test name
Test status
Simulation time 183203741 ps
CPU time 9.25 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 217504 kb
Host smart-492e0760-431d-41d4-b6f9-ef7f1d2d31ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589768664 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.589768664
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.880041492
Short name T64
Test name
Test status
Simulation time 167409242 ps
CPU time 7.93 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:32 PM PDT 24
Peak memory 210984 kb
Host smart-25b6070c-862d-4580-aeed-9a59a44656ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880041492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.880041492
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2219480519
Short name T353
Test name
Test status
Simulation time 1030443329 ps
CPU time 9.98 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 211400 kb
Host smart-6cc85b43-f9d5-48cb-967c-af08af18b677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219480519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2219480519
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1720793987
Short name T321
Test name
Test status
Simulation time 515708219 ps
CPU time 12.9 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 219052 kb
Host smart-e9dba0d8-7d58-4227-8fe4-541dc84a6d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720793987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1720793987
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.834783897
Short name T100
Test name
Test status
Simulation time 3350108745 ps
CPU time 154.17 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:05:52 PM PDT 24
Peak memory 214384 kb
Host smart-224d13b8-2d48-490b-b39f-961f0fc11eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834783897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.834783897
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1122209224
Short name T325
Test name
Test status
Simulation time 279261976 ps
CPU time 11.18 seconds
Started Jul 31 05:03:27 PM PDT 24
Finished Jul 31 05:03:38 PM PDT 24
Peak memory 216680 kb
Host smart-f4eb1fa8-94ae-47dd-8f0b-0e86b4c26f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122209224 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1122209224
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3693305673
Short name T363
Test name
Test status
Simulation time 172697834 ps
CPU time 8.02 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:30 PM PDT 24
Peak memory 210852 kb
Host smart-3bed0741-5ef0-47b2-9795-b2dd499485ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693305673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3693305673
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1278061095
Short name T385
Test name
Test status
Simulation time 249118615 ps
CPU time 9.9 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 211196 kb
Host smart-3f5ecb66-d571-4cfd-95f1-3298bb9eeb80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278061095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1278061095
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3366623535
Short name T316
Test name
Test status
Simulation time 176025145 ps
CPU time 11.65 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:41 PM PDT 24
Peak memory 219164 kb
Host smart-35fbf392-fed2-4d00-be17-3aeb19afd003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366623535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3366623535
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1950467025
Short name T335
Test name
Test status
Simulation time 187485365 ps
CPU time 10.49 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 217688 kb
Host smart-bfd1c9ac-b8eb-480d-af21-7fbddc4da511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950467025 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1950467025
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4026423751
Short name T344
Test name
Test status
Simulation time 172589756 ps
CPU time 8.16 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 210748 kb
Host smart-2a7ce56a-fb35-481b-8d88-8a29c8eace0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026423751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4026423751
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2150412559
Short name T386
Test name
Test status
Simulation time 340288861 ps
CPU time 8.29 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 211564 kb
Host smart-4159faa5-63f2-4a49-aa28-1c00a3a00a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150412559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2150412559
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1378972393
Short name T390
Test name
Test status
Simulation time 1027783404 ps
CPU time 13.13 seconds
Started Jul 31 05:03:16 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 219160 kb
Host smart-8c7be444-43af-4296-bc98-68335d3230bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378972393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1378972393
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3781691283
Short name T98
Test name
Test status
Simulation time 1292581992 ps
CPU time 150.72 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:05:45 PM PDT 24
Peak memory 214360 kb
Host smart-12c2cf78-b92d-4a4d-8a61-04ad62c0998e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781691283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3781691283
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.436871650
Short name T337
Test name
Test status
Simulation time 185264981 ps
CPU time 8.84 seconds
Started Jul 31 05:03:25 PM PDT 24
Finished Jul 31 05:03:34 PM PDT 24
Peak memory 216316 kb
Host smart-7b994400-a274-43ae-b97f-645dcb7e7ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436871650 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.436871650
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2829970220
Short name T389
Test name
Test status
Simulation time 260934062 ps
CPU time 9.86 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 210864 kb
Host smart-fedef2f3-33cc-468b-8ce3-ced2ab171cd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829970220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2829970220
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2586303542
Short name T67
Test name
Test status
Simulation time 1069027735 ps
CPU time 57.73 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 214312 kb
Host smart-c74f9a84-34f4-4534-a1ef-d3cc88206435
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586303542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2586303542
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2850704066
Short name T85
Test name
Test status
Simulation time 1030746235 ps
CPU time 10.24 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:03:53 PM PDT 24
Peak memory 211692 kb
Host smart-b583fccb-0f06-4353-9f77-09daf98a7b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850704066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2850704066
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1025485108
Short name T324
Test name
Test status
Simulation time 662526381 ps
CPU time 12.06 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:35 PM PDT 24
Peak memory 217740 kb
Host smart-1a3af460-0fc0-4328-90e9-7c24be588114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025485108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1025485108
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3861874328
Short name T351
Test name
Test status
Simulation time 1963551242 ps
CPU time 154.81 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:05:58 PM PDT 24
Peak memory 214312 kb
Host smart-5a1f55a9-ea2b-427d-82d1-56ac209175f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861874328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3861874328
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3806530957
Short name T388
Test name
Test status
Simulation time 254802112 ps
CPU time 10.29 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:03:49 PM PDT 24
Peak memory 214016 kb
Host smart-9687929c-28e0-418a-9614-654d4fef813c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806530957 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3806530957
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3736704482
Short name T365
Test name
Test status
Simulation time 171740874 ps
CPU time 8.28 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:03:51 PM PDT 24
Peak memory 210772 kb
Host smart-6b554c60-c693-4115-a2b6-a5afd425464c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736704482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3736704482
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1388366109
Short name T83
Test name
Test status
Simulation time 496665579 ps
CPU time 9.87 seconds
Started Jul 31 05:03:31 PM PDT 24
Finished Jul 31 05:03:41 PM PDT 24
Peak memory 211544 kb
Host smart-4da406a4-9ad6-4296-bd8a-4b741bc73879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388366109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1388366109
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2939654595
Short name T387
Test name
Test status
Simulation time 752684514 ps
CPU time 12.41 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 218980 kb
Host smart-45cf0d9a-5cf7-4f9e-b769-34723d3f4c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939654595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2939654595
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3626746035
Short name T395
Test name
Test status
Simulation time 840619531 ps
CPU time 82.93 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:05:04 PM PDT 24
Peak memory 212900 kb
Host smart-df8e467b-9c15-4b1b-85ae-76a6eddfff49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626746035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3626746035
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3082213097
Short name T320
Test name
Test status
Simulation time 275465331 ps
CPU time 10.68 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 216080 kb
Host smart-a2b37904-d8b3-42bf-a4b1-cfd07719cb3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082213097 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3082213097
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4201636634
Short name T356
Test name
Test status
Simulation time 168384149 ps
CPU time 8.33 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 211420 kb
Host smart-f9941028-75d0-41e3-9a46-fd7d82200404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201636634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4201636634
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2836173566
Short name T358
Test name
Test status
Simulation time 346031664 ps
CPU time 11.72 seconds
Started Jul 31 05:03:30 PM PDT 24
Finished Jul 31 05:03:42 PM PDT 24
Peak memory 217720 kb
Host smart-27f9c58a-b084-4eb0-8dd0-7ccc5485ffc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836173566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2836173566
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.930110133
Short name T97
Test name
Test status
Simulation time 940230916 ps
CPU time 157.84 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:06:12 PM PDT 24
Peak memory 219132 kb
Host smart-a57127b8-ac70-4307-ae24-4eca76c4d0af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930110133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.930110133
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3675824740
Short name T82
Test name
Test status
Simulation time 10887582355 ps
CPU time 14.91 seconds
Started Jul 31 05:03:09 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 211544 kb
Host smart-18213faa-a951-403d-865d-d6bba1db36c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675824740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3675824740
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2178367891
Short name T327
Test name
Test status
Simulation time 167347374 ps
CPU time 8.59 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210904 kb
Host smart-6a964a76-32a7-497a-9c8f-371758fa5c53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178367891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2178367891
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.884398548
Short name T87
Test name
Test status
Simulation time 179658522 ps
CPU time 11.67 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 210676 kb
Host smart-28379ebc-5760-4369-8c91-07fc445b880c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884398548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.884398548
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2682525151
Short name T377
Test name
Test status
Simulation time 543086464 ps
CPU time 10.86 seconds
Started Jul 31 05:03:31 PM PDT 24
Finished Jul 31 05:03:42 PM PDT 24
Peak memory 217156 kb
Host smart-2dd75a1c-1ba3-464f-9d86-cbb8671611bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682525151 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2682525151
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2324762717
Short name T333
Test name
Test status
Simulation time 661078957 ps
CPU time 8.02 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 211112 kb
Host smart-75d3d8c8-33db-4580-9fec-4eeeae7941b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324762717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2324762717
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1348146668
Short name T367
Test name
Test status
Simulation time 332593869 ps
CPU time 8.14 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:42 PM PDT 24
Peak memory 210660 kb
Host smart-11466450-ef52-4498-adf1-1ab7ba5e17f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348146668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1348146668
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.133179642
Short name T336
Test name
Test status
Simulation time 174479775 ps
CPU time 8.31 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 210780 kb
Host smart-234d6e99-a94d-49c5-a1a8-c91d43202ab9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133179642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
133179642
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2103363510
Short name T71
Test name
Test status
Simulation time 231330691 ps
CPU time 8.55 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 211516 kb
Host smart-42afc0de-045c-44c2-bc48-30da6f2ec9c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103363510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2103363510
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3905796211
Short name T392
Test name
Test status
Simulation time 167787670 ps
CPU time 11.32 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 219024 kb
Host smart-22667a84-8d6b-48e4-9be8-566dda1d9c57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905796211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3905796211
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2766088802
Short name T104
Test name
Test status
Simulation time 1294690628 ps
CPU time 82.98 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:04:34 PM PDT 24
Peak memory 214044 kb
Host smart-2b58695c-00be-44e3-8920-ea4fe08060d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766088802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2766088802
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1076699679
Short name T70
Test name
Test status
Simulation time 660996950 ps
CPU time 8.18 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 210744 kb
Host smart-264a3273-9f73-46be-94dd-ba044ee01ed1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076699679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1076699679
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1461543583
Short name T347
Test name
Test status
Simulation time 989732682 ps
CPU time 14.55 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 210804 kb
Host smart-1a950e8c-5fa6-4842-8098-f51521c50bcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461543583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1461543583
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.479873342
Short name T339
Test name
Test status
Simulation time 278345514 ps
CPU time 17.49 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 210844 kb
Host smart-56eb0efc-9328-4b20-9acc-8fe168fd5660
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479873342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.479873342
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3583001737
Short name T319
Test name
Test status
Simulation time 193476590 ps
CPU time 9.18 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:19 PM PDT 24
Peak memory 217192 kb
Host smart-71f60583-af9c-4df2-a6d2-5416e9c741ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583001737 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3583001737
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2935584663
Short name T376
Test name
Test status
Simulation time 176620292 ps
CPU time 7.96 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 210712 kb
Host smart-a7434e84-4509-4d9f-9e18-4b682edfbc57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935584663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2935584663
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.408038872
Short name T334
Test name
Test status
Simulation time 507158174 ps
CPU time 9.86 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 210588 kb
Host smart-4603f85a-bd9c-46b1-9423-071396cfdbfd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408038872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.408038872
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1043834328
Short name T381
Test name
Test status
Simulation time 508253433 ps
CPU time 9.84 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:03:30 PM PDT 24
Peak memory 210772 kb
Host smart-43af2909-eb04-4c84-a778-b36e5bf07f6a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043834328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1043834328
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2943193458
Short name T65
Test name
Test status
Simulation time 261129896 ps
CPU time 10.02 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 210860 kb
Host smart-7cfd25b0-9e1d-434c-8491-8f7271d24807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943193458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2943193458
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1635708661
Short name T404
Test name
Test status
Simulation time 169521021 ps
CPU time 10.75 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:33 PM PDT 24
Peak memory 219068 kb
Host smart-6180e24e-ac61-4719-920f-930663c5a86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635708661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1635708661
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1737691182
Short name T384
Test name
Test status
Simulation time 426921881 ps
CPU time 153.65 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:05:45 PM PDT 24
Peak memory 214296 kb
Host smart-6eef4054-1db5-446b-a752-2e73f3e22d42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737691182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1737691182
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4258820491
Short name T400
Test name
Test status
Simulation time 3091150192 ps
CPU time 9.8 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 210888 kb
Host smart-58bb4d56-73a3-4c71-adf7-06fe979760ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258820491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4258820491
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1710611856
Short name T348
Test name
Test status
Simulation time 872067353 ps
CPU time 8.39 seconds
Started Jul 31 05:03:08 PM PDT 24
Finished Jul 31 05:03:16 PM PDT 24
Peak memory 210804 kb
Host smart-faa18351-f5b3-4604-a42a-e8f469d62bdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710611856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1710611856
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.260898231
Short name T86
Test name
Test status
Simulation time 700284151 ps
CPU time 15.02 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 212256 kb
Host smart-a6325a8a-d787-4a85-929f-628edf608497
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260898231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.260898231
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1938455957
Short name T341
Test name
Test status
Simulation time 1012927612 ps
CPU time 15.46 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 218124 kb
Host smart-b9615eec-c632-4faa-8025-f94c27d2b7c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938455957 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1938455957
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2185469058
Short name T80
Test name
Test status
Simulation time 214187478 ps
CPU time 8.28 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:30 PM PDT 24
Peak memory 211040 kb
Host smart-0dc3110d-3112-4d15-88fd-069a5ffba5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185469058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2185469058
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1147718945
Short name T330
Test name
Test status
Simulation time 174558028 ps
CPU time 8.17 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:21 PM PDT 24
Peak memory 210676 kb
Host smart-c6608723-a84c-4c1a-8bde-08e75aafad79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147718945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1147718945
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1532098772
Short name T317
Test name
Test status
Simulation time 298596450 ps
CPU time 9.8 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:23 PM PDT 24
Peak memory 210692 kb
Host smart-9b598ec7-0e92-44ee-acc4-ce6404592452
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532098772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1532098772
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1287509362
Short name T81
Test name
Test status
Simulation time 4417630511 ps
CPU time 43.95 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:04:07 PM PDT 24
Peak memory 219172 kb
Host smart-9d3eb102-ef8b-47c2-8621-1e887d5c3278
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287509362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1287509362
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1847728072
Short name T360
Test name
Test status
Simulation time 989396575 ps
CPU time 9.93 seconds
Started Jul 31 05:03:17 PM PDT 24
Finished Jul 31 05:03:27 PM PDT 24
Peak memory 211484 kb
Host smart-35b40333-6407-4a5a-a1d9-7a5982aed8af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847728072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1847728072
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2726931858
Short name T329
Test name
Test status
Simulation time 171714649 ps
CPU time 12.98 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 219024 kb
Host smart-af45fdbb-dfdc-4f0e-86e7-8b0f17bd6616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726931858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2726931858
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.334627034
Short name T105
Test name
Test status
Simulation time 2161408788 ps
CPU time 85.47 seconds
Started Jul 31 05:03:30 PM PDT 24
Finished Jul 31 05:04:55 PM PDT 24
Peak memory 213984 kb
Host smart-01979022-a324-418c-b389-2a5ff315f88d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334627034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.334627034
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.779314228
Short name T362
Test name
Test status
Simulation time 711791953 ps
CPU time 8.87 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:22 PM PDT 24
Peak memory 217172 kb
Host smart-b143c499-e9d4-4b4b-9733-aea05fb12c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779314228 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.779314228
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2759836625
Short name T397
Test name
Test status
Simulation time 515074948 ps
CPU time 9.67 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 211032 kb
Host smart-cf522099-c944-4147-8fe5-bef5d24bc40b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759836625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2759836625
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3118866540
Short name T359
Test name
Test status
Simulation time 612059207 ps
CPU time 7.88 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:30 PM PDT 24
Peak memory 211548 kb
Host smart-4280fddd-ef7b-4749-a686-25103a1e7d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118866540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3118866540
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4084116220
Short name T391
Test name
Test status
Simulation time 1027675693 ps
CPU time 19.52 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 218908 kb
Host smart-5432a12a-406f-4747-a46b-01e582a77e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084116220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4084116220
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.120244734
Short name T103
Test name
Test status
Simulation time 308293711 ps
CPU time 147.24 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:05:37 PM PDT 24
Peak memory 214336 kb
Host smart-13058a57-585c-4ca1-964c-210cf1940bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120244734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.120244734
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1059083072
Short name T357
Test name
Test status
Simulation time 267775925 ps
CPU time 10.29 seconds
Started Jul 31 05:03:15 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 216488 kb
Host smart-8e5e7507-30d6-4c14-9def-e3430e850b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059083072 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1059083072
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.857188236
Short name T402
Test name
Test status
Simulation time 665652064 ps
CPU time 7.95 seconds
Started Jul 31 05:03:10 PM PDT 24
Finished Jul 31 05:03:18 PM PDT 24
Peak memory 211060 kb
Host smart-47cf3e3f-af58-4d41-9118-2684dc42e2c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857188236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.857188236
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3653882650
Short name T60
Test name
Test status
Simulation time 661982476 ps
CPU time 8.14 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:20 PM PDT 24
Peak memory 211428 kb
Host smart-0d598dc9-ffa9-4104-804a-45248ed58b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653882650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3653882650
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4149617676
Short name T326
Test name
Test status
Simulation time 347953324 ps
CPU time 12.77 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 219008 kb
Host smart-9285e501-d845-4a1a-86a2-9ae9049b3018
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149617676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4149617676
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.447531757
Short name T106
Test name
Test status
Simulation time 653702850 ps
CPU time 82.93 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 214064 kb
Host smart-97933855-18cf-46d7-977e-0994bc770638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447531757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.447531757
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.290195174
Short name T349
Test name
Test status
Simulation time 275175162 ps
CPU time 10.54 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:03:30 PM PDT 24
Peak memory 217708 kb
Host smart-d4728995-0b01-49c4-9ad5-0f4ddd72444f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290195174 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.290195174
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3263946915
Short name T332
Test name
Test status
Simulation time 331722071 ps
CPU time 9.39 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 210924 kb
Host smart-ebf0b12a-2838-4882-8fba-0f655e95b70f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263946915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3263946915
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.163683362
Short name T368
Test name
Test status
Simulation time 2187253687 ps
CPU time 11.92 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 212936 kb
Host smart-ddbefefb-5c76-43ca-8cae-ef2e7db9b2a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163683362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.163683362
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.239107540
Short name T343
Test name
Test status
Simulation time 172577585 ps
CPU time 12.95 seconds
Started Jul 31 05:03:13 PM PDT 24
Finished Jul 31 05:03:26 PM PDT 24
Peak memory 219052 kb
Host smart-503deda8-daa6-4a3b-af6e-f56d32bbeeb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239107540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.239107540
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3204265386
Short name T375
Test name
Test status
Simulation time 987572877 ps
CPU time 82.2 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:04:54 PM PDT 24
Peak memory 213764 kb
Host smart-39c245f9-d208-4839-90b9-6b70c7c4238a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204265386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3204265386
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.433524125
Short name T328
Test name
Test status
Simulation time 1031478378 ps
CPU time 15.24 seconds
Started Jul 31 05:03:11 PM PDT 24
Finished Jul 31 05:03:27 PM PDT 24
Peak memory 215696 kb
Host smart-078bd3a4-661d-4b19-ac90-53a839713a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433524125 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.433524125
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4076936479
Short name T373
Test name
Test status
Simulation time 615678349 ps
CPU time 8.32 seconds
Started Jul 31 05:03:16 PM PDT 24
Finished Jul 31 05:03:24 PM PDT 24
Peak memory 211192 kb
Host smart-697c091f-ab62-466d-890a-2da4b603d78c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076936479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4076936479
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1403559130
Short name T68
Test name
Test status
Simulation time 514714878 ps
CPU time 10.05 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:33 PM PDT 24
Peak memory 211756 kb
Host smart-f9837ad9-3372-44b8-9467-4491060fa8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403559130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1403559130
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3627019273
Short name T399
Test name
Test status
Simulation time 1383437897 ps
CPU time 13.11 seconds
Started Jul 31 05:03:25 PM PDT 24
Finished Jul 31 05:03:39 PM PDT 24
Peak memory 217744 kb
Host smart-f7fd3d48-8a0a-448d-af02-77efe839a2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627019273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3627019273
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1364880562
Short name T379
Test name
Test status
Simulation time 980113197 ps
CPU time 11.44 seconds
Started Jul 31 05:03:14 PM PDT 24
Finished Jul 31 05:03:25 PM PDT 24
Peak memory 218044 kb
Host smart-51de0610-b050-4644-b258-701eb46aa1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364880562 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1364880562
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1762104939
Short name T393
Test name
Test status
Simulation time 225507953 ps
CPU time 8.14 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:27 PM PDT 24
Peak memory 210800 kb
Host smart-dd2fe972-91b3-4ea7-a22d-9def43507ba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762104939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1762104939
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1319562675
Short name T394
Test name
Test status
Simulation time 517764730 ps
CPU time 10.12 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:28 PM PDT 24
Peak memory 211668 kb
Host smart-59642a8c-8e7a-4e11-b824-3ad7fd63623b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319562675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1319562675
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1786807594
Short name T315
Test name
Test status
Simulation time 1504954929 ps
CPU time 11.14 seconds
Started Jul 31 05:03:18 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 217276 kb
Host smart-9b830954-a924-408e-9f5f-9d7741e5cc4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786807594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1786807594
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1917586697
Short name T58
Test name
Test status
Simulation time 1454372919 ps
CPU time 85.15 seconds
Started Jul 31 05:03:36 PM PDT 24
Finished Jul 31 05:05:01 PM PDT 24
Peak memory 219100 kb
Host smart-9da3245c-4985-46ec-9c5f-f1e030023768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917586697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1917586697
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1188970127
Short name T34
Test name
Test status
Simulation time 1034623476 ps
CPU time 10.06 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:03:38 PM PDT 24
Peak memory 218668 kb
Host smart-4c9f0448-d5cc-40a4-a35c-9163d1684809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188970127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1188970127
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4036842755
Short name T135
Test name
Test status
Simulation time 5462545648 ps
CPU time 184.29 seconds
Started Jul 31 05:03:21 PM PDT 24
Finished Jul 31 05:06:25 PM PDT 24
Peak memory 239676 kb
Host smart-dc04c3dd-fb26-4f8a-a2e4-2e2c274a0e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036842755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4036842755
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3694955244
Short name T125
Test name
Test status
Simulation time 697552278 ps
CPU time 10.79 seconds
Started Jul 31 05:03:33 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 219968 kb
Host smart-fe6cbf47-417a-49fa-b635-3ddbcec08dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694955244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3694955244
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3985393548
Short name T27
Test name
Test status
Simulation time 512890131 ps
CPU time 116.15 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:05:21 PM PDT 24
Peak memory 238928 kb
Host smart-21c37fdc-13cc-4d83-83d7-5f0539f7bc39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985393548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3985393548
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1019249805
Short name T273
Test name
Test status
Simulation time 182122609 ps
CPU time 10.58 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:34 PM PDT 24
Peak memory 219840 kb
Host smart-f0403719-b830-4606-9427-65f80128168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019249805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1019249805
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2873267454
Short name T222
Test name
Test status
Simulation time 250139047 ps
CPU time 9.94 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 219064 kb
Host smart-057bc810-d92f-421f-b408-4267bdf9366f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873267454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2873267454
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.522617546
Short name T195
Test name
Test status
Simulation time 3811917503 ps
CPU time 234.69 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:07:29 PM PDT 24
Peak memory 219756 kb
Host smart-b54528ec-6b86-4895-922b-7f63e1985643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522617546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.522617546
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3277753113
Short name T37
Test name
Test status
Simulation time 677942883 ps
CPU time 18.78 seconds
Started Jul 31 05:03:27 PM PDT 24
Finished Jul 31 05:03:45 PM PDT 24
Peak memory 220052 kb
Host smart-881cc2f9-2134-410d-b342-977946f0642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277753113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3277753113
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2934127565
Short name T193
Test name
Test status
Simulation time 203945006 ps
CPU time 10.31 seconds
Started Jul 31 05:03:35 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 219916 kb
Host smart-8f43cccc-768e-4ea6-840b-ae14e000ccfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934127565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2934127565
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.648005175
Short name T28
Test name
Test status
Simulation time 449274306 ps
CPU time 229.04 seconds
Started Jul 31 05:03:35 PM PDT 24
Finished Jul 31 05:07:24 PM PDT 24
Peak memory 235132 kb
Host smart-3e6ad3f0-fc88-4e74-bcdc-3b6a93aeea37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648005175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.648005175
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.370285461
Short name T94
Test name
Test status
Simulation time 438376682 ps
CPU time 11.67 seconds
Started Jul 31 05:03:25 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 219956 kb
Host smart-0849473b-ebb4-4fe2-9f03-4e080e091a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370285461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.370285461
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3185547409
Short name T298
Test name
Test status
Simulation time 1020584319 ps
CPU time 16.24 seconds
Started Jul 31 05:03:12 PM PDT 24
Finished Jul 31 05:03:29 PM PDT 24
Peak memory 219868 kb
Host smart-30b6a9f8-5400-4c3c-94e4-bd1f0ba3cb76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185547409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3185547409
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2392618924
Short name T166
Test name
Test status
Simulation time 334193396 ps
CPU time 8.1 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:03:55 PM PDT 24
Peak memory 218976 kb
Host smart-5ca41ea5-04e0-4d78-9ba7-9555f805e414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392618924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2392618924
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.644155930
Short name T159
Test name
Test status
Simulation time 15011964110 ps
CPU time 206.3 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:07:07 PM PDT 24
Peak memory 219184 kb
Host smart-21e36e29-b5b4-441d-a291-e49e1d8e70ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644155930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.644155930
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2305659870
Short name T155
Test name
Test status
Simulation time 497882225 ps
CPU time 22.39 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219996 kb
Host smart-e8a3ea1f-3fd9-42ad-acc2-77ba46f304b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305659870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2305659870
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2289575186
Short name T289
Test name
Test status
Simulation time 1084231928 ps
CPU time 30.51 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219892 kb
Host smart-ce731cf8-61c1-447f-b67d-6cd4ac22daf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289575186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2289575186
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1582898898
Short name T181
Test name
Test status
Simulation time 30247851983 ps
CPU time 398.64 seconds
Started Jul 31 05:03:27 PM PDT 24
Finished Jul 31 05:10:06 PM PDT 24
Peak memory 235636 kb
Host smart-45bc5da1-dc65-4322-beed-1d5526b46b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582898898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1582898898
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1429399371
Short name T270
Test name
Test status
Simulation time 1711459497 ps
CPU time 22.54 seconds
Started Jul 31 05:03:30 PM PDT 24
Finished Jul 31 05:03:53 PM PDT 24
Peak memory 219988 kb
Host smart-d1586368-a783-4631-a846-36f45dc96a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429399371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1429399371
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.107584726
Short name T252
Test name
Test status
Simulation time 1078403345 ps
CPU time 12.36 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 220032 kb
Host smart-1131fe71-2cfb-4b53-a885-6ec147857e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107584726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.107584726
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.354536434
Short name T278
Test name
Test status
Simulation time 682774333 ps
CPU time 15.26 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:03:54 PM PDT 24
Peak memory 219832 kb
Host smart-39a84d9d-81a0-4e9e-bf36-a2e448d06957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354536434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.354536434
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2623768632
Short name T114
Test name
Test status
Simulation time 259766730 ps
CPU time 10.06 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:04:00 PM PDT 24
Peak memory 218988 kb
Host smart-6752902e-5de2-4f30-947f-6a68e686309a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623768632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2623768632
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1565679464
Short name T200
Test name
Test status
Simulation time 16740236246 ps
CPU time 245.33 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:07:37 PM PDT 24
Peak memory 239584 kb
Host smart-55955934-b870-42a3-8d0b-a3dc748037de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565679464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1565679464
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.209063225
Short name T138
Test name
Test status
Simulation time 2059542024 ps
CPU time 21.66 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:03:50 PM PDT 24
Peak memory 219956 kb
Host smart-8272e458-370f-4c61-b693-bd958974a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209063225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.209063225
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1998722819
Short name T187
Test name
Test status
Simulation time 295316194 ps
CPU time 12.3 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:03:56 PM PDT 24
Peak memory 219952 kb
Host smart-717b1d9f-1fc6-465a-afd7-d98ea8f01c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998722819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1998722819
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3924884215
Short name T303
Test name
Test status
Simulation time 3131723341 ps
CPU time 51.8 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 220036 kb
Host smart-1bfb5003-8de1-4fe7-bcff-a8acf093151c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924884215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3924884215
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2706046144
Short name T131
Test name
Test status
Simulation time 4120533701 ps
CPU time 10.31 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:58 PM PDT 24
Peak memory 219232 kb
Host smart-726fda68-1515-4805-ba1b-5a5e076fda7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706046144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2706046144
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2770738138
Short name T276
Test name
Test status
Simulation time 14937814031 ps
CPU time 377.4 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:10:01 PM PDT 24
Peak memory 237672 kb
Host smart-588b184c-87ca-4e73-96f1-d29d10bcd2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770738138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2770738138
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3509509969
Short name T112
Test name
Test status
Simulation time 3008618355 ps
CPU time 19.15 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 220124 kb
Host smart-c822aa8e-d634-459f-87de-c803a1666f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509509969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3509509969
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.819074447
Short name T89
Test name
Test status
Simulation time 1027340558 ps
CPU time 12.15 seconds
Started Jul 31 05:03:56 PM PDT 24
Finished Jul 31 05:04:08 PM PDT 24
Peak memory 219924 kb
Host smart-5ddbf197-83f4-4e82-988b-ee7c0ca22214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819074447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.819074447
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3088296456
Short name T162
Test name
Test status
Simulation time 371587296 ps
CPU time 23.2 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 219900 kb
Host smart-427aae1c-5312-4657-9adf-8f0469a8a319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088296456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3088296456
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1067468886
Short name T201
Test name
Test status
Simulation time 1657520981 ps
CPU time 10.07 seconds
Started Jul 31 05:03:51 PM PDT 24
Finished Jul 31 05:04:01 PM PDT 24
Peak memory 218924 kb
Host smart-a47b4b09-a169-4ad9-b634-f332130290ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067468886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1067468886
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4057589285
Short name T220
Test name
Test status
Simulation time 2745962408 ps
CPU time 19.7 seconds
Started Jul 31 05:03:53 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 220128 kb
Host smart-704ef610-267e-478e-9c35-f40f93a9e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057589285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4057589285
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2671647029
Short name T209
Test name
Test status
Simulation time 1029910257 ps
CPU time 12.2 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 220012 kb
Host smart-82eb8d10-b4ef-4bfa-a851-ddb4850b5202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671647029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2671647029
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3265910938
Short name T152
Test name
Test status
Simulation time 626662954 ps
CPU time 28.4 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 219896 kb
Host smart-f3966079-331b-4a30-8e92-af607fba8412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265910938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3265910938
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2345900215
Short name T50
Test name
Test status
Simulation time 164809049804 ps
CPU time 1420.91 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:27:25 PM PDT 24
Peak memory 237392 kb
Host smart-deb905f8-0cb4-4703-af73-8368603f7bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345900215 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2345900215
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2173647909
Short name T35
Test name
Test status
Simulation time 507357623 ps
CPU time 10.87 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 219084 kb
Host smart-cba3856b-1040-48de-9f25-aafff7b4d96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173647909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2173647909
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.253590304
Short name T235
Test name
Test status
Simulation time 7271591352 ps
CPU time 365.05 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:09:49 PM PDT 24
Peak memory 219912 kb
Host smart-4e394311-705c-4601-8c4d-2c34e9c5457e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253590304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.253590304
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.102168498
Short name T198
Test name
Test status
Simulation time 270502464 ps
CPU time 12.15 seconds
Started Jul 31 05:03:42 PM PDT 24
Finished Jul 31 05:03:55 PM PDT 24
Peak memory 220008 kb
Host smart-639d85c9-f744-495e-9a47-bd77973407d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102168498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.102168498
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3001404895
Short name T76
Test name
Test status
Simulation time 4315657024 ps
CPU time 23.3 seconds
Started Jul 31 05:03:50 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 220132 kb
Host smart-75a6d58f-9589-46cc-8237-4ee76e8ecba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001404895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3001404895
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.832429710
Short name T306
Test name
Test status
Simulation time 824332208 ps
CPU time 10.21 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:03:59 PM PDT 24
Peak memory 219024 kb
Host smart-081ce770-beef-4a0a-ace7-f78e49e86877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832429710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.832429710
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1270661718
Short name T18
Test name
Test status
Simulation time 7825695586 ps
CPU time 102.57 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:05:29 PM PDT 24
Peak memory 220204 kb
Host smart-15f08812-7488-404a-86da-ed38431aad61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270661718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1270661718
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3443403439
Short name T267
Test name
Test status
Simulation time 1436205006 ps
CPU time 19.98 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:04:01 PM PDT 24
Peak memory 219936 kb
Host smart-245fcba8-afbc-4342-afa8-9bda2715cd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443403439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3443403439
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2346047030
Short name T204
Test name
Test status
Simulation time 184812782 ps
CPU time 10.4 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 219988 kb
Host smart-143bb1b0-b400-4073-934a-6a13b58fb625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346047030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2346047030
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1442847751
Short name T300
Test name
Test status
Simulation time 2245335994 ps
CPU time 34.7 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 220064 kb
Host smart-c0fea673-0e53-4a5e-99f5-78573c2ca39b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442847751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1442847751
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.438639737
Short name T61
Test name
Test status
Simulation time 253045875 ps
CPU time 10.37 seconds
Started Jul 31 05:03:51 PM PDT 24
Finished Jul 31 05:04:02 PM PDT 24
Peak memory 219096 kb
Host smart-c1c98a15-d71e-44ed-8508-ff3883255d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438639737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.438639737
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.989609482
Short name T290
Test name
Test status
Simulation time 5001169303 ps
CPU time 274.11 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:08:24 PM PDT 24
Peak memory 238452 kb
Host smart-79d96b90-37b4-4e5e-b6cf-c5bc50be5c51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989609482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.989609482
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3881792495
Short name T43
Test name
Test status
Simulation time 1375849306 ps
CPU time 19.37 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 220052 kb
Host smart-fae9f080-85f5-4ab4-b14c-9c335767500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881792495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3881792495
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.123254713
Short name T90
Test name
Test status
Simulation time 531596349 ps
CPU time 12.15 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:04:02 PM PDT 24
Peak memory 219924 kb
Host smart-7885d449-cb7a-4d18-8a8b-eb00ed031fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123254713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.123254713
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1483766705
Short name T150
Test name
Test status
Simulation time 1232611851 ps
CPU time 20.41 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 219856 kb
Host smart-2d9400c0-ca1b-41f8-915a-634591ec5240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483766705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1483766705
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2745210116
Short name T264
Test name
Test status
Simulation time 58677317076 ps
CPU time 2268.62 seconds
Started Jul 31 05:03:35 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 240580 kb
Host smart-0b581617-8e3a-470a-9972-d5a4307726a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745210116 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2745210116
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1614380534
Short name T256
Test name
Test status
Simulation time 252876146 ps
CPU time 10.06 seconds
Started Jul 31 05:03:52 PM PDT 24
Finished Jul 31 05:04:02 PM PDT 24
Peak memory 218440 kb
Host smart-4b86fdc2-d060-4610-b1da-29f670978124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614380534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1614380534
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2196896444
Short name T144
Test name
Test status
Simulation time 7875784320 ps
CPU time 263.09 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:08:07 PM PDT 24
Peak memory 241576 kb
Host smart-a70f8449-05eb-4296-9763-0a9c43362df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196896444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2196896444
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3550869648
Short name T229
Test name
Test status
Simulation time 1032054691 ps
CPU time 23.37 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:04:03 PM PDT 24
Peak memory 220000 kb
Host smart-8f16d971-e973-4762-b632-1e3b23e85469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550869648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3550869648
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3221619236
Short name T307
Test name
Test status
Simulation time 731453470 ps
CPU time 10.46 seconds
Started Jul 31 05:03:52 PM PDT 24
Finished Jul 31 05:04:03 PM PDT 24
Peak memory 219968 kb
Host smart-df8e6a16-0fc1-46f3-9f70-fdcc7d3238c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221619236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3221619236
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.623363414
Short name T177
Test name
Test status
Simulation time 1507601339 ps
CPU time 34.83 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 220828 kb
Host smart-6a2b6d84-33c1-429a-8f21-d708ef604fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623363414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.623363414
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3664999266
Short name T49
Test name
Test status
Simulation time 40539180665 ps
CPU time 1709.27 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:32:25 PM PDT 24
Peak memory 245756 kb
Host smart-fcf3236e-1a68-402d-af68-739d3a27c9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664999266 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3664999266
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.291906646
Short name T301
Test name
Test status
Simulation time 956051716 ps
CPU time 10.21 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 218912 kb
Host smart-92c85d67-700c-44e5-9eea-36a7e51f45fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291906646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.291906646
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3584560004
Short name T17
Test name
Test status
Simulation time 7524692819 ps
CPU time 180.38 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:07:04 PM PDT 24
Peak memory 239716 kb
Host smart-ee57669a-4a03-4ef3-ba2e-c003031c43b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584560004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3584560004
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3375595601
Short name T274
Test name
Test status
Simulation time 513766951 ps
CPU time 23.43 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:17 PM PDT 24
Peak memory 219992 kb
Host smart-b7134257-9dc7-462a-b973-27ca29344149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375595601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3375595601
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2012609554
Short name T288
Test name
Test status
Simulation time 266442964 ps
CPU time 12.41 seconds
Started Jul 31 05:03:52 PM PDT 24
Finished Jul 31 05:04:04 PM PDT 24
Peak memory 220004 kb
Host smart-c8d83de8-15d1-4c85-9d87-e2140365afdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012609554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2012609554
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3304690927
Short name T73
Test name
Test status
Simulation time 2094809345 ps
CPU time 23.88 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 219892 kb
Host smart-648cf47f-9f96-4da0-bb8c-d8d52c6a2dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304690927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3304690927
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.742863826
Short name T140
Test name
Test status
Simulation time 479051043 ps
CPU time 10.05 seconds
Started Jul 31 05:03:25 PM PDT 24
Finished Jul 31 05:03:35 PM PDT 24
Peak memory 219048 kb
Host smart-05226a8e-d3ce-4f88-8cb5-6563cc418238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742863826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.742863826
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2474552176
Short name T156
Test name
Test status
Simulation time 2885772163 ps
CPU time 160.91 seconds
Started Jul 31 05:03:38 PM PDT 24
Finished Jul 31 05:06:19 PM PDT 24
Peak memory 235492 kb
Host smart-b37d3bda-2bec-42d0-a9fa-c344de52f9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474552176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2474552176
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1629973006
Short name T36
Test name
Test status
Simulation time 1104479971 ps
CPU time 22.8 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 219972 kb
Host smart-b1f81ebe-96b7-425c-aef6-19dbb012c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629973006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1629973006
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1293031603
Short name T133
Test name
Test status
Simulation time 1059182996 ps
CPU time 11.92 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:03:44 PM PDT 24
Peak memory 219992 kb
Host smart-a70f8ce3-6549-44ad-99ec-82b06ff25883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293031603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1293031603
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1507605444
Short name T23
Test name
Test status
Simulation time 333914905 ps
CPU time 227.49 seconds
Started Jul 31 05:03:42 PM PDT 24
Finished Jul 31 05:07:30 PM PDT 24
Peak memory 235544 kb
Host smart-f7f32af2-2bec-49f1-aa90-737457f7eb6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507605444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1507605444
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1584551907
Short name T242
Test name
Test status
Simulation time 953259371 ps
CPU time 12.22 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:35 PM PDT 24
Peak memory 219960 kb
Host smart-85c5dda6-22fa-49da-b768-92814a1f3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584551907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1584551907
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2983441080
Short name T261
Test name
Test status
Simulation time 771168795 ps
CPU time 18.09 seconds
Started Jul 31 05:03:23 PM PDT 24
Finished Jul 31 05:03:41 PM PDT 24
Peak memory 220012 kb
Host smart-afc3d207-3c83-411f-9f86-0387468cb371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983441080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2983441080
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.543196372
Short name T33
Test name
Test status
Simulation time 1104447119 ps
CPU time 8.21 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:03:53 PM PDT 24
Peak memory 218960 kb
Host smart-321e3fd5-2718-4bc7-8899-fe9735894e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543196372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.543196372
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2357153513
Short name T239
Test name
Test status
Simulation time 2925461681 ps
CPU time 170.17 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:06:36 PM PDT 24
Peak memory 239660 kb
Host smart-caaf488b-25b5-423c-8bce-f8d32c6c4c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357153513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2357153513
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1214484537
Short name T179
Test name
Test status
Simulation time 508396005 ps
CPU time 22.93 seconds
Started Jul 31 05:03:53 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219984 kb
Host smart-5b853eac-4e4e-4751-8814-4df577f5ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214484537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1214484537
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2843857371
Short name T171
Test name
Test status
Simulation time 910339211 ps
CPU time 10.43 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 220028 kb
Host smart-d352039a-55ef-49a8-b84c-aef7f3d1ea1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843857371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2843857371
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.180168703
Short name T147
Test name
Test status
Simulation time 2946641479 ps
CPU time 33.36 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:04:31 PM PDT 24
Peak memory 220068 kb
Host smart-b83aff48-568e-42ce-b96c-1ba125ae2278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180168703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.180168703
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3278287031
Short name T130
Test name
Test status
Simulation time 168296063 ps
CPU time 8.29 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:03:55 PM PDT 24
Peak memory 219004 kb
Host smart-c14718d2-bc8f-4c9b-9202-038a041b0789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278287031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3278287031
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.68332615
Short name T173
Test name
Test status
Simulation time 13875263212 ps
CPU time 377.56 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:10:15 PM PDT 24
Peak memory 241364 kb
Host smart-cc25090d-8406-4c37-99b4-701aabce17a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68332615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.68332615
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.546593232
Short name T255
Test name
Test status
Simulation time 347311088 ps
CPU time 19.5 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 220076 kb
Host smart-9eba4080-f584-4f81-94d7-e5a57a2046bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546593232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.546593232
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3048181155
Short name T19
Test name
Test status
Simulation time 184932380 ps
CPU time 10.44 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:59 PM PDT 24
Peak memory 220048 kb
Host smart-7a76d12c-7384-46b5-98ff-1deb65d399be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048181155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3048181155
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2672155139
Short name T184
Test name
Test status
Simulation time 5094712616 ps
CPU time 57.19 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:44 PM PDT 24
Peak memory 220132 kb
Host smart-9422bbf9-5fe5-4a6c-8f18-a54420435df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672155139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2672155139
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2122368075
Short name T269
Test name
Test status
Simulation time 23723863342 ps
CPU time 886.81 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:18:34 PM PDT 24
Peak memory 231036 kb
Host smart-661b962b-d70f-4185-a85c-263e2b619bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122368075 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2122368075
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2054941101
Short name T136
Test name
Test status
Simulation time 691925195 ps
CPU time 8.27 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:56 PM PDT 24
Peak memory 219052 kb
Host smart-0852220a-1744-4e6d-9e64-ee48489210ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054941101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2054941101
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2617723840
Short name T302
Test name
Test status
Simulation time 2223680501 ps
CPU time 109.69 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:05:36 PM PDT 24
Peak memory 237556 kb
Host smart-20a39326-0bc6-4dcb-a789-b44bb385cc74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617723840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2617723840
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2301732791
Short name T212
Test name
Test status
Simulation time 2067471239 ps
CPU time 23.23 seconds
Started Jul 31 05:03:50 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 220040 kb
Host smart-ac1656a2-0cbf-4fc8-9b26-437e20e88133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301732791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2301732791
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3648179369
Short name T118
Test name
Test status
Simulation time 692027967 ps
CPU time 12.37 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:04:00 PM PDT 24
Peak memory 219940 kb
Host smart-8ffd5117-01a3-4199-9948-59b7329d1be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648179369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3648179369
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3211545410
Short name T237
Test name
Test status
Simulation time 3989402610 ps
CPU time 16.25 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:17 PM PDT 24
Peak memory 219980 kb
Host smart-ebe95e73-a47a-43c6-bb45-6caec2362365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211545410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3211545410
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3143563361
Short name T174
Test name
Test status
Simulation time 176559982 ps
CPU time 8.43 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 218980 kb
Host smart-89da0106-aef5-45ae-ad5d-2c4078edcc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143563361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3143563361
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1482587409
Short name T124
Test name
Test status
Simulation time 4174215935 ps
CPU time 205.49 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:07:32 PM PDT 24
Peak memory 220324 kb
Host smart-44712136-1149-440a-b9c0-e815ade50883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482587409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1482587409
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1419546508
Short name T169
Test name
Test status
Simulation time 1378517109 ps
CPU time 19.14 seconds
Started Jul 31 05:03:58 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 220056 kb
Host smart-fb2e486d-3f30-4642-af4c-f245c743cd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419546508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1419546508
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3177987625
Short name T268
Test name
Test status
Simulation time 531198258 ps
CPU time 12.38 seconds
Started Jul 31 05:03:53 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 220028 kb
Host smart-bdce0c02-11e9-46ef-895b-a95652fc9703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177987625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3177987625
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3534212665
Short name T123
Test name
Test status
Simulation time 3055940877 ps
CPU time 30.06 seconds
Started Jul 31 05:03:38 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 219904 kb
Host smart-80e7ec59-e6ed-45b5-8117-b92daf9e63db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534212665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3534212665
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3771504582
Short name T5
Test name
Test status
Simulation time 1037131647 ps
CPU time 10.05 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 218940 kb
Host smart-9d58c1a9-c0dd-416f-903e-5e2284dd6f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771504582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3771504582
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3043435880
Short name T238
Test name
Test status
Simulation time 9555535769 ps
CPU time 270.83 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:08:17 PM PDT 24
Peak memory 241220 kb
Host smart-56053ba1-40a7-4f8f-9ef9-86d8595b8782
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043435880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3043435880
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1359759146
Short name T223
Test name
Test status
Simulation time 989551927 ps
CPU time 16.55 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 219956 kb
Host smart-2252a070-6eb4-4085-b711-d9d4f161a2bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359759146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1359759146
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3939910522
Short name T127
Test name
Test status
Simulation time 798839407 ps
CPU time 18.02 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 219984 kb
Host smart-9e6e6bbe-8067-417c-b263-3378999830da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939910522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3939910522
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3804923351
Short name T232
Test name
Test status
Simulation time 368556286 ps
CPU time 8.36 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 219060 kb
Host smart-92b27d89-1061-4cb3-8500-14772b4f73b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804923351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3804923351
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2442478404
Short name T293
Test name
Test status
Simulation time 11422247869 ps
CPU time 270.67 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:08:31 PM PDT 24
Peak memory 220316 kb
Host smart-dfa755f0-4637-4c85-9a1b-a4b527a3c166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442478404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2442478404
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1313238987
Short name T271
Test name
Test status
Simulation time 3520726634 ps
CPU time 22.81 seconds
Started Jul 31 05:03:52 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 220136 kb
Host smart-1473e945-8e31-45e8-be3f-d6caa68ba0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313238987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1313238987
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1556357401
Short name T122
Test name
Test status
Simulation time 2201592420 ps
CPU time 10.86 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:59 PM PDT 24
Peak memory 220156 kb
Host smart-13f4cfc4-3ae2-4688-8320-4e8eeec51c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556357401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1556357401
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3610015817
Short name T286
Test name
Test status
Simulation time 283561469 ps
CPU time 26.66 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:32 PM PDT 24
Peak memory 220000 kb
Host smart-41078bad-dc0a-4f42-8aad-05b8f86afc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610015817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3610015817
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.44630694
Short name T48
Test name
Test status
Simulation time 174213041208 ps
CPU time 1575.26 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:30:18 PM PDT 24
Peak memory 237388 kb
Host smart-de156fc4-bb34-45d3-ab56-7a0c91ab660b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44630694 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.44630694
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2870016332
Short name T141
Test name
Test status
Simulation time 249634925 ps
CPU time 10.15 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 218980 kb
Host smart-2290a4e3-4eca-4fb7-a8bf-7ead673eb105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870016332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2870016332
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.932835073
Short name T38
Test name
Test status
Simulation time 6633604154 ps
CPU time 355.05 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:09:59 PM PDT 24
Peak memory 242664 kb
Host smart-40f6aec1-106f-47b6-b719-b90f2d81ab65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932835073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.932835073
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4157164657
Short name T272
Test name
Test status
Simulation time 1011351326 ps
CPU time 22.45 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 219960 kb
Host smart-19552b7e-2e75-459d-82fd-a6035343fe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157164657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4157164657
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4218834783
Short name T224
Test name
Test status
Simulation time 1061965546 ps
CPU time 11.5 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 219948 kb
Host smart-4ec17f50-20fc-4fe9-9501-e834b958604c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218834783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4218834783
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2717152239
Short name T55
Test name
Test status
Simulation time 372747837 ps
CPU time 15.25 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 219752 kb
Host smart-fa2542db-d2d2-44aa-a049-ef2ba7ff06bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717152239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2717152239
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2360492643
Short name T308
Test name
Test status
Simulation time 514264604 ps
CPU time 10.2 seconds
Started Jul 31 05:04:11 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 219028 kb
Host smart-843da8e7-69f0-4f8a-a3e9-11c397d3e53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360492643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2360492643
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.686017648
Short name T39
Test name
Test status
Simulation time 3870079723 ps
CPU time 271.86 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:08:32 PM PDT 24
Peak memory 226624 kb
Host smart-8a8e1da1-f0be-4305-a888-1c3eebbe069f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686017648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.686017648
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.899990326
Short name T24
Test name
Test status
Simulation time 496144426 ps
CPU time 22.13 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 220060 kb
Host smart-1ba8c89e-81a1-43a4-b1dc-724cb1280f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899990326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.899990326
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4236366585
Short name T210
Test name
Test status
Simulation time 1075412979 ps
CPU time 12.57 seconds
Started Jul 31 05:03:53 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 219956 kb
Host smart-ef4496b4-3123-4f07-93f2-95273d4306ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236366585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4236366585
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1026199117
Short name T231
Test name
Test status
Simulation time 890868426 ps
CPU time 23.66 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 220012 kb
Host smart-096c1293-d60e-481c-b644-3a5e84526edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026199117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1026199117
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4257410787
Short name T211
Test name
Test status
Simulation time 249891700 ps
CPU time 10.05 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 219072 kb
Host smart-2f822aa7-4dbc-4834-8c94-d25b5c13e7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257410787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4257410787
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.346788050
Short name T304
Test name
Test status
Simulation time 15369197621 ps
CPU time 204.95 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:07:19 PM PDT 24
Peak memory 228732 kb
Host smart-701035dc-b284-49f5-b0d1-d9cff36e4e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346788050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.346788050
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2009711648
Short name T148
Test name
Test status
Simulation time 497399767 ps
CPU time 22.8 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:24 PM PDT 24
Peak memory 219944 kb
Host smart-653eb3ae-9187-4584-b3a4-1edd02773dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009711648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2009711648
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2754500230
Short name T227
Test name
Test status
Simulation time 536151220 ps
CPU time 12.31 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:19 PM PDT 24
Peak memory 219988 kb
Host smart-f6efb953-25f1-4db8-8b1b-703812445d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754500230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2754500230
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2405460465
Short name T313
Test name
Test status
Simulation time 368731644 ps
CPU time 26.65 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 219992 kb
Host smart-c7c1a054-e552-45e6-9b05-3d7756c52a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405460465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2405460465
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4152243409
Short name T53
Test name
Test status
Simulation time 91544160608 ps
CPU time 3209.44 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:57:34 PM PDT 24
Peak memory 253456 kb
Host smart-412e6be6-54b9-4553-b650-52c42c891a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152243409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4152243409
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2476808770
Short name T292
Test name
Test status
Simulation time 254031716 ps
CPU time 10.48 seconds
Started Jul 31 05:03:58 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 219076 kb
Host smart-09d7893f-494f-460e-8b31-8f2aaa7a704d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476808770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2476808770
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1012311727
Short name T225
Test name
Test status
Simulation time 6027276391 ps
CPU time 195.31 seconds
Started Jul 31 05:03:58 PM PDT 24
Finished Jul 31 05:07:13 PM PDT 24
Peak memory 220256 kb
Host smart-257b0d59-1236-47b1-93c5-eaeb48c951c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012311727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1012311727
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1739286180
Short name T26
Test name
Test status
Simulation time 505579185 ps
CPU time 23.31 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 219964 kb
Host smart-c2afeb54-524b-495e-8cd0-cd75433289ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739286180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1739286180
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4194505531
Short name T280
Test name
Test status
Simulation time 262737531 ps
CPU time 12.55 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 219956 kb
Host smart-88ebac20-8063-4cf6-a45b-68548b70be38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194505531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4194505531
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3807158930
Short name T191
Test name
Test status
Simulation time 538856766 ps
CPU time 33.44 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 220008 kb
Host smart-82694851-b0c8-4b8f-8a7c-843e0480b1c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807158930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3807158930
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.26415304
Short name T284
Test name
Test status
Simulation time 690506955 ps
CPU time 8.16 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:42 PM PDT 24
Peak memory 219064 kb
Host smart-2fe087ee-63fc-45d2-9324-3cba7f75204a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.26415304
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3908484488
Short name T154
Test name
Test status
Simulation time 5551418213 ps
CPU time 159.05 seconds
Started Jul 31 05:03:25 PM PDT 24
Finished Jul 31 05:06:04 PM PDT 24
Peak memory 238316 kb
Host smart-e69511ea-7021-48ad-9227-9ee5551ca72c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908484488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3908484488
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4108883121
Short name T163
Test name
Test status
Simulation time 10983978559 ps
CPU time 32.54 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 220112 kb
Host smart-ed4733cc-e20e-42a5-94c3-b729852da4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108883121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4108883121
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3811198039
Short name T259
Test name
Test status
Simulation time 910748275 ps
CPU time 10.18 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 220032 kb
Host smart-b57dcf45-4794-4704-a5bb-f00786584ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811198039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3811198039
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.530422074
Short name T22
Test name
Test status
Simulation time 241198844 ps
CPU time 115.33 seconds
Started Jul 31 05:03:30 PM PDT 24
Finished Jul 31 05:05:25 PM PDT 24
Peak memory 239852 kb
Host smart-d9c6e881-b226-459f-b097-6d37810ae7b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530422074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.530422074
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1724389769
Short name T170
Test name
Test status
Simulation time 936013157 ps
CPU time 12.04 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:03:36 PM PDT 24
Peak memory 219956 kb
Host smart-ddf92a00-c0c6-4e0a-9c27-86b5b9da22f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724389769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1724389769
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.826685672
Short name T258
Test name
Test status
Simulation time 2038255644 ps
CPU time 10.6 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:03:52 PM PDT 24
Peak memory 219952 kb
Host smart-a44e7e02-04f2-47c5-ae0c-3380d52ab3b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826685672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.826685672
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1683655599
Short name T281
Test name
Test status
Simulation time 71307646783 ps
CPU time 758.13 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 236524 kb
Host smart-8c3f3e75-e794-4ab1-a01c-6e715051fd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683655599 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1683655599
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3891780575
Short name T178
Test name
Test status
Simulation time 250995521 ps
CPU time 10.25 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:03:53 PM PDT 24
Peak memory 219056 kb
Host smart-9e5806f8-201d-4f5b-a290-0506289139a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891780575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3891780575
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2791258241
Short name T215
Test name
Test status
Simulation time 8227535974 ps
CPU time 237.97 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:08:00 PM PDT 24
Peak memory 239620 kb
Host smart-26c22f64-8a79-4871-b25a-03cbc68b2b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791258241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2791258241
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.947773729
Short name T226
Test name
Test status
Simulation time 509078074 ps
CPU time 23.42 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 220272 kb
Host smart-d199152d-1949-43f2-8ebf-c1fb330bd660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947773729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.947773729
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1743236728
Short name T32
Test name
Test status
Simulation time 531932069 ps
CPU time 12.27 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:03:57 PM PDT 24
Peak memory 219988 kb
Host smart-80a66d0e-0e0d-464c-9558-25d6c26fad12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743236728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1743236728
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.461004205
Short name T275
Test name
Test status
Simulation time 847345068 ps
CPU time 18.77 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 219884 kb
Host smart-3c501d05-8b9d-4b00-85dd-f875d1c49d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461004205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.461004205
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4279018027
Short name T52
Test name
Test status
Simulation time 22451858357 ps
CPU time 915.82 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:19:19 PM PDT 24
Peak memory 232748 kb
Host smart-cc43a897-c611-4868-950f-0c49e42cb942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279018027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.4279018027
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.439756067
Short name T203
Test name
Test status
Simulation time 171428924 ps
CPU time 8.19 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219016 kb
Host smart-02f2b26b-dabd-47cb-8ed4-55f4fd86ee7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439756067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.439756067
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.75411750
Short name T46
Test name
Test status
Simulation time 16541367627 ps
CPU time 219.79 seconds
Started Jul 31 05:03:54 PM PDT 24
Finished Jul 31 05:07:34 PM PDT 24
Peak memory 224972 kb
Host smart-b987cf25-db07-4e2f-a235-4ee500e238b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75411750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_co
rrupt_sig_fatal_chk.75411750
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.655312496
Short name T205
Test name
Test status
Simulation time 2248927872 ps
CPU time 22.24 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:29 PM PDT 24
Peak memory 220136 kb
Host smart-2bed4b4f-46d1-48c8-8b56-0c00476d00c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655312496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.655312496
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1094113188
Short name T45
Test name
Test status
Simulation time 524545959 ps
CPU time 12.24 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 219900 kb
Host smart-523748cd-beb0-46a6-9c75-3f01f5cc1514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094113188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1094113188
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1602853469
Short name T194
Test name
Test status
Simulation time 350530462 ps
CPU time 23.42 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 220008 kb
Host smart-80dc0357-3436-4a83-9276-69f85819022b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602853469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1602853469
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.106463633
Short name T12
Test name
Test status
Simulation time 28445431566 ps
CPU time 1203.67 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:23:59 PM PDT 24
Peak memory 236928 kb
Host smart-9fc23107-03f4-49bc-802a-04c4b8bdb87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106463633 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.106463633
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2688829665
Short name T249
Test name
Test status
Simulation time 345861780 ps
CPU time 10.2 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219048 kb
Host smart-4b76bfc0-dd2a-483c-b1ca-4ee49aa73bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688829665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2688829665
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1498149498
Short name T157
Test name
Test status
Simulation time 14747311244 ps
CPU time 274.41 seconds
Started Jul 31 05:04:09 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 220224 kb
Host smart-bbcf42e9-9a9b-40e9-a1e2-da442d9dca93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498149498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1498149498
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3214610230
Short name T287
Test name
Test status
Simulation time 989252676 ps
CPU time 22.53 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 219960 kb
Host smart-9f33f802-0445-4929-998e-b89af1fd0055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214610230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3214610230
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.867920524
Short name T285
Test name
Test status
Simulation time 722377664 ps
CPU time 10.28 seconds
Started Jul 31 05:03:48 PM PDT 24
Finished Jul 31 05:03:58 PM PDT 24
Peak memory 219960 kb
Host smart-4407d4db-524d-4685-8e26-cb4c7d53a02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867920524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.867920524
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3227898373
Short name T254
Test name
Test status
Simulation time 19791670389 ps
CPU time 68.62 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:05:08 PM PDT 24
Peak memory 220092 kb
Host smart-76678e03-4a9d-4844-aae4-8dc72996b923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227898373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3227898373
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4223597799
Short name T297
Test name
Test status
Simulation time 993357156 ps
CPU time 9.75 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 219112 kb
Host smart-4eb315d9-d0cd-4ee8-9e36-b38ea42dc624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223597799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4223597799
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2727579162
Short name T283
Test name
Test status
Simulation time 30865768021 ps
CPU time 287.25 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 239676 kb
Host smart-3a8611e2-ed24-4615-9a53-20c8e159cdea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727579162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2727579162
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3770214631
Short name T168
Test name
Test status
Simulation time 2154974966 ps
CPU time 22.48 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 220060 kb
Host smart-e20e0d95-0c43-4e2c-aa01-06c4c6ffd367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770214631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3770214631
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.376907797
Short name T62
Test name
Test status
Simulation time 186689872 ps
CPU time 10.55 seconds
Started Jul 31 05:03:55 PM PDT 24
Finished Jul 31 05:04:06 PM PDT 24
Peak memory 219956 kb
Host smart-443f82f9-ef7d-498c-9821-435d0b078378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376907797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.376907797
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.480663381
Short name T183
Test name
Test status
Simulation time 3108894023 ps
CPU time 14.65 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:17 PM PDT 24
Peak memory 220080 kb
Host smart-c438af9d-5ca7-4350-a91a-75318753c074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480663381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.480663381
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1631041930
Short name T109
Test name
Test status
Simulation time 172018200 ps
CPU time 8.21 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 219084 kb
Host smart-2fa8e0bc-ffdd-4cdf-96a5-b70dfe0b282d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631041930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1631041930
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.70336338
Short name T251
Test name
Test status
Simulation time 28141136834 ps
CPU time 404.63 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:10:48 PM PDT 24
Peak memory 239568 kb
Host smart-ee84d26d-06b8-4b48-95b9-03c4d94b117c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70336338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.70336338
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2481054767
Short name T188
Test name
Test status
Simulation time 4026565020 ps
CPU time 31.82 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 219492 kb
Host smart-c85a9040-f376-42da-9d58-58c1507dde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481054767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2481054767
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3978969889
Short name T214
Test name
Test status
Simulation time 356691443 ps
CPU time 10.52 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 219908 kb
Host smart-7877acee-01a5-4597-b32d-7352794acc43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978969889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3978969889
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.416891158
Short name T312
Test name
Test status
Simulation time 1045392933 ps
CPU time 48.67 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:51 PM PDT 24
Peak memory 220744 kb
Host smart-d3fcc417-bc78-463c-98a1-43020a590cb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416891158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.416891158
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3606965433
Short name T202
Test name
Test status
Simulation time 917451798 ps
CPU time 9.98 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:04:07 PM PDT 24
Peak memory 218988 kb
Host smart-1a663b20-c2e8-4443-920c-aaeb4b2e0dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606965433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3606965433
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3327938272
Short name T305
Test name
Test status
Simulation time 3199100093 ps
CPU time 230.11 seconds
Started Jul 31 05:03:58 PM PDT 24
Finished Jul 31 05:07:48 PM PDT 24
Peak memory 239492 kb
Host smart-c333d63e-3cbc-40e8-b9fa-b77e22c7243b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327938272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3327938272
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4011776284
Short name T314
Test name
Test status
Simulation time 332311888 ps
CPU time 19.32 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 220008 kb
Host smart-389fa5c6-c494-4caf-9139-90cd144692c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011776284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4011776284
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3950252006
Short name T158
Test name
Test status
Simulation time 734060148 ps
CPU time 10.4 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 220016 kb
Host smart-399ea018-478d-4f10-84ee-31eb97e768ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950252006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3950252006
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1789976185
Short name T250
Test name
Test status
Simulation time 1083582944 ps
CPU time 22.34 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:28 PM PDT 24
Peak memory 219896 kb
Host smart-1b4ff0fe-788e-4b03-a56e-4eac3c30c6ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789976185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1789976185
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3562649980
Short name T54
Test name
Test status
Simulation time 14594083514 ps
CPU time 586.1 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:13:44 PM PDT 24
Peak memory 236624 kb
Host smart-c3a6dedb-f8fc-4917-aba4-4ddc2b324e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562649980 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3562649980
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1874597854
Short name T240
Test name
Test status
Simulation time 1034964086 ps
CPU time 10.36 seconds
Started Jul 31 05:03:57 PM PDT 24
Finished Jul 31 05:04:08 PM PDT 24
Peak memory 218956 kb
Host smart-6d0d4397-5ae7-496c-8134-fd2c7bd4d01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874597854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1874597854
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2364056510
Short name T260
Test name
Test status
Simulation time 12058256566 ps
CPU time 218.78 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:07:38 PM PDT 24
Peak memory 239664 kb
Host smart-a7fa17d8-0f59-4718-97b4-52832f364974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364056510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2364056510
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3400877583
Short name T217
Test name
Test status
Simulation time 334450663 ps
CPU time 19.24 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:22 PM PDT 24
Peak memory 219956 kb
Host smart-38611b38-744d-40ed-a2e3-c5e13652e7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400877583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3400877583
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.7754692
Short name T29
Test name
Test status
Simulation time 531318508 ps
CPU time 12.04 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 220032 kb
Host smart-9ca269ac-bf38-460b-a4dd-dce08db18102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7754692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.7754692
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3964241090
Short name T8
Test name
Test status
Simulation time 1983794705 ps
CPU time 40.62 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:45 PM PDT 24
Peak memory 219892 kb
Host smart-97a53739-2ea1-4f6d-b1e8-9effe32db9fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964241090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3964241090
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2693146456
Short name T277
Test name
Test status
Simulation time 1177646501 ps
CPU time 9.8 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 218976 kb
Host smart-03f5fdbf-eca3-428b-a29d-b19c0c151bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693146456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2693146456
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3746057436
Short name T246
Test name
Test status
Simulation time 19720695920 ps
CPU time 212.57 seconds
Started Jul 31 05:04:10 PM PDT 24
Finished Jul 31 05:07:43 PM PDT 24
Peak memory 239640 kb
Host smart-810e5a9d-5706-4ca4-914e-e5e797be7ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746057436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3746057436
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.121610846
Short name T279
Test name
Test status
Simulation time 333905088 ps
CPU time 18.96 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 219964 kb
Host smart-ad68e1f5-4fee-4fd2-8423-c5312d637562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121610846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.121610846
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.654541587
Short name T248
Test name
Test status
Simulation time 315024739 ps
CPU time 12.22 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:11 PM PDT 24
Peak memory 220036 kb
Host smart-fa2e50af-04a6-4a5c-aa21-14f17d1cad5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654541587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.654541587
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.928228163
Short name T78
Test name
Test status
Simulation time 1546705009 ps
CPU time 28.45 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:30 PM PDT 24
Peak memory 219920 kb
Host smart-564ceb78-bc04-4ab2-b47d-56f8ec65677f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928228163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.928228163
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1929689106
Short name T311
Test name
Test status
Simulation time 986514064 ps
CPU time 9.82 seconds
Started Jul 31 05:04:08 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 219072 kb
Host smart-e57c3342-e384-4b00-8e8b-6663bdb8764e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929689106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1929689106
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3204733451
Short name T107
Test name
Test status
Simulation time 42420330642 ps
CPU time 429.31 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:11:15 PM PDT 24
Peak memory 240856 kb
Host smart-da6c7d60-ca7d-4e9b-8bc0-4c9afec36b66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204733451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3204733451
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2749984972
Short name T42
Test name
Test status
Simulation time 1648591448 ps
CPU time 19.24 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:24 PM PDT 24
Peak memory 220052 kb
Host smart-adb8192b-3d6a-499d-8b75-6a308d1d5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749984972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2749984972
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.292580237
Short name T294
Test name
Test status
Simulation time 683538237 ps
CPU time 10.02 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219956 kb
Host smart-331496cb-e079-411a-9f68-91d5bebae219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292580237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.292580237
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3248759421
Short name T14
Test name
Test status
Simulation time 4378384134 ps
CPU time 31.12 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 220112 kb
Host smart-b5ca0b51-72c5-4d8f-9718-b0545ae86b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248759421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3248759421
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.973336426
Short name T51
Test name
Test status
Simulation time 151000663950 ps
CPU time 3116.11 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:56:04 PM PDT 24
Peak memory 252972 kb
Host smart-5d044938-d99c-4f13-87ce-a04a74d4ab1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973336426 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.973336426
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1814020574
Short name T176
Test name
Test status
Simulation time 167404096 ps
CPU time 8.68 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219064 kb
Host smart-3010deb6-2e03-4f5e-ae94-5c784d100fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814020574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1814020574
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3785240721
Short name T134
Test name
Test status
Simulation time 16576195472 ps
CPU time 203.62 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:07:27 PM PDT 24
Peak memory 227276 kb
Host smart-f9b8884b-518f-4b40-8f93-04bf8f21136b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785240721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3785240721
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3000537130
Short name T132
Test name
Test status
Simulation time 994054219 ps
CPU time 22.27 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 219960 kb
Host smart-e9b2469f-590f-434c-bdd1-8b81ea68ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000537130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3000537130
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1451948535
Short name T185
Test name
Test status
Simulation time 293572289 ps
CPU time 12.11 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219936 kb
Host smart-ef58d40f-ae45-4057-8806-d1279ac46dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451948535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1451948535
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.847163247
Short name T74
Test name
Test status
Simulation time 532496466 ps
CPU time 33.26 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:39 PM PDT 24
Peak memory 219940 kb
Host smart-dd9d250a-c972-43f7-8b88-2d2ba2815128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847163247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.847163247
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3172388076
Short name T161
Test name
Test status
Simulation time 346156649 ps
CPU time 8.37 seconds
Started Jul 31 05:03:33 PM PDT 24
Finished Jul 31 05:03:41 PM PDT 24
Peak memory 218948 kb
Host smart-c7fa0115-d762-4f85-bdb3-5f50cdb8d3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172388076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3172388076
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3863000614
Short name T213
Test name
Test status
Simulation time 3181270959 ps
CPU time 152.08 seconds
Started Jul 31 05:03:24 PM PDT 24
Finished Jul 31 05:05:57 PM PDT 24
Peak memory 229084 kb
Host smart-e9e613bf-88ad-4071-9e58-f93619a95648
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863000614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3863000614
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4161305819
Short name T207
Test name
Test status
Simulation time 1979893290 ps
CPU time 22.33 seconds
Started Jul 31 05:03:33 PM PDT 24
Finished Jul 31 05:03:55 PM PDT 24
Peak memory 220060 kb
Host smart-480bacea-8e9b-4074-be8c-a277c8a212d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161305819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4161305819
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.719532276
Short name T137
Test name
Test status
Simulation time 499716909 ps
CPU time 11.77 seconds
Started Jul 31 05:03:19 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 220064 kb
Host smart-7210f21a-d2c5-4ca1-99fe-4933d86bf70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719532276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.719532276
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1111348056
Short name T115
Test name
Test status
Simulation time 1073614338 ps
CPU time 12.23 seconds
Started Jul 31 05:03:51 PM PDT 24
Finished Jul 31 05:04:03 PM PDT 24
Peak memory 219744 kb
Host smart-56c628b6-4e7d-4162-a964-0ed891d96193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111348056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1111348056
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3865354690
Short name T189
Test name
Test status
Simulation time 1873442995 ps
CPU time 35.52 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:04:25 PM PDT 24
Peak memory 219916 kb
Host smart-803aa20d-4614-4f57-8c5a-b827538daee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865354690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3865354690
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3468355959
Short name T219
Test name
Test status
Simulation time 340122592 ps
CPU time 8.24 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 218980 kb
Host smart-4c1767ef-9e91-4809-b1e5-87d25998396c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468355959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3468355959
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3315695759
Short name T234
Test name
Test status
Simulation time 2705903967 ps
CPU time 149.96 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:06:35 PM PDT 24
Peak memory 241344 kb
Host smart-4ccd5b61-6cb1-4ad9-a706-6e3e5cb1b88f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315695759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3315695759
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.72239399
Short name T149
Test name
Test status
Simulation time 501706718 ps
CPU time 22.93 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:30 PM PDT 24
Peak memory 220044 kb
Host smart-08796611-9686-4edd-91a4-8749c8a95105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72239399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.72239399
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1703376266
Short name T139
Test name
Test status
Simulation time 3622317885 ps
CPU time 12.14 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 220156 kb
Host smart-154e2dc3-f813-43b3-9003-6b7ed576a968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703376266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1703376266
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2945932373
Short name T253
Test name
Test status
Simulation time 585808432 ps
CPU time 16.79 seconds
Started Jul 31 05:03:59 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219880 kb
Host smart-1e0c220f-fdf2-4d90-a7ca-2debe3bef91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945932373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2945932373
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2904055385
Short name T164
Test name
Test status
Simulation time 262980889 ps
CPU time 10.4 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219040 kb
Host smart-82732ba2-0700-490e-bcb1-2371c7a3048c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904055385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2904055385
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.259829963
Short name T126
Test name
Test status
Simulation time 6320030522 ps
CPU time 118.68 seconds
Started Jul 31 05:03:58 PM PDT 24
Finished Jul 31 05:05:57 PM PDT 24
Peak memory 225708 kb
Host smart-2b7d2b87-64f2-48ab-9e33-b90770459f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259829963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.259829963
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.207457410
Short name T310
Test name
Test status
Simulation time 2053090903 ps
CPU time 22.6 seconds
Started Jul 31 05:04:14 PM PDT 24
Finished Jul 31 05:04:37 PM PDT 24
Peak memory 219960 kb
Host smart-fe3e3bbb-6b21-4155-acb7-def275de2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207457410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.207457410
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2681439661
Short name T190
Test name
Test status
Simulation time 1468485723 ps
CPU time 10.67 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 220072 kb
Host smart-7a6a3e15-3feb-4e09-8994-c07f429cfdd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681439661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2681439661
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1988243543
Short name T230
Test name
Test status
Simulation time 604780238 ps
CPU time 19.96 seconds
Started Jul 31 05:04:08 PM PDT 24
Finished Jul 31 05:04:28 PM PDT 24
Peak memory 219976 kb
Host smart-5f1a7c38-f09d-4ea2-8651-8bc5a4f189c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988243543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1988243543
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3705238005
Short name T143
Test name
Test status
Simulation time 1372973582 ps
CPU time 9.92 seconds
Started Jul 31 05:04:11 PM PDT 24
Finished Jul 31 05:04:21 PM PDT 24
Peak memory 219060 kb
Host smart-937c60bd-8487-432a-a2b9-5da6c8e0ec4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705238005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3705238005
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.219946936
Short name T30
Test name
Test status
Simulation time 6756982431 ps
CPU time 347.82 seconds
Started Jul 31 05:04:18 PM PDT 24
Finished Jul 31 05:10:06 PM PDT 24
Peak memory 231980 kb
Host smart-a21b9999-777b-4d14-bdfd-734d13182027
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219946936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.219946936
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.788936221
Short name T128
Test name
Test status
Simulation time 1981600430 ps
CPU time 22.03 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 219980 kb
Host smart-e0680e41-981b-4002-8681-430732aa331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788936221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.788936221
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.975072432
Short name T296
Test name
Test status
Simulation time 1221159271 ps
CPU time 12.19 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 219960 kb
Host smart-6dfdca19-de27-4376-9043-a9b15c5591ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975072432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.975072432
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3083607093
Short name T4
Test name
Test status
Simulation time 2304704252 ps
CPU time 29.46 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:35 PM PDT 24
Peak memory 220016 kb
Host smart-72958ba7-ca5d-4f02-b6a0-7ae35475d81b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083607093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3083607093
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3842369289
Short name T196
Test name
Test status
Simulation time 340260160 ps
CPU time 8.18 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:13 PM PDT 24
Peak memory 218872 kb
Host smart-671de3a4-283d-41ea-8c7b-fc1052a21557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842369289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3842369289
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3749095506
Short name T247
Test name
Test status
Simulation time 5180516834 ps
CPU time 269.1 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:08:34 PM PDT 24
Peak memory 225688 kb
Host smart-7d9e2bbc-cb20-4129-ba09-3aa37e5fa0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749095506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3749095506
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.191945961
Short name T236
Test name
Test status
Simulation time 523411442 ps
CPU time 23.04 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:30 PM PDT 24
Peak memory 219964 kb
Host smart-7d5bbf29-9e3a-4b3e-af59-a71b6264d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191945961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.191945961
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3748646955
Short name T243
Test name
Test status
Simulation time 260894834 ps
CPU time 12.25 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 220016 kb
Host smart-5afaf0f0-4fb5-4ad6-b7eb-d12fe753653c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748646955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3748646955
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4208012125
Short name T192
Test name
Test status
Simulation time 652686775 ps
CPU time 31.42 seconds
Started Jul 31 05:04:12 PM PDT 24
Finished Jul 31 05:04:44 PM PDT 24
Peak memory 220008 kb
Host smart-149473f4-d006-4cfd-9f82-316b2c617ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208012125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4208012125
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1104275268
Short name T113
Test name
Test status
Simulation time 251704397 ps
CPU time 10.07 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219112 kb
Host smart-49a6309d-2365-404a-9544-fb7c67c0427f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104275268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1104275268
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.914953808
Short name T116
Test name
Test status
Simulation time 27530854509 ps
CPU time 205.1 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:07:32 PM PDT 24
Peak memory 239644 kb
Host smart-14aeeb0e-13ab-41ae-8521-72d847c9cf80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914953808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.914953808
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1281473287
Short name T282
Test name
Test status
Simulation time 498150360 ps
CPU time 22.74 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:29 PM PDT 24
Peak memory 219956 kb
Host smart-ec2ed419-05e2-4bd5-95d5-14a560f79d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281473287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1281473287
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3486553784
Short name T175
Test name
Test status
Simulation time 376176371 ps
CPU time 10.47 seconds
Started Jul 31 05:04:08 PM PDT 24
Finished Jul 31 05:04:19 PM PDT 24
Peak memory 220052 kb
Host smart-a3f3d2bb-6bed-4644-a26e-85028497fc6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486553784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3486553784
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.160820623
Short name T167
Test name
Test status
Simulation time 1116687516 ps
CPU time 20.29 seconds
Started Jul 31 05:04:02 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 219960 kb
Host smart-371905e8-694d-4ac1-880f-40576ca504cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160820623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.160820623
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1358128114
Short name T221
Test name
Test status
Simulation time 1033821073 ps
CPU time 9.85 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:14 PM PDT 24
Peak memory 219012 kb
Host smart-659aa2ec-308a-4d74-ba3c-aaf542d39473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358128114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1358128114
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4054989148
Short name T20
Test name
Test status
Simulation time 3950313802 ps
CPU time 319.48 seconds
Started Jul 31 05:04:14 PM PDT 24
Finished Jul 31 05:09:33 PM PDT 24
Peak memory 239248 kb
Host smart-8007e902-9bd3-4e7d-a12d-e9f091d4ad29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054989148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4054989148
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3658646200
Short name T129
Test name
Test status
Simulation time 518928027 ps
CPU time 22.02 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:29 PM PDT 24
Peak memory 219944 kb
Host smart-c6800f9a-80f3-4edc-a67b-9c3a990e9eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658646200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3658646200
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1968458918
Short name T309
Test name
Test status
Simulation time 261130974 ps
CPU time 11.91 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:19 PM PDT 24
Peak memory 219988 kb
Host smart-586a9bbb-1ece-4b1f-b7e1-eca46fb0b432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968458918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1968458918
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3717037168
Short name T93
Test name
Test status
Simulation time 1125179091 ps
CPU time 20.08 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:24 PM PDT 24
Peak memory 220012 kb
Host smart-81c826c0-0d6d-4f0f-9863-ed5553221012
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717037168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3717037168
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2976638765
Short name T120
Test name
Test status
Simulation time 209334678 ps
CPU time 8.56 seconds
Started Jul 31 05:04:10 PM PDT 24
Finished Jul 31 05:04:18 PM PDT 24
Peak memory 218536 kb
Host smart-dcc8ba2a-92cb-4e28-a3ab-6e993945156d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976638765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2976638765
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4015839653
Short name T146
Test name
Test status
Simulation time 3087823406 ps
CPU time 22.29 seconds
Started Jul 31 05:04:03 PM PDT 24
Finished Jul 31 05:04:26 PM PDT 24
Peak memory 220100 kb
Host smart-57b02ef1-9e8d-43c1-aa0b-5ff8e9e3c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015839653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4015839653
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3098999333
Short name T160
Test name
Test status
Simulation time 182648861 ps
CPU time 10.7 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:15 PM PDT 24
Peak memory 219900 kb
Host smart-cff362a7-a0c3-4c55-a3a1-56a508e386ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098999333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3098999333
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1193892148
Short name T13
Test name
Test status
Simulation time 15274500881 ps
CPU time 39.13 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:46 PM PDT 24
Peak memory 220080 kb
Host smart-9e7c35c9-1437-4da6-93d2-6203275c9ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193892148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1193892148
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3688467381
Short name T31
Test name
Test status
Simulation time 487446786 ps
CPU time 10.06 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 218780 kb
Host smart-a9d7fadc-7d6b-4135-8f05-035394a66d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688467381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3688467381
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3329437566
Short name T142
Test name
Test status
Simulation time 7381839507 ps
CPU time 275.88 seconds
Started Jul 31 05:04:09 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 235464 kb
Host smart-8a8beeaf-698a-46b6-90a5-590a50763720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329437566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3329437566
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1601986187
Short name T111
Test name
Test status
Simulation time 4120681243 ps
CPU time 22.74 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:30 PM PDT 24
Peak memory 220040 kb
Host smart-07d167e1-8084-4977-8c35-1fdd191167b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601986187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1601986187
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4260900224
Short name T108
Test name
Test status
Simulation time 1098623622 ps
CPU time 10.31 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:16 PM PDT 24
Peak memory 219980 kb
Host smart-54cae67c-257b-4701-b33c-022382674851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260900224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4260900224
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1300401541
Short name T228
Test name
Test status
Simulation time 2106873270 ps
CPU time 40.91 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:48 PM PDT 24
Peak memory 219864 kb
Host smart-ac827b57-5430-46ec-bb82-6168e8cef22e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300401541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1300401541
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1049030015
Short name T295
Test name
Test status
Simulation time 1648083181 ps
CPU time 8.41 seconds
Started Jul 31 05:04:22 PM PDT 24
Finished Jul 31 05:04:31 PM PDT 24
Peak memory 218940 kb
Host smart-0494318c-f76f-430d-8ba5-02d7942c461f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049030015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1049030015
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.577451938
Short name T121
Test name
Test status
Simulation time 3551210928 ps
CPU time 160.12 seconds
Started Jul 31 05:04:13 PM PDT 24
Finished Jul 31 05:06:58 PM PDT 24
Peak memory 232652 kb
Host smart-03ab38ff-ce24-446b-b4b3-fc9d1c25b0fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577451938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.577451938
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1474383132
Short name T151
Test name
Test status
Simulation time 339676716 ps
CPU time 19.08 seconds
Started Jul 31 05:04:16 PM PDT 24
Finished Jul 31 05:04:36 PM PDT 24
Peak memory 219984 kb
Host smart-ff5988e2-469b-44f0-8a88-59dfb4917a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474383132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1474383132
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3015182427
Short name T299
Test name
Test status
Simulation time 183390883 ps
CPU time 10.44 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:04:12 PM PDT 24
Peak memory 219956 kb
Host smart-579a6b26-a608-4f0a-99eb-fca9c74dc302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015182427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3015182427
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2578938760
Short name T263
Test name
Test status
Simulation time 825989874 ps
CPU time 14.68 seconds
Started Jul 31 05:04:16 PM PDT 24
Finished Jul 31 05:04:31 PM PDT 24
Peak memory 219976 kb
Host smart-f3908af8-3db6-4812-a48b-8f3cd809b046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578938760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2578938760
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2561990361
Short name T95
Test name
Test status
Simulation time 101820442540 ps
CPU time 2210.02 seconds
Started Jul 31 05:04:14 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 244832 kb
Host smart-dd0ce93e-a672-4c33-b406-7671c6568f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561990361 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2561990361
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3169689927
Short name T291
Test name
Test status
Simulation time 174736766 ps
CPU time 8.08 seconds
Started Jul 31 05:04:06 PM PDT 24
Finished Jul 31 05:04:24 PM PDT 24
Peak memory 219160 kb
Host smart-a4f00f8a-f16d-42e6-911e-e8aa9b15ceb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169689927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3169689927
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4065543105
Short name T180
Test name
Test status
Simulation time 25320408980 ps
CPU time 282.47 seconds
Started Jul 31 05:04:13 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 220232 kb
Host smart-86d0fd3a-85f5-471f-8eaf-948288f5d30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065543105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4065543105
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.369395388
Short name T119
Test name
Test status
Simulation time 515251682 ps
CPU time 22.42 seconds
Started Jul 31 05:04:07 PM PDT 24
Finished Jul 31 05:04:35 PM PDT 24
Peak memory 220092 kb
Host smart-2be75a0d-17c4-4872-8aff-ca8104740dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369395388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.369395388
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1504306664
Short name T233
Test name
Test status
Simulation time 990731713 ps
CPU time 12.22 seconds
Started Jul 31 05:04:05 PM PDT 24
Finished Jul 31 05:04:17 PM PDT 24
Peak memory 220040 kb
Host smart-a254916b-a8ff-43f0-9c85-8d8c1cc439b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504306664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1504306664
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2293524268
Short name T197
Test name
Test status
Simulation time 544501420 ps
CPU time 24.72 seconds
Started Jul 31 05:04:04 PM PDT 24
Finished Jul 31 05:04:29 PM PDT 24
Peak memory 219876 kb
Host smart-e9769880-55ed-4170-90e6-d873d1a54a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293524268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2293524268
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3447860503
Short name T265
Test name
Test status
Simulation time 688461533 ps
CPU time 8.31 seconds
Started Jul 31 05:03:22 PM PDT 24
Finished Jul 31 05:03:31 PM PDT 24
Peak memory 219008 kb
Host smart-11d1b87d-1be2-40a5-ba91-0f1f0d380aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447860503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3447860503
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1257807752
Short name T40
Test name
Test status
Simulation time 12147318080 ps
CPU time 226.77 seconds
Started Jul 31 05:03:38 PM PDT 24
Finished Jul 31 05:07:25 PM PDT 24
Peak memory 242524 kb
Host smart-5b1b7a22-f0d4-447f-9078-2d58257e930c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257807752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1257807752
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4203645954
Short name T117
Test name
Test status
Simulation time 347601967 ps
CPU time 19.28 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:04:04 PM PDT 24
Peak memory 219980 kb
Host smart-e211e7b1-1ac5-4dee-9601-c6f505eec6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203645954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4203645954
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.292717461
Short name T257
Test name
Test status
Simulation time 703285752 ps
CPU time 10.55 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:39 PM PDT 24
Peak memory 219964 kb
Host smart-f5de7632-26b0-4e35-a6a0-c105e8ea6587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292717461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.292717461
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.319954353
Short name T145
Test name
Test status
Simulation time 525044288 ps
CPU time 12.02 seconds
Started Jul 31 05:03:53 PM PDT 24
Finished Jul 31 05:04:05 PM PDT 24
Peak memory 219932 kb
Host smart-c7578c29-2f64-469f-9dcd-805eb555fa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319954353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.319954353
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1874471201
Short name T216
Test name
Test status
Simulation time 1564470863 ps
CPU time 42.45 seconds
Started Jul 31 05:03:40 PM PDT 24
Finished Jul 31 05:04:23 PM PDT 24
Peak memory 219888 kb
Host smart-f259c6fa-62a7-4a6d-a69b-f7b05709d9d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874471201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1874471201
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.117355580
Short name T3
Test name
Test status
Simulation time 346094330 ps
CPU time 8.22 seconds
Started Jul 31 05:03:39 PM PDT 24
Finished Jul 31 05:03:47 PM PDT 24
Peak memory 219040 kb
Host smart-812e11c7-eaa1-4763-b97d-0308f6fa29ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117355580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.117355580
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.639005156
Short name T1
Test name
Test status
Simulation time 4435539327 ps
CPU time 260.02 seconds
Started Jul 31 05:03:20 PM PDT 24
Finished Jul 31 05:07:41 PM PDT 24
Peak memory 239356 kb
Host smart-35ddac8f-a634-4cea-b257-8409429b9de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639005156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.639005156
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1992028488
Short name T165
Test name
Test status
Simulation time 2072259477 ps
CPU time 22.8 seconds
Started Jul 31 05:03:46 PM PDT 24
Finished Jul 31 05:04:09 PM PDT 24
Peak memory 219964 kb
Host smart-29653cba-591c-482d-ae16-94a2fa454a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992028488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1992028488
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2225861826
Short name T218
Test name
Test status
Simulation time 1027433330 ps
CPU time 12.23 seconds
Started Jul 31 05:03:34 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 219924 kb
Host smart-be0e9f35-fbf4-4dba-bf36-e7e94558b624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225861826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2225861826
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1626065364
Short name T72
Test name
Test status
Simulation time 2534412051 ps
CPU time 12.32 seconds
Started Jul 31 05:03:27 PM PDT 24
Finished Jul 31 05:03:39 PM PDT 24
Peak memory 219988 kb
Host smart-5fe487e8-8011-48d0-930a-456fb5e0217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626065364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1626065364
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2113393424
Short name T153
Test name
Test status
Simulation time 417373944 ps
CPU time 21.26 seconds
Started Jul 31 05:03:47 PM PDT 24
Finished Jul 31 05:04:08 PM PDT 24
Peak memory 219716 kb
Host smart-f6f52903-9ab7-4130-b69d-c1ce2115c35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113393424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2113393424
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3222380648
Short name T2
Test name
Test status
Simulation time 1268942905 ps
CPU time 8.26 seconds
Started Jul 31 05:03:44 PM PDT 24
Finished Jul 31 05:03:52 PM PDT 24
Peak memory 219012 kb
Host smart-2b1a7adf-f48e-4908-b3cc-3110a583dbaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222380648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3222380648
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3661681674
Short name T110
Test name
Test status
Simulation time 4075236715 ps
CPU time 228.77 seconds
Started Jul 31 05:03:43 PM PDT 24
Finished Jul 31 05:07:32 PM PDT 24
Peak memory 218852 kb
Host smart-765bd5dd-5a28-42ee-be99-54ba0ee8350c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661681674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3661681674
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.296679391
Short name T182
Test name
Test status
Simulation time 346816975 ps
CPU time 19.51 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:04:05 PM PDT 24
Peak memory 219988 kb
Host smart-27fe418a-6076-45f0-93c3-f3a930530cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296679391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.296679391
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1150070550
Short name T208
Test name
Test status
Simulation time 826128981 ps
CPU time 10.6 seconds
Started Jul 31 05:03:36 PM PDT 24
Finished Jul 31 05:03:46 PM PDT 24
Peak memory 219956 kb
Host smart-ae6b79c4-557a-4576-8ea0-98728a4317af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150070550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1150070550
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.333616802
Short name T92
Test name
Test status
Simulation time 260193350 ps
CPU time 11.69 seconds
Started Jul 31 05:03:51 PM PDT 24
Finished Jul 31 05:04:04 PM PDT 24
Peak memory 219980 kb
Host smart-6e1f5a42-76c6-47cc-9dd6-181171a4a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333616802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.333616802
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1839987583
Short name T199
Test name
Test status
Simulation time 280731073 ps
CPU time 26.67 seconds
Started Jul 31 05:03:32 PM PDT 24
Finished Jul 31 05:03:59 PM PDT 24
Peak memory 219968 kb
Host smart-95db03de-28bc-4498-a66d-f586d9a6a5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839987583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1839987583
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2185081
Short name T244
Test name
Test status
Simulation time 249715575 ps
CPU time 10.33 seconds
Started Jul 31 05:03:40 PM PDT 24
Finished Jul 31 05:03:50 PM PDT 24
Peak memory 218952 kb
Host smart-01a0f32d-4c4f-4bb0-8609-bbd27699d6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2185081
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.365662908
Short name T266
Test name
Test status
Simulation time 1269812181 ps
CPU time 19.27 seconds
Started Jul 31 05:03:41 PM PDT 24
Finished Jul 31 05:04:00 PM PDT 24
Peak memory 220040 kb
Host smart-d3e9257b-f9e7-4ca3-8a8a-c8b7a781cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365662908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.365662908
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3677916284
Short name T245
Test name
Test status
Simulation time 1025603394 ps
CPU time 11.12 seconds
Started Jul 31 05:03:50 PM PDT 24
Finished Jul 31 05:04:01 PM PDT 24
Peak memory 220252 kb
Host smart-2172dd28-4fc2-45eb-aa45-3543bcd1a2e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677916284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3677916284
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1640602141
Short name T172
Test name
Test status
Simulation time 366176220 ps
CPU time 10.69 seconds
Started Jul 31 05:03:49 PM PDT 24
Finished Jul 31 05:03:59 PM PDT 24
Peak memory 219964 kb
Host smart-6a5fe707-5d7f-44ea-970a-13c671715374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640602141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1640602141
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3851440852
Short name T241
Test name
Test status
Simulation time 15740412211 ps
CPU time 59.23 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:04:27 PM PDT 24
Peak memory 220016 kb
Host smart-1892bbb6-1a2f-462a-877f-c73966713faf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851440852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3851440852
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3909040517
Short name T262
Test name
Test status
Simulation time 868282853 ps
CPU time 8.26 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:37 PM PDT 24
Peak memory 219024 kb
Host smart-8d400937-9c25-430f-a60f-3153770590ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909040517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3909040517
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.328688723
Short name T6
Test name
Test status
Simulation time 3561699557 ps
CPU time 189.09 seconds
Started Jul 31 05:04:01 PM PDT 24
Finished Jul 31 05:07:10 PM PDT 24
Peak memory 229188 kb
Host smart-0b922507-75fa-4ec1-b33f-0f651059617b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328688723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.328688723
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.641101536
Short name T186
Test name
Test status
Simulation time 333983703 ps
CPU time 20.13 seconds
Started Jul 31 05:04:00 PM PDT 24
Finished Jul 31 05:04:20 PM PDT 24
Peak memory 219952 kb
Host smart-a9a42b57-a682-461b-acbd-667f0786e8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641101536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.641101536
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1708833281
Short name T91
Test name
Test status
Simulation time 175836127 ps
CPU time 10.34 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:39 PM PDT 24
Peak memory 219932 kb
Host smart-a872a283-11ac-4b02-8791-1f2f93b127d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708833281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1708833281
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1472127475
Short name T75
Test name
Test status
Simulation time 1067957091 ps
CPU time 12.55 seconds
Started Jul 31 05:03:45 PM PDT 24
Finished Jul 31 05:03:58 PM PDT 24
Peak memory 220036 kb
Host smart-16e09f0e-5dc3-438a-b09b-feb6084c71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472127475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1472127475
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2198519606
Short name T206
Test name
Test status
Simulation time 1946503888 ps
CPU time 18.57 seconds
Started Jul 31 05:03:29 PM PDT 24
Finished Jul 31 05:03:48 PM PDT 24
Peak memory 220004 kb
Host smart-bb4921d5-13df-46b0-b6cd-a991c548236c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198519606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2198519606
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.927858554
Short name T96
Test name
Test status
Simulation time 42046323733 ps
CPU time 1604.9 seconds
Started Jul 31 05:03:28 PM PDT 24
Finished Jul 31 05:30:13 PM PDT 24
Peak memory 237160 kb
Host smart-2220e08f-9929-4d10-ae8d-867f9770acfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927858554 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.927858554
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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