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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 407
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T293 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3047754882 Aug 01 05:23:07 PM PDT 24 Aug 01 05:23:30 PM PDT 24 511566376 ps
T294 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1992548740 Aug 01 05:22:57 PM PDT 24 Aug 01 05:23:20 PM PDT 24 1971762794 ps
T295 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.995125044 Aug 01 05:22:45 PM PDT 24 Aug 01 05:22:57 PM PDT 24 269695138 ps
T296 /workspace/coverage/default/44.rom_ctrl_alert_test.3117570197 Aug 01 05:23:43 PM PDT 24 Aug 01 05:23:58 PM PDT 24 981739247 ps
T297 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.230107609 Aug 01 05:22:46 PM PDT 24 Aug 01 05:23:08 PM PDT 24 528897956 ps
T298 /workspace/coverage/default/27.rom_ctrl_alert_test.1722841148 Aug 01 05:23:24 PM PDT 24 Aug 01 05:23:34 PM PDT 24 552111625 ps
T299 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3097757201 Aug 01 05:23:33 PM PDT 24 Aug 01 05:23:55 PM PDT 24 517449933 ps
T300 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3074582752 Aug 01 05:23:23 PM PDT 24 Aug 01 05:23:43 PM PDT 24 1323515212 ps
T301 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4124244696 Aug 01 05:22:47 PM PDT 24 Aug 01 05:23:10 PM PDT 24 2251686099 ps
T302 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2021474222 Aug 01 05:23:42 PM PDT 24 Aug 01 05:24:05 PM PDT 24 516504125 ps
T303 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.15056051 Aug 01 05:23:35 PM PDT 24 Aug 01 05:23:55 PM PDT 24 1504166929 ps
T304 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2940458455 Aug 01 05:23:35 PM PDT 24 Aug 01 05:24:09 PM PDT 24 9797784018 ps
T305 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1909809459 Aug 01 05:23:27 PM PDT 24 Aug 01 05:23:39 PM PDT 24 511807360 ps
T306 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1366028023 Aug 01 05:22:57 PM PDT 24 Aug 01 05:26:02 PM PDT 24 21994167286 ps
T307 /workspace/coverage/default/25.rom_ctrl_stress_all.2191584640 Aug 01 05:23:23 PM PDT 24 Aug 01 05:23:58 PM PDT 24 805954881 ps
T308 /workspace/coverage/default/2.rom_ctrl_smoke.1130279546 Aug 01 05:22:40 PM PDT 24 Aug 01 05:22:52 PM PDT 24 966016453 ps
T309 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3978167161 Aug 01 05:23:25 PM PDT 24 Aug 01 05:23:57 PM PDT 24 10852956385 ps
T310 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1492997160 Aug 01 05:23:11 PM PDT 24 Aug 01 05:23:34 PM PDT 24 1975508229 ps
T311 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2050767022 Aug 01 05:23:34 PM PDT 24 Aug 01 05:27:28 PM PDT 24 3475425474 ps
T312 /workspace/coverage/default/23.rom_ctrl_stress_all.2368771584 Aug 01 05:23:10 PM PDT 24 Aug 01 05:23:34 PM PDT 24 345691436 ps
T313 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.179644792 Aug 01 05:23:24 PM PDT 24 Aug 01 05:23:43 PM PDT 24 1380488219 ps
T314 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3953482879 Aug 01 05:23:21 PM PDT 24 Aug 01 05:23:32 PM PDT 24 181521069 ps
T315 /workspace/coverage/default/8.rom_ctrl_alert_test.37834821 Aug 01 05:22:45 PM PDT 24 Aug 01 05:22:54 PM PDT 24 339323882 ps
T316 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2824209896 Aug 01 05:23:40 PM PDT 24 Aug 01 05:27:21 PM PDT 24 12011959877 ps
T317 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1579849981 Aug 01 05:23:37 PM PDT 24 Aug 01 07:40:17 PM PDT 24 19370305266 ps
T318 /workspace/coverage/default/34.rom_ctrl_stress_all.2839315087 Aug 01 05:23:27 PM PDT 24 Aug 01 05:23:58 PM PDT 24 2091578627 ps
T319 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4214368815 Aug 01 05:23:20 PM PDT 24 Aug 01 05:23:36 PM PDT 24 3960358793 ps
T320 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1520655636 Aug 01 05:23:19 PM PDT 24 Aug 01 05:25:28 PM PDT 24 2669658706 ps
T321 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2378751377 Aug 01 05:22:57 PM PDT 24 Aug 01 05:23:16 PM PDT 24 1650184338 ps
T322 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4126204713 Aug 01 05:45:12 PM PDT 24 Aug 01 05:45:25 PM PDT 24 1035325497 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.490876477 Aug 01 05:45:27 PM PDT 24 Aug 01 05:45:36 PM PDT 24 696881892 ps
T66 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.86799108 Aug 01 05:45:25 PM PDT 24 Aug 01 05:45:35 PM PDT 24 1045035676 ps
T323 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3810414699 Aug 01 05:45:11 PM PDT 24 Aug 01 05:45:21 PM PDT 24 988235242 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.53728776 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:12 PM PDT 24 3083618355 ps
T75 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3509260692 Aug 01 05:45:46 PM PDT 24 Aug 01 05:45:54 PM PDT 24 1836312746 ps
T324 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4062414094 Aug 01 05:45:45 PM PDT 24 Aug 01 05:45:59 PM PDT 24 4954736587 ps
T325 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2631771918 Aug 01 05:45:28 PM PDT 24 Aug 01 05:45:41 PM PDT 24 1644735692 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2782737926 Aug 01 05:45:16 PM PDT 24 Aug 01 05:45:25 PM PDT 24 989748859 ps
T326 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1584379276 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:14 PM PDT 24 249744220 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1897670076 Aug 01 05:45:44 PM PDT 24 Aug 01 05:45:52 PM PDT 24 174701787 ps
T327 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2648832167 Aug 01 05:45:15 PM PDT 24 Aug 01 05:45:29 PM PDT 24 249825010 ps
T328 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2781913983 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:09 PM PDT 24 1098439048 ps
T329 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4002256822 Aug 01 05:45:28 PM PDT 24 Aug 01 05:45:47 PM PDT 24 1077599190 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2053461374 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:10 PM PDT 24 292016963 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.858603159 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:22 PM PDT 24 340098105 ps
T330 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2790681951 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:23 PM PDT 24 1226207530 ps
T331 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.778081668 Aug 01 05:45:45 PM PDT 24 Aug 01 05:46:00 PM PDT 24 1034743236 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3357389843 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:39 PM PDT 24 700977516 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2324138559 Aug 01 05:45:21 PM PDT 24 Aug 01 05:45:30 PM PDT 24 662930842 ps
T332 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1772162924 Aug 01 05:44:50 PM PDT 24 Aug 01 05:45:00 PM PDT 24 249516720 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3525797222 Aug 01 05:45:02 PM PDT 24 Aug 01 05:47:37 PM PDT 24 1293068144 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3437538282 Aug 01 05:45:01 PM PDT 24 Aug 01 05:46:24 PM PDT 24 1377834250 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3636575235 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:28 PM PDT 24 6572148747 ps
T333 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1872432346 Aug 01 05:45:30 PM PDT 24 Aug 01 05:45:41 PM PDT 24 520741167 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3137469957 Aug 01 05:44:51 PM PDT 24 Aug 01 05:46:15 PM PDT 24 978299639 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3136584293 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 169103726 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1782138629 Aug 01 05:45:01 PM PDT 24 Aug 01 05:47:34 PM PDT 24 328491461 ps
T334 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3820677433 Aug 01 05:45:44 PM PDT 24 Aug 01 05:45:52 PM PDT 24 1675143641 ps
T335 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2262424602 Aug 01 05:44:51 PM PDT 24 Aug 01 05:45:01 PM PDT 24 1031085329 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3905540229 Aug 01 05:45:00 PM PDT 24 Aug 01 05:45:10 PM PDT 24 518769303 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3267825618 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 167685518 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1069311782 Aug 01 05:45:24 PM PDT 24 Aug 01 05:46:45 PM PDT 24 279709783 ps
T336 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3701593654 Aug 01 05:45:48 PM PDT 24 Aug 01 05:46:08 PM PDT 24 989267614 ps
T337 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2714062246 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 174227721 ps
T338 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.114332007 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:23 PM PDT 24 265952966 ps
T339 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2730386264 Aug 01 05:44:59 PM PDT 24 Aug 01 05:45:09 PM PDT 24 254514372 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1091004327 Aug 01 05:45:46 PM PDT 24 Aug 01 05:45:55 PM PDT 24 168023478 ps
T340 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.183508079 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:40 PM PDT 24 988319690 ps
T113 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2340300873 Aug 01 05:45:12 PM PDT 24 Aug 01 05:46:34 PM PDT 24 4984180814 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.965141774 Aug 01 05:44:51 PM PDT 24 Aug 01 05:45:01 PM PDT 24 1034901638 ps
T341 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1692472175 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:26 PM PDT 24 1096590185 ps
T120 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1854436995 Aug 01 05:45:26 PM PDT 24 Aug 01 05:46:46 PM PDT 24 474570361 ps
T81 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2212890963 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:24 PM PDT 24 261517912 ps
T342 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3132919692 Aug 01 05:45:11 PM PDT 24 Aug 01 05:45:21 PM PDT 24 260656465 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2233847230 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:57 PM PDT 24 272345414 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2256955734 Aug 01 05:45:45 PM PDT 24 Aug 01 05:45:55 PM PDT 24 1375698550 ps
T343 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3480852499 Aug 01 05:45:12 PM PDT 24 Aug 01 05:45:22 PM PDT 24 496019999 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1636764031 Aug 01 05:44:47 PM PDT 24 Aug 01 05:44:58 PM PDT 24 1647792414 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4205632709 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:35 PM PDT 24 167402574 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3114684475 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:53 PM PDT 24 487184001 ps
T345 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3820578532 Aug 01 05:45:25 PM PDT 24 Aug 01 05:45:39 PM PDT 24 268948000 ps
T346 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3746587519 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:24 PM PDT 24 638345231 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3302311126 Aug 01 05:45:41 PM PDT 24 Aug 01 05:46:39 PM PDT 24 2155472081 ps
T347 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2008061470 Aug 01 05:45:45 PM PDT 24 Aug 01 05:45:53 PM PDT 24 185693034 ps
T348 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1257150883 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:10 PM PDT 24 176217955 ps
T349 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2619090340 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:56 PM PDT 24 280898793 ps
T350 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1813589805 Aug 01 05:45:30 PM PDT 24 Aug 01 05:45:44 PM PDT 24 661413442 ps
T351 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.627406692 Aug 01 05:45:28 PM PDT 24 Aug 01 05:45:39 PM PDT 24 612468872 ps
T352 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3376271167 Aug 01 05:45:42 PM PDT 24 Aug 01 05:45:51 PM PDT 24 1945407433 ps
T353 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2602728583 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:19 PM PDT 24 1048714831 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3511013525 Aug 01 05:45:44 PM PDT 24 Aug 01 05:48:19 PM PDT 24 6892586362 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.370895297 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:14 PM PDT 24 660969089 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2047112198 Aug 01 05:45:12 PM PDT 24 Aug 01 05:46:33 PM PDT 24 339525732 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1718914820 Aug 01 05:45:14 PM PDT 24 Aug 01 05:47:54 PM PDT 24 1265487203 ps
T355 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1764911451 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:28 PM PDT 24 507072515 ps
T356 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4067021606 Aug 01 05:45:27 PM PDT 24 Aug 01 05:45:37 PM PDT 24 260393334 ps
T357 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1582219692 Aug 01 05:45:27 PM PDT 24 Aug 01 05:45:43 PM PDT 24 994460692 ps
T358 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3576792905 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:22 PM PDT 24 167874879 ps
T359 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1572417165 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:27 PM PDT 24 255188137 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1864509866 Aug 01 05:44:52 PM PDT 24 Aug 01 05:45:00 PM PDT 24 207558744 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4134490066 Aug 01 05:45:26 PM PDT 24 Aug 01 05:48:04 PM PDT 24 8804526150 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.280037267 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:24 PM PDT 24 1653119827 ps
T91 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2313926917 Aug 01 05:45:24 PM PDT 24 Aug 01 05:46:09 PM PDT 24 1042247072 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2296133588 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:24 PM PDT 24 1988655152 ps
T363 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1162524418 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:27 PM PDT 24 254888570 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2953779102 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 1208063357 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4077229181 Aug 01 05:45:27 PM PDT 24 Aug 01 05:48:02 PM PDT 24 391691490 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.171465922 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:37 PM PDT 24 4109322954 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.420428466 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:42 PM PDT 24 1034466753 ps
T367 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3945413542 Aug 01 05:45:45 PM PDT 24 Aug 01 05:45:56 PM PDT 24 1022402600 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2686252098 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:10 PM PDT 24 167571188 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2244976382 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 661146423 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.620520823 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:34 PM PDT 24 190858508 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.141225516 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:17 PM PDT 24 260969356 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.544774893 Aug 01 05:44:51 PM PDT 24 Aug 01 05:45:00 PM PDT 24 1399521742 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3461846287 Aug 01 05:45:13 PM PDT 24 Aug 01 05:47:52 PM PDT 24 799429849 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2190052785 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:34 PM PDT 24 660565921 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2624161561 Aug 01 05:44:49 PM PDT 24 Aug 01 05:44:58 PM PDT 24 167736142 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3244045366 Aug 01 05:45:29 PM PDT 24 Aug 01 05:45:39 PM PDT 24 261017554 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2161762019 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:10 PM PDT 24 720237246 ps
T378 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3773871344 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:21 PM PDT 24 687772300 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3874772693 Aug 01 05:45:44 PM PDT 24 Aug 01 05:45:53 PM PDT 24 167556414 ps
T380 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3507597346 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:40 PM PDT 24 270684470 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1989254325 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:11 PM PDT 24 1032416563 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1826189063 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:29 PM PDT 24 517804346 ps
T118 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3815989744 Aug 01 05:45:43 PM PDT 24 Aug 01 05:47:04 PM PDT 24 927415039 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1684259320 Aug 01 05:45:00 PM PDT 24 Aug 01 05:45:10 PM PDT 24 1035322266 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1810740873 Aug 01 05:45:00 PM PDT 24 Aug 01 05:45:09 PM PDT 24 815528166 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.207730060 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:56 PM PDT 24 620202730 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2452922952 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:52 PM PDT 24 354009438 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2994766586 Aug 01 05:45:43 PM PDT 24 Aug 01 05:45:52 PM PDT 24 1272235191 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3005308164 Aug 01 05:45:13 PM PDT 24 Aug 01 05:47:46 PM PDT 24 1524573855 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2324720479 Aug 01 05:45:28 PM PDT 24 Aug 01 05:45:36 PM PDT 24 1651297168 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3090847108 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:30 PM PDT 24 379907503 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2835815715 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:16 PM PDT 24 350709741 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3871465285 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:23 PM PDT 24 690958678 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2638921460 Aug 01 05:45:03 PM PDT 24 Aug 01 05:45:13 PM PDT 24 315642519 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2203746452 Aug 01 05:45:01 PM PDT 24 Aug 01 05:45:11 PM PDT 24 249261520 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1876564137 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:10 PM PDT 24 338377092 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3605192575 Aug 01 05:45:02 PM PDT 24 Aug 01 05:45:17 PM PDT 24 173093761 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1897373950 Aug 01 05:45:28 PM PDT 24 Aug 01 05:46:54 PM PDT 24 376189345 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.247302207 Aug 01 05:45:57 PM PDT 24 Aug 01 05:46:10 PM PDT 24 252011203 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.887710446 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:25 PM PDT 24 520584825 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2950537948 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:36 PM PDT 24 1034764835 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3611829277 Aug 01 05:45:27 PM PDT 24 Aug 01 05:45:38 PM PDT 24 4959789091 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1410778435 Aug 01 05:44:52 PM PDT 24 Aug 01 05:45:05 PM PDT 24 1038536868 ps
T117 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1188787033 Aug 01 05:45:47 PM PDT 24 Aug 01 05:47:09 PM PDT 24 250377846 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4075861512 Aug 01 05:45:13 PM PDT 24 Aug 01 05:45:23 PM PDT 24 249631641 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3166532654 Aug 01 05:45:47 PM PDT 24 Aug 01 05:48:23 PM PDT 24 1573426705 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1797732097 Aug 01 05:45:45 PM PDT 24 Aug 01 05:45:57 PM PDT 24 278429460 ps
T111 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1295464523 Aug 01 05:45:27 PM PDT 24 Aug 01 05:48:02 PM PDT 24 1547886516 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2496374070 Aug 01 05:45:14 PM PDT 24 Aug 01 05:45:23 PM PDT 24 219356929 ps
T403 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1231453739 Aug 01 05:45:41 PM PDT 24 Aug 01 05:45:51 PM PDT 24 259753665 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4241137050 Aug 01 05:45:26 PM PDT 24 Aug 01 05:45:37 PM PDT 24 943172054 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3173567792 Aug 01 05:45:25 PM PDT 24 Aug 01 05:45:36 PM PDT 24 1805834746 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3989019100 Aug 01 05:45:04 PM PDT 24 Aug 01 05:45:12 PM PDT 24 826801538 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1722924977 Aug 01 05:45:43 PM PDT 24 Aug 01 05:48:17 PM PDT 24 1218586287 ps

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2044267173
Short name T1
Test name
Test status
Simulation time 53905214230 ps
CPU time 269.51 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 232320 kb
Host smart-b9cef53a-6db0-4339-a7d4-e5bbf68360ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044267173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2044267173
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1311369929
Short name T14
Test name
Test status
Simulation time 46724303696 ps
CPU time 7494.94 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 07:27:43 PM PDT 24
Peak memory 232528 kb
Host smart-e168ecd2-cf76-48c1-8f04-5fb4d3b0058b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311369929 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1311369929
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3688743122
Short name T12
Test name
Test status
Simulation time 212315617 ps
CPU time 14.82 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:26 PM PDT 24
Peak memory 219948 kb
Host smart-0b348f06-d3d6-467f-ac73-897a30dde55c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688743122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3688743122
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3867884412
Short name T22
Test name
Test status
Simulation time 4777379833 ps
CPU time 232.88 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:27:02 PM PDT 24
Peak memory 220348 kb
Host smart-b9fa70f0-f674-4e17-b708-169ca74a0d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867884412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3867884412
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.257119616
Short name T69
Test name
Test status
Simulation time 561065699 ps
CPU time 9.82 seconds
Started Aug 01 05:23:08 PM PDT 24
Finished Aug 01 05:23:18 PM PDT 24
Peak memory 219068 kb
Host smart-b84af0d8-7a70-44c8-b77f-c789dc89c25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257119616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.257119616
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1782138629
Short name T108
Test name
Test status
Simulation time 328491461 ps
CPU time 152.4 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:47:34 PM PDT 24
Peak memory 214312 kb
Host smart-e293982c-19f6-4c34-a0f3-8196d87c5178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782138629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1782138629
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.702573339
Short name T24
Test name
Test status
Simulation time 1055528405 ps
CPU time 119 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:24:44 PM PDT 24
Peak memory 236376 kb
Host smart-618fcdab-7054-4d22-87ad-05222a9cc85a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702573339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.702573339
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.599379795
Short name T6
Test name
Test status
Simulation time 334293518 ps
CPU time 19.26 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:08 PM PDT 24
Peak memory 219944 kb
Host smart-467eb1f3-3252-449c-accb-f268e5523c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599379795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.599379795
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.858603159
Short name T77
Test name
Test status
Simulation time 340098105 ps
CPU time 8.25 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:22 PM PDT 24
Peak memory 210920 kb
Host smart-76e60c03-6eda-40ae-a07e-f1960973aeff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858603159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.858603159
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3511013525
Short name T109
Test name
Test status
Simulation time 6892586362 ps
CPU time 154.71 seconds
Started Aug 01 05:45:44 PM PDT 24
Finished Aug 01 05:48:19 PM PDT 24
Peak memory 216052 kb
Host smart-9f47236a-64b9-44a4-a6da-8670edd4529e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511013525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3511013525
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1718914820
Short name T115
Test name
Test status
Simulation time 1265487203 ps
CPU time 160.45 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:47:54 PM PDT 24
Peak memory 219028 kb
Host smart-baa687d3-868b-43c4-aae2-854f7fb65112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718914820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1718914820
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.372584485
Short name T45
Test name
Test status
Simulation time 636842850 ps
CPU time 19.66 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:30 PM PDT 24
Peak memory 220104 kb
Host smart-43bc3e67-34f6-4e34-bbdf-3cb3a897fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372584485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.372584485
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1231794637
Short name T104
Test name
Test status
Simulation time 3972298654 ps
CPU time 16.2 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:23:41 PM PDT 24
Peak memory 219744 kb
Host smart-534b2530-2b63-4cc4-a3b7-0d7a8e9bcab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231794637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1231794637
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2616662345
Short name T17
Test name
Test status
Simulation time 9089016430 ps
CPU time 1722.3 seconds
Started Aug 01 05:22:58 PM PDT 24
Finished Aug 01 05:51:40 PM PDT 24
Peak memory 227456 kb
Host smart-71f02a00-e4bb-4deb-bd2c-a8bcd02c8d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616662345 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2616662345
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2313926917
Short name T91
Test name
Test status
Simulation time 1042247072 ps
CPU time 44.62 seconds
Started Aug 01 05:45:24 PM PDT 24
Finished Aug 01 05:46:09 PM PDT 24
Peak memory 214268 kb
Host smart-5650c5be-5596-45c2-9403-f258ccace1ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313926917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2313926917
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3302311126
Short name T107
Test name
Test status
Simulation time 2155472081 ps
CPU time 57.59 seconds
Started Aug 01 05:45:41 PM PDT 24
Finished Aug 01 05:46:39 PM PDT 24
Peak memory 215192 kb
Host smart-ac9ea86c-8886-4ff7-8041-62e560f9bae7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302311126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3302311126
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3815989744
Short name T118
Test name
Test status
Simulation time 927415039 ps
CPU time 80.58 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:47:04 PM PDT 24
Peak memory 214024 kb
Host smart-4990760d-0146-4395-81f7-9b2f97eae9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815989744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3815989744
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1660265971
Short name T16
Test name
Test status
Simulation time 202647653879 ps
CPU time 2123.45 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:58:34 PM PDT 24
Peak memory 244280 kb
Host smart-1ee9ed9c-dc1a-4dd7-8c5d-e0f2ab0f66f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660265971 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1660265971
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.965141774
Short name T80
Test name
Test status
Simulation time 1034901638 ps
CPU time 10.15 seconds
Started Aug 01 05:44:51 PM PDT 24
Finished Aug 01 05:45:01 PM PDT 24
Peak memory 211640 kb
Host smart-8b0bdc69-3df5-48e6-b264-60223e35cefe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965141774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.965141774
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2624161561
Short name T375
Test name
Test status
Simulation time 167736142 ps
CPU time 8.42 seconds
Started Aug 01 05:44:49 PM PDT 24
Finished Aug 01 05:44:58 PM PDT 24
Peak memory 211080 kb
Host smart-d7f8c16b-b586-46c9-8042-8052240e1c2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624161561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2624161561
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2262424602
Short name T335
Test name
Test status
Simulation time 1031085329 ps
CPU time 10.2 seconds
Started Aug 01 05:44:51 PM PDT 24
Finished Aug 01 05:45:01 PM PDT 24
Peak memory 210896 kb
Host smart-05084e9a-2805-4462-9760-a517754eefd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262424602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2262424602
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1410778435
Short name T398
Test name
Test status
Simulation time 1038536868 ps
CPU time 13.43 seconds
Started Aug 01 05:44:52 PM PDT 24
Finished Aug 01 05:45:05 PM PDT 24
Peak memory 210588 kb
Host smart-699a0413-88a0-4b90-a097-389db974afca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410778435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1410778435
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.544774893
Short name T372
Test name
Test status
Simulation time 1399521742 ps
CPU time 8.27 seconds
Started Aug 01 05:44:51 PM PDT 24
Finished Aug 01 05:45:00 PM PDT 24
Peak memory 219196 kb
Host smart-3ddbef44-e207-4c9d-96a0-264cd7f6b8e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544774893 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.544774893
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1636764031
Short name T344
Test name
Test status
Simulation time 1647792414 ps
CPU time 10.11 seconds
Started Aug 01 05:44:47 PM PDT 24
Finished Aug 01 05:44:58 PM PDT 24
Peak memory 210992 kb
Host smart-314a5265-ab0f-4cb9-a4fe-7fdb4b5e6b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636764031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1636764031
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1864509866
Short name T360
Test name
Test status
Simulation time 207558744 ps
CPU time 8.01 seconds
Started Aug 01 05:44:52 PM PDT 24
Finished Aug 01 05:45:00 PM PDT 24
Peak memory 210476 kb
Host smart-9f589a84-4898-45b9-88dc-645469f5633c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864509866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1864509866
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1772162924
Short name T332
Test name
Test status
Simulation time 249516720 ps
CPU time 9.82 seconds
Started Aug 01 05:44:50 PM PDT 24
Finished Aug 01 05:45:00 PM PDT 24
Peak memory 210760 kb
Host smart-ea88626b-8036-4b10-b652-94454e1870d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772162924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1772162924
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.247302207
Short name T395
Test name
Test status
Simulation time 252011203 ps
CPU time 13.66 seconds
Started Aug 01 05:45:57 PM PDT 24
Finished Aug 01 05:46:10 PM PDT 24
Peak memory 219000 kb
Host smart-40e089ec-46ca-4cca-9087-beda69e32aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247302207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.247302207
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3137469957
Short name T64
Test name
Test status
Simulation time 978299639 ps
CPU time 83.47 seconds
Started Aug 01 05:44:51 PM PDT 24
Finished Aug 01 05:46:15 PM PDT 24
Peak memory 214016 kb
Host smart-256c3b18-727d-433a-ad93-a1b8a318b0a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137469957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3137469957
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2053461374
Short name T100
Test name
Test status
Simulation time 292016963 ps
CPU time 8.5 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 211152 kb
Host smart-a7478659-1435-4ce6-b9e4-881d8285a283
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053461374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2053461374
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2730386264
Short name T339
Test name
Test status
Simulation time 254514372 ps
CPU time 9.82 seconds
Started Aug 01 05:44:59 PM PDT 24
Finished Aug 01 05:45:09 PM PDT 24
Peak memory 210928 kb
Host smart-8659c478-6f27-4cd7-9c04-1c9ff8b7990e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730386264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2730386264
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3605192575
Short name T393
Test name
Test status
Simulation time 173093761 ps
CPU time 15.12 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:17 PM PDT 24
Peak memory 212012 kb
Host smart-9ee30e38-f6be-4c10-9f15-91172ec562c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605192575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3605192575
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1810740873
Short name T384
Test name
Test status
Simulation time 815528166 ps
CPU time 8.46 seconds
Started Aug 01 05:45:00 PM PDT 24
Finished Aug 01 05:45:09 PM PDT 24
Peak memory 215608 kb
Host smart-7d5acdd1-693b-480a-b766-9d963e8c6496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810740873 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1810740873
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3905540229
Short name T78
Test name
Test status
Simulation time 518769303 ps
CPU time 9.9 seconds
Started Aug 01 05:45:00 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210796 kb
Host smart-482f05e3-25ba-4f8a-8e2e-36c5ab705653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905540229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3905540229
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1257150883
Short name T348
Test name
Test status
Simulation time 176217955 ps
CPU time 8.26 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210764 kb
Host smart-1439079f-72f1-428b-81cb-a72dd37775c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257150883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1257150883
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1684259320
Short name T383
Test name
Test status
Simulation time 1035322266 ps
CPU time 9.81 seconds
Started Aug 01 05:45:00 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210776 kb
Host smart-2b732ff7-21d8-42bf-be0d-63140857f79e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684259320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1684259320
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1876564137
Short name T392
Test name
Test status
Simulation time 338377092 ps
CPU time 8.23 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 211492 kb
Host smart-0f7440a0-2f35-46b9-a050-cb694575de1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876564137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1876564137
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.370895297
Short name T354
Test name
Test status
Simulation time 660969089 ps
CPU time 13.14 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:14 PM PDT 24
Peak memory 217792 kb
Host smart-bcc3ec80-bf95-47b5-b9d5-3316bb26e9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370895297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.370895297
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3437538282
Short name T63
Test name
Test status
Simulation time 1377834250 ps
CPU time 82.76 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:46:24 PM PDT 24
Peak memory 214088 kb
Host smart-92fd6008-03f2-4667-b2d3-409941fbaa31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437538282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3437538282
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1872432346
Short name T333
Test name
Test status
Simulation time 520741167 ps
CPU time 11.11 seconds
Started Aug 01 05:45:30 PM PDT 24
Finished Aug 01 05:45:41 PM PDT 24
Peak memory 217840 kb
Host smart-9036bbbc-28f2-4e2b-93d4-cf04b7bee948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872432346 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1872432346
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.620520823
Short name T370
Test name
Test status
Simulation time 190858508 ps
CPU time 7.99 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:34 PM PDT 24
Peak memory 210856 kb
Host smart-5f58c5f7-4633-4f3a-9482-65e733207d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620520823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.620520823
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2324138559
Short name T96
Test name
Test status
Simulation time 662930842 ps
CPU time 8.12 seconds
Started Aug 01 05:45:21 PM PDT 24
Finished Aug 01 05:45:30 PM PDT 24
Peak memory 211672 kb
Host smart-3ff27b0b-3c3e-49d2-9965-6006d9ae43ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324138559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2324138559
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.627406692
Short name T351
Test name
Test status
Simulation time 612468872 ps
CPU time 11.3 seconds
Started Aug 01 05:45:28 PM PDT 24
Finished Aug 01 05:45:39 PM PDT 24
Peak memory 217476 kb
Host smart-958b8d52-a1f3-432b-a9d9-ae3b6c18cabd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627406692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.627406692
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1295464523
Short name T111
Test name
Test status
Simulation time 1547886516 ps
CPU time 155.24 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:48:02 PM PDT 24
Peak memory 214404 kb
Host smart-b6fbc672-d71a-4138-a140-aa9223f82e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295464523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1295464523
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3244045366
Short name T376
Test name
Test status
Simulation time 261017554 ps
CPU time 10.03 seconds
Started Aug 01 05:45:29 PM PDT 24
Finished Aug 01 05:45:39 PM PDT 24
Peak memory 214360 kb
Host smart-647a4568-38db-45d3-a561-35b1a2e13a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244045366 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3244045366
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2950537948
Short name T94
Test name
Test status
Simulation time 1034764835 ps
CPU time 10 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:36 PM PDT 24
Peak memory 211284 kb
Host smart-adf25ef3-a990-46a1-8215-10ea5fd3f6f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950537948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2950537948
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.420428466
Short name T366
Test name
Test status
Simulation time 1034466753 ps
CPU time 15.09 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:42 PM PDT 24
Peak memory 211512 kb
Host smart-ce96c4db-70ff-4eec-91ef-86880539c25a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420428466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.420428466
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3507597346
Short name T380
Test name
Test status
Simulation time 270684470 ps
CPU time 13.43 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:40 PM PDT 24
Peak memory 217640 kb
Host smart-9cf1fd40-6ddf-49d8-9464-343db5a443a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507597346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3507597346
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1897373950
Short name T394
Test name
Test status
Simulation time 376189345 ps
CPU time 85.37 seconds
Started Aug 01 05:45:28 PM PDT 24
Finished Aug 01 05:46:54 PM PDT 24
Peak memory 213056 kb
Host smart-870f07a7-7acc-4362-a06a-ddc48c12922f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897373950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1897373950
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4241137050
Short name T404
Test name
Test status
Simulation time 943172054 ps
CPU time 10.53 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:37 PM PDT 24
Peak memory 215924 kb
Host smart-8056d6ca-aba9-480d-a9c0-3764bb33ff89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241137050 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4241137050
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2190052785
Short name T374
Test name
Test status
Simulation time 660565921 ps
CPU time 8.08 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:34 PM PDT 24
Peak memory 210684 kb
Host smart-3ebefbe7-16ff-46e8-b11b-ad845f7747e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190052785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2190052785
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3611829277
Short name T397
Test name
Test status
Simulation time 4959789091 ps
CPU time 10.26 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:45:38 PM PDT 24
Peak memory 212048 kb
Host smart-8d13e95b-254b-47bc-a47b-54f9a1700a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611829277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3611829277
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.183508079
Short name T340
Test name
Test status
Simulation time 988319690 ps
CPU time 13.5 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:40 PM PDT 24
Peak memory 217740 kb
Host smart-279bf37a-5063-4a36-b5d8-7e8fa15c8670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183508079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.183508079
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1069311782
Short name T112
Test name
Test status
Simulation time 279709783 ps
CPU time 80.39 seconds
Started Aug 01 05:45:24 PM PDT 24
Finished Aug 01 05:46:45 PM PDT 24
Peak memory 213724 kb
Host smart-6294f9b5-6ebb-4ed1-9575-9e488103fc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069311782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1069311782
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.86799108
Short name T66
Test name
Test status
Simulation time 1045035676 ps
CPU time 10.17 seconds
Started Aug 01 05:45:25 PM PDT 24
Finished Aug 01 05:45:35 PM PDT 24
Peak memory 215736 kb
Host smart-2db32a95-bda8-4006-8f8a-3330c323189c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86799108 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.86799108
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2324720479
Short name T388
Test name
Test status
Simulation time 1651297168 ps
CPU time 8.38 seconds
Started Aug 01 05:45:28 PM PDT 24
Finished Aug 01 05:45:36 PM PDT 24
Peak memory 210780 kb
Host smart-68492d04-4c42-4346-932c-d5b2e2eb233c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324720479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2324720479
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.171465922
Short name T365
Test name
Test status
Simulation time 4109322954 ps
CPU time 10.06 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:37 PM PDT 24
Peak memory 211576 kb
Host smart-ff4b454d-0319-41cc-9983-9b902d650df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171465922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.171465922
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4002256822
Short name T329
Test name
Test status
Simulation time 1077599190 ps
CPU time 19.04 seconds
Started Aug 01 05:45:28 PM PDT 24
Finished Aug 01 05:45:47 PM PDT 24
Peak memory 219132 kb
Host smart-b1d5b722-adc7-4ef4-b8c3-97ac9e71a605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002256822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4002256822
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4077229181
Short name T110
Test name
Test status
Simulation time 391691490 ps
CPU time 154.76 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:48:02 PM PDT 24
Peak memory 214228 kb
Host smart-cf1d13a0-4465-4274-bc04-a759346365a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077229181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4077229181
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3173567792
Short name T405
Test name
Test status
Simulation time 1805834746 ps
CPU time 10.65 seconds
Started Aug 01 05:45:25 PM PDT 24
Finished Aug 01 05:45:36 PM PDT 24
Peak memory 215276 kb
Host smart-955d1846-f1e6-4133-abb9-963894170326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173567792 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3173567792
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4067021606
Short name T356
Test name
Test status
Simulation time 260393334 ps
CPU time 9.96 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:45:37 PM PDT 24
Peak memory 210932 kb
Host smart-24c7e41b-53ad-4d5d-9fd7-3b678d1396e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067021606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4067021606
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1582219692
Short name T357
Test name
Test status
Simulation time 994460692 ps
CPU time 15.15 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:45:43 PM PDT 24
Peak memory 211772 kb
Host smart-ba7f0e4e-d288-484e-b632-37302de8af99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582219692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1582219692
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2631771918
Short name T325
Test name
Test status
Simulation time 1644735692 ps
CPU time 13.14 seconds
Started Aug 01 05:45:28 PM PDT 24
Finished Aug 01 05:45:41 PM PDT 24
Peak memory 216504 kb
Host smart-771a9994-6c80-43a6-bfbd-aec618c7901f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631771918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2631771918
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1854436995
Short name T120
Test name
Test status
Simulation time 474570361 ps
CPU time 80.77 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:46:46 PM PDT 24
Peak memory 213884 kb
Host smart-b01fe8de-6ffe-4733-ad10-d5f5ffd71c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854436995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1854436995
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3820677433
Short name T334
Test name
Test status
Simulation time 1675143641 ps
CPU time 8.31 seconds
Started Aug 01 05:45:44 PM PDT 24
Finished Aug 01 05:45:52 PM PDT 24
Peak memory 215472 kb
Host smart-8f220455-aa7c-4512-a5be-7a9c545ea2e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820677433 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3820677433
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2452922952
Short name T386
Test name
Test status
Simulation time 354009438 ps
CPU time 8.07 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:52 PM PDT 24
Peak memory 211232 kb
Host smart-0d9140d5-8e66-439d-9100-86b9eb6d2abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452922952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2452922952
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2233847230
Short name T99
Test name
Test status
Simulation time 272345414 ps
CPU time 13.65 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:57 PM PDT 24
Peak memory 212524 kb
Host smart-d88359c8-d1c6-4807-ab50-ffbac549f243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233847230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2233847230
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3701593654
Short name T336
Test name
Test status
Simulation time 989267614 ps
CPU time 18.99 seconds
Started Aug 01 05:45:48 PM PDT 24
Finished Aug 01 05:46:08 PM PDT 24
Peak memory 218884 kb
Host smart-41345b0c-f9f2-4253-8b6b-32aed2a9dbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701593654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3701593654
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1722924977
Short name T407
Test name
Test status
Simulation time 1218586287 ps
CPU time 153.19 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:48:17 PM PDT 24
Peak memory 214476 kb
Host smart-da95fa32-897e-41fb-8c90-f94f18549248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722924977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1722924977
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3376271167
Short name T352
Test name
Test status
Simulation time 1945407433 ps
CPU time 8.85 seconds
Started Aug 01 05:45:42 PM PDT 24
Finished Aug 01 05:45:51 PM PDT 24
Peak memory 216500 kb
Host smart-7f4a34c0-b4dd-40fe-b13f-849f0bf6b2c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376271167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3376271167
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3874772693
Short name T379
Test name
Test status
Simulation time 167556414 ps
CPU time 8.28 seconds
Started Aug 01 05:45:44 PM PDT 24
Finished Aug 01 05:45:53 PM PDT 24
Peak memory 210848 kb
Host smart-d4bd70c2-2d26-434c-8622-b77fce586d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874772693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3874772693
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1897670076
Short name T95
Test name
Test status
Simulation time 174701787 ps
CPU time 8.3 seconds
Started Aug 01 05:45:44 PM PDT 24
Finished Aug 01 05:45:52 PM PDT 24
Peak memory 211396 kb
Host smart-5452a962-1376-4c12-bcfa-dd2f5d23b4fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897670076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1897670076
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.778081668
Short name T331
Test name
Test status
Simulation time 1034743236 ps
CPU time 14.89 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:46:00 PM PDT 24
Peak memory 217908 kb
Host smart-deadbca4-b612-451b-9088-3662d2d988fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778081668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.778081668
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1188787033
Short name T117
Test name
Test status
Simulation time 250377846 ps
CPU time 81.63 seconds
Started Aug 01 05:45:47 PM PDT 24
Finished Aug 01 05:47:09 PM PDT 24
Peak memory 213748 kb
Host smart-7bca6998-98ea-4278-bf09-0c0cea7f0d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188787033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1188787033
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2008061470
Short name T347
Test name
Test status
Simulation time 185693034 ps
CPU time 8.61 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:45:53 PM PDT 24
Peak memory 216152 kb
Host smart-6b7ec342-3214-404a-bef6-1ab09e87f77e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008061470 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2008061470
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1231453739
Short name T403
Test name
Test status
Simulation time 259753665 ps
CPU time 9.76 seconds
Started Aug 01 05:45:41 PM PDT 24
Finished Aug 01 05:45:51 PM PDT 24
Peak memory 211056 kb
Host smart-de2d0be3-6614-4d37-978a-7b24d33f61ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231453739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1231453739
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2994766586
Short name T387
Test name
Test status
Simulation time 1272235191 ps
CPU time 8.26 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:52 PM PDT 24
Peak memory 211060 kb
Host smart-6c3d2645-cc22-488f-9210-5f20862b0940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994766586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2994766586
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4062414094
Short name T324
Test name
Test status
Simulation time 4954736587 ps
CPU time 13.33 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:45:59 PM PDT 24
Peak memory 217908 kb
Host smart-25159034-d70e-4f61-900a-34e22bb15a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062414094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4062414094
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3945413542
Short name T367
Test name
Test status
Simulation time 1022402600 ps
CPU time 10.73 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:45:56 PM PDT 24
Peak memory 217160 kb
Host smart-692c5f2c-dcf5-4664-ae85-b721360fbd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945413542 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3945413542
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3114684475
Short name T84
Test name
Test status
Simulation time 487184001 ps
CPU time 9.67 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:53 PM PDT 24
Peak memory 210768 kb
Host smart-030b8c7a-bcaa-4abb-8ae6-150872a211d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114684475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3114684475
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2256955734
Short name T82
Test name
Test status
Simulation time 1375698550 ps
CPU time 9.77 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:45:55 PM PDT 24
Peak memory 211552 kb
Host smart-9c8c11b1-b569-4677-a3ec-9f110478e9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256955734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2256955734
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2619090340
Short name T349
Test name
Test status
Simulation time 280898793 ps
CPU time 12.94 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:56 PM PDT 24
Peak memory 219168 kb
Host smart-f3f52e05-0a39-4190-888d-65eff413acb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619090340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2619090340
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3166532654
Short name T400
Test name
Test status
Simulation time 1573426705 ps
CPU time 155.74 seconds
Started Aug 01 05:45:47 PM PDT 24
Finished Aug 01 05:48:23 PM PDT 24
Peak memory 213320 kb
Host smart-535f24aa-c9d7-4b24-9115-760b14788d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166532654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3166532654
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1797732097
Short name T401
Test name
Test status
Simulation time 278429460 ps
CPU time 10.99 seconds
Started Aug 01 05:45:45 PM PDT 24
Finished Aug 01 05:45:57 PM PDT 24
Peak memory 218052 kb
Host smart-36d735b0-a060-4678-97a6-126d225f827a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797732097 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1797732097
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1091004327
Short name T79
Test name
Test status
Simulation time 168023478 ps
CPU time 8.31 seconds
Started Aug 01 05:45:46 PM PDT 24
Finished Aug 01 05:45:55 PM PDT 24
Peak memory 210836 kb
Host smart-d2065c58-bfed-4878-b09d-37c0d0566fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091004327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1091004327
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3509260692
Short name T75
Test name
Test status
Simulation time 1836312746 ps
CPU time 8.34 seconds
Started Aug 01 05:45:46 PM PDT 24
Finished Aug 01 05:45:54 PM PDT 24
Peak memory 211660 kb
Host smart-4b9a53ed-03ca-4f35-a080-b3c1fc7435a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509260692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3509260692
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.207730060
Short name T385
Test name
Test status
Simulation time 620202730 ps
CPU time 13.07 seconds
Started Aug 01 05:45:43 PM PDT 24
Finished Aug 01 05:45:56 PM PDT 24
Peak memory 219156 kb
Host smart-cda97c06-b12a-417a-b61f-7ef829fc17e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207730060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.207730060
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3989019100
Short name T406
Test name
Test status
Simulation time 826801538 ps
CPU time 8.17 seconds
Started Aug 01 05:45:04 PM PDT 24
Finished Aug 01 05:45:12 PM PDT 24
Peak memory 210956 kb
Host smart-bce14aca-e4c4-475d-8f5e-4dc042386410
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989019100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3989019100
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2244976382
Short name T369
Test name
Test status
Simulation time 661146423 ps
CPU time 8.63 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 211120 kb
Host smart-134ea534-9e9d-45a3-a13f-dd217e191e94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244976382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2244976382
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2835815715
Short name T389
Test name
Test status
Simulation time 350709741 ps
CPU time 15 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:16 PM PDT 24
Peak memory 212148 kb
Host smart-732a9c2f-f2ff-4ed9-bd71-49253336aef3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835815715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2835815715
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2953779102
Short name T364
Test name
Test status
Simulation time 1208063357 ps
CPU time 8.53 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 216840 kb
Host smart-76794bce-ccaf-4306-973c-cae6e309e090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953779102 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2953779102
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2203746452
Short name T391
Test name
Test status
Simulation time 249261520 ps
CPU time 9.82 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:11 PM PDT 24
Peak memory 211028 kb
Host smart-7f7868c0-9651-45d9-8989-27819d56e735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203746452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2203746452
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2781913983
Short name T328
Test name
Test status
Simulation time 1098439048 ps
CPU time 8.13 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:09 PM PDT 24
Peak memory 210760 kb
Host smart-a5527700-88e3-4e96-ba6c-4b1ce4487b17
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781913983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2781913983
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1989254325
Short name T381
Test name
Test status
Simulation time 1032416563 ps
CPU time 9.69 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:11 PM PDT 24
Peak memory 210788 kb
Host smart-762c8fc1-5774-4bdb-ad9d-beed33294164
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989254325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1989254325
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3267825618
Short name T98
Test name
Test status
Simulation time 167685518 ps
CPU time 8.53 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 211808 kb
Host smart-b0e6c885-2a10-458a-82da-f0ebd42f4a73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267825618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3267825618
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.141225516
Short name T371
Test name
Test status
Simulation time 260969356 ps
CPU time 15.37 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:17 PM PDT 24
Peak memory 217836 kb
Host smart-f2e5884d-99e1-439e-8343-4a844822cdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141225516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.141225516
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3525797222
Short name T62
Test name
Test status
Simulation time 1293068144 ps
CPU time 155.04 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:47:37 PM PDT 24
Peak memory 214424 kb
Host smart-bd5f935f-bb5e-4ccb-937f-a5ebe0cb94d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525797222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3525797222
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2161762019
Short name T377
Test name
Test status
Simulation time 720237246 ps
CPU time 8.27 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210964 kb
Host smart-8a91026c-aef3-4211-95f7-0164d2e486bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161762019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2161762019
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3136584293
Short name T102
Test name
Test status
Simulation time 169103726 ps
CPU time 8.61 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210816 kb
Host smart-0611e7b5-1514-4975-812a-c69b0ccfbaf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136584293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3136584293
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2602728583
Short name T353
Test name
Test status
Simulation time 1048714831 ps
CPU time 17.22 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:19 PM PDT 24
Peak memory 212200 kb
Host smart-7209988c-9c0a-475c-b60d-210c28cbdd3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602728583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2602728583
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2296133588
Short name T362
Test name
Test status
Simulation time 1988655152 ps
CPU time 9.54 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:24 PM PDT 24
Peak memory 218008 kb
Host smart-a99327f8-d212-4b7c-9a0f-31f978ff47ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296133588 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2296133588
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2686252098
Short name T368
Test name
Test status
Simulation time 167571188 ps
CPU time 8.11 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210848 kb
Host smart-970610b5-d5c1-45e1-bc1c-9feb1fdf3ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686252098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2686252098
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2714062246
Short name T337
Test name
Test status
Simulation time 174227721 ps
CPU time 8.22 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:10 PM PDT 24
Peak memory 210728 kb
Host smart-2c118f77-6841-466f-93e1-80331fdece7c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714062246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2714062246
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2638921460
Short name T390
Test name
Test status
Simulation time 315642519 ps
CPU time 9.8 seconds
Started Aug 01 05:45:03 PM PDT 24
Finished Aug 01 05:45:13 PM PDT 24
Peak memory 210788 kb
Host smart-e0e6dd25-87db-4669-a37c-617c5e63e6ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638921460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2638921460
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3357389843
Short name T101
Test name
Test status
Simulation time 700977516 ps
CPU time 37.35 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:39 PM PDT 24
Peak memory 214176 kb
Host smart-c74cf0fb-bc88-4fd2-a097-23e15770fa5c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357389843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3357389843
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.53728776
Short name T67
Test name
Test status
Simulation time 3083618355 ps
CPU time 9.89 seconds
Started Aug 01 05:45:02 PM PDT 24
Finished Aug 01 05:45:12 PM PDT 24
Peak memory 211216 kb
Host smart-02cd544d-bb11-4444-ba5d-bd77254350b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53728776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_same_csr_outstanding.53728776
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1584379276
Short name T326
Test name
Test status
Simulation time 249744220 ps
CPU time 13.26 seconds
Started Aug 01 05:45:01 PM PDT 24
Finished Aug 01 05:45:14 PM PDT 24
Peak memory 219172 kb
Host smart-c56b5a99-a795-4cbc-91e1-90c8869b7f43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584379276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1584379276
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3746587519
Short name T346
Test name
Test status
Simulation time 638345231 ps
CPU time 9.86 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:24 PM PDT 24
Peak memory 210684 kb
Host smart-edf910aa-73de-4c95-93a4-59e92e142e33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746587519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3746587519
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4075861512
Short name T399
Test name
Test status
Simulation time 249631641 ps
CPU time 10.04 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 210848 kb
Host smart-a95da64b-97b4-4919-9af4-ed7fc98c0e23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075861512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4075861512
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3090847108
Short name T92
Test name
Test status
Simulation time 379907503 ps
CPU time 15.41 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:30 PM PDT 24
Peak memory 212144 kb
Host smart-a617fb45-e38e-4f92-b593-fc3e0b9270f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090847108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3090847108
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2790681951
Short name T330
Test name
Test status
Simulation time 1226207530 ps
CPU time 8.58 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 214584 kb
Host smart-ac7f8bc1-b4ea-485a-b448-bd2a0b1a7d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790681951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2790681951
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3810414699
Short name T323
Test name
Test status
Simulation time 988235242 ps
CPU time 9.57 seconds
Started Aug 01 05:45:11 PM PDT 24
Finished Aug 01 05:45:21 PM PDT 24
Peak memory 210768 kb
Host smart-55e3055b-6ab5-44ad-8bc4-628352127598
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810414699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3810414699
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3132919692
Short name T342
Test name
Test status
Simulation time 260656465 ps
CPU time 9.86 seconds
Started Aug 01 05:45:11 PM PDT 24
Finished Aug 01 05:45:21 PM PDT 24
Peak memory 210780 kb
Host smart-37c70bde-c605-4d07-896e-5287662f4f15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132919692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3132919692
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2782737926
Short name T76
Test name
Test status
Simulation time 989748859 ps
CPU time 9.78 seconds
Started Aug 01 05:45:16 PM PDT 24
Finished Aug 01 05:45:25 PM PDT 24
Peak memory 211704 kb
Host smart-df0d32fb-3c88-4913-a442-2f2dda339f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782737926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2782737926
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1826189063
Short name T382
Test name
Test status
Simulation time 517804346 ps
CPU time 16.04 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:29 PM PDT 24
Peak memory 219180 kb
Host smart-609778c9-a235-48b8-9338-2b5d4e2c72da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826189063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1826189063
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3461846287
Short name T373
Test name
Test status
Simulation time 799429849 ps
CPU time 158.35 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:47:52 PM PDT 24
Peak memory 214228 kb
Host smart-61dcc3f7-e7ff-4efb-a07e-068122c63383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461846287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3461846287
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.114332007
Short name T338
Test name
Test status
Simulation time 265952966 ps
CPU time 10.41 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 216684 kb
Host smart-f58fd0fb-d715-47fc-b742-9ec10926fc7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114332007 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.114332007
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3480852499
Short name T343
Test name
Test status
Simulation time 496019999 ps
CPU time 9.93 seconds
Started Aug 01 05:45:12 PM PDT 24
Finished Aug 01 05:45:22 PM PDT 24
Peak memory 210948 kb
Host smart-992a7e7d-0d30-4b51-8adb-51d2e26438b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480852499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3480852499
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3576792905
Short name T358
Test name
Test status
Simulation time 167874879 ps
CPU time 8.22 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:22 PM PDT 24
Peak memory 211740 kb
Host smart-1e7c9793-0e96-4bdd-8223-f14ef8b23410
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576792905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3576792905
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4126204713
Short name T322
Test name
Test status
Simulation time 1035325497 ps
CPU time 13.23 seconds
Started Aug 01 05:45:12 PM PDT 24
Finished Aug 01 05:45:25 PM PDT 24
Peak memory 219160 kb
Host smart-b6799878-7757-40b1-a33b-2da44628ee9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126204713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4126204713
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2496374070
Short name T402
Test name
Test status
Simulation time 219356929 ps
CPU time 8.89 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 215948 kb
Host smart-d6edad83-5cca-45e4-b4db-d666d96c308f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496374070 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2496374070
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2212890963
Short name T81
Test name
Test status
Simulation time 261517912 ps
CPU time 9.67 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:24 PM PDT 24
Peak memory 210972 kb
Host smart-f65868df-6431-4f86-afaa-f34a97d1cdb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212890963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2212890963
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3636575235
Short name T97
Test name
Test status
Simulation time 6572148747 ps
CPU time 14.57 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:28 PM PDT 24
Peak memory 211828 kb
Host smart-78e5c058-1ff7-4a64-bd48-428d8155f5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636575235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3636575235
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1162524418
Short name T363
Test name
Test status
Simulation time 254888570 ps
CPU time 12.96 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:27 PM PDT 24
Peak memory 219016 kb
Host smart-47862a2b-d54b-4503-b102-135034c15752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162524418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1162524418
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2047112198
Short name T114
Test name
Test status
Simulation time 339525732 ps
CPU time 80.93 seconds
Started Aug 01 05:45:12 PM PDT 24
Finished Aug 01 05:46:33 PM PDT 24
Peak memory 213324 kb
Host smart-5cf0df45-0ba0-4c9d-8cef-6e6775d7edd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047112198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2047112198
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1692472175
Short name T341
Test name
Test status
Simulation time 1096590185 ps
CPU time 10.9 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:26 PM PDT 24
Peak memory 217148 kb
Host smart-5452ac47-0978-487a-92b0-cadbb9da446a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692472175 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1692472175
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3871465285
Short name T93
Test name
Test status
Simulation time 690958678 ps
CPU time 8.29 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:23 PM PDT 24
Peak memory 211120 kb
Host smart-1a38831d-05e9-4096-8636-42a75ec35827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871465285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3871465285
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3773871344
Short name T378
Test name
Test status
Simulation time 687772300 ps
CPU time 8.04 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:45:21 PM PDT 24
Peak memory 211564 kb
Host smart-98a600f6-1437-43a5-a1eb-9d39ed7fc027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773871344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3773871344
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1764911451
Short name T355
Test name
Test status
Simulation time 507072515 ps
CPU time 12.79 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:28 PM PDT 24
Peak memory 218536 kb
Host smart-61353b78-b6b4-43d8-bc65-528fd3975a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764911451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1764911451
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3005308164
Short name T119
Test name
Test status
Simulation time 1524573855 ps
CPU time 152.73 seconds
Started Aug 01 05:45:13 PM PDT 24
Finished Aug 01 05:47:46 PM PDT 24
Peak memory 214224 kb
Host smart-d2726efa-a8ce-482b-affe-df094b0d5b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005308164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3005308164
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.887710446
Short name T396
Test name
Test status
Simulation time 520584825 ps
CPU time 11.24 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:25 PM PDT 24
Peak memory 218100 kb
Host smart-09e4c426-d668-4504-a95c-bff361d0f9c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887710446 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.887710446
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.280037267
Short name T361
Test name
Test status
Simulation time 1653119827 ps
CPU time 10.02 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:24 PM PDT 24
Peak memory 211256 kb
Host smart-b93602c4-6964-4790-addb-b63d603fc463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280037267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.280037267
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1572417165
Short name T359
Test name
Test status
Simulation time 255188137 ps
CPU time 13.46 seconds
Started Aug 01 05:45:14 PM PDT 24
Finished Aug 01 05:45:27 PM PDT 24
Peak memory 212736 kb
Host smart-9ceb0c35-753b-4ab8-88be-bbce1bdf1e10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572417165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1572417165
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2648832167
Short name T327
Test name
Test status
Simulation time 249825010 ps
CPU time 14.08 seconds
Started Aug 01 05:45:15 PM PDT 24
Finished Aug 01 05:45:29 PM PDT 24
Peak memory 217640 kb
Host smart-f2d3df62-0adb-47a7-919f-66144135aea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648832167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2648832167
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2340300873
Short name T113
Test name
Test status
Simulation time 4984180814 ps
CPU time 81.57 seconds
Started Aug 01 05:45:12 PM PDT 24
Finished Aug 01 05:46:34 PM PDT 24
Peak memory 214360 kb
Host smart-3fd58d3a-9637-4a7f-ab40-05637a4f8b84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340300873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2340300873
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.490876477
Short name T65
Test name
Test status
Simulation time 696881892 ps
CPU time 8.39 seconds
Started Aug 01 05:45:27 PM PDT 24
Finished Aug 01 05:45:36 PM PDT 24
Peak memory 214496 kb
Host smart-5a02cfaa-3dd1-42df-8e03-93c1c57a7c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490876477 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.490876477
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4205632709
Short name T83
Test name
Test status
Simulation time 167402574 ps
CPU time 7.94 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:45:35 PM PDT 24
Peak memory 211040 kb
Host smart-deb3f547-5ee2-4e4d-bd86-d09c2ff11e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205632709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4205632709
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3820578532
Short name T345
Test name
Test status
Simulation time 268948000 ps
CPU time 14.14 seconds
Started Aug 01 05:45:25 PM PDT 24
Finished Aug 01 05:45:39 PM PDT 24
Peak memory 212648 kb
Host smart-5c2b0e9d-cff7-4b9c-9637-d5a16198cdbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820578532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3820578532
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1813589805
Short name T350
Test name
Test status
Simulation time 661413442 ps
CPU time 13.79 seconds
Started Aug 01 05:45:30 PM PDT 24
Finished Aug 01 05:45:44 PM PDT 24
Peak memory 219140 kb
Host smart-e282c308-a085-4c28-95ff-a7b5cdf4a6d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813589805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1813589805
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4134490066
Short name T116
Test name
Test status
Simulation time 8804526150 ps
CPU time 157.61 seconds
Started Aug 01 05:45:26 PM PDT 24
Finished Aug 01 05:48:04 PM PDT 24
Peak memory 213572 kb
Host smart-bc0c90ed-132e-4cc2-85f2-91f9d8ef191a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134490066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4134490066
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.504238133
Short name T190
Test name
Test status
Simulation time 1029641891 ps
CPU time 9.75 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 218984 kb
Host smart-48422158-9482-4dd1-b336-9d24b9757bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504238133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.504238133
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3090329324
Short name T262
Test name
Test status
Simulation time 7103258033 ps
CPU time 222.84 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:26:27 PM PDT 24
Peak memory 239568 kb
Host smart-6cfef2d2-30d3-42e7-b780-b13c05325172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090329324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3090329324
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.265139923
Short name T36
Test name
Test status
Simulation time 2069818987 ps
CPU time 19.75 seconds
Started Aug 01 05:22:42 PM PDT 24
Finished Aug 01 05:23:02 PM PDT 24
Peak memory 219980 kb
Host smart-93f5042a-19fd-4c68-894d-2d84bd834081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265139923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.265139923
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1749124658
Short name T187
Test name
Test status
Simulation time 373695224 ps
CPU time 9.95 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:22:55 PM PDT 24
Peak memory 220072 kb
Host smart-e78a82f4-315f-4ba8-83ef-acddca8a87ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749124658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1749124658
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.809701000
Short name T23
Test name
Test status
Simulation time 419811841 ps
CPU time 226.52 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 239384 kb
Host smart-fd03d252-3183-4ce4-8310-3314ee8f663b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809701000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.809701000
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2493086017
Short name T224
Test name
Test status
Simulation time 1362822031 ps
CPU time 12.1 seconds
Started Aug 01 05:22:35 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 219988 kb
Host smart-beb5f563-62cb-4afe-b09f-30efc364cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493086017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2493086017
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.168046356
Short name T85
Test name
Test status
Simulation time 1770329711 ps
CPU time 15.4 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:05 PM PDT 24
Peak memory 219916 kb
Host smart-6b3c6fb4-71e3-4102-84b8-682b1f2ab45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168046356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.168046356
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.270039990
Short name T54
Test name
Test status
Simulation time 38508218299 ps
CPU time 733.28 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:34:53 PM PDT 24
Peak memory 235824 kb
Host smart-97a65b1e-9afe-4c8c-b3ee-d95c498710b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270039990 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.270039990
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4202486036
Short name T74
Test name
Test status
Simulation time 495586246 ps
CPU time 9.58 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 219148 kb
Host smart-4f15dfaa-f6eb-4f9f-84e3-5859b23cc294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202486036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4202486036
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4262106177
Short name T41
Test name
Test status
Simulation time 49351162472 ps
CPU time 262.72 seconds
Started Aug 01 05:22:39 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 240484 kb
Host smart-7f366f26-90d9-492c-a4cb-88a0a6a12687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262106177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4262106177
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1425132934
Short name T153
Test name
Test status
Simulation time 513091179 ps
CPU time 22.77 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:23:00 PM PDT 24
Peak memory 219984 kb
Host smart-496517a5-b3ec-4729-9586-1bdb095b4d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425132934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1425132934
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3083595237
Short name T21
Test name
Test status
Simulation time 504462724 ps
CPU time 12.35 seconds
Started Aug 01 05:22:43 PM PDT 24
Finished Aug 01 05:22:55 PM PDT 24
Peak memory 219980 kb
Host smart-d249aaef-df20-48d6-a7d2-257756016b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083595237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3083595237
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3735786954
Short name T125
Test name
Test status
Simulation time 182378374 ps
CPU time 10.38 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:22:55 PM PDT 24
Peak memory 219904 kb
Host smart-46c10942-1048-49fc-9442-29d7f851efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735786954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3735786954
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2297749357
Short name T37
Test name
Test status
Simulation time 554266238 ps
CPU time 23.9 seconds
Started Aug 01 05:22:43 PM PDT 24
Finished Aug 01 05:23:07 PM PDT 24
Peak memory 219820 kb
Host smart-af8a4edc-a34e-4b67-8d80-eafa693ca4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297749357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2297749357
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3943063067
Short name T234
Test name
Test status
Simulation time 2012562552 ps
CPU time 14.7 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:23:12 PM PDT 24
Peak memory 218724 kb
Host smart-7dad9349-c578-4a72-8191-e5d4a614a58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943063067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3943063067
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3078420630
Short name T182
Test name
Test status
Simulation time 16346227676 ps
CPU time 265.15 seconds
Started Aug 01 05:23:00 PM PDT 24
Finished Aug 01 05:27:25 PM PDT 24
Peak memory 234604 kb
Host smart-f70bb136-950f-4637-a202-b3f05105e015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078420630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3078420630
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1709949290
Short name T202
Test name
Test status
Simulation time 870050644 ps
CPU time 22.74 seconds
Started Aug 01 05:22:58 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 220056 kb
Host smart-c0a81315-c379-457a-978e-ec5c9fdfab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709949290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1709949290
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1939497689
Short name T38
Test name
Test status
Simulation time 271937116 ps
CPU time 12.02 seconds
Started Aug 01 05:23:05 PM PDT 24
Finished Aug 01 05:23:17 PM PDT 24
Peak memory 219940 kb
Host smart-e409bdc2-84a2-48bf-84d0-1439c56abaeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939497689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1939497689
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2989587215
Short name T185
Test name
Test status
Simulation time 913322618 ps
CPU time 26.29 seconds
Started Aug 01 05:22:58 PM PDT 24
Finished Aug 01 05:23:24 PM PDT 24
Peak memory 220004 kb
Host smart-e3453e04-bee9-42b8-843a-1c961fd60ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989587215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2989587215
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.37308191
Short name T272
Test name
Test status
Simulation time 553243251 ps
CPU time 9.83 seconds
Started Aug 01 05:22:56 PM PDT 24
Finished Aug 01 05:23:06 PM PDT 24
Peak memory 219772 kb
Host smart-2fed7d36-1fc8-4047-8192-29a33ed9e701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37308191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.37308191
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1284588320
Short name T44
Test name
Test status
Simulation time 6977253404 ps
CPU time 179.9 seconds
Started Aug 01 05:23:04 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 219820 kb
Host smart-254dbeaf-7f71-41e3-a428-08b040094f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284588320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1284588320
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.195212935
Short name T155
Test name
Test status
Simulation time 1982954132 ps
CPU time 21.56 seconds
Started Aug 01 05:23:01 PM PDT 24
Finished Aug 01 05:23:22 PM PDT 24
Peak memory 219956 kb
Host smart-035098e3-5385-4f73-a099-fbb282d57f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195212935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.195212935
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.456695202
Short name T221
Test name
Test status
Simulation time 674778074 ps
CPU time 10.16 seconds
Started Aug 01 05:23:04 PM PDT 24
Finished Aug 01 05:23:14 PM PDT 24
Peak memory 219916 kb
Host smart-b7c9d04a-c272-4efa-aa2c-9b1b6ad4339d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456695202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.456695202
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1602804782
Short name T145
Test name
Test status
Simulation time 1553642516 ps
CPU time 35.2 seconds
Started Aug 01 05:22:55 PM PDT 24
Finished Aug 01 05:23:31 PM PDT 24
Peak memory 219916 kb
Host smart-849ded39-e7db-42e4-addb-7503b237cd89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602804782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1602804782
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1888514807
Short name T237
Test name
Test status
Simulation time 27741103110 ps
CPU time 4503.74 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 06:38:02 PM PDT 24
Peak memory 236536 kb
Host smart-958de6ec-65d3-470b-9d32-2f71286b669a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888514807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1888514807
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2146855769
Short name T5
Test name
Test status
Simulation time 167812302 ps
CPU time 7.8 seconds
Started Aug 01 05:23:00 PM PDT 24
Finished Aug 01 05:23:08 PM PDT 24
Peak memory 219004 kb
Host smart-bb056493-c6cb-410e-9931-8092ac97c4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146855769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2146855769
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2340265508
Short name T287
Test name
Test status
Simulation time 8099388911 ps
CPU time 112.68 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 220268 kb
Host smart-0294af53-4968-488d-aff4-36e75de3baa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340265508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2340265508
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1992548740
Short name T294
Test name
Test status
Simulation time 1971762794 ps
CPU time 23.12 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:23:20 PM PDT 24
Peak memory 219976 kb
Host smart-174aabda-e4f7-4c88-8749-f2e5a3413c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992548740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1992548740
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.957620171
Short name T154
Test name
Test status
Simulation time 268909430 ps
CPU time 11.69 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:23:09 PM PDT 24
Peak memory 220104 kb
Host smart-0871ea1b-1ec4-4406-a4ca-3d6cd69266c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957620171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.957620171
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1110167021
Short name T288
Test name
Test status
Simulation time 1487155650 ps
CPU time 20.97 seconds
Started Aug 01 05:22:59 PM PDT 24
Finished Aug 01 05:23:20 PM PDT 24
Peak memory 220044 kb
Host smart-1af547ea-5f04-4017-83b8-c7c4df32c292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110167021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1110167021
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.69012368
Short name T204
Test name
Test status
Simulation time 4473273195 ps
CPU time 15.06 seconds
Started Aug 01 05:23:04 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 219008 kb
Host smart-811988cc-120c-43f1-b735-c8d1517756da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69012368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.69012368
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2912867487
Short name T172
Test name
Test status
Simulation time 24802517843 ps
CPU time 344.01 seconds
Started Aug 01 05:22:56 PM PDT 24
Finished Aug 01 05:28:40 PM PDT 24
Peak memory 231252 kb
Host smart-6689ded6-2411-417a-8cd1-eab4d90d5d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912867487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2912867487
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1010049270
Short name T208
Test name
Test status
Simulation time 1576769231 ps
CPU time 19.28 seconds
Started Aug 01 05:22:58 PM PDT 24
Finished Aug 01 05:23:17 PM PDT 24
Peak memory 220044 kb
Host smart-4dfcfb05-e6db-4ca0-a42c-3be2001c909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010049270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1010049270
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3434279092
Short name T265
Test name
Test status
Simulation time 258912939 ps
CPU time 11.41 seconds
Started Aug 01 05:23:00 PM PDT 24
Finished Aug 01 05:23:12 PM PDT 24
Peak memory 219952 kb
Host smart-a4240d30-5245-468c-8e3c-f52b80f3af58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434279092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3434279092
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1448866814
Short name T196
Test name
Test status
Simulation time 365751833 ps
CPU time 20.09 seconds
Started Aug 01 05:23:03 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 219844 kb
Host smart-5262c73b-2eb7-4082-9849-297006a24e70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448866814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1448866814
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.868102365
Short name T282
Test name
Test status
Simulation time 957530310 ps
CPU time 9.78 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 218920 kb
Host smart-2de50f42-4e50-4f85-a182-42e67a9379e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868102365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.868102365
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1366028023
Short name T306
Test name
Test status
Simulation time 21994167286 ps
CPU time 185.07 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:26:02 PM PDT 24
Peak memory 220184 kb
Host smart-2e63b908-502a-4723-90f1-d02f31c2af8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366028023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1366028023
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.843539096
Short name T233
Test name
Test status
Simulation time 273679597 ps
CPU time 13.08 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:23:10 PM PDT 24
Peak memory 219968 kb
Host smart-73cf4f5e-9496-4734-88c1-c35ddb19df29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843539096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.843539096
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1822135254
Short name T256
Test name
Test status
Simulation time 550253906 ps
CPU time 29.22 seconds
Started Aug 01 05:23:03 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219868 kb
Host smart-667f3cc0-209a-4fa4-9161-7f19ad15f6a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822135254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1822135254
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3825912664
Short name T18
Test name
Test status
Simulation time 90041430517 ps
CPU time 8021.87 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 07:36:53 PM PDT 24
Peak memory 236608 kb
Host smart-d52dc048-8faf-455a-b5f1-3edbe32a634f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825912664 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3825912664
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3457342936
Short name T235
Test name
Test status
Simulation time 988396808 ps
CPU time 9.89 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 218976 kb
Host smart-97260afc-3649-4504-a06a-83f72d357d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457342936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3457342936
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1394876702
Short name T39
Test name
Test status
Simulation time 10900681881 ps
CPU time 226.18 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:26:55 PM PDT 24
Peak memory 238580 kb
Host smart-7202a736-8399-4c89-9884-caab332353ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394876702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1394876702
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1492997160
Short name T310
Test name
Test status
Simulation time 1975508229 ps
CPU time 22.73 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:34 PM PDT 24
Peak memory 220004 kb
Host smart-2747ae71-45f9-4c43-b050-e6af1434f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492997160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1492997160
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2809470393
Short name T226
Test name
Test status
Simulation time 275489187 ps
CPU time 12.15 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 220084 kb
Host smart-cfaafbae-07f9-4a02-8c30-3bb8f50a54ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809470393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2809470393
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3417458916
Short name T205
Test name
Test status
Simulation time 290531912 ps
CPU time 15.95 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:26 PM PDT 24
Peak memory 219920 kb
Host smart-75208bb1-7a43-479b-9ee0-2112773ef441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417458916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3417458916
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3674831531
Short name T152
Test name
Test status
Simulation time 992398994 ps
CPU time 10.05 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 219088 kb
Host smart-802aecad-096d-4753-aad5-179454211ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674831531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3674831531
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.710947470
Short name T43
Test name
Test status
Simulation time 3899999945 ps
CPU time 277.15 seconds
Started Aug 01 05:23:08 PM PDT 24
Finished Aug 01 05:27:46 PM PDT 24
Peak memory 225716 kb
Host smart-9d4aeb13-75de-46f9-8bb3-5bb4a7bec90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710947470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.710947470
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1106361634
Short name T291
Test name
Test status
Simulation time 351044890 ps
CPU time 19.74 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:29 PM PDT 24
Peak memory 220068 kb
Host smart-4e07fe0f-4a06-4a4f-8702-8b6aeaba16b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106361634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1106361634
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3814562427
Short name T122
Test name
Test status
Simulation time 534585416 ps
CPU time 11.82 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 220000 kb
Host smart-7264c838-cf2b-437a-b376-229c79b06cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814562427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3814562427
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1596604772
Short name T35
Test name
Test status
Simulation time 20763523187 ps
CPU time 49.28 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:24:01 PM PDT 24
Peak memory 221680 kb
Host smart-f18eb1e4-8aa7-48ee-8bec-1dbf476831e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596604772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1596604772
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1183992378
Short name T49
Test name
Test status
Simulation time 30974843093 ps
CPU time 579.41 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:32:49 PM PDT 24
Peak memory 232112 kb
Host smart-89933e87-35d6-4bd8-8945-a5eb9e114951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183992378 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1183992378
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.651967599
Short name T276
Test name
Test status
Simulation time 26017167156 ps
CPU time 297.64 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 230248 kb
Host smart-982a9494-9ce5-403a-bd34-b496841d05f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651967599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.651967599
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3047754882
Short name T293
Test name
Test status
Simulation time 511566376 ps
CPU time 22.94 seconds
Started Aug 01 05:23:07 PM PDT 24
Finished Aug 01 05:23:30 PM PDT 24
Peak memory 220044 kb
Host smart-84a37f46-bc5b-4190-bf67-2bfb732aac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047754882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3047754882
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.496595038
Short name T181
Test name
Test status
Simulation time 702938627 ps
CPU time 10.68 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 219944 kb
Host smart-0b06c3eb-b069-4f0e-9c9c-81b758fdf5bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496595038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.496595038
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4141762855
Short name T254
Test name
Test status
Simulation time 250608820 ps
CPU time 10.34 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 218576 kb
Host smart-d2e2f9ae-6597-4c23-a391-a884174f596d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141762855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4141762855
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4055307895
Short name T175
Test name
Test status
Simulation time 7107563006 ps
CPU time 240.62 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:27:09 PM PDT 24
Peak memory 241500 kb
Host smart-e0dea501-61eb-43f0-b46b-d490af19dbca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055307895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4055307895
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2588184144
Short name T139
Test name
Test status
Simulation time 1834765998 ps
CPU time 22.61 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219960 kb
Host smart-8bfa8a6f-d417-40ab-9e7b-d7c708f1c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588184144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2588184144
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.888095521
Short name T135
Test name
Test status
Simulation time 1054284530 ps
CPU time 12.1 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 219964 kb
Host smart-301b85c5-156e-413d-8e30-dbfb9f28ad73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888095521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.888095521
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4136224406
Short name T198
Test name
Test status
Simulation time 12113728097 ps
CPU time 80.87 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 220052 kb
Host smart-4a74f22f-41af-4ab4-84ba-30353debf6f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136224406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4136224406
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1224355577
Short name T218
Test name
Test status
Simulation time 263178842 ps
CPU time 10.2 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:20 PM PDT 24
Peak memory 218992 kb
Host smart-ead5958c-431b-47bf-8a3f-ffbf7a564ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224355577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1224355577
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2214730123
Short name T267
Test name
Test status
Simulation time 8934924220 ps
CPU time 284.53 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 241084 kb
Host smart-b1d2e66e-ebe6-4366-9044-f513f84b7cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214730123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2214730123
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3500829377
Short name T138
Test name
Test status
Simulation time 497282135 ps
CPU time 22.98 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219988 kb
Host smart-a537f233-83bd-4da3-8ceb-e5c3979d67f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500829377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3500829377
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4079027985
Short name T170
Test name
Test status
Simulation time 549609860 ps
CPU time 11.91 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 220128 kb
Host smart-faa5135b-be06-42e6-a3c6-c914e0828741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079027985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4079027985
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1843596952
Short name T228
Test name
Test status
Simulation time 383269886 ps
CPU time 24.01 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:34 PM PDT 24
Peak memory 219972 kb
Host smart-adcea9c6-a682-4710-b839-a842caa8f433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843596952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1843596952
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3272000332
Short name T201
Test name
Test status
Simulation time 2245890804 ps
CPU time 9.86 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 219052 kb
Host smart-2c8d2e38-0bb7-4337-8b66-845fa24e3c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272000332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3272000332
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1973178850
Short name T239
Test name
Test status
Simulation time 5637235212 ps
CPU time 287.9 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 239760 kb
Host smart-d40f1e19-8a6c-4f70-b5d4-827be005c9c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973178850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1973178850
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.941712882
Short name T246
Test name
Test status
Simulation time 3808001842 ps
CPU time 22.97 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:23:03 PM PDT 24
Peak memory 220192 kb
Host smart-ce3e2e3c-8562-429a-88fa-6f17a041ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941712882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.941712882
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3148263682
Short name T162
Test name
Test status
Simulation time 273062026 ps
CPU time 12.11 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:22:56 PM PDT 24
Peak memory 220096 kb
Host smart-e30dd08b-4e29-4ce5-8892-438c0034105d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148263682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3148263682
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.579569310
Short name T28
Test name
Test status
Simulation time 1262534814 ps
CPU time 116.12 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 238960 kb
Host smart-796bdac5-ca7a-4dd4-a994-249abe5f5750
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579569310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.579569310
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1130279546
Short name T308
Test name
Test status
Simulation time 966016453 ps
CPU time 12.07 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:22:52 PM PDT 24
Peak memory 220044 kb
Host smart-75cfc42a-3080-4dcd-b2cd-2726192624c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130279546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1130279546
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2620318314
Short name T148
Test name
Test status
Simulation time 1322124997 ps
CPU time 27.59 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:23:05 PM PDT 24
Peak memory 219960 kb
Host smart-78ecb7f9-cb6e-412a-80c8-e7f2e99c7b2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620318314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2620318314
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.930921391
Short name T127
Test name
Test status
Simulation time 1506020657 ps
CPU time 8.36 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 219064 kb
Host smart-4a1375bf-481a-4c6f-8ea8-7cf7ffda143f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930921391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.930921391
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3554588093
Short name T225
Test name
Test status
Simulation time 25092686042 ps
CPU time 355.82 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:29:06 PM PDT 24
Peak memory 234272 kb
Host smart-ed9a5f30-73ea-4c17-9558-eaa58334fad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554588093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3554588093
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.741391260
Short name T33
Test name
Test status
Simulation time 1505636007 ps
CPU time 19.08 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:29 PM PDT 24
Peak memory 220084 kb
Host smart-e686dc7b-4d79-4c89-bb9a-b2fd40d5a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741391260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.741391260
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3029710315
Short name T280
Test name
Test status
Simulation time 939396092 ps
CPU time 11.7 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:22 PM PDT 24
Peak memory 219964 kb
Host smart-f6f4c3b1-4012-41a0-b4d8-84e35a7f88b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029710315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3029710315
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3062657105
Short name T3
Test name
Test status
Simulation time 806137360 ps
CPU time 38.93 seconds
Started Aug 01 05:23:08 PM PDT 24
Finished Aug 01 05:23:47 PM PDT 24
Peak memory 219888 kb
Host smart-d8f768f3-f6cb-4824-b389-3f26376de63a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062657105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3062657105
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2341233238
Short name T279
Test name
Test status
Simulation time 687633606 ps
CPU time 8.36 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:18 PM PDT 24
Peak memory 218948 kb
Host smart-a6b29249-8bac-49c0-81ab-846446c7735c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341233238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2341233238
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.747089509
Short name T273
Test name
Test status
Simulation time 2140672761 ps
CPU time 22.56 seconds
Started Aug 01 05:23:09 PM PDT 24
Finished Aug 01 05:23:31 PM PDT 24
Peak memory 219924 kb
Host smart-53198c75-9d26-4d39-bf28-3931c450899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747089509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.747089509
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.980954737
Short name T258
Test name
Test status
Simulation time 2075965839 ps
CPU time 16.78 seconds
Started Aug 01 05:23:08 PM PDT 24
Finished Aug 01 05:23:25 PM PDT 24
Peak memory 219988 kb
Host smart-ee186398-1abc-4c8b-b75b-60bf4e60f4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980954737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.980954737
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4247204890
Short name T88
Test name
Test status
Simulation time 337356342 ps
CPU time 16.45 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:26 PM PDT 24
Peak memory 219980 kb
Host smart-e352a759-d392-460b-a504-d0697b923e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247204890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4247204890
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1376717600
Short name T180
Test name
Test status
Simulation time 613576056 ps
CPU time 8.13 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 219056 kb
Host smart-478b6344-0c77-404a-9dc3-887b1f116a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376717600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1376717600
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3849228223
Short name T240
Test name
Test status
Simulation time 4009651922 ps
CPU time 212.43 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 218992 kb
Host smart-d285d427-8645-4f96-a6ed-5ca20e5b0c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849228223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3849228223
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1384463694
Short name T257
Test name
Test status
Simulation time 518472868 ps
CPU time 12.65 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 219964 kb
Host smart-0733318c-f304-438a-b1e7-588bfe41532d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384463694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1384463694
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2438603645
Short name T157
Test name
Test status
Simulation time 1163627047 ps
CPU time 12.86 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 219912 kb
Host smart-7125d3e3-23e2-438b-adc2-7cec7d85ec95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438603645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2438603645
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3831132542
Short name T207
Test name
Test status
Simulation time 171100103 ps
CPU time 8.34 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:29 PM PDT 24
Peak memory 218980 kb
Host smart-b132230f-bd5d-45e9-9910-87617423f5af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831132542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3831132542
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.696654584
Short name T289
Test name
Test status
Simulation time 4029079999 ps
CPU time 107.64 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:24:58 PM PDT 24
Peak memory 242152 kb
Host smart-d79932f1-1cca-40e4-8ef9-bf2242ca3159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696654584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.696654584
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2245211919
Short name T58
Test name
Test status
Simulation time 993982243 ps
CPU time 22.4 seconds
Started Aug 01 05:23:08 PM PDT 24
Finished Aug 01 05:23:30 PM PDT 24
Peak memory 220016 kb
Host smart-8b4d51e7-b294-41cf-9589-05bed6c7aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245211919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2245211919
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4045411507
Short name T57
Test name
Test status
Simulation time 966069177 ps
CPU time 10.33 seconds
Started Aug 01 05:23:11 PM PDT 24
Finished Aug 01 05:23:22 PM PDT 24
Peak memory 220004 kb
Host smart-a0eb9a3e-5a37-461e-9545-ce2f2af35ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045411507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4045411507
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2368771584
Short name T312
Test name
Test status
Simulation time 345691436 ps
CPU time 22.99 seconds
Started Aug 01 05:23:10 PM PDT 24
Finished Aug 01 05:23:34 PM PDT 24
Peak memory 219876 kb
Host smart-b443407a-8a06-46c1-a694-64f1eb5975fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368771584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2368771584
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2268250866
Short name T60
Test name
Test status
Simulation time 174401831 ps
CPU time 8.26 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:30 PM PDT 24
Peak memory 219104 kb
Host smart-a99caa30-a18a-4c1b-a9ff-344d7462ea23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268250866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2268250866
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1520655636
Short name T320
Test name
Test status
Simulation time 2669658706 ps
CPU time 128.59 seconds
Started Aug 01 05:23:19 PM PDT 24
Finished Aug 01 05:25:28 PM PDT 24
Peak memory 220400 kb
Host smart-fbc3bb8d-66d9-4663-a843-8234b53d631d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520655636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1520655636
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4010574645
Short name T34
Test name
Test status
Simulation time 516824991 ps
CPU time 22.5 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:23:48 PM PDT 24
Peak memory 219968 kb
Host smart-ad5132f5-9f1d-4aaf-afe8-c72a417479ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010574645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4010574645
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3815903038
Short name T285
Test name
Test status
Simulation time 278911339 ps
CPU time 12.03 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 219968 kb
Host smart-f826b0c8-63ca-4d7d-8706-23f3b9a16d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815903038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3815903038
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2708414832
Short name T89
Test name
Test status
Simulation time 1042899627 ps
CPU time 27.09 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:48 PM PDT 24
Peak memory 219868 kb
Host smart-e7e34a98-bfe0-48c3-b6d1-da0b9ab45193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708414832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2708414832
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.33713935
Short name T236
Test name
Test status
Simulation time 661773674 ps
CPU time 8.09 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219012 kb
Host smart-58a06578-e108-4952-8499-ffbdd84c4d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.33713935
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2474987114
Short name T216
Test name
Test status
Simulation time 11198957648 ps
CPU time 187.53 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:26:33 PM PDT 24
Peak memory 238488 kb
Host smart-3b181f85-c291-4a82-8cf7-f593d5ee960b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474987114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2474987114
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3651270542
Short name T214
Test name
Test status
Simulation time 4731250371 ps
CPU time 19.61 seconds
Started Aug 01 05:23:19 PM PDT 24
Finished Aug 01 05:23:38 PM PDT 24
Peak memory 220180 kb
Host smart-11ee62c0-4916-452f-b7e5-d70e572b4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651270542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3651270542
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1248080449
Short name T59
Test name
Test status
Simulation time 185143073 ps
CPU time 10.45 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 220040 kb
Host smart-74d7d70f-7096-4fc6-8e55-b9995402238d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248080449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1248080449
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2191584640
Short name T307
Test name
Test status
Simulation time 805954881 ps
CPU time 34.19 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 219896 kb
Host smart-2fed191e-5fc7-4c61-a5c8-4444693976a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191584640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2191584640
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3853870728
Short name T11
Test name
Test status
Simulation time 719516394 ps
CPU time 8.28 seconds
Started Aug 01 05:23:19 PM PDT 24
Finished Aug 01 05:23:28 PM PDT 24
Peak memory 219028 kb
Host smart-114f2744-82df-433e-8fd1-87993819bb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853870728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3853870728
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2948356383
Short name T211
Test name
Test status
Simulation time 8848298612 ps
CPU time 131.61 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:25:33 PM PDT 24
Peak memory 236456 kb
Host smart-16735ac8-0913-443d-9c7a-dabe090849a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948356383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2948356383
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1869003476
Short name T227
Test name
Test status
Simulation time 1320637230 ps
CPU time 19.21 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:41 PM PDT 24
Peak memory 219992 kb
Host smart-0aa954d9-a20b-442f-ba9a-6f3b5a68938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869003476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1869003476
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.826179721
Short name T283
Test name
Test status
Simulation time 181553539 ps
CPU time 10.23 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 219940 kb
Host smart-2b0d1912-3cea-43d1-9369-c38d393dad88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826179721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.826179721
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4221482031
Short name T156
Test name
Test status
Simulation time 221348244 ps
CPU time 11.08 seconds
Started Aug 01 05:23:19 PM PDT 24
Finished Aug 01 05:23:31 PM PDT 24
Peak memory 219948 kb
Host smart-a5fa02c2-ebb5-4779-94e8-cb173bca2278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221482031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4221482031
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1722841148
Short name T298
Test name
Test status
Simulation time 552111625 ps
CPU time 10.03 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:34 PM PDT 24
Peak memory 219148 kb
Host smart-5e0c19ef-eeec-450d-bd3f-609bbb514263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722841148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1722841148
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2841959195
Short name T42
Test name
Test status
Simulation time 4535212989 ps
CPU time 144.82 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:25:48 PM PDT 24
Peak memory 220284 kb
Host smart-e1b00b1e-e89d-4cde-bb33-badae4a41de9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841959195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2841959195
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3530559612
Short name T195
Test name
Test status
Simulation time 2146029141 ps
CPU time 22.6 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:46 PM PDT 24
Peak memory 219468 kb
Host smart-07bec48b-b600-41aa-b0d0-ee243b0d4b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530559612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3530559612
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4053802756
Short name T136
Test name
Test status
Simulation time 262944117 ps
CPU time 11.99 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 219944 kb
Host smart-a0a5f731-ee4f-469b-a52a-db3ef8c07d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053802756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4053802756
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4154911516
Short name T146
Test name
Test status
Simulation time 321730038 ps
CPU time 13.52 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:23:45 PM PDT 24
Peak memory 219776 kb
Host smart-bcdf19f6-08db-4c93-b85b-3eb98e629535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154911516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4154911516
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1274922214
Short name T142
Test name
Test status
Simulation time 1016906024 ps
CPU time 14.49 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:38 PM PDT 24
Peak memory 218924 kb
Host smart-4ba455ce-9e09-4802-ac63-aaea4cb66be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274922214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1274922214
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4057742833
Short name T277
Test name
Test status
Simulation time 10852774092 ps
CPU time 322.55 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:28:46 PM PDT 24
Peak memory 236996 kb
Host smart-b7019abc-d562-45fe-aae0-9dd18d424184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057742833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4057742833
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1524914139
Short name T47
Test name
Test status
Simulation time 5493398772 ps
CPU time 22.77 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 220188 kb
Host smart-f99b8d6a-f3b6-4859-8383-3a1ed55410a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524914139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1524914139
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2337607635
Short name T20
Test name
Test status
Simulation time 517801119 ps
CPU time 11.77 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219964 kb
Host smart-1f6c9289-2d25-4fda-9cb1-1030bdeaf421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337607635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2337607635
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1398335258
Short name T165
Test name
Test status
Simulation time 1539072591 ps
CPU time 38.45 seconds
Started Aug 01 05:23:20 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 219968 kb
Host smart-bb8a96d2-36bb-4b04-8cdb-d1720fa5d31e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398335258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1398335258
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3091808802
Short name T217
Test name
Test status
Simulation time 345374281 ps
CPU time 8.26 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:32 PM PDT 24
Peak memory 219148 kb
Host smart-8a06f553-5b4d-45fd-8456-a3a0fd21937b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091808802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3091808802
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4204135221
Short name T173
Test name
Test status
Simulation time 8576534483 ps
CPU time 137.79 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:25:42 PM PDT 24
Peak memory 228768 kb
Host smart-1aa10ac0-57fe-43aa-8637-0b04c8781eaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204135221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4204135221
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1413500132
Short name T46
Test name
Test status
Simulation time 1272380894 ps
CPU time 18.84 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:43 PM PDT 24
Peak memory 220016 kb
Host smart-4844d1ac-a438-46da-b4e9-9711609f5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413500132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1413500132
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.661005421
Short name T106
Test name
Test status
Simulation time 1940509447 ps
CPU time 10.29 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:32 PM PDT 24
Peak memory 220028 kb
Host smart-0ba8a22f-057d-4017-a00d-4304a6ba57ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661005421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.661005421
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.681964895
Short name T19
Test name
Test status
Simulation time 296235334 ps
CPU time 19.9 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 219924 kb
Host smart-19ba4e8d-12d0-4b4f-88db-ced224810f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681964895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.681964895
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2456667768
Short name T248
Test name
Test status
Simulation time 1375868739 ps
CPU time 8.44 seconds
Started Aug 01 05:22:50 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 218960 kb
Host smart-05929154-55b1-42e6-bf3d-9af9b04df638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456667768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2456667768
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.996436809
Short name T222
Test name
Test status
Simulation time 9748417014 ps
CPU time 242.66 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:26:51 PM PDT 24
Peak memory 225004 kb
Host smart-49793eb1-cef7-4fbc-aa1b-0da69e3c7ed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996436809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.996436809
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.230107609
Short name T297
Test name
Test status
Simulation time 528897956 ps
CPU time 22.11 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:23:08 PM PDT 24
Peak memory 220036 kb
Host smart-972292dd-872a-4fed-a6d5-2d0a72e457fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230107609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.230107609
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1260724638
Short name T134
Test name
Test status
Simulation time 272360185 ps
CPU time 11.71 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 219940 kb
Host smart-ba181635-17af-40dc-8180-251fcfdbf7ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260724638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1260724638
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2847182780
Short name T29
Test name
Test status
Simulation time 2290609485 ps
CPU time 224.68 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:26:30 PM PDT 24
Peak memory 238780 kb
Host smart-23ba0a80-7884-4468-aa55-013fc15859bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847182780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2847182780
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1703041233
Short name T255
Test name
Test status
Simulation time 262815336 ps
CPU time 12.75 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 220020 kb
Host smart-7f1a653a-1559-4185-bb04-30d98504af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703041233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1703041233
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.187445849
Short name T232
Test name
Test status
Simulation time 2989129727 ps
CPU time 39.02 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:23:24 PM PDT 24
Peak memory 220016 kb
Host smart-3fb44c39-5573-496e-915c-1db94cba90fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187445849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.187445849
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1425736470
Short name T26
Test name
Test status
Simulation time 203953377 ps
CPU time 8.32 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:31 PM PDT 24
Peak memory 219016 kb
Host smart-ab298a5d-6583-4b00-b794-ce12b98effb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425736470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1425736470
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3301325781
Short name T290
Test name
Test status
Simulation time 21043872527 ps
CPU time 236.07 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:27:17 PM PDT 24
Peak memory 240540 kb
Host smart-10f346d4-9a12-40f3-933f-e268f3e04feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301325781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3301325781
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3074582752
Short name T300
Test name
Test status
Simulation time 1323515212 ps
CPU time 19.48 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:23:43 PM PDT 24
Peak memory 219960 kb
Host smart-69e5368e-3afe-41ed-bd2b-a6617d4c1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074582752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3074582752
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4214368815
Short name T319
Test name
Test status
Simulation time 3960358793 ps
CPU time 16.64 seconds
Started Aug 01 05:23:20 PM PDT 24
Finished Aug 01 05:23:36 PM PDT 24
Peak memory 219556 kb
Host smart-0f2af915-6239-4de2-af3d-4ab04dd10b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214368815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4214368815
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.442918758
Short name T251
Test name
Test status
Simulation time 336021823 ps
CPU time 13.52 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 219784 kb
Host smart-edfe5a89-d529-4530-99b1-1f28d9007b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442918758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.442918758
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3208915493
Short name T241
Test name
Test status
Simulation time 251182742 ps
CPU time 10.07 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:23:41 PM PDT 24
Peak memory 218940 kb
Host smart-e05c3dd9-a196-4610-8d2a-2a59fe34d9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208915493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3208915493
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.217043736
Short name T168
Test name
Test status
Simulation time 1896499810 ps
CPU time 185.79 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 229216 kb
Host smart-1adc24e2-063f-43c4-8649-40c9e2619d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217043736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.217043736
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4074767726
Short name T203
Test name
Test status
Simulation time 552613024 ps
CPU time 18.87 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:43 PM PDT 24
Peak memory 219972 kb
Host smart-c649705b-b406-4b65-b7fc-19a33d216b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074767726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4074767726
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1523279729
Short name T123
Test name
Test status
Simulation time 992598925 ps
CPU time 12.22 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:36 PM PDT 24
Peak memory 220028 kb
Host smart-e617494f-d572-4856-83e9-4b3b7d85a4b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523279729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1523279729
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2266066561
Short name T87
Test name
Test status
Simulation time 554709205 ps
CPU time 31.43 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:54 PM PDT 24
Peak memory 219928 kb
Host smart-1859675b-6e42-4076-a370-4d4cee959f82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266066561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2266066561
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1586703430
Short name T51
Test name
Test status
Simulation time 1074056133195 ps
CPU time 3137.92 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 06:15:41 PM PDT 24
Peak memory 253008 kb
Host smart-f7d14275-595f-4f58-bffa-01fd818079b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586703430 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1586703430
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3526989390
Short name T220
Test name
Test status
Simulation time 1025954112 ps
CPU time 9.66 seconds
Started Aug 01 05:23:28 PM PDT 24
Finished Aug 01 05:23:38 PM PDT 24
Peak memory 219060 kb
Host smart-ff3e67a5-749f-4656-96b4-83fb0df4bcef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526989390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3526989390
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1042906150
Short name T149
Test name
Test status
Simulation time 22881762552 ps
CPU time 293.48 seconds
Started Aug 01 05:23:26 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 234544 kb
Host smart-376d65ca-010b-4432-b8d1-b276a8fb0b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042906150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1042906150
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2211848110
Short name T268
Test name
Test status
Simulation time 2200686108 ps
CPU time 19.34 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:23:50 PM PDT 24
Peak memory 220084 kb
Host smart-82ceaee3-25c9-407d-bff5-dadeafc3fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211848110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2211848110
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3953482879
Short name T314
Test name
Test status
Simulation time 181521069 ps
CPU time 10.47 seconds
Started Aug 01 05:23:21 PM PDT 24
Finished Aug 01 05:23:32 PM PDT 24
Peak memory 220004 kb
Host smart-d7d473fa-8070-4c3e-8f31-1cd189cda8f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953482879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3953482879
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.962269871
Short name T215
Test name
Test status
Simulation time 537462181 ps
CPU time 26.83 seconds
Started Aug 01 05:23:23 PM PDT 24
Finished Aug 01 05:23:50 PM PDT 24
Peak memory 220052 kb
Host smart-3ac1442a-7323-4759-85ff-8346fb1c8024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962269871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.962269871
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1930105237
Short name T53
Test name
Test status
Simulation time 29071246462 ps
CPU time 1164.49 seconds
Started Aug 01 05:23:27 PM PDT 24
Finished Aug 01 05:42:52 PM PDT 24
Peak memory 236612 kb
Host smart-6a224ee3-646d-40a0-8924-77c9a91eb8c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930105237 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1930105237
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3093390387
Short name T164
Test name
Test status
Simulation time 1270275815 ps
CPU time 8.11 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:32 PM PDT 24
Peak memory 219168 kb
Host smart-89b2a179-820e-4b8c-acca-0e502d1168f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093390387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3093390387
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3819686459
Short name T269
Test name
Test status
Simulation time 4084439329 ps
CPU time 112.99 seconds
Started Aug 01 05:23:27 PM PDT 24
Finished Aug 01 05:25:21 PM PDT 24
Peak memory 220140 kb
Host smart-5cdeeeab-25f0-48ac-84d2-bdcff57462e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819686459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3819686459
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2226734782
Short name T247
Test name
Test status
Simulation time 992302675 ps
CPU time 21.99 seconds
Started Aug 01 05:23:26 PM PDT 24
Finished Aug 01 05:23:48 PM PDT 24
Peak memory 219972 kb
Host smart-5c046d1b-5c73-4e95-b9c7-feac08870706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226734782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2226734782
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1909809459
Short name T305
Test name
Test status
Simulation time 511807360 ps
CPU time 11.93 seconds
Started Aug 01 05:23:27 PM PDT 24
Finished Aug 01 05:23:39 PM PDT 24
Peak memory 219952 kb
Host smart-8b53f4f9-516c-49fd-a190-549745e30dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909809459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1909809459
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.445054569
Short name T32
Test name
Test status
Simulation time 3720785912 ps
CPU time 27.58 seconds
Started Aug 01 05:23:27 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 220040 kb
Host smart-3327b5f9-f1bf-49b0-bd2b-83be8e83fa82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445054569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.445054569
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2983655695
Short name T266
Test name
Test status
Simulation time 58523238135 ps
CPU time 8013.96 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 07:37:00 PM PDT 24
Peak memory 233592 kb
Host smart-cf522625-68ec-4fa3-86e3-a66d908cfc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983655695 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2983655695
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.9094512
Short name T278
Test name
Test status
Simulation time 252640195 ps
CPU time 9.98 seconds
Started Aug 01 05:23:26 PM PDT 24
Finished Aug 01 05:23:36 PM PDT 24
Peak memory 219040 kb
Host smart-3d539883-fb11-4f60-a162-c57e9f83b1e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9094512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.9094512
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.895369123
Short name T40
Test name
Test status
Simulation time 6024029077 ps
CPU time 300.68 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 239048 kb
Host smart-2b56fc41-da98-40bd-a777-44ba84d33f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895369123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.895369123
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3978167161
Short name T309
Test name
Test status
Simulation time 10852956385 ps
CPU time 31.92 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:23:57 PM PDT 24
Peak memory 220072 kb
Host smart-b6c52760-3177-4e18-a5c5-2686a4774c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978167161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3978167161
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1875880817
Short name T191
Test name
Test status
Simulation time 272786546 ps
CPU time 12.19 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:37 PM PDT 24
Peak memory 219996 kb
Host smart-0ba630a9-8a37-45d3-ab21-191badc2900e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875880817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1875880817
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2839315087
Short name T318
Test name
Test status
Simulation time 2091578627 ps
CPU time 30.31 seconds
Started Aug 01 05:23:27 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 219832 kb
Host smart-cae3ab61-1f26-4b6d-96eb-ecb60dfb1365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839315087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2839315087
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.865950320
Short name T15
Test name
Test status
Simulation time 13061608424 ps
CPU time 5413.32 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 06:53:40 PM PDT 24
Peak memory 231736 kb
Host smart-98917b05-715e-4974-ae73-3d3fa823cf77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865950320 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.865950320
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1182427422
Short name T264
Test name
Test status
Simulation time 989381854 ps
CPU time 10.24 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 219124 kb
Host smart-86212e91-0675-493d-9ebb-604f8e589606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182427422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1182427422
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2668337686
Short name T193
Test name
Test status
Simulation time 4074400570 ps
CPU time 270.36 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 226252 kb
Host smart-c70221ae-4d11-4490-97a1-c230eaa65c0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668337686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2668337686
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.671035948
Short name T219
Test name
Test status
Simulation time 3799592730 ps
CPU time 22.45 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:46 PM PDT 24
Peak memory 220248 kb
Host smart-f6d6f24a-4351-4cc2-8fb2-7b858e259e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671035948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.671035948
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.287744708
Short name T253
Test name
Test status
Simulation time 1882453176 ps
CPU time 24.69 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219900 kb
Host smart-ddaac5c4-cdd6-4d5b-918b-ab9e3cf0c9a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287744708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.287744708
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1058759614
Short name T129
Test name
Test status
Simulation time 171805190 ps
CPU time 8.41 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 219004 kb
Host smart-ca0b0f48-fb33-43e5-95ed-c3fd4c56001c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058759614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1058759614
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.124181720
Short name T245
Test name
Test status
Simulation time 3111584868 ps
CPU time 200.93 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:26:46 PM PDT 24
Peak memory 219036 kb
Host smart-6402534c-ea1a-4604-b73d-8200561112cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124181720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.124181720
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.179644792
Short name T313
Test name
Test status
Simulation time 1380488219 ps
CPU time 18.72 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:43 PM PDT 24
Peak memory 220040 kb
Host smart-b2531555-eb49-44ec-88f7-e77e2fdee150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179644792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.179644792
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2316889717
Short name T188
Test name
Test status
Simulation time 3814641774 ps
CPU time 16.59 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 220152 kb
Host smart-8ba50be5-7ab0-4d1f-b9d8-1c9e5ea7c389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316889717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2316889717
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.856424151
Short name T7
Test name
Test status
Simulation time 1591303180 ps
CPU time 27.21 seconds
Started Aug 01 05:23:22 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219892 kb
Host smart-0a4332ed-c5d7-431b-b539-a7515403bf16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856424151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.856424151
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2203463380
Short name T50
Test name
Test status
Simulation time 58284316530 ps
CPU time 1122.16 seconds
Started Aug 01 05:23:25 PM PDT 24
Finished Aug 01 05:42:07 PM PDT 24
Peak memory 234860 kb
Host smart-fc2995ca-56cb-431a-86f1-e8f7ebeb2bbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203463380 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2203463380
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3562079009
Short name T271
Test name
Test status
Simulation time 3099799326 ps
CPU time 10.23 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:23:41 PM PDT 24
Peak memory 218984 kb
Host smart-0e0e620d-6aa5-45cb-abbd-93b5857e999a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562079009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3562079009
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3243630899
Short name T48
Test name
Test status
Simulation time 2642644270 ps
CPU time 200.63 seconds
Started Aug 01 05:23:37 PM PDT 24
Finished Aug 01 05:26:57 PM PDT 24
Peak memory 238540 kb
Host smart-6995e4e9-c678-4126-86a6-354089f31e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243630899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3243630899
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4081693682
Short name T167
Test name
Test status
Simulation time 1077472633 ps
CPU time 21.92 seconds
Started Aug 01 05:23:36 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 220016 kb
Host smart-fdb3c573-2b77-4968-9cf7-847be81771bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081693682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4081693682
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1361193509
Short name T151
Test name
Test status
Simulation time 348058402 ps
CPU time 12.34 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:36 PM PDT 24
Peak memory 220008 kb
Host smart-dd77112c-de7a-4341-9c69-a2f61d51b68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361193509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1361193509
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1516375260
Short name T4
Test name
Test status
Simulation time 2603267322 ps
CPU time 34.67 seconds
Started Aug 01 05:23:24 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 220100 kb
Host smart-2814d869-998f-4ecc-a476-cbd54c96c37c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516375260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1516375260
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1079004350
Short name T147
Test name
Test status
Simulation time 660378547 ps
CPU time 8.35 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:23:38 PM PDT 24
Peak memory 219016 kb
Host smart-7e50ce38-aa0b-4667-a8ab-8ac4f7616338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079004350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1079004350
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.926637123
Short name T126
Test name
Test status
Simulation time 2513821312 ps
CPU time 99.8 seconds
Started Aug 01 05:23:32 PM PDT 24
Finished Aug 01 05:25:12 PM PDT 24
Peak memory 241712 kb
Host smart-9e65f71a-5fb7-4407-aee5-b87b9ef75ea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926637123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.926637123
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4226910340
Short name T192
Test name
Test status
Simulation time 705872274 ps
CPU time 18.83 seconds
Started Aug 01 05:23:29 PM PDT 24
Finished Aug 01 05:23:48 PM PDT 24
Peak memory 220072 kb
Host smart-f65bb1ae-b326-417d-ac94-dae864f44f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226910340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4226910340
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4231932103
Short name T200
Test name
Test status
Simulation time 1080087247 ps
CPU time 12.13 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 219964 kb
Host smart-3935f804-15f2-466f-b34d-4c0dbb636d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231932103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4231932103
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1959483788
Short name T124
Test name
Test status
Simulation time 383598990 ps
CPU time 26.93 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:24:02 PM PDT 24
Peak memory 219956 kb
Host smart-318a7e14-d5c2-4ed9-90e6-c1b052fde8e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959483788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1959483788
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1845269314
Short name T130
Test name
Test status
Simulation time 1029747130 ps
CPU time 9.93 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:23:45 PM PDT 24
Peak memory 218792 kb
Host smart-71bb5d1c-e9c9-46fb-956a-1aa049ca9053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845269314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1845269314
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.215858929
Short name T238
Test name
Test status
Simulation time 7394423909 ps
CPU time 274.13 seconds
Started Aug 01 05:23:33 PM PDT 24
Finished Aug 01 05:28:08 PM PDT 24
Peak memory 235520 kb
Host smart-1471c9c8-baf4-41ec-8aaa-007c01454b3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215858929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.215858929
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3265903505
Short name T132
Test name
Test status
Simulation time 517139247 ps
CPU time 23.23 seconds
Started Aug 01 05:23:32 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 219988 kb
Host smart-9772682b-262d-406f-8b66-5cd6a28fe4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265903505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3265903505
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.481926547
Short name T177
Test name
Test status
Simulation time 1020367077 ps
CPU time 11.8 seconds
Started Aug 01 05:23:36 PM PDT 24
Finished Aug 01 05:23:48 PM PDT 24
Peak memory 219976 kb
Host smart-2e4cbc22-fa6e-4fac-ad51-34aa8e00cff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481926547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.481926547
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2843022095
Short name T210
Test name
Test status
Simulation time 357342995 ps
CPU time 24.26 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 219944 kb
Host smart-30670074-19d7-4879-a7c9-91370d0cbf68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843022095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2843022095
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.829682840
Short name T197
Test name
Test status
Simulation time 989442538 ps
CPU time 9.87 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 219428 kb
Host smart-734f406b-a2c0-4bdd-9f93-d5a022c1c644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829682840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.829682840
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2595149079
Short name T274
Test name
Test status
Simulation time 3833662597 ps
CPU time 245.8 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:26:52 PM PDT 24
Peak memory 239672 kb
Host smart-a4ea68a7-dbc4-4732-b9e3-0f7f9ed0b85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595149079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2595149079
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1486353342
Short name T250
Test name
Test status
Simulation time 1548884796 ps
CPU time 22.68 seconds
Started Aug 01 05:22:50 PM PDT 24
Finished Aug 01 05:23:12 PM PDT 24
Peak memory 219940 kb
Host smart-53f896f1-4db2-464f-840f-b0dc5a780e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486353342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1486353342
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2534025520
Short name T61
Test name
Test status
Simulation time 527332873 ps
CPU time 10.26 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:22:56 PM PDT 24
Peak memory 219928 kb
Host smart-76bc12a8-88f2-433f-b759-4ff0599e4668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534025520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2534025520
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2262420415
Short name T25
Test name
Test status
Simulation time 230454702 ps
CPU time 115.24 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 240076 kb
Host smart-e7675a5e-9591-4a57-8a89-e67833b9a988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262420415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2262420415
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.722729131
Short name T8
Test name
Test status
Simulation time 918678787 ps
CPU time 12.04 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 219808 kb
Host smart-4ec93f2b-3d07-4969-93ec-e0557f94b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722729131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.722729131
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4192868137
Short name T30
Test name
Test status
Simulation time 330915438 ps
CPU time 17.61 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:06 PM PDT 24
Peak memory 219892 kb
Host smart-f02520ad-47bb-4068-8766-e526ed78090c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192868137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4192868137
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1410325889
Short name T73
Test name
Test status
Simulation time 1076283953 ps
CPU time 14.86 seconds
Started Aug 01 05:23:34 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219072 kb
Host smart-53812098-5a0c-459d-834a-3ceb9342856c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410325889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1410325889
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.375019382
Short name T158
Test name
Test status
Simulation time 1502138292 ps
CPU time 117.34 seconds
Started Aug 01 05:23:32 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 230328 kb
Host smart-bfedd143-3106-4508-98b1-0794658d61c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375019382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.375019382
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.15056051
Short name T303
Test name
Test status
Simulation time 1504166929 ps
CPU time 19.14 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 219996 kb
Host smart-8683df64-22a8-45f9-ac83-010c72c15283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15056051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.15056051
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3405767411
Short name T141
Test name
Test status
Simulation time 277937598 ps
CPU time 12.14 seconds
Started Aug 01 05:23:37 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219976 kb
Host smart-b9f4d90a-27bc-486a-b700-8e34fc0e7740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405767411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3405767411
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.571460014
Short name T244
Test name
Test status
Simulation time 234226372 ps
CPU time 18.87 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219964 kb
Host smart-3237d10f-a74e-46e6-9a5c-b6149890a43c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571460014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.571460014
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1579849981
Short name T317
Test name
Test status
Simulation time 19370305266 ps
CPU time 8198.69 seconds
Started Aug 01 05:23:37 PM PDT 24
Finished Aug 01 07:40:17 PM PDT 24
Peak memory 231208 kb
Host smart-7d15565e-1d15-48f9-b0d7-37aa81e86e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579849981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1579849981
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3016499019
Short name T159
Test name
Test status
Simulation time 346209211 ps
CPU time 8.25 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 219044 kb
Host smart-5818b9d9-c9bf-4669-acd9-39a90ae71106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016499019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3016499019
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2050767022
Short name T311
Test name
Test status
Simulation time 3475425474 ps
CPU time 233.79 seconds
Started Aug 01 05:23:34 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 238224 kb
Host smart-c36a340c-d77b-4d9c-8758-83434a7b4d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050767022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2050767022
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2940458455
Short name T304
Test name
Test status
Simulation time 9797784018 ps
CPU time 33.08 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:24:09 PM PDT 24
Peak memory 220132 kb
Host smart-8c01330a-1677-4e47-b6d7-5973b7d3735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940458455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2940458455
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2544552113
Short name T183
Test name
Test status
Simulation time 184753770 ps
CPU time 10.27 seconds
Started Aug 01 05:23:32 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 220064 kb
Host smart-f1708a6d-1642-458f-9e98-377904164ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544552113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2544552113
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1835601213
Short name T186
Test name
Test status
Simulation time 3555914081 ps
CPU time 32.84 seconds
Started Aug 01 05:23:33 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 220152 kb
Host smart-4a122c8f-656b-4423-951e-1e82866c5197
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835601213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1835601213
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1843784321
Short name T71
Test name
Test status
Simulation time 3917492926 ps
CPU time 14.45 seconds
Started Aug 01 05:23:37 PM PDT 24
Finished Aug 01 05:23:51 PM PDT 24
Peak memory 219080 kb
Host smart-336f6c80-571e-44cc-9b5f-295a173b439b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843784321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1843784321
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3678541715
Short name T259
Test name
Test status
Simulation time 17919572677 ps
CPU time 179.93 seconds
Started Aug 01 05:23:34 PM PDT 24
Finished Aug 01 05:26:34 PM PDT 24
Peak memory 239488 kb
Host smart-a898109b-b03c-4390-aade-e1be590a2051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678541715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3678541715
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3010527814
Short name T140
Test name
Test status
Simulation time 613768656 ps
CPU time 22.24 seconds
Started Aug 01 05:23:36 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 219988 kb
Host smart-d698a81f-ac3c-4f8e-9606-233bcff9f619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010527814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3010527814
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2418337079
Short name T212
Test name
Test status
Simulation time 541584676 ps
CPU time 12.31 seconds
Started Aug 01 05:23:32 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 219916 kb
Host smart-91fbf434-e239-4c60-80f9-44530742b643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418337079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2418337079
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2951935428
Short name T284
Test name
Test status
Simulation time 991044173 ps
CPU time 35.32 seconds
Started Aug 01 05:23:31 PM PDT 24
Finished Aug 01 05:24:07 PM PDT 24
Peak memory 220564 kb
Host smart-94b1cfa6-f4e7-42c8-b51e-1f6e48b04ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951935428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2951935428
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2410750689
Short name T161
Test name
Test status
Simulation time 1367756311 ps
CPU time 9.8 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:23:51 PM PDT 24
Peak memory 219064 kb
Host smart-9a42ce69-c2fd-4ec3-a6d3-dc562ea14c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410750689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2410750689
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.152764740
Short name T292
Test name
Test status
Simulation time 16401252030 ps
CPU time 263.47 seconds
Started Aug 01 05:23:30 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 219884 kb
Host smart-c3e71882-7275-4d20-9074-41961184cd70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152764740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.152764740
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3097757201
Short name T299
Test name
Test status
Simulation time 517449933 ps
CPU time 22.14 seconds
Started Aug 01 05:23:33 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 220096 kb
Host smart-63d35d41-710e-4d99-9220-12d9884fee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097757201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3097757201
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2718065204
Short name T10
Test name
Test status
Simulation time 264387019 ps
CPU time 12.08 seconds
Started Aug 01 05:23:35 PM PDT 24
Finished Aug 01 05:23:47 PM PDT 24
Peak memory 219996 kb
Host smart-ee258974-d775-4e3c-8c86-f004a05b3577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718065204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2718065204
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1199154477
Short name T243
Test name
Test status
Simulation time 3979156234 ps
CPU time 48.3 seconds
Started Aug 01 05:23:33 PM PDT 24
Finished Aug 01 05:24:22 PM PDT 24
Peak memory 220112 kb
Host smart-be44c708-fff3-42b5-ac6c-5c90651f88ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199154477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1199154477
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3117570197
Short name T296
Test name
Test status
Simulation time 981739247 ps
CPU time 15.11 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 219032 kb
Host smart-fbf08ac6-936c-40fa-b029-dd2bcbf60545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117570197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3117570197
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2824209896
Short name T316
Test name
Test status
Simulation time 12011959877 ps
CPU time 220.9 seconds
Started Aug 01 05:23:40 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 226256 kb
Host smart-eb2a6fbc-da98-403d-b8d4-d960cde8b81b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824209896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2824209896
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2589455554
Short name T286
Test name
Test status
Simulation time 2069967373 ps
CPU time 22.14 seconds
Started Aug 01 05:23:50 PM PDT 24
Finished Aug 01 05:24:12 PM PDT 24
Peak memory 219964 kb
Host smart-4cfae19e-99d2-4451-9ba9-a51db9953f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589455554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2589455554
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1072078494
Short name T121
Test name
Test status
Simulation time 1502619153 ps
CPU time 12.11 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 219960 kb
Host smart-16a824ff-3133-4e59-9c8e-4f08ed7b439c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072078494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1072078494
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3554710068
Short name T133
Test name
Test status
Simulation time 501066360 ps
CPU time 14.92 seconds
Started Aug 01 05:23:45 PM PDT 24
Finished Aug 01 05:24:00 PM PDT 24
Peak memory 219760 kb
Host smart-30eeb3e0-e7f2-4468-9125-d0347e6efa6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554710068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3554710068
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3842271021
Short name T55
Test name
Test status
Simulation time 291570338 ps
CPU time 8.18 seconds
Started Aug 01 05:23:44 PM PDT 24
Finished Aug 01 05:23:53 PM PDT 24
Peak memory 219064 kb
Host smart-59acad9a-3e77-426f-a13a-be9828eebcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842271021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3842271021
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1220443764
Short name T231
Test name
Test status
Simulation time 10767428959 ps
CPU time 293.82 seconds
Started Aug 01 05:23:47 PM PDT 24
Finished Aug 01 05:28:41 PM PDT 24
Peak memory 237744 kb
Host smart-49391b28-bf99-49bf-a6c4-6aa8139cc81b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220443764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1220443764
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2021474222
Short name T302
Test name
Test status
Simulation time 516504125 ps
CPU time 22.57 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 219896 kb
Host smart-e6bbfc1e-0eac-4f0c-849f-7703685e8f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021474222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2021474222
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2647177228
Short name T261
Test name
Test status
Simulation time 518977562 ps
CPU time 11.92 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 220012 kb
Host smart-cb82d6ca-ba41-4f56-8c52-cf6d64cf6907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647177228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2647177228
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1767012537
Short name T13
Test name
Test status
Simulation time 2006584590 ps
CPU time 26.94 seconds
Started Aug 01 05:23:40 PM PDT 24
Finished Aug 01 05:24:08 PM PDT 24
Peak memory 219984 kb
Host smart-69d6449b-f728-4266-b47e-fcff02e4031c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767012537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1767012537
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2056849455
Short name T206
Test name
Test status
Simulation time 1026105487 ps
CPU time 10.05 seconds
Started Aug 01 05:23:44 PM PDT 24
Finished Aug 01 05:23:54 PM PDT 24
Peak memory 218984 kb
Host smart-854b4b57-9ec5-4253-ae3f-2ffb59536541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056849455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2056849455
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3919765284
Short name T184
Test name
Test status
Simulation time 12935804461 ps
CPU time 371.51 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:29:52 PM PDT 24
Peak memory 225140 kb
Host smart-23868679-8bc3-482e-b3ea-0320e5eb504c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919765284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3919765284
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1638366026
Short name T27
Test name
Test status
Simulation time 1033926331 ps
CPU time 22.44 seconds
Started Aug 01 05:23:50 PM PDT 24
Finished Aug 01 05:24:12 PM PDT 24
Peak memory 219968 kb
Host smart-66fd49ec-2d5e-4266-b858-963fcad1f846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638366026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1638366026
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3519979661
Short name T223
Test name
Test status
Simulation time 181728759 ps
CPU time 10.45 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:53 PM PDT 24
Peak memory 220076 kb
Host smart-ca5ae4d6-6ad4-4dfd-ad60-e58ac6d8fb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519979661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3519979661
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2280796014
Short name T281
Test name
Test status
Simulation time 1079650982 ps
CPU time 24.08 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 219952 kb
Host smart-4ddbba35-2b4d-47c3-b0c7-c2ce841d4302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280796014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2280796014
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3259826461
Short name T194
Test name
Test status
Simulation time 787236021 ps
CPU time 8.3 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 219108 kb
Host smart-d6ec6f7d-be4c-4f9d-ac7f-62b85c86f643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259826461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3259826461
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.738860049
Short name T270
Test name
Test status
Simulation time 8075452000 ps
CPU time 237.73 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 218816 kb
Host smart-e0e6ab13-18be-4af1-a986-a0e4a9c53f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738860049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.738860049
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2306151509
Short name T128
Test name
Test status
Simulation time 1029827814 ps
CPU time 22.45 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 220052 kb
Host smart-23f257ba-0e43-49ad-a831-a99f8d6b8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306151509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2306151509
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4209148194
Short name T252
Test name
Test status
Simulation time 916322720 ps
CPU time 11.7 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:23:54 PM PDT 24
Peak memory 220072 kb
Host smart-526c1c92-d9a2-4bc8-800c-872ce8be4910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209148194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4209148194
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1318695599
Short name T199
Test name
Test status
Simulation time 554219366 ps
CPU time 35.23 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:24:18 PM PDT 24
Peak memory 220000 kb
Host smart-9ab9a24b-ef56-498c-b59a-c1de85724f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318695599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1318695599
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1501442724
Short name T68
Test name
Test status
Simulation time 319081720 ps
CPU time 8.29 seconds
Started Aug 01 05:23:47 PM PDT 24
Finished Aug 01 05:23:56 PM PDT 24
Peak memory 219124 kb
Host smart-be7278e3-5f7c-4cd7-b4fb-d5d86758596e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501442724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1501442724
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3997481848
Short name T275
Test name
Test status
Simulation time 23516302291 ps
CPU time 128.42 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 239648 kb
Host smart-c0d58533-c1a6-44a5-97a0-3c553413f8f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997481848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3997481848
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.10235652
Short name T131
Test name
Test status
Simulation time 2905167833 ps
CPU time 22.47 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:24:04 PM PDT 24
Peak memory 220108 kb
Host smart-96f3b0ef-8492-4195-815b-35ba6bc904d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10235652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.10235652
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1186879518
Short name T249
Test name
Test status
Simulation time 721178647 ps
CPU time 9.82 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:23:52 PM PDT 24
Peak memory 219916 kb
Host smart-08fe80b3-ab96-4d04-8fe1-a2c5f9702c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186879518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1186879518
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.717275253
Short name T86
Test name
Test status
Simulation time 826549535 ps
CPU time 40.97 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:24:23 PM PDT 24
Peak memory 219944 kb
Host smart-104857a9-c07d-4fe0-af9e-1d4c5c3bc856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717275253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.717275253
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3650388468
Short name T166
Test name
Test status
Simulation time 992538289 ps
CPU time 9.92 seconds
Started Aug 01 05:23:40 PM PDT 24
Finished Aug 01 05:23:51 PM PDT 24
Peak memory 219004 kb
Host smart-f160d427-c865-41e1-b622-be9226dfc15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650388468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3650388468
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2826761427
Short name T2
Test name
Test status
Simulation time 5818235924 ps
CPU time 188.42 seconds
Started Aug 01 05:23:41 PM PDT 24
Finished Aug 01 05:26:50 PM PDT 24
Peak memory 240836 kb
Host smart-200b8a7c-f57e-447a-b45a-08e52b42e2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826761427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2826761427
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3614368324
Short name T9
Test name
Test status
Simulation time 569426530 ps
CPU time 22.93 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 220008 kb
Host smart-18c43955-7c1b-4e87-a9e1-a0a62582642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614368324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3614368324
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1478686845
Short name T189
Test name
Test status
Simulation time 178706123 ps
CPU time 10.48 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:23:53 PM PDT 24
Peak memory 220008 kb
Host smart-f11885ce-1657-4318-9d0f-6a70a73aec1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478686845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1478686845
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.620051509
Short name T150
Test name
Test status
Simulation time 1666855058 ps
CPU time 14.54 seconds
Started Aug 01 05:23:42 PM PDT 24
Finished Aug 01 05:23:57 PM PDT 24
Peak memory 219852 kb
Host smart-fbe899fc-b930-405d-8778-398c896a6252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620051509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.620051509
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4128067698
Short name T72
Test name
Test status
Simulation time 1032686258 ps
CPU time 9.69 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:22:57 PM PDT 24
Peak memory 219056 kb
Host smart-9c810119-e05e-412b-b513-4d9d105f779b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128067698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4128067698
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.726251415
Short name T144
Test name
Test status
Simulation time 187439530549 ps
CPU time 343.63 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:28:31 PM PDT 24
Peak memory 235264 kb
Host smart-6a419e42-0669-43df-ae1f-86b98682c08d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726251415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.726251415
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4124244696
Short name T301
Test name
Test status
Simulation time 2251686099 ps
CPU time 22.82 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:23:10 PM PDT 24
Peak memory 220104 kb
Host smart-40a9be18-e2b4-45d2-aa80-600b1c360307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124244696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4124244696
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2416811237
Short name T209
Test name
Test status
Simulation time 357339895 ps
CPU time 10.83 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:22:54 PM PDT 24
Peak memory 219948 kb
Host smart-45146550-e53b-460a-bbac-1954ca6310b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416811237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2416811237
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3331252920
Short name T171
Test name
Test status
Simulation time 1955690915 ps
CPU time 11.77 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 220068 kb
Host smart-83aca37b-d2a3-45a7-ada3-46406f6223da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331252920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3331252920
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1745256521
Short name T56
Test name
Test status
Simulation time 562257391 ps
CPU time 37.02 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 219988 kb
Host smart-5be40110-4e0b-49ed-81d5-36935bc43308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745256521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1745256521
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2254926845
Short name T260
Test name
Test status
Simulation time 63574175961 ps
CPU time 2917.54 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 06:11:23 PM PDT 24
Peak memory 230724 kb
Host smart-44787d27-0931-4e5c-82c3-4a9684e7b588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254926845 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2254926845
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1780623802
Short name T70
Test name
Test status
Simulation time 883605776 ps
CPU time 9.93 seconds
Started Aug 01 05:22:50 PM PDT 24
Finished Aug 01 05:23:00 PM PDT 24
Peak memory 218916 kb
Host smart-25635ebf-51e4-4558-a204-3c6db7fa934f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780623802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1780623802
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2597001249
Short name T31
Test name
Test status
Simulation time 1376636403 ps
CPU time 19.27 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:23:06 PM PDT 24
Peak memory 220288 kb
Host smart-85a16013-6586-4176-99fb-a79cb966d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597001249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2597001249
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.872222758
Short name T105
Test name
Test status
Simulation time 276003012 ps
CPU time 12.51 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:02 PM PDT 24
Peak memory 219916 kb
Host smart-7ce58f07-6fea-495f-8ae9-4ef4461a4a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872222758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.872222758
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1911287612
Short name T229
Test name
Test status
Simulation time 525392404 ps
CPU time 12.86 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 220052 kb
Host smart-3d90ccda-b37d-4032-a74d-1be909785e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911287612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1911287612
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3695953016
Short name T160
Test name
Test status
Simulation time 3106913356 ps
CPU time 38.57 seconds
Started Aug 01 05:22:51 PM PDT 24
Finished Aug 01 05:23:29 PM PDT 24
Peak memory 220108 kb
Host smart-e0e0caa5-f3f4-4d75-ac98-a03a76d2a6d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695953016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3695953016
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.152886681
Short name T169
Test name
Test status
Simulation time 548756795 ps
CPU time 9.98 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 219108 kb
Host smart-87abf060-eb3c-4f96-b3e7-f92a504d942a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152886681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.152886681
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3008493683
Short name T137
Test name
Test status
Simulation time 1935760843 ps
CPU time 138.03 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:25:05 PM PDT 24
Peak memory 236948 kb
Host smart-4e9dda6f-60ea-453f-8a1c-ab9aef9504bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008493683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3008493683
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2197951980
Short name T176
Test name
Test status
Simulation time 7536805596 ps
CPU time 32.86 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:23:19 PM PDT 24
Peak memory 220160 kb
Host smart-072edcfe-6e48-41bb-af67-fa9cfa4d790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197951980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2197951980
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.995125044
Short name T295
Test name
Test status
Simulation time 269695138 ps
CPU time 12.08 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:22:57 PM PDT 24
Peak memory 219944 kb
Host smart-11c6e98a-da61-43a0-915c-f0bd592dafc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995125044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.995125044
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3838461723
Short name T230
Test name
Test status
Simulation time 362520368 ps
CPU time 10.66 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 219972 kb
Host smart-d48b6a6a-1182-4927-a522-92c1c308d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838461723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3838461723
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2021154178
Short name T179
Test name
Test status
Simulation time 707450090 ps
CPU time 39.25 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:28 PM PDT 24
Peak memory 219876 kb
Host smart-52abe39a-7318-49c3-97d6-aca2567e4b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021154178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2021154178
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.37834821
Short name T315
Test name
Test status
Simulation time 339323882 ps
CPU time 8.34 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:22:54 PM PDT 24
Peak memory 219108 kb
Host smart-be34cadf-0a01-4574-a692-17cd41c9e06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.37834821
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3861259536
Short name T163
Test name
Test status
Simulation time 4426128628 ps
CPU time 257.07 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:27:04 PM PDT 24
Peak memory 240596 kb
Host smart-b7f80f91-a617-4f0e-b9bb-e0af6be0349a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861259536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3861259536
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.655216188
Short name T103
Test name
Test status
Simulation time 260097400 ps
CPU time 12.49 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:01 PM PDT 24
Peak memory 219912 kb
Host smart-e2fbffe3-10a9-47a1-85fc-c4edf65076f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655216188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.655216188
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4162279269
Short name T263
Test name
Test status
Simulation time 370565210 ps
CPU time 10.93 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:23:00 PM PDT 24
Peak memory 219916 kb
Host smart-0738c3fb-d666-43be-a747-3e55c3da63e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162279269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4162279269
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1420774424
Short name T178
Test name
Test status
Simulation time 220803096 ps
CPU time 18.63 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:23:08 PM PDT 24
Peak memory 219988 kb
Host smart-638e3c1a-abf6-4ebf-84cf-3248d69529d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420774424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1420774424
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.612759979
Short name T52
Test name
Test status
Simulation time 57164066495 ps
CPU time 536.93 seconds
Started Aug 01 05:22:45 PM PDT 24
Finished Aug 01 05:31:42 PM PDT 24
Peak memory 230776 kb
Host smart-b84bd87c-0d00-4885-98e0-178482264fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612759979 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.612759979
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1244341274
Short name T213
Test name
Test status
Simulation time 167759752 ps
CPU time 8.64 seconds
Started Aug 01 05:22:55 PM PDT 24
Finished Aug 01 05:23:04 PM PDT 24
Peak memory 218952 kb
Host smart-d51af2fe-576f-4cfc-a866-199ac61ccec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244341274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1244341274
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2113823752
Short name T143
Test name
Test status
Simulation time 5542179519 ps
CPU time 291.19 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:27:48 PM PDT 24
Peak memory 226368 kb
Host smart-219363bb-58f7-4625-be2b-3e87f84a6cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113823752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2113823752
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2378751377
Short name T321
Test name
Test status
Simulation time 1650184338 ps
CPU time 19.46 seconds
Started Aug 01 05:22:57 PM PDT 24
Finished Aug 01 05:23:16 PM PDT 24
Peak memory 220068 kb
Host smart-40ca30df-18c9-46fa-8db2-c727a5232d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378751377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2378751377
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1414928681
Short name T174
Test name
Test status
Simulation time 1070655371 ps
CPU time 11.66 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 220032 kb
Host smart-08a273f9-871d-4612-b98a-fbfd64a8b33e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414928681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1414928681
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3107172952
Short name T90
Test name
Test status
Simulation time 261413189 ps
CPU time 12.53 seconds
Started Aug 01 05:22:48 PM PDT 24
Finished Aug 01 05:23:01 PM PDT 24
Peak memory 220016 kb
Host smart-57589a31-3846-4895-a9a2-66ee9a36b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107172952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3107172952
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3382220248
Short name T242
Test name
Test status
Simulation time 2894532896 ps
CPU time 23.26 seconds
Started Aug 01 05:22:47 PM PDT 24
Finished Aug 01 05:23:11 PM PDT 24
Peak memory 220120 kb
Host smart-23999ef7-1b0a-4bf6-b5aa-cebbc1198192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382220248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3382220248
Directory /workspace/9.rom_ctrl_stress_all/latest
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