Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 96.89 91.85 97.68 100.00 98.28 97.30 98.14


Total test records in report: 410
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T296 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1917392245 Aug 02 04:55:24 PM PDT 24 Aug 02 04:55:36 PM PDT 24 1715722513 ps
T297 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1415036573 Aug 02 04:55:30 PM PDT 24 Aug 02 05:23:50 PM PDT 24 358784141378 ps
T298 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2302926441 Aug 02 04:55:39 PM PDT 24 Aug 02 05:01:12 PM PDT 24 11315002328 ps
T299 /workspace/coverage/default/25.rom_ctrl_alert_test.1680090323 Aug 02 04:55:19 PM PDT 24 Aug 02 04:55:29 PM PDT 24 3513907257 ps
T300 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.150076900 Aug 02 04:55:13 PM PDT 24 Aug 02 05:00:11 PM PDT 24 23639438281 ps
T301 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.856252199 Aug 02 04:55:09 PM PDT 24 Aug 02 04:55:28 PM PDT 24 973553633 ps
T302 /workspace/coverage/default/24.rom_ctrl_alert_test.2950556235 Aug 02 04:55:27 PM PDT 24 Aug 02 04:55:43 PM PDT 24 3944993479 ps
T303 /workspace/coverage/default/27.rom_ctrl_alert_test.3229083051 Aug 02 04:55:24 PM PDT 24 Aug 02 04:55:34 PM PDT 24 1768627627 ps
T304 /workspace/coverage/default/42.rom_ctrl_alert_test.348290186 Aug 02 04:55:45 PM PDT 24 Aug 02 04:55:55 PM PDT 24 1027850451 ps
T305 /workspace/coverage/default/48.rom_ctrl_alert_test.3954178586 Aug 02 04:55:43 PM PDT 24 Aug 02 04:55:58 PM PDT 24 9763438192 ps
T306 /workspace/coverage/default/28.rom_ctrl_alert_test.1067196956 Aug 02 04:55:19 PM PDT 24 Aug 02 04:55:30 PM PDT 24 259338404 ps
T307 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3501053152 Aug 02 04:55:20 PM PDT 24 Aug 02 04:58:53 PM PDT 24 14335184252 ps
T308 /workspace/coverage/default/19.rom_ctrl_alert_test.9101576 Aug 02 04:55:08 PM PDT 24 Aug 02 04:55:18 PM PDT 24 1032069242 ps
T309 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4227291745 Aug 02 04:55:33 PM PDT 24 Aug 02 05:00:28 PM PDT 24 17451070359 ps
T310 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2937189525 Aug 02 04:55:28 PM PDT 24 Aug 02 04:55:39 PM PDT 24 361495900 ps
T311 /workspace/coverage/default/44.rom_ctrl_alert_test.2000861022 Aug 02 04:55:38 PM PDT 24 Aug 02 04:55:48 PM PDT 24 258977397 ps
T312 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3907145467 Aug 02 04:55:26 PM PDT 24 Aug 02 04:55:48 PM PDT 24 1975341844 ps
T313 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.200800882 Aug 02 04:55:18 PM PDT 24 Aug 02 04:59:29 PM PDT 24 7519901150 ps
T314 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2353958623 Aug 02 04:55:15 PM PDT 24 Aug 02 04:55:26 PM PDT 24 877751911 ps
T315 /workspace/coverage/default/34.rom_ctrl_stress_all.3809670346 Aug 02 04:55:28 PM PDT 24 Aug 02 04:56:07 PM PDT 24 1224487652 ps
T316 /workspace/coverage/default/2.rom_ctrl_alert_test.4250627446 Aug 02 04:54:56 PM PDT 24 Aug 02 04:55:06 PM PDT 24 250394721 ps
T317 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2884127404 Aug 02 04:55:34 PM PDT 24 Aug 02 04:55:46 PM PDT 24 266086950 ps
T318 /workspace/coverage/default/5.rom_ctrl_stress_all.4157084463 Aug 02 04:55:01 PM PDT 24 Aug 02 04:55:31 PM PDT 24 1062515391 ps
T319 /workspace/coverage/default/15.rom_ctrl_alert_test.3312384139 Aug 02 04:55:15 PM PDT 24 Aug 02 04:55:25 PM PDT 24 1125696412 ps
T320 /workspace/coverage/default/31.rom_ctrl_stress_all.402959631 Aug 02 04:55:33 PM PDT 24 Aug 02 04:56:03 PM PDT 24 1061928916 ps
T321 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2112450803 Aug 02 04:54:58 PM PDT 24 Aug 02 04:57:46 PM PDT 24 12053142824 ps
T322 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.60787893 Aug 02 04:55:42 PM PDT 24 Aug 02 04:56:01 PM PDT 24 1325036744 ps
T323 /workspace/coverage/default/41.rom_ctrl_stress_all.3566516576 Aug 02 04:55:38 PM PDT 24 Aug 02 04:56:02 PM PDT 24 365428662 ps
T324 /workspace/coverage/default/39.rom_ctrl_stress_all.3883809517 Aug 02 04:55:35 PM PDT 24 Aug 02 04:56:34 PM PDT 24 16679962021 ps
T325 /workspace/coverage/default/47.rom_ctrl_stress_all.1930572876 Aug 02 04:55:36 PM PDT 24 Aug 02 04:56:07 PM PDT 24 2189905754 ps
T58 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2679919874 Aug 02 04:54:57 PM PDT 24 Aug 02 04:56:23 PM PDT 24 523799503 ps
T326 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1974362127 Aug 02 04:54:54 PM PDT 24 Aug 02 04:55:07 PM PDT 24 228115626 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3256728416 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:08 PM PDT 24 643125439 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3691538688 Aug 02 04:54:50 PM PDT 24 Aug 02 04:55:46 PM PDT 24 1394944428 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1127285864 Aug 02 04:54:49 PM PDT 24 Aug 02 04:54:59 PM PDT 24 1454646242 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4106683088 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:53 PM PDT 24 2058728274 ps
T59 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4122659085 Aug 02 04:54:58 PM PDT 24 Aug 02 04:57:29 PM PDT 24 1272477754 ps
T327 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.169602605 Aug 02 04:54:51 PM PDT 24 Aug 02 04:55:04 PM PDT 24 339173704 ps
T328 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.718679448 Aug 02 04:54:48 PM PDT 24 Aug 02 04:54:59 PM PDT 24 378925831 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.517345377 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:49 PM PDT 24 252421624 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.696400555 Aug 02 04:54:37 PM PDT 24 Aug 02 04:54:49 PM PDT 24 666547080 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4120429603 Aug 02 04:54:27 PM PDT 24 Aug 02 04:55:11 PM PDT 24 1018215541 ps
T329 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1338379657 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:54 PM PDT 24 256947856 ps
T330 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.438937142 Aug 02 04:54:47 PM PDT 24 Aug 02 04:54:56 PM PDT 24 1099105674 ps
T331 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2248190427 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:46 PM PDT 24 1020379715 ps
T332 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3657490272 Aug 02 04:54:51 PM PDT 24 Aug 02 04:55:04 PM PDT 24 260166484 ps
T333 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.50678768 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:59 PM PDT 24 987325188 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3295992031 Aug 02 04:54:40 PM PDT 24 Aug 02 04:54:49 PM PDT 24 612313610 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1508478285 Aug 02 04:54:36 PM PDT 24 Aug 02 04:54:46 PM PDT 24 2470995602 ps
T334 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.873510775 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:55 PM PDT 24 174899827 ps
T335 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3043316315 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:54 PM PDT 24 355959194 ps
T336 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1627160578 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:36 PM PDT 24 174531531 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2919928138 Aug 02 04:54:38 PM PDT 24 Aug 02 04:54:49 PM PDT 24 252141880 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.932073865 Aug 02 04:54:48 PM PDT 24 Aug 02 04:56:09 PM PDT 24 363795352 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1789201998 Aug 02 04:54:39 PM PDT 24 Aug 02 04:55:35 PM PDT 24 4922633355 ps
T104 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1723906757 Aug 02 04:54:38 PM PDT 24 Aug 02 04:55:59 PM PDT 24 1022426722 ps
T337 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.312964643 Aug 02 04:54:58 PM PDT 24 Aug 02 04:55:07 PM PDT 24 345328169 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3152751049 Aug 02 04:54:58 PM PDT 24 Aug 02 04:56:20 PM PDT 24 1328194875 ps
T338 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1314087280 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:47 PM PDT 24 914679358 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.463458451 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:36 PM PDT 24 332833156 ps
T90 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.653135109 Aug 02 04:54:50 PM PDT 24 Aug 02 04:55:04 PM PDT 24 1825986463 ps
T339 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1015966909 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:48 PM PDT 24 2946108423 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.531002133 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:44 PM PDT 24 773047653 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2922657463 Aug 02 04:54:49 PM PDT 24 Aug 02 04:55:03 PM PDT 24 2407705139 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1667137782 Aug 02 04:54:48 PM PDT 24 Aug 02 04:57:20 PM PDT 24 402249484 ps
T76 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1116621265 Aug 02 04:54:52 PM PDT 24 Aug 02 04:55:36 PM PDT 24 7259810308 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.628263166 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:36 PM PDT 24 226298273 ps
T340 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.34931016 Aug 02 04:55:01 PM PDT 24 Aug 02 04:55:13 PM PDT 24 339438503 ps
T341 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.518031924 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:37 PM PDT 24 688065315 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1419956126 Aug 02 04:55:00 PM PDT 24 Aug 02 04:55:11 PM PDT 24 259762050 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4258853998 Aug 02 04:54:37 PM PDT 24 Aug 02 04:57:11 PM PDT 24 5520036817 ps
T342 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3728296748 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:56 PM PDT 24 174615538 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.754445040 Aug 02 04:54:47 PM PDT 24 Aug 02 04:57:20 PM PDT 24 1287733267 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.531156495 Aug 02 04:54:40 PM PDT 24 Aug 02 04:57:15 PM PDT 24 1120562082 ps
T112 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2102698249 Aug 02 04:54:47 PM PDT 24 Aug 02 04:57:22 PM PDT 24 427535593 ps
T343 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2106014759 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:49 PM PDT 24 587790526 ps
T344 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3767698368 Aug 02 04:54:33 PM PDT 24 Aug 02 04:54:41 PM PDT 24 346993498 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3769083310 Aug 02 04:54:33 PM PDT 24 Aug 02 04:54:41 PM PDT 24 661474786 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4023864843 Aug 02 04:54:57 PM PDT 24 Aug 02 04:55:05 PM PDT 24 171127656 ps
T345 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.488450132 Aug 02 04:54:50 PM PDT 24 Aug 02 04:55:02 PM PDT 24 378307492 ps
T96 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4044443769 Aug 02 04:54:52 PM PDT 24 Aug 02 04:55:00 PM PDT 24 174706965 ps
T346 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2445720603 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:55 PM PDT 24 1041376171 ps
T347 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.454462978 Aug 02 04:54:53 PM PDT 24 Aug 02 04:55:03 PM PDT 24 975878102 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3648093843 Aug 02 04:54:31 PM PDT 24 Aug 02 04:54:48 PM PDT 24 503049947 ps
T348 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.368496698 Aug 02 04:54:38 PM PDT 24 Aug 02 04:54:48 PM PDT 24 505089553 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.221463789 Aug 02 04:54:33 PM PDT 24 Aug 02 04:55:54 PM PDT 24 1368291988 ps
T349 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4114344083 Aug 02 04:55:00 PM PDT 24 Aug 02 04:55:10 PM PDT 24 796062747 ps
T83 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1881374420 Aug 02 04:54:37 PM PDT 24 Aug 02 04:54:47 PM PDT 24 477948159 ps
T350 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1192343789 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:57 PM PDT 24 506451424 ps
T351 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.293249511 Aug 02 04:54:58 PM PDT 24 Aug 02 04:55:12 PM PDT 24 6156485666 ps
T352 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2198047365 Aug 02 04:54:42 PM PDT 24 Aug 02 04:54:52 PM PDT 24 988268046 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.946165177 Aug 02 04:54:39 PM PDT 24 Aug 02 04:55:35 PM PDT 24 4086389005 ps
T353 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1545319341 Aug 02 04:54:37 PM PDT 24 Aug 02 04:54:47 PM PDT 24 256007240 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1932700105 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:34 PM PDT 24 176826818 ps
T355 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.548699205 Aug 02 04:54:47 PM PDT 24 Aug 02 04:57:17 PM PDT 24 1162880476 ps
T356 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3415780638 Aug 02 04:54:54 PM PDT 24 Aug 02 04:55:04 PM PDT 24 178512570 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2040033492 Aug 02 04:54:38 PM PDT 24 Aug 02 04:54:53 PM PDT 24 421767718 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3345799546 Aug 02 04:54:35 PM PDT 24 Aug 02 04:54:46 PM PDT 24 3538331003 ps
T113 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3976932145 Aug 02 04:54:51 PM PDT 24 Aug 02 04:57:27 PM PDT 24 1430931924 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3569782390 Aug 02 04:55:01 PM PDT 24 Aug 02 04:55:10 PM PDT 24 174510186 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2363024683 Aug 02 04:54:41 PM PDT 24 Aug 02 04:54:58 PM PDT 24 1473720902 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3427970283 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:50 PM PDT 24 264076646 ps
T360 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2304927651 Aug 02 04:54:43 PM PDT 24 Aug 02 04:54:56 PM PDT 24 917079515 ps
T116 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3800220966 Aug 02 04:54:40 PM PDT 24 Aug 02 04:57:17 PM PDT 24 510612858 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3464022652 Aug 02 04:54:51 PM PDT 24 Aug 02 04:56:09 PM PDT 24 881029787 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.182036295 Aug 02 04:54:38 PM PDT 24 Aug 02 04:54:52 PM PDT 24 2756920038 ps
T362 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1167343788 Aug 02 04:54:47 PM PDT 24 Aug 02 04:54:58 PM PDT 24 332768133 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2953324312 Aug 02 04:54:57 PM PDT 24 Aug 02 04:55:11 PM PDT 24 525463850 ps
T364 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3932130578 Aug 02 04:54:48 PM PDT 24 Aug 02 04:54:58 PM PDT 24 262260081 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.126433929 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:40 PM PDT 24 255598870 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.384554658 Aug 02 04:55:04 PM PDT 24 Aug 02 04:55:12 PM PDT 24 2362992393 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1587323248 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:49 PM PDT 24 251213943 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1101531922 Aug 02 04:54:53 PM PDT 24 Aug 02 04:55:02 PM PDT 24 1121542937 ps
T369 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.83326087 Aug 02 04:55:02 PM PDT 24 Aug 02 04:55:17 PM PDT 24 1365835414 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2873096584 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:10 PM PDT 24 1099629042 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2787539942 Aug 02 04:54:55 PM PDT 24 Aug 02 04:55:05 PM PDT 24 1033243380 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.37165723 Aug 02 04:54:56 PM PDT 24 Aug 02 04:55:05 PM PDT 24 741466332 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.269544222 Aug 02 04:54:57 PM PDT 24 Aug 02 04:55:07 PM PDT 24 1029326208 ps
T374 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2281862842 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:12 PM PDT 24 267486312 ps
T375 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1268715391 Aug 02 04:54:46 PM PDT 24 Aug 02 04:56:07 PM PDT 24 488685919 ps
T376 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.297492878 Aug 02 04:54:46 PM PDT 24 Aug 02 04:54:57 PM PDT 24 271586887 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1927519173 Aug 02 04:54:40 PM PDT 24 Aug 02 04:54:49 PM PDT 24 172511808 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.611948002 Aug 02 04:54:41 PM PDT 24 Aug 02 04:54:49 PM PDT 24 174809909 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.815748513 Aug 02 04:54:46 PM PDT 24 Aug 02 04:54:56 PM PDT 24 249548639 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1495234639 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:39 PM PDT 24 205456707 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2259267595 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:11 PM PDT 24 178510794 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3638474515 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:53 PM PDT 24 190794067 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2250206365 Aug 02 04:54:46 PM PDT 24 Aug 02 04:54:56 PM PDT 24 323108675 ps
T383 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1265883260 Aug 02 04:55:00 PM PDT 24 Aug 02 04:55:10 PM PDT 24 1033727357 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1079878730 Aug 02 04:54:43 PM PDT 24 Aug 02 04:54:54 PM PDT 24 261299144 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2612137418 Aug 02 04:54:43 PM PDT 24 Aug 02 04:54:57 PM PDT 24 1068049496 ps
T386 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3273007935 Aug 02 04:54:48 PM PDT 24 Aug 02 04:54:56 PM PDT 24 174156034 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4233082992 Aug 02 04:54:40 PM PDT 24 Aug 02 04:54:52 PM PDT 24 789664537 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3597942690 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:57 PM PDT 24 359100549 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1181187253 Aug 02 04:54:47 PM PDT 24 Aug 02 04:54:57 PM PDT 24 519415840 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3083290385 Aug 02 04:54:42 PM PDT 24 Aug 02 04:54:51 PM PDT 24 753480917 ps
T391 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3602268997 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:53 PM PDT 24 692995179 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1872757204 Aug 02 04:54:44 PM PDT 24 Aug 02 04:56:12 PM PDT 24 1213620504 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3803115509 Aug 02 04:54:49 PM PDT 24 Aug 02 04:57:22 PM PDT 24 754851664 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1117871104 Aug 02 04:54:53 PM PDT 24 Aug 02 04:55:08 PM PDT 24 2029244447 ps
T111 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2574578699 Aug 02 04:54:43 PM PDT 24 Aug 02 04:56:03 PM PDT 24 972668099 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.243840606 Aug 02 04:54:58 PM PDT 24 Aug 02 04:55:07 PM PDT 24 362900061 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1977468303 Aug 02 04:54:51 PM PDT 24 Aug 02 04:55:02 PM PDT 24 338894791 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2190474554 Aug 02 04:54:58 PM PDT 24 Aug 02 04:55:13 PM PDT 24 1031059339 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3102314474 Aug 02 04:54:43 PM PDT 24 Aug 02 04:54:51 PM PDT 24 332669611 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2443077175 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:54 PM PDT 24 259586433 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2014859298 Aug 02 04:54:40 PM PDT 24 Aug 02 04:54:55 PM PDT 24 2810210044 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2042763096 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:14 PM PDT 24 992933203 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1669638084 Aug 02 04:54:39 PM PDT 24 Aug 02 04:54:51 PM PDT 24 174966696 ps
T87 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1359321245 Aug 02 04:54:30 PM PDT 24 Aug 02 04:54:47 PM PDT 24 259572694 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1448948077 Aug 02 04:54:39 PM PDT 24 Aug 02 04:57:13 PM PDT 24 374770448 ps
T88 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1531653704 Aug 02 04:54:59 PM PDT 24 Aug 02 04:55:09 PM PDT 24 260621476 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1149109174 Aug 02 04:54:44 PM PDT 24 Aug 02 04:54:58 PM PDT 24 1063553074 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1333990976 Aug 02 04:54:57 PM PDT 24 Aug 02 04:55:07 PM PDT 24 495869810 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.581235152 Aug 02 04:54:45 PM PDT 24 Aug 02 04:54:58 PM PDT 24 346227064 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2602246217 Aug 02 04:54:37 PM PDT 24 Aug 02 04:54:51 PM PDT 24 4123857271 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2969563030 Aug 02 04:54:49 PM PDT 24 Aug 02 04:55:02 PM PDT 24 264975911 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.648314100 Aug 02 04:54:42 PM PDT 24 Aug 02 04:54:53 PM PDT 24 499921381 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2977861986 Aug 02 04:54:40 PM PDT 24 Aug 02 04:54:51 PM PDT 24 1027346318 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.885102001 Aug 02 04:54:55 PM PDT 24 Aug 02 04:55:07 PM PDT 24 174543647 ps

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.909880914
Short name T1
Test name
Test status
Simulation time 3240419730 ps
CPU time 231.84 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:58:51 PM PDT 24
Peak memory 235184 kb
Host smart-724748b9-1b2c-4c61-910f-27073e74445e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909880914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.909880914
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1994946735
Short name T12
Test name
Test status
Simulation time 151825919641 ps
CPU time 2972.43 seconds
Started Aug 02 04:55:16 PM PDT 24
Finished Aug 02 05:44:49 PM PDT 24
Peak memory 250420 kb
Host smart-b7ac0006-64b9-45ad-bc3a-b905eba52543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994946735 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1994946735
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3667228169
Short name T44
Test name
Test status
Simulation time 756734922 ps
CPU time 23.79 seconds
Started Aug 02 04:55:41 PM PDT 24
Finished Aug 02 04:56:05 PM PDT 24
Peak memory 220028 kb
Host smart-d6c34a42-5aa4-4168-8f79-91631f01e748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667228169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3667228169
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1626222055
Short name T4
Test name
Test status
Simulation time 11205462252 ps
CPU time 238.76 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:59:39 PM PDT 24
Peak memory 228760 kb
Host smart-0130ee4a-568f-4192-b043-62e4592824c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626222055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1626222055
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2679919874
Short name T58
Test name
Test status
Simulation time 523799503 ps
CPU time 86.54 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 218984 kb
Host smart-f1a49486-f20b-4775-8b74-1acdfb18d5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679919874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2679919874
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3955795220
Short name T117
Test name
Test status
Simulation time 2118929657 ps
CPU time 33.66 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:33 PM PDT 24
Peak memory 219320 kb
Host smart-8938a715-3b72-4bdd-ad48-9892ed1c3968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955795220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3955795220
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.14703451
Short name T21
Test name
Test status
Simulation time 667376857 ps
CPU time 117.2 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 239820 kb
Host smart-9b20d08e-2d3d-49aa-b933-0a0cbc4b1fc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14703451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.14703451
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1116621265
Short name T76
Test name
Test status
Simulation time 7259810308 ps
CPU time 43.62 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:55:36 PM PDT 24
Peak memory 219088 kb
Host smart-b01bf282-558b-4202-a3bb-a56b8b7bba6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116621265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1116621265
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3976932145
Short name T113
Test name
Test status
Simulation time 1430931924 ps
CPU time 156.25 seconds
Started Aug 02 04:54:51 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 214196 kb
Host smart-d0bab9bb-340e-426f-a8ca-137a14ca5a06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976932145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3976932145
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.34484843
Short name T13
Test name
Test status
Simulation time 424788122510 ps
CPU time 4671.88 seconds
Started Aug 02 04:55:30 PM PDT 24
Finished Aug 02 06:13:23 PM PDT 24
Peak memory 255132 kb
Host smart-81085228-6adc-49e9-87d8-afba04e9ac53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34484843 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.34484843
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2685562522
Short name T10
Test name
Test status
Simulation time 990830012 ps
CPU time 10.15 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 219060 kb
Host smart-b5eb5cb8-af98-4bd7-b633-52ff70471519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685562522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2685562522
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3464022652
Short name T109
Test name
Test status
Simulation time 881029787 ps
CPU time 77.42 seconds
Started Aug 02 04:54:51 PM PDT 24
Finished Aug 02 04:56:09 PM PDT 24
Peak memory 213972 kb
Host smart-c0066b13-ac7e-428f-8f47-feb3cafffc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464022652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3464022652
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2600551205
Short name T28
Test name
Test status
Simulation time 1414934781 ps
CPU time 22.52 seconds
Started Aug 02 04:54:54 PM PDT 24
Finished Aug 02 04:55:17 PM PDT 24
Peak memory 220052 kb
Host smart-3b7eaecd-8d88-46a8-82a6-fbff9a397540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600551205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2600551205
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.739311643
Short name T6
Test name
Test status
Simulation time 7627962969 ps
CPU time 17.34 seconds
Started Aug 02 04:55:02 PM PDT 24
Finished Aug 02 04:55:19 PM PDT 24
Peak memory 220172 kb
Host smart-6fe592f6-f92e-4405-a005-35008a2943c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739311643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.739311643
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.946165177
Short name T103
Test name
Test status
Simulation time 4086389005 ps
CPU time 56.05 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 212080 kb
Host smart-05085c15-5813-4567-8485-1599effb640c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946165177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.946165177
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4120429603
Short name T71
Test name
Test status
Simulation time 1018215541 ps
CPU time 43.61 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 219084 kb
Host smart-434f0ae5-200f-4adc-b766-06b5ec1be5a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120429603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4120429603
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3207687196
Short name T133
Test name
Test status
Simulation time 4894747299 ps
CPU time 268.21 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:59:48 PM PDT 24
Peak memory 219456 kb
Host smart-94c6cff3-43e8-456b-879d-e3265f685478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207687196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3207687196
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.518031924
Short name T341
Test name
Test status
Simulation time 688065315 ps
CPU time 8.26 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 211140 kb
Host smart-48043332-287d-4c94-bb85-fe33aa7fa486
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518031924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.518031924
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.126433929
Short name T365
Test name
Test status
Simulation time 255598870 ps
CPU time 10.38 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:40 PM PDT 24
Peak memory 210848 kb
Host smart-676c8dd9-d236-4730-8c51-047056157086
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126433929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.126433929
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3648093843
Short name T82
Test name
Test status
Simulation time 503049947 ps
CPU time 17.05 seconds
Started Aug 02 04:54:31 PM PDT 24
Finished Aug 02 04:54:48 PM PDT 24
Peak memory 212416 kb
Host smart-d8e7a1cd-bc9d-43ac-b03a-bf9b14d9ed82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648093843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3648093843
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1495234639
Short name T380
Test name
Test status
Simulation time 205456707 ps
CPU time 9.94 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:39 PM PDT 24
Peak memory 217760 kb
Host smart-6408ab8e-bd11-4639-bdde-22cf3d1629af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495234639 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1495234639
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.463458451
Short name T74
Test name
Test status
Simulation time 332833156 ps
CPU time 8.22 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 211056 kb
Host smart-6fb6bb65-7057-4b48-aee1-f3a4e1c6f71c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463458451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.463458451
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1932700105
Short name T354
Test name
Test status
Simulation time 176826818 ps
CPU time 8.07 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 210616 kb
Host smart-895f01d5-634c-42c2-b7b1-2287b4462a87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932700105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1932700105
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1627160578
Short name T336
Test name
Test status
Simulation time 174531531 ps
CPU time 8.24 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 210692 kb
Host smart-2183f71e-4a2e-428e-ae09-876e8b5f3599
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627160578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1627160578
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3345799546
Short name T358
Test name
Test status
Simulation time 3538331003 ps
CPU time 9.99 seconds
Started Aug 02 04:54:35 PM PDT 24
Finished Aug 02 04:54:46 PM PDT 24
Peak memory 211512 kb
Host smart-139a543e-f281-4cea-9009-0731dc54f985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345799546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3345799546
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2248190427
Short name T331
Test name
Test status
Simulation time 1020379715 ps
CPU time 17.98 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:46 PM PDT 24
Peak memory 218616 kb
Host smart-ae8ec2d0-babf-470f-8e6b-3ec745fa63c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248190427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2248190427
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.221463789
Short name T115
Test name
Test status
Simulation time 1368291988 ps
CPU time 80.94 seconds
Started Aug 02 04:54:33 PM PDT 24
Finished Aug 02 04:55:54 PM PDT 24
Peak memory 213928 kb
Host smart-fe3c061f-55b9-44f5-b61f-d489a8f8e3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221463789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.221463789
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.531002133
Short name T75
Test name
Test status
Simulation time 773047653 ps
CPU time 9.82 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:44 PM PDT 24
Peak memory 211076 kb
Host smart-a4299934-dfb3-4b5e-b343-00321c88d1a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531002133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.531002133
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1545319341
Short name T353
Test name
Test status
Simulation time 256007240 ps
CPU time 10.29 seconds
Started Aug 02 04:54:37 PM PDT 24
Finished Aug 02 04:54:47 PM PDT 24
Peak memory 210584 kb
Host smart-27e787d2-d05c-4c49-9532-e552df9581ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545319341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1545319341
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1359321245
Short name T87
Test name
Test status
Simulation time 259572694 ps
CPU time 17.26 seconds
Started Aug 02 04:54:30 PM PDT 24
Finished Aug 02 04:54:47 PM PDT 24
Peak memory 211028 kb
Host smart-4f2a390e-9877-454f-80ff-407dbc0ccce7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359321245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1359321245
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1079878730
Short name T384
Test name
Test status
Simulation time 261299144 ps
CPU time 10.83 seconds
Started Aug 02 04:54:43 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 217044 kb
Host smart-7cf744e8-ba69-4f99-be5b-65480780ce7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079878730 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1079878730
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3769083310
Short name T94
Test name
Test status
Simulation time 661474786 ps
CPU time 8.05 seconds
Started Aug 02 04:54:33 PM PDT 24
Finished Aug 02 04:54:41 PM PDT 24
Peak memory 210860 kb
Host smart-ff90dd1b-273e-45d0-825c-7899a768438c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769083310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3769083310
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3767698368
Short name T344
Test name
Test status
Simulation time 346993498 ps
CPU time 8.1 seconds
Started Aug 02 04:54:33 PM PDT 24
Finished Aug 02 04:54:41 PM PDT 24
Peak memory 210788 kb
Host smart-b8c5ad65-e836-43b3-b345-8aab70e20892
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767698368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3767698368
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3083290385
Short name T390
Test name
Test status
Simulation time 753480917 ps
CPU time 8.13 seconds
Started Aug 02 04:54:42 PM PDT 24
Finished Aug 02 04:54:51 PM PDT 24
Peak memory 210760 kb
Host smart-c2ccbee3-8bc6-4372-a3ff-e0c27a886813
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083290385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3083290385
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.628263166
Short name T92
Test name
Test status
Simulation time 226298273 ps
CPU time 8.36 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 211624 kb
Host smart-16c18ad0-e724-4a5b-a12c-87e07e86f351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628263166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.628263166
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1314087280
Short name T338
Test name
Test status
Simulation time 914679358 ps
CPU time 12.87 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:47 PM PDT 24
Peak memory 217432 kb
Host smart-e6b9f463-7f7d-43a5-9668-0c410385ec0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314087280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1314087280
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4258853998
Short name T114
Test name
Test status
Simulation time 5520036817 ps
CPU time 153.96 seconds
Started Aug 02 04:54:37 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 214552 kb
Host smart-5b3b7d96-660b-46f1-86e6-46c298df0dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258853998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4258853998
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.297492878
Short name T376
Test name
Test status
Simulation time 271586887 ps
CPU time 10.76 seconds
Started Aug 02 04:54:46 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 216776 kb
Host smart-2121d20b-e525-485a-989d-14c187e9b16b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297492878 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.297492878
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2250206365
Short name T86
Test name
Test status
Simulation time 323108675 ps
CPU time 9.92 seconds
Started Aug 02 04:54:46 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 211008 kb
Host smart-72f58143-70a1-4774-aabd-a08ac4980ba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250206365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2250206365
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.269544222
Short name T373
Test name
Test status
Simulation time 1029326208 ps
CPU time 9.7 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 211764 kb
Host smart-dd75a9f4-c256-4d5d-8cee-fd3358d43d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269544222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.269544222
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1977468303
Short name T395
Test name
Test status
Simulation time 338894791 ps
CPU time 10.9 seconds
Started Aug 02 04:54:51 PM PDT 24
Finished Aug 02 04:55:02 PM PDT 24
Peak memory 217228 kb
Host smart-3a1b80e4-3dce-4777-bc17-9a9637f7c334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977468303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1977468303
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1872757204
Short name T392
Test name
Test status
Simulation time 1213620504 ps
CPU time 87.73 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 215092 kb
Host smart-eb806f23-c457-4511-8dc9-6e1e1e4ec830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872757204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1872757204
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.718679448
Short name T328
Test name
Test status
Simulation time 378925831 ps
CPU time 10.87 seconds
Started Aug 02 04:54:48 PM PDT 24
Finished Aug 02 04:54:59 PM PDT 24
Peak memory 218540 kb
Host smart-f3d3ae87-78f3-41e0-8fd0-f328f3bd4c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718679448 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.718679448
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1127285864
Short name T67
Test name
Test status
Simulation time 1454646242 ps
CPU time 9.94 seconds
Started Aug 02 04:54:49 PM PDT 24
Finished Aug 02 04:54:59 PM PDT 24
Peak memory 210880 kb
Host smart-72277f9d-49c8-43b1-85ba-756168fa59ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127285864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1127285864
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4023864843
Short name T95
Test name
Test status
Simulation time 171127656 ps
CPU time 8.14 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 211568 kb
Host smart-15192e76-09f3-48eb-be48-710e69291294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023864843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4023864843
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3728296748
Short name T342
Test name
Test status
Simulation time 174615538 ps
CPU time 11.88 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 219136 kb
Host smart-6b93abf2-9638-4c21-8b23-d7004edc9569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728296748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3728296748
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2102698249
Short name T112
Test name
Test status
Simulation time 427535593 ps
CPU time 154.64 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 218972 kb
Host smart-edd56d73-d55b-416c-b745-a5eecac03680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102698249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2102698249
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1265883260
Short name T383
Test name
Test status
Simulation time 1033727357 ps
CPU time 10.15 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 216296 kb
Host smart-a3b8a8ed-d646-418e-90a6-f71e4cc4f89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265883260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1265883260
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1531653704
Short name T88
Test name
Test status
Simulation time 260621476 ps
CPU time 9.54 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 211024 kb
Host smart-baeee1ad-6e95-4975-92d9-db40e3db08f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531653704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1531653704
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2259267595
Short name T381
Test name
Test status
Simulation time 178510794 ps
CPU time 11.45 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 212632 kb
Host smart-1e5b89df-2a04-4563-87ed-4c5ded5bf295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259267595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2259267595
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1192343789
Short name T350
Test name
Test status
Simulation time 506451424 ps
CPU time 12.53 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 217604 kb
Host smart-0fc71f55-d1d8-426e-bd24-0783ae45f433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192343789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1192343789
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3803115509
Short name T110
Test name
Test status
Simulation time 754851664 ps
CPU time 152.83 seconds
Started Aug 02 04:54:49 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 214184 kb
Host smart-a20dc403-4f0e-4bb2-b9ab-429cc938cba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803115509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3803115509
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3415780638
Short name T356
Test name
Test status
Simulation time 178512570 ps
CPU time 9.35 seconds
Started Aug 02 04:54:54 PM PDT 24
Finished Aug 02 04:55:04 PM PDT 24
Peak memory 217828 kb
Host smart-00b5a7ae-6168-48f7-82af-2e1136da02d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415780638 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3415780638
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1333990976
Short name T404
Test name
Test status
Simulation time 495869810 ps
CPU time 9.65 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 210664 kb
Host smart-64ff5baa-0397-4267-aef5-4259d94f02ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333990976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1333990976
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3597942690
Short name T388
Test name
Test status
Simulation time 359100549 ps
CPU time 12.26 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 212672 kb
Host smart-8b1e7142-2d5f-4417-a24c-f0ce2b483698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597942690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3597942690
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.488450132
Short name T345
Test name
Test status
Simulation time 378307492 ps
CPU time 11.64 seconds
Started Aug 02 04:54:50 PM PDT 24
Finished Aug 02 04:55:02 PM PDT 24
Peak memory 219096 kb
Host smart-b4908931-4309-4f78-96cf-67b1349684bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488450132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.488450132
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.548699205
Short name T355
Test name
Test status
Simulation time 1162880476 ps
CPU time 150.21 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 213232 kb
Host smart-64fdabbb-7b3c-4126-90fc-cb6890ff24dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548699205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.548699205
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.243840606
Short name T394
Test name
Test status
Simulation time 362900061 ps
CPU time 8.71 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 217136 kb
Host smart-3f979c37-3bf5-4131-bb08-421568a8038c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243840606 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.243840606
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3273007935
Short name T386
Test name
Test status
Simulation time 174156034 ps
CPU time 8.01 seconds
Started Aug 02 04:54:48 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 210848 kb
Host smart-28ad5b60-6e79-4cda-9814-05f7627feeb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273007935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3273007935
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2190474554
Short name T396
Test name
Test status
Simulation time 1031059339 ps
CPU time 14.55 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:13 PM PDT 24
Peak memory 211552 kb
Host smart-7b6cb999-f73d-492b-8cb0-9de057c995bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190474554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2190474554
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.581235152
Short name T405
Test name
Test status
Simulation time 346227064 ps
CPU time 12.64 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:58 PM PDT 24
Peak memory 217652 kb
Host smart-18b0882f-49af-436f-a6a9-70e29d28372e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581235152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.581235152
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.932073865
Short name T60
Test name
Test status
Simulation time 363795352 ps
CPU time 81.17 seconds
Started Aug 02 04:54:48 PM PDT 24
Finished Aug 02 04:56:09 PM PDT 24
Peak memory 213684 kb
Host smart-bd084ed6-5937-4a90-ac3a-18024992d184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932073865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.932073865
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.312964643
Short name T337
Test name
Test status
Simulation time 345328169 ps
CPU time 8.7 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 216276 kb
Host smart-ea1705c5-25bb-4a46-9c52-9805ebadbeb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312964643 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.312964643
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2787539942
Short name T371
Test name
Test status
Simulation time 1033243380 ps
CPU time 9.84 seconds
Started Aug 02 04:54:55 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 211004 kb
Host smart-7aac2987-33dc-4c4a-96a6-1719ae9aeae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787539942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2787539942
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2969563030
Short name T407
Test name
Test status
Simulation time 264975911 ps
CPU time 13.8 seconds
Started Aug 02 04:54:49 PM PDT 24
Finished Aug 02 04:55:02 PM PDT 24
Peak memory 212608 kb
Host smart-82c02763-613d-41c3-a705-0f4ce125f4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969563030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2969563030
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.34931016
Short name T340
Test name
Test status
Simulation time 339438503 ps
CPU time 12.46 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:13 PM PDT 24
Peak memory 219060 kb
Host smart-16504c38-be98-4f10-be65-168a1c82c11d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.34931016
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3256728416
Short name T62
Test name
Test status
Simulation time 643125439 ps
CPU time 8.7 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:08 PM PDT 24
Peak memory 217000 kb
Host smart-38c15b0e-2437-41e4-b6e5-52675a7a7a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256728416 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3256728416
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1181187253
Short name T389
Test name
Test status
Simulation time 519415840 ps
CPU time 10.07 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 210848 kb
Host smart-ae27043b-48ba-4aab-b37d-26d6b3bce60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181187253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1181187253
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.653135109
Short name T90
Test name
Test status
Simulation time 1825986463 ps
CPU time 13.87 seconds
Started Aug 02 04:54:50 PM PDT 24
Finished Aug 02 04:55:04 PM PDT 24
Peak memory 211772 kb
Host smart-f6c3d106-c674-43c3-a524-278c561fa57c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653135109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.653135109
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1167343788
Short name T362
Test name
Test status
Simulation time 332768133 ps
CPU time 11.2 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:54:58 PM PDT 24
Peak memory 216172 kb
Host smart-562a7107-5311-48a3-8198-613d75409ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167343788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1167343788
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1268715391
Short name T375
Test name
Test status
Simulation time 488685919 ps
CPU time 80.67 seconds
Started Aug 02 04:54:46 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 214052 kb
Host smart-9cb62fd4-3001-4651-8800-7ac8a97a50d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268715391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1268715391
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.454462978
Short name T347
Test name
Test status
Simulation time 975878102 ps
CPU time 10.7 seconds
Started Aug 02 04:54:53 PM PDT 24
Finished Aug 02 04:55:03 PM PDT 24
Peak memory 216828 kb
Host smart-7930b3c7-a61b-4c5f-8549-790003e3e713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454462978 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.454462978
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1101531922
Short name T368
Test name
Test status
Simulation time 1121542937 ps
CPU time 9.6 seconds
Started Aug 02 04:54:53 PM PDT 24
Finished Aug 02 04:55:02 PM PDT 24
Peak memory 211076 kb
Host smart-b91a73df-2ac0-45f2-8d1e-6f4acd77b036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101531922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1101531922
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4044443769
Short name T96
Test name
Test status
Simulation time 174706965 ps
CPU time 8.12 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:55:00 PM PDT 24
Peak memory 211368 kb
Host smart-aa5e7436-9838-4099-908b-d9e2e452b210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044443769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4044443769
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1974362127
Short name T326
Test name
Test status
Simulation time 228115626 ps
CPU time 12.36 seconds
Started Aug 02 04:54:54 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 217640 kb
Host smart-cdfd21b1-7e0d-4537-8fd2-10a7e5784aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974362127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1974362127
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3152751049
Short name T107
Test name
Test status
Simulation time 1328194875 ps
CPU time 81.93 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 214732 kb
Host smart-9956e9d6-2706-4aac-aeb3-897483941fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152751049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3152751049
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2873096584
Short name T370
Test name
Test status
Simulation time 1099629042 ps
CPU time 10.77 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 217408 kb
Host smart-87025f88-5640-4cf0-b5f6-aab935dbe288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873096584 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2873096584
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1419956126
Short name T93
Test name
Test status
Simulation time 259762050 ps
CPU time 10.24 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 211260 kb
Host smart-5807af19-750b-4fd5-9c32-865b638dcd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419956126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1419956126
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2953324312
Short name T363
Test name
Test status
Simulation time 525463850 ps
CPU time 14.11 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 212692 kb
Host smart-396772ed-f5c5-4293-a8b8-b8f338bb0d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953324312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2953324312
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.83326087
Short name T369
Test name
Test status
Simulation time 1365835414 ps
CPU time 14.86 seconds
Started Aug 02 04:55:02 PM PDT 24
Finished Aug 02 04:55:17 PM PDT 24
Peak memory 219072 kb
Host smart-7c0600c1-625c-4d5f-8059-0e3d37c324ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83326087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.83326087
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4122659085
Short name T59
Test name
Test status
Simulation time 1272477754 ps
CPU time 150.95 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:57:29 PM PDT 24
Peak memory 213332 kb
Host smart-455341c1-5786-4cb4-ad88-df28e9e2b298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122659085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4122659085
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.37165723
Short name T372
Test name
Test status
Simulation time 741466332 ps
CPU time 9.52 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 218104 kb
Host smart-9e4851e9-769a-4e30-b0a0-06fa05482389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37165723 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.37165723
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3569782390
Short name T84
Test name
Test status
Simulation time 174510186 ps
CPU time 8.17 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 211088 kb
Host smart-1117d068-6d7e-4ba1-85e7-b8d25316e716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569782390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3569782390
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.293249511
Short name T351
Test name
Test status
Simulation time 6156485666 ps
CPU time 14.53 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 211884 kb
Host smart-f172959d-5ce2-4cf2-a531-ba45da5d4b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293249511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.293249511
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.885102001
Short name T410
Test name
Test status
Simulation time 174543647 ps
CPU time 11.37 seconds
Started Aug 02 04:54:55 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 219140 kb
Host smart-6b0f638a-685f-4a9a-8216-89536adb041c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885102001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.885102001
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2198047365
Short name T352
Test name
Test status
Simulation time 988268046 ps
CPU time 9.94 seconds
Started Aug 02 04:54:42 PM PDT 24
Finished Aug 02 04:54:52 PM PDT 24
Peak memory 211320 kb
Host smart-7200ec84-c5ee-4045-b3dd-6cb4f00bf239
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198047365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2198047365
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2602246217
Short name T406
Test name
Test status
Simulation time 4123857271 ps
CPU time 14.49 seconds
Started Aug 02 04:54:37 PM PDT 24
Finished Aug 02 04:54:51 PM PDT 24
Peak memory 210884 kb
Host smart-68bd2d8a-44ca-4366-a037-950a0f62260b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602246217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2602246217
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.696400555
Short name T70
Test name
Test status
Simulation time 666547080 ps
CPU time 11.73 seconds
Started Aug 02 04:54:37 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 210972 kb
Host smart-6d6c8cd7-f54f-4133-b322-96df94901834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696400555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.696400555
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1015966909
Short name T339
Test name
Test status
Simulation time 2946108423 ps
CPU time 8.91 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:48 PM PDT 24
Peak memory 216608 kb
Host smart-bae22d0f-2a31-49a4-98d2-aa272313d2ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015966909 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1015966909
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4106683088
Short name T68
Test name
Test status
Simulation time 2058728274 ps
CPU time 8.25 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:53 PM PDT 24
Peak memory 211020 kb
Host smart-4e3bbf4e-8ff6-4ccb-9b47-6c09214fa411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106683088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4106683088
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3638474515
Short name T382
Test name
Test status
Simulation time 190794067 ps
CPU time 8.28 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:53 PM PDT 24
Peak memory 210624 kb
Host smart-414bef18-26e9-461c-8852-a5018d301e82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638474515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3638474515
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1338379657
Short name T329
Test name
Test status
Simulation time 256947856 ps
CPU time 9.96 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 210788 kb
Host smart-241b00ef-69f3-4887-b16e-7a384170610b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338379657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1338379657
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1789201998
Short name T73
Test name
Test status
Simulation time 4922633355 ps
CPU time 56.27 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 219160 kb
Host smart-d24a7e09-5527-42e0-a789-b640a21fc02a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789201998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1789201998
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2977861986
Short name T409
Test name
Test status
Simulation time 1027346318 ps
CPU time 10.01 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:54:51 PM PDT 24
Peak memory 211344 kb
Host smart-728cc9cb-84cd-44f3-890e-c53e5c4d8fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977861986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2977861986
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.182036295
Short name T361
Test name
Test status
Simulation time 2756920038 ps
CPU time 14.28 seconds
Started Aug 02 04:54:38 PM PDT 24
Finished Aug 02 04:54:52 PM PDT 24
Peak memory 217840 kb
Host smart-8e739f01-8bb5-495f-b02f-a34da1fd541c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182036295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.182036295
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3800220966
Short name T116
Test name
Test status
Simulation time 510612858 ps
CPU time 156.48 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 214372 kb
Host smart-63941fb6-3135-4267-8716-8cf9b62344d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800220966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3800220966
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1508478285
Short name T72
Test name
Test status
Simulation time 2470995602 ps
CPU time 9.7 seconds
Started Aug 02 04:54:36 PM PDT 24
Finished Aug 02 04:54:46 PM PDT 24
Peak memory 210856 kb
Host smart-fc21e734-36b3-4e1b-b150-90ae08b9c3b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508478285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1508478285
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2919928138
Short name T97
Test name
Test status
Simulation time 252141880 ps
CPU time 10.68 seconds
Started Aug 02 04:54:38 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 211184 kb
Host smart-e332e10e-f5da-48f6-8eae-980061d8c84d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919928138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2919928138
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2040033492
Short name T357
Test name
Test status
Simulation time 421767718 ps
CPU time 15.14 seconds
Started Aug 02 04:54:38 PM PDT 24
Finished Aug 02 04:54:53 PM PDT 24
Peak memory 212444 kb
Host smart-3a2379b6-021f-4f0a-a488-4d7525f3f4a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040033492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2040033492
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.648314100
Short name T408
Test name
Test status
Simulation time 499921381 ps
CPU time 10.28 seconds
Started Aug 02 04:54:42 PM PDT 24
Finished Aug 02 04:54:53 PM PDT 24
Peak memory 214908 kb
Host smart-23666dd0-6ea3-4aa4-860a-7df7c3757d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648314100 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.648314100
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1587323248
Short name T367
Test name
Test status
Simulation time 251213943 ps
CPU time 9.87 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 210792 kb
Host smart-b436eaff-d156-4fe1-9722-df02aa99c26e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587323248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1587323248
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.611948002
Short name T378
Test name
Test status
Simulation time 174809909 ps
CPU time 8.03 seconds
Started Aug 02 04:54:41 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 210808 kb
Host smart-0672fd37-0cad-44fb-a457-54370f9e5a64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611948002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.611948002
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.368496698
Short name T348
Test name
Test status
Simulation time 505089553 ps
CPU time 9.46 seconds
Started Aug 02 04:54:38 PM PDT 24
Finished Aug 02 04:54:48 PM PDT 24
Peak memory 210776 kb
Host smart-95805ce6-667c-401d-9d11-ef3e86c3dc31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368496698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
368496698
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3102314474
Short name T397
Test name
Test status
Simulation time 332669611 ps
CPU time 8.14 seconds
Started Aug 02 04:54:43 PM PDT 24
Finished Aug 02 04:54:51 PM PDT 24
Peak memory 211476 kb
Host smart-4459e7e0-a48c-42eb-90c2-72acb4c0e6e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102314474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3102314474
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1669638084
Short name T401
Test name
Test status
Simulation time 174966696 ps
CPU time 12 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:51 PM PDT 24
Peak memory 218736 kb
Host smart-d23b97b5-5937-4e6c-88b0-d7cf1941997b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669638084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1669638084
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1723906757
Short name T104
Test name
Test status
Simulation time 1022426722 ps
CPU time 80.63 seconds
Started Aug 02 04:54:38 PM PDT 24
Finished Aug 02 04:55:59 PM PDT 24
Peak memory 212976 kb
Host smart-c6117d7a-d373-4eb3-90f0-f2bd9e86af7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723906757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1723906757
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.517345377
Short name T69
Test name
Test status
Simulation time 252421624 ps
CPU time 9.92 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 210808 kb
Host smart-2aab6d75-034f-4236-af17-f60c00bdf567
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517345377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.517345377
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1927519173
Short name T377
Test name
Test status
Simulation time 172511808 ps
CPU time 8.47 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 211020 kb
Host smart-db7fb803-8d80-4988-8036-ee0740769146
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927519173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1927519173
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2363024683
Short name T85
Test name
Test status
Simulation time 1473720902 ps
CPU time 16.67 seconds
Started Aug 02 04:54:41 PM PDT 24
Finished Aug 02 04:54:58 PM PDT 24
Peak memory 212356 kb
Host smart-0ef445a4-e75d-46c7-8cb6-bb96dbdbf50d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363024683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2363024683
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3427970283
Short name T359
Test name
Test status
Simulation time 264076646 ps
CPU time 10.87 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:50 PM PDT 24
Peak memory 217052 kb
Host smart-f18def08-30a1-43e0-94b4-ede7e8d2a30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427970283 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3427970283
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3295992031
Short name T89
Test name
Test status
Simulation time 612313610 ps
CPU time 8.17 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 211452 kb
Host smart-fa4a50b8-1d0d-4484-a470-1dda9ea5dee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295992031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3295992031
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2106014759
Short name T343
Test name
Test status
Simulation time 587790526 ps
CPU time 9.95 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:54:49 PM PDT 24
Peak memory 210692 kb
Host smart-264766e8-e516-481c-b9bd-a746338edb03
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106014759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2106014759
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2443077175
Short name T398
Test name
Test status
Simulation time 259586433 ps
CPU time 9.75 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 210584 kb
Host smart-346e2411-a1ed-43cf-b82e-9fbf173443d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443077175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2443077175
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2014859298
Short name T399
Test name
Test status
Simulation time 2810210044 ps
CPU time 14.8 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:54:55 PM PDT 24
Peak memory 211276 kb
Host smart-7e7a3645-ee2f-4ffc-8634-737552e90956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014859298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2014859298
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4233082992
Short name T387
Test name
Test status
Simulation time 789664537 ps
CPU time 11.52 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:54:52 PM PDT 24
Peak memory 217312 kb
Host smart-8e40baf3-1234-49ba-a353-cd1877b7cc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233082992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4233082992
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1448948077
Short name T402
Test name
Test status
Simulation time 374770448 ps
CPU time 154.21 seconds
Started Aug 02 04:54:39 PM PDT 24
Finished Aug 02 04:57:13 PM PDT 24
Peak memory 214308 kb
Host smart-123b3d09-a637-4557-b738-e89930900010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448948077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1448948077
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2445720603
Short name T346
Test name
Test status
Simulation time 1041376171 ps
CPU time 9.92 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:55 PM PDT 24
Peak memory 214704 kb
Host smart-3ed936f0-992a-4abb-bff2-ff0dc07ebfd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445720603 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2445720603
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1881374420
Short name T83
Test name
Test status
Simulation time 477948159 ps
CPU time 9.74 seconds
Started Aug 02 04:54:37 PM PDT 24
Finished Aug 02 04:54:47 PM PDT 24
Peak memory 211112 kb
Host smart-916ee39f-64a5-47e9-97a5-42dbd61c7544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881374420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1881374420
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2612137418
Short name T385
Test name
Test status
Simulation time 1068049496 ps
CPU time 13.85 seconds
Started Aug 02 04:54:43 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 212912 kb
Host smart-859fadbe-d6ad-43b4-9e74-0a62c176b9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612137418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2612137418
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2304927651
Short name T360
Test name
Test status
Simulation time 917079515 ps
CPU time 13.52 seconds
Started Aug 02 04:54:43 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 217692 kb
Host smart-3774979b-5ce2-4d69-b440-45fc40015459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304927651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2304927651
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.531156495
Short name T106
Test name
Test status
Simulation time 1120562082 ps
CPU time 154.69 seconds
Started Aug 02 04:54:40 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 214608 kb
Host smart-cbff0889-9add-4429-a307-196c86f2f924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531156495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.531156495
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.438937142
Short name T330
Test name
Test status
Simulation time 1099105674 ps
CPU time 8.56 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 216324 kb
Host smart-2dc34242-b13b-4aaa-af48-1b7923ec39e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438937142 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.438937142
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3932130578
Short name T364
Test name
Test status
Simulation time 262260081 ps
CPU time 9.88 seconds
Started Aug 02 04:54:48 PM PDT 24
Finished Aug 02 04:54:58 PM PDT 24
Peak memory 211020 kb
Host smart-8f926de9-e292-4e3c-8168-9e97a254f73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932130578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3932130578
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.384554658
Short name T366
Test name
Test status
Simulation time 2362992393 ps
CPU time 7.91 seconds
Started Aug 02 04:55:04 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 211632 kb
Host smart-63faa68d-e10c-47b2-9605-c720351205cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384554658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.384554658
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.873510775
Short name T334
Test name
Test status
Simulation time 174899827 ps
CPU time 11.08 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:55 PM PDT 24
Peak memory 219032 kb
Host smart-fcd3779e-a4a6-431a-9ff8-ea5fa13dae19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873510775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.873510775
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.754445040
Short name T108
Test name
Test status
Simulation time 1287733267 ps
CPU time 153.33 seconds
Started Aug 02 04:54:47 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 214520 kb
Host smart-bdf541d1-d35b-4776-8295-3bbaaa36a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754445040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.754445040
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4114344083
Short name T349
Test name
Test status
Simulation time 796062747 ps
CPU time 9.67 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 214996 kb
Host smart-704f30ce-dcb0-4340-9045-928d93402b6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114344083 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4114344083
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2922657463
Short name T91
Test name
Test status
Simulation time 2407705139 ps
CPU time 14.4 seconds
Started Aug 02 04:54:49 PM PDT 24
Finished Aug 02 04:55:03 PM PDT 24
Peak memory 211820 kb
Host smart-3ff26e8f-9f7a-42f9-82f5-51cc17b575a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922657463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2922657463
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.815748513
Short name T379
Test name
Test status
Simulation time 249548639 ps
CPU time 9.92 seconds
Started Aug 02 04:54:46 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 211372 kb
Host smart-a423aa0b-f17b-4ce0-9d2a-d9bfd58f37b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815748513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.815748513
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3657490272
Short name T332
Test name
Test status
Simulation time 260166484 ps
CPU time 12.84 seconds
Started Aug 02 04:54:51 PM PDT 24
Finished Aug 02 04:55:04 PM PDT 24
Peak memory 217484 kb
Host smart-cdfb7c5e-a145-4ef9-8b2b-a901002bf63c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657490272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3657490272
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2574578699
Short name T111
Test name
Test status
Simulation time 972668099 ps
CPU time 79.93 seconds
Started Aug 02 04:54:43 PM PDT 24
Finished Aug 02 04:56:03 PM PDT 24
Peak memory 219064 kb
Host smart-39eb65a2-349a-4836-a035-cad1fcfd4f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574578699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2574578699
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3043316315
Short name T335
Test name
Test status
Simulation time 355959194 ps
CPU time 8.67 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 215372 kb
Host smart-80face45-237a-4d16-99b7-cf45c28dbfe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043316315 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3043316315
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2042763096
Short name T400
Test name
Test status
Simulation time 992933203 ps
CPU time 14.25 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:14 PM PDT 24
Peak memory 212000 kb
Host smart-59d52a99-a973-4370-b344-4696805346c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042763096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2042763096
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3691538688
Short name T63
Test name
Test status
Simulation time 1394944428 ps
CPU time 55.43 seconds
Started Aug 02 04:54:50 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 219024 kb
Host smart-714d77d8-f40c-4143-8f3f-75acf5cdead6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691538688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3691538688
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2281862842
Short name T374
Test name
Test status
Simulation time 267486312 ps
CPU time 13.28 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 212704 kb
Host smart-4ba732a1-a956-4b5c-86e9-0e6ab3ed3488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281862842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2281862842
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.50678768
Short name T333
Test name
Test status
Simulation time 987325188 ps
CPU time 13.26 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:59 PM PDT 24
Peak memory 217644 kb
Host smart-f8da7e7e-7211-4800-9eed-0f92b0b7b635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50678768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.50678768
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1117871104
Short name T393
Test name
Test status
Simulation time 2029244447 ps
CPU time 15.08 seconds
Started Aug 02 04:54:53 PM PDT 24
Finished Aug 02 04:55:08 PM PDT 24
Peak memory 216860 kb
Host smart-41ce65ec-1eee-482b-996f-dbece5d0fe5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117871104 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1117871104
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3602268997
Short name T391
Test name
Test status
Simulation time 692995179 ps
CPU time 8.34 seconds
Started Aug 02 04:54:45 PM PDT 24
Finished Aug 02 04:54:53 PM PDT 24
Peak memory 210780 kb
Host smart-a5386388-03ab-4467-97cb-2d387890ba47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602268997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3602268997
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1149109174
Short name T403
Test name
Test status
Simulation time 1063553074 ps
CPU time 13.74 seconds
Started Aug 02 04:54:44 PM PDT 24
Finished Aug 02 04:54:58 PM PDT 24
Peak memory 212896 kb
Host smart-55ba551f-8280-4a43-ae37-0cee4dff7ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149109174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1149109174
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.169602605
Short name T327
Test name
Test status
Simulation time 339173704 ps
CPU time 12.87 seconds
Started Aug 02 04:54:51 PM PDT 24
Finished Aug 02 04:55:04 PM PDT 24
Peak memory 219044 kb
Host smart-2f13b0cc-7212-4b06-9983-ecb671734cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169602605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.169602605
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1667137782
Short name T105
Test name
Test status
Simulation time 402249484 ps
CPU time 152.1 seconds
Started Aug 02 04:54:48 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 214448 kb
Host smart-91aed2bf-a892-42b3-924d-01ac6ce1019e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667137782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1667137782
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3771062307
Short name T66
Test name
Test status
Simulation time 1044792904 ps
CPU time 15.25 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 218836 kb
Host smart-8b12efb3-2ea3-4f90-8815-8931b6f9c7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771062307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3771062307
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3651394075
Short name T29
Test name
Test status
Simulation time 3266051645 ps
CPU time 154.86 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 220348 kb
Host smart-cc2a7631-449b-4117-aadd-5ec986f11337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651394075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3651394075
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.391596871
Short name T222
Test name
Test status
Simulation time 1923812720 ps
CPU time 10.69 seconds
Started Aug 02 04:54:54 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 220016 kb
Host smart-4b8e52b5-df72-42d8-a258-5611e0bde65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391596871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.391596871
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1843326053
Short name T25
Test name
Test status
Simulation time 386681463 ps
CPU time 225.96 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 239624 kb
Host smart-8767b244-7458-4640-b41a-8c235bdbc939
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843326053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1843326053
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.666723065
Short name T250
Test name
Test status
Simulation time 1067245068 ps
CPU time 12.56 seconds
Started Aug 02 04:55:02 PM PDT 24
Finished Aug 02 04:55:15 PM PDT 24
Peak memory 219928 kb
Host smart-b9619a87-2caa-421a-a086-09373cc419cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666723065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.666723065
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3886478561
Short name T224
Test name
Test status
Simulation time 1973333160 ps
CPU time 31.19 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:28 PM PDT 24
Peak memory 219972 kb
Host smart-1cc4b22d-13d0-449e-a565-d1f349f9388e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886478561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3886478561
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.557119812
Short name T242
Test name
Test status
Simulation time 7791183798 ps
CPU time 272.82 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:59:31 PM PDT 24
Peak memory 241184 kb
Host smart-1c1a0882-d999-4c01-b9f3-d06f82fba67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557119812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.557119812
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2018781203
Short name T145
Test name
Test status
Simulation time 346663389 ps
CPU time 19.47 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:19 PM PDT 24
Peak memory 220040 kb
Host smart-d7ed33cd-bdc2-46e9-bb7a-c472ce0acc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018781203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2018781203
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2152839907
Short name T142
Test name
Test status
Simulation time 353139855 ps
CPU time 10.14 seconds
Started Aug 02 04:54:55 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 220028 kb
Host smart-f093912a-9aa3-4eb5-8bf0-fc4d03a19d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152839907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2152839907
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.999495372
Short name T228
Test name
Test status
Simulation time 387546116 ps
CPU time 12.25 seconds
Started Aug 02 04:54:53 PM PDT 24
Finished Aug 02 04:55:06 PM PDT 24
Peak memory 220100 kb
Host smart-24fc2b43-cdaf-45d7-ad39-1058824aad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999495372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.999495372
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.687247307
Short name T268
Test name
Test status
Simulation time 2070702226 ps
CPU time 29.32 seconds
Started Aug 02 04:54:55 PM PDT 24
Finished Aug 02 04:55:25 PM PDT 24
Peak memory 219912 kb
Host smart-d7e3e0e9-0f33-451d-8221-b86666bf5631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687247307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.687247307
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1013879813
Short name T65
Test name
Test status
Simulation time 254646456 ps
CPU time 10.07 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 218996 kb
Host smart-ec3fb5b5-fa9b-4279-bd84-aa7d4c4926dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013879813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1013879813
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3843465468
Short name T265
Test name
Test status
Simulation time 14858984285 ps
CPU time 212.34 seconds
Started Aug 02 04:55:03 PM PDT 24
Finished Aug 02 04:58:36 PM PDT 24
Peak memory 220312 kb
Host smart-c6bf96b6-7994-4fbb-af76-67245b120a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843465468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3843465468
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.538520919
Short name T98
Test name
Test status
Simulation time 178547207 ps
CPU time 10.48 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 220012 kb
Host smart-71c9d0bf-b7b6-493a-9ed0-32b821796576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538520919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.538520919
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4278447409
Short name T79
Test name
Test status
Simulation time 4027848419 ps
CPU time 31.06 seconds
Started Aug 02 04:55:04 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 220088 kb
Host smart-ad4beefc-ae26-46a6-8b32-7c57d6757192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278447409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4278447409
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.993249686
Short name T267
Test name
Test status
Simulation time 688067526 ps
CPU time 8.27 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 218948 kb
Host smart-2819e50d-2c38-4078-8f6e-14b46acf00cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993249686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.993249686
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.150076900
Short name T300
Test name
Test status
Simulation time 23639438281 ps
CPU time 297.49 seconds
Started Aug 02 04:55:13 PM PDT 24
Finished Aug 02 05:00:11 PM PDT 24
Peak memory 230380 kb
Host smart-26861fce-6ff1-47bf-b6d1-3288e57c4702
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150076900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.150076900
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3719621417
Short name T47
Test name
Test status
Simulation time 497877448 ps
CPU time 22.4 seconds
Started Aug 02 04:55:05 PM PDT 24
Finished Aug 02 04:55:28 PM PDT 24
Peak memory 220056 kb
Host smart-32f49262-d28f-477a-934c-ca10e2a9d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719621417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3719621417
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1015081844
Short name T129
Test name
Test status
Simulation time 692945388 ps
CPU time 10.16 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 219980 kb
Host smart-8f3e0068-9cec-445e-86a9-aeffab568652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015081844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1015081844
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2208416319
Short name T80
Test name
Test status
Simulation time 3405360258 ps
CPU time 40.01 seconds
Started Aug 02 04:55:12 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 220124 kb
Host smart-a9c4192e-6122-4716-b956-8ed1c310d98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208416319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2208416319
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1455666532
Short name T186
Test name
Test status
Simulation time 345430696 ps
CPU time 8.47 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:28 PM PDT 24
Peak memory 219072 kb
Host smart-92f11328-d0a0-4946-b221-f763e377c2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455666532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1455666532
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4120498314
Short name T150
Test name
Test status
Simulation time 5703989228 ps
CPU time 104.7 seconds
Started Aug 02 04:55:23 PM PDT 24
Finished Aug 02 04:57:07 PM PDT 24
Peak memory 242612 kb
Host smart-a7a12448-1555-41c7-a109-eb08993579f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120498314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4120498314
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3859050031
Short name T154
Test name
Test status
Simulation time 991285956 ps
CPU time 22.3 seconds
Started Aug 02 04:55:12 PM PDT 24
Finished Aug 02 04:55:34 PM PDT 24
Peak memory 220080 kb
Host smart-24e27906-55d1-4026-bb13-06f1af50c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859050031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3859050031
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1917392245
Short name T296
Test name
Test status
Simulation time 1715722513 ps
CPU time 12 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:36 PM PDT 24
Peak memory 220080 kb
Host smart-442ec868-69b5-4a6d-9d47-a7bb27acd917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917392245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1917392245
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.50213571
Short name T241
Test name
Test status
Simulation time 3575561099 ps
CPU time 40.3 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 220132 kb
Host smart-d39e81e3-eaff-4c96-ab82-2e23ef12d372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50213571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.rom_ctrl_stress_all.50213571
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3074317045
Short name T157
Test name
Test status
Simulation time 1031332536 ps
CPU time 9.88 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 218988 kb
Host smart-77f0a7e5-d228-4a7f-b844-d1b707339529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074317045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3074317045
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2358964153
Short name T275
Test name
Test status
Simulation time 991328430 ps
CPU time 22.62 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:42 PM PDT 24
Peak memory 220100 kb
Host smart-a0efa11b-7735-457b-9a3c-5d855ae7d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358964153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2358964153
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3560054012
Short name T56
Test name
Test status
Simulation time 2547825200 ps
CPU time 11.7 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 220168 kb
Host smart-204cbbb4-1efa-4df0-a19a-28ef1baddf2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560054012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3560054012
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2697215982
Short name T212
Test name
Test status
Simulation time 540610154 ps
CPU time 35.07 seconds
Started Aug 02 04:55:11 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 219944 kb
Host smart-1cca5dde-9747-4551-9744-e18fe30a2502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697215982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2697215982
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2427095535
Short name T160
Test name
Test status
Simulation time 1033834222 ps
CPU time 10.06 seconds
Started Aug 02 04:55:20 PM PDT 24
Finished Aug 02 04:55:30 PM PDT 24
Peak memory 219044 kb
Host smart-5d30dca8-3c16-4960-87c9-e1fe7cd12445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427095535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2427095535
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1392252246
Short name T238
Test name
Test status
Simulation time 21349476676 ps
CPU time 290.6 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 05:00:05 PM PDT 24
Peak memory 240128 kb
Host smart-4eae8cae-5373-47af-855f-92a97394a6e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392252246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1392252246
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4236542659
Short name T43
Test name
Test status
Simulation time 1577081083 ps
CPU time 19.89 seconds
Started Aug 02 04:55:06 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 219964 kb
Host smart-5a5d4cc0-ad44-4649-9b7c-3151f51c0790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236542659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4236542659
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2406130125
Short name T120
Test name
Test status
Simulation time 179469953 ps
CPU time 10.26 seconds
Started Aug 02 04:55:06 PM PDT 24
Finished Aug 02 04:55:17 PM PDT 24
Peak memory 219968 kb
Host smart-a81c63fb-beac-4675-976e-87885e80e12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406130125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2406130125
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3769972974
Short name T206
Test name
Test status
Simulation time 1289589551 ps
CPU time 21.33 seconds
Started Aug 02 04:55:12 PM PDT 24
Finished Aug 02 04:55:34 PM PDT 24
Peak memory 219924 kb
Host smart-9db9e08c-02b3-418a-a5b7-13c07fa2a575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769972974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3769972974
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.747284512
Short name T52
Test name
Test status
Simulation time 280378957150 ps
CPU time 2702.24 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 05:40:21 PM PDT 24
Peak memory 248968 kb
Host smart-2c463130-2808-43e1-acae-5ab5783a58c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747284512 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.747284512
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3312384139
Short name T319
Test name
Test status
Simulation time 1125696412 ps
CPU time 10 seconds
Started Aug 02 04:55:15 PM PDT 24
Finished Aug 02 04:55:25 PM PDT 24
Peak memory 218940 kb
Host smart-469bef57-0b6b-407e-8f85-e465c9a428ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312384139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3312384139
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3501053152
Short name T307
Test name
Test status
Simulation time 14335184252 ps
CPU time 213.21 seconds
Started Aug 02 04:55:20 PM PDT 24
Finished Aug 02 04:58:53 PM PDT 24
Peak memory 237772 kb
Host smart-b396b767-da77-4044-9620-6d308b73c94c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501053152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3501053152
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.856252199
Short name T301
Test name
Test status
Simulation time 973553633 ps
CPU time 19.46 seconds
Started Aug 02 04:55:09 PM PDT 24
Finished Aug 02 04:55:28 PM PDT 24
Peak memory 219948 kb
Host smart-0a0fc5af-a157-4798-8ce4-3a1ab5557019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856252199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.856252199
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2332956596
Short name T124
Test name
Test status
Simulation time 5156607248 ps
CPU time 11.97 seconds
Started Aug 02 04:55:11 PM PDT 24
Finished Aug 02 04:55:23 PM PDT 24
Peak memory 220160 kb
Host smart-579c5577-a823-4f4b-9e47-de727761f5be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332956596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2332956596
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3175786616
Short name T33
Test name
Test status
Simulation time 8402641976 ps
CPU time 36.31 seconds
Started Aug 02 04:55:12 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 220096 kb
Host smart-edb56881-5762-4a4e-8e9d-f5bcfc309823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175786616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3175786616
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1811615574
Short name T168
Test name
Test status
Simulation time 167667958 ps
CPU time 8.73 seconds
Started Aug 02 04:55:13 PM PDT 24
Finished Aug 02 04:55:22 PM PDT 24
Peak memory 219188 kb
Host smart-5a219214-3439-4f51-a08a-491296894266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811615574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1811615574
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4067272023
Short name T35
Test name
Test status
Simulation time 33443586208 ps
CPU time 323.38 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 05:00:45 PM PDT 24
Peak memory 239608 kb
Host smart-180ac8ff-8389-4264-bd5e-7244d58cf574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067272023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4067272023
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3447140756
Short name T123
Test name
Test status
Simulation time 1981984720 ps
CPU time 22.87 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 220120 kb
Host smart-e71153d6-0edb-4dda-a102-caccdf426344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447140756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3447140756
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2353958623
Short name T314
Test name
Test status
Simulation time 877751911 ps
CPU time 10.59 seconds
Started Aug 02 04:55:15 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 220088 kb
Host smart-5633d66a-7e16-4201-98d0-52377b9e3075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353958623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2353958623
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3446698708
Short name T166
Test name
Test status
Simulation time 2354717582 ps
CPU time 37.12 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 220012 kb
Host smart-1a86e28e-8db5-44e1-b49e-80931d55bc94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446698708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3446698708
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1227114233
Short name T249
Test name
Test status
Simulation time 251802770 ps
CPU time 9.88 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 04:55:24 PM PDT 24
Peak memory 219144 kb
Host smart-58ca622d-c45b-4e86-b072-be9a5500e790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227114233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1227114233
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.196463157
Short name T158
Test name
Test status
Simulation time 6163181239 ps
CPU time 260.14 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:59:37 PM PDT 24
Peak memory 239540 kb
Host smart-45f2fd59-8c5d-45a9-a9be-b862212fcefd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196463157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.196463157
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1115784916
Short name T34
Test name
Test status
Simulation time 507526873 ps
CPU time 23.05 seconds
Started Aug 02 04:55:13 PM PDT 24
Finished Aug 02 04:55:36 PM PDT 24
Peak memory 220064 kb
Host smart-74c2d1d6-4b2a-44f3-b86b-9ed2781ffb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115784916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1115784916
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2337531073
Short name T118
Test name
Test status
Simulation time 1023025820 ps
CPU time 12.03 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:33 PM PDT 24
Peak memory 220056 kb
Host smart-f50a78b6-4263-4a9e-80c1-57942bcfb417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337531073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2337531073
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2813067703
Short name T216
Test name
Test status
Simulation time 2124013136 ps
CPU time 31.85 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:49 PM PDT 24
Peak memory 220020 kb
Host smart-4d60c1fe-d6e8-4460-a3fd-62230770f8d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813067703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2813067703
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2482654479
Short name T53
Test name
Test status
Simulation time 75924505248 ps
CPU time 697 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 05:06:55 PM PDT 24
Peak memory 232832 kb
Host smart-13827ab4-a248-4eb3-923e-d3048b24b989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482654479 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2482654479
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1483368558
Short name T64
Test name
Test status
Simulation time 640440545 ps
CPU time 8.41 seconds
Started Aug 02 04:55:23 PM PDT 24
Finished Aug 02 04:55:32 PM PDT 24
Peak memory 219052 kb
Host smart-40ede244-987e-463d-8ae8-c6e392efdcfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483368558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1483368558
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.134444027
Short name T162
Test name
Test status
Simulation time 4514922428 ps
CPU time 235.54 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:59:21 PM PDT 24
Peak memory 239116 kb
Host smart-ff0e9388-5c1e-417e-a0be-3e229ee20997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134444027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.134444027
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1562079965
Short name T164
Test name
Test status
Simulation time 2472517835 ps
CPU time 23.16 seconds
Started Aug 02 04:55:07 PM PDT 24
Finished Aug 02 04:55:30 PM PDT 24
Peak memory 220148 kb
Host smart-cebbe350-bee2-4948-aa0a-7b9b28ea29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562079965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1562079965
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.450391506
Short name T232
Test name
Test status
Simulation time 257084135 ps
CPU time 11.86 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 219904 kb
Host smart-253708ba-bcd9-4048-b68a-1191432161d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450391506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.450391506
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.7626934
Short name T78
Test name
Test status
Simulation time 1544492366 ps
CPU time 42.3 seconds
Started Aug 02 04:55:05 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 219868 kb
Host smart-cfe1de1b-dc66-415a-ad0b-4016fb82cce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7626934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.rom_ctrl_stress_all.7626934
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.9101576
Short name T308
Test name
Test status
Simulation time 1032069242 ps
CPU time 10.12 seconds
Started Aug 02 04:55:08 PM PDT 24
Finished Aug 02 04:55:18 PM PDT 24
Peak memory 219184 kb
Host smart-187c2614-14b9-424d-9c4b-350175a31d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9101576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.9101576
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3942574164
Short name T201
Test name
Test status
Simulation time 7779457366 ps
CPU time 140.96 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:57:39 PM PDT 24
Peak memory 239724 kb
Host smart-fc44fb3d-576c-4b91-ad31-627c2ee6703d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942574164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3942574164
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2135968409
Short name T282
Test name
Test status
Simulation time 1269820100 ps
CPU time 19.42 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 219956 kb
Host smart-728ad5ff-42fa-48cd-b77b-de910c681ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135968409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2135968409
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2548328525
Short name T261
Test name
Test status
Simulation time 261954344 ps
CPU time 12.24 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:30 PM PDT 24
Peak memory 219984 kb
Host smart-63836ad2-13a5-41b8-9d17-6a89b5ff5811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548328525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2548328525
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3645851627
Short name T214
Test name
Test status
Simulation time 3140667396 ps
CPU time 42.2 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:56:02 PM PDT 24
Peak memory 220584 kb
Host smart-2c749711-8fab-4354-9636-145d368c6f37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645851627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3645851627
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4250627446
Short name T316
Test name
Test status
Simulation time 250394721 ps
CPU time 9.97 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:55:06 PM PDT 24
Peak memory 219004 kb
Host smart-72ab47e4-c5ba-4e82-9ac6-a949aef83c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250627446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4250627446
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1325962793
Short name T7
Test name
Test status
Simulation time 45665399476 ps
CPU time 136.07 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:57:14 PM PDT 24
Peak memory 237496 kb
Host smart-16e4e1cd-e426-4fc2-aa71-f9a05b0a7350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325962793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1325962793
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2193287029
Short name T251
Test name
Test status
Simulation time 339534888 ps
CPU time 19.49 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 219964 kb
Host smart-398a5ead-485e-4fcb-8515-eafa744db61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193287029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2193287029
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1798928542
Short name T178
Test name
Test status
Simulation time 348587627 ps
CPU time 10.36 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 219984 kb
Host smart-7a01819b-69cc-4f44-9418-623f63069e04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798928542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1798928542
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3225154
Short name T22
Test name
Test status
Simulation time 1910531450 ps
CPU time 228.9 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:58:45 PM PDT 24
Peak memory 235048 kb
Host smart-2f19a340-a936-47c6-8269-4abb21f41218
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3225154
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.985412008
Short name T55
Test name
Test status
Simulation time 1074969145 ps
CPU time 10.03 seconds
Started Aug 02 04:54:49 PM PDT 24
Finished Aug 02 04:54:59 PM PDT 24
Peak memory 219936 kb
Host smart-34304d05-5cd3-4c59-849b-9f897ef9fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985412008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.985412008
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.340022577
Short name T16
Test name
Test status
Simulation time 387950407 ps
CPU time 31.07 seconds
Started Aug 02 04:54:52 PM PDT 24
Finished Aug 02 04:55:23 PM PDT 24
Peak memory 219892 kb
Host smart-87916c2d-cb61-4fc1-bb3f-f6ea7a4c7ea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340022577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.340022577
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2634121921
Short name T57
Test name
Test status
Simulation time 178353120 ps
CPU time 8.28 seconds
Started Aug 02 04:55:14 PM PDT 24
Finished Aug 02 04:55:22 PM PDT 24
Peak memory 219172 kb
Host smart-4eb4f422-6297-4130-bb57-321a1ae3eebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634121921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2634121921
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3646925183
Short name T36
Test name
Test status
Simulation time 10743292850 ps
CPU time 219.96 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:58:59 PM PDT 24
Peak memory 242012 kb
Host smart-ce3c997b-4d50-4a90-a22e-e6a19a504918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646925183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3646925183
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.86205372
Short name T171
Test name
Test status
Simulation time 1980705836 ps
CPU time 22.63 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:43 PM PDT 24
Peak memory 220040 kb
Host smart-13750b1b-e860-4d3c-b1f0-88bd35948539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86205372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.86205372
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2346735472
Short name T144
Test name
Test status
Simulation time 266797616 ps
CPU time 12.19 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:55:30 PM PDT 24
Peak memory 220060 kb
Host smart-0860f68f-6e32-443f-8588-0013b340b18a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346735472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2346735472
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1008142998
Short name T126
Test name
Test status
Simulation time 727575107 ps
CPU time 20.04 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 219988 kb
Host smart-29bf3dcf-2ea1-4aec-994e-df3cdbd96e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008142998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1008142998
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.443291331
Short name T49
Test name
Test status
Simulation time 27771210711 ps
CPU time 1040.6 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 05:12:45 PM PDT 24
Peak memory 232488 kb
Host smart-333f1f31-b0df-4fa7-a041-4750cba5c678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443291331 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.443291331
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2289561558
Short name T205
Test name
Test status
Simulation time 309172195 ps
CPU time 9.55 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:34 PM PDT 24
Peak memory 219044 kb
Host smart-cc3ac5c5-a87f-420d-8974-a48eeb99610e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289561558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2289561558
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.200800882
Short name T313
Test name
Test status
Simulation time 7519901150 ps
CPU time 250.47 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:59:29 PM PDT 24
Peak memory 238424 kb
Host smart-2b97978b-e6bc-4544-868a-90bd41d5aee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200800882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.200800882
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1376038275
Short name T181
Test name
Test status
Simulation time 5032098722 ps
CPU time 32.1 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:56 PM PDT 24
Peak memory 219776 kb
Host smart-c0256857-3195-41d1-b215-d3f76d90153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376038275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1376038275
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.300971462
Short name T270
Test name
Test status
Simulation time 274439905 ps
CPU time 12.18 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:31 PM PDT 24
Peak memory 219936 kb
Host smart-9d56a88f-ef47-4e15-8411-6bcc8bc8949b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300971462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.300971462
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.574773858
Short name T179
Test name
Test status
Simulation time 1086297318 ps
CPU time 11.68 seconds
Started Aug 02 04:55:26 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 219972 kb
Host smart-c90479fc-a51d-43e4-9c30-6b666a29fcfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574773858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.574773858
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.524824989
Short name T246
Test name
Test status
Simulation time 1129936704 ps
CPU time 10.55 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:55:36 PM PDT 24
Peak memory 219084 kb
Host smart-5beb97c6-305a-4bb2-b881-2fc5a0f65475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524824989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.524824989
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1277081117
Short name T286
Test name
Test status
Simulation time 2465812355 ps
CPU time 154.65 seconds
Started Aug 02 04:55:20 PM PDT 24
Finished Aug 02 04:57:54 PM PDT 24
Peak memory 220220 kb
Host smart-53f4ec73-d2c3-414a-b6d1-8677393c2465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277081117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1277081117
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2831144471
Short name T229
Test name
Test status
Simulation time 349885998 ps
CPU time 19.15 seconds
Started Aug 02 04:55:26 PM PDT 24
Finished Aug 02 04:55:45 PM PDT 24
Peak memory 220040 kb
Host smart-8609f01b-a571-4847-896d-a3293c259bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831144471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2831144471
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.862986120
Short name T19
Test name
Test status
Simulation time 638565720 ps
CPU time 10.35 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:55:35 PM PDT 24
Peak memory 220020 kb
Host smart-00b92442-5004-4e76-ac27-62526177cc6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862986120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.862986120
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.684874275
Short name T209
Test name
Test status
Simulation time 815643364 ps
CPU time 44.77 seconds
Started Aug 02 04:55:26 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 219980 kb
Host smart-11b52237-f314-4c18-95ea-2ad7b4684158
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684874275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.684874275
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2437952065
Short name T292
Test name
Test status
Simulation time 2738034031 ps
CPU time 10.05 seconds
Started Aug 02 04:55:13 PM PDT 24
Finished Aug 02 04:55:24 PM PDT 24
Peak memory 219224 kb
Host smart-b78f2e32-86e3-4233-8673-870a79ba9892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437952065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2437952065
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1988100792
Short name T40
Test name
Test status
Simulation time 81018685981 ps
CPU time 294.8 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 05:00:14 PM PDT 24
Peak memory 228416 kb
Host smart-563421f9-2f74-467f-ac8a-87b3712d6890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988100792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1988100792
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3111656055
Short name T23
Test name
Test status
Simulation time 517869000 ps
CPU time 22.5 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:40 PM PDT 24
Peak memory 219960 kb
Host smart-2e9a3c90-4fdc-4b3e-9450-4a66cb654bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111656055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3111656055
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3242551314
Short name T263
Test name
Test status
Simulation time 4749821238 ps
CPU time 17.01 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:55:44 PM PDT 24
Peak memory 220152 kb
Host smart-1fac064f-243f-40dc-819e-36abb6fb30fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242551314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3242551314
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1764269207
Short name T172
Test name
Test status
Simulation time 552782752 ps
CPU time 31.97 seconds
Started Aug 02 04:55:22 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 219956 kb
Host smart-4d4969c8-5ced-440f-bf73-87a708504d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764269207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1764269207
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2041539128
Short name T50
Test name
Test status
Simulation time 44980496265 ps
CPU time 889.85 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 05:10:08 PM PDT 24
Peak memory 233148 kb
Host smart-5d564631-0d53-4de7-bf3f-16d72fcc0495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041539128 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2041539128
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2950556235
Short name T302
Test name
Test status
Simulation time 3944993479 ps
CPU time 15.21 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:55:43 PM PDT 24
Peak memory 219112 kb
Host smart-72db2bf2-6978-40d0-a29e-3690247eeb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950556235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2950556235
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4133165329
Short name T202
Test name
Test status
Simulation time 33998664932 ps
CPU time 206.77 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:58:52 PM PDT 24
Peak memory 220268 kb
Host smart-97f462ff-b3bf-4d25-8567-742fd89f8b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133165329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4133165329
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.547454195
Short name T269
Test name
Test status
Simulation time 2062330973 ps
CPU time 22.19 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:39 PM PDT 24
Peak memory 219924 kb
Host smart-46506abc-a949-485e-9e0e-ebc47a1cb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547454195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.547454195
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3823112035
Short name T276
Test name
Test status
Simulation time 713166168 ps
CPU time 10.01 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 219932 kb
Host smart-0e1ab530-497b-4e55-8e43-a43baaf1007c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823112035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3823112035
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.532737122
Short name T81
Test name
Test status
Simulation time 786968172 ps
CPU time 28.98 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:50 PM PDT 24
Peak memory 220000 kb
Host smart-91b1c280-fff5-455e-b302-183aa4442d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532737122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.532737122
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1816758214
Short name T54
Test name
Test status
Simulation time 47268143078 ps
CPU time 474.63 seconds
Started Aug 02 04:55:20 PM PDT 24
Finished Aug 02 05:03:14 PM PDT 24
Peak memory 229892 kb
Host smart-b0f8a216-802d-450d-b447-75dc9b91c259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816758214 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1816758214
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1680090323
Short name T299
Test name
Test status
Simulation time 3513907257 ps
CPU time 9.93 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 218996 kb
Host smart-44b7dc7e-144e-4011-af7b-e7d3a4f80e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680090323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1680090323
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1946850722
Short name T262
Test name
Test status
Simulation time 5043649591 ps
CPU time 326.17 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 05:00:47 PM PDT 24
Peak memory 226800 kb
Host smart-6203efa9-3d42-4109-85fd-051b897de88c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946850722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1946850722
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3907145467
Short name T312
Test name
Test status
Simulation time 1975341844 ps
CPU time 22.43 seconds
Started Aug 02 04:55:26 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 220104 kb
Host smart-8cc38fa5-8021-47d7-8f49-9ce27a740317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907145467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3907145467
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.970369135
Short name T99
Test name
Test status
Simulation time 727936634 ps
CPU time 12.02 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 220044 kb
Host smart-5c0f924a-70fd-4385-852b-dfdb2a2382db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970369135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.970369135
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.163726781
Short name T199
Test name
Test status
Simulation time 277302144 ps
CPU time 12.75 seconds
Started Aug 02 04:55:13 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 219996 kb
Host smart-e5a7e3c5-2815-4ff4-a270-60061d25602b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163726781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.163726781
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1409575508
Short name T218
Test name
Test status
Simulation time 689445019 ps
CPU time 8.23 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 219056 kb
Host smart-ce0cbdba-549b-4693-9ae0-f4a3af9ee226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409575508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1409575508
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.534555937
Short name T135
Test name
Test status
Simulation time 2493774361 ps
CPU time 233.57 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:59:21 PM PDT 24
Peak memory 238456 kb
Host smart-23cadc2b-504a-44f6-a897-1fad2fb39145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534555937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.534555937
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.872538561
Short name T253
Test name
Test status
Simulation time 1012848224 ps
CPU time 21.97 seconds
Started Aug 02 04:55:22 PM PDT 24
Finished Aug 02 04:55:44 PM PDT 24
Peak memory 220028 kb
Host smart-1c12c181-43fe-4e33-9583-104c44bd53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872538561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.872538561
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2275080305
Short name T236
Test name
Test status
Simulation time 1969163128 ps
CPU time 12.5 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:31 PM PDT 24
Peak memory 219988 kb
Host smart-22cc53b3-f6ca-4298-bb42-c2ba36bf63fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275080305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2275080305
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3889138589
Short name T174
Test name
Test status
Simulation time 1772679647 ps
CPU time 31.22 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 220044 kb
Host smart-1f062400-2201-45f6-a99c-b060dd3ad7c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889138589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3889138589
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3229083051
Short name T303
Test name
Test status
Simulation time 1768627627 ps
CPU time 9.87 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:34 PM PDT 24
Peak memory 219164 kb
Host smart-2f379e10-59f3-4baf-bbc0-bb3761d0c502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229083051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3229083051
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3876867712
Short name T183
Test name
Test status
Simulation time 11098993127 ps
CPU time 177.72 seconds
Started Aug 02 04:55:16 PM PDT 24
Finished Aug 02 04:58:14 PM PDT 24
Peak memory 220284 kb
Host smart-8afcd9fd-eea7-4554-9295-2267a5b83bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876867712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3876867712
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1906874181
Short name T211
Test name
Test status
Simulation time 499054909 ps
CPU time 22.69 seconds
Started Aug 02 04:55:20 PM PDT 24
Finished Aug 02 04:55:43 PM PDT 24
Peak memory 219920 kb
Host smart-b5238aef-1a0f-4342-9645-9165145f0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906874181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1906874181
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.500989807
Short name T210
Test name
Test status
Simulation time 1313680266 ps
CPU time 10.36 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 220060 kb
Host smart-876e6e7c-b0af-458c-9015-aa821937ed2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500989807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.500989807
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4111439905
Short name T294
Test name
Test status
Simulation time 1675637203 ps
CPU time 39.2 seconds
Started Aug 02 04:55:18 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 219940 kb
Host smart-63d0a47b-b96e-4f56-9570-c087f7526ae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111439905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4111439905
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1067196956
Short name T306
Test name
Test status
Simulation time 259338404 ps
CPU time 10.06 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:30 PM PDT 24
Peak memory 219036 kb
Host smart-6b0cd5ee-c6bf-44cf-8c8f-7c85e05882a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067196956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1067196956
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1709924248
Short name T189
Test name
Test status
Simulation time 8067397553 ps
CPU time 169.54 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:58:07 PM PDT 24
Peak memory 225196 kb
Host smart-9af61fb2-3571-4889-8d6b-5820b7840829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709924248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1709924248
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4086378163
Short name T127
Test name
Test status
Simulation time 662037704 ps
CPU time 19.14 seconds
Started Aug 02 04:55:22 PM PDT 24
Finished Aug 02 04:55:41 PM PDT 24
Peak memory 220024 kb
Host smart-0d53830c-ad6e-4981-9b8c-938130e6167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086378163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4086378163
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2001094809
Short name T170
Test name
Test status
Simulation time 257894884 ps
CPU time 11.82 seconds
Started Aug 02 04:55:26 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 219996 kb
Host smart-c1800826-9184-4ea0-a264-ff87a6cd5de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001094809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2001094809
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3776717003
Short name T190
Test name
Test status
Simulation time 829292873 ps
CPU time 37.27 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:56:02 PM PDT 24
Peak memory 219872 kb
Host smart-c5ec19d2-f767-47c9-87e4-aafcbb5e9a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776717003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3776717003
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3728373351
Short name T15
Test name
Test status
Simulation time 26085101525 ps
CPU time 1990.17 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 228708 kb
Host smart-164234c5-a784-407a-b24e-b42b64fab624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728373351 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3728373351
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3686569639
Short name T227
Test name
Test status
Simulation time 4689111003 ps
CPU time 14.94 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 219140 kb
Host smart-d9e14e0f-7e8d-4ccb-a83d-11daa2fb9184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686569639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3686569639
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4016355071
Short name T258
Test name
Test status
Simulation time 6008966541 ps
CPU time 184.76 seconds
Started Aug 02 04:55:32 PM PDT 24
Finished Aug 02 04:58:37 PM PDT 24
Peak memory 219940 kb
Host smart-9da311cd-fb87-4170-8b09-6c1f74ba7751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016355071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4016355071
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1290047615
Short name T30
Test name
Test status
Simulation time 1037978845 ps
CPU time 22.31 seconds
Started Aug 02 04:55:23 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 220040 kb
Host smart-ec0e97d0-5ac8-480e-92c5-8cb75ce70182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290047615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1290047615
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4229320359
Short name T130
Test name
Test status
Simulation time 516649726 ps
CPU time 11.91 seconds
Started Aug 02 04:55:25 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 220020 kb
Host smart-97db8ecc-b7e3-4c9d-9fc9-3ad8ec926bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229320359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4229320359
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3328732989
Short name T293
Test name
Test status
Simulation time 2666900278 ps
CPU time 35.6 seconds
Started Aug 02 04:55:19 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 220008 kb
Host smart-5b20aa7a-f9c0-4e2f-8a04-4f643e463e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328732989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3328732989
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3108364397
Short name T243
Test name
Test status
Simulation time 337752344 ps
CPU time 9.94 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 218940 kb
Host smart-88eaff0f-f939-4d69-a295-9236bd7856bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108364397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3108364397
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1709992264
Short name T247
Test name
Test status
Simulation time 12665017510 ps
CPU time 170.06 seconds
Started Aug 02 04:54:55 PM PDT 24
Finished Aug 02 04:57:45 PM PDT 24
Peak memory 238404 kb
Host smart-de7269a7-ee11-46d1-9e8d-ca77aee08d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709992264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1709992264
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.45807631
Short name T132
Test name
Test status
Simulation time 333827969 ps
CPU time 18.88 seconds
Started Aug 02 04:54:56 PM PDT 24
Finished Aug 02 04:55:15 PM PDT 24
Peak memory 219956 kb
Host smart-95dd4bb1-c5cc-4dbb-bfc6-dcf060842b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45807631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.45807631
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3147378133
Short name T271
Test name
Test status
Simulation time 724154259 ps
CPU time 10.31 seconds
Started Aug 02 04:54:54 PM PDT 24
Finished Aug 02 04:55:05 PM PDT 24
Peak memory 220020 kb
Host smart-274924c9-b30a-45d8-8f48-02e908977326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147378133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3147378133
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2957037114
Short name T20
Test name
Test status
Simulation time 2233239043 ps
CPU time 226.2 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:58:48 PM PDT 24
Peak memory 238964 kb
Host smart-6c6952ce-9e45-4ce0-ac2c-5eb2725a8551
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957037114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2957037114
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1212797845
Short name T252
Test name
Test status
Simulation time 1056640931 ps
CPU time 17.79 seconds
Started Aug 02 04:54:57 PM PDT 24
Finished Aug 02 04:55:15 PM PDT 24
Peak memory 219932 kb
Host smart-e2a8265e-8136-4393-9f81-d8fdf3fbd94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212797845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1212797845
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.540506858
Short name T274
Test name
Test status
Simulation time 1017237693 ps
CPU time 18.46 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:16 PM PDT 24
Peak memory 219672 kb
Host smart-37e753bb-a427-4918-a8db-9b310ea9884d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540506858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.540506858
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3522727867
Short name T248
Test name
Test status
Simulation time 56798052753 ps
CPU time 739.98 seconds
Started Aug 02 04:55:02 PM PDT 24
Finished Aug 02 05:07:22 PM PDT 24
Peak memory 236520 kb
Host smart-6f8692d0-97e9-4e6b-982b-08862d781f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522727867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3522727867
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4167941250
Short name T27
Test name
Test status
Simulation time 992178981 ps
CPU time 10.08 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 219048 kb
Host smart-76f272aa-08f4-40ba-8286-7a4246581b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167941250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4167941250
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2855086578
Short name T39
Test name
Test status
Simulation time 17535265474 ps
CPU time 286.06 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 05:00:22 PM PDT 24
Peak memory 226924 kb
Host smart-f4b2c1d3-47be-4efc-b6a4-b08b2c9d09a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855086578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2855086578
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2757635618
Short name T24
Test name
Test status
Simulation time 6189758736 ps
CPU time 32.9 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:56:10 PM PDT 24
Peak memory 219728 kb
Host smart-61315ea5-9e9b-44ef-87e2-5987b752eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757635618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2757635618
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2937189525
Short name T310
Test name
Test status
Simulation time 361495900 ps
CPU time 10.29 seconds
Started Aug 02 04:55:28 PM PDT 24
Finished Aug 02 04:55:39 PM PDT 24
Peak memory 219988 kb
Host smart-6c6ac418-7969-4c2f-9602-ecb6b095ce55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937189525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2937189525
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.813515507
Short name T100
Test name
Test status
Simulation time 2086317087 ps
CPU time 23.65 seconds
Started Aug 02 04:55:24 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 219880 kb
Host smart-79560ae2-adc3-4b58-956d-659e4e830f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813515507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.813515507
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2219354905
Short name T136
Test name
Test status
Simulation time 173509106 ps
CPU time 8.5 seconds
Started Aug 02 04:55:32 PM PDT 24
Finished Aug 02 04:55:41 PM PDT 24
Peak memory 219096 kb
Host smart-e0dccba1-8d17-4e08-9052-77ec0f78122b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219354905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2219354905
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2074534635
Short name T8
Test name
Test status
Simulation time 9977563780 ps
CPU time 159.4 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:58:16 PM PDT 24
Peak memory 228588 kb
Host smart-06f8a44c-dbca-4d5b-a456-597d5fe1f159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074534635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2074534635
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1395810109
Short name T42
Test name
Test status
Simulation time 1035144147 ps
CPU time 21.78 seconds
Started Aug 02 04:55:31 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 220076 kb
Host smart-696b1a7b-cf4f-4090-b441-1f2808883c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395810109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1395810109
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3556387752
Short name T207
Test name
Test status
Simulation time 268517242 ps
CPU time 12.63 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:49 PM PDT 24
Peak memory 220040 kb
Host smart-84062749-b8c7-4206-91ae-90b6d9119c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556387752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3556387752
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.402959631
Short name T320
Test name
Test status
Simulation time 1061928916 ps
CPU time 29.86 seconds
Started Aug 02 04:55:33 PM PDT 24
Finished Aug 02 04:56:03 PM PDT 24
Peak memory 219900 kb
Host smart-0491b8e6-aad4-482e-94d8-25d8bf0b699b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402959631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.402959631
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3655713896
Short name T146
Test name
Test status
Simulation time 172893007 ps
CPU time 8.31 seconds
Started Aug 02 04:55:34 PM PDT 24
Finished Aug 02 04:55:43 PM PDT 24
Peak memory 219100 kb
Host smart-b76c2e27-1a8e-4e46-b7c6-ba69b9fc0612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655713896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3655713896
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2559208985
Short name T31
Test name
Test status
Simulation time 10774059068 ps
CPU time 191.59 seconds
Started Aug 02 04:55:31 PM PDT 24
Finished Aug 02 04:58:42 PM PDT 24
Peak memory 240544 kb
Host smart-fd3fc87a-ef92-4175-8f16-d828e1698de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559208985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2559208985
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2467023559
Short name T159
Test name
Test status
Simulation time 2155097546 ps
CPU time 22.72 seconds
Started Aug 02 04:55:33 PM PDT 24
Finished Aug 02 04:55:56 PM PDT 24
Peak memory 220132 kb
Host smart-05708baa-3756-4278-8b34-66a729cd7e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467023559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2467023559
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1349004778
Short name T122
Test name
Test status
Simulation time 724145034 ps
CPU time 10.65 seconds
Started Aug 02 04:55:27 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 220072 kb
Host smart-e4ee546f-2761-4c60-bbf1-ac04f22ca349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349004778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1349004778
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4154941373
Short name T18
Test name
Test status
Simulation time 1147583613 ps
CPU time 13.18 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:49 PM PDT 24
Peak memory 219880 kb
Host smart-46093c19-d6aa-4b1a-a92b-c84857df616b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154941373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4154941373
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2694583263
Short name T283
Test name
Test status
Simulation time 1028576953 ps
CPU time 9.66 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:55:45 PM PDT 24
Peak memory 219060 kb
Host smart-f98a9c68-3816-4aff-acae-5a78e4bfa4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694583263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2694583263
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4227291745
Short name T309
Test name
Test status
Simulation time 17451070359 ps
CPU time 294.87 seconds
Started Aug 02 04:55:33 PM PDT 24
Finished Aug 02 05:00:28 PM PDT 24
Peak memory 220272 kb
Host smart-5ff733e7-0357-41ee-8922-46f9e9a0301d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227291745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4227291745
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.953320900
Short name T131
Test name
Test status
Simulation time 2023525451 ps
CPU time 32.42 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:56:10 PM PDT 24
Peak memory 220068 kb
Host smart-988943a5-e2fb-47fe-a517-2814e5ba4245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953320900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.953320900
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1578979783
Short name T225
Test name
Test status
Simulation time 185295723 ps
CPU time 10.26 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:55:50 PM PDT 24
Peak memory 220060 kb
Host smart-cf4d3eff-8eb2-404d-be1d-ae847fe1bc2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578979783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1578979783
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.376721490
Short name T280
Test name
Test status
Simulation time 702136213 ps
CPU time 41.32 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 220020 kb
Host smart-f37a21df-f842-4b24-9adc-b099f5c8cf7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376721490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.376721490
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1702605977
Short name T203
Test name
Test status
Simulation time 167526150 ps
CPU time 8.37 seconds
Started Aug 02 04:55:29 PM PDT 24
Finished Aug 02 04:55:38 PM PDT 24
Peak memory 219212 kb
Host smart-eeb39432-edcd-4eb7-8cdb-d233cb4036cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702605977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1702605977
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1878267533
Short name T38
Test name
Test status
Simulation time 7141599267 ps
CPU time 365.77 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 05:01:43 PM PDT 24
Peak memory 239768 kb
Host smart-87de17a7-3405-49a8-9c75-e3bd7e3f80a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878267533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1878267533
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1583574604
Short name T217
Test name
Test status
Simulation time 39325495060 ps
CPU time 32.73 seconds
Started Aug 02 04:55:28 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 220168 kb
Host smart-1e6339c5-c843-40d1-be33-57b74bf6b8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583574604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1583574604
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1998366226
Short name T281
Test name
Test status
Simulation time 266717390 ps
CPU time 12.42 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:55:50 PM PDT 24
Peak memory 220012 kb
Host smart-53d57733-437b-4c2d-823f-8d0ea6fd1ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998366226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1998366226
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3809670346
Short name T315
Test name
Test status
Simulation time 1224487652 ps
CPU time 38.92 seconds
Started Aug 02 04:55:28 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 220000 kb
Host smart-18b86058-f5b2-4e78-8698-1f5f142a372d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809670346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3809670346
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1905601268
Short name T193
Test name
Test status
Simulation time 249811615 ps
CPU time 10.16 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 218664 kb
Host smart-232838e7-423a-44af-8560-a5d862345b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905601268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1905601268
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2370109081
Short name T184
Test name
Test status
Simulation time 3859374895 ps
CPU time 283.24 seconds
Started Aug 02 04:55:34 PM PDT 24
Finished Aug 02 05:00:18 PM PDT 24
Peak memory 230600 kb
Host smart-25af4903-dc24-40bd-9401-24b9cd7b6abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370109081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2370109081
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2840586371
Short name T197
Test name
Test status
Simulation time 1033168018 ps
CPU time 22.8 seconds
Started Aug 02 04:55:28 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 220016 kb
Host smart-e8bf660f-e2d7-417d-8d7c-cef5521050dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840586371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2840586371
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2884127404
Short name T317
Test name
Test status
Simulation time 266086950 ps
CPU time 12.33 seconds
Started Aug 02 04:55:34 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 220024 kb
Host smart-326a644f-6b08-42b6-9ad1-66f829d5dad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884127404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2884127404
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2095796857
Short name T279
Test name
Test status
Simulation time 3109380884 ps
CPU time 29.12 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 220196 kb
Host smart-eea1f0c4-92c6-44a1-9cfc-697b536f172c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095796857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2095796857
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.134801677
Short name T187
Test name
Test status
Simulation time 1122861895 ps
CPU time 10.08 seconds
Started Aug 02 04:55:34 PM PDT 24
Finished Aug 02 04:55:45 PM PDT 24
Peak memory 219128 kb
Host smart-15d08730-8ae2-4cee-91ac-90c86ff8e8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134801677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.134801677
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2869622223
Short name T37
Test name
Test status
Simulation time 3613068251 ps
CPU time 243.49 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:59:40 PM PDT 24
Peak memory 226244 kb
Host smart-5d211b4a-fdf9-4602-9fdf-6e56159728a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869622223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2869622223
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2700530734
Short name T244
Test name
Test status
Simulation time 1832851939 ps
CPU time 18.4 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 219864 kb
Host smart-21136a45-95e3-44e6-9634-7aa67af3884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700530734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2700530734
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3466470947
Short name T101
Test name
Test status
Simulation time 1064845585 ps
CPU time 11.46 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 219952 kb
Host smart-e993225d-3262-4c2f-a65a-70f11c939e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466470947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3466470947
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.649359545
Short name T139
Test name
Test status
Simulation time 183373137 ps
CPU time 17.86 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 219940 kb
Host smart-4907bb05-ab54-44df-b2e3-6dfbc18299b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649359545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.649359545
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1415036573
Short name T297
Test name
Test status
Simulation time 358784141378 ps
CPU time 1699.98 seconds
Started Aug 02 04:55:30 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 250424 kb
Host smart-a1b7223b-fedf-4cc7-8a84-f828f2ac2a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415036573 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1415036573
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3653561651
Short name T14
Test name
Test status
Simulation time 172943790 ps
CPU time 8.12 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 219000 kb
Host smart-5555ec85-5ce3-4de6-9798-81889ca5bb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653561651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3653561651
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3288506354
Short name T215
Test name
Test status
Simulation time 12999898257 ps
CPU time 239.29 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:59:36 PM PDT 24
Peak memory 234652 kb
Host smart-f090993a-44cc-480b-b480-44d0fbe6737b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288506354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3288506354
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1860243747
Short name T185
Test name
Test status
Simulation time 396411835 ps
CPU time 18.59 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 219952 kb
Host smart-5adedc8d-0c24-485b-bc72-5220242ad466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860243747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1860243747
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1952229894
Short name T239
Test name
Test status
Simulation time 328949416 ps
CPU time 10.58 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 220108 kb
Host smart-7cf5586b-8e18-4132-b479-b5bea23c22b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952229894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1952229894
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1838250667
Short name T182
Test name
Test status
Simulation time 531997346 ps
CPU time 27.13 seconds
Started Aug 02 04:55:34 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 219920 kb
Host smart-8e422f30-9a92-4b31-9c85-75ba873189b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838250667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1838250667
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.818841554
Short name T102
Test name
Test status
Simulation time 54336631292 ps
CPU time 2222.48 seconds
Started Aug 02 04:55:33 PM PDT 24
Finished Aug 02 05:32:36 PM PDT 24
Peak memory 244748 kb
Host smart-c969e095-2471-426d-b482-4d99e472fe6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818841554 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.818841554
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4154222363
Short name T148
Test name
Test status
Simulation time 1032396536 ps
CPU time 10.18 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 219216 kb
Host smart-b85a704a-6f32-478c-8bb5-53b99a04f12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154222363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4154222363
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1391110985
Short name T45
Test name
Test status
Simulation time 5664965871 ps
CPU time 287.25 seconds
Started Aug 02 04:55:39 PM PDT 24
Finished Aug 02 05:00:26 PM PDT 24
Peak memory 234636 kb
Host smart-1986a230-5a53-41d2-b404-99d1f8cad72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391110985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1391110985
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3702770450
Short name T223
Test name
Test status
Simulation time 2996711569 ps
CPU time 18.54 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 220048 kb
Host smart-262cb70c-e179-4495-9f65-94f7c754a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702770450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3702770450
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1179145312
Short name T141
Test name
Test status
Simulation time 192077366 ps
CPU time 10.14 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 220132 kb
Host smart-308122d0-718a-44f5-b0f1-c103b529ed44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179145312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1179145312
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3071637611
Short name T266
Test name
Test status
Simulation time 1500634579 ps
CPU time 21.37 seconds
Started Aug 02 04:55:30 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 220036 kb
Host smart-b2de9edf-e0bc-494c-ae55-5e057301cf2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071637611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3071637611
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1509378741
Short name T245
Test name
Test status
Simulation time 1030428442 ps
CPU time 9.96 seconds
Started Aug 02 04:55:47 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 218944 kb
Host smart-41944790-c178-4499-bc23-b596795d818a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509378741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1509378741
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.926541805
Short name T175
Test name
Test status
Simulation time 4847359237 ps
CPU time 187.33 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:58:48 PM PDT 24
Peak memory 220260 kb
Host smart-e2e05d10-3198-40a9-9c56-84dbb31df3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926541805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.926541805
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2947473262
Short name T9
Test name
Test status
Simulation time 349732446 ps
CPU time 19.42 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 220100 kb
Host smart-baa2088b-58cb-4bad-a3ae-f155f6afed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947473262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2947473262
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.673432000
Short name T230
Test name
Test status
Simulation time 1179898677 ps
CPU time 12.69 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 219944 kb
Host smart-4d4f6373-976a-43e3-b639-986b93eebbbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673432000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.673432000
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3883809517
Short name T324
Test name
Test status
Simulation time 16679962021 ps
CPU time 59 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:56:34 PM PDT 24
Peak memory 220080 kb
Host smart-c239cb6d-6f39-47fa-88c4-cde9144c758b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883809517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3883809517
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.755163350
Short name T191
Test name
Test status
Simulation time 257200532 ps
CPU time 10.19 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 219156 kb
Host smart-437d056d-2ca7-461c-81b2-1e594a683109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755163350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.755163350
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2112450803
Short name T321
Test name
Test status
Simulation time 12053142824 ps
CPU time 167.89 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 238084 kb
Host smart-7b9d465d-346e-406d-b572-b2b68dac491f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112450803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2112450803
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4292745890
Short name T140
Test name
Test status
Simulation time 664895236 ps
CPU time 19 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:19 PM PDT 24
Peak memory 219932 kb
Host smart-a2da07d1-4ce5-42dc-9446-60635e8b4df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292745890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4292745890
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1044309549
Short name T255
Test name
Test status
Simulation time 181344290 ps
CPU time 10.27 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 219956 kb
Host smart-94199409-fce1-4b7d-931a-99bef1ddfbf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044309549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1044309549
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.458178055
Short name T26
Test name
Test status
Simulation time 2414326931 ps
CPU time 116.94 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 234176 kb
Host smart-fd06865d-665c-4577-9c65-5c41e99ebff8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458178055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.458178055
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.113066542
Short name T213
Test name
Test status
Simulation time 662305112 ps
CPU time 10.15 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 219948 kb
Host smart-892e0d39-44ee-4402-ab62-faa7d69ee502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113066542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.113066542
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2173095652
Short name T259
Test name
Test status
Simulation time 3512636850 ps
CPU time 37.51 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:37 PM PDT 24
Peak memory 219928 kb
Host smart-4116773c-95ff-4c00-adc4-8434996c9f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173095652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2173095652
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2735584313
Short name T134
Test name
Test status
Simulation time 249532266 ps
CPU time 10.39 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 219180 kb
Host smart-a1f4e8f6-bb9a-4b39-86e4-60604262a4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735584313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2735584313
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.248639949
Short name T226
Test name
Test status
Simulation time 6447036253 ps
CPU time 195.19 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:58:52 PM PDT 24
Peak memory 220276 kb
Host smart-422ef020-bd2e-40fa-842e-526eb3f40da5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248639949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.248639949
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3087932734
Short name T128
Test name
Test status
Simulation time 517921022 ps
CPU time 22.44 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 219976 kb
Host smart-63cb7b81-4ee8-453f-b33b-ce6e7030b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087932734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3087932734
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3329777425
Short name T233
Test name
Test status
Simulation time 1720287444 ps
CPU time 10.29 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 220020 kb
Host smart-236d63bd-88b2-438c-8318-7f21573fd003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329777425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3329777425
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3754675184
Short name T235
Test name
Test status
Simulation time 894803110 ps
CPU time 27.97 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 219968 kb
Host smart-e3055765-dee2-4f83-9e05-52d995c9d35b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754675184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3754675184
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2021149169
Short name T48
Test name
Test status
Simulation time 174754926124 ps
CPU time 7191.64 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 06:55:28 PM PDT 24
Peak memory 234244 kb
Host smart-fefd6203-1214-4226-8a6b-38f67b921949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021149169 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2021149169
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1018158586
Short name T219
Test name
Test status
Simulation time 1766338017 ps
CPU time 9.93 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 219016 kb
Host smart-58e67d57-0dab-461c-ab20-038a9d217fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018158586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1018158586
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2600611629
Short name T260
Test name
Test status
Simulation time 19433535690 ps
CPU time 294.17 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 05:00:30 PM PDT 24
Peak memory 239600 kb
Host smart-92650245-4387-4a37-a905-99e8f110a0eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600611629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2600611629
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3372743042
Short name T204
Test name
Test status
Simulation time 1035169159 ps
CPU time 22.77 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 220064 kb
Host smart-d748352f-f247-441a-981d-7e0b1d3c6241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372743042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3372743042
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1421932720
Short name T163
Test name
Test status
Simulation time 757692280 ps
CPU time 10.04 seconds
Started Aug 02 04:55:44 PM PDT 24
Finished Aug 02 04:55:54 PM PDT 24
Peak memory 220108 kb
Host smart-43020855-909f-4e36-9a98-c48ee5276e10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421932720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1421932720
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3566516576
Short name T323
Test name
Test status
Simulation time 365428662 ps
CPU time 23.45 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:56:02 PM PDT 24
Peak memory 219944 kb
Host smart-2f47bb02-a70a-4abf-a2ec-f83bc095fb88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566516576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3566516576
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.348290186
Short name T304
Test name
Test status
Simulation time 1027850451 ps
CPU time 9.88 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 219084 kb
Host smart-fb3fe6a8-ef02-49a5-8444-3af70b894f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348290186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.348290186
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.858056392
Short name T194
Test name
Test status
Simulation time 19860376728 ps
CPU time 273.72 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 05:00:09 PM PDT 24
Peak memory 220236 kb
Host smart-76e7a4c9-014d-41be-9f9a-a2241d9179d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858056392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.858056392
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2964001625
Short name T198
Test name
Test status
Simulation time 7069406746 ps
CPU time 23.1 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 220156 kb
Host smart-0a10dd02-1622-4914-98e7-684135accdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964001625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2964001625
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2203843636
Short name T11
Test name
Test status
Simulation time 1282960495 ps
CPU time 12.01 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:56:03 PM PDT 24
Peak memory 219960 kb
Host smart-03d725d0-2494-4fb6-b740-268cd56d144e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203843636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2203843636
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2242471953
Short name T289
Test name
Test status
Simulation time 49461987774 ps
CPU time 10496.7 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 07:50:32 PM PDT 24
Peak memory 234976 kb
Host smart-0f4ef0a2-80e1-475b-a136-ec890b9b1253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242471953 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2242471953
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3153766057
Short name T125
Test name
Test status
Simulation time 509393796 ps
CPU time 10.15 seconds
Started Aug 02 04:55:39 PM PDT 24
Finished Aug 02 04:55:49 PM PDT 24
Peak memory 219056 kb
Host smart-f88eaa8b-c082-460a-9e92-5e34c075714c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153766057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3153766057
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1009207917
Short name T231
Test name
Test status
Simulation time 691185066 ps
CPU time 18.76 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 219936 kb
Host smart-53e91b72-1c40-4719-928d-914a4d25f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009207917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1009207917
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1936501048
Short name T273
Test name
Test status
Simulation time 725670489 ps
CPU time 10.95 seconds
Started Aug 02 04:55:39 PM PDT 24
Finished Aug 02 04:55:50 PM PDT 24
Peak memory 220088 kb
Host smart-ce3a153d-4dc4-42c7-9431-0b6f622266f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936501048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1936501048
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.603425607
Short name T61
Test name
Test status
Simulation time 803622386 ps
CPU time 38.95 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:56:19 PM PDT 24
Peak memory 219472 kb
Host smart-e1eaf7da-e092-49df-af75-7a8965ebdc1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603425607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.603425607
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2000861022
Short name T311
Test name
Test status
Simulation time 258977397 ps
CPU time 10.08 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 218544 kb
Host smart-04430bca-df29-4eb2-87ae-353872b4a6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000861022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2000861022
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3232940894
Short name T46
Test name
Test status
Simulation time 13013054624 ps
CPU time 325.54 seconds
Started Aug 02 04:55:41 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 243924 kb
Host smart-9efbb446-7d42-41a3-b657-f057798a41e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232940894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3232940894
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1709472397
Short name T137
Test name
Test status
Simulation time 495851347 ps
CPU time 22.15 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 219936 kb
Host smart-dba42281-9491-498f-accd-88658a2d487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709472397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1709472397
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4062415073
Short name T155
Test name
Test status
Simulation time 1013022354 ps
CPU time 16.71 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 219400 kb
Host smart-88cae6d9-7fe2-4b21-9912-7749aee200fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062415073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4062415073
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1292648011
Short name T196
Test name
Test status
Simulation time 8027586649 ps
CPU time 35.97 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 220204 kb
Host smart-0070c4f9-6526-410c-a906-0196e3d804c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292648011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1292648011
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3030411046
Short name T195
Test name
Test status
Simulation time 256486333 ps
CPU time 10.01 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 219016 kb
Host smart-5eaf5558-1753-4df0-a67e-805192437828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030411046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3030411046
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3653540768
Short name T290
Test name
Test status
Simulation time 6021008577 ps
CPU time 341.07 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 05:01:30 PM PDT 24
Peak memory 238464 kb
Host smart-a58136a0-102c-4be8-9d4d-6f056cb1f6ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653540768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3653540768
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2063916852
Short name T3
Test name
Test status
Simulation time 229742343 ps
CPU time 10.38 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 219520 kb
Host smart-1386343d-bbed-48ba-bf9f-7d858544e3dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063916852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2063916852
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2441959697
Short name T254
Test name
Test status
Simulation time 1230895021 ps
CPU time 12.83 seconds
Started Aug 02 04:55:40 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 219936 kb
Host smart-89373726-0690-4e24-a797-31bbe3fa4f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441959697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2441959697
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3788816553
Short name T51
Test name
Test status
Simulation time 5976857106 ps
CPU time 853.05 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 05:10:03 PM PDT 24
Peak memory 228364 kb
Host smart-9a6074d6-9172-434f-89b0-8046b6278814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788816553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3788816553
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4147401787
Short name T167
Test name
Test status
Simulation time 1029826787 ps
CPU time 9.9 seconds
Started Aug 02 04:55:35 PM PDT 24
Finished Aug 02 04:55:45 PM PDT 24
Peak memory 219040 kb
Host smart-62879993-6697-450d-a539-d809c269ebb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147401787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4147401787
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2302926441
Short name T298
Test name
Test status
Simulation time 11315002328 ps
CPU time 332.72 seconds
Started Aug 02 04:55:39 PM PDT 24
Finished Aug 02 05:01:12 PM PDT 24
Peak memory 235648 kb
Host smart-44b937bb-a952-45d3-b0c8-f0b1098ebb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302926441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2302926441
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.943622845
Short name T176
Test name
Test status
Simulation time 346881696 ps
CPU time 18.42 seconds
Started Aug 02 04:55:46 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 219936 kb
Host smart-99b6e5ec-17a0-4976-b068-cbde3400cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943622845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.943622845
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.759582545
Short name T119
Test name
Test status
Simulation time 185137035 ps
CPU time 10.26 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:55:59 PM PDT 24
Peak memory 219960 kb
Host smart-0e1fae3f-86bb-4ca3-b2c9-3567bfb2cc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759582545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.759582545
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3578270427
Short name T291
Test name
Test status
Simulation time 1024833520 ps
CPU time 32.87 seconds
Started Aug 02 04:55:47 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 220036 kb
Host smart-077da540-3bfe-4cb9-a272-efe218fa4440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578270427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3578270427
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1683368836
Short name T200
Test name
Test status
Simulation time 249310337 ps
CPU time 10.26 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 218624 kb
Host smart-8bc3b60a-f7d6-465a-bf2b-225451ae8096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683368836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1683368836
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1022447669
Short name T41
Test name
Test status
Simulation time 12320351571 ps
CPU time 241.46 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:59:38 PM PDT 24
Peak memory 235512 kb
Host smart-db123297-5a55-4639-818d-9cf3fb5e4850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022447669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1022447669
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2054446298
Short name T240
Test name
Test status
Simulation time 2361719172 ps
CPU time 22.43 seconds
Started Aug 02 04:55:42 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 220144 kb
Host smart-6b80e3e6-66e4-464e-9b6e-6efe0ed92eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054446298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2054446298
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4270673839
Short name T161
Test name
Test status
Simulation time 671394452 ps
CPU time 10.45 seconds
Started Aug 02 04:55:37 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 219980 kb
Host smart-4537d407-01fd-4ebd-8979-0b5e235f7ef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270673839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4270673839
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1930572876
Short name T325
Test name
Test status
Simulation time 2189905754 ps
CPU time 30.32 seconds
Started Aug 02 04:55:36 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 220204 kb
Host smart-3fa5eee3-9b2d-4134-b35e-e47123229c50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930572876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1930572876
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3954178586
Short name T305
Test name
Test status
Simulation time 9763438192 ps
CPU time 15.25 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 219052 kb
Host smart-9d5c94ad-b741-4838-8836-a3301b378779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954178586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3954178586
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3838425447
Short name T153
Test name
Test status
Simulation time 46338989750 ps
CPU time 311.87 seconds
Started Aug 02 04:55:42 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 233640 kb
Host smart-037cf974-7266-46dc-b2d1-d7e5b04b36ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838425447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3838425447
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.392815610
Short name T169
Test name
Test status
Simulation time 332191682 ps
CPU time 18.96 seconds
Started Aug 02 04:55:47 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 220004 kb
Host smart-d4e86e5a-5b14-4f47-8d8a-b0e69aa12cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392815610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.392815610
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1444199540
Short name T295
Test name
Test status
Simulation time 507934992 ps
CPU time 10.32 seconds
Started Aug 02 04:55:38 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 219968 kb
Host smart-fc4602e0-86ad-453c-87c0-156b1b36aae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444199540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1444199540
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2704741446
Short name T173
Test name
Test status
Simulation time 561154159 ps
CPU time 34.56 seconds
Started Aug 02 04:55:39 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 219944 kb
Host smart-3e9f6236-e578-48f6-acd6-2236d717ff32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704741446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2704741446
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1641599715
Short name T237
Test name
Test status
Simulation time 26578195490 ps
CPU time 977.19 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 05:12:02 PM PDT 24
Peak memory 232872 kb
Host smart-d7cda50d-b8da-4cdf-aaec-c268f8c28eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641599715 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1641599715
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1235739729
Short name T138
Test name
Test status
Simulation time 238012304 ps
CPU time 8.64 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 219108 kb
Host smart-2c4f8849-067e-4d9e-be4c-a2b8bfd7b2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235739729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1235739729
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.106039978
Short name T156
Test name
Test status
Simulation time 8010932800 ps
CPU time 409.32 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 05:02:37 PM PDT 24
Peak memory 226620 kb
Host smart-023c0be8-de6d-44a6-8ff1-fcda73cc28ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106039978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.106039978
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.60787893
Short name T322
Test name
Test status
Simulation time 1325036744 ps
CPU time 19.17 seconds
Started Aug 02 04:55:42 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 220040 kb
Host smart-487e3312-d4b6-4bce-8f62-e81a1204a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60787893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.60787893
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1383988380
Short name T278
Test name
Test status
Simulation time 711161117 ps
CPU time 10.7 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 219976 kb
Host smart-63aad547-addb-4cfb-b1b2-1ea1151050b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383988380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1383988380
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1681069627
Short name T277
Test name
Test status
Simulation time 544459462 ps
CPU time 37.18 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:56:22 PM PDT 24
Peak memory 220072 kb
Host smart-619d6179-7b92-4225-91ba-42de69217583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681069627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1681069627
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2949090360
Short name T2
Test name
Test status
Simulation time 332122997 ps
CPU time 8.46 seconds
Started Aug 02 04:55:05 PM PDT 24
Finished Aug 02 04:55:14 PM PDT 24
Peak memory 219100 kb
Host smart-926d8f2e-5daf-47c7-98e7-dcdb307a8cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949090360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2949090360
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3904352958
Short name T287
Test name
Test status
Simulation time 12125262651 ps
CPU time 300.94 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 05:00:01 PM PDT 24
Peak memory 238360 kb
Host smart-632d55e0-44c2-4bc5-8688-86440cccc3df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904352958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3904352958
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3398438051
Short name T165
Test name
Test status
Simulation time 499314604 ps
CPU time 22.78 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:21 PM PDT 24
Peak memory 219964 kb
Host smart-c7ec1b52-ac05-4838-9f13-8f28728e30a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398438051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3398438051
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2744736232
Short name T256
Test name
Test status
Simulation time 184317610 ps
CPU time 10.38 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 220088 kb
Host smart-2246dd13-eabb-44f9-b5b1-499616794b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744736232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2744736232
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1230690411
Short name T17
Test name
Test status
Simulation time 385015357 ps
CPU time 12.4 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 220084 kb
Host smart-3a5dc838-d9ad-48fc-9da5-f898771efb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230690411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1230690411
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4157084463
Short name T318
Test name
Test status
Simulation time 1062515391 ps
CPU time 30.11 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:31 PM PDT 24
Peak memory 219880 kb
Host smart-a90ea5cc-063e-4c02-888c-58ed1e6c085f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157084463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4157084463
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3217003288
Short name T208
Test name
Test status
Simulation time 825633928 ps
CPU time 8.29 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:55:07 PM PDT 24
Peak memory 218964 kb
Host smart-61a96227-f74a-4df4-a23f-6afe556a0078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217003288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3217003288
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3776173277
Short name T151
Test name
Test status
Simulation time 353424084 ps
CPU time 19.28 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:19 PM PDT 24
Peak memory 220088 kb
Host smart-6e00b68e-0730-4e2b-b8a2-4d6efd3b9e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776173277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3776173277
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1025401592
Short name T220
Test name
Test status
Simulation time 418880597 ps
CPU time 11.82 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 220048 kb
Host smart-197b643d-e9b8-4946-a550-0a1f1329e7de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025401592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1025401592
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1664608040
Short name T32
Test name
Test status
Simulation time 372701006 ps
CPU time 10.2 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:10 PM PDT 24
Peak memory 219928 kb
Host smart-56338bdc-588b-478a-9485-1b208a4d0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664608040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1664608040
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3543542334
Short name T177
Test name
Test status
Simulation time 1384499802 ps
CPU time 25.03 seconds
Started Aug 02 04:55:06 PM PDT 24
Finished Aug 02 04:55:32 PM PDT 24
Peak memory 219968 kb
Host smart-8dcd142d-5aa4-475a-829c-687550748b43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543542334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3543542334
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2767456318
Short name T149
Test name
Test status
Simulation time 353139778 ps
CPU time 8.07 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 219232 kb
Host smart-334389d2-325c-45cf-a07d-68e172948155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767456318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2767456318
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3220907512
Short name T192
Test name
Test status
Simulation time 3134396284 ps
CPU time 240.01 seconds
Started Aug 02 04:55:02 PM PDT 24
Finished Aug 02 04:59:02 PM PDT 24
Peak memory 228576 kb
Host smart-205ec813-36ed-4782-a43a-b8b59e411dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220907512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3220907512
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1246617413
Short name T285
Test name
Test status
Simulation time 2586740384 ps
CPU time 31.47 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:31 PM PDT 24
Peak memory 219660 kb
Host smart-513cfc5c-a250-4975-8669-5f68bbe3c857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246617413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1246617413
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.87076891
Short name T5
Test name
Test status
Simulation time 1079343517 ps
CPU time 12.17 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 220008 kb
Host smart-2d70c752-6d49-4b4e-9366-42a94d7a300f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87076891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.87076891
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1142558872
Short name T284
Test name
Test status
Simulation time 740366841 ps
CPU time 10.42 seconds
Started Aug 02 04:55:07 PM PDT 24
Finished Aug 02 04:55:17 PM PDT 24
Peak memory 219992 kb
Host smart-30362a88-df48-4a15-bac9-a82f9189a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142558872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1142558872
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1248636118
Short name T147
Test name
Test status
Simulation time 183464079 ps
CPU time 17.48 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:18 PM PDT 24
Peak memory 220096 kb
Host smart-b440f575-2bc2-46e4-a579-aa5e18c71b5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248636118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1248636118
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2441947584
Short name T272
Test name
Test status
Simulation time 172732657 ps
CPU time 8.62 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 218968 kb
Host smart-0f1c0921-3322-4fa1-8e2c-787b958876cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441947584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2441947584
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1768148384
Short name T180
Test name
Test status
Simulation time 7488891060 ps
CPU time 186.69 seconds
Started Aug 02 04:55:04 PM PDT 24
Finished Aug 02 04:58:11 PM PDT 24
Peak memory 240520 kb
Host smart-06b1926f-b5b1-4a53-a0a6-882861984130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768148384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1768148384
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2053597405
Short name T264
Test name
Test status
Simulation time 332677709 ps
CPU time 18.55 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:19 PM PDT 24
Peak memory 220004 kb
Host smart-a0e36bb3-9097-4c56-8798-e13e5ec0eb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053597405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2053597405
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3605543751
Short name T143
Test name
Test status
Simulation time 528446585 ps
CPU time 12.13 seconds
Started Aug 02 04:55:03 PM PDT 24
Finished Aug 02 04:55:15 PM PDT 24
Peak memory 219944 kb
Host smart-4e4749b5-bbbb-4afc-8aec-44d37966bccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605543751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3605543751
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3296592533
Short name T121
Test name
Test status
Simulation time 277486461 ps
CPU time 10.52 seconds
Started Aug 02 04:55:04 PM PDT 24
Finished Aug 02 04:55:14 PM PDT 24
Peak memory 219932 kb
Host smart-b1eab806-d3f6-4e4e-af11-e4ba7fc48a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296592533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3296592533
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2896256738
Short name T77
Test name
Test status
Simulation time 3377109555 ps
CPU time 27.96 seconds
Started Aug 02 04:55:04 PM PDT 24
Finished Aug 02 04:55:32 PM PDT 24
Peak memory 219984 kb
Host smart-645d13d4-078d-456a-8526-e0168161f980
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896256738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2896256738
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2044864077
Short name T234
Test name
Test status
Simulation time 662712888 ps
CPU time 8.6 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 219092 kb
Host smart-5ed6ff63-ceca-456e-a07d-6f95ed2e5100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044864077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2044864077
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2317557438
Short name T188
Test name
Test status
Simulation time 8986833608 ps
CPU time 155.38 seconds
Started Aug 02 04:54:58 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 237084 kb
Host smart-2a089bd8-3fbe-4d1f-9234-2294a744e691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317557438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2317557438
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3393508535
Short name T288
Test name
Test status
Simulation time 354303173 ps
CPU time 19.35 seconds
Started Aug 02 04:55:01 PM PDT 24
Finished Aug 02 04:55:20 PM PDT 24
Peak memory 220008 kb
Host smart-e1dc354e-2de7-4067-aa74-38730640d1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393508535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3393508535
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3840694206
Short name T221
Test name
Test status
Simulation time 525696135 ps
CPU time 12.1 seconds
Started Aug 02 04:55:00 PM PDT 24
Finished Aug 02 04:55:13 PM PDT 24
Peak memory 219928 kb
Host smart-c4cec78a-c04e-4bba-b9a5-430e4b409f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840694206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3840694206
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3515726505
Short name T152
Test name
Test status
Simulation time 571230032 ps
CPU time 33.47 seconds
Started Aug 02 04:55:09 PM PDT 24
Finished Aug 02 04:55:42 PM PDT 24
Peak memory 219896 kb
Host smart-feba613b-ff82-4722-8de5-5be363f58b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515726505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3515726505
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.441591971
Short name T257
Test name
Test status
Simulation time 27230243692 ps
CPU time 4321.31 seconds
Started Aug 02 04:54:59 PM PDT 24
Finished Aug 02 06:07:01 PM PDT 24
Peak memory 235916 kb
Host smart-6085da2a-11ba-47c4-80c5-e6b08e40f1f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441591971 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.441591971
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%