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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 92.42 97.68 100.00 98.62 97.30 97.90


Total test records in report: 415
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T286 /workspace/coverage/default/25.rom_ctrl_alert_test.843490004 Aug 03 04:33:40 PM PDT 24 Aug 03 04:33:50 PM PDT 24 1035054620 ps
T287 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.337536072 Aug 03 04:33:24 PM PDT 24 Aug 03 04:33:44 PM PDT 24 351515192 ps
T288 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2622518271 Aug 03 04:33:25 PM PDT 24 Aug 03 04:33:37 PM PDT 24 1023804657 ps
T289 /workspace/coverage/default/25.rom_ctrl_stress_all.1092825116 Aug 03 04:33:41 PM PDT 24 Aug 03 04:34:19 PM PDT 24 2422257394 ps
T290 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1976311193 Aug 03 04:33:33 PM PDT 24 Aug 03 04:33:52 PM PDT 24 386088631 ps
T291 /workspace/coverage/default/36.rom_ctrl_alert_test.269722804 Aug 03 04:33:54 PM PDT 24 Aug 03 04:34:02 PM PDT 24 1649212663 ps
T292 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3434799436 Aug 03 04:34:02 PM PDT 24 Aug 03 04:34:25 PM PDT 24 512286977 ps
T293 /workspace/coverage/default/21.rom_ctrl_stress_all.2301241493 Aug 03 04:33:30 PM PDT 24 Aug 03 04:34:00 PM PDT 24 3711212722 ps
T294 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3244809095 Aug 03 04:33:22 PM PDT 24 Aug 03 05:27:56 PM PDT 24 76623408627 ps
T295 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3981215851 Aug 03 04:34:31 PM PDT 24 Aug 03 04:34:49 PM PDT 24 2758734708 ps
T296 /workspace/coverage/default/3.rom_ctrl_alert_test.106639297 Aug 03 04:33:18 PM PDT 24 Aug 03 04:33:28 PM PDT 24 257705352 ps
T297 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2444246433 Aug 03 04:33:30 PM PDT 24 Aug 03 04:33:40 PM PDT 24 1741066706 ps
T298 /workspace/coverage/default/34.rom_ctrl_alert_test.3293039837 Aug 03 04:34:04 PM PDT 24 Aug 03 04:34:14 PM PDT 24 251229423 ps
T299 /workspace/coverage/default/6.rom_ctrl_alert_test.3688300053 Aug 03 04:33:15 PM PDT 24 Aug 03 04:33:24 PM PDT 24 971387572 ps
T300 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2414758206 Aug 03 04:33:21 PM PDT 24 Aug 03 04:37:23 PM PDT 24 13402755911 ps
T301 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1699829569 Aug 03 04:33:37 PM PDT 24 Aug 03 04:39:52 PM PDT 24 11256470527 ps
T302 /workspace/coverage/default/39.rom_ctrl_alert_test.1687363051 Aug 03 04:33:48 PM PDT 24 Aug 03 04:33:58 PM PDT 24 249954771 ps
T303 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3313564744 Aug 03 04:34:07 PM PDT 24 Aug 03 04:34:27 PM PDT 24 333865572 ps
T304 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3445115483 Aug 03 04:33:32 PM PDT 24 Aug 03 04:37:18 PM PDT 24 15950472865 ps
T305 /workspace/coverage/default/12.rom_ctrl_alert_test.418885172 Aug 03 04:33:24 PM PDT 24 Aug 03 04:33:39 PM PDT 24 1889053325 ps
T306 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2118464450 Aug 03 04:33:49 PM PDT 24 Aug 03 04:34:00 PM PDT 24 185627694 ps
T307 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2821964056 Aug 03 04:33:23 PM PDT 24 Aug 03 04:33:46 PM PDT 24 513493831 ps
T308 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3487750335 Aug 03 04:33:15 PM PDT 24 Aug 03 04:33:26 PM PDT 24 718830213 ps
T309 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2919637576 Aug 03 04:33:30 PM PDT 24 Aug 03 04:33:50 PM PDT 24 335652386 ps
T310 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2674050269 Aug 03 04:33:50 PM PDT 24 Aug 03 04:34:10 PM PDT 24 676565513 ps
T311 /workspace/coverage/default/8.rom_ctrl_stress_all.4108274291 Aug 03 04:33:26 PM PDT 24 Aug 03 04:33:45 PM PDT 24 531972938 ps
T312 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2124565183 Aug 03 04:33:25 PM PDT 24 Aug 03 04:33:49 PM PDT 24 2489963905 ps
T313 /workspace/coverage/default/27.rom_ctrl_stress_all.2930258109 Aug 03 04:33:50 PM PDT 24 Aug 03 04:34:41 PM PDT 24 1071263887 ps
T314 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.721579404 Aug 03 04:33:33 PM PDT 24 Aug 03 04:33:44 PM PDT 24 209762400 ps
T315 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1911395456 Aug 03 04:33:16 PM PDT 24 Aug 03 04:36:59 PM PDT 24 7546304413 ps
T316 /workspace/coverage/default/32.rom_ctrl_stress_all.3115067875 Aug 03 04:34:00 PM PDT 24 Aug 03 04:34:43 PM PDT 24 1695597355 ps
T317 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2982250697 Aug 03 04:33:47 PM PDT 24 Aug 03 04:34:10 PM PDT 24 2068931200 ps
T318 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.200014934 Aug 03 04:33:29 PM PDT 24 Aug 03 04:33:48 PM PDT 24 661296389 ps
T319 /workspace/coverage/default/11.rom_ctrl_alert_test.2882843904 Aug 03 04:33:25 PM PDT 24 Aug 03 04:33:33 PM PDT 24 1500337006 ps
T320 /workspace/coverage/default/37.rom_ctrl_alert_test.4109896379 Aug 03 04:33:47 PM PDT 24 Aug 03 04:33:57 PM PDT 24 1033934635 ps
T56 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2884377788 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:30 PM PDT 24 170915794 ps
T57 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.161800553 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:31 PM PDT 24 176154313 ps
T321 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2654496397 Aug 03 04:30:33 PM PDT 24 Aug 03 04:30:48 PM PDT 24 266449875 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1346916136 Aug 03 04:30:08 PM PDT 24 Aug 03 04:30:17 PM PDT 24 663897922 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1090881781 Aug 03 04:30:25 PM PDT 24 Aug 03 04:30:35 PM PDT 24 1366019991 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3580824654 Aug 03 04:30:03 PM PDT 24 Aug 03 04:30:11 PM PDT 24 339630433 ps
T322 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1650759081 Aug 03 04:30:01 PM PDT 24 Aug 03 04:30:09 PM PDT 24 1181168263 ps
T323 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.906425028 Aug 03 04:30:02 PM PDT 24 Aug 03 04:30:12 PM PDT 24 187721255 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2167805553 Aug 03 04:30:15 PM PDT 24 Aug 03 04:30:24 PM PDT 24 404295543 ps
T324 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2199764728 Aug 03 04:30:07 PM PDT 24 Aug 03 04:30:18 PM PDT 24 266398719 ps
T53 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.118424520 Aug 03 04:30:27 PM PDT 24 Aug 03 04:33:04 PM PDT 24 1236361515 ps
T325 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2697998199 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:31 PM PDT 24 3221182978 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1860665680 Aug 03 04:30:30 PM PDT 24 Aug 03 04:30:40 PM PDT 24 987061359 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2090474847 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:24 PM PDT 24 479572959 ps
T326 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1211802824 Aug 03 04:30:31 PM PDT 24 Aug 03 04:30:44 PM PDT 24 174351264 ps
T327 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.251506361 Aug 03 04:30:30 PM PDT 24 Aug 03 04:30:41 PM PDT 24 274416680 ps
T328 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.198526781 Aug 03 04:30:05 PM PDT 24 Aug 03 04:30:14 PM PDT 24 174679096 ps
T329 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.383894164 Aug 03 04:30:23 PM PDT 24 Aug 03 04:30:37 PM PDT 24 250466395 ps
T64 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2324139487 Aug 03 04:30:35 PM PDT 24 Aug 03 04:30:43 PM PDT 24 612065188 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2762073000 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:58 PM PDT 24 9215600995 ps
T330 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2948727492 Aug 03 04:30:07 PM PDT 24 Aug 03 04:30:20 PM PDT 24 173499203 ps
T54 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1662270425 Aug 03 04:30:14 PM PDT 24 Aug 03 04:31:37 PM PDT 24 358267088 ps
T331 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2757851360 Aug 03 04:30:35 PM PDT 24 Aug 03 04:30:44 PM PDT 24 180535660 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3037415513 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:19 PM PDT 24 255452612 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2949008443 Aug 03 04:30:28 PM PDT 24 Aug 03 04:30:37 PM PDT 24 174599721 ps
T75 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1192026183 Aug 03 04:30:28 PM PDT 24 Aug 03 04:31:05 PM PDT 24 2759977218 ps
T332 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2452852032 Aug 03 04:30:24 PM PDT 24 Aug 03 04:30:34 PM PDT 24 271632781 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3182251460 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:24 PM PDT 24 170303573 ps
T333 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3191606117 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:19 PM PDT 24 336737708 ps
T334 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.63534945 Aug 03 04:30:03 PM PDT 24 Aug 03 04:30:41 PM PDT 24 691922810 ps
T55 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1818885749 Aug 03 04:30:22 PM PDT 24 Aug 03 04:31:44 PM PDT 24 4180634353 ps
T77 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2518397539 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:31 PM PDT 24 259946296 ps
T335 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2678716711 Aug 03 04:30:10 PM PDT 24 Aug 03 04:30:22 PM PDT 24 339901302 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2860637422 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:32 PM PDT 24 517685915 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4290839559 Aug 03 04:30:14 PM PDT 24 Aug 03 04:32:48 PM PDT 24 759117839 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3820275639 Aug 03 04:30:37 PM PDT 24 Aug 03 04:30:50 PM PDT 24 259467284 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3204928274 Aug 03 04:30:42 PM PDT 24 Aug 03 04:30:52 PM PDT 24 519364298 ps
T336 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3629565289 Aug 03 04:30:20 PM PDT 24 Aug 03 04:30:30 PM PDT 24 1035842631 ps
T337 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2833875662 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:24 PM PDT 24 320184528 ps
T338 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.347419937 Aug 03 04:30:12 PM PDT 24 Aug 03 04:30:26 PM PDT 24 338844715 ps
T92 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4226427739 Aug 03 04:30:21 PM PDT 24 Aug 03 04:31:47 PM PDT 24 4329462778 ps
T90 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3118394906 Aug 03 04:30:18 PM PDT 24 Aug 03 04:30:56 PM PDT 24 6842252859 ps
T339 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1947933186 Aug 03 04:30:19 PM PDT 24 Aug 03 04:30:32 PM PDT 24 272379418 ps
T340 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4025267447 Aug 03 04:30:29 PM PDT 24 Aug 03 04:30:40 PM PDT 24 272090982 ps
T341 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3614429427 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:31 PM PDT 24 345845087 ps
T342 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1820000524 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:40 PM PDT 24 2073764208 ps
T343 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.836680445 Aug 03 04:30:10 PM PDT 24 Aug 03 04:30:18 PM PDT 24 751953136 ps
T344 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1640246403 Aug 03 04:30:25 PM PDT 24 Aug 03 04:30:35 PM PDT 24 526165113 ps
T345 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2995188513 Aug 03 04:30:08 PM PDT 24 Aug 03 04:30:18 PM PDT 24 507341423 ps
T346 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3031459728 Aug 03 04:30:23 PM PDT 24 Aug 03 04:30:31 PM PDT 24 176910621 ps
T347 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2195595588 Aug 03 04:30:05 PM PDT 24 Aug 03 04:30:14 PM PDT 24 1236892450 ps
T348 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2178707757 Aug 03 04:30:26 PM PDT 24 Aug 03 04:30:36 PM PDT 24 4960302053 ps
T349 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1975778085 Aug 03 04:30:11 PM PDT 24 Aug 03 04:30:21 PM PDT 24 1075849646 ps
T350 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4250072043 Aug 03 04:30:23 PM PDT 24 Aug 03 04:30:42 PM PDT 24 19910883548 ps
T351 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3115977390 Aug 03 04:30:27 PM PDT 24 Aug 03 04:30:40 PM PDT 24 689011593 ps
T98 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3398645647 Aug 03 04:30:22 PM PDT 24 Aug 03 04:32:55 PM PDT 24 299450479 ps
T352 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1420467448 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:17 PM PDT 24 920232779 ps
T78 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3183409034 Aug 03 04:30:45 PM PDT 24 Aug 03 04:30:55 PM PDT 24 508763749 ps
T353 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2094511350 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:24 PM PDT 24 941209208 ps
T354 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3275493576 Aug 03 04:30:32 PM PDT 24 Aug 03 04:30:40 PM PDT 24 873547803 ps
T355 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2436815538 Aug 03 04:30:26 PM PDT 24 Aug 03 04:30:36 PM PDT 24 497196368 ps
T356 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.864288471 Aug 03 04:30:25 PM PDT 24 Aug 03 04:30:34 PM PDT 24 692324934 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1167840182 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:22 PM PDT 24 254502550 ps
T358 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.846315115 Aug 03 04:30:25 PM PDT 24 Aug 03 04:30:36 PM PDT 24 917301879 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2802560818 Aug 03 04:30:16 PM PDT 24 Aug 03 04:30:26 PM PDT 24 262342105 ps
T360 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.689980934 Aug 03 04:30:15 PM PDT 24 Aug 03 04:30:25 PM PDT 24 224674737 ps
T361 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3586957992 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:26 PM PDT 24 2757087972 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1785556935 Aug 03 04:30:09 PM PDT 24 Aug 03 04:32:46 PM PDT 24 508832043 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2798368171 Aug 03 04:30:08 PM PDT 24 Aug 03 04:30:18 PM PDT 24 182481100 ps
T363 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2323137613 Aug 03 04:30:16 PM PDT 24 Aug 03 04:30:24 PM PDT 24 785518460 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3207279665 Aug 03 04:30:11 PM PDT 24 Aug 03 04:30:19 PM PDT 24 171308197 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3750466426 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:30 PM PDT 24 179649529 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1645694349 Aug 03 04:30:23 PM PDT 24 Aug 03 04:31:44 PM PDT 24 1156506523 ps
T367 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3080383287 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:34 PM PDT 24 179939200 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3647949221 Aug 03 04:30:38 PM PDT 24 Aug 03 04:30:49 PM PDT 24 1324322486 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3138138996 Aug 03 04:30:20 PM PDT 24 Aug 03 04:30:31 PM PDT 24 167548625 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3757180501 Aug 03 04:30:38 PM PDT 24 Aug 03 04:30:46 PM PDT 24 214185653 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1897649276 Aug 03 04:30:07 PM PDT 24 Aug 03 04:31:34 PM PDT 24 1097969203 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2741369305 Aug 03 04:30:31 PM PDT 24 Aug 03 04:31:51 PM PDT 24 890208010 ps
T96 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2256010142 Aug 03 04:30:30 PM PDT 24 Aug 03 04:33:07 PM PDT 24 435253804 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2557257435 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:36 PM PDT 24 360970879 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1204255 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:10 PM PDT 24 988929802 ps
T373 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.231372805 Aug 03 04:30:24 PM PDT 24 Aug 03 04:30:34 PM PDT 24 1126714506 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2609733511 Aug 03 04:30:45 PM PDT 24 Aug 03 04:30:55 PM PDT 24 1064716675 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3354427135 Aug 03 04:30:11 PM PDT 24 Aug 03 04:31:31 PM PDT 24 237464006 ps
T99 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1815796964 Aug 03 04:30:27 PM PDT 24 Aug 03 04:31:48 PM PDT 24 526182060 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3884812985 Aug 03 04:30:20 PM PDT 24 Aug 03 04:30:30 PM PDT 24 2053964855 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2561198949 Aug 03 04:30:07 PM PDT 24 Aug 03 04:30:16 PM PDT 24 1303031375 ps
T378 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1579359584 Aug 03 04:30:19 PM PDT 24 Aug 03 04:32:53 PM PDT 24 730950149 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1563757541 Aug 03 04:30:14 PM PDT 24 Aug 03 04:31:37 PM PDT 24 482602677 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1909686678 Aug 03 04:30:01 PM PDT 24 Aug 03 04:30:17 PM PDT 24 7068351111 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.808402522 Aug 03 04:30:04 PM PDT 24 Aug 03 04:30:14 PM PDT 24 1032096109 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1587223089 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:13 PM PDT 24 1042013088 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2111726355 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:27 PM PDT 24 532161533 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.530579572 Aug 03 04:30:16 PM PDT 24 Aug 03 04:30:26 PM PDT 24 2052268338 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3890959336 Aug 03 04:30:12 PM PDT 24 Aug 03 04:30:27 PM PDT 24 188791081 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1969810950 Aug 03 04:30:31 PM PDT 24 Aug 03 04:30:39 PM PDT 24 174304861 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1787211372 Aug 03 04:30:23 PM PDT 24 Aug 03 04:31:20 PM PDT 24 4304807119 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3538462724 Aug 03 04:30:19 PM PDT 24 Aug 03 04:30:31 PM PDT 24 178555149 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.363934825 Aug 03 04:30:11 PM PDT 24 Aug 03 04:30:21 PM PDT 24 917548281 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2098225556 Aug 03 04:30:09 PM PDT 24 Aug 03 04:31:29 PM PDT 24 1089459439 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4223846175 Aug 03 04:30:02 PM PDT 24 Aug 03 04:30:16 PM PDT 24 2101258052 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.148097807 Aug 03 04:30:08 PM PDT 24 Aug 03 04:30:16 PM PDT 24 340063709 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1580530118 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:33 PM PDT 24 790082052 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3422690130 Aug 03 04:30:40 PM PDT 24 Aug 03 04:30:49 PM PDT 24 339235750 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.982739808 Aug 03 04:30:42 PM PDT 24 Aug 03 04:30:51 PM PDT 24 791709943 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.371314196 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:34 PM PDT 24 581928317 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1781651814 Aug 03 04:30:19 PM PDT 24 Aug 03 04:30:27 PM PDT 24 320297576 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3772433879 Aug 03 04:30:12 PM PDT 24 Aug 03 04:32:47 PM PDT 24 464970033 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2885934571 Aug 03 04:30:28 PM PDT 24 Aug 03 04:31:50 PM PDT 24 688583489 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1887857860 Aug 03 04:30:12 PM PDT 24 Aug 03 04:30:20 PM PDT 24 387157949 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.41217059 Aug 03 04:30:23 PM PDT 24 Aug 03 04:30:32 PM PDT 24 231664349 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2133973655 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:27 PM PDT 24 254294943 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2968370844 Aug 03 04:30:11 PM PDT 24 Aug 03 04:30:20 PM PDT 24 360249814 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3093606296 Aug 03 04:30:00 PM PDT 24 Aug 03 04:30:09 PM PDT 24 338717658 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.206173746 Aug 03 04:30:15 PM PDT 24 Aug 03 04:32:47 PM PDT 24 1043770320 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.487569585 Aug 03 04:30:04 PM PDT 24 Aug 03 04:30:12 PM PDT 24 887995462 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.307882442 Aug 03 04:30:09 PM PDT 24 Aug 03 04:30:19 PM PDT 24 249504985 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4099909307 Aug 03 04:30:13 PM PDT 24 Aug 03 04:30:23 PM PDT 24 707801534 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1925345524 Aug 03 04:30:38 PM PDT 24 Aug 03 04:32:04 PM PDT 24 2555052083 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3905878566 Aug 03 04:30:21 PM PDT 24 Aug 03 04:30:34 PM PDT 24 872884127 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2789126913 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:27 PM PDT 24 377200467 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.552748216 Aug 03 04:30:11 PM PDT 24 Aug 03 04:30:20 PM PDT 24 260153259 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2951952010 Aug 03 04:30:24 PM PDT 24 Aug 03 04:30:40 PM PDT 24 527195107 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3450788686 Aug 03 04:30:26 PM PDT 24 Aug 03 04:30:39 PM PDT 24 689740691 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.747072775 Aug 03 04:30:26 PM PDT 24 Aug 03 04:30:35 PM PDT 24 175838811 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1778287463 Aug 03 04:30:24 PM PDT 24 Aug 03 04:30:35 PM PDT 24 184706304 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2363079894 Aug 03 04:30:29 PM PDT 24 Aug 03 04:30:43 PM PDT 24 4951872936 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3201034448 Aug 03 04:30:22 PM PDT 24 Aug 03 04:30:35 PM PDT 24 360512061 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3111505877 Aug 03 04:30:14 PM PDT 24 Aug 03 04:30:23 PM PDT 24 171128309 ps

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2366601043
Short name T2
Test name
Test status
Simulation time 104493131231 ps
CPU time 9671.9 seconds
Started Aug 03 04:33:28 PM PDT 24
Finished Aug 03 07:14:41 PM PDT 24
Peak memory 236048 kb
Host smart-918b1457-e4e7-4bcc-9942-547fa2dd1ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366601043 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2366601043
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4090015865
Short name T34
Test name
Test status
Simulation time 14174991726 ps
CPU time 220.11 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 04:37:36 PM PDT 24
Peak memory 226248 kb
Host smart-3a208aa9-5b01-4088-a294-dc76a81a30f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090015865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4090015865
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3096606831
Short name T5
Test name
Test status
Simulation time 44299220510 ps
CPU time 210.73 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 237416 kb
Host smart-25df6968-0109-4e30-b5da-493f3d7f0357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096606831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3096606831
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4290839559
Short name T91
Test name
Test status
Simulation time 759117839 ps
CPU time 153.91 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:32:48 PM PDT 24
Peak memory 214112 kb
Host smart-6b3025df-18a8-4487-84fd-dc72b39e930b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290839559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4290839559
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4102677037
Short name T15
Test name
Test status
Simulation time 622516377 ps
CPU time 116.82 seconds
Started Aug 03 04:33:21 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 239988 kb
Host smart-89f4d963-218f-4c13-9ed7-d57dc1c47103
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102677037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4102677037
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2762073000
Short name T65
Test name
Test status
Simulation time 9215600995 ps
CPU time 43.64 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:58 PM PDT 24
Peak memory 214416 kb
Host smart-deeb8f9d-8850-42ba-9a49-ec43a43b153d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762073000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2762073000
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1446248638
Short name T1
Test name
Test status
Simulation time 557389315 ps
CPU time 35.05 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:34:24 PM PDT 24
Peak memory 219580 kb
Host smart-e9147270-cf15-4a2f-9d7e-ffd90521e8cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446248638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1446248638
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2981283754
Short name T104
Test name
Test status
Simulation time 4092139628 ps
CPU time 14.71 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:34:02 PM PDT 24
Peak memory 219104 kb
Host smart-4856fcbf-218b-455d-a54e-25b76d682d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981283754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2981283754
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2256010142
Short name T96
Test name
Test status
Simulation time 435253804 ps
CPU time 156.38 seconds
Started Aug 03 04:30:30 PM PDT 24
Finished Aug 03 04:33:07 PM PDT 24
Peak memory 214352 kb
Host smart-b36f2269-240e-4252-8ca6-539d2399d0a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256010142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2256010142
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1171353271
Short name T4
Test name
Test status
Simulation time 2061201991 ps
CPU time 22.96 seconds
Started Aug 03 04:33:46 PM PDT 24
Finished Aug 03 04:34:09 PM PDT 24
Peak memory 220000 kb
Host smart-31165a9d-31fd-4767-9e1a-19eafca3dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171353271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1171353271
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1676198244
Short name T42
Test name
Test status
Simulation time 1030854752 ps
CPU time 22.84 seconds
Started Aug 03 04:33:17 PM PDT 24
Finished Aug 03 04:33:40 PM PDT 24
Peak memory 220084 kb
Host smart-329ca58c-60bb-4d6d-9e9d-6d66315a6cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676198244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1676198244
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2727313164
Short name T119
Test name
Test status
Simulation time 408202546 ps
CPU time 32.05 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:34:05 PM PDT 24
Peak memory 220044 kb
Host smart-deb38905-f29f-4258-ae63-c36bff72ba12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727313164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2727313164
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.118424520
Short name T53
Test name
Test status
Simulation time 1236361515 ps
CPU time 156.74 seconds
Started Aug 03 04:30:27 PM PDT 24
Finished Aug 03 04:33:04 PM PDT 24
Peak memory 215156 kb
Host smart-e37f575b-3f96-4bbb-a7d9-b908e364e9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118424520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.118424520
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.840833572
Short name T40
Test name
Test status
Simulation time 129834367886 ps
CPU time 2282.39 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 05:11:55 PM PDT 24
Peak memory 249632 kb
Host smart-9791b009-5ca8-4919-ace5-4bc6d895fe61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840833572 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.840833572
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4226427739
Short name T92
Test name
Test status
Simulation time 4329462778 ps
CPU time 85.69 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:31:47 PM PDT 24
Peak memory 214352 kb
Host smart-926fd1be-6340-42dc-9365-10cef32771c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226427739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4226427739
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.659108150
Short name T49
Test name
Test status
Simulation time 31707053977 ps
CPU time 1293.23 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:54:56 PM PDT 24
Peak memory 236680 kb
Host smart-25979af5-3cb1-452b-8e8b-f9f2e1c661bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659108150 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.659108150
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3757180501
Short name T79
Test name
Test status
Simulation time 214185653 ps
CPU time 8.09 seconds
Started Aug 03 04:30:38 PM PDT 24
Finished Aug 03 04:30:46 PM PDT 24
Peak memory 210904 kb
Host smart-b482c8f2-b37e-49c2-b25a-a6742ae87957
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757180501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3757180501
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.363934825
Short name T388
Test name
Test status
Simulation time 917548281 ps
CPU time 9.94 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:21 PM PDT 24
Peak memory 210744 kb
Host smart-4e250f40-ba4f-4450-9447-27f68de6c899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363934825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.363934825
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.198526781
Short name T328
Test name
Test status
Simulation time 174679096 ps
CPU time 8.37 seconds
Started Aug 03 04:30:05 PM PDT 24
Finished Aug 03 04:30:14 PM PDT 24
Peak memory 210760 kb
Host smart-7ac679a3-65f9-4c0a-a60e-60c7344c93c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198526781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.198526781
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4250072043
Short name T350
Test name
Test status
Simulation time 19910883548 ps
CPU time 18.46 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:30:42 PM PDT 24
Peak memory 211008 kb
Host smart-71c2c0f3-de56-4c6e-9d2f-d298e708a3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250072043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4250072043
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.487569585
Short name T404
Test name
Test status
Simulation time 887995462 ps
CPU time 8.56 seconds
Started Aug 03 04:30:04 PM PDT 24
Finished Aug 03 04:30:12 PM PDT 24
Peak memory 214000 kb
Host smart-86fed3d4-436a-4ad2-9764-37df2b433ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487569585 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.487569585
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2195595588
Short name T347
Test name
Test status
Simulation time 1236892450 ps
CPU time 9.71 seconds
Started Aug 03 04:30:05 PM PDT 24
Finished Aug 03 04:30:14 PM PDT 24
Peak memory 211184 kb
Host smart-d521f0ad-51dc-4d2c-83f4-8bd98015b3ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195595588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2195595588
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3093606296
Short name T403
Test name
Test status
Simulation time 338717658 ps
CPU time 8.16 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:09 PM PDT 24
Peak memory 210676 kb
Host smart-68b36ce1-df19-4922-9bce-731ba058260a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093606296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3093606296
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1909686678
Short name T380
Test name
Test status
Simulation time 7068351111 ps
CPU time 15.04 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:17 PM PDT 24
Peak memory 211052 kb
Host smart-5cd23985-5f7e-4295-9b5e-3957b863e6ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909686678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1909686678
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.63534945
Short name T334
Test name
Test status
Simulation time 691922810 ps
CPU time 37.73 seconds
Started Aug 03 04:30:03 PM PDT 24
Finished Aug 03 04:30:41 PM PDT 24
Peak memory 213888 kb
Host smart-148e7330-4722-424f-9303-168cc5c4333f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63534945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pass
thru_mem_tl_intg_err.63534945
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4223846175
Short name T390
Test name
Test status
Simulation time 2101258052 ps
CPU time 13.59 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:16 PM PDT 24
Peak memory 212916 kb
Host smart-9c553d62-37dc-45a0-9b0e-ba1377e0b8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223846175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4223846175
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2654496397
Short name T321
Test name
Test status
Simulation time 266449875 ps
CPU time 15.1 seconds
Started Aug 03 04:30:33 PM PDT 24
Finished Aug 03 04:30:48 PM PDT 24
Peak memory 218960 kb
Host smart-d2418b58-6860-4b8a-9115-043db3a54240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654496397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2654496397
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1897649276
Short name T370
Test name
Test status
Simulation time 1097969203 ps
CPU time 87.51 seconds
Started Aug 03 04:30:07 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 213364 kb
Host smart-c22f49ff-f451-4643-a12d-a9213fdd1ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897649276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1897649276
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1204255
Short name T372
Test name
Test status
Simulation time 988929802 ps
CPU time 9.95 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:10 PM PDT 24
Peak memory 211072 kb
Host smart-6ce48be4-4998-486b-ac84-715206fae746
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bas
h.1204255
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1587223089
Short name T382
Test name
Test status
Simulation time 1042013088 ps
CPU time 13.41 seconds
Started Aug 03 04:30:00 PM PDT 24
Finished Aug 03 04:30:13 PM PDT 24
Peak memory 210660 kb
Host smart-d3358705-dc85-4b61-aaf6-1f1ee1c229d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587223089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1587223089
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.906425028
Short name T323
Test name
Test status
Simulation time 187721255 ps
CPU time 9.75 seconds
Started Aug 03 04:30:02 PM PDT 24
Finished Aug 03 04:30:12 PM PDT 24
Peak memory 219068 kb
Host smart-a0fbaa6e-0198-4aa0-bba9-784754fee59d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906425028 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.906425028
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3580824654
Short name T60
Test name
Test status
Simulation time 339630433 ps
CPU time 8.35 seconds
Started Aug 03 04:30:03 PM PDT 24
Finished Aug 03 04:30:11 PM PDT 24
Peak memory 211168 kb
Host smart-b44c58bf-37e0-44d2-9885-365e16be4328
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580824654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3580824654
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.808402522
Short name T381
Test name
Test status
Simulation time 1032096109 ps
CPU time 9.99 seconds
Started Aug 03 04:30:04 PM PDT 24
Finished Aug 03 04:30:14 PM PDT 24
Peak memory 210672 kb
Host smart-fee651cf-f519-45bb-a90b-64e0db391ecc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808402522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.808402522
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1650759081
Short name T322
Test name
Test status
Simulation time 1181168263 ps
CPU time 7.98 seconds
Started Aug 03 04:30:01 PM PDT 24
Finished Aug 03 04:30:09 PM PDT 24
Peak memory 210600 kb
Host smart-3167fa96-cee6-4745-9d2a-2e69fd55c9ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650759081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1650759081
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3614429427
Short name T341
Test name
Test status
Simulation time 345845087 ps
CPU time 8.13 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 211412 kb
Host smart-c60375b5-1185-49d9-bf14-e64649befbb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614429427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3614429427
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2678716711
Short name T335
Test name
Test status
Simulation time 339901302 ps
CPU time 11.77 seconds
Started Aug 03 04:30:10 PM PDT 24
Finished Aug 03 04:30:22 PM PDT 24
Peak memory 217620 kb
Host smart-a8f99f65-3fcc-4c4a-a13c-77e41c098271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678716711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2678716711
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3772433879
Short name T397
Test name
Test status
Simulation time 464970033 ps
CPU time 155.33 seconds
Started Aug 03 04:30:12 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 214276 kb
Host smart-b1a8c1b7-aaa4-40cc-83bd-41ffa3749001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772433879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3772433879
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2452852032
Short name T332
Test name
Test status
Simulation time 271632781 ps
CPU time 10.78 seconds
Started Aug 03 04:30:24 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 217632 kb
Host smart-018a39a6-5f4e-44f6-8acb-22591eee839d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452852032 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2452852032
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3183409034
Short name T78
Test name
Test status
Simulation time 508763749 ps
CPU time 9.89 seconds
Started Aug 03 04:30:45 PM PDT 24
Finished Aug 03 04:30:55 PM PDT 24
Peak memory 211080 kb
Host smart-b9a0e12d-5017-4df9-a434-d618a96ed2d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183409034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3183409034
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2884377788
Short name T56
Test name
Test status
Simulation time 170915794 ps
CPU time 8.6 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:30 PM PDT 24
Peak memory 211496 kb
Host smart-74a54e06-6af6-491b-9608-35f035043d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884377788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2884377788
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3138138996
Short name T369
Test name
Test status
Simulation time 167548625 ps
CPU time 11.1 seconds
Started Aug 03 04:30:20 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 217160 kb
Host smart-3bd340f2-6070-45b0-8564-90efa058bd86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138138996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3138138996
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3031459728
Short name T346
Test name
Test status
Simulation time 176910621 ps
CPU time 8.34 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 215068 kb
Host smart-29442f50-e7cd-4b90-ae9d-875747472881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031459728 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3031459728
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2178707757
Short name T348
Test name
Test status
Simulation time 4960302053 ps
CPU time 10.18 seconds
Started Aug 03 04:30:26 PM PDT 24
Finished Aug 03 04:30:36 PM PDT 24
Peak memory 211688 kb
Host smart-6f1cdfdf-fb89-4d12-b9e9-8a7013f4689f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178707757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2178707757
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1192026183
Short name T75
Test name
Test status
Simulation time 2759977218 ps
CPU time 37.08 seconds
Started Aug 03 04:30:28 PM PDT 24
Finished Aug 03 04:31:05 PM PDT 24
Peak memory 214020 kb
Host smart-454b1b0d-5ac7-4c95-9acc-b47e6d18ab56
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192026183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1192026183
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3080383287
Short name T367
Test name
Test status
Simulation time 179939200 ps
CPU time 12.13 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 211736 kb
Host smart-0786c548-be2c-4e7e-a973-939375d5b47f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080383287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3080383287
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.383894164
Short name T329
Test name
Test status
Simulation time 250466395 ps
CPU time 14.5 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:30:37 PM PDT 24
Peak memory 219052 kb
Host smart-4bf1ac04-c4b0-4f8e-9bf1-5a974c9f98ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383894164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.383894164
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1925345524
Short name T97
Test name
Test status
Simulation time 2555052083 ps
CPU time 86.2 seconds
Started Aug 03 04:30:38 PM PDT 24
Finished Aug 03 04:32:04 PM PDT 24
Peak memory 219056 kb
Host smart-ce9f07a7-2a89-4808-95af-da97d7cac6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925345524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1925345524
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.846315115
Short name T358
Test name
Test status
Simulation time 917301879 ps
CPU time 11.32 seconds
Started Aug 03 04:30:25 PM PDT 24
Finished Aug 03 04:30:36 PM PDT 24
Peak memory 217892 kb
Host smart-953dc19b-dde0-4461-8f32-c4ea9c34c4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846315115 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.846315115
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.161800553
Short name T57
Test name
Test status
Simulation time 176154313 ps
CPU time 8.19 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 210744 kb
Host smart-eced4d7a-0bcb-4fa1-a9df-4c562c6b0da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161800553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.161800553
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2860637422
Short name T82
Test name
Test status
Simulation time 517685915 ps
CPU time 9.67 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:32 PM PDT 24
Peak memory 211304 kb
Host smart-8f9d49dd-b97a-4d8e-8767-557b87c860b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860637422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2860637422
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1947933186
Short name T339
Test name
Test status
Simulation time 272379418 ps
CPU time 12.99 seconds
Started Aug 03 04:30:19 PM PDT 24
Finished Aug 03 04:30:32 PM PDT 24
Peak memory 218748 kb
Host smart-ff7a95fe-4b56-4973-9866-00ccf740980e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947933186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1947933186
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2885934571
Short name T398
Test name
Test status
Simulation time 688583489 ps
CPU time 81.48 seconds
Started Aug 03 04:30:28 PM PDT 24
Finished Aug 03 04:31:50 PM PDT 24
Peak memory 213548 kb
Host smart-3ec0be25-034f-4923-bc7f-19afa5c3be4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885934571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2885934571
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2609733511
Short name T374
Test name
Test status
Simulation time 1064716675 ps
CPU time 10.04 seconds
Started Aug 03 04:30:45 PM PDT 24
Finished Aug 03 04:30:55 PM PDT 24
Peak memory 215844 kb
Host smart-53c07af3-eff1-4e1a-9246-8a08d982a2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609733511 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2609733511
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1090881781
Short name T85
Test name
Test status
Simulation time 1366019991 ps
CPU time 9.94 seconds
Started Aug 03 04:30:25 PM PDT 24
Finished Aug 03 04:30:35 PM PDT 24
Peak memory 211248 kb
Host smart-772227a6-7718-4d17-ad76-6c2afc555fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090881781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1090881781
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3422690130
Short name T393
Test name
Test status
Simulation time 339235750 ps
CPU time 8.39 seconds
Started Aug 03 04:30:40 PM PDT 24
Finished Aug 03 04:30:49 PM PDT 24
Peak memory 211324 kb
Host smart-43ab4427-6af0-4d50-80ee-63a50da8baf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422690130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3422690130
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2557257435
Short name T371
Test name
Test status
Simulation time 360970879 ps
CPU time 13.06 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:36 PM PDT 24
Peak memory 219292 kb
Host smart-c662fc75-0f85-4f5f-80ae-35c1f970c114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557257435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2557257435
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.371314196
Short name T395
Test name
Test status
Simulation time 581928317 ps
CPU time 11.18 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 217004 kb
Host smart-fcd2fe9c-1117-43ae-ae1e-8b1bded910ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371314196 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.371314196
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3629565289
Short name T336
Test name
Test status
Simulation time 1035842631 ps
CPU time 9.73 seconds
Started Aug 03 04:30:20 PM PDT 24
Finished Aug 03 04:30:30 PM PDT 24
Peak memory 211096 kb
Host smart-fb915a8e-cfd2-4d90-b4be-2b0d9475d500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629565289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3629565289
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.864288471
Short name T356
Test name
Test status
Simulation time 692324934 ps
CPU time 8.48 seconds
Started Aug 03 04:30:25 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 211612 kb
Host smart-9c0b450e-24a1-450a-b643-2b0be0024549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864288471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.864288471
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1778287463
Short name T412
Test name
Test status
Simulation time 184706304 ps
CPU time 11.3 seconds
Started Aug 03 04:30:24 PM PDT 24
Finished Aug 03 04:30:35 PM PDT 24
Peak memory 218416 kb
Host smart-493cea46-75a1-4913-ac57-1700aee8a522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778287463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1778287463
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3398645647
Short name T98
Test name
Test status
Simulation time 299450479 ps
CPU time 152.22 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:32:55 PM PDT 24
Peak memory 214156 kb
Host smart-803d02f6-f1fd-4546-9251-fcccc6f1849f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398645647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3398645647
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2757851360
Short name T331
Test name
Test status
Simulation time 180535660 ps
CPU time 8.77 seconds
Started Aug 03 04:30:35 PM PDT 24
Finished Aug 03 04:30:44 PM PDT 24
Peak memory 216656 kb
Host smart-d6384dcd-f893-46c7-a80d-0d17b7106bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757851360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2757851360
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.231372805
Short name T373
Test name
Test status
Simulation time 1126714506 ps
CPU time 9.72 seconds
Started Aug 03 04:30:24 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 211096 kb
Host smart-ea34da4a-359b-455d-8d71-1febda9c60d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231372805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.231372805
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1787211372
Short name T386
Test name
Test status
Simulation time 4304807119 ps
CPU time 56.24 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 215236 kb
Host smart-195267ee-8738-486a-951c-c1c820cb5171
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787211372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1787211372
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3884812985
Short name T376
Test name
Test status
Simulation time 2053964855 ps
CPU time 9.89 seconds
Started Aug 03 04:30:20 PM PDT 24
Finished Aug 03 04:30:30 PM PDT 24
Peak memory 211548 kb
Host smart-9a4f02ba-9143-479f-953f-8dae7d30a728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884812985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3884812985
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3115977390
Short name T351
Test name
Test status
Simulation time 689011593 ps
CPU time 12.52 seconds
Started Aug 03 04:30:27 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 219040 kb
Host smart-964d4607-3ed9-45b3-920c-8580e619960c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115977390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3115977390
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1818885749
Short name T55
Test name
Test status
Simulation time 4180634353 ps
CPU time 81.49 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:31:44 PM PDT 24
Peak memory 213000 kb
Host smart-8e3e3740-b92e-4a77-848c-575bc0c87e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818885749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1818885749
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3647949221
Short name T368
Test name
Test status
Simulation time 1324322486 ps
CPU time 10.5 seconds
Started Aug 03 04:30:38 PM PDT 24
Finished Aug 03 04:30:49 PM PDT 24
Peak memory 215816 kb
Host smart-0680c572-c30b-426c-bf78-1e8707015e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647949221 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3647949221
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3275493576
Short name T354
Test name
Test status
Simulation time 873547803 ps
CPU time 8.06 seconds
Started Aug 03 04:30:32 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 211076 kb
Host smart-233f88ed-d6d8-47b3-b342-7c022f7b2740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275493576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3275493576
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3204928274
Short name T84
Test name
Test status
Simulation time 519364298 ps
CPU time 9.91 seconds
Started Aug 03 04:30:42 PM PDT 24
Finished Aug 03 04:30:52 PM PDT 24
Peak memory 211544 kb
Host smart-d715647e-0d30-45bc-aaca-8fa5cd727196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204928274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3204928274
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1580530118
Short name T392
Test name
Test status
Simulation time 790082052 ps
CPU time 12.19 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:33 PM PDT 24
Peak memory 217524 kb
Host smart-ac406e8c-0236-4318-9861-4fc3db2ac649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580530118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1580530118
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1579359584
Short name T378
Test name
Test status
Simulation time 730950149 ps
CPU time 153.84 seconds
Started Aug 03 04:30:19 PM PDT 24
Finished Aug 03 04:32:53 PM PDT 24
Peak memory 214232 kb
Host smart-51bf6469-bdee-4d20-923b-262479bf3408
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579359584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1579359584
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4025267447
Short name T340
Test name
Test status
Simulation time 272090982 ps
CPU time 10.9 seconds
Started Aug 03 04:30:29 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 217720 kb
Host smart-71387548-19a5-4db5-ad4e-03e7df89807e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025267447 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4025267447
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2436815538
Short name T355
Test name
Test status
Simulation time 497196368 ps
CPU time 9.78 seconds
Started Aug 03 04:30:26 PM PDT 24
Finished Aug 03 04:30:36 PM PDT 24
Peak memory 210740 kb
Host smart-9182c046-e414-4477-97f3-f681c8a09030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436815538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2436815538
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2949008443
Short name T67
Test name
Test status
Simulation time 174599721 ps
CPU time 8.33 seconds
Started Aug 03 04:30:28 PM PDT 24
Finished Aug 03 04:30:37 PM PDT 24
Peak memory 211596 kb
Host smart-c87e6e1d-2cbc-4048-be3a-e448a08d25eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949008443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2949008443
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3450788686
Short name T410
Test name
Test status
Simulation time 689740691 ps
CPU time 13.57 seconds
Started Aug 03 04:30:26 PM PDT 24
Finished Aug 03 04:30:39 PM PDT 24
Peak memory 219024 kb
Host smart-62a13466-cfb8-4dc1-ab3a-9738086d306e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450788686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3450788686
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.747072775
Short name T411
Test name
Test status
Simulation time 175838811 ps
CPU time 8.69 seconds
Started Aug 03 04:30:26 PM PDT 24
Finished Aug 03 04:30:35 PM PDT 24
Peak memory 215824 kb
Host smart-6ef3e3a0-0305-453c-8224-fe183db24135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747072775 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.747072775
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1969810950
Short name T385
Test name
Test status
Simulation time 174304861 ps
CPU time 8.07 seconds
Started Aug 03 04:30:31 PM PDT 24
Finished Aug 03 04:30:39 PM PDT 24
Peak memory 210952 kb
Host smart-b8f4f84c-4d21-47c8-9c1a-934110e83805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969810950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1969810950
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2324139487
Short name T64
Test name
Test status
Simulation time 612065188 ps
CPU time 8.06 seconds
Started Aug 03 04:30:35 PM PDT 24
Finished Aug 03 04:30:43 PM PDT 24
Peak memory 211200 kb
Host smart-92ee31fd-0506-4a98-8fd8-e904ded16244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324139487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2324139487
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1211802824
Short name T326
Test name
Test status
Simulation time 174351264 ps
CPU time 12.88 seconds
Started Aug 03 04:30:31 PM PDT 24
Finished Aug 03 04:30:44 PM PDT 24
Peak memory 219160 kb
Host smart-fb5e0fda-a7c5-4466-9bd3-e33022358545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211802824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1211802824
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2741369305
Short name T93
Test name
Test status
Simulation time 890208010 ps
CPU time 79.61 seconds
Started Aug 03 04:30:31 PM PDT 24
Finished Aug 03 04:31:51 PM PDT 24
Peak memory 213860 kb
Host smart-6e1ca3ad-7b02-4040-bc1c-06ad64d30b79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741369305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2741369305
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.251506361
Short name T327
Test name
Test status
Simulation time 274416680 ps
CPU time 11.26 seconds
Started Aug 03 04:30:30 PM PDT 24
Finished Aug 03 04:30:41 PM PDT 24
Peak memory 217220 kb
Host smart-2185d2c5-65c7-4243-b926-76240511bef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251506361 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.251506361
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.982739808
Short name T394
Test name
Test status
Simulation time 791709943 ps
CPU time 8.21 seconds
Started Aug 03 04:30:42 PM PDT 24
Finished Aug 03 04:30:51 PM PDT 24
Peak memory 210896 kb
Host smart-2f789def-9b34-4707-928d-e75994c8b17f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982739808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.982739808
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3820275639
Short name T83
Test name
Test status
Simulation time 259467284 ps
CPU time 13.56 seconds
Started Aug 03 04:30:37 PM PDT 24
Finished Aug 03 04:30:50 PM PDT 24
Peak memory 212552 kb
Host smart-a1325208-06e5-4de6-ab3d-f27d1ee4a043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820275639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3820275639
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2363079894
Short name T413
Test name
Test status
Simulation time 4951872936 ps
CPU time 14.4 seconds
Started Aug 03 04:30:29 PM PDT 24
Finished Aug 03 04:30:43 PM PDT 24
Peak memory 219064 kb
Host smart-717e4d73-c26e-4ad5-9aac-7c2444b9564a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363079894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2363079894
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1815796964
Short name T99
Test name
Test status
Simulation time 526182060 ps
CPU time 81.17 seconds
Started Aug 03 04:30:27 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 212600 kb
Host smart-0cbe9892-ba11-43cb-a215-837c83fa1988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815796964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1815796964
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3191606117
Short name T333
Test name
Test status
Simulation time 336737708 ps
CPU time 10.23 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:19 PM PDT 24
Peak memory 210752 kb
Host smart-c291a974-0342-4d2f-878b-51cf653473f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191606117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3191606117
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2968370844
Short name T402
Test name
Test status
Simulation time 360249814 ps
CPU time 8.59 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:20 PM PDT 24
Peak memory 210808 kb
Host smart-d49b8097-aa5a-4667-ae5f-a32f918875f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968370844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2968370844
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3750466426
Short name T365
Test name
Test status
Simulation time 179649529 ps
CPU time 15.42 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:30 PM PDT 24
Peak memory 211992 kb
Host smart-64921ca1-5ea7-4c6f-aa34-781bf7b97ff1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750466426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3750466426
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2798368171
Short name T362
Test name
Test status
Simulation time 182481100 ps
CPU time 9.52 seconds
Started Aug 03 04:30:08 PM PDT 24
Finished Aug 03 04:30:18 PM PDT 24
Peak memory 217704 kb
Host smart-8baa2a41-b7c0-43b6-8319-780eb4a3be93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798368171 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2798368171
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2561198949
Short name T377
Test name
Test status
Simulation time 1303031375 ps
CPU time 9.51 seconds
Started Aug 03 04:30:07 PM PDT 24
Finished Aug 03 04:30:16 PM PDT 24
Peak memory 211092 kb
Host smart-c7508aca-6446-47d1-8324-224c0a7b48d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561198949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2561198949
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1975778085
Short name T349
Test name
Test status
Simulation time 1075849646 ps
CPU time 9.83 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:21 PM PDT 24
Peak memory 210592 kb
Host smart-35d981ae-324f-4c19-bc73-88f17b45b87f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975778085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1975778085
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3207279665
Short name T364
Test name
Test status
Simulation time 171308197 ps
CPU time 8.01 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:19 PM PDT 24
Peak memory 210600 kb
Host smart-3f92ef40-43f8-4ef0-b997-b4a671d6af02
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207279665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3207279665
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2167805553
Short name T61
Test name
Test status
Simulation time 404295543 ps
CPU time 8.41 seconds
Started Aug 03 04:30:15 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 211496 kb
Host smart-30208669-0308-4c03-8e03-25ed3a66b19e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167805553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2167805553
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.347419937
Short name T338
Test name
Test status
Simulation time 338844715 ps
CPU time 13.36 seconds
Started Aug 03 04:30:12 PM PDT 24
Finished Aug 03 04:30:26 PM PDT 24
Peak memory 219016 kb
Host smart-12beb2ff-ce28-4600-86a3-5afe724208d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347419937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.347419937
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1785556935
Short name T95
Test name
Test status
Simulation time 508832043 ps
CPU time 156.52 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 214196 kb
Host smart-0696c2f0-e4fa-40f6-8a8d-d2c65feb3387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785556935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1785556935
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3037415513
Short name T66
Test name
Test status
Simulation time 255452612 ps
CPU time 10.09 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:19 PM PDT 24
Peak memory 210824 kb
Host smart-c0bb2eb6-2d50-4468-a7dd-57fdf217da61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037415513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3037415513
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1346916136
Short name T58
Test name
Test status
Simulation time 663897922 ps
CPU time 8.76 seconds
Started Aug 03 04:30:08 PM PDT 24
Finished Aug 03 04:30:17 PM PDT 24
Peak memory 211012 kb
Host smart-3bc25dde-dcfa-433b-8519-3392543f6cbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346916136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1346916136
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3182251460
Short name T76
Test name
Test status
Simulation time 170303573 ps
CPU time 15.34 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 211248 kb
Host smart-5fd9e930-4b23-4cc1-8f62-8bcd46f12b53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182251460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3182251460
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2199764728
Short name T324
Test name
Test status
Simulation time 266398719 ps
CPU time 10.52 seconds
Started Aug 03 04:30:07 PM PDT 24
Finished Aug 03 04:30:18 PM PDT 24
Peak memory 217536 kb
Host smart-faf1563d-e48f-40be-bf2b-e2bb9a0742c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199764728 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2199764728
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.148097807
Short name T391
Test name
Test status
Simulation time 340063709 ps
CPU time 8.12 seconds
Started Aug 03 04:30:08 PM PDT 24
Finished Aug 03 04:30:16 PM PDT 24
Peak memory 210748 kb
Host smart-c147fd5e-db95-4004-885a-5647f1952ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148097807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.148097807
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1887857860
Short name T399
Test name
Test status
Simulation time 387157949 ps
CPU time 8.04 seconds
Started Aug 03 04:30:12 PM PDT 24
Finished Aug 03 04:30:20 PM PDT 24
Peak memory 210664 kb
Host smart-7e061cd4-b609-4298-8d39-7778ce340a30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887857860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1887857860
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2995188513
Short name T345
Test name
Test status
Simulation time 507341423 ps
CPU time 10.24 seconds
Started Aug 03 04:30:08 PM PDT 24
Finished Aug 03 04:30:18 PM PDT 24
Peak memory 210612 kb
Host smart-2bf49a28-ade1-49cc-83cb-a1594f4ab7e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995188513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2995188513
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1420467448
Short name T352
Test name
Test status
Simulation time 920232779 ps
CPU time 8.38 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:17 PM PDT 24
Peak memory 211456 kb
Host smart-a6c7f61d-2e43-4b90-91a2-5fbdd5cbb310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420467448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1420467448
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1167840182
Short name T357
Test name
Test status
Simulation time 254502550 ps
CPU time 12.83 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:22 PM PDT 24
Peak memory 217456 kb
Host smart-7f4afec7-c3f4-4283-954f-8d63e94127ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167840182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1167840182
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2098225556
Short name T389
Test name
Test status
Simulation time 1089459439 ps
CPU time 79.45 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 213800 kb
Host smart-76f61543-5cab-475b-b137-e5617ce9c20e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098225556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2098225556
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1860665680
Short name T62
Test name
Test status
Simulation time 987061359 ps
CPU time 9.94 seconds
Started Aug 03 04:30:30 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 210788 kb
Host smart-57c84f83-3072-4246-9245-e5058ae44db9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860665680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1860665680
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.307882442
Short name T81
Test name
Test status
Simulation time 249504985 ps
CPU time 9.94 seconds
Started Aug 03 04:30:09 PM PDT 24
Finished Aug 03 04:30:19 PM PDT 24
Peak memory 210796 kb
Host smart-7bfb8ae9-1a38-4360-af90-e8fe851206e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307882442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.307882442
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3890959336
Short name T384
Test name
Test status
Simulation time 188791081 ps
CPU time 15.61 seconds
Started Aug 03 04:30:12 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 212008 kb
Host smart-23ba7991-bd19-403d-8bf7-a710b72fe993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890959336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3890959336
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2802560818
Short name T359
Test name
Test status
Simulation time 262342105 ps
CPU time 10.36 seconds
Started Aug 03 04:30:16 PM PDT 24
Finished Aug 03 04:30:26 PM PDT 24
Peak memory 216844 kb
Host smart-fe084fa3-5f5e-400f-9e75-0689536a5531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802560818 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2802560818
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.530579572
Short name T80
Test name
Test status
Simulation time 2052268338 ps
CPU time 9.98 seconds
Started Aug 03 04:30:16 PM PDT 24
Finished Aug 03 04:30:26 PM PDT 24
Peak memory 210872 kb
Host smart-d1ac0537-bec4-4afc-9ea4-69a532b6594e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530579572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.530579572
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.552748216
Short name T408
Test name
Test status
Simulation time 260153259 ps
CPU time 9.44 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:30:20 PM PDT 24
Peak memory 210592 kb
Host smart-3e7b0319-b729-42eb-87d4-1e602bb357ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552748216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.552748216
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.836680445
Short name T343
Test name
Test status
Simulation time 751953136 ps
CPU time 8.04 seconds
Started Aug 03 04:30:10 PM PDT 24
Finished Aug 03 04:30:18 PM PDT 24
Peak memory 210632 kb
Host smart-ab5bd50e-d494-4069-884f-c140dd069bfb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836680445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
836680445
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2090474847
Short name T63
Test name
Test status
Simulation time 479572959 ps
CPU time 9.71 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 211328 kb
Host smart-ba9e2fad-c0ad-4bce-a256-0c6571802a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090474847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2090474847
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2948727492
Short name T330
Test name
Test status
Simulation time 173499203 ps
CPU time 13.43 seconds
Started Aug 03 04:30:07 PM PDT 24
Finished Aug 03 04:30:20 PM PDT 24
Peak memory 219144 kb
Host smart-78325852-04db-4990-a3cc-33b4edc9cb32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948727492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2948727492
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3354427135
Short name T375
Test name
Test status
Simulation time 237464006 ps
CPU time 80.27 seconds
Started Aug 03 04:30:11 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 213580 kb
Host smart-66d8db42-d18a-491e-ae76-8e66b48f81c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354427135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3354427135
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4099909307
Short name T405
Test name
Test status
Simulation time 707801534 ps
CPU time 9.57 seconds
Started Aug 03 04:30:13 PM PDT 24
Finished Aug 03 04:30:23 PM PDT 24
Peak memory 217844 kb
Host smart-38746806-93e4-42cd-bac2-fc3e09a4d307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099909307 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4099909307
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2833875662
Short name T337
Test name
Test status
Simulation time 320184528 ps
CPU time 9.74 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 210724 kb
Host smart-19a5ca98-71ec-4674-ab8f-99f5b54dd0ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833875662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2833875662
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2133973655
Short name T401
Test name
Test status
Simulation time 254294943 ps
CPU time 13.33 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 212564 kb
Host smart-a335100f-4403-4564-815b-1053cb15be12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133973655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2133973655
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2789126913
Short name T407
Test name
Test status
Simulation time 377200467 ps
CPU time 12.67 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 217640 kb
Host smart-f88fa410-075a-4951-8495-cf394e1f948e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789126913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2789126913
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1645694349
Short name T366
Test name
Test status
Simulation time 1156506523 ps
CPU time 81.16 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:31:44 PM PDT 24
Peak memory 212940 kb
Host smart-df1372a6-f887-4d21-983d-95a126faef14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645694349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1645694349
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2094511350
Short name T353
Test name
Test status
Simulation time 941209208 ps
CPU time 10.15 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 215220 kb
Host smart-6dd9522e-e2eb-4f9b-9bcb-8938ae62d5b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094511350 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2094511350
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1781651814
Short name T396
Test name
Test status
Simulation time 320297576 ps
CPU time 8.05 seconds
Started Aug 03 04:30:19 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 210740 kb
Host smart-b8fbb5d9-a944-411f-be55-0f44f5821320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781651814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1781651814
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3538462724
Short name T387
Test name
Test status
Simulation time 178555149 ps
CPU time 12 seconds
Started Aug 03 04:30:19 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 212596 kb
Host smart-c2578dfc-b3a1-47b9-873e-eb03b7360342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538462724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3538462724
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2951952010
Short name T409
Test name
Test status
Simulation time 527195107 ps
CPU time 15.16 seconds
Started Aug 03 04:30:24 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 219056 kb
Host smart-a38f478f-280b-41ca-8d94-85f84b93729b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951952010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2951952010
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1662270425
Short name T54
Test name
Test status
Simulation time 358267088 ps
CPU time 82.4 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:31:37 PM PDT 24
Peak memory 213800 kb
Host smart-8e1ab9fe-af33-46cb-bf01-accab6810e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662270425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1662270425
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2697998199
Short name T325
Test name
Test status
Simulation time 3221182978 ps
CPU time 10.37 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 216608 kb
Host smart-de0cf9dd-b7ed-42dd-9e1b-14b8d7327d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697998199 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2697998199
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2323137613
Short name T363
Test name
Test status
Simulation time 785518460 ps
CPU time 8.21 seconds
Started Aug 03 04:30:16 PM PDT 24
Finished Aug 03 04:30:24 PM PDT 24
Peak memory 210808 kb
Host smart-80d0b8ad-6889-49ef-9a29-24d03c5cb4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323137613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2323137613
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.41217059
Short name T400
Test name
Test status
Simulation time 231664349 ps
CPU time 8.44 seconds
Started Aug 03 04:30:23 PM PDT 24
Finished Aug 03 04:30:32 PM PDT 24
Peak memory 211228 kb
Host smart-9cfbd28c-2fdf-4f8e-8b1d-5c51cd75b942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41217059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctr
l_same_csr_outstanding.41217059
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3586957992
Short name T361
Test name
Test status
Simulation time 2757087972 ps
CPU time 11.44 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:26 PM PDT 24
Peak memory 217440 kb
Host smart-34bac304-65b6-4ad9-a955-80bc21896fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586957992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3586957992
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.206173746
Short name T94
Test name
Test status
Simulation time 1043770320 ps
CPU time 152.07 seconds
Started Aug 03 04:30:15 PM PDT 24
Finished Aug 03 04:32:47 PM PDT 24
Peak memory 214156 kb
Host smart-af4c8003-3ec2-45b1-89e9-a45c3d44faee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206173746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.206173746
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1640246403
Short name T344
Test name
Test status
Simulation time 526165113 ps
CPU time 9.96 seconds
Started Aug 03 04:30:25 PM PDT 24
Finished Aug 03 04:30:35 PM PDT 24
Peak memory 215304 kb
Host smart-72fde06b-1320-4c6a-bf3c-78f1c110f9e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640246403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1640246403
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3111505877
Short name T415
Test name
Test status
Simulation time 171128309 ps
CPU time 8.11 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:23 PM PDT 24
Peak memory 210740 kb
Host smart-b311a7f2-2db8-418d-a909-b9b274df25e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111505877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3111505877
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1820000524
Short name T342
Test name
Test status
Simulation time 2073764208 ps
CPU time 18.35 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 212904 kb
Host smart-6844b6cd-c649-42de-90d5-dbe45bf61277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820000524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1820000524
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3201034448
Short name T414
Test name
Test status
Simulation time 360512061 ps
CPU time 12.53 seconds
Started Aug 03 04:30:22 PM PDT 24
Finished Aug 03 04:30:35 PM PDT 24
Peak memory 219016 kb
Host smart-dff642f1-b25f-4c8f-aa32-ea74973b044d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201034448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3201034448
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1563757541
Short name T379
Test name
Test status
Simulation time 482602677 ps
CPU time 82.69 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:31:37 PM PDT 24
Peak memory 214672 kb
Host smart-3c835097-92b8-46a9-9219-6c7df24f8717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563757541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1563757541
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.689980934
Short name T360
Test name
Test status
Simulation time 224674737 ps
CPU time 10.19 seconds
Started Aug 03 04:30:15 PM PDT 24
Finished Aug 03 04:30:25 PM PDT 24
Peak memory 217952 kb
Host smart-c49a4ab0-6d23-48f6-a4b8-9742b19e67c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689980934 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.689980934
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2518397539
Short name T77
Test name
Test status
Simulation time 259946296 ps
CPU time 9.85 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:31 PM PDT 24
Peak memory 211120 kb
Host smart-2dbc1378-b7aa-4d76-8730-400e82cb2079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518397539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2518397539
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3118394906
Short name T90
Test name
Test status
Simulation time 6842252859 ps
CPU time 37.45 seconds
Started Aug 03 04:30:18 PM PDT 24
Finished Aug 03 04:30:56 PM PDT 24
Peak memory 215012 kb
Host smart-08c02645-c759-40d0-bff8-d15176ac8005
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118394906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3118394906
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2111726355
Short name T383
Test name
Test status
Simulation time 532161533 ps
CPU time 13.58 seconds
Started Aug 03 04:30:14 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 212656 kb
Host smart-aa75304e-b4b5-4d5c-b454-7a8b5f1047b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111726355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2111726355
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3905878566
Short name T406
Test name
Test status
Simulation time 872884127 ps
CPU time 12.58 seconds
Started Aug 03 04:30:21 PM PDT 24
Finished Aug 03 04:30:34 PM PDT 24
Peak memory 219064 kb
Host smart-22d7f668-f94f-47cc-ac5f-546e23cf6e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905878566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3905878566
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.11180393
Short name T140
Test name
Test status
Simulation time 1176274934 ps
CPU time 10.24 seconds
Started Aug 03 04:33:14 PM PDT 24
Finished Aug 03 04:33:25 PM PDT 24
Peak memory 219064 kb
Host smart-9efa3ebf-9e70-48eb-8ca5-e810881d2fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11180393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.11180393
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2694637331
Short name T198
Test name
Test status
Simulation time 2873345613 ps
CPU time 147.95 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:35:51 PM PDT 24
Peak memory 231500 kb
Host smart-0437a6da-4815-46e5-b669-dfdc787fb911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694637331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2694637331
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3487750335
Short name T308
Test name
Test status
Simulation time 718830213 ps
CPU time 10.27 seconds
Started Aug 03 04:33:15 PM PDT 24
Finished Aug 03 04:33:26 PM PDT 24
Peak memory 219956 kb
Host smart-7bf80fd0-1af6-4267-860a-fbb634b572cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487750335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3487750335
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3652158163
Short name T16
Test name
Test status
Simulation time 1461897904 ps
CPU time 226.21 seconds
Started Aug 03 04:33:13 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 235460 kb
Host smart-c296208c-52cf-4806-9ea2-1675b533a663
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652158163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3652158163
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.588238358
Short name T72
Test name
Test status
Simulation time 184015549 ps
CPU time 10.44 seconds
Started Aug 03 04:33:17 PM PDT 24
Finished Aug 03 04:33:28 PM PDT 24
Peak memory 219912 kb
Host smart-9558582e-4256-4811-9528-e5adec480663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588238358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.588238358
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3371119939
Short name T161
Test name
Test status
Simulation time 546707529 ps
CPU time 28.94 seconds
Started Aug 03 04:33:15 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219908 kb
Host smart-5c8fc8f7-3aa3-4e56-a7b3-94669eb3b81a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371119939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3371119939
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.632795249
Short name T268
Test name
Test status
Simulation time 260489523994 ps
CPU time 2409.41 seconds
Started Aug 03 04:33:13 PM PDT 24
Finished Aug 03 05:13:23 PM PDT 24
Peak memory 244888 kb
Host smart-0612b406-cf77-4a6e-b775-ee7a13e45aac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632795249 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.632795249
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1012180481
Short name T19
Test name
Test status
Simulation time 661932362 ps
CPU time 8.59 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 218920 kb
Host smart-1db7cf1e-6452-4a55-b7f6-227a55bab69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012180481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1012180481
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.189103149
Short name T233
Test name
Test status
Simulation time 8810660000 ps
CPU time 127.85 seconds
Started Aug 03 04:33:10 PM PDT 24
Finished Aug 03 04:35:18 PM PDT 24
Peak memory 234456 kb
Host smart-498a2899-dce6-4d44-a543-d0365cb98cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189103149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.189103149
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4000248678
Short name T156
Test name
Test status
Simulation time 1013066359 ps
CPU time 22.43 seconds
Started Aug 03 04:33:10 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 220008 kb
Host smart-6041d399-c5eb-4e09-82c4-7ebc0a8ea89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000248678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4000248678
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3236339059
Short name T29
Test name
Test status
Simulation time 1030962878 ps
CPU time 12.23 seconds
Started Aug 03 04:33:14 PM PDT 24
Finished Aug 03 04:33:26 PM PDT 24
Peak memory 219868 kb
Host smart-22c7c93f-e828-4a5a-8d23-d00b4e28c21d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236339059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3236339059
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3616251121
Short name T24
Test name
Test status
Simulation time 2245878254 ps
CPU time 231.19 seconds
Started Aug 03 04:33:15 PM PDT 24
Finished Aug 03 04:37:07 PM PDT 24
Peak memory 235484 kb
Host smart-e34265a8-c7e5-494d-8836-76eef588ec50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616251121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3616251121
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4281630547
Short name T8
Test name
Test status
Simulation time 381925531 ps
CPU time 10.68 seconds
Started Aug 03 04:33:19 PM PDT 24
Finished Aug 03 04:33:30 PM PDT 24
Peak memory 219904 kb
Host smart-b1228584-bb04-4220-8ccf-2c7c9394b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281630547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4281630547
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1530575779
Short name T174
Test name
Test status
Simulation time 198201033 ps
CPU time 17.92 seconds
Started Aug 03 04:33:19 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219580 kb
Host smart-2f80e56d-f92d-409a-afff-8d572ddfce51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530575779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1530575779
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3912393266
Short name T257
Test name
Test status
Simulation time 168227112 ps
CPU time 8.38 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 219048 kb
Host smart-e2cd20a8-d441-4591-96d0-855d240a17a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912393266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3912393266
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1784300498
Short name T45
Test name
Test status
Simulation time 3064295608 ps
CPU time 162.47 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:36:09 PM PDT 24
Peak memory 237556 kb
Host smart-aa225875-4f56-44c3-be3f-7478bb8ebb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784300498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1784300498
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3044614447
Short name T142
Test name
Test status
Simulation time 1098503293 ps
CPU time 22.51 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:47 PM PDT 24
Peak memory 220008 kb
Host smart-653af7fa-b791-4ec5-b1cc-bdac7d8b8456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044614447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3044614447
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3631510301
Short name T207
Test name
Test status
Simulation time 520802013 ps
CPU time 11.59 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:38 PM PDT 24
Peak memory 219996 kb
Host smart-1fe35a1f-49c1-4707-aa6d-25cdc17f68b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631510301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3631510301
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4724899
Short name T12
Test name
Test status
Simulation time 570607167 ps
CPU time 20.48 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 218148 kb
Host smart-87eeaa3f-8fab-4074-8ee7-dba6b2234786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4724899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.rom_ctrl_stress_all.4724899
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4214800491
Short name T264
Test name
Test status
Simulation time 55886055688 ps
CPU time 2041.6 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 05:07:27 PM PDT 24
Peak memory 237716 kb
Host smart-e76cc801-a8b5-42d7-9a25-f93f703bce12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214800491 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4214800491
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2882843904
Short name T319
Test name
Test status
Simulation time 1500337006 ps
CPU time 8.57 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 218864 kb
Host smart-715076bf-0b5f-4efb-b359-1f30004aee51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882843904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2882843904
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2211967500
Short name T112
Test name
Test status
Simulation time 1647436460 ps
CPU time 152.23 seconds
Started Aug 03 04:33:28 PM PDT 24
Finished Aug 03 04:36:00 PM PDT 24
Peak memory 243708 kb
Host smart-b95a0f4e-78f7-43e8-bec2-fb14252ee2d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211967500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2211967500
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.742906119
Short name T176
Test name
Test status
Simulation time 8233587811 ps
CPU time 33.4 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 220064 kb
Host smart-f206e86d-010e-4fb4-8738-c58be1dd0406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742906119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.742906119
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4135751598
Short name T275
Test name
Test status
Simulation time 719093924 ps
CPU time 10.03 seconds
Started Aug 03 04:33:30 PM PDT 24
Finished Aug 03 04:33:41 PM PDT 24
Peak memory 219952 kb
Host smart-54c08c3d-918c-4b89-98e2-48b5c686cc9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135751598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4135751598
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3693184450
Short name T175
Test name
Test status
Simulation time 2025464124 ps
CPU time 26.27 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:54 PM PDT 24
Peak memory 219892 kb
Host smart-dfc81190-fe7f-4c2b-b6bd-019610d240e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693184450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3693184450
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.418885172
Short name T305
Test name
Test status
Simulation time 1889053325 ps
CPU time 15.06 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:39 PM PDT 24
Peak memory 219040 kb
Host smart-b71b49b6-b365-461b-bc19-58b09c1401a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418885172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.418885172
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2710184227
Short name T181
Test name
Test status
Simulation time 1011585852 ps
CPU time 22.68 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 220068 kb
Host smart-494d4730-e5dc-402d-b3c4-061374434da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710184227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2710184227
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3247065982
Short name T122
Test name
Test status
Simulation time 3654991561 ps
CPU time 12.35 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:39 PM PDT 24
Peak memory 220064 kb
Host smart-4476d770-b1b7-46cb-8ea1-c113874b31f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247065982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3247065982
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.666997783
Short name T220
Test name
Test status
Simulation time 2233052366 ps
CPU time 30.96 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 220028 kb
Host smart-2f43b65d-ee8f-48c0-9db1-5cd8df28fce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666997783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.666997783
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3244809095
Short name T294
Test name
Test status
Simulation time 76623408627 ps
CPU time 3272.79 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 05:27:56 PM PDT 24
Peak memory 252896 kb
Host smart-e2ab42e9-2bea-41c4-88b1-80d620100908
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244809095 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3244809095
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3783293390
Short name T148
Test name
Test status
Simulation time 339214460 ps
CPU time 8.53 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:33:31 PM PDT 24
Peak memory 219048 kb
Host smart-71a70bb8-c6a5-49db-8757-22d7a77a8ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783293390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3783293390
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1985876128
Short name T262
Test name
Test status
Simulation time 22943030708 ps
CPU time 238.46 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:37:21 PM PDT 24
Peak memory 241172 kb
Host smart-31556b59-c3ac-4327-b46c-52f1dad41ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985876128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1985876128
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2720750057
Short name T131
Test name
Test status
Simulation time 517098284 ps
CPU time 22.38 seconds
Started Aug 03 04:33:26 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 220000 kb
Host smart-1c1d17c5-325c-4cde-92c2-2e388bebab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720750057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2720750057
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3823854290
Short name T178
Test name
Test status
Simulation time 184663379 ps
CPU time 9.77 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219924 kb
Host smart-94668014-da36-46c3-b464-830c95b21a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823854290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3823854290
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.709613459
Short name T226
Test name
Test status
Simulation time 3007174612 ps
CPU time 38.62 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219980 kb
Host smart-c6f8ec79-f30d-4736-9ee3-fc21a15541af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709613459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.709613459
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1347345126
Short name T206
Test name
Test status
Simulation time 174580939 ps
CPU time 8.22 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:33:32 PM PDT 24
Peak memory 219028 kb
Host smart-aa6cd2d1-7d7e-41de-9afd-3c2e3663a7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347345126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1347345126
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2621464755
Short name T261
Test name
Test status
Simulation time 12029086155 ps
CPU time 301.86 seconds
Started Aug 03 04:33:26 PM PDT 24
Finished Aug 03 04:38:28 PM PDT 24
Peak memory 239652 kb
Host smart-2a187e0f-31a6-4e98-ac34-0ca41507d7c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621464755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2621464755
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.337536072
Short name T287
Test name
Test status
Simulation time 351515192 ps
CPU time 19.49 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219976 kb
Host smart-91c01ef6-b549-44be-938f-2a4f9cb74363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337536072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.337536072
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.669904381
Short name T201
Test name
Test status
Simulation time 1071055285 ps
CPU time 12.41 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219944 kb
Host smart-2ddba29b-3e24-4221-9dfd-bd18d08e40bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669904381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.669904381
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1141963310
Short name T146
Test name
Test status
Simulation time 3119879625 ps
CPU time 31.23 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:55 PM PDT 24
Peak memory 220184 kb
Host smart-8350f57a-7c81-48eb-883c-637f1b8b67b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141963310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1141963310
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3460162717
Short name T279
Test name
Test status
Simulation time 176093072 ps
CPU time 8.2 seconds
Started Aug 03 04:33:36 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219188 kb
Host smart-c12cea4a-9097-4f7b-87f2-ac12e2cf1836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460162717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3460162717
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1258795821
Short name T265
Test name
Test status
Simulation time 1378221375 ps
CPU time 99.51 seconds
Started Aug 03 04:33:28 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 220144 kb
Host smart-9178cf49-5d57-445b-b36c-e127305d65f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258795821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1258795821
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4272890664
Short name T169
Test name
Test status
Simulation time 1973882507 ps
CPU time 22.55 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:33:45 PM PDT 24
Peak memory 220004 kb
Host smart-81e8b614-8334-48c3-8a15-ffdf4363d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272890664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4272890664
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1268897423
Short name T113
Test name
Test status
Simulation time 526982509 ps
CPU time 12.43 seconds
Started Aug 03 04:33:28 PM PDT 24
Finished Aug 03 04:33:41 PM PDT 24
Peak memory 219968 kb
Host smart-d196895a-d9a7-415e-b168-7d4759f90e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268897423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1268897423
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.158979008
Short name T71
Test name
Test status
Simulation time 2127915551 ps
CPU time 30.29 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 219932 kb
Host smart-8e5ca12a-8e86-4857-90f7-842e85377b7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158979008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.158979008
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1618539032
Short name T33
Test name
Test status
Simulation time 689007142 ps
CPU time 8.55 seconds
Started Aug 03 04:33:31 PM PDT 24
Finished Aug 03 04:33:39 PM PDT 24
Peak memory 219012 kb
Host smart-c8e0a1b9-33be-483a-ad0b-159d092fcc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618539032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1618539032
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4090491687
Short name T100
Test name
Test status
Simulation time 11189614559 ps
CPU time 261.3 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:37:53 PM PDT 24
Peak memory 241320 kb
Host smart-6b3591fe-9fb7-408d-a033-e82210601228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090491687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4090491687
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2919637576
Short name T309
Test name
Test status
Simulation time 335652386 ps
CPU time 19.17 seconds
Started Aug 03 04:33:30 PM PDT 24
Finished Aug 03 04:33:50 PM PDT 24
Peak memory 220008 kb
Host smart-60c56023-7cb8-45a1-9f7a-da644cf5d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919637576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2919637576
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2444246433
Short name T297
Test name
Test status
Simulation time 1741066706 ps
CPU time 10.28 seconds
Started Aug 03 04:33:30 PM PDT 24
Finished Aug 03 04:33:40 PM PDT 24
Peak memory 220064 kb
Host smart-6eb2303e-8dec-4e81-ad7a-065da45de8d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444246433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2444246433
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1670467818
Short name T230
Test name
Test status
Simulation time 1903531986 ps
CPU time 9.79 seconds
Started Aug 03 04:33:34 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 218936 kb
Host smart-f1b26ecd-ff0c-4507-85d8-e7e5f07436fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670467818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1670467818
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3738812936
Short name T127
Test name
Test status
Simulation time 4090785815 ps
CPU time 157.78 seconds
Started Aug 03 04:33:29 PM PDT 24
Finished Aug 03 04:36:07 PM PDT 24
Peak memory 237580 kb
Host smart-c514b3ed-4727-4509-80f8-1d82e66b56d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738812936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3738812936
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1976311193
Short name T290
Test name
Test status
Simulation time 386088631 ps
CPU time 18.76 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:52 PM PDT 24
Peak memory 220004 kb
Host smart-dbe85fb9-a3d4-47b4-ba3f-b8416a4fedda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976311193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1976311193
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1170281111
Short name T283
Test name
Test status
Simulation time 1060664666 ps
CPU time 11.85 seconds
Started Aug 03 04:33:34 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 219988 kb
Host smart-850287fc-0bf2-433b-b175-fb97994fae7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170281111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1170281111
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3852582769
Short name T59
Test name
Test status
Simulation time 796740874 ps
CPU time 13.67 seconds
Started Aug 03 04:34:31 PM PDT 24
Finished Aug 03 04:34:45 PM PDT 24
Peak memory 219680 kb
Host smart-e227d059-b4cd-4054-97c0-4e6b21e4e517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852582769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3852582769
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2364523687
Short name T259
Test name
Test status
Simulation time 346437755 ps
CPU time 8.5 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:33:41 PM PDT 24
Peak memory 219000 kb
Host smart-94b126d6-b27f-4081-8417-6f14d034c4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364523687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2364523687
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2526545302
Short name T184
Test name
Test status
Simulation time 13994951953 ps
CPU time 184.92 seconds
Started Aug 03 04:34:31 PM PDT 24
Finished Aug 03 04:37:36 PM PDT 24
Peak memory 219952 kb
Host smart-59b65d52-70f1-4e1c-898a-6bf8007d395e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526545302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2526545302
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2167812689
Short name T193
Test name
Test status
Simulation time 2067803158 ps
CPU time 23.1 seconds
Started Aug 03 04:33:35 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 219972 kb
Host smart-3894f59d-d159-4d0a-84f7-873fd10f4c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167812689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2167812689
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2524840967
Short name T252
Test name
Test status
Simulation time 529358657 ps
CPU time 12.2 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219936 kb
Host smart-a9fe7331-df43-4f0d-a55b-6f842660df19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524840967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2524840967
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3930551984
Short name T87
Test name
Test status
Simulation time 544714729 ps
CPU time 26.19 seconds
Started Aug 03 04:33:34 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 219888 kb
Host smart-9bd855cc-8ac0-433d-bd66-caa310ec10fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930551984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3930551984
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1930714303
Short name T244
Test name
Test status
Simulation time 250590702 ps
CPU time 9.69 seconds
Started Aug 03 04:33:36 PM PDT 24
Finished Aug 03 04:33:45 PM PDT 24
Peak memory 219104 kb
Host smart-3ca48c0e-4908-4769-bf32-46f086eb77bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930714303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1930714303
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.472961691
Short name T248
Test name
Test status
Simulation time 10768517785 ps
CPU time 290.37 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:38:29 PM PDT 24
Peak memory 239740 kb
Host smart-9eb05857-c8e6-43e3-9049-844a7f4dfbda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472961691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.472961691
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.200014934
Short name T318
Test name
Test status
Simulation time 661296389 ps
CPU time 19.28 seconds
Started Aug 03 04:33:29 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 219996 kb
Host smart-ff712828-489d-4e79-afd3-95c539e5ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200014934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.200014934
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3127616520
Short name T88
Test name
Test status
Simulation time 260932339 ps
CPU time 12.05 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 219992 kb
Host smart-4aee3e4b-e3e7-44dd-86b8-d4658cd711f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127616520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3127616520
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3937642894
Short name T209
Test name
Test status
Simulation time 4432320356 ps
CPU time 35.69 seconds
Started Aug 03 04:33:35 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 220048 kb
Host smart-88a08ca0-c279-4fe3-983e-c20eb37e3cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937642894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3937642894
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.195694257
Short name T158
Test name
Test status
Simulation time 7518364794 ps
CPU time 14.97 seconds
Started Aug 03 04:33:20 PM PDT 24
Finished Aug 03 04:33:35 PM PDT 24
Peak memory 219052 kb
Host smart-4b663c89-84c7-43fb-ad47-207fc9373668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195694257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.195694257
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3181761809
Short name T39
Test name
Test status
Simulation time 13619975043 ps
CPU time 215.74 seconds
Started Aug 03 04:33:20 PM PDT 24
Finished Aug 03 04:36:56 PM PDT 24
Peak memory 240684 kb
Host smart-75ddf542-7223-4ed3-be8f-bea5a18c8550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181761809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3181761809
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1109684250
Short name T182
Test name
Test status
Simulation time 517766940 ps
CPU time 23.17 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 219936 kb
Host smart-1d856357-a0f2-494c-b512-eab4f306e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109684250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1109684250
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4177595903
Short name T210
Test name
Test status
Simulation time 270849336 ps
CPU time 12.15 seconds
Started Aug 03 04:33:14 PM PDT 24
Finished Aug 03 04:33:26 PM PDT 24
Peak memory 219944 kb
Host smart-42a69bd8-044e-4f8b-88d9-f20a63e5bbdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177595903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4177595903
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1832593400
Short name T239
Test name
Test status
Simulation time 182242300 ps
CPU time 9.78 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:34:33 PM PDT 24
Peak memory 218028 kb
Host smart-913b1cd1-5262-416b-a253-2c8900ee83cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832593400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1832593400
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3527395655
Short name T69
Test name
Test status
Simulation time 785928503 ps
CPU time 24.31 seconds
Started Aug 03 04:33:07 PM PDT 24
Finished Aug 03 04:33:31 PM PDT 24
Peak memory 219872 kb
Host smart-0710f6b6-02cf-4ddc-9b40-eeb465cdf170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527395655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3527395655
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.468038350
Short name T126
Test name
Test status
Simulation time 259813539 ps
CPU time 9.65 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:43 PM PDT 24
Peak memory 218964 kb
Host smart-b10a9c06-a3aa-41b9-ba74-f97a764e2aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468038350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.468038350
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1994923504
Short name T256
Test name
Test status
Simulation time 4222366852 ps
CPU time 292.92 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:38:25 PM PDT 24
Peak memory 243344 kb
Host smart-321be9e0-ef46-41f8-a92e-76ed0c26b46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994923504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1994923504
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.658610396
Short name T217
Test name
Test status
Simulation time 340396904 ps
CPU time 19.36 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:33:57 PM PDT 24
Peak memory 220020 kb
Host smart-f8df13a4-85ca-4ec2-8a93-a7bcfba7a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658610396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.658610396
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4283774990
Short name T6
Test name
Test status
Simulation time 564157814 ps
CPU time 11.7 seconds
Started Aug 03 04:34:31 PM PDT 24
Finished Aug 03 04:34:42 PM PDT 24
Peak memory 219688 kb
Host smart-9873109d-f385-4c9c-8be2-ee3525b3dde5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283774990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4283774990
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2697923205
Short name T273
Test name
Test status
Simulation time 711000800 ps
CPU time 23.33 seconds
Started Aug 03 04:33:44 PM PDT 24
Finished Aug 03 04:34:08 PM PDT 24
Peak memory 220004 kb
Host smart-c55959aa-a600-4775-a36d-de3e05215fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697923205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2697923205
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4139455601
Short name T164
Test name
Test status
Simulation time 172448455 ps
CPU time 7.87 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:41 PM PDT 24
Peak memory 218836 kb
Host smart-51b3c1de-fc22-42fd-95cc-c5bf081f5ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139455601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4139455601
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4086636731
Short name T194
Test name
Test status
Simulation time 4571501614 ps
CPU time 235.45 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:37:28 PM PDT 24
Peak memory 237856 kb
Host smart-6dbcf4bc-8377-4e2a-9531-75afc25d1bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086636731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4086636731
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3663101648
Short name T32
Test name
Test status
Simulation time 1009854806 ps
CPU time 22.81 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:33:55 PM PDT 24
Peak memory 220068 kb
Host smart-ba7f1754-43cf-49ba-8720-ceb34d495646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663101648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3663101648
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4136908931
Short name T86
Test name
Test status
Simulation time 260703894 ps
CPU time 12.39 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:45 PM PDT 24
Peak memory 219936 kb
Host smart-62e748fe-3cc4-4c3e-9342-2e312f3958fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136908931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4136908931
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2301241493
Short name T293
Test name
Test status
Simulation time 3711212722 ps
CPU time 30.24 seconds
Started Aug 03 04:33:30 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 220052 kb
Host smart-0d72268e-1409-41cd-b76c-8103afac15f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301241493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2301241493
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3348202312
Short name T171
Test name
Test status
Simulation time 1762408900 ps
CPU time 9.67 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:33:47 PM PDT 24
Peak memory 219108 kb
Host smart-10ffda0e-2edf-45f3-a34a-3fb7c6bf70b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348202312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3348202312
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3445115483
Short name T304
Test name
Test status
Simulation time 15950472865 ps
CPU time 226.21 seconds
Started Aug 03 04:33:32 PM PDT 24
Finished Aug 03 04:37:18 PM PDT 24
Peak memory 220268 kb
Host smart-58410515-a13b-4fda-acb6-a5dd94fb7d82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445115483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3445115483
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3981215851
Short name T295
Test name
Test status
Simulation time 2758734708 ps
CPU time 18.12 seconds
Started Aug 03 04:34:31 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 219836 kb
Host smart-4e32a70d-07e9-4c86-b0eb-5746b35ab6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981215851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3981215851
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3347758793
Short name T235
Test name
Test status
Simulation time 1066396726 ps
CPU time 11.75 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:33:50 PM PDT 24
Peak memory 219928 kb
Host smart-54e71744-003d-451c-ae6d-824a14436a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347758793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3347758793
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1451898019
Short name T137
Test name
Test status
Simulation time 1103194013 ps
CPU time 28.1 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 220048 kb
Host smart-51e86e83-594d-4183-b7fa-c6c4d4f4f848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451898019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1451898019
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4061535970
Short name T192
Test name
Test status
Simulation time 251456263 ps
CPU time 10.21 seconds
Started Aug 03 04:33:35 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 219052 kb
Host smart-0ffc0cf5-6cd4-4aa9-be10-35ca2d04d9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061535970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4061535970
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1004861651
Short name T125
Test name
Test status
Simulation time 5064215441 ps
CPU time 187.56 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:36:46 PM PDT 24
Peak memory 240672 kb
Host smart-b0518a8b-abb2-417f-ae08-62ce2a9a3322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004861651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1004861651
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.94673499
Short name T143
Test name
Test status
Simulation time 498364616 ps
CPU time 22.81 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:56 PM PDT 24
Peak memory 219976 kb
Host smart-aa1ec0a0-5eac-4305-918e-1a87e321675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94673499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.94673499
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.721579404
Short name T314
Test name
Test status
Simulation time 209762400 ps
CPU time 10.56 seconds
Started Aug 03 04:33:33 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 220000 kb
Host smart-4a825468-c5e1-417b-83df-16fd44f98a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721579404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.721579404
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3900707200
Short name T68
Test name
Test status
Simulation time 1076013861 ps
CPU time 24.95 seconds
Started Aug 03 04:33:31 PM PDT 24
Finished Aug 03 04:33:56 PM PDT 24
Peak memory 219944 kb
Host smart-78b4a1cd-6d9e-4262-b4df-f4457ba7ef95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900707200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3900707200
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2986757550
Short name T231
Test name
Test status
Simulation time 661931077 ps
CPU time 8.34 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:33:59 PM PDT 24
Peak memory 219068 kb
Host smart-f3323fd9-bd6e-4ddc-ba5c-c4d3608e449e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986757550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2986757550
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4048411778
Short name T196
Test name
Test status
Simulation time 6033629683 ps
CPU time 312.21 seconds
Started Aug 03 04:33:36 PM PDT 24
Finished Aug 03 04:38:48 PM PDT 24
Peak memory 239460 kb
Host smart-428c0cd0-7c7b-4a03-a3de-69202da32872
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048411778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4048411778
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1110911084
Short name T136
Test name
Test status
Simulation time 347166349 ps
CPU time 19.55 seconds
Started Aug 03 04:33:41 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219908 kb
Host smart-2bd47ca6-d945-4771-8ac3-cfdb99e59dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110911084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1110911084
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.995688347
Short name T280
Test name
Test status
Simulation time 2515544408 ps
CPU time 10.48 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 220108 kb
Host smart-4cdd015e-c51a-4862-8928-49c2c2d160f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995688347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.995688347
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2169608855
Short name T135
Test name
Test status
Simulation time 545759917 ps
CPU time 36.89 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:34:15 PM PDT 24
Peak memory 219744 kb
Host smart-b3d246f4-7a3a-4308-a58a-0010b72a10d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169608855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2169608855
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.159211693
Short name T21
Test name
Test status
Simulation time 38864760704 ps
CPU time 1466.56 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:58:04 PM PDT 24
Peak memory 236656 kb
Host smart-52ea6785-a583-4977-a04c-2136e9527f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159211693 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.159211693
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.843490004
Short name T286
Test name
Test status
Simulation time 1035054620 ps
CPU time 10.14 seconds
Started Aug 03 04:33:40 PM PDT 24
Finished Aug 03 04:33:50 PM PDT 24
Peak memory 219076 kb
Host smart-71aa64f6-e352-4f18-95cf-fa5be3f24b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843490004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.843490004
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3806975079
Short name T249
Test name
Test status
Simulation time 4177121554 ps
CPU time 263.74 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:38:01 PM PDT 24
Peak memory 234504 kb
Host smart-745c3d5b-8b91-46d0-aaba-eb0823bfa35c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806975079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3806975079
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3434799436
Short name T292
Test name
Test status
Simulation time 512286977 ps
CPU time 22.96 seconds
Started Aug 03 04:34:02 PM PDT 24
Finished Aug 03 04:34:25 PM PDT 24
Peak memory 219988 kb
Host smart-a4fe4229-fac7-4b72-9af5-17abf6bb9492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434799436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3434799436
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2505725888
Short name T254
Test name
Test status
Simulation time 1158186943 ps
CPU time 11.65 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:33:49 PM PDT 24
Peak memory 219932 kb
Host smart-6b4670dc-0b1e-4451-a6b7-fbb94890b691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505725888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2505725888
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1092825116
Short name T289
Test name
Test status
Simulation time 2422257394 ps
CPU time 37.27 seconds
Started Aug 03 04:33:41 PM PDT 24
Finished Aug 03 04:34:19 PM PDT 24
Peak memory 220088 kb
Host smart-13bd259b-0016-4bdc-8388-186b4cf38a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092825116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1092825116
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2081232009
Short name T50
Test name
Test status
Simulation time 37230302436 ps
CPU time 1414.05 seconds
Started Aug 03 04:33:43 PM PDT 24
Finished Aug 03 04:57:17 PM PDT 24
Peak memory 239288 kb
Host smart-31642b96-b734-494a-8366-bde462c97121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081232009 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2081232009
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.920672282
Short name T114
Test name
Test status
Simulation time 2254763368 ps
CPU time 10.24 seconds
Started Aug 03 04:33:46 PM PDT 24
Finished Aug 03 04:33:56 PM PDT 24
Peak memory 219120 kb
Host smart-e932693e-f5b0-4669-adec-6a2c56944b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920672282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.920672282
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2002168279
Short name T236
Test name
Test status
Simulation time 8219042478 ps
CPU time 31.98 seconds
Started Aug 03 04:33:46 PM PDT 24
Finished Aug 03 04:34:18 PM PDT 24
Peak memory 220096 kb
Host smart-6d56cbb4-53d2-4ddb-a65a-688c0a06d412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002168279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2002168279
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4136415851
Short name T111
Test name
Test status
Simulation time 259704778 ps
CPU time 12.32 seconds
Started Aug 03 04:33:42 PM PDT 24
Finished Aug 03 04:33:54 PM PDT 24
Peak memory 220220 kb
Host smart-3b11e202-4b8b-446d-9619-6a2ce420dacf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136415851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4136415851
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1058579161
Short name T199
Test name
Test status
Simulation time 2291291469 ps
CPU time 12.18 seconds
Started Aug 03 04:33:57 PM PDT 24
Finished Aug 03 04:34:09 PM PDT 24
Peak memory 220140 kb
Host smart-d6f62c3b-18cc-4a88-85e7-64c9e2bdd573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058579161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1058579161
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4034030337
Short name T89
Test name
Test status
Simulation time 74923046942 ps
CPU time 2827.74 seconds
Started Aug 03 04:33:59 PM PDT 24
Finished Aug 03 05:21:08 PM PDT 24
Peak memory 244756 kb
Host smart-e979a1d1-d2d8-4dd7-909c-a7bbc7525a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034030337 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4034030337
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3582743261
Short name T18
Test name
Test status
Simulation time 570922847 ps
CPU time 8.59 seconds
Started Aug 03 04:33:57 PM PDT 24
Finished Aug 03 04:34:05 PM PDT 24
Peak memory 219012 kb
Host smart-af454fe2-580c-4e9e-bc17-be39276408cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582743261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3582743261
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2181392823
Short name T215
Test name
Test status
Simulation time 4162471963 ps
CPU time 289.35 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:38:27 PM PDT 24
Peak memory 235208 kb
Host smart-deeb7b2e-3965-4e7a-b9ed-08411e191450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181392823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2181392823
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3357888285
Short name T214
Test name
Test status
Simulation time 689423121 ps
CPU time 19.44 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 219956 kb
Host smart-e6faf4bd-42ce-488d-9882-5367aa017620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357888285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3357888285
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1409297142
Short name T31
Test name
Test status
Simulation time 177084973 ps
CPU time 10.85 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 04:34:07 PM PDT 24
Peak memory 219912 kb
Host smart-43b5845d-2ecd-40e4-a5db-01f2be96fdf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409297142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1409297142
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2930258109
Short name T313
Test name
Test status
Simulation time 1071263887 ps
CPU time 51.09 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:34:41 PM PDT 24
Peak memory 219968 kb
Host smart-2f124c64-3ae5-45ca-9d10-642baaa88e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930258109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2930258109
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3661979673
Short name T179
Test name
Test status
Simulation time 169284729 ps
CPU time 8.08 seconds
Started Aug 03 04:33:40 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 219132 kb
Host smart-8ee0ec9a-5018-4356-ad70-f4fc8b604f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661979673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3661979673
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2221200957
Short name T152
Test name
Test status
Simulation time 3340658036 ps
CPU time 223.84 seconds
Started Aug 03 04:33:59 PM PDT 24
Finished Aug 03 04:37:43 PM PDT 24
Peak memory 226840 kb
Host smart-971a86b5-d3aa-443d-94c3-ab4f4aa372dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221200957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2221200957
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.214717234
Short name T108
Test name
Test status
Simulation time 1839486958 ps
CPU time 19.02 seconds
Started Aug 03 04:33:41 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 219932 kb
Host smart-a7cd6420-e227-48f5-82c1-05f7319371d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214717234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.214717234
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2936216009
Short name T117
Test name
Test status
Simulation time 291970823 ps
CPU time 12.1 seconds
Started Aug 03 04:33:45 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 219968 kb
Host smart-3da972ac-2253-43d4-bd0e-10c840a80ffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936216009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2936216009
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1112128704
Short name T232
Test name
Test status
Simulation time 205427812 ps
CPU time 15.26 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 219912 kb
Host smart-889cff25-a53d-48e2-b953-9be2e9390dfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112128704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1112128704
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3719706228
Short name T51
Test name
Test status
Simulation time 345988843078 ps
CPU time 2888.73 seconds
Started Aug 03 04:33:41 PM PDT 24
Finished Aug 03 05:21:50 PM PDT 24
Peak memory 252924 kb
Host smart-ab8efb2b-aeea-47c6-aa5e-2f0fc91a04f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719706228 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3719706228
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4150213901
Short name T224
Test name
Test status
Simulation time 174794783 ps
CPU time 8.44 seconds
Started Aug 03 04:33:48 PM PDT 24
Finished Aug 03 04:33:57 PM PDT 24
Peak memory 218884 kb
Host smart-6b22a8d7-67e7-4b56-9a62-2e5ee359d23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150213901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4150213901
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1699829569
Short name T301
Test name
Test status
Simulation time 11256470527 ps
CPU time 374.85 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:39:52 PM PDT 24
Peak memory 226896 kb
Host smart-c768464e-b412-414e-80da-4a41c98fb1c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699829569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1699829569
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1861648787
Short name T200
Test name
Test status
Simulation time 705506678 ps
CPU time 19.02 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 219844 kb
Host smart-f8a00f1c-a96a-4881-9ad7-c2b37afeab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861648787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1861648787
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1884382335
Short name T147
Test name
Test status
Simulation time 1071392485 ps
CPU time 12.19 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:34:08 PM PDT 24
Peak memory 220044 kb
Host smart-39410e6e-d637-4911-afd3-3b412e777a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884382335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1884382335
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.580267588
Short name T271
Test name
Test status
Simulation time 2131909043 ps
CPU time 18.08 seconds
Started Aug 03 04:33:59 PM PDT 24
Finished Aug 03 04:34:17 PM PDT 24
Peak memory 219908 kb
Host smart-51640ab5-f48d-411e-9b49-b24dcd546397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580267588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.580267588
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.106639297
Short name T296
Test name
Test status
Simulation time 257705352 ps
CPU time 10.31 seconds
Started Aug 03 04:33:18 PM PDT 24
Finished Aug 03 04:33:28 PM PDT 24
Peak memory 219012 kb
Host smart-ca844923-20f6-4aac-a7f2-f3f323fe358b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106639297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.106639297
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.493957692
Short name T240
Test name
Test status
Simulation time 14285076456 ps
CPU time 176.82 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:37:20 PM PDT 24
Peak memory 234228 kb
Host smart-42d42e69-6a9e-4fc4-9c2b-d2f109167da0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493957692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.493957692
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3114178839
Short name T219
Test name
Test status
Simulation time 830044012 ps
CPU time 19.7 seconds
Started Aug 03 04:33:14 PM PDT 24
Finished Aug 03 04:33:34 PM PDT 24
Peak memory 219984 kb
Host smart-ba03f83d-aaa6-4935-bd15-b0ca5fbb089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114178839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3114178839
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.794567146
Short name T278
Test name
Test status
Simulation time 1457837186 ps
CPU time 10.96 seconds
Started Aug 03 04:33:16 PM PDT 24
Finished Aug 03 04:33:27 PM PDT 24
Peak memory 220088 kb
Host smart-fbb5293e-3e14-4917-a36c-53888c5b6628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794567146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.794567146
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1572601778
Short name T23
Test name
Test status
Simulation time 3991762047 ps
CPU time 223.72 seconds
Started Aug 03 04:33:19 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 235620 kb
Host smart-36ec0fa1-52bb-4267-b71d-942d744a71d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572601778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1572601778
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3857858810
Short name T188
Test name
Test status
Simulation time 1080550021 ps
CPU time 11.62 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 218652 kb
Host smart-5005bee7-64e3-4be6-8c44-6db6cc5270e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857858810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3857858810
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3220911985
Short name T243
Test name
Test status
Simulation time 2637648610 ps
CPU time 22.99 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:34:47 PM PDT 24
Peak memory 217736 kb
Host smart-f415bb11-c36b-4d74-adf0-5c96c279dbeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220911985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3220911985
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.172726653
Short name T251
Test name
Test status
Simulation time 147311692956 ps
CPU time 1523.9 seconds
Started Aug 03 04:34:32 PM PDT 24
Finished Aug 03 04:59:57 PM PDT 24
Peak memory 244500 kb
Host smart-a91155e1-b4a0-447d-906f-f265f427d342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172726653 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.172726653
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2960676128
Short name T272
Test name
Test status
Simulation time 517103138 ps
CPU time 10.15 seconds
Started Aug 03 04:33:45 PM PDT 24
Finished Aug 03 04:33:55 PM PDT 24
Peak memory 219068 kb
Host smart-f50badeb-1938-493a-8a31-b1b046a90216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960676128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2960676128
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1313573702
Short name T167
Test name
Test status
Simulation time 4868248133 ps
CPU time 299.44 seconds
Started Aug 03 04:33:36 PM PDT 24
Finished Aug 03 04:38:36 PM PDT 24
Peak memory 243620 kb
Host smart-6d0e45b8-cdec-423f-a3dd-4d09b6e277fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313573702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1313573702
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1583839396
Short name T173
Test name
Test status
Simulation time 1382749922 ps
CPU time 19.19 seconds
Started Aug 03 04:33:41 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 219944 kb
Host smart-4ed03613-c01e-4465-8685-4c89aa40e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583839396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1583839396
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3518425204
Short name T218
Test name
Test status
Simulation time 181237323 ps
CPU time 10.64 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 219984 kb
Host smart-4c2cb290-1a54-40cd-ab46-b0f166787ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518425204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3518425204
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2746077048
Short name T285
Test name
Test status
Simulation time 1483525062 ps
CPU time 23.48 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 04:34:19 PM PDT 24
Peak memory 219992 kb
Host smart-6337a93d-40cc-4413-bfff-7d39443e2e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746077048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2746077048
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3073249900
Short name T7
Test name
Test status
Simulation time 132891048168 ps
CPU time 1538.46 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:59:30 PM PDT 24
Peak memory 238296 kb
Host smart-077a3a68-8f48-41d0-8412-e949b93a510a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073249900 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3073249900
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1273239596
Short name T172
Test name
Test status
Simulation time 13455814257 ps
CPU time 175.2 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:36:50 PM PDT 24
Peak memory 242832 kb
Host smart-96cd1629-9c40-4aa4-8ac5-e8929b6ace63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273239596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1273239596
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1003168853
Short name T205
Test name
Test status
Simulation time 991488914 ps
CPU time 22.42 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:34:18 PM PDT 24
Peak memory 219980 kb
Host smart-99ab8fcc-d95e-4d83-b69c-b214b9f932d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003168853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1003168853
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2284282315
Short name T245
Test name
Test status
Simulation time 582202781 ps
CPU time 10.41 seconds
Started Aug 03 04:33:39 PM PDT 24
Finished Aug 03 04:33:50 PM PDT 24
Peak memory 219984 kb
Host smart-b78f8a43-87f0-4098-9cc9-6635188a4827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284282315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2284282315
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.447035456
Short name T109
Test name
Test status
Simulation time 394251416 ps
CPU time 17.6 seconds
Started Aug 03 04:33:43 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 219784 kb
Host smart-abb7bb16-249d-4267-8937-259efbef7a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447035456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.447035456
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2007867773
Short name T48
Test name
Test status
Simulation time 263746438596 ps
CPU time 2746.48 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 05:19:43 PM PDT 24
Peak memory 252884 kb
Host smart-ce624672-2bdd-433d-ab49-e64fb68841ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007867773 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2007867773
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3787961886
Short name T221
Test name
Test status
Simulation time 2357184482 ps
CPU time 8.53 seconds
Started Aug 03 04:33:59 PM PDT 24
Finished Aug 03 04:34:08 PM PDT 24
Peak memory 219104 kb
Host smart-bd7f43e5-b416-4781-97a4-1489c87568b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787961886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3787961886
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2928231111
Short name T155
Test name
Test status
Simulation time 4255669136 ps
CPU time 272.16 seconds
Started Aug 03 04:33:42 PM PDT 24
Finished Aug 03 04:38:14 PM PDT 24
Peak memory 239296 kb
Host smart-f5044f4a-a7cc-48f2-bbce-a757a81b8d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928231111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2928231111
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1524904161
Short name T9
Test name
Test status
Simulation time 349626297 ps
CPU time 19.33 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:19 PM PDT 24
Peak memory 219952 kb
Host smart-871615c1-00e7-497c-9312-fd5359490fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524904161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1524904161
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.869090999
Short name T159
Test name
Test status
Simulation time 363608287 ps
CPU time 10.05 seconds
Started Aug 03 04:33:42 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 220060 kb
Host smart-b75c2001-b1ba-40cb-ba64-f3b6bacf022e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869090999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.869090999
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3115067875
Short name T316
Test name
Test status
Simulation time 1695597355 ps
CPU time 43.05 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:43 PM PDT 24
Peak memory 220728 kb
Host smart-aa60d027-6c73-4cdd-a719-cd6a72a6d8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115067875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3115067875
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1422230319
Short name T151
Test name
Test status
Simulation time 145610515279 ps
CPU time 1401.05 seconds
Started Aug 03 04:33:45 PM PDT 24
Finished Aug 03 04:57:06 PM PDT 24
Peak memory 238196 kb
Host smart-ddf08ed1-66a2-4b61-847d-d658d28e5e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422230319 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1422230319
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.756892485
Short name T177
Test name
Test status
Simulation time 1979318792 ps
CPU time 14.64 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:33:52 PM PDT 24
Peak memory 219128 kb
Host smart-7c7c9260-a646-4fb1-a005-df86a24e1d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756892485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.756892485
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3768703533
Short name T13
Test name
Test status
Simulation time 9303396621 ps
CPU time 259.01 seconds
Started Aug 03 04:33:43 PM PDT 24
Finished Aug 03 04:38:02 PM PDT 24
Peak memory 234480 kb
Host smart-18884c32-7e31-458c-a937-3ae17aa7282a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768703533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3768703533
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1849393648
Short name T203
Test name
Test status
Simulation time 2058863925 ps
CPU time 21.9 seconds
Started Aug 03 04:33:38 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219972 kb
Host smart-992f8147-a1fc-4659-9b7e-b822cd2c542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849393648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1849393648
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.586452956
Short name T187
Test name
Test status
Simulation time 1683658585 ps
CPU time 11.91 seconds
Started Aug 03 04:33:37 PM PDT 24
Finished Aug 03 04:33:49 PM PDT 24
Peak memory 219980 kb
Host smart-154a2432-1b5d-4668-91c2-c1ca9ac9d493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586452956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.586452956
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1483441084
Short name T14
Test name
Test status
Simulation time 6123035025 ps
CPU time 24.62 seconds
Started Aug 03 04:33:39 PM PDT 24
Finished Aug 03 04:34:04 PM PDT 24
Peak memory 220036 kb
Host smart-04b6d495-2495-42b0-99a8-7b0da3c5205d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483441084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1483441084
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3293039837
Short name T298
Test name
Test status
Simulation time 251229423 ps
CPU time 10.05 seconds
Started Aug 03 04:34:04 PM PDT 24
Finished Aug 03 04:34:14 PM PDT 24
Peak memory 219164 kb
Host smart-7e998e63-bf97-4951-ae02-cbee5abe9803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293039837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3293039837
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2590721554
Short name T11
Test name
Test status
Simulation time 2578350411 ps
CPU time 159.62 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:36:35 PM PDT 24
Peak memory 219960 kb
Host smart-8f0cf53a-59fe-457d-924c-91c9f7892332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590721554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2590721554
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.452794353
Short name T22
Test name
Test status
Simulation time 3092171595 ps
CPU time 22.77 seconds
Started Aug 03 04:34:02 PM PDT 24
Finished Aug 03 04:34:25 PM PDT 24
Peak memory 220200 kb
Host smart-6dd70107-d8cc-4f90-8d96-49e73320b71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452794353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.452794353
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.294577211
Short name T28
Test name
Test status
Simulation time 721054432 ps
CPU time 10.22 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:33:59 PM PDT 24
Peak memory 220064 kb
Host smart-d61dc01e-4757-4bd2-830c-098c4942dd76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294577211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.294577211
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3855518297
Short name T185
Test name
Test status
Simulation time 3616541315 ps
CPU time 43.29 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:34:34 PM PDT 24
Peak memory 220084 kb
Host smart-93ad3c02-d93c-425b-bf98-4b5eeb8a8707
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855518297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3855518297
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1116057640
Short name T141
Test name
Test status
Simulation time 66024568952 ps
CPU time 1150.06 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 234984 kb
Host smart-d340d395-ba61-4628-85b2-b118c8a0915c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116057640 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1116057640
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2698422556
Short name T128
Test name
Test status
Simulation time 3104256564 ps
CPU time 9.79 seconds
Started Aug 03 04:33:46 PM PDT 24
Finished Aug 03 04:33:56 PM PDT 24
Peak memory 219252 kb
Host smart-c380ec30-05d0-472a-a1b1-27ba7a006aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698422556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2698422556
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1232557479
Short name T153
Test name
Test status
Simulation time 18710188930 ps
CPU time 246.83 seconds
Started Aug 03 04:34:07 PM PDT 24
Finished Aug 03 04:38:14 PM PDT 24
Peak memory 219800 kb
Host smart-61c59a0b-8f6d-4f31-ac88-bf01ed33ea64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232557479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1232557479
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2674050269
Short name T310
Test name
Test status
Simulation time 676565513 ps
CPU time 19.14 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:34:10 PM PDT 24
Peak memory 219952 kb
Host smart-3bfd60e6-270c-4315-826a-9ca50a64323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674050269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2674050269
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3090650631
Short name T250
Test name
Test status
Simulation time 710699049 ps
CPU time 10.66 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 220088 kb
Host smart-14d910ed-527a-489f-a025-befe866e2926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090650631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3090650631
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2647412976
Short name T73
Test name
Test status
Simulation time 553872912 ps
CPU time 27.4 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:28 PM PDT 24
Peak memory 219752 kb
Host smart-cb3d4167-3714-4a94-85f8-39c1b8c7546c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647412976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2647412976
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3357989266
Short name T46
Test name
Test status
Simulation time 64206132347 ps
CPU time 588.94 seconds
Started Aug 03 04:33:45 PM PDT 24
Finished Aug 03 04:43:34 PM PDT 24
Peak memory 232552 kb
Host smart-9e052ed4-e6cb-4eec-be7e-e90924d94e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357989266 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3357989266
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.269722804
Short name T291
Test name
Test status
Simulation time 1649212663 ps
CPU time 8.34 seconds
Started Aug 03 04:33:54 PM PDT 24
Finished Aug 03 04:34:02 PM PDT 24
Peak memory 219012 kb
Host smart-01ad4e2e-f737-49fd-a4b8-b6be57095922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269722804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.269722804
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3843782098
Short name T116
Test name
Test status
Simulation time 1559138414 ps
CPU time 109.71 seconds
Started Aug 03 04:33:48 PM PDT 24
Finished Aug 03 04:35:38 PM PDT 24
Peak memory 241432 kb
Host smart-c4940c34-75a4-418b-a0c4-70798e04a1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843782098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3843782098
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4068407263
Short name T276
Test name
Test status
Simulation time 2362308963 ps
CPU time 22.73 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:20 PM PDT 24
Peak memory 220088 kb
Host smart-6390ba8d-1683-4307-bbdf-1d55c9218b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068407263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4068407263
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1162486169
Short name T105
Test name
Test status
Simulation time 739681773 ps
CPU time 10.8 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:12 PM PDT 24
Peak memory 219964 kb
Host smart-115950bd-be15-4541-b31c-28f3ade9355b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162486169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1162486169
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.763745993
Short name T144
Test name
Test status
Simulation time 1869203836 ps
CPU time 23.87 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:34:14 PM PDT 24
Peak memory 220016 kb
Host smart-b908db0a-b2c2-47b0-a7e3-af8835605e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763745993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.763745993
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4109896379
Short name T320
Test name
Test status
Simulation time 1033934635 ps
CPU time 10.07 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:33:57 PM PDT 24
Peak memory 219004 kb
Host smart-7089bed4-f553-4414-a18a-2c56f2053da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109896379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4109896379
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1952249146
Short name T102
Test name
Test status
Simulation time 87016606255 ps
CPU time 443.58 seconds
Started Aug 03 04:34:05 PM PDT 24
Finished Aug 03 04:41:29 PM PDT 24
Peak memory 237196 kb
Host smart-8321aabb-3e85-4a31-90bc-624b7d428b50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952249146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1952249146
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1300425799
Short name T202
Test name
Test status
Simulation time 1271463066 ps
CPU time 19.46 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:19 PM PDT 24
Peak memory 220072 kb
Host smart-acc9cb4f-98d7-4c76-b7d5-602f1666bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300425799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1300425799
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3915924681
Short name T106
Test name
Test status
Simulation time 750105453 ps
CPU time 10.18 seconds
Started Aug 03 04:34:01 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 219960 kb
Host smart-6a5eedef-d6cc-4617-a9ec-ffe2746329d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915924681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3915924681
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2384055579
Short name T149
Test name
Test status
Simulation time 3452439462 ps
CPU time 27.09 seconds
Started Aug 03 04:33:57 PM PDT 24
Finished Aug 03 04:34:24 PM PDT 24
Peak memory 220060 kb
Host smart-577ef6ac-f3cf-43ca-b9ca-c411d9c1ff25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384055579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2384055579
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3457759717
Short name T52
Test name
Test status
Simulation time 87922190417 ps
CPU time 3015.68 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 236548 kb
Host smart-04641ca8-f693-46b9-ada1-354b53217249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457759717 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3457759717
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.874639003
Short name T129
Test name
Test status
Simulation time 752134967 ps
CPU time 8.31 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:33:55 PM PDT 24
Peak memory 219108 kb
Host smart-ae7fe9ff-4e2e-42be-995a-6f3f9916573d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874639003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.874639003
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.495183969
Short name T228
Test name
Test status
Simulation time 2740443620 ps
CPU time 207.63 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:37:18 PM PDT 24
Peak memory 243780 kb
Host smart-69d4e3f4-191d-4c4c-b9f1-8c58e5a7507d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495183969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.495183969
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2982250697
Short name T317
Test name
Test status
Simulation time 2068931200 ps
CPU time 22.71 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:34:10 PM PDT 24
Peak memory 219984 kb
Host smart-4184026c-5f69-4b33-bd9c-629c4167bf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982250697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2982250697
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.595358268
Short name T118
Test name
Test status
Simulation time 1106675328 ps
CPU time 11.98 seconds
Started Aug 03 04:34:01 PM PDT 24
Finished Aug 03 04:34:13 PM PDT 24
Peak memory 219952 kb
Host smart-86182f68-0242-4974-a223-7ff3dc2b252e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595358268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.595358268
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3873533756
Short name T227
Test name
Test status
Simulation time 588706370 ps
CPU time 16.35 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 220016 kb
Host smart-57e71cd5-3b66-4386-8924-9c6e22451cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873533756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3873533756
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1687363051
Short name T302
Test name
Test status
Simulation time 249954771 ps
CPU time 10.01 seconds
Started Aug 03 04:33:48 PM PDT 24
Finished Aug 03 04:33:58 PM PDT 24
Peak memory 218980 kb
Host smart-0bad3880-331c-4daf-9129-5ec6f75a1d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687363051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1687363051
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3666129138
Short name T163
Test name
Test status
Simulation time 3559395593 ps
CPU time 178.23 seconds
Started Aug 03 04:34:04 PM PDT 24
Finished Aug 03 04:37:03 PM PDT 24
Peak memory 225672 kb
Host smart-6532eae0-e76a-4823-bdd9-9f7495c2c9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666129138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3666129138
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1417952314
Short name T123
Test name
Test status
Simulation time 1603856131 ps
CPU time 11.8 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 220092 kb
Host smart-5f6a0d40-4b87-439e-90bf-6b47923ec4be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417952314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1417952314
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.376604514
Short name T222
Test name
Test status
Simulation time 1480847126 ps
CPU time 20.85 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:34:08 PM PDT 24
Peak memory 219908 kb
Host smart-ec61c3a8-de3c-4d0b-80d5-4deee6f09ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376604514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.376604514
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4225097949
Short name T246
Test name
Test status
Simulation time 662826579 ps
CPU time 8.58 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:33:31 PM PDT 24
Peak memory 218952 kb
Host smart-096d5377-ab12-440b-a63b-7375a5447404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225097949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4225097949
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4088200387
Short name T38
Test name
Test status
Simulation time 2202542466 ps
CPU time 149.83 seconds
Started Aug 03 04:33:20 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 238768 kb
Host smart-436e2185-2e26-40ea-9210-83ec47a9a9a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088200387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4088200387
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2124565183
Short name T312
Test name
Test status
Simulation time 2489963905 ps
CPU time 23.95 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:49 PM PDT 24
Peak memory 221528 kb
Host smart-3942ffe5-70d2-47dc-97f5-9dae1840ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124565183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2124565183
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2881112457
Short name T223
Test name
Test status
Simulation time 1104940740 ps
CPU time 11.63 seconds
Started Aug 03 04:34:22 PM PDT 24
Finished Aug 03 04:34:34 PM PDT 24
Peak memory 217576 kb
Host smart-98d0000d-1521-4804-bd12-4a246fb35c63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881112457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2881112457
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4144927608
Short name T17
Test name
Test status
Simulation time 1123834525 ps
CPU time 217.9 seconds
Started Aug 03 04:34:22 PM PDT 24
Finished Aug 03 04:38:00 PM PDT 24
Peak memory 233288 kb
Host smart-dcc887d2-8540-409a-99b9-746618d73e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144927608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4144927608
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1335611431
Short name T234
Test name
Test status
Simulation time 1033624729 ps
CPU time 12.64 seconds
Started Aug 03 04:33:31 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 219988 kb
Host smart-812d9978-7032-4316-ae25-b8fb498b0cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335611431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1335611431
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.604718281
Short name T133
Test name
Test status
Simulation time 577093388 ps
CPU time 31.89 seconds
Started Aug 03 04:33:21 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 219880 kb
Host smart-b78234ac-b2e1-4cba-813f-b644bdd48af5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604718281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.604718281
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1973135945
Short name T30
Test name
Test status
Simulation time 251494841 ps
CPU time 9.74 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:33:59 PM PDT 24
Peak memory 219016 kb
Host smart-e1b57fe2-89f6-41f2-80cb-ea833b8af3f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973135945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1973135945
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3233502767
Short name T269
Test name
Test status
Simulation time 4151344459 ps
CPU time 231.25 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:37:43 PM PDT 24
Peak memory 239600 kb
Host smart-60627dc9-2643-4afa-b820-d3d39f744f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233502767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3233502767
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4268895542
Short name T115
Test name
Test status
Simulation time 2056900439 ps
CPU time 22.33 seconds
Started Aug 03 04:34:03 PM PDT 24
Finished Aug 03 04:34:25 PM PDT 24
Peak memory 220096 kb
Host smart-45a29f8f-ebf0-451e-bfeb-4d7ef01c4389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268895542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4268895542
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3648739832
Short name T107
Test name
Test status
Simulation time 721609097 ps
CPU time 10.29 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:33:57 PM PDT 24
Peak memory 219980 kb
Host smart-d29c7b63-4fd3-4e91-ba46-f16d9dce0877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648739832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3648739832
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.467629331
Short name T212
Test name
Test status
Simulation time 501588834 ps
CPU time 15.02 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:16 PM PDT 24
Peak memory 219920 kb
Host smart-55a7e7da-f6a0-4fc3-81a1-606d4505bddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467629331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.467629331
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2988828172
Short name T281
Test name
Test status
Simulation time 917722407 ps
CPU time 10.07 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:33:59 PM PDT 24
Peak memory 219036 kb
Host smart-599ea83c-c508-4b00-956f-b085a4d4fa1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988828172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2988828172
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2341650757
Short name T37
Test name
Test status
Simulation time 14030172558 ps
CPU time 220.47 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:37:33 PM PDT 24
Peak memory 234492 kb
Host smart-8f877a47-6ab7-4a4d-80d1-08a1d608d99b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341650757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2341650757
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4248803380
Short name T186
Test name
Test status
Simulation time 1377030720 ps
CPU time 19.11 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:20 PM PDT 24
Peak memory 220016 kb
Host smart-6f865ea4-48f0-462c-85e8-1175ef209e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248803380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4248803380
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1519211970
Short name T121
Test name
Test status
Simulation time 266793910 ps
CPU time 12.34 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:13 PM PDT 24
Peak memory 219836 kb
Host smart-3edfaaef-126c-4fd9-81ab-a99491da0bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519211970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1519211970
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4064856789
Short name T134
Test name
Test status
Simulation time 375651985 ps
CPU time 13.97 seconds
Started Aug 03 04:34:01 PM PDT 24
Finished Aug 03 04:34:15 PM PDT 24
Peak memory 219964 kb
Host smart-016c9290-72ba-4cbf-ad80-141b582d17fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064856789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4064856789
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.4081370170
Short name T41
Test name
Test status
Simulation time 119642151515 ps
CPU time 1129.8 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 236528 kb
Host smart-ddbab606-b18f-4a91-8f7a-33fcc84c33bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081370170 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.4081370170
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1815847199
Short name T238
Test name
Test status
Simulation time 250394921 ps
CPU time 10.08 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 219148 kb
Host smart-1579c709-58e5-47a6-bc2a-d97cfd0203d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815847199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1815847199
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1525977566
Short name T101
Test name
Test status
Simulation time 5654569352 ps
CPU time 128.02 seconds
Started Aug 03 04:34:07 PM PDT 24
Finished Aug 03 04:36:15 PM PDT 24
Peak memory 220268 kb
Host smart-c692c56d-9558-4f6a-8bce-e1620fbd3e23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525977566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1525977566
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.347027741
Short name T237
Test name
Test status
Simulation time 2064418046 ps
CPU time 22.52 seconds
Started Aug 03 04:34:04 PM PDT 24
Finished Aug 03 04:34:26 PM PDT 24
Peak memory 220032 kb
Host smart-6e7e2e18-5127-46e2-afe3-c2a353054e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347027741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.347027741
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3594676684
Short name T168
Test name
Test status
Simulation time 1076369736 ps
CPU time 12.46 seconds
Started Aug 03 04:33:47 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219936 kb
Host smart-b0a6192f-b83e-4788-9d42-b90c37267a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594676684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3594676684
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3638357167
Short name T266
Test name
Test status
Simulation time 527102242 ps
CPU time 37.25 seconds
Started Aug 03 04:34:02 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 219952 kb
Host smart-ca59b77e-9a75-4cd6-a647-b0ed7619aac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638357167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3638357167
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1843223713
Short name T195
Test name
Test status
Simulation time 105446486613 ps
CPU time 523.67 seconds
Started Aug 03 04:34:03 PM PDT 24
Finished Aug 03 04:42:47 PM PDT 24
Peak memory 232448 kb
Host smart-f654bf37-0e9c-446e-ba42-24eb92fff1a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843223713 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1843223713
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2865887117
Short name T160
Test name
Test status
Simulation time 5493465817 ps
CPU time 14.53 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 218764 kb
Host smart-eb97c28a-c1e7-4764-b2f3-7ad89bd5917b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865887117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2865887117
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1925744261
Short name T242
Test name
Test status
Simulation time 5362112412 ps
CPU time 286.94 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:38:36 PM PDT 24
Peak memory 240924 kb
Host smart-1fdf5db2-58ec-4db8-980a-8df0337addb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925744261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1925744261
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1987365384
Short name T166
Test name
Test status
Simulation time 673371909 ps
CPU time 22.31 seconds
Started Aug 03 04:33:57 PM PDT 24
Finished Aug 03 04:34:20 PM PDT 24
Peak memory 219924 kb
Host smart-5f13390c-be63-46ed-a19d-baac8d6d3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987365384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1987365384
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3345822834
Short name T241
Test name
Test status
Simulation time 721255385 ps
CPU time 10.43 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 219872 kb
Host smart-81f74f13-9fa3-4db1-a443-571b7b4c3da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345822834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3345822834
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1815552710
Short name T124
Test name
Test status
Simulation time 5329705878 ps
CPU time 57.28 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 219980 kb
Host smart-01d40d37-1492-41ba-8d71-bfbdce5cbbf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815552710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1815552710
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3316308166
Short name T47
Test name
Test status
Simulation time 35860611011 ps
CPU time 7764.35 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 06:43:26 PM PDT 24
Peak memory 232956 kb
Host smart-868d8641-7db0-4147-9778-f5c420583b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316308166 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3316308166
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.555484999
Short name T260
Test name
Test status
Simulation time 1033510098 ps
CPU time 9.79 seconds
Started Aug 03 04:33:50 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219036 kb
Host smart-276d1fd5-e804-4acb-8a4a-fbf993b4e55b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555484999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.555484999
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3629929315
Short name T213
Test name
Test status
Simulation time 6956784120 ps
CPU time 346.65 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:39:36 PM PDT 24
Peak memory 220364 kb
Host smart-2a57bcd2-3264-4f44-8dd2-3ec05dde99e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629929315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3629929315
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4096932625
Short name T170
Test name
Test status
Simulation time 516793947 ps
CPU time 21.29 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:34:13 PM PDT 24
Peak memory 219972 kb
Host smart-dffd6673-bbbd-4435-b0bd-28a76150e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096932625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4096932625
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2118464450
Short name T306
Test name
Test status
Simulation time 185627694 ps
CPU time 10.72 seconds
Started Aug 03 04:33:49 PM PDT 24
Finished Aug 03 04:34:00 PM PDT 24
Peak memory 219944 kb
Host smart-fe09d907-629f-4d25-9978-27f49a84118b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118464450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2118464450
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3011432729
Short name T191
Test name
Test status
Simulation time 249824588 ps
CPU time 9.89 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:10 PM PDT 24
Peak memory 218908 kb
Host smart-4904865c-b11f-49b4-944e-1c5683b3dc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011432729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3011432729
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3885362662
Short name T145
Test name
Test status
Simulation time 17120987751 ps
CPU time 410.25 seconds
Started Aug 03 04:34:08 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 220236 kb
Host smart-f2b2fbb2-6389-4d7e-9356-b60d6f9bcb19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885362662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3885362662
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4033408197
Short name T43
Test name
Test status
Simulation time 1719182875 ps
CPU time 23.25 seconds
Started Aug 03 04:34:04 PM PDT 24
Finished Aug 03 04:34:28 PM PDT 24
Peak memory 220572 kb
Host smart-cd8b33e4-2ebc-4643-9b6b-1a49119af74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033408197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4033408197
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3748358424
Short name T216
Test name
Test status
Simulation time 374939353 ps
CPU time 12.22 seconds
Started Aug 03 04:34:04 PM PDT 24
Finished Aug 03 04:34:17 PM PDT 24
Peak memory 219956 kb
Host smart-aaff6340-b433-4611-a2dd-2e073fa0bcf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748358424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3748358424
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4252095700
Short name T180
Test name
Test status
Simulation time 2137492197 ps
CPU time 27.09 seconds
Started Aug 03 04:33:48 PM PDT 24
Finished Aug 03 04:34:15 PM PDT 24
Peak memory 219840 kb
Host smart-6f759408-c442-4fae-beda-9ec9e19be44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252095700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4252095700
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1502666309
Short name T247
Test name
Test status
Simulation time 790370069 ps
CPU time 8.19 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 219060 kb
Host smart-d006aee0-936f-402b-aa39-9f30ad8cce83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502666309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1502666309
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1244166106
Short name T208
Test name
Test status
Simulation time 4614326173 ps
CPU time 267.89 seconds
Started Aug 03 04:34:10 PM PDT 24
Finished Aug 03 04:38:38 PM PDT 24
Peak memory 238920 kb
Host smart-1de68875-cc13-4c25-a7a0-ff959763656d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244166106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1244166106
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3693812786
Short name T154
Test name
Test status
Simulation time 356924023 ps
CPU time 19.94 seconds
Started Aug 03 04:33:51 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 219984 kb
Host smart-1b2e8b8f-54bb-4f69-a36d-3043ce0127d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693812786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3693812786
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2953695677
Short name T103
Test name
Test status
Simulation time 3969410455 ps
CPU time 17.2 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:15 PM PDT 24
Peak memory 219804 kb
Host smart-58d5414e-d4f5-4ca5-8f53-156d41142e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953695677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2953695677
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3000801159
Short name T120
Test name
Test status
Simulation time 693065413 ps
CPU time 42.37 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:40 PM PDT 24
Peak memory 219896 kb
Host smart-5bea0d3c-61b2-4c95-bcf7-7c2fa6b51e0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000801159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3000801159
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4074601884
Short name T270
Test name
Test status
Simulation time 174610070 ps
CPU time 8.25 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:07 PM PDT 24
Peak memory 218984 kb
Host smart-e2143e94-5410-4461-8871-4763ca608874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074601884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4074601884
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2916849866
Short name T165
Test name
Test status
Simulation time 7502370019 ps
CPU time 380.84 seconds
Started Aug 03 04:34:08 PM PDT 24
Finished Aug 03 04:40:29 PM PDT 24
Peak memory 220328 kb
Host smart-ea2465c8-ec01-4ae0-863e-1cdc136b2c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916849866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2916849866
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3313564744
Short name T303
Test name
Test status
Simulation time 333865572 ps
CPU time 20.03 seconds
Started Aug 03 04:34:07 PM PDT 24
Finished Aug 03 04:34:27 PM PDT 24
Peak memory 219936 kb
Host smart-42ea067a-d11d-427b-bcfa-1f7c1b20971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313564744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3313564744
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.471650850
Short name T258
Test name
Test status
Simulation time 262318229 ps
CPU time 12.38 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:34:04 PM PDT 24
Peak memory 220004 kb
Host smart-c817542e-0e71-4d26-b557-077be407439e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471650850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.471650850
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2254188732
Short name T229
Test name
Test status
Simulation time 3426538994 ps
CPU time 38.53 seconds
Started Aug 03 04:33:54 PM PDT 24
Finished Aug 03 04:34:32 PM PDT 24
Peak memory 220036 kb
Host smart-c61fb59a-b3dd-423c-9d42-a6ed31e31af3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254188732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2254188732
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.228510695
Short name T10
Test name
Test status
Simulation time 250678527 ps
CPU time 9.81 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 218996 kb
Host smart-8a528674-0911-481d-a4b0-7eae96906923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228510695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.228510695
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1835193576
Short name T35
Test name
Test status
Simulation time 2957795425 ps
CPU time 163.36 seconds
Started Aug 03 04:34:10 PM PDT 24
Finished Aug 03 04:36:54 PM PDT 24
Peak memory 240028 kb
Host smart-a9c71141-44f5-47c6-80dd-f3a95b185448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835193576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1835193576
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1478335956
Short name T197
Test name
Test status
Simulation time 1773737568 ps
CPU time 22.98 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:34:18 PM PDT 24
Peak memory 220052 kb
Host smart-d933fe5c-8da0-4c94-9df9-898046450fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478335956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1478335956
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4035195653
Short name T138
Test name
Test status
Simulation time 185977036 ps
CPU time 10.41 seconds
Started Aug 03 04:33:55 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 219984 kb
Host smart-27fc8d62-61d9-4d77-b5a9-856d19bb034c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035195653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4035195653
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1628986835
Short name T132
Test name
Test status
Simulation time 1172815771 ps
CPU time 13.27 seconds
Started Aug 03 04:34:10 PM PDT 24
Finished Aug 03 04:34:24 PM PDT 24
Peak memory 219796 kb
Host smart-aab79658-3068-4965-a430-711f94665775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628986835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1628986835
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1878378164
Short name T225
Test name
Test status
Simulation time 332529225 ps
CPU time 8.51 seconds
Started Aug 03 04:33:53 PM PDT 24
Finished Aug 03 04:34:02 PM PDT 24
Peak memory 219048 kb
Host smart-c8900618-e8a6-4510-855d-c65cc596e39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878378164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1878378164
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4045971209
Short name T3
Test name
Test status
Simulation time 4867508495 ps
CPU time 145.34 seconds
Started Aug 03 04:33:56 PM PDT 24
Finished Aug 03 04:36:21 PM PDT 24
Peak memory 220280 kb
Host smart-722130e9-ea2f-4f4c-8ef2-1be4bfbfb1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045971209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4045971209
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.873733541
Short name T204
Test name
Test status
Simulation time 339089051 ps
CPU time 18.82 seconds
Started Aug 03 04:34:00 PM PDT 24
Finished Aug 03 04:34:19 PM PDT 24
Peak memory 219960 kb
Host smart-63b79f43-da58-40eb-82f5-7c0a74f07b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873733541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.873733541
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4270963606
Short name T190
Test name
Test status
Simulation time 266428308 ps
CPU time 12.26 seconds
Started Aug 03 04:33:58 PM PDT 24
Finished Aug 03 04:34:10 PM PDT 24
Peak memory 219992 kb
Host smart-b8d50a9e-9f3c-451b-81d3-f21c96c94524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270963606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4270963606
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.753695347
Short name T26
Test name
Test status
Simulation time 1031522356 ps
CPU time 27.33 seconds
Started Aug 03 04:33:52 PM PDT 24
Finished Aug 03 04:34:20 PM PDT 24
Peak memory 219964 kb
Host smart-2a265aae-ed94-4945-ac57-ae5935a65375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753695347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.753695347
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3943946865
Short name T282
Test name
Test status
Simulation time 538827067 ps
CPU time 10.12 seconds
Started Aug 03 04:33:21 PM PDT 24
Finished Aug 03 04:33:31 PM PDT 24
Peak memory 219148 kb
Host smart-42525ad2-9747-4bc7-a5e7-96d7e762199c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943946865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3943946865
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1911395456
Short name T315
Test name
Test status
Simulation time 7546304413 ps
CPU time 222.61 seconds
Started Aug 03 04:33:16 PM PDT 24
Finished Aug 03 04:36:59 PM PDT 24
Peak memory 234452 kb
Host smart-16967c2c-4dc5-4498-ac84-8518f520bbca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911395456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1911395456
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.696575645
Short name T27
Test name
Test status
Simulation time 691514932 ps
CPU time 19.45 seconds
Started Aug 03 04:33:17 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219972 kb
Host smart-338e176a-4e13-4071-928b-02ae5a09ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696575645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.696575645
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2057187664
Short name T25
Test name
Test status
Simulation time 362541086 ps
CPU time 9.86 seconds
Started Aug 03 04:34:24 PM PDT 24
Finished Aug 03 04:34:34 PM PDT 24
Peak memory 219524 kb
Host smart-0278496f-70fa-4b05-a401-9eecef8902ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057187664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2057187664
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3009381062
Short name T189
Test name
Test status
Simulation time 1593629864 ps
CPU time 12.25 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:34:36 PM PDT 24
Peak memory 217560 kb
Host smart-2474620e-2d56-4e94-923b-d434898ac9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009381062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3009381062
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3135194829
Short name T110
Test name
Test status
Simulation time 554620679 ps
CPU time 35.33 seconds
Started Aug 03 04:34:22 PM PDT 24
Finished Aug 03 04:34:58 PM PDT 24
Peak memory 217700 kb
Host smart-d0bc6264-c8d2-46c4-b812-3c3ec4db995d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135194829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3135194829
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3688300053
Short name T299
Test name
Test status
Simulation time 971387572 ps
CPU time 8.29 seconds
Started Aug 03 04:33:15 PM PDT 24
Finished Aug 03 04:33:24 PM PDT 24
Peak memory 218832 kb
Host smart-a86f461d-b590-44ca-acc0-f3c26c895af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688300053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3688300053
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3209397338
Short name T255
Test name
Test status
Simulation time 25014934478 ps
CPU time 319.6 seconds
Started Aug 03 04:34:22 PM PDT 24
Finished Aug 03 04:39:42 PM PDT 24
Peak memory 237736 kb
Host smart-23f11ac2-176f-49fa-a767-a3f05cf64b01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209397338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3209397338
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2303208158
Short name T284
Test name
Test status
Simulation time 517772645 ps
CPU time 22.12 seconds
Started Aug 03 04:33:15 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219944 kb
Host smart-dae83aa0-9863-4713-8b97-dae93be23430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303208158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2303208158
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2050967087
Short name T211
Test name
Test status
Simulation time 402081043 ps
CPU time 12.28 seconds
Started Aug 03 04:33:18 PM PDT 24
Finished Aug 03 04:33:30 PM PDT 24
Peak memory 220012 kb
Host smart-56511f1c-4211-43ef-9423-3e0acdae0f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050967087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2050967087
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2126238894
Short name T74
Test name
Test status
Simulation time 268968072 ps
CPU time 12.41 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219992 kb
Host smart-a2efee84-9bdf-45b2-89a8-ca101d094021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126238894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2126238894
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3235786683
Short name T183
Test name
Test status
Simulation time 3320448164 ps
CPU time 44.22 seconds
Started Aug 03 04:34:23 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 217620 kb
Host smart-c0395f25-880d-42f7-a489-ff743ec422f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235786683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3235786683
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.771349910
Short name T139
Test name
Test status
Simulation time 176495175 ps
CPU time 8.4 seconds
Started Aug 03 04:33:34 PM PDT 24
Finished Aug 03 04:33:43 PM PDT 24
Peak memory 218980 kb
Host smart-80d80be2-3901-4cb9-b905-d5a23e6f624a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771349910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.771349910
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2414758206
Short name T300
Test name
Test status
Simulation time 13402755911 ps
CPU time 241.85 seconds
Started Aug 03 04:33:21 PM PDT 24
Finished Aug 03 04:37:23 PM PDT 24
Peak memory 238396 kb
Host smart-5e7fb547-e91e-4046-aebe-edfbf7a14d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414758206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2414758206
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2143193941
Short name T150
Test name
Test status
Simulation time 342708679 ps
CPU time 19.49 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:43 PM PDT 24
Peak memory 219956 kb
Host smart-8dd82be7-c4ab-4de2-aabb-db847a4c148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143193941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2143193941
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3003382775
Short name T267
Test name
Test status
Simulation time 967306484 ps
CPU time 9.71 seconds
Started Aug 03 04:34:33 PM PDT 24
Finished Aug 03 04:34:42 PM PDT 24
Peak memory 219708 kb
Host smart-b296b184-22e0-4174-bbf2-9593fe14c9b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003382775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3003382775
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2341425847
Short name T263
Test name
Test status
Simulation time 2107826259 ps
CPU time 12.15 seconds
Started Aug 03 04:33:17 PM PDT 24
Finished Aug 03 04:33:30 PM PDT 24
Peak memory 219964 kb
Host smart-92ebcfb9-50fd-45ef-b735-c89587d73201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341425847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2341425847
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1429131783
Short name T70
Test name
Test status
Simulation time 3198287277 ps
CPU time 27.27 seconds
Started Aug 03 04:33:26 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 220036 kb
Host smart-33f545a8-0359-45e3-8ced-b4e13476a03c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429131783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1429131783
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.871909808
Short name T20
Test name
Test status
Simulation time 4122250979 ps
CPU time 10.04 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 219264 kb
Host smart-5cc49d6e-b66b-4123-b6b8-e857bff50c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871909808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.871909808
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1708000232
Short name T253
Test name
Test status
Simulation time 38281548930 ps
CPU time 206.43 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:36:49 PM PDT 24
Peak memory 234512 kb
Host smart-bd0c22dc-a994-4e46-acd7-ab6c0242be98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708000232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1708000232
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1083048314
Short name T44
Test name
Test status
Simulation time 336633556 ps
CPU time 19.38 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 219968 kb
Host smart-b8f8752a-bc3c-4cd3-a7d8-b835f6aa14f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083048314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1083048314
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1161078638
Short name T162
Test name
Test status
Simulation time 181103109 ps
CPU time 10.62 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:33:35 PM PDT 24
Peak memory 220220 kb
Host smart-f6271d96-3e28-42f6-844f-493fd12f721d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161078638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1161078638
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2385482921
Short name T130
Test name
Test status
Simulation time 4172119293 ps
CPU time 19.36 seconds
Started Aug 03 04:33:28 PM PDT 24
Finished Aug 03 04:33:48 PM PDT 24
Peak memory 220064 kb
Host smart-ff35826a-7a61-4195-9f72-879a047e0f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385482921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2385482921
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4108274291
Short name T311
Test name
Test status
Simulation time 531972938 ps
CPU time 19.29 seconds
Started Aug 03 04:33:26 PM PDT 24
Finished Aug 03 04:33:45 PM PDT 24
Peak memory 219576 kb
Host smart-38f08f16-32e5-472a-8bcc-0579bb710dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108274291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4108274291
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1273087130
Short name T277
Test name
Test status
Simulation time 339920391 ps
CPU time 8.19 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:35 PM PDT 24
Peak memory 218920 kb
Host smart-8945cfcf-57dd-41b9-a2ca-8a0dfc9485dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273087130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1273087130
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1490082411
Short name T36
Test name
Test status
Simulation time 4453478053 ps
CPU time 306.17 seconds
Started Aug 03 04:33:24 PM PDT 24
Finished Aug 03 04:38:31 PM PDT 24
Peak memory 235220 kb
Host smart-fa2245a0-3ae9-4608-b507-09609b237f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490082411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1490082411
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2821964056
Short name T307
Test name
Test status
Simulation time 513493831 ps
CPU time 22.91 seconds
Started Aug 03 04:33:23 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 219892 kb
Host smart-5a2e5842-9755-4106-a110-dce08abe770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821964056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2821964056
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2622518271
Short name T288
Test name
Test status
Simulation time 1023804657 ps
CPU time 12.31 seconds
Started Aug 03 04:33:25 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 219944 kb
Host smart-50a506c1-a5a3-4db1-baa8-9e285c4e3e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622518271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2622518271
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3519949225
Short name T157
Test name
Test status
Simulation time 1078825965 ps
CPU time 12.42 seconds
Started Aug 03 04:33:27 PM PDT 24
Finished Aug 03 04:33:40 PM PDT 24
Peak memory 219960 kb
Host smart-0cdb163b-1108-425b-ba93-e449b25e9ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519949225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3519949225
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.399600903
Short name T274
Test name
Test status
Simulation time 1328577607 ps
CPU time 58.13 seconds
Started Aug 03 04:33:22 PM PDT 24
Finished Aug 03 04:34:21 PM PDT 24
Peak memory 220012 kb
Host smart-475cb9fa-b817-4932-97e0-0d5e61b42736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399600903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.399600903
Directory /workspace/9.rom_ctrl_stress_all/latest
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