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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.13 96.89 91.85 97.68 100.00 98.28 97.30 97.90


Total test records in report: 402
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T299 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4245655059 Aug 04 05:32:15 PM PDT 24 Aug 04 05:34:32 PM PDT 24 7216233563 ps
T300 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4207996483 Aug 04 05:31:55 PM PDT 24 Aug 04 05:36:40 PM PDT 24 8216750270 ps
T301 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3048821694 Aug 04 05:32:10 PM PDT 24 Aug 04 05:37:26 PM PDT 24 8827200012 ps
T302 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3492069842 Aug 04 05:31:42 PM PDT 24 Aug 04 05:36:23 PM PDT 24 52116512043 ps
T303 /workspace/coverage/default/3.rom_ctrl_alert_test.637829622 Aug 04 05:31:48 PM PDT 24 Aug 04 05:32:04 PM PDT 24 1045566714 ps
T304 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3687314739 Aug 04 05:31:31 PM PDT 24 Aug 04 05:31:50 PM PDT 24 2356429357 ps
T305 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.792406365 Aug 04 05:32:07 PM PDT 24 Aug 04 05:32:20 PM PDT 24 271491382 ps
T28 /workspace/coverage/default/0.rom_ctrl_sec_cm.1936555594 Aug 04 05:31:39 PM PDT 24 Aug 04 05:35:25 PM PDT 24 341056028 ps
T306 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3897427454 Aug 04 05:32:11 PM PDT 24 Aug 04 05:32:31 PM PDT 24 1507902319 ps
T307 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3892492508 Aug 04 05:32:06 PM PDT 24 Aug 04 05:32:28 PM PDT 24 2249081608 ps
T308 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3473492631 Aug 04 05:31:50 PM PDT 24 Aug 04 05:36:17 PM PDT 24 4490400209 ps
T309 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2111399540 Aug 04 05:32:08 PM PDT 24 Aug 04 05:32:18 PM PDT 24 185023368 ps
T310 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3344280533 Aug 04 05:31:33 PM PDT 24 Aug 04 05:31:56 PM PDT 24 1766187757 ps
T311 /workspace/coverage/default/36.rom_ctrl_alert_test.3642534295 Aug 04 05:32:10 PM PDT 24 Aug 04 05:32:21 PM PDT 24 991609735 ps
T312 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.969907777 Aug 04 05:32:02 PM PDT 24 Aug 04 05:32:21 PM PDT 24 333753367 ps
T313 /workspace/coverage/default/22.rom_ctrl_stress_all.492282936 Aug 04 05:32:05 PM PDT 24 Aug 04 05:32:17 PM PDT 24 438343761 ps
T314 /workspace/coverage/default/44.rom_ctrl_alert_test.854765972 Aug 04 05:32:09 PM PDT 24 Aug 04 05:32:18 PM PDT 24 345567039 ps
T315 /workspace/coverage/default/47.rom_ctrl_stress_all.3770498729 Aug 04 05:32:16 PM PDT 24 Aug 04 05:32:36 PM PDT 24 1604812308 ps
T316 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1115388994 Aug 04 05:32:06 PM PDT 24 Aug 04 05:32:19 PM PDT 24 519532996 ps
T317 /workspace/coverage/default/46.rom_ctrl_stress_all.2846511643 Aug 04 05:32:17 PM PDT 24 Aug 04 05:32:55 PM PDT 24 700908549 ps
T318 /workspace/coverage/default/0.rom_ctrl_stress_all.91680062 Aug 04 05:31:26 PM PDT 24 Aug 04 05:31:49 PM PDT 24 521507664 ps
T319 /workspace/coverage/default/42.rom_ctrl_stress_all.3135629530 Aug 04 05:32:05 PM PDT 24 Aug 04 05:32:16 PM PDT 24 2568329947 ps
T320 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1187613021 Aug 04 05:31:46 PM PDT 24 Aug 04 05:31:57 PM PDT 24 184209098 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.1371365468 Aug 04 05:31:30 PM PDT 24 Aug 04 05:33:29 PM PDT 24 597883166 ps
T321 /workspace/coverage/default/26.rom_ctrl_alert_test.4018923368 Aug 04 05:32:01 PM PDT 24 Aug 04 05:32:09 PM PDT 24 169526355 ps
T322 /workspace/coverage/default/46.rom_ctrl_alert_test.4074337850 Aug 04 05:32:18 PM PDT 24 Aug 04 05:32:26 PM PDT 24 719490004 ps
T323 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.174055711 Aug 04 05:28:22 PM PDT 24 Aug 04 05:28:35 PM PDT 24 2064788267 ps
T57 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1938607307 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:25 PM PDT 24 1021294903 ps
T324 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1349308888 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:29 PM PDT 24 4095796374 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1116767972 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:38 PM PDT 24 2090563086 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4179738935 Aug 04 05:28:27 PM PDT 24 Aug 04 05:28:36 PM PDT 24 181352904 ps
T64 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3834222293 Aug 04 05:28:31 PM PDT 24 Aug 04 05:28:41 PM PDT 24 250127835 ps
T325 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3535459055 Aug 04 05:28:27 PM PDT 24 Aug 04 05:28:37 PM PDT 24 192089870 ps
T54 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.149706292 Aug 04 05:28:21 PM PDT 24 Aug 04 05:30:56 PM PDT 24 1489182111 ps
T96 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2597005405 Aug 04 05:28:17 PM PDT 24 Aug 04 05:28:25 PM PDT 24 338317799 ps
T326 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2848169588 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:28 PM PDT 24 1765975466 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3294141135 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:13 PM PDT 24 689129345 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3717052063 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:20 PM PDT 24 263086776 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1646632022 Aug 04 05:28:12 PM PDT 24 Aug 04 05:28:21 PM PDT 24 692216275 ps
T327 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2029701444 Aug 04 05:28:22 PM PDT 24 Aug 04 05:28:33 PM PDT 24 270575341 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2392329189 Aug 04 05:28:22 PM PDT 24 Aug 04 05:28:32 PM PDT 24 260449735 ps
T328 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2351774480 Aug 04 05:28:10 PM PDT 24 Aug 04 05:28:21 PM PDT 24 1146329095 ps
T329 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1474136077 Aug 04 05:28:37 PM PDT 24 Aug 04 05:28:47 PM PDT 24 259305424 ps
T330 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2347593124 Aug 04 05:28:34 PM PDT 24 Aug 04 05:28:45 PM PDT 24 530306498 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2684912601 Aug 04 05:28:16 PM PDT 24 Aug 04 05:28:25 PM PDT 24 691214493 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2755032816 Aug 04 05:28:24 PM PDT 24 Aug 04 05:28:34 PM PDT 24 990301806 ps
T55 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2270795223 Aug 04 05:28:35 PM PDT 24 Aug 04 05:31:11 PM PDT 24 1848928768 ps
T67 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2138271913 Aug 04 05:28:34 PM PDT 24 Aug 04 05:28:44 PM PDT 24 2474818648 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2562248459 Aug 04 05:28:34 PM PDT 24 Aug 04 05:28:43 PM PDT 24 169777301 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1192915337 Aug 04 05:28:12 PM PDT 24 Aug 04 05:29:32 PM PDT 24 2394705402 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3699300488 Aug 04 05:28:27 PM PDT 24 Aug 04 05:31:05 PM PDT 24 1900572731 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.43666218 Aug 04 05:28:28 PM PDT 24 Aug 04 05:31:03 PM PDT 24 1165854882 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1411253323 Aug 04 05:28:32 PM PDT 24 Aug 04 05:29:54 PM PDT 24 269153772 ps
T331 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2648101931 Aug 04 05:28:09 PM PDT 24 Aug 04 05:29:31 PM PDT 24 322073446 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2635347453 Aug 04 05:28:16 PM PDT 24 Aug 04 05:28:31 PM PDT 24 385760719 ps
T332 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1366085651 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:15 PM PDT 24 275511816 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1703640107 Aug 04 05:28:24 PM PDT 24 Aug 04 05:28:34 PM PDT 24 4936773370 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2198963145 Aug 04 05:28:24 PM PDT 24 Aug 04 05:28:33 PM PDT 24 665078737 ps
T333 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.168026243 Aug 04 05:28:35 PM PDT 24 Aug 04 05:28:48 PM PDT 24 2355273196 ps
T334 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1210179836 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:37 PM PDT 24 486276187 ps
T335 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4074327805 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:44 PM PDT 24 1304659610 ps
T71 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.560107293 Aug 04 05:28:25 PM PDT 24 Aug 04 05:28:33 PM PDT 24 661501556 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.542747318 Aug 04 05:28:30 PM PDT 24 Aug 04 05:31:07 PM PDT 24 419431221 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.492371052 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:42 PM PDT 24 266322837 ps
T336 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3114383352 Aug 04 05:28:10 PM PDT 24 Aug 04 05:28:20 PM PDT 24 263279632 ps
T337 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2611885978 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:24 PM PDT 24 573277597 ps
T338 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1856658461 Aug 04 05:28:30 PM PDT 24 Aug 04 05:28:42 PM PDT 24 700851166 ps
T339 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1365878044 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:27 PM PDT 24 169431961 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1000712591 Aug 04 05:28:24 PM PDT 24 Aug 04 05:28:35 PM PDT 24 251760162 ps
T340 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.870256476 Aug 04 05:28:33 PM PDT 24 Aug 04 05:28:42 PM PDT 24 243207031 ps
T341 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2095181878 Aug 04 05:28:19 PM PDT 24 Aug 04 05:28:29 PM PDT 24 250576869 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3543452818 Aug 04 05:28:17 PM PDT 24 Aug 04 05:28:55 PM PDT 24 710779298 ps
T81 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1464802610 Aug 04 05:28:27 PM PDT 24 Aug 04 05:28:35 PM PDT 24 425539183 ps
T342 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.458317918 Aug 04 05:28:30 PM PDT 24 Aug 04 05:28:45 PM PDT 24 993471556 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2051645748 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:38 PM PDT 24 1832907570 ps
T343 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4211831183 Aug 04 05:28:33 PM PDT 24 Aug 04 05:28:46 PM PDT 24 172768704 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2406171093 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:14 PM PDT 24 4963604324 ps
T345 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1874825391 Aug 04 05:28:21 PM PDT 24 Aug 04 05:29:45 PM PDT 24 726804842 ps
T94 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1803993484 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:40 PM PDT 24 1031223336 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1681547691 Aug 04 05:28:05 PM PDT 24 Aug 04 05:30:39 PM PDT 24 5417368598 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.700929328 Aug 04 05:28:11 PM PDT 24 Aug 04 05:28:29 PM PDT 24 902841290 ps
T346 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2913688718 Aug 04 05:28:27 PM PDT 24 Aug 04 05:28:44 PM PDT 24 1018609050 ps
T347 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2767435253 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:32 PM PDT 24 694050941 ps
T348 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.652164234 Aug 04 05:28:16 PM PDT 24 Aug 04 05:28:25 PM PDT 24 914750646 ps
T349 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.425440846 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:38 PM PDT 24 176562079 ps
T350 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1621163465 Aug 04 05:28:37 PM PDT 24 Aug 04 05:28:49 PM PDT 24 3358374980 ps
T351 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1838884730 Aug 04 05:28:21 PM PDT 24 Aug 04 05:28:29 PM PDT 24 167583409 ps
T111 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.826182889 Aug 04 05:28:18 PM PDT 24 Aug 04 05:30:52 PM PDT 24 589489851 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.655091107 Aug 04 05:28:33 PM PDT 24 Aug 04 05:28:43 PM PDT 24 385089749 ps
T352 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.726356289 Aug 04 05:28:14 PM PDT 24 Aug 04 05:29:36 PM PDT 24 467146860 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3435168443 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:33 PM PDT 24 347001437 ps
T353 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1763098920 Aug 04 05:28:08 PM PDT 24 Aug 04 05:28:18 PM PDT 24 253723211 ps
T354 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1954033241 Aug 04 05:28:22 PM PDT 24 Aug 04 05:28:35 PM PDT 24 174808009 ps
T355 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3291252022 Aug 04 05:28:17 PM PDT 24 Aug 04 05:28:29 PM PDT 24 1028452917 ps
T356 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3127281476 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:39 PM PDT 24 469882410 ps
T357 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3137339449 Aug 04 05:28:06 PM PDT 24 Aug 04 05:28:16 PM PDT 24 262232251 ps
T358 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2111693386 Aug 04 05:28:36 PM PDT 24 Aug 04 05:28:44 PM PDT 24 662321505 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1987386395 Aug 04 05:28:32 PM PDT 24 Aug 04 05:29:10 PM PDT 24 689927133 ps
T359 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3607643458 Aug 04 05:28:20 PM PDT 24 Aug 04 05:28:28 PM PDT 24 560167712 ps
T360 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.131726971 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:46 PM PDT 24 272979465 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.518722489 Aug 04 05:28:24 PM PDT 24 Aug 04 05:29:46 PM PDT 24 958074406 ps
T362 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4267169935 Aug 04 05:28:13 PM PDT 24 Aug 04 05:28:25 PM PDT 24 177133631 ps
T363 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3604432156 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:42 PM PDT 24 883200337 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.185997249 Aug 04 05:28:31 PM PDT 24 Aug 04 05:28:39 PM PDT 24 287412779 ps
T364 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3865206820 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:32 PM PDT 24 721236176 ps
T365 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3509385199 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:46 PM PDT 24 264028280 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1269225956 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:46 PM PDT 24 255554430 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1056654213 Aug 04 05:28:20 PM PDT 24 Aug 04 05:28:32 PM PDT 24 360919288 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2133600477 Aug 04 05:28:27 PM PDT 24 Aug 04 05:29:48 PM PDT 24 924325285 ps
T368 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.56154425 Aug 04 05:28:35 PM PDT 24 Aug 04 05:28:45 PM PDT 24 1030084412 ps
T86 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.937274084 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:41 PM PDT 24 613753285 ps
T87 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3860146612 Aug 04 05:28:31 PM PDT 24 Aug 04 05:28:41 PM PDT 24 986007885 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1960917902 Aug 04 05:28:22 PM PDT 24 Aug 04 05:28:31 PM PDT 24 1177052326 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2806865559 Aug 04 05:28:38 PM PDT 24 Aug 04 05:28:48 PM PDT 24 1128293435 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3367389250 Aug 04 05:28:26 PM PDT 24 Aug 04 05:28:38 PM PDT 24 338966826 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1961884162 Aug 04 05:28:26 PM PDT 24 Aug 04 05:28:34 PM PDT 24 175043069 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.271822809 Aug 04 05:28:23 PM PDT 24 Aug 04 05:28:31 PM PDT 24 170969369 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2252697062 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:24 PM PDT 24 1032080531 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3510849690 Aug 04 05:28:06 PM PDT 24 Aug 04 05:28:17 PM PDT 24 1030262020 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2367613439 Aug 04 05:28:19 PM PDT 24 Aug 04 05:28:27 PM PDT 24 174655230 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3822394140 Aug 04 05:28:07 PM PDT 24 Aug 04 05:29:30 PM PDT 24 3865214573 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3027568492 Aug 04 05:28:09 PM PDT 24 Aug 04 05:28:18 PM PDT 24 167326819 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1419603139 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:14 PM PDT 24 167659258 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.696155351 Aug 04 05:28:12 PM PDT 24 Aug 04 05:28:22 PM PDT 24 257444089 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3123110100 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:45 PM PDT 24 988998217 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2482610143 Aug 04 05:28:35 PM PDT 24 Aug 04 05:28:50 PM PDT 24 496036554 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1506830746 Aug 04 05:28:25 PM PDT 24 Aug 04 05:28:41 PM PDT 24 19811258548 ps
T383 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2548683959 Aug 04 05:28:29 PM PDT 24 Aug 04 05:28:40 PM PDT 24 1603119846 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2614371322 Aug 04 05:28:30 PM PDT 24 Aug 04 05:29:52 PM PDT 24 1251255823 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3118294393 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:25 PM PDT 24 529259863 ps
T384 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3170331195 Aug 04 05:28:36 PM PDT 24 Aug 04 05:28:50 PM PDT 24 2021320263 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3260315141 Aug 04 05:28:16 PM PDT 24 Aug 04 05:28:26 PM PDT 24 518252625 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1243023661 Aug 04 05:28:31 PM PDT 24 Aug 04 05:28:44 PM PDT 24 249206662 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1429569868 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:23 PM PDT 24 689671152 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2167478411 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:12 PM PDT 24 3309208160 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1767667511 Aug 04 05:28:19 PM PDT 24 Aug 04 05:28:32 PM PDT 24 1041707414 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1799852515 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:12 PM PDT 24 204148132 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1633896350 Aug 04 05:28:32 PM PDT 24 Aug 04 05:29:52 PM PDT 24 240652432 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2731119859 Aug 04 05:28:18 PM PDT 24 Aug 04 05:28:31 PM PDT 24 540901012 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.297962446 Aug 04 05:28:34 PM PDT 24 Aug 04 05:28:44 PM PDT 24 260578369 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.498568017 Aug 04 05:28:13 PM PDT 24 Aug 04 05:28:22 PM PDT 24 361797589 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.570003876 Aug 04 05:28:18 PM PDT 24 Aug 04 05:28:27 PM PDT 24 687706285 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2152478928 Aug 04 05:28:26 PM PDT 24 Aug 04 05:31:04 PM PDT 24 563347584 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.828622173 Aug 04 05:28:12 PM PDT 24 Aug 04 05:28:26 PM PDT 24 249950087 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3010542459 Aug 04 05:28:32 PM PDT 24 Aug 04 05:28:43 PM PDT 24 285838673 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1477015835 Aug 04 05:28:31 PM PDT 24 Aug 04 05:28:41 PM PDT 24 267640130 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2704898288 Aug 04 05:28:13 PM PDT 24 Aug 04 05:28:21 PM PDT 24 693125792 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4281951549 Aug 04 05:28:06 PM PDT 24 Aug 04 05:28:18 PM PDT 24 672930605 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1528775327 Aug 04 05:28:35 PM PDT 24 Aug 04 05:28:45 PM PDT 24 1039341308 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1671997955 Aug 04 05:28:16 PM PDT 24 Aug 04 05:28:31 PM PDT 24 3406701182 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.49660567 Aug 04 05:28:35 PM PDT 24 Aug 04 05:29:56 PM PDT 24 2449597788 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1049636372 Aug 04 05:28:23 PM PDT 24 Aug 04 05:29:45 PM PDT 24 260570589 ps

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2426100252
Short name T6
Test name
Test status
Simulation time 24193723853 ps
CPU time 479.76 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:40:06 PM PDT 24
Peak memory 230884 kb
Host smart-a4abc58f-7a52-4187-a44e-abddeedaf385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426100252 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2426100252
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1180436441
Short name T16
Test name
Test status
Simulation time 5194544649 ps
CPU time 276.43 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:36:43 PM PDT 24
Peak memory 234576 kb
Host smart-72f08fb3-96ca-41f3-bee4-cfb8adaedfd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180436441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1180436441
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1778754422
Short name T45
Test name
Test status
Simulation time 47972698060 ps
CPU time 8931.07 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 08:00:59 PM PDT 24
Peak memory 236628 kb
Host smart-4d40aa51-7b54-4624-a689-0595cf2fd49f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778754422 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1778754422
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2987206924
Short name T35
Test name
Test status
Simulation time 8662293920 ps
CPU time 289.51 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:36:42 PM PDT 24
Peak memory 219416 kb
Host smart-60835bbd-48d1-44ec-99a3-da6c32c9ef58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987206924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2987206924
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.149706292
Short name T54
Test name
Test status
Simulation time 1489182111 ps
CPU time 155.05 seconds
Started Aug 04 05:28:21 PM PDT 24
Finished Aug 04 05:30:56 PM PDT 24
Peak memory 214444 kb
Host smart-2961afa8-602f-4622-a626-60d18d04c7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149706292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.149706292
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1706847235
Short name T12
Test name
Test status
Simulation time 121955361869 ps
CPU time 9605.6 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 08:12:14 PM PDT 24
Peak memory 236572 kb
Host smart-107eafcf-15ae-498f-9f34-8eb600e4a478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706847235 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1706847235
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2981482810
Short name T8
Test name
Test status
Simulation time 296025462 ps
CPU time 16.59 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219992 kb
Host smart-8d7ef244-0f8f-4797-b78b-7921f037151b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981482810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2981482810
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.429906188
Short name T23
Test name
Test status
Simulation time 1406056124 ps
CPU time 224.42 seconds
Started Aug 04 05:31:31 PM PDT 24
Finished Aug 04 05:35:15 PM PDT 24
Peak memory 239784 kb
Host smart-3cce81d8-6ac4-47f0-9940-eaeb14b16488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429906188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.429906188
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.492371052
Short name T72
Test name
Test status
Simulation time 266322837 ps
CPU time 9.94 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 210944 kb
Host smart-da756b1f-3e4f-48e0-a7e4-18b9a8ac3322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492371052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.492371052
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2715425058
Short name T2
Test name
Test status
Simulation time 518903010 ps
CPU time 22.93 seconds
Started Aug 04 05:31:44 PM PDT 24
Finished Aug 04 05:32:07 PM PDT 24
Peak memory 220100 kb
Host smart-0e6e8e94-ebdf-4245-afc4-a8307344a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715425058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2715425058
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1633896350
Short name T103
Test name
Test status
Simulation time 240652432 ps
CPU time 79.73 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:29:52 PM PDT 24
Peak memory 214104 kb
Host smart-61625663-a564-4d0f-93f2-cca2b5a9a3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633896350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1633896350
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2066035281
Short name T278
Test name
Test status
Simulation time 3932771670 ps
CPU time 44.35 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:32:49 PM PDT 24
Peak memory 220196 kb
Host smart-86b936bb-b6d3-489d-b826-833f8269a793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066035281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2066035281
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2352154951
Short name T9
Test name
Test status
Simulation time 178288205 ps
CPU time 8.26 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 219144 kb
Host smart-03823d48-f7ee-4ac0-ad13-e4492370835c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352154951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2352154951
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2101768262
Short name T207
Test name
Test status
Simulation time 1375547253 ps
CPU time 19.22 seconds
Started Aug 04 05:31:47 PM PDT 24
Finished Aug 04 05:32:07 PM PDT 24
Peak memory 220096 kb
Host smart-ec398712-364e-4931-b072-009e84549104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101768262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2101768262
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2152478928
Short name T113
Test name
Test status
Simulation time 563347584 ps
CPU time 157.46 seconds
Started Aug 04 05:28:26 PM PDT 24
Finished Aug 04 05:31:04 PM PDT 24
Peak memory 215504 kb
Host smart-452278d0-ccaf-4339-837c-bc5706eaa418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152478928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2152478928
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2755032816
Short name T91
Test name
Test status
Simulation time 990301806 ps
CPU time 10.15 seconds
Started Aug 04 05:28:24 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 211324 kb
Host smart-ff82d489-2d1c-4703-871a-b741e1d5aa64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755032816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2755032816
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2133600477
Short name T105
Test name
Test status
Simulation time 924325285 ps
CPU time 80.8 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:29:48 PM PDT 24
Peak memory 213836 kb
Host smart-2c09960b-4ac0-4ecb-a946-aabcbaf6c575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133600477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2133600477
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1192915337
Short name T56
Test name
Test status
Simulation time 2394705402 ps
CPU time 80.56 seconds
Started Aug 04 05:28:12 PM PDT 24
Finished Aug 04 05:29:32 PM PDT 24
Peak memory 213080 kb
Host smart-b89bf24f-f18c-480d-8b14-df22263ca76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192915337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1192915337
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1724903808
Short name T47
Test name
Test status
Simulation time 1560584305 ps
CPU time 109.68 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:33:55 PM PDT 24
Peak memory 236688 kb
Host smart-462acc6b-8ffa-44bb-b4c8-c7aee79a2f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724903808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1724903808
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2540261532
Short name T247
Test name
Test status
Simulation time 1504322577 ps
CPU time 11.94 seconds
Started Aug 04 05:31:44 PM PDT 24
Finished Aug 04 05:31:56 PM PDT 24
Peak memory 220100 kb
Host smart-8d3032ce-2559-43f0-87d5-9858df59b000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540261532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2540261532
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.498568017
Short name T393
Test name
Test status
Simulation time 361797589 ps
CPU time 8.16 seconds
Started Aug 04 05:28:13 PM PDT 24
Finished Aug 04 05:28:22 PM PDT 24
Peak memory 211256 kb
Host smart-d7f5d133-4fb4-4c2b-9a0d-ea44fd778571
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498568017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.498568017
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3027568492
Short name T377
Test name
Test status
Simulation time 167326819 ps
CPU time 8.56 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:28:18 PM PDT 24
Peak memory 210928 kb
Host smart-2d383ae2-b66e-4ac6-9793-cd82f7b8ee63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027568492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3027568492
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2635347453
Short name T68
Test name
Test status
Simulation time 385760719 ps
CPU time 15.62 seconds
Started Aug 04 05:28:16 PM PDT 24
Finished Aug 04 05:28:31 PM PDT 24
Peak memory 212128 kb
Host smart-cb29c6f2-83a8-4361-8bc5-dd7da5faf66e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635347453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2635347453
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2351774480
Short name T328
Test name
Test status
Simulation time 1146329095 ps
CPU time 11 seconds
Started Aug 04 05:28:10 PM PDT 24
Finished Aug 04 05:28:21 PM PDT 24
Peak memory 216772 kb
Host smart-edfb693f-d8aa-469c-b19d-0ec49eed7bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351774480 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2351774480
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2406171093
Short name T344
Test name
Test status
Simulation time 4963604324 ps
CPU time 10.36 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:14 PM PDT 24
Peak memory 211784 kb
Host smart-42fad505-ca30-47a4-98c6-105e69860004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406171093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2406171093
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1960917902
Short name T369
Test name
Test status
Simulation time 1177052326 ps
CPU time 8.42 seconds
Started Aug 04 05:28:22 PM PDT 24
Finished Aug 04 05:28:31 PM PDT 24
Peak memory 210636 kb
Host smart-77cde30c-e339-4fe0-b2a0-b1708ae35e87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960917902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1960917902
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1763098920
Short name T353
Test name
Test status
Simulation time 253723211 ps
CPU time 9.83 seconds
Started Aug 04 05:28:08 PM PDT 24
Finished Aug 04 05:28:18 PM PDT 24
Peak memory 210796 kb
Host smart-e9fa92ae-937c-47bf-bd96-9d1d8f4665de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763098920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1763098920
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1671997955
Short name T401
Test name
Test status
Simulation time 3406701182 ps
CPU time 15.31 seconds
Started Aug 04 05:28:16 PM PDT 24
Finished Aug 04 05:28:31 PM PDT 24
Peak memory 211652 kb
Host smart-187fe47f-6583-46cf-b775-14d96c4698e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671997955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1671997955
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3291252022
Short name T355
Test name
Test status
Simulation time 1028452917 ps
CPU time 12.76 seconds
Started Aug 04 05:28:17 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 219184 kb
Host smart-c74c45e1-8570-4af2-9d8d-3c920a3062af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291252022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3291252022
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2648101931
Short name T331
Test name
Test status
Simulation time 322073446 ps
CPU time 81.34 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:29:31 PM PDT 24
Peak memory 212976 kb
Host smart-d68d6fab-3aba-4cd0-91b9-cb9a6af5dc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648101931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2648101931
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3118294393
Short name T89
Test name
Test status
Simulation time 529259863 ps
CPU time 10.11 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 210940 kb
Host smart-f079df5c-e1b1-408d-8627-ba9bf4a20ebb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118294393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3118294393
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3294141135
Short name T97
Test name
Test status
Simulation time 689129345 ps
CPU time 8.51 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:13 PM PDT 24
Peak memory 210324 kb
Host smart-70375e8e-b2da-4124-8cc2-264d3ac323a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294141135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3294141135
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4281951549
Short name T399
Test name
Test status
Simulation time 672930605 ps
CPU time 11.72 seconds
Started Aug 04 05:28:06 PM PDT 24
Finished Aug 04 05:28:18 PM PDT 24
Peak memory 210888 kb
Host smart-281c025c-da94-4f2b-98ff-66a4c099d721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281951549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4281951549
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1799852515
Short name T390
Test name
Test status
Simulation time 204148132 ps
CPU time 9.72 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:12 PM PDT 24
Peak memory 217912 kb
Host smart-356d27d6-5ae5-4d36-a6f7-6517bffbbdce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799852515 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1799852515
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2704898288
Short name T398
Test name
Test status
Simulation time 693125792 ps
CPU time 8.06 seconds
Started Aug 04 05:28:13 PM PDT 24
Finished Aug 04 05:28:21 PM PDT 24
Peak memory 211196 kb
Host smart-320e68bb-0409-47c8-b732-ca7378d068d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704898288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2704898288
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1838884730
Short name T351
Test name
Test status
Simulation time 167583409 ps
CPU time 7.97 seconds
Started Aug 04 05:28:21 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 210740 kb
Host smart-d0762080-6528-4b55-baee-cc96dfbfe939
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838884730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1838884730
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3260315141
Short name T385
Test name
Test status
Simulation time 518252625 ps
CPU time 10.1 seconds
Started Aug 04 05:28:16 PM PDT 24
Finished Aug 04 05:28:26 PM PDT 24
Peak memory 211024 kb
Host smart-291712ff-e02b-4024-b60e-881a121ff324
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260315141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3260315141
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3435168443
Short name T95
Test name
Test status
Simulation time 347001437 ps
CPU time 10.14 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:33 PM PDT 24
Peak memory 212064 kb
Host smart-9f1ee365-35d0-4866-a741-5d5f7149209d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435168443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3435168443
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.828622173
Short name T395
Test name
Test status
Simulation time 249950087 ps
CPU time 14.44 seconds
Started Aug 04 05:28:12 PM PDT 24
Finished Aug 04 05:28:26 PM PDT 24
Peak memory 219128 kb
Host smart-92d1bcf7-d6ff-4fc4-9aa7-97664ec0f601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828622173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.828622173
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1681547691
Short name T109
Test name
Test status
Simulation time 5417368598 ps
CPU time 154.46 seconds
Started Aug 04 05:28:05 PM PDT 24
Finished Aug 04 05:30:39 PM PDT 24
Peak memory 214816 kb
Host smart-e9126a6c-2899-4948-a1e3-5a96fa243153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681547691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1681547691
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3114383352
Short name T336
Test name
Test status
Simulation time 263279632 ps
CPU time 10.17 seconds
Started Aug 04 05:28:10 PM PDT 24
Finished Aug 04 05:28:20 PM PDT 24
Peak memory 216216 kb
Host smart-376ce6a2-7be0-4565-a642-7cdde792bde2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114383352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3114383352
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3170331195
Short name T384
Test name
Test status
Simulation time 2021320263 ps
CPU time 14.33 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:50 PM PDT 24
Peak memory 210956 kb
Host smart-5bb2f0c6-dd37-4bd3-ab4a-ceb7321097d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170331195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3170331195
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.131726971
Short name T360
Test name
Test status
Simulation time 272979465 ps
CPU time 13.86 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 212728 kb
Host smart-43940510-f3d3-4421-b30d-bb046de5d4d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131726971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.131726971
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1243023661
Short name T386
Test name
Test status
Simulation time 249206662 ps
CPU time 13.24 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 217652 kb
Host smart-25239630-448b-45e9-a5b2-3e1b04672dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243023661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1243023661
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1049636372
Short name T402
Test name
Test status
Simulation time 260570589 ps
CPU time 81.6 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 212844 kb
Host smart-920ee118-b12c-428b-9e8a-795d586a6667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049636372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1049636372
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.425440846
Short name T349
Test name
Test status
Simulation time 176562079 ps
CPU time 9.02 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 217328 kb
Host smart-ef1959d4-c77d-46b1-9740-242de3a5c771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425440846 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.425440846
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1269225956
Short name T366
Test name
Test status
Simulation time 255554430 ps
CPU time 14 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 212716 kb
Host smart-38429fa3-75a0-436a-9cf9-9061012282e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269225956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1269225956
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.174055711
Short name T323
Test name
Test status
Simulation time 2064788267 ps
CPU time 12.63 seconds
Started Aug 04 05:28:22 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 217648 kb
Host smart-285991d1-e48d-4e58-8102-1679b1bf54c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174055711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.174055711
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3535459055
Short name T325
Test name
Test status
Simulation time 192089870 ps
CPU time 10.39 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 218196 kb
Host smart-1a2e3e1f-a39c-4be1-9375-af51b4726a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535459055 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3535459055
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2252697062
Short name T374
Test name
Test status
Simulation time 1032080531 ps
CPU time 9.92 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:24 PM PDT 24
Peak memory 211240 kb
Host smart-8bb0d75a-a08c-4940-a1b0-5aab5b737154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252697062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2252697062
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3865206820
Short name T364
Test name
Test status
Simulation time 721236176 ps
CPU time 8.24 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 211736 kb
Host smart-8864cce4-210a-4293-9001-dbfbe9512c19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865206820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3865206820
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3604432156
Short name T363
Test name
Test status
Simulation time 883200337 ps
CPU time 13.7 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 219220 kb
Host smart-3c6d9189-6a9d-4d57-af78-0b4dbfaaeece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604432156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3604432156
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2270795223
Short name T55
Test name
Test status
Simulation time 1848928768 ps
CPU time 156.13 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:31:11 PM PDT 24
Peak memory 214384 kb
Host smart-bc2d8f4e-5169-4aec-b521-864013fbb84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270795223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2270795223
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1528775327
Short name T400
Test name
Test status
Simulation time 1039341308 ps
CPU time 10.43 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 216776 kb
Host smart-8ea2b795-e4a0-4c02-8a21-f0fe9ff51c17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528775327 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1528775327
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2095181878
Short name T341
Test name
Test status
Simulation time 250576869 ps
CPU time 10.1 seconds
Started Aug 04 05:28:19 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 211012 kb
Host smart-1e0abcfe-9e87-43c7-8398-7047a1bbcde7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095181878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2095181878
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2731119859
Short name T391
Test name
Test status
Simulation time 540901012 ps
CPU time 13.66 seconds
Started Aug 04 05:28:18 PM PDT 24
Finished Aug 04 05:28:31 PM PDT 24
Peak memory 213084 kb
Host smart-e747cb2a-7c16-484d-97d6-c51527d76cf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731119859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2731119859
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.518722489
Short name T361
Test name
Test status
Simulation time 958074406 ps
CPU time 81.36 seconds
Started Aug 04 05:28:24 PM PDT 24
Finished Aug 04 05:29:46 PM PDT 24
Peak memory 214116 kb
Host smart-e1c78772-8817-406a-89f9-c6c5ff266f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518722489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.518722489
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.458317918
Short name T342
Test name
Test status
Simulation time 993471556 ps
CPU time 14.6 seconds
Started Aug 04 05:28:30 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 217280 kb
Host smart-27f1838c-5040-4068-9a57-f5d900a76192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458317918 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.458317918
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3860146612
Short name T87
Test name
Test status
Simulation time 986007885 ps
CPU time 10.12 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 211356 kb
Host smart-3ff8ad22-56b5-4bf4-b66f-c75818e4f897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860146612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3860146612
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.271822809
Short name T373
Test name
Test status
Simulation time 170969369 ps
CPU time 8.47 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:31 PM PDT 24
Peak memory 211656 kb
Host smart-e18bb4b1-f74a-4ca1-b962-701629ad587d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271822809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.271822809
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.168026243
Short name T333
Test name
Test status
Simulation time 2355273196 ps
CPU time 12.52 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 216516 kb
Host smart-01edd5e9-d40f-4fe3-b1e8-543c1b6fba5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168026243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.168026243
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.542747318
Short name T108
Test name
Test status
Simulation time 419431221 ps
CPU time 157.66 seconds
Started Aug 04 05:28:30 PM PDT 24
Finished Aug 04 05:31:07 PM PDT 24
Peak memory 214612 kb
Host smart-cc5793f2-8cf5-4f69-93e8-7ec731a2440f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542747318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.542747318
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3010542459
Short name T396
Test name
Test status
Simulation time 285838673 ps
CPU time 11.44 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 217884 kb
Host smart-5cddfdb0-a3a3-471b-8fa3-2d6375165a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010542459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3010542459
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3834222293
Short name T64
Test name
Test status
Simulation time 250127835 ps
CPU time 9.96 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 211560 kb
Host smart-cdb49472-46f2-4327-b60c-10908f9e5081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834222293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3834222293
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4074327805
Short name T335
Test name
Test status
Simulation time 1304659610 ps
CPU time 14.78 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 217652 kb
Host smart-28bbc577-46e9-4fbb-9dc7-5d0dd8545142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074327805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4074327805
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.870256476
Short name T340
Test name
Test status
Simulation time 243207031 ps
CPU time 9.01 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 217368 kb
Host smart-8cdc1457-7616-4a3f-9fc5-245fdba95342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870256476 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.870256476
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.937274084
Short name T86
Test name
Test status
Simulation time 613753285 ps
CPU time 8.28 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 211308 kb
Host smart-ce1e737f-1506-4708-af91-f8c8e289b755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937274084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.937274084
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2051645748
Short name T93
Test name
Test status
Simulation time 1832907570 ps
CPU time 8.08 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 211752 kb
Host smart-b82ae6f7-2beb-4c3d-b87e-4a33175e7a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051645748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2051645748
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1210179836
Short name T334
Test name
Test status
Simulation time 486276187 ps
CPU time 14.32 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 217836 kb
Host smart-704f93b9-830f-480d-bd34-3f06250f9e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210179836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1210179836
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.43666218
Short name T112
Test name
Test status
Simulation time 1165854882 ps
CPU time 154.27 seconds
Started Aug 04 05:28:28 PM PDT 24
Finished Aug 04 05:31:03 PM PDT 24
Peak memory 214512 kb
Host smart-32b5decc-068c-4303-beae-4b50607b3035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43666218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_int
g_err.43666218
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2767435253
Short name T347
Test name
Test status
Simulation time 694050941 ps
CPU time 8.81 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 216140 kb
Host smart-cbc84609-b476-4248-bee4-f582914dbf82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767435253 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2767435253
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2806865559
Short name T370
Test name
Test status
Simulation time 1128293435 ps
CPU time 9.73 seconds
Started Aug 04 05:28:38 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 211216 kb
Host smart-dfe72b41-f345-480b-8b4d-37b0dbd3fff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806865559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2806865559
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2548683959
Short name T383
Test name
Test status
Simulation time 1603119846 ps
CPU time 11.73 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 212704 kb
Host smart-e4e0a780-da8e-4e19-a1ba-f6136fa953a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548683959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2548683959
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4211831183
Short name T343
Test name
Test status
Simulation time 172768704 ps
CPU time 12.63 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 217912 kb
Host smart-a2aeb99f-9e96-488f-8429-b6ac07e4f9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211831183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4211831183
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1621163465
Short name T350
Test name
Test status
Simulation time 3358374980 ps
CPU time 11.16 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 217984 kb
Host smart-1f9d139a-210e-4c6d-b2cd-9374b78bf77c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621163465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1621163465
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2111693386
Short name T358
Test name
Test status
Simulation time 662321505 ps
CPU time 8.21 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 210844 kb
Host smart-e47c614a-aaa3-4a87-a5dc-a822c9a4a952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111693386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2111693386
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1987386395
Short name T84
Test name
Test status
Simulation time 689927133 ps
CPU time 37.32 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 214024 kb
Host smart-863d5a87-1912-44b2-b3d6-66adbef49beb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987386395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1987386395
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2138271913
Short name T67
Test name
Test status
Simulation time 2474818648 ps
CPU time 10.13 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 212116 kb
Host smart-70709e4d-7b7d-4edd-afe3-1c2ede36f517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138271913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2138271913
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2482610143
Short name T381
Test name
Test status
Simulation time 496036554 ps
CPU time 14.65 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:50 PM PDT 24
Peak memory 219096 kb
Host smart-95503170-ae9f-482d-bc29-2fad01212525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482610143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2482610143
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.49660567
Short name T104
Test name
Test status
Simulation time 2449597788 ps
CPU time 80.84 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:29:56 PM PDT 24
Peak memory 214812 kb
Host smart-7a7d4bda-a22c-4dcd-a0a2-b7c74dc53b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49660567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_int
g_err.49660567
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2347593124
Short name T330
Test name
Test status
Simulation time 530306498 ps
CPU time 10.54 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 216148 kb
Host smart-e3e68460-9694-41d6-be27-835ac57a93d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347593124 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2347593124
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.56154425
Short name T368
Test name
Test status
Simulation time 1030084412 ps
CPU time 9.79 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 210920 kb
Host smart-155cecee-b941-4113-82be-72bb58a2a874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56154425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.56154425
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.297962446
Short name T392
Test name
Test status
Simulation time 260578369 ps
CPU time 10.25 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 211440 kb
Host smart-1d5b3dc6-7aad-4919-a00c-80a5b8f0fab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297962446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.297962446
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3509385199
Short name T365
Test name
Test status
Simulation time 264028280 ps
CPU time 14.14 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 219168 kb
Host smart-99124239-b89b-493a-aa80-8a9c7d2684b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509385199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3509385199
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1411253323
Short name T107
Test name
Test status
Simulation time 269153772 ps
CPU time 82.12 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:29:54 PM PDT 24
Peak memory 215252 kb
Host smart-39b97f63-1dec-4b7d-b239-e520b9ff01a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411253323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1411253323
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3510849690
Short name T88
Test name
Test status
Simulation time 1030262020 ps
CPU time 10.16 seconds
Started Aug 04 05:28:06 PM PDT 24
Finished Aug 04 05:28:17 PM PDT 24
Peak memory 210972 kb
Host smart-445ffd76-d6ab-4c8b-8487-ace3af3095ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510849690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3510849690
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2198963145
Short name T70
Test name
Test status
Simulation time 665078737 ps
CPU time 8.5 seconds
Started Aug 04 05:28:24 PM PDT 24
Finished Aug 04 05:28:33 PM PDT 24
Peak memory 210912 kb
Host smart-68707d33-a32e-44a7-8e91-c1cb8d355d0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198963145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2198963145
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3717052063
Short name T65
Test name
Test status
Simulation time 263086776 ps
CPU time 16.79 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:20 PM PDT 24
Peak memory 212236 kb
Host smart-b80d2ba9-79f7-4d47-8f6a-a6a1c1761270
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717052063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3717052063
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1366085651
Short name T332
Test name
Test status
Simulation time 275511816 ps
CPU time 10.92 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:15 PM PDT 24
Peak memory 217368 kb
Host smart-b706f02b-dea5-4176-a3c1-3cb25a54331f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366085651 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1366085651
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3137339449
Short name T357
Test name
Test status
Simulation time 262232251 ps
CPU time 9.9 seconds
Started Aug 04 05:28:06 PM PDT 24
Finished Aug 04 05:28:16 PM PDT 24
Peak memory 211428 kb
Host smart-97cfb1fd-320d-4703-ad60-c307c6f19d3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137339449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3137339449
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1349308888
Short name T324
Test name
Test status
Simulation time 4095796374 ps
CPU time 14.1 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 210804 kb
Host smart-b3bea16c-5746-4b75-8e9f-020e57c60eba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349308888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1349308888
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2611885978
Short name T337
Test name
Test status
Simulation time 573277597 ps
CPU time 8.33 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:24 PM PDT 24
Peak memory 210752 kb
Host smart-b4c66fa6-8b71-40d9-9b73-ab20d735719b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611885978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2611885978
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3543452818
Short name T92
Test name
Test status
Simulation time 710779298 ps
CPU time 37.51 seconds
Started Aug 04 05:28:17 PM PDT 24
Finished Aug 04 05:28:55 PM PDT 24
Peak memory 218428 kb
Host smart-1e784cb3-ab52-477c-a344-73b4941bba20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543452818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3543452818
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2167478411
Short name T388
Test name
Test status
Simulation time 3309208160 ps
CPU time 8.43 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:12 PM PDT 24
Peak memory 211728 kb
Host smart-e92ab67e-e42a-4550-8598-9438fcd30f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167478411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2167478411
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2848169588
Short name T326
Test name
Test status
Simulation time 1765975466 ps
CPU time 13.18 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:28 PM PDT 24
Peak memory 218764 kb
Host smart-2297a70c-bcf8-4a90-a1a9-4591bc26b0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848169588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2848169588
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1429569868
Short name T387
Test name
Test status
Simulation time 689671152 ps
CPU time 8.41 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:23 PM PDT 24
Peak memory 211272 kb
Host smart-e2456295-c548-42a6-83d2-3df349ac618d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429569868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1429569868
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.570003876
Short name T394
Test name
Test status
Simulation time 687706285 ps
CPU time 8.82 seconds
Started Aug 04 05:28:18 PM PDT 24
Finished Aug 04 05:28:27 PM PDT 24
Peak memory 210848 kb
Host smart-0ca93c61-4dcb-4c66-8d4c-b3d17ccf0a25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570003876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.570003876
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.700929328
Short name T82
Test name
Test status
Simulation time 902841290 ps
CPU time 17.42 seconds
Started Aug 04 05:28:11 PM PDT 24
Finished Aug 04 05:28:29 PM PDT 24
Peak memory 212336 kb
Host smart-5ebed56e-937f-4a9a-91eb-d99b899105fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700929328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.700929328
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2029701444
Short name T327
Test name
Test status
Simulation time 270575341 ps
CPU time 10.98 seconds
Started Aug 04 05:28:22 PM PDT 24
Finished Aug 04 05:28:33 PM PDT 24
Peak memory 217272 kb
Host smart-11a2a796-a9d6-42d0-96d5-db73513e5ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029701444 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2029701444
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1703640107
Short name T69
Test name
Test status
Simulation time 4936773370 ps
CPU time 9.7 seconds
Started Aug 04 05:28:24 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 211688 kb
Host smart-f22d5f49-a5f6-4821-bdad-d7d6df9906d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703640107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1703640107
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2367613439
Short name T375
Test name
Test status
Simulation time 174655230 ps
CPU time 8.11 seconds
Started Aug 04 05:28:19 PM PDT 24
Finished Aug 04 05:28:27 PM PDT 24
Peak memory 210808 kb
Host smart-03586cda-e457-41ae-be4c-f3bb2810e56e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367613439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2367613439
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.696155351
Short name T379
Test name
Test status
Simulation time 257444089 ps
CPU time 10.27 seconds
Started Aug 04 05:28:12 PM PDT 24
Finished Aug 04 05:28:22 PM PDT 24
Peak memory 210756 kb
Host smart-a2cd9537-6bb8-43bf-9dc7-1428b1c74899
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696155351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
696155351
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1646632022
Short name T90
Test name
Test status
Simulation time 692216275 ps
CPU time 8.42 seconds
Started Aug 04 05:28:12 PM PDT 24
Finished Aug 04 05:28:21 PM PDT 24
Peak memory 211616 kb
Host smart-7b12df67-cf18-4f9b-9d69-99f7bc1c15d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646632022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1646632022
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1419603139
Short name T378
Test name
Test status
Simulation time 167659258 ps
CPU time 11.77 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:14 PM PDT 24
Peak memory 216752 kb
Host smart-d0a1cfd2-7b8e-4aec-abda-a0d67d569d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419603139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1419603139
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1000712591
Short name T73
Test name
Test status
Simulation time 251760162 ps
CPU time 10.37 seconds
Started Aug 04 05:28:24 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 210836 kb
Host smart-3f93a508-bd43-4698-9830-250e109dcd20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000712591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1000712591
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2684912601
Short name T98
Test name
Test status
Simulation time 691214493 ps
CPU time 8.85 seconds
Started Aug 04 05:28:16 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 211160 kb
Host smart-866b955c-ea31-4e1e-98c8-c20786830055
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684912601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2684912601
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1856658461
Short name T338
Test name
Test status
Simulation time 700851166 ps
CPU time 11.66 seconds
Started Aug 04 05:28:30 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 210824 kb
Host smart-8f2f1cac-5e20-4adc-9669-95ea3a4f0233
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856658461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1856658461
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1116767972
Short name T58
Test name
Test status
Simulation time 2090563086 ps
CPU time 15.76 seconds
Started Aug 04 05:28:23 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 216788 kb
Host smart-f324e761-bde6-4524-9cb6-d9280f8b6b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116767972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1116767972
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2392329189
Short name T66
Test name
Test status
Simulation time 260449735 ps
CPU time 9.95 seconds
Started Aug 04 05:28:22 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 211016 kb
Host smart-31ea586c-cfa1-427b-a6d6-9358ad0112ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392329189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2392329189
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.652164234
Short name T348
Test name
Test status
Simulation time 914750646 ps
CPU time 9.66 seconds
Started Aug 04 05:28:16 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 210796 kb
Host smart-20d8ee38-aa36-4e26-ad6e-bcb9cd4c7c70
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652164234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.652164234
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1474136077
Short name T329
Test name
Test status
Simulation time 259305424 ps
CPU time 9.85 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 210748 kb
Host smart-36cca7d6-7aa3-4d52-8ca6-e762beaa4775
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474136077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1474136077
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1767667511
Short name T389
Test name
Test status
Simulation time 1041707414 ps
CPU time 13.57 seconds
Started Aug 04 05:28:19 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 212828 kb
Host smart-0781fe74-9855-4cff-b672-283d638d2ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767667511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1767667511
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1954033241
Short name T354
Test name
Test status
Simulation time 174808009 ps
CPU time 12.82 seconds
Started Aug 04 05:28:22 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 218900 kb
Host smart-95ae28ec-03de-46f7-a6c9-1df3b6565b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954033241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1954033241
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3822394140
Short name T376
Test name
Test status
Simulation time 3865214573 ps
CPU time 83.18 seconds
Started Aug 04 05:28:07 PM PDT 24
Finished Aug 04 05:29:30 PM PDT 24
Peak memory 213896 kb
Host smart-16914c27-4174-41ce-833b-d035b6ce993d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822394140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3822394140
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1506830746
Short name T382
Test name
Test status
Simulation time 19811258548 ps
CPU time 15.98 seconds
Started Aug 04 05:28:25 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 216872 kb
Host smart-f568dd4c-0c51-47ca-818f-7a61c8c2e17e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506830746 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1506830746
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.185997249
Short name T85
Test name
Test status
Simulation time 287412779 ps
CPU time 8.24 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 211180 kb
Host smart-374011da-c666-4d73-b25c-f28131d9feb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185997249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.185997249
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.560107293
Short name T71
Test name
Test status
Simulation time 661501556 ps
CPU time 8.39 seconds
Started Aug 04 05:28:25 PM PDT 24
Finished Aug 04 05:28:33 PM PDT 24
Peak memory 211848 kb
Host smart-906b4dfa-4c8d-427a-9a7b-d945edb47e7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560107293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.560107293
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3367389250
Short name T371
Test name
Test status
Simulation time 338966826 ps
CPU time 11.28 seconds
Started Aug 04 05:28:26 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 217376 kb
Host smart-bd5da9ad-7046-45ba-98c4-64de656c3e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367389250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3367389250
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1874825391
Short name T345
Test name
Test status
Simulation time 726804842 ps
CPU time 84.26 seconds
Started Aug 04 05:28:21 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 213964 kb
Host smart-a7ce874f-378f-44e7-8e30-b21fd3c4be6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874825391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1874825391
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1938607307
Short name T57
Test name
Test status
Simulation time 1021294903 ps
CPU time 10.57 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 217580 kb
Host smart-93482ea6-2b10-4398-8f1f-de921b967319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938607307 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1938607307
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.655091107
Short name T83
Test name
Test status
Simulation time 385089749 ps
CPU time 9.59 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 211460 kb
Host smart-9d742e9c-de7b-419c-a406-899f9b108017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655091107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.655091107
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1803993484
Short name T94
Test name
Test status
Simulation time 1031223336 ps
CPU time 10.27 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 211820 kb
Host smart-049c4c86-4c50-4e4f-aee9-6c21dd1f6ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803993484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1803993484
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1056654213
Short name T367
Test name
Test status
Simulation time 360919288 ps
CPU time 11.96 seconds
Started Aug 04 05:28:20 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 216608 kb
Host smart-64aacc68-b937-4f6e-9886-f4ea16a2417a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056654213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1056654213
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.726356289
Short name T352
Test name
Test status
Simulation time 467146860 ps
CPU time 81.91 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:29:36 PM PDT 24
Peak memory 213012 kb
Host smart-74273cd6-fbf5-475d-9946-b6097fc6285f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726356289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.726356289
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3607643458
Short name T359
Test name
Test status
Simulation time 560167712 ps
CPU time 8.59 seconds
Started Aug 04 05:28:20 PM PDT 24
Finished Aug 04 05:28:28 PM PDT 24
Peak memory 215780 kb
Host smart-7ad4ed21-f646-4f1d-9566-9bc54d4052a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607643458 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3607643458
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2562248459
Short name T99
Test name
Test status
Simulation time 169777301 ps
CPU time 8.17 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 210936 kb
Host smart-76279d00-95ce-4631-8ef1-f9fa54d00f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562248459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2562248459
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1961884162
Short name T372
Test name
Test status
Simulation time 175043069 ps
CPU time 8.1 seconds
Started Aug 04 05:28:26 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 211336 kb
Host smart-62631684-7ca0-4e88-ac2d-6677bf0c2603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961884162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1961884162
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1365878044
Short name T339
Test name
Test status
Simulation time 169431961 ps
CPU time 11.42 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:27 PM PDT 24
Peak memory 217392 kb
Host smart-1578d38f-5aac-499c-bf0b-3fadf2ac56b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365878044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1365878044
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.826182889
Short name T111
Test name
Test status
Simulation time 589489851 ps
CPU time 154 seconds
Started Aug 04 05:28:18 PM PDT 24
Finished Aug 04 05:30:52 PM PDT 24
Peak memory 214304 kb
Host smart-42cad664-d751-44b7-95a4-16c165fe6ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826182889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.826182889
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4179738935
Short name T59
Test name
Test status
Simulation time 181352904 ps
CPU time 8.93 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:28:36 PM PDT 24
Peak memory 216960 kb
Host smart-d71c9e89-9059-417c-9c7e-56f68662760b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179738935 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4179738935
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1464802610
Short name T81
Test name
Test status
Simulation time 425539183 ps
CPU time 8.16 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 211124 kb
Host smart-32523153-1e00-466d-ab88-de534aca7260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464802610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1464802610
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4267169935
Short name T362
Test name
Test status
Simulation time 177133631 ps
CPU time 12.07 seconds
Started Aug 04 05:28:13 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 212536 kb
Host smart-384fc217-0fb0-4401-af6b-eba7de239b12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267169935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4267169935
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2913688718
Short name T346
Test name
Test status
Simulation time 1018609050 ps
CPU time 17.65 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 218580 kb
Host smart-90716b5d-8e59-4ccd-a803-54602ed2e342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913688718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2913688718
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2614371322
Short name T110
Test name
Test status
Simulation time 1251255823 ps
CPU time 81.44 seconds
Started Aug 04 05:28:30 PM PDT 24
Finished Aug 04 05:29:52 PM PDT 24
Peak memory 213764 kb
Host smart-d5f049e3-f8c4-4763-9b6c-fd3168213742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614371322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2614371322
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1477015835
Short name T397
Test name
Test status
Simulation time 267640130 ps
CPU time 10.23 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 214088 kb
Host smart-9f40cf69-75ba-40df-b826-dcdceaa12fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477015835 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1477015835
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2597005405
Short name T96
Test name
Test status
Simulation time 338317799 ps
CPU time 8.43 seconds
Started Aug 04 05:28:17 PM PDT 24
Finished Aug 04 05:28:25 PM PDT 24
Peak memory 210908 kb
Host smart-5187964b-7496-441a-bd6d-0d05847c6109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597005405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2597005405
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3127281476
Short name T356
Test name
Test status
Simulation time 469882410 ps
CPU time 10.07 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 211708 kb
Host smart-7e76113f-c7e3-4501-b657-75d7f06a5ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127281476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3127281476
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3123110100
Short name T380
Test name
Test status
Simulation time 988998217 ps
CPU time 13.62 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 219092 kb
Host smart-95e2deaa-f289-4dd9-ae3e-1570d9e12f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123110100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3123110100
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3699300488
Short name T106
Test name
Test status
Simulation time 1900572731 ps
CPU time 157.93 seconds
Started Aug 04 05:28:27 PM PDT 24
Finished Aug 04 05:31:05 PM PDT 24
Peak memory 214544 kb
Host smart-f7632702-0027-4fae-abe5-a2c45b68315e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699300488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3699300488
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3803867738
Short name T265
Test name
Test status
Simulation time 211591959 ps
CPU time 8.38 seconds
Started Aug 04 05:31:29 PM PDT 24
Finished Aug 04 05:31:38 PM PDT 24
Peak memory 219036 kb
Host smart-d6b4a8b3-4b18-41ee-8ccd-d93c6e9c3e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803867738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3803867738
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3473492631
Short name T308
Test name
Test status
Simulation time 4490400209 ps
CPU time 266.99 seconds
Started Aug 04 05:31:50 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 238532 kb
Host smart-d9c80a7b-76cc-4412-860a-8cd5976409c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473492631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3473492631
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3129007234
Short name T221
Test name
Test status
Simulation time 176698759 ps
CPU time 10.68 seconds
Started Aug 04 05:31:29 PM PDT 24
Finished Aug 04 05:31:40 PM PDT 24
Peak memory 220120 kb
Host smart-9850c07f-6c6f-4659-a1b4-a60b443ec692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129007234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3129007234
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1936555594
Short name T28
Test name
Test status
Simulation time 341056028 ps
CPU time 225.15 seconds
Started Aug 04 05:31:39 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 239772 kb
Host smart-208321a9-2679-4c4d-8aea-d74226c459c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936555594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1936555594
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3490912818
Short name T188
Test name
Test status
Simulation time 729813915 ps
CPU time 10.5 seconds
Started Aug 04 05:31:41 PM PDT 24
Finished Aug 04 05:31:51 PM PDT 24
Peak memory 219952 kb
Host smart-56399a13-a008-40cc-a735-663cf6d0d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490912818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3490912818
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.91680062
Short name T318
Test name
Test status
Simulation time 521507664 ps
CPU time 23.69 seconds
Started Aug 04 05:31:26 PM PDT 24
Finished Aug 04 05:31:49 PM PDT 24
Peak memory 220024 kb
Host smart-f9229a29-e912-4980-aa6f-de057f14d05a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91680062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_ctrl_stress_all.91680062
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2835526078
Short name T140
Test name
Test status
Simulation time 174557486 ps
CPU time 8.59 seconds
Started Aug 04 05:31:31 PM PDT 24
Finished Aug 04 05:31:39 PM PDT 24
Peak memory 219124 kb
Host smart-9da8c2dd-f6d2-4ac0-ab17-c8a6272d937a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835526078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2835526078
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4160915702
Short name T114
Test name
Test status
Simulation time 29966843764 ps
CPU time 295.77 seconds
Started Aug 04 05:31:38 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 234500 kb
Host smart-ae89f131-54c5-4ccc-a911-d22cd98ff3a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160915702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4160915702
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3000705052
Short name T252
Test name
Test status
Simulation time 2600692526 ps
CPU time 23.23 seconds
Started Aug 04 05:31:41 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 220144 kb
Host smart-2919bf72-ab54-473f-9927-c4abd66b369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000705052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3000705052
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.142830820
Short name T283
Test name
Test status
Simulation time 1063954652 ps
CPU time 11.99 seconds
Started Aug 04 05:31:35 PM PDT 24
Finished Aug 04 05:31:47 PM PDT 24
Peak memory 220060 kb
Host smart-7460ccc0-79b9-44d8-946e-29ee585519fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142830820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.142830820
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.289604729
Short name T24
Test name
Test status
Simulation time 1323166145 ps
CPU time 228.32 seconds
Started Aug 04 05:31:32 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 235688 kb
Host smart-745693a6-80be-4415-9f1c-347517152095
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289604729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.289604729
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1144558422
Short name T264
Test name
Test status
Simulation time 263563727 ps
CPU time 12.1 seconds
Started Aug 04 05:31:45 PM PDT 24
Finished Aug 04 05:31:58 PM PDT 24
Peak memory 220004 kb
Host smart-f1b83cd5-b146-4550-b576-5134dbea3e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144558422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1144558422
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1151418616
Short name T292
Test name
Test status
Simulation time 1045830686 ps
CPU time 27.56 seconds
Started Aug 04 05:31:42 PM PDT 24
Finished Aug 04 05:32:10 PM PDT 24
Peak memory 220008 kb
Host smart-27b47ce6-2c5a-44ff-8171-405a7b2e9092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151418616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1151418616
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1020430528
Short name T296
Test name
Test status
Simulation time 662234855 ps
CPU time 8.49 seconds
Started Aug 04 05:31:41 PM PDT 24
Finished Aug 04 05:31:50 PM PDT 24
Peak memory 219000 kb
Host smart-d444c4b8-a4af-4a11-8c2b-fc792350aaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020430528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1020430528
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1946785404
Short name T198
Test name
Test status
Simulation time 37896762673 ps
CPU time 191.39 seconds
Started Aug 04 05:31:51 PM PDT 24
Finished Aug 04 05:35:02 PM PDT 24
Peak memory 220380 kb
Host smart-032b86de-a57e-403b-8845-5721afdbe8fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946785404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1946785404
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1711661565
Short name T241
Test name
Test status
Simulation time 340192760 ps
CPU time 18.69 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 219960 kb
Host smart-d29ec3f2-5734-41e1-bdb5-a827d623357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711661565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1711661565
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2864906070
Short name T223
Test name
Test status
Simulation time 2117590312 ps
CPU time 11.91 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 219956 kb
Host smart-1f7270da-ddd2-40ec-957d-a57b721f3018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864906070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2864906070
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3084270461
Short name T75
Test name
Test status
Simulation time 1068651521 ps
CPU time 30.58 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 219908 kb
Host smart-1ea7c7f4-2944-46db-b41e-df1d41d70cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084270461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3084270461
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3484989502
Short name T165
Test name
Test status
Simulation time 167708015 ps
CPU time 8.27 seconds
Started Aug 04 05:31:50 PM PDT 24
Finished Aug 04 05:31:58 PM PDT 24
Peak memory 219212 kb
Host smart-ec51ddde-b95a-4304-a6c4-5e0df148c526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484989502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3484989502
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3675123570
Short name T293
Test name
Test status
Simulation time 842577700 ps
CPU time 22.5 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 220048 kb
Host smart-1138b14a-dce3-43f1-a751-ad9d49703885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675123570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3675123570
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.749279581
Short name T215
Test name
Test status
Simulation time 1432613743 ps
CPU time 23.73 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:32:07 PM PDT 24
Peak memory 219960 kb
Host smart-01299f14-3a14-464d-ac6b-b01b900c2596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749279581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.749279581
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.888034441
Short name T134
Test name
Test status
Simulation time 175046753 ps
CPU time 8.34 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:11 PM PDT 24
Peak memory 219076 kb
Host smart-2a4ebcb0-326d-4692-9a4a-91821a7e901b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888034441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.888034441
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4207996483
Short name T300
Test name
Test status
Simulation time 8216750270 ps
CPU time 285.14 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:36:40 PM PDT 24
Peak memory 240484 kb
Host smart-23d7bbc1-c060-41f9-b00a-85b23f62dc2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207996483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4207996483
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4160211310
Short name T259
Test name
Test status
Simulation time 1319553066 ps
CPU time 19.51 seconds
Started Aug 04 05:31:57 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 220112 kb
Host smart-bbe042ab-8f79-4cbf-b6e3-dd15d64007ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160211310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4160211310
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3710405368
Short name T263
Test name
Test status
Simulation time 528964738 ps
CPU time 12.16 seconds
Started Aug 04 05:31:53 PM PDT 24
Finished Aug 04 05:32:05 PM PDT 24
Peak memory 220100 kb
Host smart-3900ef1a-2e82-477d-804d-af6c6b9a8469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710405368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3710405368
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2820816238
Short name T246
Test name
Test status
Simulation time 580565513 ps
CPU time 30.78 seconds
Started Aug 04 05:31:51 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220056 kb
Host smart-83876dae-72c9-4081-b0dd-231768548f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820816238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2820816238
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3828486422
Short name T155
Test name
Test status
Simulation time 515839055 ps
CPU time 9.98 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:09 PM PDT 24
Peak memory 219056 kb
Host smart-2b0833b7-842d-4254-be1e-6b9b8f8b256c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828486422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3828486422
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2954106692
Short name T222
Test name
Test status
Simulation time 8851869493 ps
CPU time 220.78 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 244056 kb
Host smart-0d65207e-a04b-423e-b19d-4e0a075bb0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954106692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2954106692
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1812515864
Short name T17
Test name
Test status
Simulation time 518745018 ps
CPU time 11.48 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:11 PM PDT 24
Peak memory 219980 kb
Host smart-30522e84-cdd9-4db3-b37d-6232713c408e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812515864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1812515864
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2718716153
Short name T200
Test name
Test status
Simulation time 190211841 ps
CPU time 13.98 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:13 PM PDT 24
Peak memory 219544 kb
Host smart-b956752a-175f-4fda-8bcd-700f4bb8735d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718716153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2718716153
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2434719566
Short name T61
Test name
Test status
Simulation time 248386371 ps
CPU time 10.12 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:31:53 PM PDT 24
Peak memory 219124 kb
Host smart-900abea6-284e-44cd-bc50-4ac25a3c646c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434719566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2434719566
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.514555708
Short name T266
Test name
Test status
Simulation time 26063733516 ps
CPU time 338.99 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:37:22 PM PDT 24
Peak memory 220360 kb
Host smart-ec0ae617-45a6-478d-831c-e7429669af61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514555708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.514555708
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.969907777
Short name T312
Test name
Test status
Simulation time 333753367 ps
CPU time 18.88 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219956 kb
Host smart-a53eb057-59ec-4974-a011-5d062350e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969907777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.969907777
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4172808328
Short name T277
Test name
Test status
Simulation time 3973151683 ps
CPU time 16.95 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220076 kb
Host smart-d0169df3-57e2-4072-ad11-287dbac55c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172808328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4172808328
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1312093358
Short name T238
Test name
Test status
Simulation time 536281929 ps
CPU time 27.32 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219920 kb
Host smart-0949527b-e849-46de-abc7-3411e77e79d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312093358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1312093358
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2701543125
Short name T33
Test name
Test status
Simulation time 990726472 ps
CPU time 10.35 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:32:09 PM PDT 24
Peak memory 219164 kb
Host smart-713d899b-3ee4-4deb-94dc-dfd1c52ef72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701543125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2701543125
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.527276320
Short name T261
Test name
Test status
Simulation time 8842367514 ps
CPU time 277.99 seconds
Started Aug 04 05:32:01 PM PDT 24
Finished Aug 04 05:36:39 PM PDT 24
Peak memory 234616 kb
Host smart-5d8ad395-212b-4441-bbaf-b4c76188c3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527276320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.527276320
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3480916872
Short name T208
Test name
Test status
Simulation time 4100218650 ps
CPU time 31.93 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:37 PM PDT 24
Peak memory 220088 kb
Host smart-c46ca1b7-62d2-49b7-9b37-5a5399f947fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480916872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3480916872
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.52988520
Short name T244
Test name
Test status
Simulation time 1065925909 ps
CPU time 12.02 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:08 PM PDT 24
Peak memory 220120 kb
Host smart-98f215a6-2341-48a8-bfdd-91dca5c04093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52988520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.52988520
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3433598638
Short name T18
Test name
Test status
Simulation time 214783680 ps
CPU time 18.79 seconds
Started Aug 04 05:31:42 PM PDT 24
Finished Aug 04 05:32:01 PM PDT 24
Peak memory 220040 kb
Host smart-6ab34c30-f791-451f-94c6-ec109ae738d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433598638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3433598638
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4269301486
Short name T256
Test name
Test status
Simulation time 338963670 ps
CPU time 8.09 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:02 PM PDT 24
Peak memory 219036 kb
Host smart-ea1f2467-1b79-441b-b759-eda586ad5113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269301486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4269301486
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3809622544
Short name T20
Test name
Test status
Simulation time 3530017383 ps
CPU time 177.47 seconds
Started Aug 04 05:31:53 PM PDT 24
Finished Aug 04 05:34:51 PM PDT 24
Peak memory 239008 kb
Host smart-2d4efc60-9fd5-471d-b519-907f2440a43a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809622544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3809622544
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2587211130
Short name T138
Test name
Test status
Simulation time 1414200730 ps
CPU time 22.22 seconds
Started Aug 04 05:31:57 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 220064 kb
Host smart-5446e4ec-0df1-4866-8c42-24a33f055d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587211130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2587211130
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.737352792
Short name T116
Test name
Test status
Simulation time 14220282887 ps
CPU time 17.21 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 220084 kb
Host smart-dccabff2-48d4-4927-b834-7d8af938c9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737352792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.737352792
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.182224867
Short name T213
Test name
Test status
Simulation time 1131851337 ps
CPU time 37.37 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:32 PM PDT 24
Peak memory 220036 kb
Host smart-530cf506-0ee1-408d-9529-bf2867c2d443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182224867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.182224867
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.436605033
Short name T220
Test name
Test status
Simulation time 661201509 ps
CPU time 8.22 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 219260 kb
Host smart-0d07a830-5e7b-4ed8-a4fa-7d9a95cd0550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436605033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.436605033
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2137230680
Short name T239
Test name
Test status
Simulation time 15242080633 ps
CPU time 216.8 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 240312 kb
Host smart-0ced71bb-01f9-48cf-b465-c83679b024bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137230680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2137230680
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2501705574
Short name T26
Test name
Test status
Simulation time 2062334796 ps
CPU time 22.29 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 220104 kb
Host smart-2a4a605d-e5cb-4dcb-ad78-df5f7e87fac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501705574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2501705574
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3604223787
Short name T36
Test name
Test status
Simulation time 183477315 ps
CPU time 10.38 seconds
Started Aug 04 05:31:50 PM PDT 24
Finished Aug 04 05:32:00 PM PDT 24
Peak memory 220024 kb
Host smart-d9a2f1e5-1967-4baf-ab89-20dae4ccba9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604223787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3604223787
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2088835029
Short name T79
Test name
Test status
Simulation time 413779193 ps
CPU time 15.04 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:14 PM PDT 24
Peak memory 219976 kb
Host smart-de87c572-1e19-4523-8d0e-6ed3245d847b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088835029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2088835029
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3709514715
Short name T62
Test name
Test status
Simulation time 1376597827 ps
CPU time 9.94 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 219176 kb
Host smart-c93be7a0-24d0-4691-9a43-43a038149e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709514715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3709514715
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2895122859
Short name T42
Test name
Test status
Simulation time 3123355657 ps
CPU time 168.55 seconds
Started Aug 04 05:31:46 PM PDT 24
Finished Aug 04 05:34:35 PM PDT 24
Peak memory 225740 kb
Host smart-943981ec-0a13-4906-a14a-d02027df5e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895122859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2895122859
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2997788848
Short name T202
Test name
Test status
Simulation time 663147428 ps
CPU time 19.54 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 220124 kb
Host smart-ae1945d7-7406-4603-9bf9-4f121f2cce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997788848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2997788848
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4039506151
Short name T117
Test name
Test status
Simulation time 1022926175 ps
CPU time 16.55 seconds
Started Aug 04 05:31:48 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 219992 kb
Host smart-ca589b48-5f8d-4b41-9434-8b0872aaf72b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039506151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4039506151
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1525937612
Short name T3
Test name
Test status
Simulation time 522488891 ps
CPU time 27.41 seconds
Started Aug 04 05:31:50 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 220032 kb
Host smart-55f295aa-cf2b-460b-a0d3-4ec0481c43f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525937612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1525937612
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4027450257
Short name T288
Test name
Test status
Simulation time 174244679 ps
CPU time 8.15 seconds
Started Aug 04 05:31:51 PM PDT 24
Finished Aug 04 05:31:59 PM PDT 24
Peak memory 218952 kb
Host smart-412d0fbc-5ba4-442b-8016-2b9ecae80937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027450257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4027450257
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1175270602
Short name T258
Test name
Test status
Simulation time 32189737924 ps
CPU time 192.14 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:35:04 PM PDT 24
Peak memory 243588 kb
Host smart-88dcbea0-26a1-4138-8fca-079542f2b400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175270602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1175270602
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1681971435
Short name T269
Test name
Test status
Simulation time 4962999551 ps
CPU time 22.42 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 220140 kb
Host smart-bf454e72-8189-4bfd-aa73-d1d58f4acd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681971435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1681971435
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.405044462
Short name T159
Test name
Test status
Simulation time 263024096 ps
CPU time 12.12 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220096 kb
Host smart-42212937-6276-4db1-97e3-2d3b1360db1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405044462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.405044462
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1027550134
Short name T231
Test name
Test status
Simulation time 219025749 ps
CPU time 18.26 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:14 PM PDT 24
Peak memory 220004 kb
Host smart-af314b85-b0de-4147-94e6-2009ff3991bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027550134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1027550134
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3237621688
Short name T149
Test name
Test status
Simulation time 332305470 ps
CPU time 8.35 seconds
Started Aug 04 05:31:35 PM PDT 24
Finished Aug 04 05:31:44 PM PDT 24
Peak memory 219168 kb
Host smart-acc7fd07-4114-43e8-a7d7-792b5f93800e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237621688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3237621688
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1438103260
Short name T285
Test name
Test status
Simulation time 5589845781 ps
CPU time 308.89 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:36:52 PM PDT 24
Peak memory 228868 kb
Host smart-91a7acf6-aeb2-4024-b969-fb47a760f310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438103260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1438103260
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3344280533
Short name T310
Test name
Test status
Simulation time 1766187757 ps
CPU time 22.93 seconds
Started Aug 04 05:31:33 PM PDT 24
Finished Aug 04 05:31:56 PM PDT 24
Peak memory 220004 kb
Host smart-5ba2a1c5-b3e1-4aec-ae19-c214052519b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344280533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3344280533
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1772605839
Short name T185
Test name
Test status
Simulation time 312561062 ps
CPU time 12.34 seconds
Started Aug 04 05:31:34 PM PDT 24
Finished Aug 04 05:31:47 PM PDT 24
Peak memory 220000 kb
Host smart-2d414c64-c439-46a9-8379-c8da91ccfc91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772605839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1772605839
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2864995642
Short name T10
Test name
Test status
Simulation time 873180603 ps
CPU time 10.23 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:43 PM PDT 24
Peak memory 220080 kb
Host smart-557f517d-2228-4687-b861-4e30df621a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864995642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2864995642
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.749867070
Short name T126
Test name
Test status
Simulation time 811740536 ps
CPU time 37.58 seconds
Started Aug 04 05:31:35 PM PDT 24
Finished Aug 04 05:32:13 PM PDT 24
Peak memory 220036 kb
Host smart-8225c465-43ac-406f-ba78-06f1fbe51e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749867070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.749867070
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3837899546
Short name T148
Test name
Test status
Simulation time 1239227887 ps
CPU time 10.07 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 219156 kb
Host smart-b6746fa9-7073-4da9-8770-e6fe74ebad97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837899546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3837899546
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3831286493
Short name T227
Test name
Test status
Simulation time 9751144477 ps
CPU time 190.51 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:35:09 PM PDT 24
Peak memory 241752 kb
Host smart-6b5d72cc-771a-486f-af66-7dea80afd49d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831286493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3831286493
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1850068352
Short name T233
Test name
Test status
Simulation time 518489720 ps
CPU time 22.75 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:26 PM PDT 24
Peak memory 220092 kb
Host smart-470e437b-33ee-4cb5-8568-422077caeaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850068352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1850068352
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1739151845
Short name T38
Test name
Test status
Simulation time 359807955 ps
CPU time 12.32 seconds
Started Aug 04 05:31:49 PM PDT 24
Finished Aug 04 05:32:01 PM PDT 24
Peak memory 220048 kb
Host smart-21a1168f-8b71-4ff4-84c8-98910c66ee6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739151845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1739151845
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3736105053
Short name T254
Test name
Test status
Simulation time 1196318456 ps
CPU time 23.44 seconds
Started Aug 04 05:32:01 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 219980 kb
Host smart-c0568c06-754d-4fb0-b62c-a33db32db787
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736105053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3736105053
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.410238037
Short name T50
Test name
Test status
Simulation time 23129423831 ps
CPU time 893.02 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:46:55 PM PDT 24
Peak memory 232116 kb
Host smart-9d0e20db-1a79-434f-8d27-9c0dd1dd19a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410238037 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.410238037
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2197114939
Short name T272
Test name
Test status
Simulation time 169870351 ps
CPU time 8.33 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:32:00 PM PDT 24
Peak memory 219088 kb
Host smart-3f0acb53-cce4-4209-8345-0b6a9d61d2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197114939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2197114939
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2566869612
Short name T212
Test name
Test status
Simulation time 5669976173 ps
CPU time 296.16 seconds
Started Aug 04 05:31:56 PM PDT 24
Finished Aug 04 05:36:52 PM PDT 24
Peak memory 226880 kb
Host smart-81f513f1-7538-46bd-962e-fa883d71c6b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566869612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2566869612
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1487301745
Short name T298
Test name
Test status
Simulation time 511178052 ps
CPU time 22.66 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 220108 kb
Host smart-224675f3-48b1-4e9d-90a8-b48ef491e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487301745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1487301745
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3305941500
Short name T236
Test name
Test status
Simulation time 5078401451 ps
CPU time 12.13 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220216 kb
Host smart-a4a27540-284a-400d-800c-2045aad29669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305941500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3305941500
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.389120024
Short name T214
Test name
Test status
Simulation time 2117134934 ps
CPU time 24.7 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:27 PM PDT 24
Peak memory 220024 kb
Host smart-676fedec-5a4f-4b71-befe-1e098f8aafa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389120024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.389120024
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1135959037
Short name T13
Test name
Test status
Simulation time 78535012002 ps
CPU time 1472.74 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:56:33 PM PDT 24
Peak memory 239340 kb
Host smart-8d5e9952-f0c8-46b9-a762-c24b4987ee3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135959037 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1135959037
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1818772050
Short name T162
Test name
Test status
Simulation time 176215204 ps
CPU time 8.52 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 219332 kb
Host smart-f7b68de5-79fb-4d74-b773-24ce42d768a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818772050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1818772050
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3304421943
Short name T172
Test name
Test status
Simulation time 4574132374 ps
CPU time 185.46 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:35:03 PM PDT 24
Peak memory 241228 kb
Host smart-e21cf66b-bfca-4837-9f9e-cc7cb1648ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304421943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3304421943
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4266551624
Short name T173
Test name
Test status
Simulation time 502992521 ps
CPU time 19.41 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 220096 kb
Host smart-f0c48d06-93b0-4bf4-8bbe-f5b7159c3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266551624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4266551624
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1203294737
Short name T100
Test name
Test status
Simulation time 183692409 ps
CPU time 10.36 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:05 PM PDT 24
Peak memory 219980 kb
Host smart-de2a45e2-5fac-419c-a998-374f73ae1f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203294737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1203294737
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.492282936
Short name T313
Test name
Test status
Simulation time 438343761 ps
CPU time 11.7 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 219944 kb
Host smart-a0e8aa8a-dc8b-4aa0-a91d-b6869231efab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492282936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.492282936
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2286016523
Short name T197
Test name
Test status
Simulation time 1030921010 ps
CPU time 10.11 seconds
Started Aug 04 05:31:56 PM PDT 24
Finished Aug 04 05:32:06 PM PDT 24
Peak memory 219044 kb
Host smart-a7375978-3cc9-401c-965e-e0a3cfee5392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286016523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2286016523
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2229101678
Short name T41
Test name
Test status
Simulation time 4085964954 ps
CPU time 213.04 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 234580 kb
Host smart-0fe88d1c-6b9a-45d7-a545-56ce9f4043f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229101678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2229101678
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.95801221
Short name T186
Test name
Test status
Simulation time 1320923855 ps
CPU time 19.34 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:26 PM PDT 24
Peak memory 220116 kb
Host smart-17647dda-a4af-4b66-bee5-5fe54b196e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95801221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.95801221
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4044278887
Short name T184
Test name
Test status
Simulation time 273773348 ps
CPU time 12.36 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 220024 kb
Host smart-bd41c64e-0ed7-42ec-af0b-9f7c783b3e90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044278887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4044278887
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.412953503
Short name T242
Test name
Test status
Simulation time 1288884223 ps
CPU time 26.78 seconds
Started Aug 04 05:31:56 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 219964 kb
Host smart-5d8fb9e3-faf1-484d-b05e-24d93633e7c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412953503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.412953503
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3190672602
Short name T153
Test name
Test status
Simulation time 660336814 ps
CPU time 8.38 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 219080 kb
Host smart-e2fd74ae-cae7-4bd5-9995-30e3644d98fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190672602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3190672602
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2968551142
Short name T245
Test name
Test status
Simulation time 3790085505 ps
CPU time 204.16 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 230344 kb
Host smart-b1adfc5e-405b-4db2-b739-9a50da5b4df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968551142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2968551142
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.567148840
Short name T171
Test name
Test status
Simulation time 2058600063 ps
CPU time 22.53 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 220080 kb
Host smart-1e440968-f3a6-4b90-9647-e64b708c3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567148840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.567148840
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.792406365
Short name T305
Test name
Test status
Simulation time 271491382 ps
CPU time 12.12 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 220044 kb
Host smart-3e45e095-6775-405e-8400-e1cec6eaa573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792406365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.792406365
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3375863524
Short name T228
Test name
Test status
Simulation time 1057941657 ps
CPU time 28.97 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:38 PM PDT 24
Peak memory 220040 kb
Host smart-d3dbd101-9e25-45ac-b26e-49ee314b4b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375863524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3375863524
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2598956025
Short name T49
Test name
Test status
Simulation time 20608681749 ps
CPU time 6966.11 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 07:28:16 PM PDT 24
Peak memory 236652 kb
Host smart-49806633-a447-4158-80fc-6ec6482e6c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598956025 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2598956025
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1096413910
Short name T137
Test name
Test status
Simulation time 496575552 ps
CPU time 10.03 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 219008 kb
Host smart-b06ab2b7-7545-4fb0-838d-aafce324e679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096413910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1096413910
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1426679141
Short name T167
Test name
Test status
Simulation time 4258233042 ps
CPU time 327.14 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:37:20 PM PDT 24
Peak memory 226932 kb
Host smart-6015a685-d822-415c-983c-c90d94747bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426679141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1426679141
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.584465718
Short name T46
Test name
Test status
Simulation time 1378658889 ps
CPU time 19.14 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220068 kb
Host smart-0ea3345b-af38-4620-b3b0-8b53a2ac98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584465718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.584465718
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1735952579
Short name T226
Test name
Test status
Simulation time 273808386 ps
CPU time 12.45 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 220004 kb
Host smart-4364cf68-a520-45ac-ae49-8e1ddb01ffe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735952579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1735952579
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1379047645
Short name T209
Test name
Test status
Simulation time 1952689725 ps
CPU time 31.17 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:38 PM PDT 24
Peak memory 219976 kb
Host smart-5f2329e0-6149-4efc-a1e6-91f22da4527e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379047645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1379047645
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4018923368
Short name T321
Test name
Test status
Simulation time 169526355 ps
CPU time 8.31 seconds
Started Aug 04 05:32:01 PM PDT 24
Finished Aug 04 05:32:09 PM PDT 24
Peak memory 219124 kb
Host smart-50eba35d-a12d-47c8-bca3-75c6b63f905a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018923368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4018923368
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2852245054
Short name T169
Test name
Test status
Simulation time 8255660372 ps
CPU time 316.79 seconds
Started Aug 04 05:31:58 PM PDT 24
Finished Aug 04 05:37:15 PM PDT 24
Peak memory 240212 kb
Host smart-5658865d-7c43-4e67-86c1-fc22b1c13bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852245054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2852245054
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2398114656
Short name T132
Test name
Test status
Simulation time 535267039 ps
CPU time 22.44 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:33 PM PDT 24
Peak memory 220068 kb
Host smart-41f269c3-3def-46b8-8014-692b017d9c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398114656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2398114656
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3369306988
Short name T177
Test name
Test status
Simulation time 184704678 ps
CPU time 10.55 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220088 kb
Host smart-cefa721d-5639-40e5-8a8d-d55b0e4ea7c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369306988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3369306988
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2434949232
Short name T118
Test name
Test status
Simulation time 813141298 ps
CPU time 38.82 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:32:43 PM PDT 24
Peak memory 220072 kb
Host smart-6daec1f8-0a4d-4ca6-ba1f-512e335c26c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434949232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2434949232
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3582689910
Short name T271
Test name
Test status
Simulation time 1497013390 ps
CPU time 8.2 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:14 PM PDT 24
Peak memory 219032 kb
Host smart-d7f44086-be42-4e99-91ae-935556bb6d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582689910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3582689910
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3944229802
Short name T216
Test name
Test status
Simulation time 82767042884 ps
CPU time 422.74 seconds
Started Aug 04 05:32:13 PM PDT 24
Finished Aug 04 05:39:16 PM PDT 24
Peak memory 219704 kb
Host smart-ea726fa3-8cdd-4a69-84c7-16723803a17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944229802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3944229802
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.59080549
Short name T144
Test name
Test status
Simulation time 2248414122 ps
CPU time 22.97 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220248 kb
Host smart-91697413-e4e1-4efe-9b91-da5dfcd2853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59080549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.59080549
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1062125534
Short name T297
Test name
Test status
Simulation time 4144886450 ps
CPU time 17.16 seconds
Started Aug 04 05:32:01 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 220208 kb
Host smart-081d3c6f-e915-47a9-97a0-a742d5b2a8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062125534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1062125534
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2415149838
Short name T101
Test name
Test status
Simulation time 371612717 ps
CPU time 14.32 seconds
Started Aug 04 05:31:57 PM PDT 24
Finished Aug 04 05:32:11 PM PDT 24
Peak memory 220076 kb
Host smart-bc02964d-9b37-4ddd-9cd4-badeacf6c77f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415149838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2415149838
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.602379750
Short name T182
Test name
Test status
Simulation time 256667396 ps
CPU time 9.84 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:13 PM PDT 24
Peak memory 219060 kb
Host smart-753f3fcb-84ea-4030-9b04-c701cca493d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602379750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.602379750
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2340958441
Short name T229
Test name
Test status
Simulation time 7263020853 ps
CPU time 284.2 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:36:54 PM PDT 24
Peak memory 235584 kb
Host smart-87fe971f-4262-4744-aa7a-e6b84004d0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340958441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2340958441
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3198888252
Short name T128
Test name
Test status
Simulation time 518607606 ps
CPU time 22.7 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:31 PM PDT 24
Peak memory 220060 kb
Host smart-187bb583-66c5-42d8-807b-1beac7fc3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198888252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3198888252
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2111399540
Short name T309
Test name
Test status
Simulation time 185023368 ps
CPU time 10.04 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 220072 kb
Host smart-181a3b52-f75b-45d0-a090-1157d9aaee20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111399540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2111399540
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.57500989
Short name T287
Test name
Test status
Simulation time 2090217911 ps
CPU time 25.11 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:32 PM PDT 24
Peak memory 219920 kb
Host smart-c370ecc4-d6ae-4352-bca6-34359efe2e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57500989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.rom_ctrl_stress_all.57500989
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3876016757
Short name T51
Test name
Test status
Simulation time 102764233254 ps
CPU time 10726.6 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 08:30:57 PM PDT 24
Peak memory 240792 kb
Host smart-35b52444-ca01-45cf-b486-7c57cf36832f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876016757 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3876016757
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3285375561
Short name T210
Test name
Test status
Simulation time 2047748778 ps
CPU time 9.98 seconds
Started Aug 04 05:32:12 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 219080 kb
Host smart-e6d163de-7a68-4b4c-b138-36fdb0c21e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285375561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3285375561
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4163981294
Short name T234
Test name
Test status
Simulation time 11564522646 ps
CPU time 157.63 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:34:47 PM PDT 24
Peak memory 219004 kb
Host smart-a0bd49b6-fcfd-4cfa-b2a0-290e738757dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163981294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4163981294
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4026017448
Short name T158
Test name
Test status
Simulation time 692011964 ps
CPU time 19.22 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 220112 kb
Host smart-4483b96d-07a7-48c6-98e6-f91a20dd80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026017448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4026017448
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.434120129
Short name T121
Test name
Test status
Simulation time 341398425 ps
CPU time 10.25 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 220004 kb
Host smart-6f11fafd-3145-4890-bb1d-b267725287bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434120129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.434120129
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.622095991
Short name T122
Test name
Test status
Simulation time 389609203 ps
CPU time 20.2 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 219952 kb
Host smart-7625df39-cde1-47d1-893e-fc4b5709e651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622095991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.622095991
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.637829622
Short name T303
Test name
Test status
Simulation time 1045566714 ps
CPU time 15.38 seconds
Started Aug 04 05:31:48 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 219104 kb
Host smart-1209b918-78f3-420e-829d-eca3fc449b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637829622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.637829622
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3242475572
Short name T37
Test name
Test status
Simulation time 4706423815 ps
CPU time 336.11 seconds
Started Aug 04 05:31:53 PM PDT 24
Finished Aug 04 05:37:29 PM PDT 24
Peak memory 234604 kb
Host smart-fb909bad-d2be-46fa-9977-f51340c0985c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242475572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3242475572
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1805217175
Short name T183
Test name
Test status
Simulation time 1376032741 ps
CPU time 19.26 seconds
Started Aug 04 05:31:47 PM PDT 24
Finished Aug 04 05:32:06 PM PDT 24
Peak memory 220084 kb
Host smart-f95fce40-1088-4ef0-8a92-9b5407159c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805217175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1805217175
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2107184043
Short name T267
Test name
Test status
Simulation time 369795711 ps
CPU time 10.77 seconds
Started Aug 04 05:31:36 PM PDT 24
Finished Aug 04 05:31:47 PM PDT 24
Peak memory 220080 kb
Host smart-8b5b054c-55d3-4bde-91b2-e17a87a10094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107184043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2107184043
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1371365468
Short name T29
Test name
Test status
Simulation time 597883166 ps
CPU time 119.23 seconds
Started Aug 04 05:31:30 PM PDT 24
Finished Aug 04 05:33:29 PM PDT 24
Peak memory 233972 kb
Host smart-0454744f-9d2f-49c8-b785-0f5f52e609cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371365468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1371365468
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2285817809
Short name T11
Test name
Test status
Simulation time 1077198395 ps
CPU time 12.09 seconds
Started Aug 04 05:31:29 PM PDT 24
Finished Aug 04 05:31:41 PM PDT 24
Peak memory 220028 kb
Host smart-f046b514-71e2-4875-a9cf-0a9497421b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285817809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2285817809
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1488820919
Short name T204
Test name
Test status
Simulation time 560099209 ps
CPU time 13.37 seconds
Started Aug 04 05:31:47 PM PDT 24
Finished Aug 04 05:32:00 PM PDT 24
Peak memory 219920 kb
Host smart-051323c3-8616-40e7-a5fe-b3b83f8fd963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488820919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1488820919
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3454225318
Short name T34
Test name
Test status
Simulation time 565051897 ps
CPU time 10.09 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 219220 kb
Host smart-0c609460-240e-4687-ae44-dceb566daed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454225318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3454225318
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2123539109
Short name T199
Test name
Test status
Simulation time 1381301480 ps
CPU time 19.26 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:24 PM PDT 24
Peak memory 220100 kb
Host smart-c8d29347-646f-48fe-934b-3271ffcc76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123539109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2123539109
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2395289107
Short name T5
Test name
Test status
Simulation time 271113141 ps
CPU time 12.04 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 220008 kb
Host smart-698cbd6d-9d07-4f25-aa3d-4191e6086190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395289107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2395289107
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1557739774
Short name T44
Test name
Test status
Simulation time 380077917 ps
CPU time 26.89 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:35 PM PDT 24
Peak memory 219976 kb
Host smart-52801912-8474-4c43-a8fa-619acb2ff67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557739774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1557739774
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2396184944
Short name T219
Test name
Test status
Simulation time 168195057 ps
CPU time 8.31 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:32:13 PM PDT 24
Peak memory 219100 kb
Host smart-83c2675e-b637-4566-8ce6-32dc230624e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396184944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2396184944
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4245655059
Short name T299
Test name
Test status
Simulation time 7216233563 ps
CPU time 137.44 seconds
Started Aug 04 05:32:15 PM PDT 24
Finished Aug 04 05:34:32 PM PDT 24
Peak memory 242648 kb
Host smart-82e51104-edf3-45eb-8e64-1bc650f03ad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245655059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4245655059
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3635105733
Short name T131
Test name
Test status
Simulation time 339772947 ps
CPU time 19.37 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:26 PM PDT 24
Peak memory 220060 kb
Host smart-d3a925d6-3476-4b88-b45b-0cd401df7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635105733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3635105733
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2832226847
Short name T257
Test name
Test status
Simulation time 184467535 ps
CPU time 10.22 seconds
Started Aug 04 05:32:14 PM PDT 24
Finished Aug 04 05:32:24 PM PDT 24
Peak memory 220080 kb
Host smart-478a2083-952f-4c64-b64b-00e2aea51a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832226847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2832226847
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4119438124
Short name T157
Test name
Test status
Simulation time 818524314 ps
CPU time 38.42 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:46 PM PDT 24
Peak memory 220024 kb
Host smart-67429b58-05cd-400c-878e-b61c9a0f9d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119438124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4119438124
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1341614706
Short name T40
Test name
Test status
Simulation time 9112352898 ps
CPU time 181.38 seconds
Started Aug 04 05:32:01 PM PDT 24
Finished Aug 04 05:35:02 PM PDT 24
Peak memory 237804 kb
Host smart-4c6d7bff-6f91-4b46-9f2d-f182ac59b37f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341614706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1341614706
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.693214157
Short name T27
Test name
Test status
Simulation time 1374718336 ps
CPU time 19.18 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:30 PM PDT 24
Peak memory 220116 kb
Host smart-b62d0b9f-8dfa-48da-b0d1-2b7d628e0b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693214157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.693214157
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3927003557
Short name T253
Test name
Test status
Simulation time 270921284 ps
CPU time 12.24 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:32:14 PM PDT 24
Peak memory 220272 kb
Host smart-260668f7-2fee-41ae-998e-9e5b56f5dc5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927003557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3927003557
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.400706327
Short name T130
Test name
Test status
Simulation time 687868693 ps
CPU time 8.13 seconds
Started Aug 04 05:32:14 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 219180 kb
Host smart-39d0c60a-60ff-4d62-8ac7-657a3ab09959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400706327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.400706327
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.354873116
Short name T22
Test name
Test status
Simulation time 5876923638 ps
CPU time 142.32 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:34:27 PM PDT 24
Peak memory 220332 kb
Host smart-3070c26a-55ae-4335-a0da-f3df572d70b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354873116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.354873116
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3892492508
Short name T307
Test name
Test status
Simulation time 2249081608 ps
CPU time 22.74 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:28 PM PDT 24
Peak memory 220212 kb
Host smart-621abf4d-8cb7-4c26-af08-fed5cae8ee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892492508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3892492508
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1032583945
Short name T164
Test name
Test status
Simulation time 179035946 ps
CPU time 10.74 seconds
Started Aug 04 05:32:14 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 220080 kb
Host smart-8833c4f2-13d7-441f-9218-f706c1743147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032583945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1032583945
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1183945367
Short name T230
Test name
Test status
Simulation time 2345706596 ps
CPU time 27.71 seconds
Started Aug 04 05:32:12 PM PDT 24
Finished Aug 04 05:32:40 PM PDT 24
Peak memory 220176 kb
Host smart-cec57a93-cf1d-47c1-bc11-29d493bb4e65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183945367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1183945367
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.541634702
Short name T60
Test name
Test status
Simulation time 334322513 ps
CPU time 8.35 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 219004 kb
Host smart-dc79edd3-affa-422d-b587-91139693c578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541634702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.541634702
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4103145829
Short name T235
Test name
Test status
Simulation time 4614650186 ps
CPU time 184.64 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:35:09 PM PDT 24
Peak memory 245820 kb
Host smart-3bbfbffc-2ff8-4787-b503-a4261b70dd8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103145829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4103145829
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.640728521
Short name T284
Test name
Test status
Simulation time 1831696609 ps
CPU time 22.18 seconds
Started Aug 04 05:32:02 PM PDT 24
Finished Aug 04 05:32:24 PM PDT 24
Peak memory 220124 kb
Host smart-9a7acba3-72fe-47cb-89ab-f27e0d0ff2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640728521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.640728521
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2173059560
Short name T275
Test name
Test status
Simulation time 996570828 ps
CPU time 16.75 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 219352 kb
Host smart-ffb96233-25a8-4d40-98ba-0bab95609164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173059560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2173059560
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1248621557
Short name T281
Test name
Test status
Simulation time 570899965 ps
CPU time 20.61 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 219956 kb
Host smart-3b7f2c3a-a71a-48ea-8bc1-89d2dbc98902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248621557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1248621557
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3518280244
Short name T166
Test name
Test status
Simulation time 437079046 ps
CPU time 10.02 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 219180 kb
Host smart-51fcc7a4-9ec4-4110-a49d-241b0741b6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518280244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3518280244
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2370147596
Short name T218
Test name
Test status
Simulation time 4518851269 ps
CPU time 168.77 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:34:59 PM PDT 24
Peak memory 220312 kb
Host smart-aef821a1-4685-4e2e-baa6-a5a7830b901a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370147596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2370147596
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1664077760
Short name T248
Test name
Test status
Simulation time 664007635 ps
CPU time 19.27 seconds
Started Aug 04 05:32:12 PM PDT 24
Finished Aug 04 05:32:31 PM PDT 24
Peak memory 220072 kb
Host smart-e6380677-fe77-4e5e-82d6-1e96e46f5f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664077760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1664077760
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1009659510
Short name T161
Test name
Test status
Simulation time 1123158838 ps
CPU time 12.17 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220040 kb
Host smart-18d0232e-3de7-4007-80a8-5d7c1b73b230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009659510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1009659510
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.427081628
Short name T203
Test name
Test status
Simulation time 18030040566 ps
CPU time 39.41 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:45 PM PDT 24
Peak memory 220032 kb
Host smart-bbf311ff-485b-4ae8-b16f-144b9183924b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427081628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.427081628
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3642534295
Short name T311
Test name
Test status
Simulation time 991609735 ps
CPU time 9.99 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219076 kb
Host smart-c46d2751-7710-469e-8da9-00c642878cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642534295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3642534295
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.535548578
Short name T21
Test name
Test status
Simulation time 3460552311 ps
CPU time 263.88 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:36:31 PM PDT 24
Peak memory 235372 kb
Host smart-fda7c15f-be7c-4743-b4ad-cb7d70a0f1cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535548578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.535548578
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1730906106
Short name T178
Test name
Test status
Simulation time 722031322 ps
CPU time 19.29 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 220108 kb
Host smart-79d1a8a8-148d-4d1b-a7dc-5614b547c212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730906106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1730906106
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4119283095
Short name T124
Test name
Test status
Simulation time 264415279 ps
CPU time 12.22 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 220040 kb
Host smart-6c42846c-905b-45b9-a9da-4f06ce589aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119283095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4119283095
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.86008450
Short name T14
Test name
Test status
Simulation time 1488730768 ps
CPU time 20.99 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:28 PM PDT 24
Peak memory 220052 kb
Host smart-e24d484a-2b42-4de6-a5ca-9fca0940a8dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86008450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.86008450
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3059912617
Short name T294
Test name
Test status
Simulation time 112111097069 ps
CPU time 1035.21 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:49:25 PM PDT 24
Peak memory 237976 kb
Host smart-c4ae8ab4-dad3-49ab-9603-8a481e09e93d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059912617 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3059912617
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1570156853
Short name T191
Test name
Test status
Simulation time 1904913245 ps
CPU time 9.83 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 219064 kb
Host smart-4f92d40d-d072-43ba-b589-787bf7df587e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570156853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1570156853
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2847396752
Short name T193
Test name
Test status
Simulation time 6779453796 ps
CPU time 185.97 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:35:14 PM PDT 24
Peak memory 230412 kb
Host smart-41c6758f-4cef-4023-ac55-f4ecccb3a685
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847396752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2847396752
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.451875145
Short name T145
Test name
Test status
Simulation time 1977200698 ps
CPU time 22.92 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:30 PM PDT 24
Peak memory 219980 kb
Host smart-88ce7d80-8d2f-4f63-a29e-e435bf0484af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451875145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.451875145
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.116979916
Short name T119
Test name
Test status
Simulation time 184201584 ps
CPU time 10.61 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220028 kb
Host smart-35b21934-b911-403e-8fff-90f10496f83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116979916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.116979916
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2579046944
Short name T48
Test name
Test status
Simulation time 110872582887 ps
CPU time 3655.46 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 06:32:51 PM PDT 24
Peak memory 257032 kb
Host smart-8084053b-ccb3-465b-8696-6b9ffb5d8ac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579046944 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2579046944
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4044391254
Short name T276
Test name
Test status
Simulation time 497882781 ps
CPU time 10.02 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 219016 kb
Host smart-b8729219-8680-4022-a62f-57db2b6eaa56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044391254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4044391254
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.106784380
Short name T135
Test name
Test status
Simulation time 1823095346 ps
CPU time 121.36 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:34:05 PM PDT 24
Peak memory 219836 kb
Host smart-1b73b068-8f42-48e5-baaa-5e7c3237af6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106784380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.106784380
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2872907749
Short name T163
Test name
Test status
Simulation time 1381946931 ps
CPU time 19.35 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220080 kb
Host smart-fa373ee9-b671-4b19-84ec-7caa7ad0b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872907749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2872907749
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2668554359
Short name T179
Test name
Test status
Simulation time 181596525 ps
CPU time 10.05 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 220040 kb
Host smart-369907ac-2cf7-43be-a73c-12f8a55d5465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668554359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2668554359
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.597634585
Short name T295
Test name
Test status
Simulation time 935293240 ps
CPU time 11.77 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220032 kb
Host smart-5b8659b6-98b0-4ff8-a6d0-6e27c0e07963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597634585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.597634585
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3655141551
Short name T211
Test name
Test status
Simulation time 2247805064 ps
CPU time 10.09 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 219208 kb
Host smart-cf8145be-9285-46b3-8ce0-e3130a41f93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655141551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3655141551
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1245189784
Short name T260
Test name
Test status
Simulation time 14442469081 ps
CPU time 173.69 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:34:58 PM PDT 24
Peak memory 220340 kb
Host smart-615b1b48-7968-4236-8be4-4ff1c3905e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245189784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1245189784
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1698347391
Short name T217
Test name
Test status
Simulation time 1323662454 ps
CPU time 19.29 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 220004 kb
Host smart-b59fb039-a7f7-4ed8-809b-8094c240ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698347391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1698347391
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3274445792
Short name T262
Test name
Test status
Simulation time 763536030 ps
CPU time 10.35 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 220040 kb
Host smart-7c1adc20-651d-4273-96a1-e6d5c79cde5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274445792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3274445792
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.693034466
Short name T251
Test name
Test status
Simulation time 7992643962 ps
CPU time 40.28 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:50 PM PDT 24
Peak memory 220156 kb
Host smart-90aa1e38-d94d-4f4c-b3d1-d0698c916130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693034466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.693034466
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2289179682
Short name T176
Test name
Test status
Simulation time 689848309 ps
CPU time 8.63 seconds
Started Aug 04 05:31:48 PM PDT 24
Finished Aug 04 05:31:57 PM PDT 24
Peak memory 219228 kb
Host smart-e969c031-28f9-49e8-a3b7-27ac8d521772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289179682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2289179682
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3756708028
Short name T1
Test name
Test status
Simulation time 36342247315 ps
CPU time 393.41 seconds
Started Aug 04 05:31:34 PM PDT 24
Finished Aug 04 05:38:07 PM PDT 24
Peak memory 231868 kb
Host smart-80c1dcdd-30c2-4614-8ed4-85721386ceeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756708028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3756708028
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.744714465
Short name T232
Test name
Test status
Simulation time 5511516906 ps
CPU time 19.51 seconds
Started Aug 04 05:31:30 PM PDT 24
Finished Aug 04 05:31:50 PM PDT 24
Peak memory 220140 kb
Host smart-d1022cf8-5fea-458c-b66e-83e3d726f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744714465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.744714465
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1245716163
Short name T32
Test name
Test status
Simulation time 735554256 ps
CPU time 10.77 seconds
Started Aug 04 05:31:45 PM PDT 24
Finished Aug 04 05:31:56 PM PDT 24
Peak memory 220124 kb
Host smart-7c11abbe-4ec6-46fd-807f-8be1362365a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245716163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1245716163
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2681757362
Short name T25
Test name
Test status
Simulation time 357745047 ps
CPU time 119.29 seconds
Started Aug 04 05:31:33 PM PDT 24
Finished Aug 04 05:33:32 PM PDT 24
Peak memory 239984 kb
Host smart-c6e52c11-2cd4-4741-ae13-9c6387dc9e8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681757362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2681757362
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1018446846
Short name T243
Test name
Test status
Simulation time 1027365243 ps
CPU time 12.12 seconds
Started Aug 04 05:31:27 PM PDT 24
Finished Aug 04 05:31:44 PM PDT 24
Peak memory 220072 kb
Host smart-d2d3315d-a8c8-4e91-8284-406316f3adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018446846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1018446846
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2351776947
Short name T240
Test name
Test status
Simulation time 814608342 ps
CPU time 38.32 seconds
Started Aug 04 05:31:38 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 220048 kb
Host smart-daeef53d-c157-4647-b074-50f96737ebf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351776947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2351776947
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1641542925
Short name T273
Test name
Test status
Simulation time 987751008 ps
CPU time 9.9 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219208 kb
Host smart-fe6b7bca-0a87-4118-a13a-5b8e01e0bd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641542925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1641542925
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3048821694
Short name T301
Test name
Test status
Simulation time 8827200012 ps
CPU time 316.28 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:37:26 PM PDT 24
Peak memory 235772 kb
Host smart-142e89c6-92e9-4432-aa14-29dbf1ba6d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048821694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3048821694
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3258736192
Short name T43
Test name
Test status
Simulation time 846941787 ps
CPU time 19.45 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220064 kb
Host smart-2cc5a354-caf0-4739-8f21-de57c8a48184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258736192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3258736192
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3534738485
Short name T102
Test name
Test status
Simulation time 266832117 ps
CPU time 12.03 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 220084 kb
Host smart-19653b1c-f10c-483c-858e-6247e0809094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534738485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3534738485
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2162697933
Short name T15
Test name
Test status
Simulation time 589199141 ps
CPU time 33.2 seconds
Started Aug 04 05:31:55 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220036 kb
Host smart-027e4b37-a232-42b7-b6b8-d510ee248a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162697933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2162697933
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3643888419
Short name T63
Test name
Test status
Simulation time 176409252 ps
CPU time 8.19 seconds
Started Aug 04 05:32:17 PM PDT 24
Finished Aug 04 05:32:25 PM PDT 24
Peak memory 218972 kb
Host smart-8c28fe30-13e2-4bec-bfca-3d63457559db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643888419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3643888419
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.327176596
Short name T154
Test name
Test status
Simulation time 3254967896 ps
CPU time 153.67 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:34:44 PM PDT 24
Peak memory 237460 kb
Host smart-a773b42c-e100-4479-8b3b-aa368cb85e09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327176596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.327176596
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3382095392
Short name T146
Test name
Test status
Simulation time 678396962 ps
CPU time 22.22 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 219972 kb
Host smart-afaef28d-9365-4b17-b9dc-6c4cacbd09cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382095392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3382095392
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1115388994
Short name T316
Test name
Test status
Simulation time 519532996 ps
CPU time 12.2 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220072 kb
Host smart-c1b5afb5-fb10-455c-b5ce-6fbce127c707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115388994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1115388994
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1804749955
Short name T147
Test name
Test status
Simulation time 2087936677 ps
CPU time 27.31 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:27 PM PDT 24
Peak memory 220056 kb
Host smart-88068257-f7b0-4dca-a5f9-36694e9309c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804749955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1804749955
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2821548071
Short name T150
Test name
Test status
Simulation time 506956651 ps
CPU time 10.02 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 219096 kb
Host smart-b582c654-b82a-4a92-94b1-306769490419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821548071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2821548071
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4191666705
Short name T174
Test name
Test status
Simulation time 17879302703 ps
CPU time 238.15 seconds
Started Aug 04 05:32:13 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 226816 kb
Host smart-66728edd-d835-4336-acc6-140db73d5c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191666705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4191666705
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3897427454
Short name T306
Test name
Test status
Simulation time 1507902319 ps
CPU time 19.32 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:31 PM PDT 24
Peak memory 220124 kb
Host smart-1d860157-af3f-412e-9f37-1246120f6b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897427454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3897427454
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3821347109
Short name T152
Test name
Test status
Simulation time 2870684035 ps
CPU time 9.92 seconds
Started Aug 04 05:33:09 PM PDT 24
Finished Aug 04 05:33:19 PM PDT 24
Peak memory 219288 kb
Host smart-b648862d-3284-4922-adc2-dd0602977d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821347109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3821347109
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3135629530
Short name T319
Test name
Test status
Simulation time 2568329947 ps
CPU time 10.73 seconds
Started Aug 04 05:32:05 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 220048 kb
Host smart-a620b9cd-4f12-408d-b246-0584e764ae15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135629530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3135629530
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3256584537
Short name T291
Test name
Test status
Simulation time 259914021 ps
CPU time 10.01 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 218992 kb
Host smart-b8fbf4ea-917d-423f-8729-c77bf86cc4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256584537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3256584537
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1491485972
Short name T136
Test name
Test status
Simulation time 21391079830 ps
CPU time 306.25 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:37:10 PM PDT 24
Peak memory 241536 kb
Host smart-b9289b46-47fd-4303-a9ab-f3b802249ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491485972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1491485972
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3581273299
Short name T224
Test name
Test status
Simulation time 1650220336 ps
CPU time 18.98 seconds
Started Aug 04 05:32:04 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 220132 kb
Host smart-d35dfbbc-0502-43c2-bf6c-29c17b65b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581273299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3581273299
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2826889777
Short name T270
Test name
Test status
Simulation time 1148003967 ps
CPU time 11.65 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220064 kb
Host smart-5c191c0f-11dc-4ceb-8918-8789c06bd670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826889777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2826889777
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3211134704
Short name T286
Test name
Test status
Simulation time 2224390342 ps
CPU time 37.6 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:45 PM PDT 24
Peak memory 220048 kb
Host smart-778925f5-041c-486c-be07-25fd1e387490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211134704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3211134704
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.854765972
Short name T314
Test name
Test status
Simulation time 345567039 ps
CPU time 8.56 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 219020 kb
Host smart-b2ba93e1-da0b-4b98-a4cd-0fcc245275a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854765972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.854765972
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1526958489
Short name T249
Test name
Test status
Simulation time 15659691934 ps
CPU time 265.39 seconds
Started Aug 04 05:32:17 PM PDT 24
Finished Aug 04 05:36:43 PM PDT 24
Peak memory 240360 kb
Host smart-c74d2fb5-0636-4b7f-a0eb-e5680e723e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526958489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1526958489
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2253409190
Short name T201
Test name
Test status
Simulation time 2150619119 ps
CPU time 23.12 seconds
Started Aug 04 05:32:14 PM PDT 24
Finished Aug 04 05:32:37 PM PDT 24
Peak memory 220244 kb
Host smart-8c0f83c7-e129-493b-97b7-71313772b5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253409190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2253409190
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1826380474
Short name T189
Test name
Test status
Simulation time 365200090 ps
CPU time 10.49 seconds
Started Aug 04 05:32:03 PM PDT 24
Finished Aug 04 05:32:13 PM PDT 24
Peak memory 220076 kb
Host smart-2a355157-75fa-40c0-8993-4af33828f296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826380474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1826380474
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1077736031
Short name T127
Test name
Test status
Simulation time 813284919 ps
CPU time 27.58 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:35 PM PDT 24
Peak memory 220016 kb
Host smart-e761daf3-067a-408d-b95e-30d1eb217450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077736031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1077736031
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.203604453
Short name T156
Test name
Test status
Simulation time 250173098 ps
CPU time 9.72 seconds
Started Aug 04 05:33:21 PM PDT 24
Finished Aug 04 05:33:31 PM PDT 24
Peak memory 219040 kb
Host smart-26c147fe-85c3-44a3-8ebc-60f98346ad24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203604453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.203604453
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2489207677
Short name T133
Test name
Test status
Simulation time 9797669127 ps
CPU time 124.47 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:34:15 PM PDT 24
Peak memory 220236 kb
Host smart-809d468e-99ab-41fa-86ab-abd91d6b7813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489207677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2489207677
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3516966060
Short name T280
Test name
Test status
Simulation time 3938184085 ps
CPU time 32.51 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:40 PM PDT 24
Peak memory 219700 kb
Host smart-6727ba51-107a-464a-bed8-aab514d7700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516966060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3516966060
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.582628108
Short name T255
Test name
Test status
Simulation time 536930900 ps
CPU time 11.96 seconds
Started Aug 04 05:32:17 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 219824 kb
Host smart-035fef4d-5462-410d-90ce-29a97a754648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582628108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.582628108
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3559198641
Short name T115
Test name
Test status
Simulation time 11885350187 ps
CPU time 49.06 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:33:11 PM PDT 24
Peak memory 220192 kb
Host smart-a8b4b404-42ba-4bec-a8e0-306c4387a2b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559198641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3559198641
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4074337850
Short name T322
Test name
Test status
Simulation time 719490004 ps
CPU time 8.25 seconds
Started Aug 04 05:32:18 PM PDT 24
Finished Aug 04 05:32:26 PM PDT 24
Peak memory 219076 kb
Host smart-1f6efcaf-8a4e-4ed0-9447-7dc50521a095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074337850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4074337850
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2121779143
Short name T196
Test name
Test status
Simulation time 38553452413 ps
CPU time 313.82 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:37:30 PM PDT 24
Peak memory 220276 kb
Host smart-c94b90b5-34b5-4fa8-ba50-7737aa9aad25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121779143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2121779143
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3872857419
Short name T282
Test name
Test status
Simulation time 2250461833 ps
CPU time 21.84 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:32:38 PM PDT 24
Peak memory 220116 kb
Host smart-deb60510-26c4-4adf-88a9-c49832f37779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872857419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3872857419
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3155607125
Short name T125
Test name
Test status
Simulation time 262797763 ps
CPU time 12.57 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 220064 kb
Host smart-d0f68afd-d447-40d6-8c87-b2641cd77f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155607125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3155607125
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2846511643
Short name T317
Test name
Test status
Simulation time 700908549 ps
CPU time 38.33 seconds
Started Aug 04 05:32:17 PM PDT 24
Finished Aug 04 05:32:55 PM PDT 24
Peak memory 219924 kb
Host smart-953d7519-4e71-434d-b295-852e53986165
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846511643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2846511643
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3302647457
Short name T181
Test name
Test status
Simulation time 1033972323 ps
CPU time 9.99 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 218992 kb
Host smart-94d654f6-04e4-4314-beab-ecc516e2ad74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302647457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3302647457
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.792395451
Short name T180
Test name
Test status
Simulation time 3328889041 ps
CPU time 175.73 seconds
Started Aug 04 05:32:12 PM PDT 24
Finished Aug 04 05:35:08 PM PDT 24
Peak memory 238268 kb
Host smart-189754a8-ef20-4a4c-a25f-77dac19a97fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792395451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.792395451
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4188646516
Short name T274
Test name
Test status
Simulation time 675342051 ps
CPU time 19.16 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:32:35 PM PDT 24
Peak memory 220016 kb
Host smart-ed3ed125-d60c-4715-a27a-24c2ef24e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188646516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4188646516
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.989881485
Short name T141
Test name
Test status
Simulation time 273836649 ps
CPU time 11.68 seconds
Started Aug 04 05:33:19 PM PDT 24
Finished Aug 04 05:33:31 PM PDT 24
Peak memory 219744 kb
Host smart-494ddedd-2c93-49fa-850b-0733c8830cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989881485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.989881485
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3770498729
Short name T315
Test name
Test status
Simulation time 1604812308 ps
CPU time 19.56 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:32:36 PM PDT 24
Peak memory 219916 kb
Host smart-c2d8eb3d-43c2-4b6e-b629-48b130c4eb8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770498729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3770498729
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3557722817
Short name T139
Test name
Test status
Simulation time 639527287 ps
CPU time 8.28 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:19 PM PDT 24
Peak memory 219060 kb
Host smart-59e824cc-756d-4bf2-8e75-d3025786754b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557722817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3557722817
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.380664698
Short name T279
Test name
Test status
Simulation time 2144098140 ps
CPU time 175.14 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:35:03 PM PDT 24
Peak memory 243876 kb
Host smart-6f6e63ba-06d8-4a09-9d54-a17825cd69fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380664698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.380664698
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2933963246
Short name T237
Test name
Test status
Simulation time 496811938 ps
CPU time 22.65 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220096 kb
Host smart-0376310b-f57b-46ec-bdfc-e407bd0d1130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933963246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2933963246
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1853848618
Short name T170
Test name
Test status
Simulation time 367280740 ps
CPU time 10.07 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:21 PM PDT 24
Peak memory 220072 kb
Host smart-e6a3ffb7-aa45-437d-ae5d-58723047158f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853848618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1853848618
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2342991365
Short name T80
Test name
Test status
Simulation time 1095659143 ps
CPU time 28.06 seconds
Started Aug 04 05:32:11 PM PDT 24
Finished Aug 04 05:32:39 PM PDT 24
Peak memory 219988 kb
Host smart-a07998b9-a386-448c-932b-33f6acfddf9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342991365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2342991365
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3496723949
Short name T187
Test name
Test status
Simulation time 251212588 ps
CPU time 10.06 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:18 PM PDT 24
Peak memory 219308 kb
Host smart-9a2fba31-ef46-48c3-8fdf-3588514f83fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496723949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3496723949
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3008024199
Short name T123
Test name
Test status
Simulation time 26087394052 ps
CPU time 415.82 seconds
Started Aug 04 05:32:16 PM PDT 24
Finished Aug 04 05:39:12 PM PDT 24
Peak memory 240764 kb
Host smart-5b4ae415-98cc-4406-85a4-f1e30861d964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008024199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3008024199
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1049384936
Short name T30
Test name
Test status
Simulation time 338847879 ps
CPU time 19.62 seconds
Started Aug 04 05:32:09 PM PDT 24
Finished Aug 04 05:32:29 PM PDT 24
Peak memory 220104 kb
Host smart-65416f4f-cc3d-4dd2-b9a5-cbefe7bde5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049384936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1049384936
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1323662718
Short name T194
Test name
Test status
Simulation time 1808864040 ps
CPU time 11.97 seconds
Started Aug 04 05:32:10 PM PDT 24
Finished Aug 04 05:32:22 PM PDT 24
Peak memory 220092 kb
Host smart-ec8447dc-d5b6-493b-b23c-1e5eddcc1be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323662718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1323662718
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2453503700
Short name T250
Test name
Test status
Simulation time 305273582 ps
CPU time 24.14 seconds
Started Aug 04 05:32:13 PM PDT 24
Finished Aug 04 05:32:37 PM PDT 24
Peak memory 219996 kb
Host smart-25ddcf5a-7d7a-4f46-b7e4-3c0218b7b88d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453503700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2453503700
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1301635455
Short name T7
Test name
Test status
Simulation time 3090527323 ps
CPU time 10.09 seconds
Started Aug 04 05:31:44 PM PDT 24
Finished Aug 04 05:31:54 PM PDT 24
Peak memory 219136 kb
Host smart-b30bb386-6910-44d1-99f2-a18cb67a3564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301635455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1301635455
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3557377551
Short name T268
Test name
Test status
Simulation time 5969773804 ps
CPU time 399.76 seconds
Started Aug 04 05:31:51 PM PDT 24
Finished Aug 04 05:38:31 PM PDT 24
Peak memory 243236 kb
Host smart-ae6da409-26c0-4515-a42e-faeedc764cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557377551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3557377551
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3687314739
Short name T304
Test name
Test status
Simulation time 2356429357 ps
CPU time 19.4 seconds
Started Aug 04 05:31:31 PM PDT 24
Finished Aug 04 05:31:50 PM PDT 24
Peak memory 220224 kb
Host smart-7dc283d4-5e67-4a7a-b5eb-e58d3f3cc174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687314739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3687314739
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2329730183
Short name T290
Test name
Test status
Simulation time 511915652 ps
CPU time 12.03 seconds
Started Aug 04 05:32:08 PM PDT 24
Finished Aug 04 05:32:20 PM PDT 24
Peak memory 220084 kb
Host smart-ae5de228-e552-4f9e-bb7d-7804278d48bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329730183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2329730183
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3400745745
Short name T142
Test name
Test status
Simulation time 903133886 ps
CPU time 10.25 seconds
Started Aug 04 05:31:38 PM PDT 24
Finished Aug 04 05:31:48 PM PDT 24
Peak memory 220116 kb
Host smart-a85ba0d7-0864-4f1c-a85f-d48887e41cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400745745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3400745745
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2528809447
Short name T19
Test name
Test status
Simulation time 875111355 ps
CPU time 44.16 seconds
Started Aug 04 05:31:46 PM PDT 24
Finished Aug 04 05:32:30 PM PDT 24
Peak memory 220056 kb
Host smart-90b5032d-b2a9-4d4b-baf5-c521c3b2787c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528809447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2528809447
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3549926025
Short name T31
Test name
Test status
Simulation time 990300165 ps
CPU time 9.94 seconds
Started Aug 04 05:31:51 PM PDT 24
Finished Aug 04 05:32:01 PM PDT 24
Peak memory 219900 kb
Host smart-86e70c5d-6939-419b-88bd-c9d610cd52b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549926025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3549926025
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3492069842
Short name T302
Test name
Test status
Simulation time 52116512043 ps
CPU time 281.12 seconds
Started Aug 04 05:31:42 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 241040 kb
Host smart-519b47a4-489b-4524-9d49-0520f8c8b9f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492069842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3492069842
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2688955411
Short name T129
Test name
Test status
Simulation time 2066187575 ps
CPU time 22.86 seconds
Started Aug 04 05:32:00 PM PDT 24
Finished Aug 04 05:32:23 PM PDT 24
Peak memory 220084 kb
Host smart-f6a81e22-584b-4882-abbc-07b040be5ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688955411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2688955411
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2605834759
Short name T206
Test name
Test status
Simulation time 185110860 ps
CPU time 10.41 seconds
Started Aug 04 05:31:49 PM PDT 24
Finished Aug 04 05:31:59 PM PDT 24
Peak memory 220116 kb
Host smart-07daaa9b-2417-4303-86d3-220043743c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605834759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2605834759
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.22615126
Short name T76
Test name
Test status
Simulation time 1021126106 ps
CPU time 12.71 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:07 PM PDT 24
Peak memory 220068 kb
Host smart-cea0d5e0-0db8-41e2-9485-4a087de50296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22615126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.22615126
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.283147485
Short name T225
Test name
Test status
Simulation time 1541005344 ps
CPU time 20.95 seconds
Started Aug 04 05:31:34 PM PDT 24
Finished Aug 04 05:31:55 PM PDT 24
Peak memory 220032 kb
Host smart-17d2cd77-e243-4f59-9b6d-d6109b875e92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283147485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.283147485
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.219618985
Short name T52
Test name
Test status
Simulation time 80823854600 ps
CPU time 8097.26 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 07:46:50 PM PDT 24
Peak memory 234808 kb
Host smart-2c6ae9df-ebe1-48f0-ba6d-98fd0eea495e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219618985 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.219618985
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2856887987
Short name T4
Test name
Test status
Simulation time 2239850002 ps
CPU time 10.06 seconds
Started Aug 04 05:31:31 PM PDT 24
Finished Aug 04 05:31:41 PM PDT 24
Peak memory 219136 kb
Host smart-df2bbd00-f9d1-4d28-9440-acd8624b5ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856887987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2856887987
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3960991302
Short name T160
Test name
Test status
Simulation time 2245463888 ps
CPU time 22.8 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 220192 kb
Host smart-54f44601-ed31-48f5-abd2-81529dd363fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960991302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3960991302
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1187613021
Short name T320
Test name
Test status
Simulation time 184209098 ps
CPU time 10.42 seconds
Started Aug 04 05:31:46 PM PDT 24
Finished Aug 04 05:31:57 PM PDT 24
Peak memory 220108 kb
Host smart-10c55bc3-ae28-465b-a353-3a07d4b18cd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187613021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1187613021
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.10642910
Short name T77
Test name
Test status
Simulation time 1069260917 ps
CPU time 12.76 seconds
Started Aug 04 05:31:56 PM PDT 24
Finished Aug 04 05:32:09 PM PDT 24
Peak memory 219520 kb
Host smart-99a7b9fc-5d67-4d96-8d44-df71ce64874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10642910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.10642910
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3164523300
Short name T74
Test name
Test status
Simulation time 4057080564 ps
CPU time 31.75 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:32:24 PM PDT 24
Peak memory 220108 kb
Host smart-3613ca71-6eed-475a-b4f1-36ad5a8b101f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164523300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3164523300
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3800524302
Short name T53
Test name
Test status
Simulation time 38513843284 ps
CPU time 8458.58 seconds
Started Aug 04 05:31:38 PM PDT 24
Finished Aug 04 07:52:37 PM PDT 24
Peak memory 236664 kb
Host smart-f4a8dc53-61c8-4108-99c1-f8541e362089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800524302 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3800524302
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3683628375
Short name T168
Test name
Test status
Simulation time 988546527 ps
CPU time 10.25 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:04 PM PDT 24
Peak memory 218940 kb
Host smart-7f2072d9-1a1c-4dec-8488-de6047f11bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683628375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3683628375
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.167031042
Short name T39
Test name
Test status
Simulation time 7518584513 ps
CPU time 247.3 seconds
Started Aug 04 05:31:48 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 241040 kb
Host smart-77d6c661-9266-43eb-b7d0-6798aa356a79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167031042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.167031042
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3662623488
Short name T143
Test name
Test status
Simulation time 1985920875 ps
CPU time 22.23 seconds
Started Aug 04 05:31:52 PM PDT 24
Finished Aug 04 05:32:14 PM PDT 24
Peak memory 219992 kb
Host smart-b630ad2d-836f-4fdd-ac36-6f47f24cc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662623488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3662623488
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3966851643
Short name T192
Test name
Test status
Simulation time 180929820 ps
CPU time 10.21 seconds
Started Aug 04 05:31:43 PM PDT 24
Finished Aug 04 05:31:53 PM PDT 24
Peak memory 220080 kb
Host smart-10fe8d9d-f332-4320-b33e-55b2155ed6da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966851643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3966851643
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3433253872
Short name T175
Test name
Test status
Simulation time 257334323 ps
CPU time 11.9 seconds
Started Aug 04 05:31:54 PM PDT 24
Finished Aug 04 05:32:06 PM PDT 24
Peak memory 219496 kb
Host smart-fa4ee1ae-5ae2-446d-98f4-bb9d33bb1bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433253872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3433253872
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1605982717
Short name T195
Test name
Test status
Simulation time 203933046 ps
CPU time 22.09 seconds
Started Aug 04 05:31:53 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 219456 kb
Host smart-e5072b11-58a1-46c3-852c-6ffb847201d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605982717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1605982717
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1676780065
Short name T151
Test name
Test status
Simulation time 176146693 ps
CPU time 8.32 seconds
Started Aug 04 05:31:42 PM PDT 24
Finished Aug 04 05:31:50 PM PDT 24
Peak memory 219172 kb
Host smart-3a161000-a5c7-4043-8c7d-039e22d6557c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676780065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1676780065
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2211431198
Short name T205
Test name
Test status
Simulation time 5128958323 ps
CPU time 188.87 seconds
Started Aug 04 05:31:40 PM PDT 24
Finished Aug 04 05:34:49 PM PDT 24
Peak memory 239716 kb
Host smart-6c9c1109-1e09-4d5c-a990-1ed59d603ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211431198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2211431198
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4070963623
Short name T289
Test name
Test status
Simulation time 2058838076 ps
CPU time 31.56 seconds
Started Aug 04 05:32:07 PM PDT 24
Finished Aug 04 05:32:38 PM PDT 24
Peak memory 219652 kb
Host smart-150ab0f9-81b6-489d-a7d1-7a2580865012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070963623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4070963623
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.842949649
Short name T120
Test name
Test status
Simulation time 176873663 ps
CPU time 10.11 seconds
Started Aug 04 05:32:06 PM PDT 24
Finished Aug 04 05:32:17 PM PDT 24
Peak memory 219952 kb
Host smart-8ce011f3-44d1-40c8-abf3-a975f7b5d440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842949649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.842949649
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3471204473
Short name T78
Test name
Test status
Simulation time 640460716 ps
CPU time 12 seconds
Started Aug 04 05:31:59 PM PDT 24
Finished Aug 04 05:32:11 PM PDT 24
Peak memory 219960 kb
Host smart-5f3692c6-ee5f-471d-a072-058120f9cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471204473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3471204473
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3940070211
Short name T190
Test name
Test status
Simulation time 596274745 ps
CPU time 19.84 seconds
Started Aug 04 05:31:46 PM PDT 24
Finished Aug 04 05:32:06 PM PDT 24
Peak memory 219996 kb
Host smart-9fbf4227-4a7f-45f8-8052-0b910033e940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940070211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3940070211
Directory /workspace/9.rom_ctrl_stress_all/latest
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