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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 409
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T296 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3047825360 Aug 05 04:53:38 PM PDT 24 Aug 05 04:53:57 PM PDT 24 1326373705 ps
T297 /workspace/coverage/default/18.rom_ctrl_alert_test.3056241959 Aug 05 04:53:39 PM PDT 24 Aug 05 04:53:49 PM PDT 24 260319198 ps
T298 /workspace/coverage/default/1.rom_ctrl_alert_test.2252479989 Aug 05 04:53:37 PM PDT 24 Aug 05 04:53:46 PM PDT 24 661147548 ps
T299 /workspace/coverage/default/29.rom_ctrl_stress_all.898013505 Aug 05 04:53:37 PM PDT 24 Aug 05 04:53:53 PM PDT 24 1105647069 ps
T300 /workspace/coverage/default/19.rom_ctrl_alert_test.3698333756 Aug 05 04:53:38 PM PDT 24 Aug 05 04:53:46 PM PDT 24 234927126 ps
T301 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.734829554 Aug 05 04:53:38 PM PDT 24 Aug 05 04:53:57 PM PDT 24 4721018561 ps
T302 /workspace/coverage/default/45.rom_ctrl_alert_test.554459990 Aug 05 04:53:52 PM PDT 24 Aug 05 04:54:00 PM PDT 24 663868628 ps
T98 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.955048101 Aug 05 04:53:54 PM PDT 24 Aug 05 05:23:26 PM PDT 24 48338181771 ps
T303 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1144562527 Aug 05 04:53:39 PM PDT 24 Aug 05 04:57:47 PM PDT 24 15775451961 ps
T304 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1180816332 Aug 05 04:53:54 PM PDT 24 Aug 05 04:58:34 PM PDT 24 16115774726 ps
T305 /workspace/coverage/default/3.rom_ctrl_alert_test.4018654422 Aug 05 04:53:37 PM PDT 24 Aug 05 04:53:46 PM PDT 24 175343831 ps
T14 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1283156790 Aug 05 04:53:45 PM PDT 24 Aug 05 05:11:36 PM PDT 24 110300124537 ps
T306 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.724363085 Aug 05 04:53:50 PM PDT 24 Aug 05 04:54:10 PM PDT 24 1320563030 ps
T307 /workspace/coverage/default/5.rom_ctrl_smoke.1791818447 Aug 05 04:53:40 PM PDT 24 Aug 05 04:53:51 PM PDT 24 783741798 ps
T308 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1526713223 Aug 05 04:53:38 PM PDT 24 Aug 05 05:07:31 PM PDT 24 22053583854 ps
T309 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4141925803 Aug 05 04:53:50 PM PDT 24 Aug 05 04:54:10 PM PDT 24 3008231480 ps
T310 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4173240550 Aug 05 04:53:40 PM PDT 24 Aug 05 04:53:59 PM PDT 24 1320591224 ps
T311 /workspace/coverage/default/47.rom_ctrl_alert_test.517505215 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:15 PM PDT 24 262824821 ps
T312 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2743022664 Aug 05 04:54:03 PM PDT 24 Aug 05 04:58:41 PM PDT 24 16726656734 ps
T313 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2056242567 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:16 PM PDT 24 881198269 ps
T314 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1485009232 Aug 05 04:53:57 PM PDT 24 Aug 05 04:54:19 PM PDT 24 518351643 ps
T315 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2115797828 Aug 05 04:53:36 PM PDT 24 Aug 05 04:53:59 PM PDT 24 494607278 ps
T316 /workspace/coverage/default/22.rom_ctrl_stress_all.1112484788 Aug 05 04:53:38 PM PDT 24 Aug 05 04:54:08 PM PDT 24 2130990472 ps
T317 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3875310553 Aug 05 04:53:28 PM PDT 24 Aug 05 04:53:41 PM PDT 24 1074587763 ps
T318 /workspace/coverage/default/27.rom_ctrl_stress_all.2053460435 Aug 05 04:53:56 PM PDT 24 Aug 05 04:54:31 PM PDT 24 4132742952 ps
T319 /workspace/coverage/default/16.rom_ctrl_stress_all.2896112847 Aug 05 04:53:43 PM PDT 24 Aug 05 04:54:04 PM PDT 24 448025680 ps
T320 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1166963930 Aug 05 04:53:58 PM PDT 24 Aug 05 04:59:57 PM PDT 24 24965467980 ps
T321 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3036280464 Aug 05 04:53:36 PM PDT 24 Aug 05 05:59:30 PM PDT 24 101737756987 ps
T322 /workspace/coverage/default/6.rom_ctrl_stress_all.36959192 Aug 05 04:53:40 PM PDT 24 Aug 05 04:54:04 PM PDT 24 679880915 ps
T323 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2232408784 Aug 05 04:53:54 PM PDT 24 Aug 05 04:54:05 PM PDT 24 213707126 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1994831874 Aug 05 04:54:30 PM PDT 24 Aug 05 04:54:39 PM PDT 24 171764172 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.445033249 Aug 05 04:54:00 PM PDT 24 Aug 05 04:54:13 PM PDT 24 754301666 ps
T58 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1505110769 Aug 05 04:53:51 PM PDT 24 Aug 05 04:54:01 PM PDT 24 917064636 ps
T324 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2737716717 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:18 PM PDT 24 1377179391 ps
T325 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4277368242 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:33 PM PDT 24 1373434832 ps
T326 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3563822437 Aug 05 04:53:57 PM PDT 24 Aug 05 04:54:06 PM PDT 24 172487920 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1460914223 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:49 PM PDT 24 695535841 ps
T327 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1084532316 Aug 05 04:53:55 PM PDT 24 Aug 05 04:54:05 PM PDT 24 376282653 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2291916616 Aug 05 04:54:04 PM PDT 24 Aug 05 04:54:13 PM PDT 24 177991573 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2306591479 Aug 05 04:54:21 PM PDT 24 Aug 05 04:54:29 PM PDT 24 662557979 ps
T62 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1217633045 Aug 05 04:54:32 PM PDT 24 Aug 05 04:54:46 PM PDT 24 259888260 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1552743336 Aug 05 04:54:17 PM PDT 24 Aug 05 04:54:56 PM PDT 24 698615834 ps
T328 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1852394035 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:31 PM PDT 24 972619384 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.57445366 Aug 05 04:54:20 PM PDT 24 Aug 05 04:54:28 PM PDT 24 755636902 ps
T329 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2524216697 Aug 05 04:54:25 PM PDT 24 Aug 05 04:54:34 PM PDT 24 364907506 ps
T330 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.562571966 Aug 05 04:54:31 PM PDT 24 Aug 05 04:54:46 PM PDT 24 262448365 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1772726870 Aug 05 04:54:04 PM PDT 24 Aug 05 04:55:27 PM PDT 24 1436549639 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2427037765 Aug 05 04:53:58 PM PDT 24 Aug 05 04:54:06 PM PDT 24 183847323 ps
T54 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.561127457 Aug 05 04:54:04 PM PDT 24 Aug 05 04:55:29 PM PDT 24 534915526 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1319619080 Aug 05 04:54:25 PM PDT 24 Aug 05 04:54:35 PM PDT 24 918924719 ps
T331 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3335039639 Aug 05 04:53:52 PM PDT 24 Aug 05 04:54:01 PM PDT 24 688602438 ps
T64 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4163067378 Aug 05 04:54:07 PM PDT 24 Aug 05 04:54:15 PM PDT 24 689473280 ps
T55 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.175299246 Aug 05 04:54:07 PM PDT 24 Aug 05 04:55:29 PM PDT 24 1193351709 ps
T65 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.648441159 Aug 05 04:54:30 PM PDT 24 Aug 05 04:55:08 PM PDT 24 2540265502 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1995382452 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:27 PM PDT 24 276037438 ps
T332 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.613983612 Aug 05 04:54:00 PM PDT 24 Aug 05 04:54:08 PM PDT 24 169399906 ps
T90 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2408388268 Aug 05 04:54:20 PM PDT 24 Aug 05 04:54:32 PM PDT 24 2463475997 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2289819844 Aug 05 04:53:54 PM PDT 24 Aug 05 04:54:03 PM PDT 24 169606018 ps
T333 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2788446316 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:27 PM PDT 24 316244339 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.925469236 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:21 PM PDT 24 266948079 ps
T334 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3573432237 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:17 PM PDT 24 169798054 ps
T335 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1310594397 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:19 PM PDT 24 721790939 ps
T336 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1902388443 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:27 PM PDT 24 259850168 ps
T67 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2882031456 Aug 05 04:54:08 PM PDT 24 Aug 05 04:54:16 PM PDT 24 660827781 ps
T337 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3537782604 Aug 05 04:53:59 PM PDT 24 Aug 05 04:54:10 PM PDT 24 1080671755 ps
T338 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3891877841 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:22 PM PDT 24 735294435 ps
T339 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4262536991 Aug 05 04:54:14 PM PDT 24 Aug 05 04:54:28 PM PDT 24 961093247 ps
T340 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1058526981 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:16 PM PDT 24 533983442 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.760775461 Aug 05 04:54:01 PM PDT 24 Aug 05 04:54:19 PM PDT 24 511203525 ps
T341 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.962776189 Aug 05 04:54:32 PM PDT 24 Aug 05 04:54:45 PM PDT 24 1029212913 ps
T342 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3054312949 Aug 05 04:54:09 PM PDT 24 Aug 05 04:54:21 PM PDT 24 339551068 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3773621872 Aug 05 04:54:26 PM PDT 24 Aug 05 04:56:59 PM PDT 24 650861918 ps
T343 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2172699827 Aug 05 04:54:26 PM PDT 24 Aug 05 04:54:35 PM PDT 24 367400545 ps
T344 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2047082716 Aug 05 04:54:15 PM PDT 24 Aug 05 04:54:25 PM PDT 24 1033758744 ps
T345 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3928253910 Aug 05 04:54:29 PM PDT 24 Aug 05 04:54:42 PM PDT 24 255184723 ps
T346 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1795514859 Aug 05 04:53:59 PM PDT 24 Aug 05 04:54:09 PM PDT 24 495790801 ps
T99 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3102816205 Aug 05 04:54:20 PM PDT 24 Aug 05 04:55:40 PM PDT 24 1401053189 ps
T347 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2847453842 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:57 PM PDT 24 1029886584 ps
T348 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3494072898 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:13 PM PDT 24 1178893023 ps
T349 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.871457469 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:14 PM PDT 24 281474792 ps
T350 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2027212861 Aug 05 04:54:24 PM PDT 24 Aug 05 04:55:43 PM PDT 24 1714360895 ps
T351 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3002485447 Aug 05 04:53:59 PM PDT 24 Aug 05 04:54:12 PM PDT 24 505548461 ps
T78 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1751060132 Aug 05 04:54:28 PM PDT 24 Aug 05 04:54:38 PM PDT 24 260555225 ps
T352 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1278152686 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:23 PM PDT 24 988690434 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3079362273 Aug 05 04:54:03 PM PDT 24 Aug 05 04:56:38 PM PDT 24 1628951852 ps
T353 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3496578827 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:21 PM PDT 24 1081212032 ps
T354 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.66082086 Aug 05 04:54:09 PM PDT 24 Aug 05 04:54:21 PM PDT 24 180332405 ps
T355 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3368844148 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:24 PM PDT 24 180639090 ps
T356 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2695141251 Aug 05 04:54:36 PM PDT 24 Aug 05 04:54:55 PM PDT 24 6124486512 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.9249053 Aug 05 04:53:58 PM PDT 24 Aug 05 04:56:32 PM PDT 24 1457994971 ps
T79 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.993407072 Aug 05 04:54:15 PM PDT 24 Aug 05 04:54:25 PM PDT 24 497275357 ps
T357 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1269299474 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:11 PM PDT 24 660837681 ps
T80 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.129681770 Aug 05 04:54:38 PM PDT 24 Aug 05 04:54:47 PM PDT 24 660226960 ps
T358 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3703714404 Aug 05 04:54:14 PM PDT 24 Aug 05 04:54:24 PM PDT 24 260092471 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2598640226 Aug 05 04:54:07 PM PDT 24 Aug 05 04:54:18 PM PDT 24 2367302837 ps
T360 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3340042974 Aug 05 04:54:16 PM PDT 24 Aug 05 04:54:30 PM PDT 24 787088830 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3012016517 Aug 05 04:53:57 PM PDT 24 Aug 05 04:54:11 PM PDT 24 499142423 ps
T361 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.786582043 Aug 05 04:54:09 PM PDT 24 Aug 05 04:54:20 PM PDT 24 1112565953 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.744899500 Aug 05 04:53:58 PM PDT 24 Aug 05 04:54:08 PM PDT 24 519737480 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4270764393 Aug 05 04:54:22 PM PDT 24 Aug 05 04:54:31 PM PDT 24 701741064 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.625658187 Aug 05 04:54:23 PM PDT 24 Aug 05 04:55:47 PM PDT 24 678995381 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1169808328 Aug 05 04:54:02 PM PDT 24 Aug 05 04:54:12 PM PDT 24 991695142 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1654754965 Aug 05 04:54:06 PM PDT 24 Aug 05 04:54:15 PM PDT 24 260758019 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1450615895 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:30 PM PDT 24 167414719 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3853936284 Aug 05 04:54:07 PM PDT 24 Aug 05 04:54:15 PM PDT 24 1499885058 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3958530263 Aug 05 04:54:02 PM PDT 24 Aug 05 04:54:16 PM PDT 24 1457994851 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3007571741 Aug 05 04:54:08 PM PDT 24 Aug 05 04:54:22 PM PDT 24 1108277775 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3166733844 Aug 05 04:54:24 PM PDT 24 Aug 05 04:56:59 PM PDT 24 384708343 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2626044446 Aug 05 04:54:07 PM PDT 24 Aug 05 04:54:17 PM PDT 24 498486040 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4004081746 Aug 05 04:54:32 PM PDT 24 Aug 05 04:54:43 PM PDT 24 987678753 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1939009357 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:20 PM PDT 24 376929904 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4038801697 Aug 05 04:54:17 PM PDT 24 Aug 05 04:56:50 PM PDT 24 318112692 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1686916813 Aug 05 04:53:54 PM PDT 24 Aug 05 04:54:03 PM PDT 24 691084503 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.695663771 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:24 PM PDT 24 1055908067 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1902410576 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:27 PM PDT 24 2858913407 ps
T375 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2179013742 Aug 05 04:54:10 PM PDT 24 Aug 05 04:54:20 PM PDT 24 1181717035 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1027586164 Aug 05 04:54:15 PM PDT 24 Aug 05 04:56:51 PM PDT 24 1666618023 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.395202683 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:12 PM PDT 24 174820665 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.278709676 Aug 05 04:54:05 PM PDT 24 Aug 05 04:55:27 PM PDT 24 2487460740 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3998153008 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:23 PM PDT 24 265722104 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3032818913 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:24 PM PDT 24 688233881 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2591239128 Aug 05 04:54:18 PM PDT 24 Aug 05 04:54:27 PM PDT 24 1998761631 ps
T380 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.803608822 Aug 05 04:54:23 PM PDT 24 Aug 05 04:54:34 PM PDT 24 700705023 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4141257500 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:14 PM PDT 24 255290121 ps
T104 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1963012466 Aug 05 04:54:06 PM PDT 24 Aug 05 04:56:43 PM PDT 24 2934601024 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2678017454 Aug 05 04:54:23 PM PDT 24 Aug 05 04:54:31 PM PDT 24 351937905 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.942616193 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:15 PM PDT 24 495542377 ps
T384 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.546259737 Aug 05 04:54:01 PM PDT 24 Aug 05 04:54:14 PM PDT 24 170930586 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3423297960 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:13 PM PDT 24 1025512965 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.212223303 Aug 05 04:54:03 PM PDT 24 Aug 05 04:54:16 PM PDT 24 1122771329 ps
T101 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.587623241 Aug 05 04:54:13 PM PDT 24 Aug 05 04:56:47 PM PDT 24 4258631668 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2716355768 Aug 05 04:54:27 PM PDT 24 Aug 05 04:55:49 PM PDT 24 866852976 ps
T388 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2317252863 Aug 05 04:54:17 PM PDT 24 Aug 05 04:54:27 PM PDT 24 261185362 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.180828528 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:22 PM PDT 24 700848119 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3406943531 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:27 PM PDT 24 261265355 ps
T102 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2893656485 Aug 05 04:54:00 PM PDT 24 Aug 05 04:56:38 PM PDT 24 419401111 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2534958260 Aug 05 04:54:31 PM PDT 24 Aug 05 04:54:39 PM PDT 24 338809306 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2001558863 Aug 05 04:54:11 PM PDT 24 Aug 05 04:54:21 PM PDT 24 3548676510 ps
T84 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.383792384 Aug 05 04:54:27 PM PDT 24 Aug 05 04:54:42 PM PDT 24 995553892 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1597216560 Aug 05 04:54:19 PM PDT 24 Aug 05 04:54:28 PM PDT 24 338730403 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3153527297 Aug 05 04:54:01 PM PDT 24 Aug 05 04:54:15 PM PDT 24 1246905455 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3128575553 Aug 05 04:54:12 PM PDT 24 Aug 05 04:54:26 PM PDT 24 1010922190 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1948346101 Aug 05 04:54:01 PM PDT 24 Aug 05 04:54:18 PM PDT 24 170945844 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2654630161 Aug 05 04:54:15 PM PDT 24 Aug 05 04:54:27 PM PDT 24 319728180 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.487418866 Aug 05 04:54:09 PM PDT 24 Aug 05 04:54:17 PM PDT 24 661432022 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1153219746 Aug 05 04:54:03 PM PDT 24 Aug 05 04:55:28 PM PDT 24 372458966 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2335871926 Aug 05 04:54:12 PM PDT 24 Aug 05 04:54:21 PM PDT 24 652048359 ps
T85 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1632640800 Aug 05 04:54:01 PM PDT 24 Aug 05 04:54:18 PM PDT 24 1478209931 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3672734649 Aug 05 04:54:09 PM PDT 24 Aug 05 04:55:31 PM PDT 24 992245225 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.962646914 Aug 05 04:54:14 PM PDT 24 Aug 05 04:54:24 PM PDT 24 506078358 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2986146976 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:16 PM PDT 24 262065043 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1935631112 Aug 05 04:54:05 PM PDT 24 Aug 05 04:54:15 PM PDT 24 261775827 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.707170598 Aug 05 04:54:13 PM PDT 24 Aug 05 04:54:22 PM PDT 24 2761292902 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1362513180 Aug 05 04:54:21 PM PDT 24 Aug 05 04:55:45 PM PDT 24 358073328 ps
T405 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1383123314 Aug 05 04:54:24 PM PDT 24 Aug 05 04:54:33 PM PDT 24 688059573 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.659106916 Aug 05 04:54:10 PM PDT 24 Aug 05 04:54:18 PM PDT 24 167728944 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3298398988 Aug 05 04:53:57 PM PDT 24 Aug 05 04:54:05 PM PDT 24 338937954 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1879366794 Aug 05 04:54:20 PM PDT 24 Aug 05 04:54:30 PM PDT 24 915170417 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2417841373 Aug 05 04:53:57 PM PDT 24 Aug 05 04:54:08 PM PDT 24 4232877887 ps

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1634176334
Short name T8
Test name
Test status
Simulation time 106311116532 ps
CPU time 967.04 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 05:09:47 PM PDT 24
Peak memory 237164 kb
Host smart-9d42455f-4574-4652-8f3d-369d6c819c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634176334 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1634176334
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3658920406
Short name T10
Test name
Test status
Simulation time 17986169257 ps
CPU time 236.58 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:57:37 PM PDT 24
Peak memory 226116 kb
Host smart-9c52bc27-9615-495e-88fe-080e9223395c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658920406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3658920406
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3242418489
Short name T43
Test name
Test status
Simulation time 2337706050 ps
CPU time 154 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:56:09 PM PDT 24
Peak memory 237416 kb
Host smart-2d5fd535-3c7e-402d-bea5-5f45e6d36c61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242418489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3242418489
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.561127457
Short name T54
Test name
Test status
Simulation time 534915526 ps
CPU time 85.21 seconds
Started Aug 05 04:54:04 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 215144 kb
Host smart-92fa86c2-2812-45d4-aef2-0dcd6f585668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561127457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.561127457
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1425186669
Short name T22
Test name
Test status
Simulation time 604087475 ps
CPU time 229.03 seconds
Started Aug 05 04:53:31 PM PDT 24
Finished Aug 05 04:57:21 PM PDT 24
Peak memory 235740 kb
Host smart-2e8bf924-ecd7-4cec-8d66-cfaa791193a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425186669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1425186669
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1027586164
Short name T108
Test name
Test status
Simulation time 1666618023 ps
CPU time 155.69 seconds
Started Aug 05 04:54:15 PM PDT 24
Finished Aug 05 04:56:51 PM PDT 24
Peak memory 213304 kb
Host smart-83e8ba23-2fc6-4315-9dda-5ded408cee3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027586164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1027586164
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.207383407
Short name T24
Test name
Test status
Simulation time 169347535 ps
CPU time 8.6 seconds
Started Aug 05 04:53:32 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 219044 kb
Host smart-18281fab-11b3-4fe8-b63f-7084575521f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207383407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.207383407
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1552743336
Short name T63
Test name
Test status
Simulation time 698615834 ps
CPU time 38.34 seconds
Started Aug 05 04:54:17 PM PDT 24
Finished Aug 05 04:54:56 PM PDT 24
Peak memory 213948 kb
Host smart-2d1df5bb-c1e0-4d84-af37-12676cd2ff3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552743336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1552743336
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2337648021
Short name T69
Test name
Test status
Simulation time 7943010206 ps
CPU time 46.53 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 220136 kb
Host smart-b1414abc-9d22-4560-af49-31fbc8e3b346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337648021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2337648021
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.134736837
Short name T4
Test name
Test status
Simulation time 2148698689 ps
CPU time 22.03 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 220124 kb
Host smart-e25bf43a-778a-42f0-a63a-dddc91a37fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134736837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.134736837
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1963012466
Short name T104
Test name
Test status
Simulation time 2934601024 ps
CPU time 156.88 seconds
Started Aug 05 04:54:06 PM PDT 24
Finished Aug 05 04:56:43 PM PDT 24
Peak memory 214388 kb
Host smart-667df26b-036b-462e-bad7-a2699a9a4225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963012466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1963012466
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2382536719
Short name T41
Test name
Test status
Simulation time 894197736 ps
CPU time 19.22 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:55 PM PDT 24
Peak memory 219984 kb
Host smart-2e683c55-e543-436f-955c-1f533f0556db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382536719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2382536719
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4244683172
Short name T51
Test name
Test status
Simulation time 28694961587 ps
CPU time 1045.99 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 05:11:31 PM PDT 24
Peak memory 236512 kb
Host smart-61aa60c4-e337-4530-88c2-82f72770e32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244683172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4244683172
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1486575419
Short name T11
Test name
Test status
Simulation time 528273865 ps
CPU time 12.53 seconds
Started Aug 05 04:53:21 PM PDT 24
Finished Aug 05 04:53:34 PM PDT 24
Peak memory 219972 kb
Host smart-f1781422-c35a-425a-9f97-b8f544526a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486575419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1486575419
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3853936284
Short name T82
Test name
Test status
Simulation time 1499885058 ps
CPU time 8.16 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 210820 kb
Host smart-3ef8fea6-58cf-4c7a-94e2-4d4cc16c5dd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853936284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3853936284
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2289819844
Short name T91
Test name
Test status
Simulation time 169606018 ps
CPU time 8.52 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 211584 kb
Host smart-999f6dcf-8cd1-4257-862f-a17ef82a6093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289819844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2289819844
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2427037765
Short name T93
Test name
Test status
Simulation time 183847323 ps
CPU time 8.63 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 210792 kb
Host smart-9812b322-d272-4cba-b590-378a0df8ec76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427037765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2427037765
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3298398988
Short name T407
Test name
Test status
Simulation time 338937954 ps
CPU time 8.18 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:05 PM PDT 24
Peak memory 210968 kb
Host smart-2028a1e9-b5da-4a38-b4f7-94e6f59af45a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298398988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3298398988
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.760775461
Short name T77
Test name
Test status
Simulation time 511203525 ps
CPU time 17.18 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:19 PM PDT 24
Peak memory 211772 kb
Host smart-b68b9fb9-1b80-40d3-bd8f-4fab8528f951
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760775461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.760775461
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3496578827
Short name T353
Test name
Test status
Simulation time 1081212032 ps
CPU time 10.5 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 216216 kb
Host smart-a20e6979-b4ca-4346-a3bf-d269d7e34e19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496578827 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3496578827
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.659106916
Short name T406
Test name
Test status
Simulation time 167728944 ps
CPU time 8.43 seconds
Started Aug 05 04:54:10 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 210964 kb
Host smart-68c74b67-ef09-4ec5-bef9-bfa07aa30689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659106916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.659106916
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1084532316
Short name T327
Test name
Test status
Simulation time 376282653 ps
CPU time 9.79 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:05 PM PDT 24
Peak memory 210728 kb
Host smart-4e7effb5-2249-4a1a-aef4-ba39de8ac88a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084532316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1084532316
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3335039639
Short name T331
Test name
Test status
Simulation time 688602438 ps
CPU time 8.23 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 210840 kb
Host smart-c950933d-8b8e-4ba9-aad4-f46f1bac3a60
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335039639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3335039639
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3002485447
Short name T351
Test name
Test status
Simulation time 505548461 ps
CPU time 13.28 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 219400 kb
Host smart-e7bc832d-5b93-42d9-a32a-2ff32986ef82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002485447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3002485447
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.9249053
Short name T107
Test name
Test status
Simulation time 1457994971 ps
CPU time 154.01 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:56:32 PM PDT 24
Peak memory 214180 kb
Host smart-71443dad-f805-4684-ad9f-19911505ac6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9249053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_
err.9249053
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.871457469
Short name T349
Test name
Test status
Simulation time 281474792 ps
CPU time 8.7 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:14 PM PDT 24
Peak memory 210848 kb
Host smart-fffb42f1-40d8-4ebb-8f04-fd43391e63be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871457469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.871457469
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.445033249
Short name T57
Test name
Test status
Simulation time 754301666 ps
CPU time 13.54 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 210704 kb
Host smart-31c76f9f-45cc-4414-b765-30c73619b255
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445033249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.445033249
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2986146976
Short name T402
Test name
Test status
Simulation time 262065043 ps
CPU time 11.44 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 217800 kb
Host smart-7c5768cd-f2b4-47d2-ab22-ea626ccf3157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986146976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2986146976
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3494072898
Short name T348
Test name
Test status
Simulation time 1178893023 ps
CPU time 9.84 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 210904 kb
Host smart-afd5b0e1-c7ae-4dad-a627-03ad4151a409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494072898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3494072898
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2001558863
Short name T391
Test name
Test status
Simulation time 3548676510 ps
CPU time 9.66 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 210780 kb
Host smart-659c3d70-f215-465e-85a9-75f9aa1088dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001558863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2001558863
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3563822437
Short name T326
Test name
Test status
Simulation time 172487920 ps
CPU time 8.4 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 210716 kb
Host smart-51b9cc55-3fe5-444f-a0d8-24a5b05571cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563822437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3563822437
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1460914223
Short name T60
Test name
Test status
Simulation time 695535841 ps
CPU time 38 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:49 PM PDT 24
Peak memory 219192 kb
Host smart-6b85586b-8fa6-40e9-9962-00342e9148db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460914223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1460914223
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1169808328
Short name T364
Test name
Test status
Simulation time 991695142 ps
CPU time 9.87 seconds
Started Aug 05 04:54:02 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 211244 kb
Host smart-2220719b-14a1-479e-b063-aa44c997ef63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169808328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1169808328
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3958530263
Short name T367
Test name
Test status
Simulation time 1457994851 ps
CPU time 13.38 seconds
Started Aug 05 04:54:02 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 217680 kb
Host smart-c5a5e1c6-3dfd-4fd1-a422-b24964969951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958530263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3958530263
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1153219746
Short name T398
Test name
Test status
Simulation time 372458966 ps
CPU time 84.97 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:55:28 PM PDT 24
Peak memory 214084 kb
Host smart-e4a3aacf-0806-483b-a4b7-2c9f16781e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153219746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1153219746
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.180828528
Short name T389
Test name
Test status
Simulation time 700848119 ps
CPU time 8.27 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 215996 kb
Host smart-8c8ecb70-b296-4383-b3ff-a7bcfd78147a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180828528 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.180828528
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3128575553
Short name T394
Test name
Test status
Simulation time 1010922190 ps
CPU time 14.36 seconds
Started Aug 05 04:54:12 PM PDT 24
Finished Aug 05 04:54:26 PM PDT 24
Peak memory 211580 kb
Host smart-689c1cce-23f8-4347-8c31-7a7ff446c81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128575553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3128575553
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2047082716
Short name T344
Test name
Test status
Simulation time 1033758744 ps
CPU time 9.82 seconds
Started Aug 05 04:54:15 PM PDT 24
Finished Aug 05 04:54:25 PM PDT 24
Peak memory 211564 kb
Host smart-6907858e-c8ad-46c5-94d0-2c3b3cb82a73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047082716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2047082716
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.546259737
Short name T384
Test name
Test status
Simulation time 170930586 ps
CPU time 12.76 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:14 PM PDT 24
Peak memory 217628 kb
Host smart-fe01382b-ed85-47d0-9c24-64fe442ffedf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546259737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.546259737
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4270764393
Short name T363
Test name
Test status
Simulation time 701741064 ps
CPU time 8.79 seconds
Started Aug 05 04:54:22 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 216572 kb
Host smart-fc646ff8-8b64-454b-9c44-83adefa939e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270764393 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4270764393
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.925469236
Short name T66
Test name
Test status
Simulation time 266948079 ps
CPU time 9.73 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 211120 kb
Host smart-0621e4f8-0617-4f50-98ca-7583d70d2aea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925469236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.925469236
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3007571741
Short name T368
Test name
Test status
Simulation time 1108277775 ps
CPU time 13.96 seconds
Started Aug 05 04:54:08 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 212804 kb
Host smart-0e9bc0eb-c4e6-4361-82cb-390a1f854db3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007571741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3007571741
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.962776189
Short name T341
Test name
Test status
Simulation time 1029212913 ps
CPU time 12.71 seconds
Started Aug 05 04:54:32 PM PDT 24
Finished Aug 05 04:54:45 PM PDT 24
Peak memory 219176 kb
Host smart-7f782c04-5991-4b5d-862d-8b6d8daaa226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962776189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.962776189
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1362513180
Short name T404
Test name
Test status
Simulation time 358073328 ps
CPU time 82.95 seconds
Started Aug 05 04:54:21 PM PDT 24
Finished Aug 05 04:55:45 PM PDT 24
Peak memory 214268 kb
Host smart-b546b1bf-2cc5-4a52-a285-2aeb560cb669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362513180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1362513180
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.695663771
Short name T373
Test name
Test status
Simulation time 1055908067 ps
CPU time 10.58 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 216840 kb
Host smart-80ec912a-6b1a-4e0f-8fad-64cc28005823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695663771 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.695663771
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.487418866
Short name T397
Test name
Test status
Simulation time 661432022 ps
CPU time 8.25 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 04:54:17 PM PDT 24
Peak memory 211208 kb
Host smart-fb2a145f-2a0e-41ea-bea2-3da70dbf4591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487418866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.487418866
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1995382452
Short name T89
Test name
Test status
Simulation time 276037438 ps
CPU time 14.03 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 212664 kb
Host smart-48e1db93-d84a-494b-87af-f5c8a6795dcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995382452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1995382452
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3032818913
Short name T378
Test name
Test status
Simulation time 688233881 ps
CPU time 11.3 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 219176 kb
Host smart-5b28b0da-8e46-4369-bf3e-afa5ebb1d88e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032818913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3032818913
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.587623241
Short name T101
Test name
Test status
Simulation time 4258631668 ps
CPU time 154.52 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:56:47 PM PDT 24
Peak memory 214608 kb
Host smart-60ff447b-2b8b-4f40-91e5-b973c0e5451f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587623241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.587623241
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3998153008
Short name T377
Test name
Test status
Simulation time 265722104 ps
CPU time 10.48 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:23 PM PDT 24
Peak memory 216272 kb
Host smart-d47397e1-4f3f-4c09-beb7-ff3e41258c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998153008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3998153008
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1383123314
Short name T405
Test name
Test status
Simulation time 688059573 ps
CPU time 8.33 seconds
Started Aug 05 04:54:24 PM PDT 24
Finished Aug 05 04:54:33 PM PDT 24
Peak memory 210792 kb
Host smart-bc21b8a8-edfb-48fc-87c1-310c576ee08f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383123314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1383123314
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4262536991
Short name T339
Test name
Test status
Simulation time 961093247 ps
CPU time 13.24 seconds
Started Aug 05 04:54:14 PM PDT 24
Finished Aug 05 04:54:28 PM PDT 24
Peak memory 212784 kb
Host smart-1d6dad3c-b823-4567-a6f2-289b75450a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262536991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4262536991
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3340042974
Short name T360
Test name
Test status
Simulation time 787088830 ps
CPU time 13.65 seconds
Started Aug 05 04:54:16 PM PDT 24
Finished Aug 05 04:54:30 PM PDT 24
Peak memory 219212 kb
Host smart-c1444e64-995c-4ac0-b535-6aa1876e9ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340042974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3340042974
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3102816205
Short name T99
Test name
Test status
Simulation time 1401053189 ps
CPU time 80.71 seconds
Started Aug 05 04:54:20 PM PDT 24
Finished Aug 05 04:55:40 PM PDT 24
Peak memory 213856 kb
Host smart-7f499324-c9bb-4d75-ad66-e872b38c0dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102816205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3102816205
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2524216697
Short name T329
Test name
Test status
Simulation time 364907506 ps
CPU time 8.69 seconds
Started Aug 05 04:54:25 PM PDT 24
Finished Aug 05 04:54:34 PM PDT 24
Peak memory 215980 kb
Host smart-195f6dde-1a13-4d2d-940e-31f76c4ff8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524216697 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2524216697
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.383792384
Short name T84
Test name
Test status
Simulation time 995553892 ps
CPU time 15.07 seconds
Started Aug 05 04:54:27 PM PDT 24
Finished Aug 05 04:54:42 PM PDT 24
Peak memory 211052 kb
Host smart-5a5a7deb-4b8d-4074-9c7d-b1ffe5de768f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383792384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.383792384
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2317252863
Short name T388
Test name
Test status
Simulation time 261185362 ps
CPU time 9.61 seconds
Started Aug 05 04:54:17 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 211416 kb
Host smart-a9b928e9-e1fc-4a41-98d2-4c52d8318a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317252863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2317252863
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1902388443
Short name T336
Test name
Test status
Simulation time 259850168 ps
CPU time 13.1 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 219200 kb
Host smart-988a707b-3c13-4b51-b825-0c4136b9dcfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902388443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1902388443
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2027212861
Short name T350
Test name
Test status
Simulation time 1714360895 ps
CPU time 78.88 seconds
Started Aug 05 04:54:24 PM PDT 24
Finished Aug 05 04:55:43 PM PDT 24
Peak memory 214004 kb
Host smart-eb566674-57b5-4c79-8295-449767e6dd38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027212861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2027212861
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2591239128
Short name T379
Test name
Test status
Simulation time 1998761631 ps
CPU time 8.94 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 217036 kb
Host smart-b2891191-eaab-4f1b-9fbf-464f629575f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591239128 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2591239128
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2306591479
Short name T61
Test name
Test status
Simulation time 662557979 ps
CPU time 8.34 seconds
Started Aug 05 04:54:21 PM PDT 24
Finished Aug 05 04:54:29 PM PDT 24
Peak memory 211048 kb
Host smart-214fdac3-51e3-4a1a-94b6-99f62b62e76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306591479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2306591479
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3703714404
Short name T358
Test name
Test status
Simulation time 260092471 ps
CPU time 9.68 seconds
Started Aug 05 04:54:14 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 211668 kb
Host smart-14b082c8-f957-498c-b28d-d57fb3655be5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703714404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3703714404
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2654630161
Short name T396
Test name
Test status
Simulation time 319728180 ps
CPU time 11.55 seconds
Started Aug 05 04:54:15 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 216400 kb
Host smart-022392f7-0e61-4eea-a5a9-ae4ec41e0376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654630161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2654630161
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2788446316
Short name T333
Test name
Test status
Simulation time 316244339 ps
CPU time 8.72 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 216400 kb
Host smart-4dbf8bc5-92a8-483a-b185-6a41adbc56a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788446316 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2788446316
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1879366794
Short name T408
Test name
Test status
Simulation time 915170417 ps
CPU time 9.94 seconds
Started Aug 05 04:54:20 PM PDT 24
Finished Aug 05 04:54:30 PM PDT 24
Peak memory 211016 kb
Host smart-22b12720-5347-4f4c-904b-b58ba13f3c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879366794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1879366794
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1319619080
Short name T88
Test name
Test status
Simulation time 918924719 ps
CPU time 10.07 seconds
Started Aug 05 04:54:25 PM PDT 24
Finished Aug 05 04:54:35 PM PDT 24
Peak memory 211348 kb
Host smart-8efb8807-b6d3-410a-a170-e98d28bd3c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319619080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1319619080
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.562571966
Short name T330
Test name
Test status
Simulation time 262448365 ps
CPU time 14.69 seconds
Started Aug 05 04:54:31 PM PDT 24
Finished Aug 05 04:54:46 PM PDT 24
Peak memory 216748 kb
Host smart-e1198429-e2ce-4e7f-ad36-825c3044fd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562571966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.562571966
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4038801697
Short name T105
Test name
Test status
Simulation time 318112692 ps
CPU time 152.42 seconds
Started Aug 05 04:54:17 PM PDT 24
Finished Aug 05 04:56:50 PM PDT 24
Peak memory 215460 kb
Host smart-8c0c2605-16c1-4cac-a2a8-2f0c5c9f47da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038801697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4038801697
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.803608822
Short name T380
Test name
Test status
Simulation time 700705023 ps
CPU time 11.13 seconds
Started Aug 05 04:54:23 PM PDT 24
Finished Aug 05 04:54:34 PM PDT 24
Peak memory 217208 kb
Host smart-2a50b66f-7e61-422e-b979-c31812b3a31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803608822 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.803608822
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1751060132
Short name T78
Test name
Test status
Simulation time 260555225 ps
CPU time 9.92 seconds
Started Aug 05 04:54:28 PM PDT 24
Finished Aug 05 04:54:38 PM PDT 24
Peak memory 210796 kb
Host smart-2faa9754-65f9-4484-b132-971403d5037e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751060132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1751060132
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.648441159
Short name T65
Test name
Test status
Simulation time 2540265502 ps
CPU time 37.78 seconds
Started Aug 05 04:54:30 PM PDT 24
Finished Aug 05 04:55:08 PM PDT 24
Peak memory 212200 kb
Host smart-e84f7ec6-10f1-4b5f-a4ce-e6d55465487e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648441159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.648441159
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1217633045
Short name T62
Test name
Test status
Simulation time 259888260 ps
CPU time 14.09 seconds
Started Aug 05 04:54:32 PM PDT 24
Finished Aug 05 04:54:46 PM PDT 24
Peak memory 212764 kb
Host smart-101ddfd6-d67a-466b-a879-6e1cac8769b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217633045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1217633045
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2695141251
Short name T356
Test name
Test status
Simulation time 6124486512 ps
CPU time 19.06 seconds
Started Aug 05 04:54:36 PM PDT 24
Finished Aug 05 04:54:55 PM PDT 24
Peak memory 219192 kb
Host smart-1d2b7de5-107a-4059-87d3-76a21d64b94c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695141251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2695141251
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3166733844
Short name T110
Test name
Test status
Simulation time 384708343 ps
CPU time 155.06 seconds
Started Aug 05 04:54:24 PM PDT 24
Finished Aug 05 04:56:59 PM PDT 24
Peak memory 214288 kb
Host smart-cdeb797f-a49f-427e-b406-640e6b523bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166733844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3166733844
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2172699827
Short name T343
Test name
Test status
Simulation time 367400545 ps
CPU time 8.76 seconds
Started Aug 05 04:54:26 PM PDT 24
Finished Aug 05 04:54:35 PM PDT 24
Peak memory 216384 kb
Host smart-b3dccd9b-e798-4b1c-aefc-8f9d1bdedb21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172699827 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2172699827
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.129681770
Short name T80
Test name
Test status
Simulation time 660226960 ps
CPU time 8.34 seconds
Started Aug 05 04:54:38 PM PDT 24
Finished Aug 05 04:54:47 PM PDT 24
Peak memory 211464 kb
Host smart-622f20c6-d17a-461b-831b-4d9afd5e7751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129681770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.129681770
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2408388268
Short name T90
Test name
Test status
Simulation time 2463475997 ps
CPU time 12.08 seconds
Started Aug 05 04:54:20 PM PDT 24
Finished Aug 05 04:54:32 PM PDT 24
Peak memory 212936 kb
Host smart-a714a98c-c427-45b4-b6f3-684ebc5bd454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408388268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2408388268
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1450615895
Short name T366
Test name
Test status
Simulation time 167414719 ps
CPU time 11.28 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:30 PM PDT 24
Peak memory 217608 kb
Host smart-a3918d63-fd81-4862-b460-fd2a9de51c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450615895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1450615895
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3773621872
Short name T103
Test name
Test status
Simulation time 650861918 ps
CPU time 152.26 seconds
Started Aug 05 04:54:26 PM PDT 24
Finished Aug 05 04:56:59 PM PDT 24
Peak memory 214396 kb
Host smart-06c3a261-f5d7-4be0-a2dd-a656220c2c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773621872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3773621872
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2678017454
Short name T382
Test name
Test status
Simulation time 351937905 ps
CPU time 8.8 seconds
Started Aug 05 04:54:23 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 219104 kb
Host smart-8897e0ef-e3f1-4432-aa49-941851336703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678017454 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2678017454
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2534958260
Short name T83
Test name
Test status
Simulation time 338809306 ps
CPU time 8.43 seconds
Started Aug 05 04:54:31 PM PDT 24
Finished Aug 05 04:54:39 PM PDT 24
Peak memory 210892 kb
Host smart-f1c010c1-9ccb-4975-b4ac-273c25e77f0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534958260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2534958260
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4004081746
Short name T370
Test name
Test status
Simulation time 987678753 ps
CPU time 10.06 seconds
Started Aug 05 04:54:32 PM PDT 24
Finished Aug 05 04:54:43 PM PDT 24
Peak memory 211728 kb
Host smart-ff4aa968-948e-449f-9e7c-8a3bb34743b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004081746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4004081746
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3928253910
Short name T345
Test name
Test status
Simulation time 255184723 ps
CPU time 13.66 seconds
Started Aug 05 04:54:29 PM PDT 24
Finished Aug 05 04:54:42 PM PDT 24
Peak memory 217500 kb
Host smart-e85d7cf8-3765-437c-8572-73b68e85c1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928253910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3928253910
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.625658187
Short name T109
Test name
Test status
Simulation time 678995381 ps
CPU time 83.41 seconds
Started Aug 05 04:54:23 PM PDT 24
Finished Aug 05 04:55:47 PM PDT 24
Peak memory 213096 kb
Host smart-ad47c671-4876-46b9-8021-edf3e84509dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625658187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.625658187
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.613983612
Short name T332
Test name
Test status
Simulation time 169399906 ps
CPU time 8.39 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 210980 kb
Host smart-290a118b-9c8f-40a6-b5eb-5388391dd432
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613983612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.613983612
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1686916813
Short name T372
Test name
Test status
Simulation time 691084503 ps
CPU time 8.81 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 211208 kb
Host smart-0cf40a53-4013-4d90-bac1-9b45f412b386
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686916813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1686916813
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3012016517
Short name T81
Test name
Test status
Simulation time 499142423 ps
CPU time 13.38 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:11 PM PDT 24
Peak memory 210972 kb
Host smart-4a34e5da-5d27-43de-9166-c05a5ef97566
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012016517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3012016517
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2417841373
Short name T409
Test name
Test status
Simulation time 4232877887 ps
CPU time 10.76 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 217464 kb
Host smart-ac29a7f6-ef04-4d0e-996f-fefe19e52356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417841373 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2417841373
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1505110769
Short name T58
Test name
Test status
Simulation time 917064636 ps
CPU time 9.75 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 211252 kb
Host smart-507c6e95-0ab5-4a91-9005-1f5d5a93886a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505110769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1505110769
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1269299474
Short name T357
Test name
Test status
Simulation time 660837681 ps
CPU time 8.07 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:11 PM PDT 24
Peak memory 210620 kb
Host smart-c3daa29e-0851-4291-ac81-66f2963243e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269299474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1269299474
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.744899500
Short name T362
Test name
Test status
Simulation time 519737480 ps
CPU time 10.06 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 210720 kb
Host smart-b36057d6-6cef-44cd-8fe4-f653a642b82e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744899500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
744899500
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1058526981
Short name T340
Test name
Test status
Simulation time 533983442 ps
CPU time 13.31 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 212720 kb
Host smart-ced4b60b-ef78-407f-afcf-f6634d5b619b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058526981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1058526981
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3054312949
Short name T342
Test name
Test status
Simulation time 339551068 ps
CPU time 11.14 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 217264 kb
Host smart-20a20ae5-170a-49a7-acee-abab1adb5629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054312949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3054312949
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3079362273
Short name T100
Test name
Test status
Simulation time 1628951852 ps
CPU time 154.52 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:56:38 PM PDT 24
Peak memory 214240 kb
Host smart-0c4df19e-34ef-4c16-afc5-b47421b040fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079362273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3079362273
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.707170598
Short name T86
Test name
Test status
Simulation time 2761292902 ps
CPU time 8.4 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 211236 kb
Host smart-3de826db-4756-48a2-ab54-6e0336539474
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707170598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.707170598
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1310594397
Short name T335
Test name
Test status
Simulation time 721790939 ps
CPU time 8.69 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:19 PM PDT 24
Peak memory 211112 kb
Host smart-c313626a-171c-41e2-a504-72b7bf8b1e68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310594397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1310594397
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1632640800
Short name T85
Test name
Test status
Simulation time 1478209931 ps
CPU time 17.04 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 212460 kb
Host smart-4c7c1ab1-a322-4078-9874-880e43a8f9fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632640800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1632640800
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2598640226
Short name T359
Test name
Test status
Simulation time 2367302837 ps
CPU time 10.46 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 216360 kb
Host smart-134f62c7-3060-485f-90e0-613fcebce0fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598640226 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2598640226
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1994831874
Short name T56
Test name
Test status
Simulation time 171764172 ps
CPU time 8.25 seconds
Started Aug 05 04:54:30 PM PDT 24
Finished Aug 05 04:54:39 PM PDT 24
Peak memory 210892 kb
Host smart-10a7ad38-0c4b-4c80-a5ca-7700eae4fc4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994831874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1994831874
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1597216560
Short name T392
Test name
Test status
Simulation time 338730403 ps
CPU time 8.24 seconds
Started Aug 05 04:54:19 PM PDT 24
Finished Aug 05 04:54:28 PM PDT 24
Peak memory 211016 kb
Host smart-1fab3891-9ade-49ac-8abd-a593aa02d668
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597216560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1597216560
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1939009357
Short name T371
Test name
Test status
Simulation time 376929904 ps
CPU time 8.29 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 210716 kb
Host smart-6df53c61-9be4-4915-9fbd-ba8aad4a41d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939009357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1939009357
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.66082086
Short name T354
Test name
Test status
Simulation time 180332405 ps
CPU time 11.81 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 212840 kb
Host smart-e9aa969e-579e-4436-a267-b2889d6d8786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66082086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_same_csr_outstanding.66082086
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.212223303
Short name T386
Test name
Test status
Simulation time 1122771329 ps
CPU time 12.9 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 217544 kb
Host smart-54b9b4d4-6410-4119-a700-8528241b5792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212223303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.212223303
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3672734649
Short name T400
Test name
Test status
Simulation time 992245225 ps
CPU time 82 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 04:55:31 PM PDT 24
Peak memory 213688 kb
Host smart-9a1dd350-a61a-4188-ab8d-f8fc11db184e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672734649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3672734649
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.395202683
Short name T376
Test name
Test status
Simulation time 174820665 ps
CPU time 8.24 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 210800 kb
Host smart-0145b458-12cb-4370-87fe-20263dddd1a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395202683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.395202683
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2626044446
Short name T369
Test name
Test status
Simulation time 498486040 ps
CPU time 10.11 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:17 PM PDT 24
Peak memory 210948 kb
Host smart-e1302468-1664-4083-8068-0243e5e39b98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626044446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2626044446
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3153527297
Short name T393
Test name
Test status
Simulation time 1246905455 ps
CPU time 13.23 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 210804 kb
Host smart-f650060d-cd27-4b89-81a7-4c10bbc12015
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153527297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3153527297
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4141257500
Short name T381
Test name
Test status
Simulation time 255290121 ps
CPU time 10.4 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:14 PM PDT 24
Peak memory 214048 kb
Host smart-f1294953-0038-4e92-be08-de5281a58323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141257500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4141257500
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1654754965
Short name T365
Test name
Test status
Simulation time 260758019 ps
CPU time 9.48 seconds
Started Aug 05 04:54:06 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 211084 kb
Host smart-71f3f5f5-b697-4502-9691-ab9560b0b1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654754965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1654754965
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.962646914
Short name T401
Test name
Test status
Simulation time 506078358 ps
CPU time 9.95 seconds
Started Aug 05 04:54:14 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 210780 kb
Host smart-5164444f-af01-40a7-85e4-8651a129688c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962646914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.962646914
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3423297960
Short name T385
Test name
Test status
Simulation time 1025512965 ps
CPU time 9.69 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 210836 kb
Host smart-474c7a86-883b-43df-923c-b773f16785a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423297960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3423297960
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1795514859
Short name T346
Test name
Test status
Simulation time 495790801 ps
CPU time 9.88 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 211824 kb
Host smart-66c491af-4c9f-4a5b-8acd-2c171414c5e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795514859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1795514859
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1948346101
Short name T395
Test name
Test status
Simulation time 170945844 ps
CPU time 11.76 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 218704 kb
Host smart-95cee473-5610-4f5a-a14d-33cacd31588e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948346101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1948346101
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.175299246
Short name T55
Test name
Test status
Simulation time 1193351709 ps
CPU time 81.75 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 213088 kb
Host smart-9a7d748d-8a50-4e1b-8f3a-2e8c4e9a4df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175299246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.175299246
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3537782604
Short name T337
Test name
Test status
Simulation time 1080671755 ps
CPU time 11.18 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 217648 kb
Host smart-786ba3dd-8f4a-42f1-abb6-fcf86af1137c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537782604 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3537782604
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4163067378
Short name T64
Test name
Test status
Simulation time 689473280 ps
CPU time 8.21 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 211016 kb
Host smart-ceba9922-c3c9-423d-b278-9707ff5e74f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163067378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4163067378
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.942616193
Short name T383
Test name
Test status
Simulation time 495542377 ps
CPU time 10.21 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 211684 kb
Host smart-92b04277-0056-4eec-a2b7-232297d72433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942616193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.942616193
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3406943531
Short name T390
Test name
Test status
Simulation time 261265355 ps
CPU time 13.25 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 217656 kb
Host smart-6a4bc21b-3b33-4aa4-b4b6-2885191e6b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406943531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3406943531
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1902410576
Short name T374
Test name
Test status
Simulation time 2858913407 ps
CPU time 8.49 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:27 PM PDT 24
Peak memory 214888 kb
Host smart-887e64db-3f8e-4bdf-83b2-6eacb95fd496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902410576 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1902410576
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.993407072
Short name T79
Test name
Test status
Simulation time 497275357 ps
CPU time 10.06 seconds
Started Aug 05 04:54:15 PM PDT 24
Finished Aug 05 04:54:25 PM PDT 24
Peak memory 210788 kb
Host smart-821e4743-8acf-4f72-a0a8-8f8d2ee06964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993407072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.993407072
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3368844148
Short name T355
Test name
Test status
Simulation time 180639090 ps
CPU time 12.11 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 212668 kb
Host smart-6c79d1d5-8a76-4e45-b653-0b12370cf859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368844148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3368844148
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3573432237
Short name T334
Test name
Test status
Simulation time 169798054 ps
CPU time 11.93 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:17 PM PDT 24
Peak memory 219208 kb
Host smart-8a805153-cc34-4674-b3c7-53d706b5e905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573432237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3573432237
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2893656485
Short name T102
Test name
Test status
Simulation time 419401111 ps
CPU time 157.76 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:56:38 PM PDT 24
Peak memory 214340 kb
Host smart-9f8376c5-6bcc-4fb9-919a-5399154ceec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893656485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2893656485
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2335871926
Short name T399
Test name
Test status
Simulation time 652048359 ps
CPU time 9.31 seconds
Started Aug 05 04:54:12 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 217928 kb
Host smart-a788272f-fcd8-49bf-9a23-4bc08dde1b16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335871926 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2335871926
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1278152686
Short name T352
Test name
Test status
Simulation time 988690434 ps
CPU time 9.54 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:23 PM PDT 24
Peak memory 211160 kb
Host smart-6502ba52-58f7-4029-ba83-5246ce27ed18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278152686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1278152686
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2291916616
Short name T87
Test name
Test status
Simulation time 177991573 ps
CPU time 8.79 seconds
Started Aug 05 04:54:04 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 212036 kb
Host smart-ab1784fc-3be9-49d3-9203-592f97eb8052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291916616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2291916616
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1852394035
Short name T328
Test name
Test status
Simulation time 972619384 ps
CPU time 12.13 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 217708 kb
Host smart-6e8d0396-b121-44fe-a0ec-a199cd0e5c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852394035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1852394035
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2716355768
Short name T387
Test name
Test status
Simulation time 866852976 ps
CPU time 81.61 seconds
Started Aug 05 04:54:27 PM PDT 24
Finished Aug 05 04:55:49 PM PDT 24
Peak memory 213132 kb
Host smart-2258d4bb-de1e-479d-9d61-48891a945cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716355768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2716355768
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3891877841
Short name T338
Test name
Test status
Simulation time 735294435 ps
CPU time 9.27 seconds
Started Aug 05 04:54:13 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 219176 kb
Host smart-07687fba-1773-4cda-8a20-86dde2a98419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891877841 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3891877841
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2882031456
Short name T67
Test name
Test status
Simulation time 660827781 ps
CPU time 8.43 seconds
Started Aug 05 04:54:08 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 210900 kb
Host smart-75610282-5e81-4e99-b64e-ac61127188ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882031456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2882031456
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2847453842
Short name T347
Test name
Test status
Simulation time 1029886584 ps
CPU time 45.08 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:57 PM PDT 24
Peak memory 215024 kb
Host smart-89a055c0-427a-4047-8104-451cc3eab369
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847453842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2847453842
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2179013742
Short name T375
Test name
Test status
Simulation time 1181717035 ps
CPU time 9.84 seconds
Started Aug 05 04:54:10 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 211632 kb
Host smart-ab50fd9f-b996-47f0-943a-4d61c2a27263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179013742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2179013742
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2737716717
Short name T324
Test name
Test status
Simulation time 1377179391 ps
CPU time 12.96 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 217660 kb
Host smart-d6dac13d-3382-4ce2-978e-db89792e4028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737716717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2737716717
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.278709676
Short name T106
Test name
Test status
Simulation time 2487460740 ps
CPU time 81.75 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:55:27 PM PDT 24
Peak memory 213064 kb
Host smart-641589b2-7dd6-4b69-8045-98cab7b0dd87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278709676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.278709676
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.786582043
Short name T361
Test name
Test status
Simulation time 1112565953 ps
CPU time 10.52 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 216212 kb
Host smart-3af9c09c-e807-45c7-85cb-33231fdf7c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786582043 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.786582043
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.57445366
Short name T92
Test name
Test status
Simulation time 755636902 ps
CPU time 8.22 seconds
Started Aug 05 04:54:20 PM PDT 24
Finished Aug 05 04:54:28 PM PDT 24
Peak memory 210960 kb
Host smart-33d45199-f85c-4b5b-b511-52ae22250535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57445366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.57445366
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1935631112
Short name T403
Test name
Test status
Simulation time 261775827 ps
CPU time 10.2 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 211608 kb
Host smart-616f3ffb-dbf3-47c7-8c80-e3163c10232a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935631112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1935631112
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4277368242
Short name T325
Test name
Test status
Simulation time 1373434832 ps
CPU time 14.41 seconds
Started Aug 05 04:54:18 PM PDT 24
Finished Aug 05 04:54:33 PM PDT 24
Peak memory 217708 kb
Host smart-4fd9f4b2-94ba-49e8-b87f-ec4cf3a1466d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277368242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4277368242
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1772726870
Short name T53
Test name
Test status
Simulation time 1436549639 ps
CPU time 82.75 seconds
Started Aug 05 04:54:04 PM PDT 24
Finished Aug 05 04:55:27 PM PDT 24
Peak memory 214628 kb
Host smart-9012dbfc-9857-4d02-b842-f540410a1fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772726870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1772726870
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2099171931
Short name T205
Test name
Test status
Simulation time 347684638 ps
CPU time 8.4 seconds
Started Aug 05 04:53:25 PM PDT 24
Finished Aug 05 04:53:33 PM PDT 24
Peak memory 219076 kb
Host smart-38b4e586-407e-48ad-bc89-3b15911cd31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099171931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2099171931
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3947286909
Short name T231
Test name
Test status
Simulation time 2702644588 ps
CPU time 209.15 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:57:04 PM PDT 24
Peak memory 225192 kb
Host smart-a2172b5c-7ad4-46d6-91a6-7b0dc974cc09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947286909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3947286909
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2121072403
Short name T26
Test name
Test status
Simulation time 970414075 ps
CPU time 22.6 seconds
Started Aug 05 04:53:17 PM PDT 24
Finished Aug 05 04:53:40 PM PDT 24
Peak memory 220080 kb
Host smart-49c38fbb-9e01-42d9-be00-4e7659ae5a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121072403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2121072403
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.267363237
Short name T131
Test name
Test status
Simulation time 2008675926 ps
CPU time 16.79 seconds
Started Aug 05 04:53:20 PM PDT 24
Finished Aug 05 04:53:37 PM PDT 24
Peak memory 220168 kb
Host smart-885c1921-91e3-4655-a3ec-c49039ec9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267363237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.267363237
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2746744881
Short name T279
Test name
Test status
Simulation time 1003653787 ps
CPU time 20.35 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 219996 kb
Host smart-6e931127-7bc7-4226-b629-754482a08a69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746744881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2746744881
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2252479989
Short name T298
Test name
Test status
Simulation time 661147548 ps
CPU time 8.33 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 219020 kb
Host smart-85a53c28-d87c-4181-8e6e-a09d728ed738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252479989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2252479989
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2239042453
Short name T290
Test name
Test status
Simulation time 7448774856 ps
CPU time 334.29 seconds
Started Aug 05 04:53:25 PM PDT 24
Finished Aug 05 04:59:00 PM PDT 24
Peak memory 228320 kb
Host smart-aafff621-4204-474e-81f1-063e351cd75f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239042453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2239042453
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1224401386
Short name T147
Test name
Test status
Simulation time 347696325 ps
CPU time 19 seconds
Started Aug 05 04:53:23 PM PDT 24
Finished Aug 05 04:53:42 PM PDT 24
Peak memory 220036 kb
Host smart-58dac7c7-8074-4bb9-ae69-19ce28824841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224401386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1224401386
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2459236379
Short name T212
Test name
Test status
Simulation time 2118543439 ps
CPU time 11.83 seconds
Started Aug 05 04:53:17 PM PDT 24
Finished Aug 05 04:53:29 PM PDT 24
Peak memory 220104 kb
Host smart-e3973cf8-14b2-455c-bee2-14f91908e598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459236379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2459236379
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3625597246
Short name T21
Test name
Test status
Simulation time 316527955 ps
CPU time 225.69 seconds
Started Aug 05 04:53:19 PM PDT 24
Finished Aug 05 04:57:05 PM PDT 24
Peak memory 239736 kb
Host smart-ee2865d2-0b4e-41b4-8b14-c7916cdf6549
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625597246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3625597246
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2291432735
Short name T242
Test name
Test status
Simulation time 1925230401 ps
CPU time 10.65 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:47 PM PDT 24
Peak memory 220028 kb
Host smart-7f40c125-fc61-442e-8493-ab928d812c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291432735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2291432735
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2125776677
Short name T247
Test name
Test status
Simulation time 3737668461 ps
CPU time 19.5 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:53:52 PM PDT 24
Peak memory 219996 kb
Host smart-5965dd78-3151-4bd3-aca5-2cff97ac9a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125776677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2125776677
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1286184139
Short name T207
Test name
Test status
Simulation time 507305683 ps
CPU time 10.37 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 218968 kb
Host smart-e4e4e04f-23ec-4659-aa2a-6a50ac6e0ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286184139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1286184139
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1888203646
Short name T38
Test name
Test status
Simulation time 6035953605 ps
CPU time 320.37 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:58:55 PM PDT 24
Peak memory 235632 kb
Host smart-6ae3e91d-c4c4-4aa0-b01b-1c2430b6b4c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888203646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1888203646
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2150413993
Short name T177
Test name
Test status
Simulation time 989980828 ps
CPU time 22.6 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:54:04 PM PDT 24
Peak memory 219892 kb
Host smart-188856af-daad-46ff-825c-d922f8cbdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150413993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2150413993
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2562168514
Short name T2
Test name
Test status
Simulation time 1472265214 ps
CPU time 10.52 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 219992 kb
Host smart-c97ac542-ab1f-4344-a618-4b572b7280d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562168514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2562168514
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1841115335
Short name T156
Test name
Test status
Simulation time 3207584338 ps
CPU time 34.49 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:54:11 PM PDT 24
Peak memory 220032 kb
Host smart-958be986-32d9-44e9-a123-81d29473cd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841115335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1841115335
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2789231569
Short name T12
Test name
Test status
Simulation time 863505973884 ps
CPU time 2913.2 seconds
Started Aug 05 04:53:30 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 252484 kb
Host smart-629a91f7-03cb-4a61-a11b-60a77f8b316d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789231569 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2789231569
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2145155047
Short name T140
Test name
Test status
Simulation time 10270462481 ps
CPU time 289.98 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 04:58:35 PM PDT 24
Peak memory 242668 kb
Host smart-ecea3f87-cde7-4232-9513-29af69d58d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145155047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2145155047
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2465370802
Short name T199
Test name
Test status
Simulation time 1414433300 ps
CPU time 22.29 seconds
Started Aug 05 04:53:27 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 220020 kb
Host smart-86b48687-21a0-4349-86d2-42734f420bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465370802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2465370802
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2197418505
Short name T35
Test name
Test status
Simulation time 3406905600 ps
CPU time 10.29 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 220100 kb
Host smart-421a03d9-fdf1-42f2-ba93-7c7d9e54cb68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197418505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2197418505
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4153249308
Short name T1
Test name
Test status
Simulation time 5322978602 ps
CPU time 27.73 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 220100 kb
Host smart-b9bde672-e35e-4d36-a123-62de2df14f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153249308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4153249308
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1530353010
Short name T171
Test name
Test status
Simulation time 260713625 ps
CPU time 10.25 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:53:52 PM PDT 24
Peak memory 219088 kb
Host smart-c62e6263-f3dd-40bf-a737-db43bc5dc5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530353010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1530353010
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.363343281
Short name T133
Test name
Test status
Simulation time 6352702367 ps
CPU time 147.28 seconds
Started Aug 05 04:53:44 PM PDT 24
Finished Aug 05 04:56:12 PM PDT 24
Peak memory 220332 kb
Host smart-72499789-e9bc-49b7-8ac2-ce0eb5b404e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363343281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.363343281
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2926460569
Short name T196
Test name
Test status
Simulation time 187228413 ps
CPU time 10.49 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 219980 kb
Host smart-e7d271ca-3cd5-4c9a-b7c8-c917d16415aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926460569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2926460569
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.130928960
Short name T129
Test name
Test status
Simulation time 1161266663 ps
CPU time 30.59 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:54:07 PM PDT 24
Peak memory 219948 kb
Host smart-030d0441-8f74-4594-8647-59035349072c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130928960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.130928960
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3388927291
Short name T161
Test name
Test status
Simulation time 259806987 ps
CPU time 10.24 seconds
Started Aug 05 04:53:29 PM PDT 24
Finished Aug 05 04:53:39 PM PDT 24
Peak memory 218988 kb
Host smart-396ebc2e-1944-44c7-846d-e636fdc701b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388927291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3388927291
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2755053924
Short name T168
Test name
Test status
Simulation time 16234200202 ps
CPU time 213.36 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:57:21 PM PDT 24
Peak memory 239548 kb
Host smart-50508bb1-b24d-41cf-88b1-a694239b0666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755053924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2755053924
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3055996746
Short name T160
Test name
Test status
Simulation time 1053461646 ps
CPU time 23.1 seconds
Started Aug 05 04:53:27 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 220020 kb
Host smart-a517465d-6451-4ab5-a7d9-720e961943d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055996746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3055996746
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1651839593
Short name T209
Test name
Test status
Simulation time 182767730 ps
CPU time 10.84 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 219980 kb
Host smart-84375d18-5f39-470a-824a-f410049a955c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651839593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1651839593
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.825900228
Short name T75
Test name
Test status
Simulation time 2550004805 ps
CPU time 35.58 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 220064 kb
Host smart-cf532b8d-050c-4932-818e-451e6044ceed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825900228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.825900228
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3496360988
Short name T249
Test name
Test status
Simulation time 167384074 ps
CPU time 8.56 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 219048 kb
Host smart-a5c4440a-d709-4a0c-8e69-ce34fb2e32d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496360988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3496360988
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.167247798
Short name T145
Test name
Test status
Simulation time 49677408200 ps
CPU time 528.86 seconds
Started Aug 05 04:53:46 PM PDT 24
Finished Aug 05 05:02:35 PM PDT 24
Peak memory 249204 kb
Host smart-4f7155dd-f2df-44f7-9886-fc49845ae1c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167247798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.167247798
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1139186520
Short name T154
Test name
Test status
Simulation time 990554959 ps
CPU time 22.22 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 219956 kb
Host smart-1966a068-cebc-4e76-8ee1-23c37a3d1d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139186520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1139186520
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4122137229
Short name T274
Test name
Test status
Simulation time 1071874799 ps
CPU time 12 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 220160 kb
Host smart-5a128c98-816e-4136-bf4a-8bb6bcddf076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122137229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4122137229
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1005830294
Short name T15
Test name
Test status
Simulation time 1442733498 ps
CPU time 29.21 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 219448 kb
Host smart-e0ba2be2-fda2-44a9-a00c-ead8df202b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005830294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1005830294
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1029074132
Short name T34
Test name
Test status
Simulation time 661955488 ps
CPU time 8.47 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 218844 kb
Host smart-e1853342-200e-49da-8a28-6436f05b8e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029074132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1029074132
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2760708770
Short name T165
Test name
Test status
Simulation time 11904499769 ps
CPU time 288.9 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:58:28 PM PDT 24
Peak memory 220336 kb
Host smart-a877fc5f-fcf3-483e-9c24-be619d2767be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760708770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2760708770
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3763877687
Short name T233
Test name
Test status
Simulation time 546349250 ps
CPU time 22.19 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 219988 kb
Host smart-4ae338f8-6a60-4009-8e9e-b52b2735260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763877687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3763877687
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2563830625
Short name T126
Test name
Test status
Simulation time 735227718 ps
CPU time 10.51 seconds
Started Aug 05 04:53:30 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 219980 kb
Host smart-f0aad571-74d2-4e65-bf5d-63872a692ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563830625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2563830625
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3485076391
Short name T251
Test name
Test status
Simulation time 2211158420 ps
CPU time 34.32 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 220124 kb
Host smart-bf865252-6f8b-4d17-a8f2-9a55d95a77ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485076391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3485076391
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3828389070
Short name T46
Test name
Test status
Simulation time 38122835287 ps
CPU time 1501.78 seconds
Started Aug 05 04:53:53 PM PDT 24
Finished Aug 05 05:18:55 PM PDT 24
Peak memory 236756 kb
Host smart-164c330b-e76b-407f-b523-3b5b8d769a83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828389070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3828389070
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4178202076
Short name T137
Test name
Test status
Simulation time 3814434474 ps
CPU time 15.52 seconds
Started Aug 05 04:53:29 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 219092 kb
Host smart-ee3d0df8-9a65-4d6b-b30d-58f535c12f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178202076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4178202076
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4115658101
Short name T44
Test name
Test status
Simulation time 11480400573 ps
CPU time 158.52 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:56:21 PM PDT 24
Peak memory 220276 kb
Host smart-778ccf67-cd21-41cf-a1ba-ba1c346ce30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115658101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4115658101
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3047825360
Short name T296
Test name
Test status
Simulation time 1326373705 ps
CPU time 18.3 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:57 PM PDT 24
Peak memory 219976 kb
Host smart-f58b1721-99f6-44e1-ae7a-ea873e557734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047825360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3047825360
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.284143888
Short name T141
Test name
Test status
Simulation time 190175445 ps
CPU time 10.69 seconds
Started Aug 05 04:53:27 PM PDT 24
Finished Aug 05 04:53:38 PM PDT 24
Peak memory 219956 kb
Host smart-f71cf11e-2c86-4005-9087-a342d4ce1601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284143888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.284143888
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2896112847
Short name T319
Test name
Test status
Simulation time 448025680 ps
CPU time 20.5 seconds
Started Aug 05 04:53:43 PM PDT 24
Finished Aug 05 04:54:04 PM PDT 24
Peak memory 219920 kb
Host smart-f9f2f781-c52f-4e22-8141-881cc0f89cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896112847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2896112847
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1553270759
Short name T13
Test name
Test status
Simulation time 55271106906 ps
CPU time 582.33 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 05:03:20 PM PDT 24
Peak memory 236524 kb
Host smart-b70bf9fc-0a21-461f-af3e-f462381abfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553270759 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1553270759
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2239438685
Short name T262
Test name
Test status
Simulation time 255481796 ps
CPU time 10.21 seconds
Started Aug 05 04:53:43 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 219032 kb
Host smart-9949983a-e140-4871-a629-b9ecf3f7084a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239438685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2239438685
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1257795688
Short name T245
Test name
Test status
Simulation time 27761175501 ps
CPU time 357.78 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:59:36 PM PDT 24
Peak memory 220236 kb
Host smart-8ef37b6d-396f-4d87-a00e-7017fbb070dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257795688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1257795688
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3327300911
Short name T158
Test name
Test status
Simulation time 551477334 ps
CPU time 22.34 seconds
Started Aug 05 04:53:50 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 220020 kb
Host smart-0f5e230c-9b16-4602-8f1a-b21fa2b6da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327300911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3327300911
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3819040823
Short name T170
Test name
Test status
Simulation time 207188599 ps
CPU time 10.09 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 219988 kb
Host smart-64df581b-4f93-4640-b3e7-39519e8661d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819040823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3819040823
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.789746064
Short name T71
Test name
Test status
Simulation time 3269708730 ps
CPU time 14.09 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:53:55 PM PDT 24
Peak memory 219860 kb
Host smart-743efd4e-cdfc-4e0e-8110-a5d542aebbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789746064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.789746064
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3056241959
Short name T297
Test name
Test status
Simulation time 260319198 ps
CPU time 9.9 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:49 PM PDT 24
Peak memory 219000 kb
Host smart-3a2f68eb-b8fc-4ac5-a2f1-ccfce755ff14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056241959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3056241959
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.688284815
Short name T37
Test name
Test status
Simulation time 44800775434 ps
CPU time 288.3 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:58:30 PM PDT 24
Peak memory 240672 kb
Host smart-3124f805-9ab3-40bd-b681-b5c4812dd986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688284815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.688284815
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2907218711
Short name T42
Test name
Test status
Simulation time 1320183721 ps
CPU time 19.03 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 219980 kb
Host smart-9a3f12e5-98a0-4c54-b84f-8cbcf939b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907218711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2907218711
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1627409650
Short name T189
Test name
Test status
Simulation time 326157968 ps
CPU time 12.18 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 220016 kb
Host smart-0c33ab6a-c785-4389-a7e6-3bca59174103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627409650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1627409650
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1438998908
Short name T138
Test name
Test status
Simulation time 824023712 ps
CPU time 10.81 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219960 kb
Host smart-ab16f68d-8eef-49f6-b417-098adb6159ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438998908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1438998908
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3698333756
Short name T300
Test name
Test status
Simulation time 234927126 ps
CPU time 8.28 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 218968 kb
Host smart-9eacb60f-3617-481d-bc1f-82bb4b7ff79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698333756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3698333756
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.896549633
Short name T289
Test name
Test status
Simulation time 2697524932 ps
CPU time 209.99 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:57:08 PM PDT 24
Peak memory 241168 kb
Host smart-0f2a098c-d143-45d9-a5ab-e12d12147af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896549633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.896549633
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2418574772
Short name T293
Test name
Test status
Simulation time 1379650326 ps
CPU time 19.91 seconds
Started Aug 05 04:53:48 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 220040 kb
Host smart-403ea14a-e54e-41e9-a8ee-e2135d41c4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418574772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2418574772
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3489888952
Short name T236
Test name
Test status
Simulation time 261847653 ps
CPU time 12.11 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 219960 kb
Host smart-cff21bb9-6c4d-43b4-8129-2075fdc18e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489888952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3489888952
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1655995359
Short name T246
Test name
Test status
Simulation time 577211405 ps
CPU time 38.28 seconds
Started Aug 05 04:53:46 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 219932 kb
Host smart-05839ef2-4175-405e-90e9-72c43cd135e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655995359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1655995359
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.913563356
Short name T186
Test name
Test status
Simulation time 3088883018 ps
CPU time 9.89 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 219100 kb
Host smart-deeb2ff6-8cb1-46e8-9cd2-fbca1b435919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913563356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.913563356
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1598688262
Short name T258
Test name
Test status
Simulation time 3543728620 ps
CPU time 249.9 seconds
Started Aug 05 04:53:27 PM PDT 24
Finished Aug 05 04:57:37 PM PDT 24
Peak memory 235168 kb
Host smart-4d51d1fa-d283-4bbd-ac80-658c7c771b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598688262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1598688262
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3768956008
Short name T198
Test name
Test status
Simulation time 1977584163 ps
CPU time 22.6 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:57 PM PDT 24
Peak memory 219980 kb
Host smart-29273ef8-1b78-465d-a587-bb56a724abcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768956008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3768956008
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3875310553
Short name T317
Test name
Test status
Simulation time 1074587763 ps
CPU time 12.96 seconds
Started Aug 05 04:53:28 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 219952 kb
Host smart-1ffb1541-58d3-47c3-99bd-7e636b5d5d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875310553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3875310553
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3477172308
Short name T27
Test name
Test status
Simulation time 1193811888 ps
CPU time 120 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:55:35 PM PDT 24
Peak memory 239108 kb
Host smart-85454a19-90a0-4957-b1db-01571d9463bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477172308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3477172308
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3550987806
Short name T276
Test name
Test status
Simulation time 178396340 ps
CPU time 10.14 seconds
Started Aug 05 04:53:32 PM PDT 24
Finished Aug 05 04:53:42 PM PDT 24
Peak memory 219996 kb
Host smart-ac65c16a-0be4-40ef-a30e-db89dd6b03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550987806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3550987806
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3136758868
Short name T123
Test name
Test status
Simulation time 278404880 ps
CPU time 18.92 seconds
Started Aug 05 04:53:22 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 219588 kb
Host smart-cd6ef85a-0873-49df-925d-e10572ab479d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136758868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3136758868
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.162169595
Short name T256
Test name
Test status
Simulation time 5768812051 ps
CPU time 14.7 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 219100 kb
Host smart-f046bb97-bd3a-4bb8-a297-fe0aec978d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162169595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.162169595
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.762535467
Short name T36
Test name
Test status
Simulation time 10534112093 ps
CPU time 304.49 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:58:47 PM PDT 24
Peak memory 240832 kb
Host smart-06fff44f-2a87-48f6-bdeb-ee43aabf9eba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762535467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.762535467
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1151662278
Short name T260
Test name
Test status
Simulation time 2433912497 ps
CPU time 30.97 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 219772 kb
Host smart-2c631883-4541-496d-abfa-3e1dc39a415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151662278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1151662278
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2056242567
Short name T313
Test name
Test status
Simulation time 881198269 ps
CPU time 10.58 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 219992 kb
Host smart-b61707a1-9fe8-4129-a4ef-f18a780db358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056242567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2056242567
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1767028609
Short name T144
Test name
Test status
Simulation time 1684609046 ps
CPU time 31.01 seconds
Started Aug 05 04:53:50 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 219924 kb
Host smart-a154e5d8-21c2-40cc-94f9-6a8eeb7c7d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767028609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1767028609
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1526713223
Short name T308
Test name
Test status
Simulation time 22053583854 ps
CPU time 833.19 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 05:07:31 PM PDT 24
Peak memory 232044 kb
Host smart-df68c098-821e-482d-aee0-e244da6c3ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526713223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1526713223
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2948726206
Short name T116
Test name
Test status
Simulation time 250630261 ps
CPU time 10.1 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 219000 kb
Host smart-e77feb91-3760-49e6-9f64-767b6105275e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948726206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2948726206
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2959433148
Short name T182
Test name
Test status
Simulation time 1979772512 ps
CPU time 22.76 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:17 PM PDT 24
Peak memory 219996 kb
Host smart-a34ca4a2-3358-4e8c-bb5e-b2fd9e36a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959433148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2959433148
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1329796223
Short name T121
Test name
Test status
Simulation time 3227694269 ps
CPU time 12.26 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 220088 kb
Host smart-9055a9cd-901d-47ef-9f26-014a5d698a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329796223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1329796223
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3720140351
Short name T96
Test name
Test status
Simulation time 576731731 ps
CPU time 12.19 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 219904 kb
Host smart-225a94c3-2aeb-4618-9634-390fc6b42b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720140351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3720140351
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.612568209
Short name T5
Test name
Test status
Simulation time 2061860317 ps
CPU time 9.94 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:47 PM PDT 24
Peak memory 219072 kb
Host smart-91e33bf0-826c-4547-b9c9-3ef82d93a853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612568209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.612568209
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4254928167
Short name T271
Test name
Test status
Simulation time 3099104512 ps
CPU time 219.65 seconds
Started Aug 05 04:53:32 PM PDT 24
Finished Aug 05 04:57:12 PM PDT 24
Peak memory 239484 kb
Host smart-79595727-ee31-49d4-9bcb-417ac2770d35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254928167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4254928167
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.734829554
Short name T301
Test name
Test status
Simulation time 4721018561 ps
CPU time 18.36 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:57 PM PDT 24
Peak memory 220096 kb
Host smart-fec889f8-d43b-4ff3-b7bc-bf5cbd7fb9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734829554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.734829554
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2173106054
Short name T169
Test name
Test status
Simulation time 523441626 ps
CPU time 12.35 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 220008 kb
Host smart-9a8c04cf-5839-460d-a0f2-f3d6c3b21db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173106054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2173106054
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1112484788
Short name T316
Test name
Test status
Simulation time 2130990472 ps
CPU time 29.68 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219912 kb
Host smart-7147b52d-a672-4b21-ae8d-90920636bf27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112484788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1112484788
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.153223790
Short name T143
Test name
Test status
Simulation time 259552684 ps
CPU time 10 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 218996 kb
Host smart-13de845c-6449-4063-9407-df74bcea73e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153223790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.153223790
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1144562527
Short name T303
Test name
Test status
Simulation time 15775451961 ps
CPU time 247.93 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:57:47 PM PDT 24
Peak memory 239492 kb
Host smart-5e39ade4-cc2a-406b-8e00-837b9d282f4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144562527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1144562527
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3564983976
Short name T257
Test name
Test status
Simulation time 346359907 ps
CPU time 19.63 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:54:07 PM PDT 24
Peak memory 220088 kb
Host smart-ee57c283-cddc-4f5f-94f0-14ee0d1a17db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564983976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3564983976
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.871415625
Short name T159
Test name
Test status
Simulation time 1593760705 ps
CPU time 10.58 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 219956 kb
Host smart-af920572-9121-4341-9a54-8f02c5f4e432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871415625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.871415625
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1566356302
Short name T208
Test name
Test status
Simulation time 386935873 ps
CPU time 8.45 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:49 PM PDT 24
Peak memory 219008 kb
Host smart-18edbc97-353c-439a-865a-37e1e89af601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566356302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1566356302
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2799473224
Short name T127
Test name
Test status
Simulation time 4981787476 ps
CPU time 303.87 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:58:37 PM PDT 24
Peak memory 230476 kb
Host smart-88e0bb32-0b8c-4353-a29b-5f6d096c13ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799473224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2799473224
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2352585489
Short name T195
Test name
Test status
Simulation time 690128207 ps
CPU time 19.15 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 219980 kb
Host smart-a52891c1-9073-4caf-a97e-c3cd44667b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352585489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2352585489
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.920081717
Short name T287
Test name
Test status
Simulation time 514159487 ps
CPU time 12.6 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 219980 kb
Host smart-41a227f0-0c3f-474f-b398-aa10c5bfdf64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920081717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.920081717
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1836179283
Short name T188
Test name
Test status
Simulation time 441299735 ps
CPU time 15.35 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:16 PM PDT 24
Peak memory 219936 kb
Host smart-da5c0399-091e-420f-8d9a-b8c58aa3d982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836179283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1836179283
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3043741863
Short name T149
Test name
Test status
Simulation time 167649404 ps
CPU time 8.2 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:47 PM PDT 24
Peak memory 218992 kb
Host smart-0041299f-8ae6-4067-8ebe-ded23481e905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043741863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3043741863
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.900347026
Short name T39
Test name
Test status
Simulation time 23589395344 ps
CPU time 279.32 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:58:20 PM PDT 24
Peak memory 238440 kb
Host smart-235e1020-65e4-4283-a355-3349473075d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900347026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.900347026
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2480083771
Short name T32
Test name
Test status
Simulation time 2897797939 ps
CPU time 10.17 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 220204 kb
Host smart-7de26072-9b2b-4356-9705-2a449098030a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480083771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2480083771
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3063490772
Short name T203
Test name
Test status
Simulation time 430236512 ps
CPU time 21.83 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 219976 kb
Host smart-d40c457a-046b-4fcc-aa2f-d561331e3332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063490772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3063490772
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.955048101
Short name T98
Test name
Test status
Simulation time 48338181771 ps
CPU time 1772.23 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 05:23:26 PM PDT 24
Peak memory 239364 kb
Host smart-21ef337e-3f6f-456e-bb91-bf2ed2ec8590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955048101 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.955048101
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2772246826
Short name T180
Test name
Test status
Simulation time 517276674 ps
CPU time 10.01 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 218984 kb
Host smart-a4f690e5-b82d-4bd5-8b4e-264632751cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772246826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2772246826
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.348645292
Short name T9
Test name
Test status
Simulation time 14262436955 ps
CPU time 244.21 seconds
Started Aug 05 04:53:43 PM PDT 24
Finished Aug 05 04:57:48 PM PDT 24
Peak memory 242672 kb
Host smart-7e0a97c6-bc17-4f64-a199-4336ce016089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348645292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.348645292
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.588031577
Short name T211
Test name
Test status
Simulation time 332364028 ps
CPU time 19.45 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 220040 kb
Host smart-b228fe65-fd11-4a7c-ae21-047e86e3ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588031577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.588031577
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2886203941
Short name T179
Test name
Test status
Simulation time 347238564 ps
CPU time 10.67 seconds
Started Aug 05 04:53:48 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220020 kb
Host smart-ef77c4ff-b284-414c-adff-0b2c4f5ba025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886203941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2886203941
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4142412651
Short name T148
Test name
Test status
Simulation time 1573091146 ps
CPU time 34.16 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 219888 kb
Host smart-fe8cca33-127f-4f91-a3ea-7a09e1bfcaa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142412651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4142412651
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4288777050
Short name T187
Test name
Test status
Simulation time 564743556 ps
CPU time 9.96 seconds
Started Aug 05 04:53:50 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 219236 kb
Host smart-d5745a4a-58e2-47eb-9f62-6c3bf83a7779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288777050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4288777050
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1180816332
Short name T304
Test name
Test status
Simulation time 16115774726 ps
CPU time 280.56 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:58:34 PM PDT 24
Peak memory 220276 kb
Host smart-919546d6-f7a6-4d3e-b68b-23e4eb014b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180816332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1180816332
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.724363085
Short name T306
Test name
Test status
Simulation time 1320563030 ps
CPU time 19.33 seconds
Started Aug 05 04:53:50 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 220016 kb
Host smart-a4caf9bf-f5ca-4fd5-bff1-794887f37103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724363085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.724363085
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1100946723
Short name T194
Test name
Test status
Simulation time 271792132 ps
CPU time 12.15 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 219988 kb
Host smart-b66c46c2-7151-4834-a01e-756d32c099d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100946723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1100946723
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2053460435
Short name T318
Test name
Test status
Simulation time 4132742952 ps
CPU time 35.14 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 220152 kb
Host smart-5de34ec4-bee1-4f58-a0f9-393bc30726d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053460435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2053460435
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.163344556
Short name T150
Test name
Test status
Simulation time 1035185695 ps
CPU time 9.73 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 219096 kb
Host smart-172d2e32-2d6e-49e9-b41d-234dc40157bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163344556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.163344556
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2912520645
Short name T284
Test name
Test status
Simulation time 113518071790 ps
CPU time 219.48 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:57:21 PM PDT 24
Peak memory 241696 kb
Host smart-325065d4-b906-402b-bac2-f4ce0919aecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912520645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2912520645
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.960093622
Short name T215
Test name
Test status
Simulation time 334162714 ps
CPU time 19.29 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 220040 kb
Host smart-085de3b3-1da6-4b7c-8607-556dfb59d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960093622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.960093622
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3081189346
Short name T243
Test name
Test status
Simulation time 828077828 ps
CPU time 10.46 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 220084 kb
Host smart-095bf9e6-b8a5-49ee-8342-d56d746e5dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081189346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3081189346
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3937126554
Short name T118
Test name
Test status
Simulation time 682800992 ps
CPU time 23.76 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:54:04 PM PDT 24
Peak memory 219944 kb
Host smart-cea8f83f-64c0-4199-bb38-c69635b7d65e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937126554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3937126554
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3527393219
Short name T164
Test name
Test status
Simulation time 2758275226 ps
CPU time 8.41 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:44 PM PDT 24
Peak memory 219300 kb
Host smart-61a8ac00-95cd-4b53-88e4-eb942ecc95b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527393219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3527393219
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1905637370
Short name T263
Test name
Test status
Simulation time 5147079753 ps
CPU time 260.89 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 04:58:06 PM PDT 24
Peak memory 220248 kb
Host smart-2a5e8718-ae01-48a5-a740-9a29ab289064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905637370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1905637370
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3625922501
Short name T282
Test name
Test status
Simulation time 974520312 ps
CPU time 19.27 seconds
Started Aug 05 04:53:53 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 219976 kb
Host smart-9125dfbc-4b1c-43ff-8e21-d6af98ac6c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625922501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3625922501
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1145768357
Short name T95
Test name
Test status
Simulation time 647845965 ps
CPU time 10.5 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 220004 kb
Host smart-2df86308-86da-4283-8ba9-26904ed97a3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145768357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1145768357
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.898013505
Short name T299
Test name
Test status
Simulation time 1105647069 ps
CPU time 15.89 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 219920 kb
Host smart-03b707a9-e7db-42f8-ae81-f03845d5feec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898013505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.898013505
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1283156790
Short name T14
Test name
Test status
Simulation time 110300124537 ps
CPU time 1070.95 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 05:11:36 PM PDT 24
Peak memory 236632 kb
Host smart-0cc766a0-e3ee-4094-8f74-0c5bc6906e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283156790 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1283156790
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4018654422
Short name T305
Test name
Test status
Simulation time 175343831 ps
CPU time 8.5 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 219052 kb
Host smart-d2417fe3-f081-41d5-8193-fbe88ab096f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018654422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4018654422
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2115797828
Short name T315
Test name
Test status
Simulation time 494607278 ps
CPU time 23.2 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220088 kb
Host smart-9a58da0a-6a59-4fd1-955c-62ce7da6bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115797828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2115797828
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2646671747
Short name T285
Test name
Test status
Simulation time 272677695 ps
CPU time 11.73 seconds
Started Aug 05 04:53:34 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 220052 kb
Host smart-e652ca5f-c4fe-4371-8fd3-9182bfdd083a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646671747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2646671747
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2036230931
Short name T23
Test name
Test status
Simulation time 1559333539 ps
CPU time 227.11 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:57:22 PM PDT 24
Peak memory 234392 kb
Host smart-69bb9826-71cc-406a-9e21-f6cc88a6beb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036230931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2036230931
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1037592278
Short name T191
Test name
Test status
Simulation time 276945994 ps
CPU time 11.99 seconds
Started Aug 05 04:53:28 PM PDT 24
Finished Aug 05 04:53:40 PM PDT 24
Peak memory 219964 kb
Host smart-631c5488-83ec-431d-9349-8c79c41d5f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037592278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1037592278
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2838345122
Short name T268
Test name
Test status
Simulation time 1404266688 ps
CPU time 19.69 seconds
Started Aug 05 04:53:32 PM PDT 24
Finished Aug 05 04:53:52 PM PDT 24
Peak memory 220032 kb
Host smart-f9b70e8a-82ae-4ef1-ae56-216dabaf0e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838345122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2838345122
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.262642620
Short name T52
Test name
Test status
Simulation time 18054708624 ps
CPU time 662.16 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 05:04:37 PM PDT 24
Peak memory 221176 kb
Host smart-cbcf49b7-0311-477b-8c58-de0e5b45bc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262642620 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.262642620
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3665110929
Short name T124
Test name
Test status
Simulation time 264960964 ps
CPU time 10.33 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 219120 kb
Host smart-bbcc7ce0-2e99-49c9-9849-6b7bddb63593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665110929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3665110929
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3927655408
Short name T267
Test name
Test status
Simulation time 11202736980 ps
CPU time 205.18 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:57:05 PM PDT 24
Peak memory 238388 kb
Host smart-bbc1fab8-084d-42c5-b4cc-cb7b1bf97afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927655408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3927655408
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4173240550
Short name T310
Test name
Test status
Simulation time 1320591224 ps
CPU time 18.84 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220008 kb
Host smart-a54f4bb9-2924-415d-8613-37090314aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173240550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4173240550
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1579127039
Short name T17
Test name
Test status
Simulation time 727313868 ps
CPU time 10.49 seconds
Started Aug 05 04:53:48 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220012 kb
Host smart-b993508e-4984-4de2-9b4d-17a1863b5893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579127039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1579127039
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2718368819
Short name T112
Test name
Test status
Simulation time 2244142300 ps
CPU time 34.08 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 220032 kb
Host smart-dbd201f2-ab85-4698-b099-89b9bd84b570
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718368819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2718368819
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1283326108
Short name T47
Test name
Test status
Simulation time 104868484629 ps
CPU time 1814.8 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 05:24:06 PM PDT 24
Peak memory 247236 kb
Host smart-4b6b2ebf-a9a6-47df-84e8-853e42b3df38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283326108 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1283326108
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4143426149
Short name T115
Test name
Test status
Simulation time 663537010 ps
CPU time 8.36 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 218952 kb
Host smart-2fa8100e-a09a-446b-b8df-8684bc9d611c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143426149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4143426149
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.921550124
Short name T294
Test name
Test status
Simulation time 84483691524 ps
CPU time 258.6 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 234468 kb
Host smart-0ece0cfc-0729-4320-9c70-7b6673114b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921550124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.921550124
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3727896393
Short name T142
Test name
Test status
Simulation time 512409472 ps
CPU time 22.26 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 220052 kb
Host smart-4428d9af-0bb0-479f-8999-9c8c8e945fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727896393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3727896393
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.938996044
Short name T228
Test name
Test status
Simulation time 725193807 ps
CPU time 10.49 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 219976 kb
Host smart-4469bfb8-bd6c-4043-a706-3ba26200288b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938996044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.938996044
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.107612752
Short name T197
Test name
Test status
Simulation time 534316265 ps
CPU time 27.81 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 219940 kb
Host smart-109363df-ed85-4767-b366-6a719e15fe2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107612752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.107612752
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.145442906
Short name T33
Test name
Test status
Simulation time 691299201 ps
CPU time 8.26 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 218932 kb
Host smart-41bbf33e-01ea-4a56-a4eb-e300b96fd771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145442906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.145442906
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4181358545
Short name T213
Test name
Test status
Simulation time 7102050849 ps
CPU time 392.89 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 05:00:18 PM PDT 24
Peak memory 239520 kb
Host smart-61526272-23f7-4219-bc56-6619b0020388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181358545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4181358545
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2425232903
Short name T277
Test name
Test status
Simulation time 1946635904 ps
CPU time 19.78 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 220000 kb
Host smart-aa41f03a-d093-4a53-a236-790bfa56c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425232903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2425232903
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2503639467
Short name T261
Test name
Test status
Simulation time 518868670 ps
CPU time 12.25 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 220020 kb
Host smart-1e69c4d3-5a8d-4397-ab3e-4555ed2f23bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503639467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2503639467
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4253259294
Short name T70
Test name
Test status
Simulation time 473389356 ps
CPU time 28.93 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219948 kb
Host smart-76cabb4c-b6cb-464f-a626-21fe4cac0d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253259294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4253259294
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3337728854
Short name T224
Test name
Test status
Simulation time 37807123846 ps
CPU time 1468.33 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 05:18:09 PM PDT 24
Peak memory 239824 kb
Host smart-0da5141b-6f14-49df-897d-579d562ed698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337728854 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3337728854
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1473839554
Short name T3
Test name
Test status
Simulation time 260914009 ps
CPU time 9.98 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219124 kb
Host smart-1a04b2dc-0683-4b4f-ae81-4203e68a7af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473839554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1473839554
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1029059942
Short name T292
Test name
Test status
Simulation time 28900258387 ps
CPU time 183.6 seconds
Started Aug 05 04:53:53 PM PDT 24
Finished Aug 05 04:56:57 PM PDT 24
Peak memory 230352 kb
Host smart-18b3c31e-a12a-42ca-b487-99cc6bd565bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029059942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1029059942
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2711509842
Short name T223
Test name
Test status
Simulation time 6182739329 ps
CPU time 22.04 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 220152 kb
Host smart-1826d608-48b8-4304-9d21-e6c19424b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711509842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2711509842
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.257694680
Short name T273
Test name
Test status
Simulation time 184343529 ps
CPU time 10.46 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 219884 kb
Host smart-10ad90de-ca3e-47d0-871c-64c7681db5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257694680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.257694680
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3838391945
Short name T130
Test name
Test status
Simulation time 268262400 ps
CPU time 19.43 seconds
Started Aug 05 04:53:46 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 219912 kb
Host smart-8782c2b2-3b23-46b6-82bb-87966730c761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838391945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3838391945
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3590731360
Short name T238
Test name
Test status
Simulation time 1383003507 ps
CPU time 8.56 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 219908 kb
Host smart-ebab71eb-f4f7-4e31-a716-36c5c2262235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590731360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3590731360
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1279574325
Short name T45
Test name
Test status
Simulation time 11815286577 ps
CPU time 231.33 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:57:39 PM PDT 24
Peak memory 238712 kb
Host smart-d23d686d-3a8a-4ad3-9865-449eeec63b11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279574325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1279574325
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2126023640
Short name T202
Test name
Test status
Simulation time 1012622276 ps
CPU time 22.9 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 220004 kb
Host smart-965e77d8-4f85-41ca-99a7-0571f05bda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126023640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2126023640
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1651820189
Short name T139
Test name
Test status
Simulation time 1029119626 ps
CPU time 12.09 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 219936 kb
Host smart-96df21cc-dc11-4263-a248-3beda110b41b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651820189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1651820189
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1101427886
Short name T269
Test name
Test status
Simulation time 269996086 ps
CPU time 19.34 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:14 PM PDT 24
Peak memory 219612 kb
Host smart-86a4cd86-79bb-4a75-9bc2-d0758dedbfc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101427886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1101427886
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3225663658
Short name T275
Test name
Test status
Simulation time 260784495 ps
CPU time 10.15 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219096 kb
Host smart-b4935733-3b3f-41f5-a669-7ab2d9bf903b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225663658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3225663658
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1269188067
Short name T240
Test name
Test status
Simulation time 10466617763 ps
CPU time 259.32 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:58:13 PM PDT 24
Peak memory 239544 kb
Host smart-6d6ce3fc-71d3-4b10-83f9-3b8f38c61e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269188067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1269188067
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3964651109
Short name T291
Test name
Test status
Simulation time 3299686017 ps
CPU time 19.37 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 220116 kb
Host smart-16f1d9ae-341f-4bb1-a36e-104017afab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964651109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3964651109
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3339204916
Short name T253
Test name
Test status
Simulation time 2333854056 ps
CPU time 12.07 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 220172 kb
Host smart-d4ba6279-1e2a-483c-9d04-4c8baedb4b01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339204916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3339204916
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3351236707
Short name T72
Test name
Test status
Simulation time 306940085 ps
CPU time 19.94 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:54:07 PM PDT 24
Peak memory 219976 kb
Host smart-533fdb4e-bfc5-459d-b9fb-509b4be020e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351236707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3351236707
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1781508940
Short name T184
Test name
Test status
Simulation time 991118408 ps
CPU time 9.82 seconds
Started Aug 05 04:53:43 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 219028 kb
Host smart-2896fd58-676c-4e52-af5a-ff280e8c5f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781508940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1781508940
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2539782402
Short name T119
Test name
Test status
Simulation time 9852187089 ps
CPU time 354.39 seconds
Started Aug 05 04:53:48 PM PDT 24
Finished Aug 05 04:59:43 PM PDT 24
Peak memory 240892 kb
Host smart-3dfc12e6-4643-45f6-bfe1-35c763327ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539782402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2539782402
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.288815429
Short name T117
Test name
Test status
Simulation time 1012949141 ps
CPU time 22.54 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 220044 kb
Host smart-6e07bb7e-eaa1-4b55-b454-f89f581fb3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288815429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.288815429
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1233052847
Short name T272
Test name
Test status
Simulation time 723527132 ps
CPU time 10.54 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 219976 kb
Host smart-a4e21d2a-7b59-4353-9db5-e7b7acab710e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233052847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1233052847
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2919636983
Short name T264
Test name
Test status
Simulation time 820423119 ps
CPU time 45.77 seconds
Started Aug 05 04:53:42 PM PDT 24
Finished Aug 05 04:54:28 PM PDT 24
Peak memory 219916 kb
Host smart-e0d9601c-5cf1-460f-8032-baba719f5069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919636983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2919636983
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2182138226
Short name T286
Test name
Test status
Simulation time 259936933 ps
CPU time 10.29 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 219032 kb
Host smart-1108cd36-b723-4708-8651-0fbfc6a34420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182138226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2182138226
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4221330295
Short name T134
Test name
Test status
Simulation time 10372947412 ps
CPU time 164.55 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 04:56:30 PM PDT 24
Peak memory 234628 kb
Host smart-6b870225-930c-4804-abb2-d1c2c7e81633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221330295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4221330295
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.697587633
Short name T200
Test name
Test status
Simulation time 346849577 ps
CPU time 19.42 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 220276 kb
Host smart-caef03cc-e9aa-415a-8fe6-e22ea7cd63ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697587633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.697587633
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1996332621
Short name T7
Test name
Test status
Simulation time 344180562 ps
CPU time 12.11 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219988 kb
Host smart-d32a6606-1dab-4e87-a59c-fb8311227753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996332621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1996332621
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3801690448
Short name T218
Test name
Test status
Simulation time 1821914362 ps
CPU time 54.8 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:54:51 PM PDT 24
Peak memory 220012 kb
Host smart-520f5f7e-1fc1-4015-b73d-ccc8d916b9aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801690448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3801690448
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3707596751
Short name T259
Test name
Test status
Simulation time 1072519584 ps
CPU time 9.66 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:09 PM PDT 24
Peak memory 218996 kb
Host smart-c436ae93-55aa-41a8-a303-e510b7655df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707596751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3707596751
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.85903537
Short name T20
Test name
Test status
Simulation time 5457843706 ps
CPU time 304.38 seconds
Started Aug 05 04:53:46 PM PDT 24
Finished Aug 05 04:58:51 PM PDT 24
Peak memory 219580 kb
Host smart-ebd073a5-e8d1-412a-8f08-dd6be2354a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85903537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_co
rrupt_sig_fatal_chk.85903537
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3437984894
Short name T125
Test name
Test status
Simulation time 332667269 ps
CPU time 19.46 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 220004 kb
Host smart-2c00b309-61ff-4576-9788-49eba3dfb188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437984894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3437984894
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.698480707
Short name T153
Test name
Test status
Simulation time 676297999 ps
CPU time 12.13 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 220100 kb
Host smart-72c735cb-15bc-4123-ac1f-3c9371d17700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698480707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.698480707
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.34625482
Short name T281
Test name
Test status
Simulation time 279154815 ps
CPU time 16.28 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:19 PM PDT 24
Peak memory 219952 kb
Host smart-7c05555b-8b88-4ae5-9f92-c99a8e64e1c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.rom_ctrl_stress_all.34625482
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3617214301
Short name T135
Test name
Test status
Simulation time 750788109 ps
CPU time 8.74 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 219004 kb
Host smart-69b48a20-0505-4133-9402-f63a3720d513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617214301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3617214301
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1818379497
Short name T227
Test name
Test status
Simulation time 3674017375 ps
CPU time 123.2 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:56:10 PM PDT 24
Peak memory 220240 kb
Host smart-c5889a4c-e9fd-4f97-9bad-f45ae07de53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818379497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1818379497
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4141925803
Short name T309
Test name
Test status
Simulation time 3008231480 ps
CPU time 19.51 seconds
Started Aug 05 04:53:50 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 220136 kb
Host smart-15666db3-e529-436f-8a91-be2adc0f94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141925803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4141925803
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2319556784
Short name T265
Test name
Test status
Simulation time 260298587 ps
CPU time 12.23 seconds
Started Aug 05 04:53:51 PM PDT 24
Finished Aug 05 04:54:04 PM PDT 24
Peak memory 219956 kb
Host smart-9f3ddb06-c28a-47e0-87fc-cbda8eea8451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319556784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2319556784
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3212513684
Short name T248
Test name
Test status
Simulation time 2131522396 ps
CPU time 32.02 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:31 PM PDT 24
Peak memory 219968 kb
Host smart-5862cf2b-72ae-4614-89fe-5594f08225a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212513684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3212513684
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.114921148
Short name T166
Test name
Test status
Simulation time 994141278 ps
CPU time 10.18 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 218960 kb
Host smart-c0f21c59-0f99-4eaf-90b3-9e776d779f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114921148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.114921148
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2126449864
Short name T229
Test name
Test status
Simulation time 6635873396 ps
CPU time 356.56 seconds
Started Aug 05 04:53:28 PM PDT 24
Finished Aug 05 04:59:24 PM PDT 24
Peak memory 239564 kb
Host smart-a6dbdd71-1601-46ca-a54a-da4ce1e7dc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126449864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2126449864
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2087149994
Short name T40
Test name
Test status
Simulation time 332605961 ps
CPU time 19.45 seconds
Started Aug 05 04:53:30 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 220016 kb
Host smart-086c1591-ee67-4d09-8b37-22caf59ae8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087149994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2087149994
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1832589381
Short name T151
Test name
Test status
Simulation time 2026516527 ps
CPU time 16.43 seconds
Started Aug 05 04:53:44 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 219400 kb
Host smart-09f00503-317d-40c9-8496-f33504425ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832589381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1832589381
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1104058862
Short name T28
Test name
Test status
Simulation time 285573577 ps
CPU time 222.37 seconds
Started Aug 05 04:53:32 PM PDT 24
Finished Aug 05 04:57:14 PM PDT 24
Peak memory 239572 kb
Host smart-5b9493cd-6357-40f2-b5b3-897ca18bf8a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104058862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1104058862
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2539897659
Short name T255
Test name
Test status
Simulation time 259101078 ps
CPU time 11.77 seconds
Started Aug 05 04:53:28 PM PDT 24
Finished Aug 05 04:53:40 PM PDT 24
Peak memory 219988 kb
Host smart-9f54fb48-76af-4e52-b801-023a1457cce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539897659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2539897659
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2267382259
Short name T172
Test name
Test status
Simulation time 3576090487 ps
CPU time 27.58 seconds
Started Aug 05 04:53:31 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220024 kb
Host smart-af3b8f8f-6683-4072-a758-4da3d89ff793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267382259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2267382259
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2507231901
Short name T49
Test name
Test status
Simulation time 47191993903 ps
CPU time 1850.86 seconds
Started Aug 05 04:53:26 PM PDT 24
Finished Aug 05 05:24:17 PM PDT 24
Peak memory 239060 kb
Host smart-c34aadba-f101-4a3b-8a7d-72726709e29b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507231901 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2507231901
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1997899402
Short name T136
Test name
Test status
Simulation time 176537669 ps
CPU time 8.49 seconds
Started Aug 05 04:53:48 PM PDT 24
Finished Aug 05 04:53:57 PM PDT 24
Peak memory 219072 kb
Host smart-2114c9cc-7523-4254-a5c2-357be83a52fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997899402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1997899402
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3067463124
Short name T222
Test name
Test status
Simulation time 2332930409 ps
CPU time 149.82 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:56:25 PM PDT 24
Peak memory 239644 kb
Host smart-18b639a1-d202-489f-914d-aa0fe9d638ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067463124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3067463124
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2482247314
Short name T266
Test name
Test status
Simulation time 497316649 ps
CPU time 23.43 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 219972 kb
Host smart-002d35e2-f003-43e2-bc0a-c4f4cac6ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482247314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2482247314
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.524399178
Short name T128
Test name
Test status
Simulation time 365820791 ps
CPU time 10.71 seconds
Started Aug 05 04:53:41 PM PDT 24
Finished Aug 05 04:53:52 PM PDT 24
Peak memory 219756 kb
Host smart-3b3304cb-e62b-4a8d-8abe-3936caa94579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524399178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.524399178
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1261317758
Short name T244
Test name
Test status
Simulation time 1045562394 ps
CPU time 13.02 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 219940 kb
Host smart-d3e4895e-c1fd-44e6-9404-4f62306bf2fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261317758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1261317758
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.78441456
Short name T178
Test name
Test status
Simulation time 347540727 ps
CPU time 8.25 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 218976 kb
Host smart-a2e2e253-04be-49b8-84aa-c152026aa9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78441456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.78441456
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1024915554
Short name T217
Test name
Test status
Simulation time 5849062737 ps
CPU time 219.54 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:57:32 PM PDT 24
Peak memory 239620 kb
Host smart-2fa90f3b-4f21-4cff-8617-ffde579ac49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024915554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1024915554
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.756758511
Short name T167
Test name
Test status
Simulation time 2248970394 ps
CPU time 22.23 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:23 PM PDT 24
Peak memory 220088 kb
Host smart-dbe58e7c-1da4-4b49-90cf-8a38fc23a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756758511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.756758511
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.894172297
Short name T204
Test name
Test status
Simulation time 404353464 ps
CPU time 12.03 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 220100 kb
Host smart-11ccdc52-3727-4c56-a8fa-ea7a5c8de328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894172297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.894172297
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1495789956
Short name T278
Test name
Test status
Simulation time 1346081424 ps
CPU time 27.67 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 219948 kb
Host smart-135c1037-ba19-481e-9f6b-33265f11796d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495789956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1495789956
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1982856890
Short name T113
Test name
Test status
Simulation time 255368304 ps
CPU time 10.4 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 219008 kb
Host smart-2bd79c10-6686-4291-988b-fa1f4c8445a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982856890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1982856890
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4080893319
Short name T270
Test name
Test status
Simulation time 4496875129 ps
CPU time 235.2 seconds
Started Aug 05 04:53:56 PM PDT 24
Finished Aug 05 04:57:51 PM PDT 24
Peak memory 218880 kb
Host smart-8aab65b1-3eef-4107-98fa-c2a8e80c1d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080893319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4080893319
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.541527196
Short name T288
Test name
Test status
Simulation time 1380287054 ps
CPU time 19.42 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 220168 kb
Host smart-7ed7614e-b287-42f5-93ff-e0cb1055a2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541527196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.541527196
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3128111934
Short name T232
Test name
Test status
Simulation time 358936728 ps
CPU time 10.86 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:03 PM PDT 24
Peak memory 220004 kb
Host smart-c1779bd9-0945-4437-bacf-a4d9b87c9988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128111934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3128111934
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4230197660
Short name T220
Test name
Test status
Simulation time 356236294 ps
CPU time 19.8 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:19 PM PDT 24
Peak memory 219948 kb
Host smart-6b145c0c-2b12-4d1d-a096-aa5710dcbb01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230197660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4230197660
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.770948451
Short name T192
Test name
Test status
Simulation time 515906037 ps
CPU time 9.73 seconds
Started Aug 05 04:53:45 PM PDT 24
Finished Aug 05 04:53:55 PM PDT 24
Peak memory 219072 kb
Host smart-f3ec7359-0b85-4891-91fc-8484b25add93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770948451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.770948451
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.234482568
Short name T111
Test name
Test status
Simulation time 11297892050 ps
CPU time 219.22 seconds
Started Aug 05 04:53:46 PM PDT 24
Finished Aug 05 04:57:26 PM PDT 24
Peak memory 235856 kb
Host smart-018c209e-bccf-40e5-99b3-ddd036d7fcee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234482568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.234482568
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1485009232
Short name T314
Test name
Test status
Simulation time 518351643 ps
CPU time 22.73 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:19 PM PDT 24
Peak memory 219980 kb
Host smart-9559e4b2-afc8-4019-be21-b944b92f5552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485009232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1485009232
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1154141777
Short name T181
Test name
Test status
Simulation time 696522905 ps
CPU time 12.31 seconds
Started Aug 05 04:54:00 PM PDT 24
Finished Aug 05 04:54:13 PM PDT 24
Peak memory 220084 kb
Host smart-55c476a9-a45c-44fb-bd81-49d90ca90476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154141777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1154141777
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2853491776
Short name T201
Test name
Test status
Simulation time 2095757573 ps
CPU time 38.99 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:54:37 PM PDT 24
Peak memory 219944 kb
Host smart-1951cbeb-0deb-43c0-8ebb-27b7bf57b3ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853491776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2853491776
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4265513242
Short name T31
Test name
Test status
Simulation time 496561085 ps
CPU time 10.18 seconds
Started Aug 05 04:54:11 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 219124 kb
Host smart-398359dc-744d-4450-ae67-7ce43a5c7c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265513242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4265513242
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1166963930
Short name T320
Test name
Test status
Simulation time 24965467980 ps
CPU time 358.94 seconds
Started Aug 05 04:53:58 PM PDT 24
Finished Aug 05 04:59:57 PM PDT 24
Peak memory 220304 kb
Host smart-c77de03f-ffda-43f0-b814-247fe331d832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166963930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1166963930
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3934661386
Short name T157
Test name
Test status
Simulation time 496223563 ps
CPU time 22.77 seconds
Started Aug 05 04:54:01 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 220020 kb
Host smart-594154c0-ef74-4d86-ab09-f5ad812c029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934661386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3934661386
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2232408784
Short name T323
Test name
Test status
Simulation time 213707126 ps
CPU time 10.47 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:54:05 PM PDT 24
Peak memory 220040 kb
Host smart-06ab2ed6-c35d-4286-9dc7-256ea4673a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232408784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2232408784
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1539678918
Short name T68
Test name
Test status
Simulation time 9146307528 ps
CPU time 39.31 seconds
Started Aug 05 04:53:53 PM PDT 24
Finished Aug 05 04:54:32 PM PDT 24
Peak memory 220064 kb
Host smart-197f3429-12fb-426a-93bb-9942a2ef1c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539678918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1539678918
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3583712923
Short name T50
Test name
Test status
Simulation time 109841142558 ps
CPU time 1062.94 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 05:11:42 PM PDT 24
Peak memory 236764 kb
Host smart-29031ef2-be9a-4fc8-b8fa-1ddf1670e2f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583712923 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3583712923
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.554459990
Short name T302
Test name
Test status
Simulation time 663868628 ps
CPU time 8.26 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 218932 kb
Host smart-e5fb8ebe-ce76-4118-bb8e-44331d15e7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554459990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.554459990
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1779911274
Short name T252
Test name
Test status
Simulation time 5693182076 ps
CPU time 320.43 seconds
Started Aug 05 04:54:04 PM PDT 24
Finished Aug 05 04:59:25 PM PDT 24
Peak memory 243920 kb
Host smart-1a2b2823-1c47-4852-8257-9698b097ad8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779911274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1779911274
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.869036200
Short name T25
Test name
Test status
Simulation time 663709640 ps
CPU time 19.17 seconds
Started Aug 05 04:53:49 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 220092 kb
Host smart-651359cc-0d47-4cda-b3d8-6b0c37cd0001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869036200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.869036200
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3862053350
Short name T97
Test name
Test status
Simulation time 1177121182 ps
CPU time 17.12 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 219336 kb
Host smart-8badbeb4-d4ed-4b5b-a1b4-310656bb3b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862053350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3862053350
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1771752053
Short name T155
Test name
Test status
Simulation time 755344306 ps
CPU time 28.22 seconds
Started Aug 05 04:53:54 PM PDT 24
Finished Aug 05 04:54:22 PM PDT 24
Peak memory 219952 kb
Host smart-6365265c-2793-410e-8688-b88041cb5460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771752053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1771752053
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3247559393
Short name T295
Test name
Test status
Simulation time 268638026452 ps
CPU time 2703.96 seconds
Started Aug 05 04:54:09 PM PDT 24
Finished Aug 05 05:39:14 PM PDT 24
Peak memory 245752 kb
Host smart-c987acb3-6c2d-41b3-877a-de51a5b795ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247559393 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3247559393
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3192430996
Short name T152
Test name
Test status
Simulation time 174555283 ps
CPU time 8.33 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:54:00 PM PDT 24
Peak memory 219168 kb
Host smart-e12c6eef-6ab2-4352-a005-390af170fbfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192430996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3192430996
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1329456981
Short name T162
Test name
Test status
Simulation time 13729117637 ps
CPU time 216.74 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:57:44 PM PDT 24
Peak memory 225376 kb
Host smart-0e95ae70-7c54-4ad8-a003-64112f13589a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329456981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1329456981
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.193919993
Short name T230
Test name
Test status
Simulation time 190976328 ps
CPU time 10.66 seconds
Started Aug 05 04:54:07 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 220072 kb
Host smart-4dca7dee-f3fd-4585-85ca-d9b2109dbf83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193919993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.193919993
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1443497473
Short name T239
Test name
Test status
Simulation time 492867803 ps
CPU time 15.07 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:14 PM PDT 24
Peak memory 219520 kb
Host smart-b9bf6445-ccad-4b1a-aa8f-c3f455cbe6b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443497473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1443497473
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.517505215
Short name T311
Test name
Test status
Simulation time 262824821 ps
CPU time 10.17 seconds
Started Aug 05 04:54:05 PM PDT 24
Finished Aug 05 04:54:15 PM PDT 24
Peak memory 218964 kb
Host smart-942cc32d-2986-4c89-b3ee-0b918e62920e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517505215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.517505215
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.993145650
Short name T226
Test name
Test status
Simulation time 9067924278 ps
CPU time 129.92 seconds
Started Aug 05 04:53:52 PM PDT 24
Finished Aug 05 04:56:02 PM PDT 24
Peak memory 241560 kb
Host smart-c0acac6a-cd6f-4123-a0e4-23df988be201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993145650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.993145650
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2511483038
Short name T237
Test name
Test status
Simulation time 335630710 ps
CPU time 19.23 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 220020 kb
Host smart-7806eea6-0b12-4515-8603-addff8e8182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511483038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2511483038
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2059547155
Short name T219
Test name
Test status
Simulation time 733004115 ps
CPU time 10.74 seconds
Started Aug 05 04:53:57 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 220048 kb
Host smart-6c1b05b1-d292-4e32-bac2-9203d3b8c2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059547155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2059547155
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2259364739
Short name T16
Test name
Test status
Simulation time 1116829779 ps
CPU time 36.52 seconds
Started Aug 05 04:54:06 PM PDT 24
Finished Aug 05 04:54:43 PM PDT 24
Peak memory 219968 kb
Host smart-3ad2980c-0dd8-452d-90d3-ed96046b68d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259364739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2259364739
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1447434745
Short name T29
Test name
Test status
Simulation time 688922991 ps
CPU time 8.42 seconds
Started Aug 05 04:54:02 PM PDT 24
Finished Aug 05 04:54:11 PM PDT 24
Peak memory 219184 kb
Host smart-1dba4406-aada-4654-9c29-4a6e3bbbe096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447434745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1447434745
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2743022664
Short name T312
Test name
Test status
Simulation time 16726656734 ps
CPU time 277.69 seconds
Started Aug 05 04:54:03 PM PDT 24
Finished Aug 05 04:58:41 PM PDT 24
Peak memory 226344 kb
Host smart-11260e56-9932-4d0f-af18-b03a55510be7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743022664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2743022664
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3711678159
Short name T122
Test name
Test status
Simulation time 1977777135 ps
CPU time 22.47 seconds
Started Aug 05 04:53:55 PM PDT 24
Finished Aug 05 04:54:18 PM PDT 24
Peak memory 220072 kb
Host smart-882a88f7-4ffe-48ad-8395-c047e7ff783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711678159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3711678159
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2308034540
Short name T241
Test name
Test status
Simulation time 700420756 ps
CPU time 10.66 seconds
Started Aug 05 04:53:59 PM PDT 24
Finished Aug 05 04:54:10 PM PDT 24
Peak memory 220064 kb
Host smart-3fd6d696-4bc4-4f04-bfb9-f87ce77f8ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308034540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2308034540
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3433612123
Short name T225
Test name
Test status
Simulation time 3276759998 ps
CPU time 39.38 seconds
Started Aug 05 04:54:02 PM PDT 24
Finished Aug 05 04:54:41 PM PDT 24
Peak memory 220024 kb
Host smart-2afaf7af-6ba2-4826-be4e-ad8eaf3db737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433612123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3433612123
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1245964780
Short name T120
Test name
Test status
Simulation time 508320233 ps
CPU time 9.97 seconds
Started Aug 05 04:54:14 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 219008 kb
Host smart-3a93b350-6fa9-484e-a92c-00af76877e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245964780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1245964780
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1993437295
Short name T19
Test name
Test status
Simulation time 2606943193 ps
CPU time 142.55 seconds
Started Aug 05 04:54:04 PM PDT 24
Finished Aug 05 04:56:26 PM PDT 24
Peak memory 237712 kb
Host smart-2540509a-6b96-4696-b6d7-040a3498162b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993437295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1993437295
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2253949519
Short name T206
Test name
Test status
Simulation time 1436341462 ps
CPU time 19.32 seconds
Started Aug 05 04:53:53 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 219996 kb
Host smart-d06ce1c0-c2a4-4f1e-99b1-9b71d737f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253949519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2253949519
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3148162141
Short name T6
Test name
Test status
Simulation time 178714942 ps
CPU time 10.34 seconds
Started Aug 05 04:54:10 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 219996 kb
Host smart-e39bd8b0-6f4b-4f79-8bc8-a367bfb7ac59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148162141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3148162141
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3871190454
Short name T94
Test name
Test status
Simulation time 2025374721 ps
CPU time 26.64 seconds
Started Aug 05 04:54:26 PM PDT 24
Finished Aug 05 04:54:53 PM PDT 24
Peak memory 219924 kb
Host smart-028c4996-d952-4b81-b11e-64a878ac547b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871190454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3871190454
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.830957849
Short name T114
Test name
Test status
Simulation time 262950807 ps
CPU time 10.09 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:49 PM PDT 24
Peak memory 219804 kb
Host smart-bc30ccaf-dbd0-43bb-a378-92ee8459e184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830957849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.830957849
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2003029872
Short name T18
Test name
Test status
Simulation time 4146900867 ps
CPU time 224.01 seconds
Started Aug 05 04:53:20 PM PDT 24
Finished Aug 05 04:57:04 PM PDT 24
Peak memory 238460 kb
Host smart-3fa27fb9-c484-417e-a8d9-b00b510b7859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003029872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2003029872
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2456871696
Short name T234
Test name
Test status
Simulation time 1379590645 ps
CPU time 19.44 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220300 kb
Host smart-420d2e94-68c9-468f-a963-0557647273c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456871696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2456871696
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.27846721
Short name T173
Test name
Test status
Simulation time 529076985 ps
CPU time 12.55 seconds
Started Aug 05 04:53:28 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 219980 kb
Host smart-beb81b88-193e-4ef3-8da5-30901e550b10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27846721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.27846721
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1791818447
Short name T307
Test name
Test status
Simulation time 783741798 ps
CPU time 10.36 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 219968 kb
Host smart-e423f3bf-df5b-401b-866e-e852f60da369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791818447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1791818447
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2541106188
Short name T214
Test name
Test status
Simulation time 671953984 ps
CPU time 22.53 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 220224 kb
Host smart-c7aaeb18-0347-4709-b3e0-06dac734ebde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541106188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2541106188
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1590688202
Short name T132
Test name
Test status
Simulation time 588930352 ps
CPU time 9.7 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 219032 kb
Host smart-ed514ae2-d2d5-4d6f-9539-1f40898ad749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590688202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1590688202
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4214766362
Short name T174
Test name
Test status
Simulation time 54852777470 ps
CPU time 289.46 seconds
Started Aug 05 04:53:47 PM PDT 24
Finished Aug 05 04:58:37 PM PDT 24
Peak memory 225252 kb
Host smart-7d0f3800-86bd-486e-a9fe-4ed88f104a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214766362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4214766362
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1255572592
Short name T176
Test name
Test status
Simulation time 511935516 ps
CPU time 22.31 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 219992 kb
Host smart-a6eac835-40e4-434c-81e9-1484333cb6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255572592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1255572592
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1943362049
Short name T175
Test name
Test status
Simulation time 1830761163 ps
CPU time 12.14 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:53:48 PM PDT 24
Peak memory 220160 kb
Host smart-9729d84e-e107-4c4e-bef6-7a8d4e0f688a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943362049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1943362049
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3675137816
Short name T59
Test name
Test status
Simulation time 270906078 ps
CPU time 12.38 seconds
Started Aug 05 04:53:16 PM PDT 24
Finished Aug 05 04:53:28 PM PDT 24
Peak memory 220064 kb
Host smart-fd4387f1-7af2-4258-8d49-26316b9b8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675137816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3675137816
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.36959192
Short name T322
Test name
Test status
Simulation time 679880915 ps
CPU time 23.47 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:54:04 PM PDT 24
Peak memory 219936 kb
Host smart-3081a9cf-de6c-4fec-b97a-0f9cd095cdd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.36959192
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.359244117
Short name T48
Test name
Test status
Simulation time 12329691684 ps
CPU time 484.75 seconds
Started Aug 05 04:53:38 PM PDT 24
Finished Aug 05 05:01:43 PM PDT 24
Peak memory 230584 kb
Host smart-36aebae5-83ca-4fe2-ac01-535c9ad727df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359244117 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.359244117
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.55053010
Short name T193
Test name
Test status
Simulation time 352738102 ps
CPU time 8.28 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 219052 kb
Host smart-27be7f26-ef0f-41c0-b537-939cef220025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55053010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.55053010
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.465126320
Short name T30
Test name
Test status
Simulation time 106631126699 ps
CPU time 285.38 seconds
Started Aug 05 04:53:25 PM PDT 24
Finished Aug 05 04:58:10 PM PDT 24
Peak memory 219856 kb
Host smart-5bbeb7f6-275e-4fef-b4cb-8962f44cb618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465126320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.465126320
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.148398776
Short name T283
Test name
Test status
Simulation time 332129885 ps
CPU time 19.26 seconds
Started Aug 05 04:53:35 PM PDT 24
Finished Aug 05 04:53:54 PM PDT 24
Peak memory 220084 kb
Host smart-e2dbce6e-2a7c-438f-a4f4-7159f44f1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148398776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.148398776
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2668896033
Short name T216
Test name
Test status
Simulation time 272129143 ps
CPU time 12.16 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 219996 kb
Host smart-20124e84-995a-4806-bdf8-c1d6d0e9b457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668896033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2668896033
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2604563351
Short name T235
Test name
Test status
Simulation time 541662038 ps
CPU time 12.27 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 219940 kb
Host smart-d3adf02b-9bf7-4bf2-8fee-0077066b3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604563351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2604563351
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.506621666
Short name T73
Test name
Test status
Simulation time 538453014 ps
CPU time 37.12 seconds
Started Aug 05 04:53:30 PM PDT 24
Finished Aug 05 04:54:07 PM PDT 24
Peak memory 219920 kb
Host smart-bcaa7884-293f-42c4-8a18-c05969f80b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506621666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.506621666
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.175700266
Short name T250
Test name
Test status
Simulation time 1027272698 ps
CPU time 10.08 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 219000 kb
Host smart-79de5d85-693e-48e3-b3c5-9e65c5ef6851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175700266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.175700266
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2421035321
Short name T210
Test name
Test status
Simulation time 5687430293 ps
CPU time 159.27 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:56:20 PM PDT 24
Peak memory 238464 kb
Host smart-48d35100-4b88-4451-adec-debf9aabd40a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421035321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2421035321
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1692098399
Short name T280
Test name
Test status
Simulation time 2251862106 ps
CPU time 22.96 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:53:56 PM PDT 24
Peak memory 220092 kb
Host smart-f4e9e00a-2d72-45b9-9851-7fb0e53b22c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692098399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1692098399
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1978684221
Short name T163
Test name
Test status
Simulation time 1017436338 ps
CPU time 11.92 seconds
Started Aug 05 04:53:37 PM PDT 24
Finished Aug 05 04:53:49 PM PDT 24
Peak memory 219940 kb
Host smart-bc695870-6877-4ac6-aa85-dd9c7c5852ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978684221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1978684221
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3125290126
Short name T190
Test name
Test status
Simulation time 1020268237 ps
CPU time 11.92 seconds
Started Aug 05 04:53:26 PM PDT 24
Finished Aug 05 04:53:38 PM PDT 24
Peak memory 220016 kb
Host smart-2b38f47f-9d21-420f-a4aa-916599d0239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125290126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3125290126
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1433308204
Short name T76
Test name
Test status
Simulation time 884513069 ps
CPU time 15.13 seconds
Started Aug 05 04:53:44 PM PDT 24
Finished Aug 05 04:53:59 PM PDT 24
Peak memory 220128 kb
Host smart-3d4236c6-0135-4d87-9fb0-b118ec63fe0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433308204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1433308204
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3036280464
Short name T321
Test name
Test status
Simulation time 101737756987 ps
CPU time 3953.8 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 05:59:30 PM PDT 24
Peak memory 252496 kb
Host smart-a5d8b908-a3e4-47b2-9204-09c726816260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036280464 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3036280464
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2401456687
Short name T146
Test name
Test status
Simulation time 989792002 ps
CPU time 10.05 seconds
Started Aug 05 04:53:39 PM PDT 24
Finished Aug 05 04:53:49 PM PDT 24
Peak memory 219676 kb
Host smart-2a8a964a-650e-41a9-8ff5-6c5f086e811c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401456687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2401456687
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2419033360
Short name T183
Test name
Test status
Simulation time 11747394155 ps
CPU time 187.25 seconds
Started Aug 05 04:53:36 PM PDT 24
Finished Aug 05 04:56:44 PM PDT 24
Peak memory 234772 kb
Host smart-afc9e66d-7947-47dc-a60c-bb10ec12d2e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419033360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2419033360
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2910833504
Short name T254
Test name
Test status
Simulation time 1318838816 ps
CPU time 19.32 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:53:53 PM PDT 24
Peak memory 220004 kb
Host smart-baa5d389-dc71-4d33-88ef-a8e31db76cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910833504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2910833504
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.297948239
Short name T221
Test name
Test status
Simulation time 1168672381 ps
CPU time 12.04 seconds
Started Aug 05 04:53:33 PM PDT 24
Finished Aug 05 04:53:45 PM PDT 24
Peak memory 220004 kb
Host smart-d752e14c-80d0-431b-8512-8c4f51f32907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297948239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.297948239
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1830049749
Short name T185
Test name
Test status
Simulation time 725690071 ps
CPU time 10.9 seconds
Started Aug 05 04:53:40 PM PDT 24
Finished Aug 05 04:53:51 PM PDT 24
Peak memory 219920 kb
Host smart-ac8b5bb3-cd4a-4ac1-9c9a-c45d32ff88c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830049749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1830049749
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3406386110
Short name T74
Test name
Test status
Simulation time 769745325 ps
CPU time 38.76 seconds
Started Aug 05 04:53:30 PM PDT 24
Finished Aug 05 04:54:08 PM PDT 24
Peak memory 219960 kb
Host smart-f061f898-9190-40a0-bf1c-03cae9c0df49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406386110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3406386110
Directory /workspace/9.rom_ctrl_stress_all/latest
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