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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 96.89 91.85 97.68 100.00 98.28 97.30 98.14


Total test records in report: 427
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T297 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2663248327 Aug 08 06:09:36 PM PDT 24 Aug 08 06:09:46 PM PDT 24 183950938 ps
T298 /workspace/coverage/default/1.rom_ctrl_stress_all.4280499710 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:42 PM PDT 24 551004105 ps
T299 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1468845513 Aug 08 06:09:34 PM PDT 24 Aug 08 06:12:09 PM PDT 24 63307834038 ps
T300 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.543674718 Aug 08 06:10:09 PM PDT 24 Aug 08 06:14:35 PM PDT 24 4496521569 ps
T301 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1715557773 Aug 08 06:09:17 PM PDT 24 Aug 08 06:09:36 PM PDT 24 691618547 ps
T302 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.261212546 Aug 08 06:09:47 PM PDT 24 Aug 08 06:09:59 PM PDT 24 1076784873 ps
T303 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.827060529 Aug 08 06:10:04 PM PDT 24 Aug 08 06:10:23 PM PDT 24 1648499199 ps
T304 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.220557574 Aug 08 06:09:52 PM PDT 24 Aug 08 06:10:14 PM PDT 24 2740354585 ps
T305 /workspace/coverage/default/20.rom_ctrl_stress_all.3858023556 Aug 08 06:09:37 PM PDT 24 Aug 08 06:09:54 PM PDT 24 292991535 ps
T306 /workspace/coverage/default/40.rom_ctrl_stress_all.740212969 Aug 08 06:10:03 PM PDT 24 Aug 08 06:10:23 PM PDT 24 230859103 ps
T307 /workspace/coverage/default/10.rom_ctrl_stress_all.3129094623 Aug 08 06:09:33 PM PDT 24 Aug 08 06:09:54 PM PDT 24 761020662 ps
T308 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1540071499 Aug 08 06:09:27 PM PDT 24 Aug 08 06:09:39 PM PDT 24 1023708664 ps
T309 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.936496864 Aug 08 06:10:00 PM PDT 24 Aug 08 06:21:43 PM PDT 24 19170450323 ps
T310 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1710361373 Aug 08 06:09:47 PM PDT 24 Aug 08 06:09:59 PM PDT 24 2146867462 ps
T311 /workspace/coverage/default/48.rom_ctrl_alert_test.1012131538 Aug 08 06:10:09 PM PDT 24 Aug 08 06:10:18 PM PDT 24 167380849 ps
T312 /workspace/coverage/default/17.rom_ctrl_alert_test.3768387756 Aug 08 06:09:30 PM PDT 24 Aug 08 06:09:39 PM PDT 24 691228814 ps
T313 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4292076533 Aug 08 06:09:23 PM PDT 24 Aug 08 06:13:14 PM PDT 24 3742385027 ps
T314 /workspace/coverage/default/43.rom_ctrl_alert_test.1114984862 Aug 08 06:10:02 PM PDT 24 Aug 08 06:10:10 PM PDT 24 345372263 ps
T315 /workspace/coverage/default/32.rom_ctrl_alert_test.2035192775 Aug 08 06:09:44 PM PDT 24 Aug 08 06:09:54 PM PDT 24 262705492 ps
T316 /workspace/coverage/default/4.rom_ctrl_stress_all.3361826781 Aug 08 06:09:18 PM PDT 24 Aug 08 06:09:43 PM PDT 24 1345399097 ps
T317 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1004416364 Aug 08 06:09:40 PM PDT 24 Aug 08 06:09:52 PM PDT 24 882707330 ps
T318 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.659433261 Aug 08 06:10:03 PM PDT 24 Aug 08 06:10:13 PM PDT 24 696354486 ps
T319 /workspace/coverage/default/38.rom_ctrl_stress_all.1919214197 Aug 08 06:09:54 PM PDT 24 Aug 08 06:10:18 PM PDT 24 2469185283 ps
T320 /workspace/coverage/default/8.rom_ctrl_alert_test.1374336481 Aug 08 06:09:29 PM PDT 24 Aug 08 06:09:38 PM PDT 24 332270184 ps
T321 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1176139815 Aug 08 06:09:53 PM PDT 24 Aug 08 06:38:07 PM PDT 24 160288971244 ps
T322 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1452113579 Aug 08 06:09:56 PM PDT 24 Aug 08 06:17:06 PM PDT 24 38768608670 ps
T323 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2188891939 Aug 08 06:09:34 PM PDT 24 Aug 08 06:14:13 PM PDT 24 13502172892 ps
T28 /workspace/coverage/default/3.rom_ctrl_sec_cm.113862366 Aug 08 06:09:23 PM PDT 24 Aug 08 06:13:11 PM PDT 24 546939654 ps
T324 /workspace/coverage/default/16.rom_ctrl_alert_test.1987538068 Aug 08 06:09:24 PM PDT 24 Aug 08 06:09:34 PM PDT 24 1078027067 ps
T325 /workspace/coverage/default/5.rom_ctrl_stress_all.3622780691 Aug 08 06:09:17 PM PDT 24 Aug 08 06:09:57 PM PDT 24 3341799198 ps
T326 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4131416699 Aug 08 06:09:23 PM PDT 24 Aug 08 06:09:35 PM PDT 24 272338442 ps
T327 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2968295680 Aug 08 06:09:25 PM PDT 24 Aug 08 06:09:36 PM PDT 24 186827645 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4208767480 Aug 08 06:08:53 PM PDT 24 Aug 08 06:09:02 PM PDT 24 342940318 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.116252010 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:56 PM PDT 24 4228603325 ps
T60 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.908221185 Aug 08 06:08:50 PM PDT 24 Aug 08 06:09:06 PM PDT 24 709504275 ps
T328 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3298854110 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:27 PM PDT 24 4082482547 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1804457799 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:17 PM PDT 24 7211773718 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3042765066 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:04 PM PDT 24 176063299 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3318060988 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:20 PM PDT 24 332533155 ps
T329 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2927412591 Aug 08 06:09:16 PM PDT 24 Aug 08 06:09:27 PM PDT 24 2036164655 ps
T54 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4015905982 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:34 PM PDT 24 5185663053 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2061998782 Aug 08 06:09:16 PM PDT 24 Aug 08 06:09:26 PM PDT 24 1037430893 ps
T68 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.856268128 Aug 08 06:09:09 PM PDT 24 Aug 08 06:09:17 PM PDT 24 789232887 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3913168224 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:23 PM PDT 24 257526619 ps
T330 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3198831627 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:22 PM PDT 24 177936585 ps
T55 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.380017294 Aug 08 06:09:10 PM PDT 24 Aug 08 06:10:34 PM PDT 24 311705175 ps
T94 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3699246054 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:21 PM PDT 24 253022663 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.469701196 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:03 PM PDT 24 1774686479 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.515772090 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:00 PM PDT 24 345602096 ps
T331 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.330191828 Aug 08 06:09:05 PM PDT 24 Aug 08 06:09:16 PM PDT 24 915956828 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3684097214 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:00 PM PDT 24 786689106 ps
T332 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.366278884 Aug 08 06:09:14 PM PDT 24 Aug 08 06:09:22 PM PDT 24 168039942 ps
T333 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1704182806 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:24 PM PDT 24 1025365477 ps
T334 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2822717820 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:26 PM PDT 24 4337097669 ps
T335 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2871062852 Aug 08 06:08:50 PM PDT 24 Aug 08 06:09:00 PM PDT 24 649397263 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1824672053 Aug 08 06:09:08 PM PDT 24 Aug 08 06:10:14 PM PDT 24 6916232817 ps
T336 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3408497906 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:19 PM PDT 24 3298657275 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1908930196 Aug 08 06:09:07 PM PDT 24 Aug 08 06:11:43 PM PDT 24 387241283 ps
T337 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2971903616 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:02 PM PDT 24 260999591 ps
T338 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2486485753 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:00 PM PDT 24 1766444031 ps
T339 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4034112270 Aug 08 06:08:50 PM PDT 24 Aug 08 06:09:04 PM PDT 24 664077887 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3857632958 Aug 08 06:09:00 PM PDT 24 Aug 08 06:11:39 PM PDT 24 968158536 ps
T340 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.373195807 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:22 PM PDT 24 265306220 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4167730684 Aug 08 06:09:04 PM PDT 24 Aug 08 06:09:14 PM PDT 24 3081213934 ps
T341 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.120000111 Aug 08 06:08:53 PM PDT 24 Aug 08 06:09:05 PM PDT 24 171152619 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3390992918 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:19 PM PDT 24 331897075 ps
T342 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2051958098 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:06 PM PDT 24 916818798 ps
T71 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.516309633 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:22 PM PDT 24 1030891125 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2141622132 Aug 08 06:09:06 PM PDT 24 Aug 08 06:09:16 PM PDT 24 995684222 ps
T343 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4216325733 Aug 08 06:09:06 PM PDT 24 Aug 08 06:09:16 PM PDT 24 359784483 ps
T344 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.37828689 Aug 08 06:08:58 PM PDT 24 Aug 08 06:09:08 PM PDT 24 190110755 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.717094013 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:35 PM PDT 24 347335595 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3151645618 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:01 PM PDT 24 257635695 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1021645572 Aug 08 06:09:13 PM PDT 24 Aug 08 06:10:34 PM PDT 24 912505750 ps
T111 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3906966315 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:36 PM PDT 24 348714064 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1124320641 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:22 PM PDT 24 578614098 ps
T345 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.114716776 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:23 PM PDT 24 994983215 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2726224066 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:58 PM PDT 24 4231570229 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4108612479 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:50 PM PDT 24 3132158158 ps
T83 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.336451999 Aug 08 06:09:07 PM PDT 24 Aug 08 06:10:13 PM PDT 24 1532300081 ps
T346 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2437373010 Aug 08 06:09:07 PM PDT 24 Aug 08 06:09:20 PM PDT 24 690978682 ps
T347 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.606336981 Aug 08 06:09:06 PM PDT 24 Aug 08 06:09:19 PM PDT 24 884713007 ps
T348 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.769126255 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:18 PM PDT 24 271307103 ps
T349 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1787310515 Aug 08 06:09:01 PM PDT 24 Aug 08 06:09:12 PM PDT 24 987759378 ps
T350 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3994610477 Aug 08 06:09:00 PM PDT 24 Aug 08 06:09:19 PM PDT 24 2018337556 ps
T351 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1763337051 Aug 08 06:09:14 PM PDT 24 Aug 08 06:09:22 PM PDT 24 660222002 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4097453820 Aug 08 06:09:14 PM PDT 24 Aug 08 06:09:22 PM PDT 24 692477565 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3218720603 Aug 08 06:09:06 PM PDT 24 Aug 08 06:11:41 PM PDT 24 786377322 ps
T352 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1201879068 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:21 PM PDT 24 484215546 ps
T353 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2528971510 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:19 PM PDT 24 167881173 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3177879776 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:47 PM PDT 24 12154108370 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3635585562 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:22 PM PDT 24 1001343613 ps
T355 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1509007831 Aug 08 06:09:16 PM PDT 24 Aug 08 06:09:26 PM PDT 24 478421784 ps
T356 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3872003539 Aug 08 06:09:05 PM PDT 24 Aug 08 06:09:13 PM PDT 24 172835880 ps
T357 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1558451359 Aug 08 06:08:49 PM PDT 24 Aug 08 06:09:00 PM PDT 24 479799027 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2555391062 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:03 PM PDT 24 220691485 ps
T359 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2914175346 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:25 PM PDT 24 256269006 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3658056950 Aug 08 06:09:10 PM PDT 24 Aug 08 06:11:45 PM PDT 24 1543312202 ps
T360 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3245808495 Aug 08 06:09:09 PM PDT 24 Aug 08 06:09:54 PM PDT 24 1052811061 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4257847216 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:36 PM PDT 24 1054110376 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1459449373 Aug 08 06:09:06 PM PDT 24 Aug 08 06:09:23 PM PDT 24 500666753 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3401450046 Aug 08 06:08:49 PM PDT 24 Aug 08 06:08:59 PM PDT 24 356337741 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2295527718 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:37 PM PDT 24 1017456749 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1243896674 Aug 08 06:09:05 PM PDT 24 Aug 08 06:09:13 PM PDT 24 169089416 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2874404478 Aug 08 06:08:57 PM PDT 24 Aug 08 06:09:11 PM PDT 24 1750870955 ps
T108 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2217295216 Aug 08 06:09:08 PM PDT 24 Aug 08 06:11:42 PM PDT 24 1549876344 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3489502454 Aug 08 06:09:09 PM PDT 24 Aug 08 06:09:20 PM PDT 24 257898233 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1554335950 Aug 08 06:09:14 PM PDT 24 Aug 08 06:09:30 PM PDT 24 4124137966 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2298889640 Aug 08 06:08:57 PM PDT 24 Aug 08 06:09:06 PM PDT 24 167960051 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.591231437 Aug 08 06:09:09 PM PDT 24 Aug 08 06:10:16 PM PDT 24 6358282227 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.67798504 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:22 PM PDT 24 195058150 ps
T370 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1660049215 Aug 08 06:09:01 PM PDT 24 Aug 08 06:09:10 PM PDT 24 689002811 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2565008389 Aug 08 06:09:01 PM PDT 24 Aug 08 06:09:12 PM PDT 24 1019651072 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2199416177 Aug 08 06:08:59 PM PDT 24 Aug 08 06:09:16 PM PDT 24 1037444489 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2227609208 Aug 08 06:09:16 PM PDT 24 Aug 08 06:11:51 PM PDT 24 321365757 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.746498492 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:24 PM PDT 24 167306036 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3323455094 Aug 08 06:09:29 PM PDT 24 Aug 08 06:09:37 PM PDT 24 174647291 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1785023998 Aug 08 06:09:16 PM PDT 24 Aug 08 06:09:30 PM PDT 24 257276703 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.472703846 Aug 08 06:09:03 PM PDT 24 Aug 08 06:09:13 PM PDT 24 1128372554 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1467595329 Aug 08 06:09:02 PM PDT 24 Aug 08 06:09:12 PM PDT 24 249425233 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3367608512 Aug 08 06:09:04 PM PDT 24 Aug 08 06:09:14 PM PDT 24 406619436 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3397703552 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:18 PM PDT 24 989343262 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3980509132 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:23 PM PDT 24 825866988 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.713657475 Aug 08 06:08:53 PM PDT 24 Aug 08 06:11:30 PM PDT 24 458378559 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4106433022 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:24 PM PDT 24 368099878 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3807890035 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:29 PM PDT 24 262298134 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.272785843 Aug 08 06:08:49 PM PDT 24 Aug 08 06:09:27 PM PDT 24 692983297 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.878724769 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:24 PM PDT 24 264872862 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2499707723 Aug 08 06:09:11 PM PDT 24 Aug 08 06:11:49 PM PDT 24 452887725 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1962534889 Aug 08 06:08:59 PM PDT 24 Aug 08 06:09:07 PM PDT 24 168354640 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.37122847 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:08 PM PDT 24 1079850257 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1755550417 Aug 08 06:09:00 PM PDT 24 Aug 08 06:09:13 PM PDT 24 317122523 ps
T388 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.185760468 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:23 PM PDT 24 499716176 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2709450587 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:23 PM PDT 24 252962826 ps
T390 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1872640734 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:30 PM PDT 24 997515277 ps
T391 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.585768057 Aug 08 06:09:08 PM PDT 24 Aug 08 06:10:41 PM PDT 24 434737571 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3129235317 Aug 08 06:08:59 PM PDT 24 Aug 08 06:09:11 PM PDT 24 347468668 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2959857551 Aug 08 06:09:08 PM PDT 24 Aug 08 06:10:30 PM PDT 24 673149768 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3721406075 Aug 08 06:08:50 PM PDT 24 Aug 08 06:09:03 PM PDT 24 249885696 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2611168258 Aug 08 06:09:09 PM PDT 24 Aug 08 06:09:20 PM PDT 24 175120900 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2198895420 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:22 PM PDT 24 221899177 ps
T397 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2151333667 Aug 08 06:09:13 PM PDT 24 Aug 08 06:09:21 PM PDT 24 170662797 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2979129169 Aug 08 06:08:56 PM PDT 24 Aug 08 06:11:31 PM PDT 24 1389436446 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.561948916 Aug 08 06:09:01 PM PDT 24 Aug 08 06:09:57 PM PDT 24 2059426235 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4124569414 Aug 08 06:09:13 PM PDT 24 Aug 08 06:11:52 PM PDT 24 1106631284 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3963645914 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:25 PM PDT 24 703422197 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.749126624 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:23 PM PDT 24 993222538 ps
T403 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.30798968 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:25 PM PDT 24 1340994464 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1628867540 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:48 PM PDT 24 2857686928 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.395177578 Aug 08 06:09:06 PM PDT 24 Aug 08 06:09:17 PM PDT 24 276315405 ps
T92 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3667629384 Aug 08 06:09:01 PM PDT 24 Aug 08 06:09:38 PM PDT 24 3121006280 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2981948580 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:47 PM PDT 24 20502055786 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1022129163 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:19 PM PDT 24 339103278 ps
T406 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2015112691 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:17 PM PDT 24 2284591790 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3034663191 Aug 08 06:09:12 PM PDT 24 Aug 08 06:09:22 PM PDT 24 250573417 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.261053493 Aug 08 06:08:54 PM PDT 24 Aug 08 06:09:05 PM PDT 24 1108677636 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1429301979 Aug 08 06:09:04 PM PDT 24 Aug 08 06:09:13 PM PDT 24 612349956 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.309434780 Aug 08 06:08:52 PM PDT 24 Aug 08 06:09:00 PM PDT 24 688561697 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1700106573 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:28 PM PDT 24 169354885 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4292824069 Aug 08 06:08:57 PM PDT 24 Aug 08 06:09:10 PM PDT 24 173624608 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1337531300 Aug 08 06:09:11 PM PDT 24 Aug 08 06:09:19 PM PDT 24 333687438 ps
T414 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4008894529 Aug 08 06:09:08 PM PDT 24 Aug 08 06:09:21 PM PDT 24 176545136 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.694791646 Aug 08 06:08:51 PM PDT 24 Aug 08 06:09:00 PM PDT 24 167403353 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3924338003 Aug 08 06:08:53 PM PDT 24 Aug 08 06:09:03 PM PDT 24 274512603 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1454813198 Aug 08 06:09:10 PM PDT 24 Aug 08 06:11:44 PM PDT 24 1048456046 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4014822440 Aug 08 06:09:05 PM PDT 24 Aug 08 06:09:13 PM PDT 24 661412246 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2676739842 Aug 08 06:09:15 PM PDT 24 Aug 08 06:09:26 PM PDT 24 591247022 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1828216645 Aug 08 06:08:57 PM PDT 24 Aug 08 06:09:06 PM PDT 24 690935357 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3236491650 Aug 08 06:08:52 PM PDT 24 Aug 08 06:11:30 PM PDT 24 388348966 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3820144178 Aug 08 06:08:53 PM PDT 24 Aug 08 06:09:01 PM PDT 24 167479389 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2365556415 Aug 08 06:09:05 PM PDT 24 Aug 08 06:09:14 PM PDT 24 713551466 ps
T423 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2700777484 Aug 08 06:09:11 PM PDT 24 Aug 08 06:10:31 PM PDT 24 919523454 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.454892131 Aug 08 06:09:12 PM PDT 24 Aug 08 06:10:08 PM PDT 24 1118852672 ps
T424 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3080280705 Aug 08 06:09:19 PM PDT 24 Aug 08 06:10:03 PM PDT 24 4244452955 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2799050289 Aug 08 06:09:10 PM PDT 24 Aug 08 06:09:18 PM PDT 24 171377707 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.728044873 Aug 08 06:09:12 PM PDT 24 Aug 08 06:10:09 PM PDT 24 1064233910 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2292765861 Aug 08 06:09:09 PM PDT 24 Aug 08 06:09:17 PM PDT 24 1270365166 ps

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.666696372
Short name T7
Test name
Test status
Simulation time 35291004163 ps
CPU time 1326.5 seconds
Started Aug 08 06:10:10 PM PDT 24
Finished Aug 08 06:32:17 PM PDT 24
Peak memory 234228 kb
Host smart-2d75b3ff-54b6-4dbc-be39-ca5679ae819f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666696372 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.666696372
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2625575316
Short name T2
Test name
Test status
Simulation time 28146540724 ps
CPU time 407.17 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:16:07 PM PDT 24
Peak memory 239864 kb
Host smart-8f518c5d-0426-4d2e-976e-577fac2cccdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625575316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2625575316
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1607681997
Short name T45
Test name
Test status
Simulation time 12400694134 ps
CPU time 302.72 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:14:36 PM PDT 24
Peak memory 220372 kb
Host smart-e020bf2a-0fc0-4355-8e55-0f1a548c503f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607681997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1607681997
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3857632958
Short name T107
Test name
Test status
Simulation time 968158536 ps
CPU time 158.95 seconds
Started Aug 08 06:09:00 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 214680 kb
Host smart-21c1e9ea-1a3f-4abd-9b6a-789c95126358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857632958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3857632958
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4055965522
Short name T16
Test name
Test status
Simulation time 211567515 ps
CPU time 14.8 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 219988 kb
Host smart-06b1c594-8328-4417-9a01-ffb94b3ce5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055965522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4055965522
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2813886081
Short name T21
Test name
Test status
Simulation time 1033413839 ps
CPU time 226.4 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:13:00 PM PDT 24
Peak memory 235744 kb
Host smart-88670151-8e76-46e6-b7d6-8bc77548c2fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813886081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2813886081
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1804457799
Short name T65
Test name
Test status
Simulation time 7211773718 ps
CPU time 65.84 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:17 PM PDT 24
Peak memory 216640 kb
Host smart-86916c8d-3472-4b64-8452-76e6ce507121
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804457799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1804457799
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.713657475
Short name T110
Test name
Test status
Simulation time 458378559 ps
CPU time 156.43 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:11:30 PM PDT 24
Peak memory 214904 kb
Host smart-a9c27d94-0b0b-4c9f-b382-5d4953ee8739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713657475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.713657475
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.404248302
Short name T63
Test name
Test status
Simulation time 4115214302 ps
CPU time 15.22 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 219192 kb
Host smart-c17abdf4-0474-4a27-b6ae-edef6a392faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404248302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.404248302
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4170029078
Short name T73
Test name
Test status
Simulation time 562214841 ps
CPU time 31.36 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:10:04 PM PDT 24
Peak memory 220048 kb
Host smart-37fd772d-85b7-4039-8f91-ef5880e15b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170029078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4170029078
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3724725996
Short name T127
Test name
Test status
Simulation time 2058935436 ps
CPU time 22.36 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 220008 kb
Host smart-da9a161f-40f5-4d02-9c27-c117833e81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724725996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3724725996
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3197446872
Short name T43
Test name
Test status
Simulation time 345696422 ps
CPU time 19.34 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 220292 kb
Host smart-90f0f07e-4425-4ddf-ad93-22efd099ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197446872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3197446872
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2217295216
Short name T108
Test name
Test status
Simulation time 1549876344 ps
CPU time 153.86 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 214656 kb
Host smart-0166f3bc-4b2e-42c0-a221-fb65ac1abe30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217295216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2217295216
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.694791646
Short name T88
Test name
Test status
Simulation time 167403353 ps
CPU time 8.29 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211440 kb
Host smart-f8edc437-f602-4abb-ad72-f64360dccf2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694791646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.694791646
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.272785843
Short name T383
Test name
Test status
Simulation time 692983297 ps
CPU time 37.57 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 214384 kb
Host smart-7e8fe135-5812-4f15-83b3-7c8099264d80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272785843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.272785843
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4015905982
Short name T54
Test name
Test status
Simulation time 5185663053 ps
CPU time 82.12 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 215592 kb
Host smart-61ef3a9b-6a5d-4b37-8ebe-a4fa9de9d771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015905982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4015905982
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2513027961
Short name T184
Test name
Test status
Simulation time 49781334665 ps
CPU time 59.35 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 220140 kb
Host smart-399c1416-338c-4fef-86d0-9205d9367fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513027961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2513027961
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2871062852
Short name T335
Test name
Test status
Simulation time 649397263 ps
CPU time 10.2 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211528 kb
Host smart-0b8489ec-51e3-4ead-8ad5-51bf1271b0cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871062852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2871062852
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.908221185
Short name T60
Test name
Test status
Simulation time 709504275 ps
CPU time 15.7 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:09:06 PM PDT 24
Peak memory 212812 kb
Host smart-6f77c998-f723-4326-9886-8df3c46890f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908221185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.908221185
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4208767480
Short name T58
Test name
Test status
Simulation time 342940318 ps
CPU time 9.26 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:09:02 PM PDT 24
Peak memory 217100 kb
Host smart-98a2ce81-f4b5-4b76-b8f0-c5e11bd1647b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208767480 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4208767480
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1828216645
Short name T419
Test name
Test status
Simulation time 690935357 ps
CPU time 8 seconds
Started Aug 08 06:08:57 PM PDT 24
Finished Aug 08 06:09:06 PM PDT 24
Peak memory 211724 kb
Host smart-7c46bc2c-c9a2-41cd-be7f-6f12152bad23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828216645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1828216645
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.309434780
Short name T410
Test name
Test status
Simulation time 688561697 ps
CPU time 8.35 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211252 kb
Host smart-a99e2cc4-83a4-4e60-a9e2-00fa87652c9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309434780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.309434780
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3820144178
Short name T421
Test name
Test status
Simulation time 167479389 ps
CPU time 8.15 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:09:01 PM PDT 24
Peak memory 211192 kb
Host smart-4b91ae5a-c30d-4a3d-b4ab-7d05820870fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820144178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3820144178
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3151645618
Short name T99
Test name
Test status
Simulation time 257635695 ps
CPU time 10.35 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:01 PM PDT 24
Peak memory 211980 kb
Host smart-c1f330ed-d6fd-4091-816e-d4a851720a04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151645618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3151645618
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2051958098
Short name T342
Test name
Test status
Simulation time 916818798 ps
CPU time 13.11 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:06 PM PDT 24
Peak memory 218100 kb
Host smart-c8a91d22-6ca4-47c9-aae1-be63c25f325f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051958098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2051958098
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3924338003
Short name T415
Test name
Test status
Simulation time 274512603 ps
CPU time 10 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:09:03 PM PDT 24
Peak memory 211500 kb
Host smart-b90b2d70-a20c-4ad1-ae37-627def37deff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924338003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3924338003
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2971903616
Short name T337
Test name
Test status
Simulation time 260999591 ps
CPU time 10.13 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:02 PM PDT 24
Peak memory 211324 kb
Host smart-5f93060a-75e1-43cf-9ea2-8da38dfd0b4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971903616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2971903616
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2555391062
Short name T358
Test name
Test status
Simulation time 220691485 ps
CPU time 11.77 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:03 PM PDT 24
Peak memory 211296 kb
Host smart-14616d17-b1cf-420d-83e1-1ecc96605551
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555391062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2555391062
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.261053493
Short name T408
Test name
Test status
Simulation time 1108677636 ps
CPU time 10.93 seconds
Started Aug 08 06:08:54 PM PDT 24
Finished Aug 08 06:09:05 PM PDT 24
Peak memory 217784 kb
Host smart-bb64ad70-4fdc-45ca-a210-bc40a9245762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261053493 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.261053493
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.515772090
Short name T95
Test name
Test status
Simulation time 345602096 ps
CPU time 8.14 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211528 kb
Host smart-643a4177-75ba-4117-90eb-22d8daca49f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515772090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.515772090
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2292765861
Short name T427
Test name
Test status
Simulation time 1270365166 ps
CPU time 8.18 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 211264 kb
Host smart-afee15ad-410e-4882-a5c1-7bb43e419e94
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292765861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2292765861
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3401450046
Short name T363
Test name
Test status
Simulation time 356337741 ps
CPU time 9.92 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:08:59 PM PDT 24
Peak memory 211412 kb
Host smart-fe12d296-2359-43bb-981b-d26fb87f4ec4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401450046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3401450046
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4257847216
Short name T361
Test name
Test status
Simulation time 1054110376 ps
CPU time 43.64 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 214468 kb
Host smart-a6616956-762a-4afb-99a7-d59961b706d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257847216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4257847216
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1558451359
Short name T357
Test name
Test status
Simulation time 479799027 ps
CPU time 9.98 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211900 kb
Host smart-b333490e-7f67-4276-b3c9-5fa558fc49b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558451359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1558451359
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.120000111
Short name T341
Test name
Test status
Simulation time 171152619 ps
CPU time 11.53 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:09:05 PM PDT 24
Peak memory 217516 kb
Host smart-6cffa988-86d5-4ae9-a896-16aac5d8aad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120000111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.120000111
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3236491650
Short name T420
Test name
Test status
Simulation time 388348966 ps
CPU time 157.9 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:11:30 PM PDT 24
Peak memory 214932 kb
Host smart-e6542c8e-5487-4d3c-b338-d44a2ba7cfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236491650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3236491650
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.373195807
Short name T340
Test name
Test status
Simulation time 265306220 ps
CPU time 9.89 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 214452 kb
Host smart-e25bc5ea-bb71-466f-9ac3-f3c6bf4b47f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373195807 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.373195807
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3408497906
Short name T336
Test name
Test status
Simulation time 3298657275 ps
CPU time 8.26 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 211620 kb
Host smart-f6b50e2f-8ab2-4659-b0bc-a856684d8770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408497906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3408497906
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.37122847
Short name T85
Test name
Test status
Simulation time 1079850257 ps
CPU time 57.42 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 219084 kb
Host smart-b0a3a237-b2ef-4099-87cb-4186d20a14af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pas
sthru_mem_tl_intg_err.37122847
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.746498492
Short name T373
Test name
Test status
Simulation time 167306036 ps
CPU time 8.06 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 211696 kb
Host smart-3cf7e7fa-2334-4ac9-8599-9da8b5587f82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746498492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.746498492
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3963645914
Short name T401
Test name
Test status
Simulation time 703422197 ps
CPU time 12.25 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:25 PM PDT 24
Peak memory 217176 kb
Host smart-4926914c-ed56-4bbd-9de7-1f9f00b50e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963645914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3963645914
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2822717820
Short name T334
Test name
Test status
Simulation time 4337097669 ps
CPU time 16.08 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:26 PM PDT 24
Peak memory 218444 kb
Host smart-362f60dc-1622-4c8a-a86a-cf2f97e12ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822717820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2822717820
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3318060988
Short name T67
Test name
Test status
Simulation time 332533155 ps
CPU time 7.92 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:20 PM PDT 24
Peak memory 211280 kb
Host smart-7ded8838-c5c3-4611-a815-4e64123315e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318060988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3318060988
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4108612479
Short name T82
Test name
Test status
Simulation time 3132158158 ps
CPU time 37.69 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 214768 kb
Host smart-3b66afe2-888b-4025-aabd-7d6299a53ef0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108612479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4108612479
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1872640734
Short name T390
Test name
Test status
Simulation time 997515277 ps
CPU time 18.37 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 213252 kb
Host smart-30d72573-6396-4286-9edd-fdf0a35f75c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872640734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1872640734
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2914175346
Short name T359
Test name
Test status
Simulation time 256269006 ps
CPU time 14.7 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:25 PM PDT 24
Peak memory 219432 kb
Host smart-f101bdaa-b31b-4c05-a328-f18074baf3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914175346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2914175346
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.717094013
Short name T114
Test name
Test status
Simulation time 347335595 ps
CPU time 83.41 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:35 PM PDT 24
Peak memory 214616 kb
Host smart-b131e8bb-3178-4fb6-a5fe-31d9b7be25f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717094013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.717094013
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3489502454
Short name T366
Test name
Test status
Simulation time 257898233 ps
CPU time 10.5 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:09:20 PM PDT 24
Peak memory 215848 kb
Host smart-6a83da38-1af6-4d79-ace1-9f8781af6942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489502454 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3489502454
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2799050289
Short name T425
Test name
Test status
Simulation time 171377707 ps
CPU time 8.22 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:18 PM PDT 24
Peak memory 211444 kb
Host smart-73e03ba3-1544-4e30-a0c8-c68f2b602ba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799050289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2799050289
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.728044873
Short name T426
Test name
Test status
Simulation time 1064233910 ps
CPU time 56.52 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 214628 kb
Host smart-1ada333b-eaa2-4302-aa1f-939c06b79e5c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728044873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.728044873
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1337531300
Short name T413
Test name
Test status
Simulation time 333687438 ps
CPU time 8.32 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 211944 kb
Host smart-946fdaeb-41a4-4e2f-b914-c73dca39b211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337531300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1337531300
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.114716776
Short name T345
Test name
Test status
Simulation time 994983215 ps
CPU time 13.78 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 219276 kb
Host smart-9962a6fb-ab23-475f-981d-bb74c2f8a4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114716776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.114716776
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1454813198
Short name T416
Test name
Test status
Simulation time 1048456046 ps
CPU time 154.75 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 215872 kb
Host smart-a13b1850-a908-4fc4-999d-ba90614baaec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454813198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1454813198
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4106433022
Short name T381
Test name
Test status
Simulation time 368099878 ps
CPU time 8.71 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 216788 kb
Host smart-8aaeecba-6f63-48cd-8b24-e0bdff25da5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106433022 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4106433022
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3699246054
Short name T94
Test name
Test status
Simulation time 253022663 ps
CPU time 9.65 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:21 PM PDT 24
Peak memory 211492 kb
Host smart-3a0ae64a-819c-4d2d-b595-5fd66a5efae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699246054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3699246054
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3177879776
Short name T91
Test name
Test status
Simulation time 12154108370 ps
CPU time 95.18 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:47 PM PDT 24
Peak memory 216784 kb
Host smart-b4148660-3bc1-4a22-8e76-975b94576d67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177879776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3177879776
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3034663191
Short name T407
Test name
Test status
Simulation time 250573417 ps
CPU time 9.79 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 212228 kb
Host smart-ad2d5edb-2cfc-4bed-a311-b34fd4e8d4d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034663191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3034663191
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1554335950
Short name T367
Test name
Test status
Simulation time 4124137966 ps
CPU time 15.91 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 219580 kb
Host smart-47373b84-4df7-438e-95dd-34dc548a4bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554335950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1554335950
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3635585562
Short name T354
Test name
Test status
Simulation time 1001343613 ps
CPU time 9.77 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 214212 kb
Host smart-9add328e-75d9-43d4-bd13-ab1a410c689a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635585562 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3635585562
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1022129163
Short name T405
Test name
Test status
Simulation time 339103278 ps
CPU time 8.06 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 211416 kb
Host smart-d57332ca-d2d1-4e8e-8ba7-c6c654186c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022129163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1022129163
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1124320641
Short name T100
Test name
Test status
Simulation time 578614098 ps
CPU time 9.7 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 212012 kb
Host smart-1a9b39c0-a252-4404-99bc-98011b392774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124320641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1124320641
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3980509132
Short name T380
Test name
Test status
Simulation time 825866988 ps
CPU time 11.59 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 218088 kb
Host smart-dc201a36-183d-40f4-9bf1-d951cd9055c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980509132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3980509132
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2499707723
Short name T385
Test name
Test status
Simulation time 452887725 ps
CPU time 157.4 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 214848 kb
Host smart-5fb4da23-adde-4b76-b9ff-e5e40e35372a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499707723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2499707723
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2198895420
Short name T396
Test name
Test status
Simulation time 221899177 ps
CPU time 8.58 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 215556 kb
Host smart-baae190f-05ca-4fd4-adc5-c0e39b615f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198895420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2198895420
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3913168224
Short name T93
Test name
Test status
Simulation time 257526619 ps
CPU time 9.8 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 211464 kb
Host smart-ed5ffb43-5ebc-4f23-a919-265155a8710c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913168224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3913168224
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.591231437
Short name T104
Test name
Test status
Simulation time 6358282227 ps
CPU time 66.52 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 215532 kb
Host smart-378ed620-a770-4075-a8be-120983dd8a28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591231437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.591231437
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2528971510
Short name T353
Test name
Test status
Simulation time 167881173 ps
CPU time 8.3 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 212020 kb
Host smart-e64ce786-3211-4b58-97e4-93f606cdfb38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528971510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2528971510
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1700106573
Short name T411
Test name
Test status
Simulation time 169354885 ps
CPU time 11.91 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:28 PM PDT 24
Peak memory 218292 kb
Host smart-28ed3bd2-6212-4143-87be-c36078206a40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700106573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1700106573
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3906966315
Short name T111
Test name
Test status
Simulation time 348714064 ps
CPU time 84.82 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:36 PM PDT 24
Peak memory 213572 kb
Host smart-4959452f-ff7f-4b03-81da-ab4ec5e3116d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906966315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3906966315
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.30798968
Short name T403
Test name
Test status
Simulation time 1340994464 ps
CPU time 8.79 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:25 PM PDT 24
Peak memory 216260 kb
Host smart-308bd2fd-c0c0-47a6-9c45-4d3f95f1533b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30798968 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.30798968
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.516309633
Short name T71
Test name
Test status
Simulation time 1030891125 ps
CPU time 9.69 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 211440 kb
Host smart-8a4dd6a6-e36b-4891-b4a5-e440613cc66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516309633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.516309633
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.116252010
Short name T59
Test name
Test status
Simulation time 4228603325 ps
CPU time 44.19 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:56 PM PDT 24
Peak memory 215604 kb
Host smart-c385aa23-2a6e-450c-84ab-8386eb03b7e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116252010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.116252010
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3807890035
Short name T382
Test name
Test status
Simulation time 262298134 ps
CPU time 13.46 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 213312 kb
Host smart-eb065660-fb5f-4017-940d-ce74fa1f7db4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807890035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3807890035
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1704182806
Short name T333
Test name
Test status
Simulation time 1025365477 ps
CPU time 13.7 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 217908 kb
Host smart-81f745de-67d6-4eee-b725-56f898247488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704182806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1704182806
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2700777484
Short name T423
Test name
Test status
Simulation time 919523454 ps
CPU time 78.94 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 214352 kb
Host smart-cc870e59-8d10-44fa-b27f-d2e410eb3dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700777484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2700777484
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1201879068
Short name T352
Test name
Test status
Simulation time 484215546 ps
CPU time 9.88 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:21 PM PDT 24
Peak memory 214736 kb
Host smart-827ef996-a21c-46fe-97ee-9ee6dfa3fa0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201879068 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1201879068
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.366278884
Short name T332
Test name
Test status
Simulation time 168039942 ps
CPU time 8.12 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 211536 kb
Host smart-db0c538b-68d0-48ed-9bd8-2a7328859e08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366278884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.366278884
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.454892131
Short name T90
Test name
Test status
Simulation time 1118852672 ps
CPU time 55.95 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 215772 kb
Host smart-1e442b93-b148-4d3e-8621-14104776c13d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454892131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.454892131
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2151333667
Short name T397
Test name
Test status
Simulation time 170662797 ps
CPU time 8.32 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:21 PM PDT 24
Peak memory 212176 kb
Host smart-c0c176fb-cf92-4b2e-ba68-1822d0cf29ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151333667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2151333667
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.878724769
Short name T384
Test name
Test status
Simulation time 264872862 ps
CPU time 13.04 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 218172 kb
Host smart-9bf315f7-2bbd-48d7-8df3-a6db246ef903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878724769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.878724769
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4124569414
Short name T400
Test name
Test status
Simulation time 1106631284 ps
CPU time 159.25 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 214852 kb
Host smart-df50af24-2f15-4cb3-8b20-fbb29d90eaf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124569414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4124569414
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2927412591
Short name T329
Test name
Test status
Simulation time 2036164655 ps
CPU time 10.86 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 218092 kb
Host smart-4f4c510e-4295-453e-ba7e-148e2f970683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927412591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2927412591
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3323455094
Short name T374
Test name
Test status
Simulation time 174647291 ps
CPU time 8.23 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:37 PM PDT 24
Peak memory 211504 kb
Host smart-bf9df7e4-a362-4ba1-8075-523a92ec802b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323455094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3323455094
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2726224066
Short name T81
Test name
Test status
Simulation time 4231570229 ps
CPU time 44.52 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:58 PM PDT 24
Peak memory 214944 kb
Host smart-70fc1fef-d33b-43f1-9cd1-ae1734b94c28
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726224066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2726224066
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1785023998
Short name T375
Test name
Test status
Simulation time 257276703 ps
CPU time 13.73 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 213120 kb
Host smart-a45521af-008b-40d6-b61d-0c13c35b4bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785023998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1785023998
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.749126624
Short name T402
Test name
Test status
Simulation time 993222538 ps
CPU time 13.27 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 218180 kb
Host smart-be478ce8-7a53-4dea-b31e-9e2383bc3aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749126624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.749126624
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.585768057
Short name T391
Test name
Test status
Simulation time 434737571 ps
CPU time 82.75 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:10:41 PM PDT 24
Peak memory 214524 kb
Host smart-cb2ec099-f821-4d6a-8132-a870ab5ff667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585768057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.585768057
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2015112691
Short name T406
Test name
Test status
Simulation time 2284591790 ps
CPU time 9.07 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 217788 kb
Host smart-6b26671b-4e0a-4c88-ba97-24ed508dfade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015112691 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2015112691
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2061998782
Short name T101
Test name
Test status
Simulation time 1037430893 ps
CPU time 9.87 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:26 PM PDT 24
Peak memory 211740 kb
Host smart-ca1cfb92-b2e0-4df2-988d-e267d7644b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061998782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2061998782
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3080280705
Short name T424
Test name
Test status
Simulation time 4244452955 ps
CPU time 44.52 seconds
Started Aug 08 06:09:19 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 214672 kb
Host smart-8f9ccc74-165c-4676-95c3-807417c5b906
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080280705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3080280705
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1509007831
Short name T355
Test name
Test status
Simulation time 478421784 ps
CPU time 9.92 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:26 PM PDT 24
Peak memory 212024 kb
Host smart-c08aa2d1-6797-4ec7-ba52-f2248801ffec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509007831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1509007831
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2676739842
Short name T418
Test name
Test status
Simulation time 591247022 ps
CPU time 10.52 seconds
Started Aug 08 06:09:15 PM PDT 24
Finished Aug 08 06:09:26 PM PDT 24
Peak memory 217892 kb
Host smart-12eda361-4f0c-49f6-9572-d9050393eb37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676739842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2676739842
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1021645572
Short name T113
Test name
Test status
Simulation time 912505750 ps
CPU time 81.34 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 214440 kb
Host smart-16f20326-4e9d-470e-bb40-df1a0fdad79e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021645572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1021645572
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2298889640
Short name T368
Test name
Test status
Simulation time 167960051 ps
CPU time 8.05 seconds
Started Aug 08 06:08:57 PM PDT 24
Finished Aug 08 06:09:06 PM PDT 24
Peak memory 211436 kb
Host smart-2f9b02ef-d635-4691-aa4c-020b883aa805
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298889640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2298889640
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2874404478
Short name T365
Test name
Test status
Simulation time 1750870955 ps
CPU time 14.17 seconds
Started Aug 08 06:08:57 PM PDT 24
Finished Aug 08 06:09:11 PM PDT 24
Peak memory 211368 kb
Host smart-f147a16b-9ade-4a59-9ed0-856260e33b5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874404478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2874404478
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3042765066
Short name T66
Test name
Test status
Simulation time 176063299 ps
CPU time 11.8 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:04 PM PDT 24
Peak memory 211320 kb
Host smart-c40d8126-f7d1-4938-898d-877f20b6ba4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042765066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3042765066
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.37828689
Short name T344
Test name
Test status
Simulation time 190110755 ps
CPU time 9.92 seconds
Started Aug 08 06:08:58 PM PDT 24
Finished Aug 08 06:09:08 PM PDT 24
Peak memory 218224 kb
Host smart-600cb895-6fc2-4090-b4ad-5ae99bafa8aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37828689 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.37828689
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.469701196
Short name T69
Test name
Test status
Simulation time 1774686479 ps
CPU time 10.09 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:03 PM PDT 24
Peak memory 211976 kb
Host smart-7e4cd7ab-48f3-47f7-bf58-e50d3f3b3b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469701196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.469701196
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4034112270
Short name T339
Test name
Test status
Simulation time 664077887 ps
CPU time 8.34 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:09:04 PM PDT 24
Peak memory 211216 kb
Host smart-fc2e669f-edd0-4a0b-877c-39da6a59fac3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034112270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4034112270
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2486485753
Short name T338
Test name
Test status
Simulation time 1766444031 ps
CPU time 9.89 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 211220 kb
Host smart-dbc6d70f-f8ef-4958-87c5-1263bba5a952
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486485753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2486485753
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2295527718
Short name T89
Test name
Test status
Simulation time 1017456749 ps
CPU time 45.05 seconds
Started Aug 08 06:08:52 PM PDT 24
Finished Aug 08 06:09:37 PM PDT 24
Peak memory 214532 kb
Host smart-89f45d8d-a626-4d5f-b2fc-2cb89cb5c5a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295527718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2295527718
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3684097214
Short name T96
Test name
Test status
Simulation time 786689106 ps
CPU time 8.34 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:00 PM PDT 24
Peak memory 212104 kb
Host smart-e801abb1-4894-4637-bd95-e12605773a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684097214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3684097214
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4292824069
Short name T412
Test name
Test status
Simulation time 173624608 ps
CPU time 13.14 seconds
Started Aug 08 06:08:57 PM PDT 24
Finished Aug 08 06:09:10 PM PDT 24
Peak memory 219284 kb
Host smart-9f68030f-26cc-4118-8819-509a468b8190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292824069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4292824069
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2979129169
Short name T398
Test name
Test status
Simulation time 1389436446 ps
CPU time 154.34 seconds
Started Aug 08 06:08:56 PM PDT 24
Finished Aug 08 06:11:31 PM PDT 24
Peak memory 214736 kb
Host smart-04528707-6de5-4b0a-ba7b-74917bbf24ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979129169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2979129169
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1962534889
Short name T386
Test name
Test status
Simulation time 168354640 ps
CPU time 8.24 seconds
Started Aug 08 06:08:59 PM PDT 24
Finished Aug 08 06:09:07 PM PDT 24
Peak memory 211484 kb
Host smart-7d95151f-84f2-4877-9bee-a5dea9a4eebc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962534889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1962534889
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1467595329
Short name T377
Test name
Test status
Simulation time 249425233 ps
CPU time 10.26 seconds
Started Aug 08 06:09:02 PM PDT 24
Finished Aug 08 06:09:12 PM PDT 24
Peak memory 211228 kb
Host smart-6fcd3688-543c-4f48-afd8-814b0043bac4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467595329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1467595329
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1459449373
Short name T362
Test name
Test status
Simulation time 500666753 ps
CPU time 17.19 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 212812 kb
Host smart-a328ce36-aa8d-4960-adb7-5a81dbd43654
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459449373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1459449373
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2365556415
Short name T422
Test name
Test status
Simulation time 713551466 ps
CPU time 9.46 seconds
Started Aug 08 06:09:05 PM PDT 24
Finished Aug 08 06:09:14 PM PDT 24
Peak memory 218200 kb
Host smart-82f6ae3a-2bc3-4ce3-9097-8fda27261e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365556415 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2365556415
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3367608512
Short name T378
Test name
Test status
Simulation time 406619436 ps
CPU time 10.05 seconds
Started Aug 08 06:09:04 PM PDT 24
Finished Aug 08 06:09:14 PM PDT 24
Peak memory 211644 kb
Host smart-4e75279c-d6d6-4559-af72-8e163e43e466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367608512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3367608512
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3198831627
Short name T330
Test name
Test status
Simulation time 177936585 ps
CPU time 8.06 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 211208 kb
Host smart-e6967b90-db0d-4b6d-98e4-0d14312f4dd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198831627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3198831627
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.330191828
Short name T331
Test name
Test status
Simulation time 915956828 ps
CPU time 10.11 seconds
Started Aug 08 06:09:05 PM PDT 24
Finished Aug 08 06:09:16 PM PDT 24
Peak memory 211248 kb
Host smart-48973eb8-12aa-408d-b1a7-2830620b6f73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330191828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
330191828
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2981948580
Short name T87
Test name
Test status
Simulation time 20502055786 ps
CPU time 56.32 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 216604 kb
Host smart-98f3e8c6-8022-4f4c-b50c-c083bb83a3bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981948580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2981948580
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2141622132
Short name T72
Test name
Test status
Simulation time 995684222 ps
CPU time 9.95 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:09:16 PM PDT 24
Peak memory 212148 kb
Host smart-fc4f4b0e-6cd5-40e2-a0eb-4873dcb86023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141622132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2141622132
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3721406075
Short name T394
Test name
Test status
Simulation time 249885696 ps
CPU time 12.93 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:09:03 PM PDT 24
Peak memory 218148 kb
Host smart-f99d1fd7-0f61-4360-8ad3-e28a2f523edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721406075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3721406075
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3658056950
Short name T115
Test name
Test status
Simulation time 1543312202 ps
CPU time 154.83 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:11:45 PM PDT 24
Peak memory 219516 kb
Host smart-aafdb47f-c1d8-45b3-859c-f5dbf6b9fc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658056950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3658056950
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3397703552
Short name T379
Test name
Test status
Simulation time 989343262 ps
CPU time 9.83 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:18 PM PDT 24
Peak memory 211240 kb
Host smart-49814894-96ea-412a-89a1-8580acc8219d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397703552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3397703552
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1787310515
Short name T349
Test name
Test status
Simulation time 987759378 ps
CPU time 10.47 seconds
Started Aug 08 06:09:01 PM PDT 24
Finished Aug 08 06:09:12 PM PDT 24
Peak memory 211316 kb
Host smart-3f1c24ef-83e2-4e47-989f-e1b3dba14466
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787310515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1787310515
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2199416177
Short name T372
Test name
Test status
Simulation time 1037444489 ps
CPU time 17.39 seconds
Started Aug 08 06:08:59 PM PDT 24
Finished Aug 08 06:09:16 PM PDT 24
Peak memory 212808 kb
Host smart-81529df5-e925-4b76-99ba-5a8df3deaf41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199416177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2199416177
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4216325733
Short name T343
Test name
Test status
Simulation time 359784483 ps
CPU time 9.61 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:09:16 PM PDT 24
Peak memory 218548 kb
Host smart-7e903594-bd22-41ec-bcf5-77e6d8ac3ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216325733 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4216325733
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.472703846
Short name T376
Test name
Test status
Simulation time 1128372554 ps
CPU time 9.93 seconds
Started Aug 08 06:09:03 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 211940 kb
Host smart-3bea51bf-cb16-44fb-8ce9-68cf71672cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472703846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.472703846
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4014822440
Short name T417
Test name
Test status
Simulation time 661412246 ps
CPU time 8.04 seconds
Started Aug 08 06:09:05 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 211200 kb
Host smart-502711a1-f676-4c8d-b9ea-4507b2bf1b30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014822440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4014822440
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1429301979
Short name T409
Test name
Test status
Simulation time 612349956 ps
CPU time 8.19 seconds
Started Aug 08 06:09:04 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 211104 kb
Host smart-019da21e-44b1-4164-b35b-7997de2c24a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429301979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1429301979
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.561948916
Short name T399
Test name
Test status
Simulation time 2059426235 ps
CPU time 55.57 seconds
Started Aug 08 06:09:01 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 215556 kb
Host smart-f0731a91-1884-4a1f-b763-b2b3fd186ace
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561948916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.561948916
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4167730684
Short name T97
Test name
Test status
Simulation time 3081213934 ps
CPU time 10.26 seconds
Started Aug 08 06:09:04 PM PDT 24
Finished Aug 08 06:09:14 PM PDT 24
Peak memory 212160 kb
Host smart-71ba449a-7479-4743-91fe-250247b536ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167730684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4167730684
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3129235317
Short name T392
Test name
Test status
Simulation time 347468668 ps
CPU time 11.73 seconds
Started Aug 08 06:08:59 PM PDT 24
Finished Aug 08 06:09:11 PM PDT 24
Peak memory 219620 kb
Host smart-fe47d7c2-6b98-4908-bec8-ca0e32103bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129235317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3129235317
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2565008389
Short name T371
Test name
Test status
Simulation time 1019651072 ps
CPU time 10.93 seconds
Started Aug 08 06:09:01 PM PDT 24
Finished Aug 08 06:09:12 PM PDT 24
Peak memory 218236 kb
Host smart-f2955ff1-ad3c-4e5a-8231-22a2bcf8b97b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565008389 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2565008389
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1243896674
Short name T364
Test name
Test status
Simulation time 169089416 ps
CPU time 8.25 seconds
Started Aug 08 06:09:05 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 211260 kb
Host smart-8a19e10b-283a-4ee0-820e-b48282f80953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243896674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1243896674
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1824672053
Short name T70
Test name
Test status
Simulation time 6916232817 ps
CPU time 65.91 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 216796 kb
Host smart-7fe5dbe5-ad4e-4a0f-8a87-73e9dec55aa6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824672053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1824672053
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.67798504
Short name T369
Test name
Test status
Simulation time 195058150 ps
CPU time 12 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 213228 kb
Host smart-7a67c49b-cd01-4c49-88db-636e939ffc01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67798504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctr
l_same_csr_outstanding.67798504
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.606336981
Short name T347
Test name
Test status
Simulation time 884713007 ps
CPU time 13.61 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 218052 kb
Host smart-a229f52f-05d6-4fb4-af26-dbafd96cd507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606336981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.606336981
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3218720603
Short name T112
Test name
Test status
Simulation time 786377322 ps
CPU time 154.9 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:11:41 PM PDT 24
Peak memory 214872 kb
Host smart-feecc269-5d54-4462-81a9-5135a4c2338e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218720603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3218720603
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.395177578
Short name T404
Test name
Test status
Simulation time 276315405 ps
CPU time 10.64 seconds
Started Aug 08 06:09:06 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 216888 kb
Host smart-a9fe27d0-50d2-48f7-baa7-3324eb5ef11a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395177578 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.395177578
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3872003539
Short name T356
Test name
Test status
Simulation time 172835880 ps
CPU time 7.97 seconds
Started Aug 08 06:09:05 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 211264 kb
Host smart-fb85e483-694d-4ffd-9382-63ce7a01a118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872003539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3872003539
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3667629384
Short name T92
Test name
Test status
Simulation time 3121006280 ps
CPU time 37.19 seconds
Started Aug 08 06:09:01 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 214960 kb
Host smart-bb0c8fdb-dc93-4d9f-8efe-640225a071c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667629384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3667629384
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3994610477
Short name T350
Test name
Test status
Simulation time 2018337556 ps
CPU time 18.5 seconds
Started Aug 08 06:09:00 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 213200 kb
Host smart-9c331f5a-41f5-40d5-9a69-e099bfe7a3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994610477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3994610477
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2611168258
Short name T395
Test name
Test status
Simulation time 175120900 ps
CPU time 11.46 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:09:20 PM PDT 24
Peak memory 218452 kb
Host smart-d863d72f-0f7b-4967-878e-ea12efebf6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611168258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2611168258
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1908930196
Short name T56
Test name
Test status
Simulation time 387241283 ps
CPU time 155.04 seconds
Started Aug 08 06:09:07 PM PDT 24
Finished Aug 08 06:11:43 PM PDT 24
Peak memory 214812 kb
Host smart-5eb51753-8555-49df-ae78-502b6f163258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908930196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1908930196
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2709450587
Short name T389
Test name
Test status
Simulation time 252962826 ps
CPU time 10.2 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 216884 kb
Host smart-2dd5c0d6-a8ab-48ee-a627-08d7a3823a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709450587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2709450587
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1660049215
Short name T370
Test name
Test status
Simulation time 689002811 ps
CPU time 8.12 seconds
Started Aug 08 06:09:01 PM PDT 24
Finished Aug 08 06:09:10 PM PDT 24
Peak memory 211480 kb
Host smart-b040c397-4838-492a-b25d-f233bab61438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660049215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1660049215
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.336451999
Short name T83
Test name
Test status
Simulation time 1532300081 ps
CPU time 65.63 seconds
Started Aug 08 06:09:07 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 215040 kb
Host smart-a1b15ec5-9220-4995-9360-8cb004bd4b8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336451999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.336451999
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3390992918
Short name T98
Test name
Test status
Simulation time 331897075 ps
CPU time 8.15 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 211928 kb
Host smart-54c94992-313f-40d4-8abb-eeb9eb556e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390992918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3390992918
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1755550417
Short name T387
Test name
Test status
Simulation time 317122523 ps
CPU time 13.58 seconds
Started Aug 08 06:09:00 PM PDT 24
Finished Aug 08 06:09:13 PM PDT 24
Peak memory 218156 kb
Host smart-100004b4-5c2d-43ae-814a-9d44cad2d3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755550417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1755550417
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2959857551
Short name T393
Test name
Test status
Simulation time 673149768 ps
CPU time 81.86 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 213436 kb
Host smart-5c235ca3-26cb-4b61-88d5-d152b503c827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959857551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2959857551
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.769126255
Short name T348
Test name
Test status
Simulation time 271307103 ps
CPU time 10.29 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:18 PM PDT 24
Peak memory 217064 kb
Host smart-4d0d97ba-d268-4dd7-afe6-54748197be12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769126255 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.769126255
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.856268128
Short name T68
Test name
Test status
Simulation time 789232887 ps
CPU time 8.04 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 211724 kb
Host smart-4293a8dd-171c-4e09-8185-b1fca31ec76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856268128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.856268128
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1628867540
Short name T86
Test name
Test status
Simulation time 2857686928 ps
CPU time 36.83 seconds
Started Aug 08 06:09:11 PM PDT 24
Finished Aug 08 06:09:48 PM PDT 24
Peak memory 215136 kb
Host smart-f83e8095-e078-4e89-becf-c689c43aa2b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628867540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1628867540
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1763337051
Short name T351
Test name
Test status
Simulation time 660222002 ps
CPU time 8.47 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 212280 kb
Host smart-650c261f-15f9-44d8-860e-03800240d38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763337051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1763337051
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2437373010
Short name T346
Test name
Test status
Simulation time 690978682 ps
CPU time 12.94 seconds
Started Aug 08 06:09:07 PM PDT 24
Finished Aug 08 06:09:20 PM PDT 24
Peak memory 218404 kb
Host smart-76512e98-73c0-44e9-8328-c709754e0ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437373010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2437373010
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.380017294
Short name T55
Test name
Test status
Simulation time 311705175 ps
CPU time 83.1 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 214404 kb
Host smart-4ac1fa8e-d6bc-455f-b455-9dc09ee4bf76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380017294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.380017294
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.185760468
Short name T388
Test name
Test status
Simulation time 499716176 ps
CPU time 10.43 seconds
Started Aug 08 06:09:12 PM PDT 24
Finished Aug 08 06:09:23 PM PDT 24
Peak memory 215580 kb
Host smart-62c07d5d-310f-4d5f-b05a-b6d295d2fb47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185760468 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.185760468
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4097453820
Short name T84
Test name
Test status
Simulation time 692477565 ps
CPU time 8.41 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 211592 kb
Host smart-1abb0ba2-0d56-49d9-a60d-ebb7fa04a94f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097453820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4097453820
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3245808495
Short name T360
Test name
Test status
Simulation time 1052811061 ps
CPU time 44.43 seconds
Started Aug 08 06:09:09 PM PDT 24
Finished Aug 08 06:09:54 PM PDT 24
Peak memory 214444 kb
Host smart-4dc3015d-00b4-4749-bf38-dbf9712a8ad6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245808495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3245808495
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4008894529
Short name T414
Test name
Test status
Simulation time 176545136 ps
CPU time 8.39 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:21 PM PDT 24
Peak memory 212200 kb
Host smart-58878bee-b6ea-4300-8457-355867e1c4c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008894529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4008894529
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3298854110
Short name T328
Test name
Test status
Simulation time 4082482547 ps
CPU time 19.09 seconds
Started Aug 08 06:09:08 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 218260 kb
Host smart-046d7da0-5d41-4305-989e-8e212613eb89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298854110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3298854110
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2227609208
Short name T109
Test name
Test status
Simulation time 321365757 ps
CPU time 154.41 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:11:51 PM PDT 24
Peak memory 219512 kb
Host smart-1ce1f1a0-858f-487d-a103-a1658a656f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227609208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2227609208
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2867883278
Short name T266
Test name
Test status
Simulation time 267898899 ps
CPU time 9.9 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 219104 kb
Host smart-f8d0722b-6176-4f42-9f32-c06040414a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867883278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2867883278
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1545614602
Short name T294
Test name
Test status
Simulation time 4793906000 ps
CPU time 280.92 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:13:59 PM PDT 24
Peak memory 247952 kb
Host smart-1a0212f9-68df-49bf-8fb6-b53e462c9d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545614602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1545614602
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.280429810
Short name T221
Test name
Test status
Simulation time 1903116172 ps
CPU time 22.64 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 220144 kb
Host smart-0337bb8d-4413-4baf-b47f-70222c0c363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280429810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.280429810
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3781664853
Short name T8
Test name
Test status
Simulation time 1583950824 ps
CPU time 10.54 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 220088 kb
Host smart-8a2cdef7-02d5-490b-8aa5-721dd45c06a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781664853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3781664853
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2221568695
Short name T229
Test name
Test status
Simulation time 178921930 ps
CPU time 10.48 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:28 PM PDT 24
Peak memory 220084 kb
Host smart-1c69b680-fd5e-4d17-85a7-0f97b1ae5269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221568695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2221568695
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2129658667
Short name T280
Test name
Test status
Simulation time 2142090438 ps
CPU time 27.84 seconds
Started Aug 08 06:09:14 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 219956 kb
Host smart-305cf3ce-d0f3-463a-9a94-c9b5ee6239ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129658667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2129658667
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2898912333
Short name T138
Test name
Test status
Simulation time 532056050 ps
CPU time 10.05 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 219000 kb
Host smart-477c4545-d3da-408d-b48f-30c621186dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898912333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2898912333
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.433400483
Short name T187
Test name
Test status
Simulation time 4548777358 ps
CPU time 245.42 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 240160 kb
Host smart-6a027eec-6273-4b89-81b3-14a5ab407f12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433400483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.433400483
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1715557773
Short name T301
Test name
Test status
Simulation time 691618547 ps
CPU time 19.58 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 220116 kb
Host smart-a9c19c34-210f-4858-bd03-7163f4a73df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715557773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1715557773
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.274691285
Short name T284
Test name
Test status
Simulation time 518712094 ps
CPU time 11.85 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:32 PM PDT 24
Peak memory 220096 kb
Host smart-ecbd95de-29e6-4724-afb8-50cdee72cee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274691285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.274691285
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1434882986
Short name T23
Test name
Test status
Simulation time 414372173 ps
CPU time 118.46 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 240036 kb
Host smart-781d58dd-2a56-4757-b6af-5c0251fc0e71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434882986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1434882986
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1050573330
Short name T277
Test name
Test status
Simulation time 1434995277 ps
CPU time 12.08 seconds
Started Aug 08 06:09:10 PM PDT 24
Finished Aug 08 06:09:22 PM PDT 24
Peak memory 220132 kb
Host smart-1ed918d6-9bb5-42e2-b8ef-eb343246b185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050573330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1050573330
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4280499710
Short name T298
Test name
Test status
Simulation time 551004105 ps
CPU time 28.34 seconds
Started Aug 08 06:09:13 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 220096 kb
Host smart-39123b8f-ae6e-4006-acf9-29cdbe48b992
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280499710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4280499710
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1667880008
Short name T271
Test name
Test status
Simulation time 987826315 ps
CPU time 9.93 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 219888 kb
Host smart-fbaf439a-51e9-432d-8804-47a844b16d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667880008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1667880008
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.569553498
Short name T46
Test name
Test status
Simulation time 6530359647 ps
CPU time 151.68 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 237368 kb
Host smart-d1cbcbd8-cc4f-4bdb-ba62-8236bfc6642a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569553498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.569553498
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3461037666
Short name T295
Test name
Test status
Simulation time 1010492256 ps
CPU time 22.61 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 220008 kb
Host smart-2d1b7b27-0456-4619-aff4-267ab0331aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461037666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3461037666
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1418064772
Short name T204
Test name
Test status
Simulation time 3466732421 ps
CPU time 10.35 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:09:33 PM PDT 24
Peak memory 220224 kb
Host smart-4365060f-978f-49b2-8022-36e673c1aa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418064772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1418064772
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3129094623
Short name T307
Test name
Test status
Simulation time 761020662 ps
CPU time 20.49 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:54 PM PDT 24
Peak memory 220032 kb
Host smart-6f3946f8-7671-4ff4-a670-f556cee0e9e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129094623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3129094623
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3447307467
Short name T105
Test name
Test status
Simulation time 288327093777 ps
CPU time 1904.23 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:41:17 PM PDT 24
Peak memory 244896 kb
Host smart-5c02a07a-04f9-4251-a409-e02340e1f640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447307467 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3447307467
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.584695100
Short name T144
Test name
Test status
Simulation time 167970561 ps
CPU time 8.34 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:35 PM PDT 24
Peak memory 219064 kb
Host smart-55931081-fd08-436e-9d2d-19bd3886545f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584695100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.584695100
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1763378502
Short name T183
Test name
Test status
Simulation time 19743703828 ps
CPU time 401.88 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:16:13 PM PDT 24
Peak memory 226692 kb
Host smart-beb1578f-ddf4-494e-8f98-8f744459925c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763378502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1763378502
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2521029569
Short name T241
Test name
Test status
Simulation time 1097085752 ps
CPU time 22.43 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 220056 kb
Host smart-d255aab2-557d-4323-a753-aeed406df237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521029569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2521029569
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1341038400
Short name T231
Test name
Test status
Simulation time 1068544076 ps
CPU time 12.1 seconds
Started Aug 08 06:09:24 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 220032 kb
Host smart-01f87785-69ba-475f-b2aa-16b6a0d98c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341038400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1341038400
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1830001878
Short name T17
Test name
Test status
Simulation time 574859701 ps
CPU time 16.4 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 220012 kb
Host smart-e3c7ed1b-3992-4947-9e37-de627f9fdddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830001878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1830001878
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3306414419
Short name T285
Test name
Test status
Simulation time 15336687627 ps
CPU time 559.86 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:18:52 PM PDT 24
Peak memory 236532 kb
Host smart-b740a570-4438-42aa-9d08-1549bafe3f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306414419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3306414419
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3858345641
Short name T220
Test name
Test status
Simulation time 3931348896 ps
CPU time 15.22 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:48 PM PDT 24
Peak memory 219336 kb
Host smart-d3df9eff-64c8-4a9a-9651-97b6ddba95b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858345641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3858345641
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1520541180
Short name T125
Test name
Test status
Simulation time 1374387811 ps
CPU time 19.41 seconds
Started Aug 08 06:09:27 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 220012 kb
Host smart-f4ffc992-4f0f-4495-a033-575cc5b15395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520541180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1520541180
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2968295680
Short name T327
Test name
Test status
Simulation time 186827645 ps
CPU time 10.48 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 220008 kb
Host smart-e39a7ad8-a3bf-44e9-8e3f-4f2a74b9320d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968295680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2968295680
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3719708687
Short name T57
Test name
Test status
Simulation time 4575650214 ps
CPU time 16.24 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 220112 kb
Host smart-8fe78257-7fd3-4272-ae84-c3a8b06d4edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719708687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3719708687
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1166716359
Short name T36
Test name
Test status
Simulation time 204020255 ps
CPU time 8.33 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 219116 kb
Host smart-f2f6319d-e599-40dc-a8ff-91394f5e7a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166716359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1166716359
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.12544860
Short name T259
Test name
Test status
Simulation time 5953538859 ps
CPU time 196.33 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:12:41 PM PDT 24
Peak memory 240364 kb
Host smart-47afc659-347e-4efb-a0ff-fa6521b681fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.12544860
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1657079324
Short name T26
Test name
Test status
Simulation time 1743409682 ps
CPU time 19.4 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:45 PM PDT 24
Peak memory 220076 kb
Host smart-eb543e08-6523-45c1-99d3-6d920944e292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657079324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1657079324
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3613642868
Short name T133
Test name
Test status
Simulation time 261605586 ps
CPU time 12.28 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 220100 kb
Host smart-271d35a2-c39b-4236-963a-e05b7c5183ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613642868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3613642868
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3754683830
Short name T80
Test name
Test status
Simulation time 1440747249 ps
CPU time 20.88 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:52 PM PDT 24
Peak memory 220076 kb
Host smart-c0373e6b-cec0-4ef5-93c7-97eb9ab5ab91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754683830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3754683830
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1185984867
Short name T13
Test name
Test status
Simulation time 21920574305 ps
CPU time 874.89 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:24:04 PM PDT 24
Peak memory 236668 kb
Host smart-a73291b0-fbdf-4ff2-b412-be68912058a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185984867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1185984867
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1861373374
Short name T32
Test name
Test status
Simulation time 169738248 ps
CPU time 8.14 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:34 PM PDT 24
Peak memory 219200 kb
Host smart-e96c8729-2a25-4ee8-bd48-946332e8239d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861373374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1861373374
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.185302242
Short name T190
Test name
Test status
Simulation time 12964192628 ps
CPU time 335.87 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 241496 kb
Host smart-05673642-f8b7-4dac-b30e-551553566f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185302242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.185302242
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3174266605
Short name T269
Test name
Test status
Simulation time 497129198 ps
CPU time 22.76 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:53 PM PDT 24
Peak memory 220076 kb
Host smart-c56a80e4-dcf2-479b-8034-718a3ca001da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174266605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3174266605
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2663248327
Short name T297
Test name
Test status
Simulation time 183950938 ps
CPU time 10.08 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 220120 kb
Host smart-28ca3aa3-0668-41c8-8dd7-674a2776d837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663248327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2663248327
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3088617450
Short name T154
Test name
Test status
Simulation time 2119102222 ps
CPU time 27.12 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:52 PM PDT 24
Peak memory 220048 kb
Host smart-28d783b8-c825-483a-bf94-69521f94478d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088617450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3088617450
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.420407646
Short name T48
Test name
Test status
Simulation time 29518579154 ps
CPU time 782.08 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 236540 kb
Host smart-0ea66c60-fd32-4f84-8476-4fe17304b98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420407646 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.420407646
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3526784913
Short name T44
Test name
Test status
Simulation time 174594127 ps
CPU time 8.45 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:35 PM PDT 24
Peak memory 219132 kb
Host smart-33503d0a-2f70-4aad-aadf-a23207376d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526784913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3526784913
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1755312305
Short name T291
Test name
Test status
Simulation time 2002413822 ps
CPU time 117.8 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 243956 kb
Host smart-477d64e4-b025-433c-894c-7ecd156ea96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755312305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1755312305
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2352870809
Short name T148
Test name
Test status
Simulation time 1976749756 ps
CPU time 22.49 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:51 PM PDT 24
Peak memory 220100 kb
Host smart-22bc1efe-0593-49bd-a0d8-9b8c8a858092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352870809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2352870809
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2890594689
Short name T14
Test name
Test status
Simulation time 350440660 ps
CPU time 10.69 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 220092 kb
Host smart-b793245a-394d-4a57-b1ba-427b192a4b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890594689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2890594689
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3543080186
Short name T226
Test name
Test status
Simulation time 394110233 ps
CPU time 24.61 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 220024 kb
Host smart-9b18c013-a293-4cce-8bd1-42ea5d1995cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543080186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3543080186
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1987538068
Short name T324
Test name
Test status
Simulation time 1078027067 ps
CPU time 10.13 seconds
Started Aug 08 06:09:24 PM PDT 24
Finished Aug 08 06:09:34 PM PDT 24
Peak memory 219084 kb
Host smart-68ae7563-eb78-4b32-9c99-5933ea2c6a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987538068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1987538068
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4083964566
Short name T188
Test name
Test status
Simulation time 515965605 ps
CPU time 12.08 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 220064 kb
Host smart-af51442a-6557-4d1c-a61b-f20a1726eac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083964566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4083964566
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3089317657
Short name T217
Test name
Test status
Simulation time 1528967900 ps
CPU time 24.01 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 219944 kb
Host smart-87cd19f4-396d-4549-8313-8e6cde271797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089317657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3089317657
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3768387756
Short name T312
Test name
Test status
Simulation time 691228814 ps
CPU time 8.19 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 219176 kb
Host smart-60203330-467b-4434-ae75-b96099de9c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768387756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3768387756
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3096024729
Short name T29
Test name
Test status
Simulation time 3695223242 ps
CPU time 225.52 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:13:18 PM PDT 24
Peak memory 238592 kb
Host smart-11526f0f-08a6-4b2e-bca7-a103c4ed0114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096024729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3096024729
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.907731646
Short name T216
Test name
Test status
Simulation time 1379658783 ps
CPU time 18.81 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 220076 kb
Host smart-4669776f-5874-424a-8f57-9ba90044b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907731646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.907731646
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3927235744
Short name T119
Test name
Test status
Simulation time 262102105 ps
CPU time 12.55 seconds
Started Aug 08 06:09:27 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 220032 kb
Host smart-aa67df21-403d-460c-93b5-76c66275d92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927235744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3927235744
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2165053783
Short name T35
Test name
Test status
Simulation time 379103927 ps
CPU time 23.58 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 220056 kb
Host smart-6327ba0d-4d6f-4067-8ae0-e79b87abae3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165053783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2165053783
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3870310364
Short name T245
Test name
Test status
Simulation time 45568968917 ps
CPU time 1021.13 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:26:29 PM PDT 24
Peak memory 235204 kb
Host smart-bae137d1-07b1-4e04-b962-0c209388ba51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870310364 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3870310364
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1730468343
Short name T145
Test name
Test status
Simulation time 1039262128 ps
CPU time 15.66 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 219200 kb
Host smart-5b3cf6ee-2bea-47fb-94f5-9a5989f6db87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730468343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1730468343
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3171147991
Short name T268
Test name
Test status
Simulation time 4813361671 ps
CPU time 308.1 seconds
Started Aug 08 06:09:27 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 220380 kb
Host smart-caa3d3e0-2776-4716-8afa-04460594335d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171147991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3171147991
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.156061076
Short name T270
Test name
Test status
Simulation time 7076667553 ps
CPU time 22.57 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:51 PM PDT 24
Peak memory 220248 kb
Host smart-d512820e-9d78-441f-a58c-7391ee4c9186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156061076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.156061076
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1540071499
Short name T308
Test name
Test status
Simulation time 1023708664 ps
CPU time 12.47 seconds
Started Aug 08 06:09:27 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 220120 kb
Host smart-ad3826bc-8a42-45e5-a5e8-1da92220ec52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540071499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1540071499
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1316031561
Short name T162
Test name
Test status
Simulation time 816800069 ps
CPU time 36.65 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 219948 kb
Host smart-afe51deb-d824-427b-a909-891b9e346a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316031561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1316031561
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3209525346
Short name T192
Test name
Test status
Simulation time 436983748 ps
CPU time 10.16 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 219216 kb
Host smart-18c548e1-d0a2-4a02-9153-6902bc7988f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209525346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3209525346
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.50529022
Short name T126
Test name
Test status
Simulation time 4685588605 ps
CPU time 168 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:12:16 PM PDT 24
Peak memory 240824 kb
Host smart-6d17acd1-6397-425d-8d43-792e760eb26f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50529022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co
rrupt_sig_fatal_chk.50529022
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2827442097
Short name T161
Test name
Test status
Simulation time 2365222628 ps
CPU time 19.6 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 220196 kb
Host smart-e4dc9e3b-4fec-4d89-88e3-0605a6c09766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827442097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2827442097
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4206459622
Short name T228
Test name
Test status
Simulation time 1018639082 ps
CPU time 12.24 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 220136 kb
Host smart-7df0f5a4-4c9d-4c05-b816-c1a345ccf0e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206459622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4206459622
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3189083933
Short name T253
Test name
Test status
Simulation time 261384470 ps
CPU time 18.73 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:09:51 PM PDT 24
Peak memory 220040 kb
Host smart-568086d4-a531-4cd0-aa50-b712c4896b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189083933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3189083933
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.271834517
Short name T247
Test name
Test status
Simulation time 2752716091 ps
CPU time 9.83 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:09:42 PM PDT 24
Peak memory 219272 kb
Host smart-108158d2-25bc-414c-a4d5-3785245638f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271834517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.271834517
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4292076533
Short name T313
Test name
Test status
Simulation time 3742385027 ps
CPU time 231.16 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 238152 kb
Host smart-dcf07a73-0e83-4205-8eaf-87c56fd7a9f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292076533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4292076533
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.987677078
Short name T261
Test name
Test status
Simulation time 1272414634 ps
CPU time 19.04 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 220108 kb
Host smart-ecdb41c6-2240-4715-a867-7eb393b77bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987677078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.987677078
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3026763671
Short name T141
Test name
Test status
Simulation time 524455406 ps
CPU time 12.29 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 220128 kb
Host smart-89670153-2aac-4906-bde9-649bc3420019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026763671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3026763671
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3572289449
Short name T22
Test name
Test status
Simulation time 2372450244 ps
CPU time 229.36 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 239560 kb
Host smart-0e637dfe-bd4d-4c37-b210-c54982b28154
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572289449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3572289449
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1617884342
Short name T197
Test name
Test status
Simulation time 190773843 ps
CPU time 10.76 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 220068 kb
Host smart-4e18c142-ea32-4941-b98b-66329df4703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617884342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1617884342
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3317104636
Short name T143
Test name
Test status
Simulation time 551081192 ps
CPU time 29.52 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 219956 kb
Host smart-f423f42a-7c63-482c-9696-8102b8f55ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317104636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3317104636
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.123733421
Short name T51
Test name
Test status
Simulation time 108413712462 ps
CPU time 4508.95 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 07:24:28 PM PDT 24
Peak memory 261232 kb
Host smart-e7f3a3b1-2760-4e90-95ca-a3c47f00f498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123733421 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.123733421
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.488133999
Short name T218
Test name
Test status
Simulation time 395143585 ps
CPU time 8.3 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 219116 kb
Host smart-4889383c-681f-4dbc-8617-6739fdd9862a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488133999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.488133999
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2263799996
Short name T263
Test name
Test status
Simulation time 7267605358 ps
CPU time 372.08 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 239448 kb
Host smart-7cfcb556-e3f9-428b-92ab-df296bc0a9d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263799996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2263799996
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3320422898
Short name T159
Test name
Test status
Simulation time 512664890 ps
CPU time 22.74 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:56 PM PDT 24
Peak memory 220044 kb
Host smart-baf03fe6-fa38-45b8-84b9-16344efbd6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320422898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3320422898
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3055176632
Short name T189
Test name
Test status
Simulation time 723199656 ps
CPU time 10.26 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 220144 kb
Host smart-9a004c10-fcbc-47b6-9e5a-1cd922fb9c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055176632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3055176632
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3858023556
Short name T305
Test name
Test status
Simulation time 292991535 ps
CPU time 17.17 seconds
Started Aug 08 06:09:37 PM PDT 24
Finished Aug 08 06:09:54 PM PDT 24
Peak memory 219988 kb
Host smart-f9bc7194-f859-414d-9fef-ab5297161f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858023556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3858023556
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2638149010
Short name T166
Test name
Test status
Simulation time 167472852 ps
CPU time 8.63 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 219140 kb
Host smart-c7b5d661-9bed-4858-a22f-775450e2ac75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638149010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2638149010
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4113363622
Short name T199
Test name
Test status
Simulation time 11435891941 ps
CPU time 201.95 seconds
Started Aug 08 06:09:27 PM PDT 24
Finished Aug 08 06:12:49 PM PDT 24
Peak memory 220320 kb
Host smart-6fe87761-d2ae-49fa-b69e-09bf3f911bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113363622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4113363622
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1153401242
Short name T273
Test name
Test status
Simulation time 346096971 ps
CPU time 19.65 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:53 PM PDT 24
Peak memory 220040 kb
Host smart-5dc1a3b0-e24a-4105-8ff5-5c0895362818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153401242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1153401242
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1331280513
Short name T153
Test name
Test status
Simulation time 698227763 ps
CPU time 10.52 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 220084 kb
Host smart-be3eb7ce-a95b-4b77-82fc-f4da44fb9d1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331280513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1331280513
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1640618485
Short name T74
Test name
Test status
Simulation time 3750179752 ps
CPU time 28.2 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 220128 kb
Host smart-5f127d5a-a136-4b72-b640-687530984ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640618485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1640618485
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1740730291
Short name T292
Test name
Test status
Simulation time 1830951713 ps
CPU time 8.23 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 219140 kb
Host smart-80c1332b-c37d-408f-a017-89bd63280675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740730291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1740730291
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1468845513
Short name T299
Test name
Test status
Simulation time 63307834038 ps
CPU time 154.52 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 220440 kb
Host smart-675897ff-1c79-4153-b01a-768249a77745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468845513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1468845513
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3860003026
Short name T237
Test name
Test status
Simulation time 346107883 ps
CPU time 19.33 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 220080 kb
Host smart-b560c944-d8fa-48a4-952f-560abb4b7f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860003026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3860003026
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2171513833
Short name T181
Test name
Test status
Simulation time 180263021 ps
CPU time 10.33 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 220092 kb
Host smart-e14835bd-c7a8-4ff9-9de2-9307710b41cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171513833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2171513833
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.82909027
Short name T227
Test name
Test status
Simulation time 1535585754 ps
CPU time 38.41 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 220092 kb
Host smart-e4092c91-b210-473a-9221-81d2f498455b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82909027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.rom_ctrl_stress_all.82909027
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3636574154
Short name T238
Test name
Test status
Simulation time 76432536626 ps
CPU time 708.77 seconds
Started Aug 08 06:09:32 PM PDT 24
Finished Aug 08 06:21:21 PM PDT 24
Peak memory 233968 kb
Host smart-a5bfcb95-e3db-42e8-91c2-62f9611037c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636574154 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3636574154
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.489862487
Short name T30
Test name
Test status
Simulation time 686844847 ps
CPU time 9.93 seconds
Started Aug 08 06:09:38 PM PDT 24
Finished Aug 08 06:09:48 PM PDT 24
Peak memory 219040 kb
Host smart-da908a98-efb4-4be3-9d45-4da7e4eb7ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489862487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.489862487
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1193484516
Short name T198
Test name
Test status
Simulation time 82907420560 ps
CPU time 364.81 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 238524 kb
Host smart-8b4699d8-9937-4b8a-83b5-81b04b7d755a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193484516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1193484516
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2695827151
Short name T224
Test name
Test status
Simulation time 1056911134 ps
CPU time 22.34 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:09:58 PM PDT 24
Peak memory 220084 kb
Host smart-698240b8-250b-4e78-9982-4150d4f8bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695827151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2695827151
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1534024377
Short name T177
Test name
Test status
Simulation time 461153927 ps
CPU time 12.23 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 220016 kb
Host smart-b1d6a5ba-6a86-4231-a819-cddf20484da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534024377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1534024377
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3366013383
Short name T146
Test name
Test status
Simulation time 576627783 ps
CPU time 36.52 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 220036 kb
Host smart-97e6858a-486f-49ae-9327-5c659ff90f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366013383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3366013383
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1991379737
Short name T168
Test name
Test status
Simulation time 420236182 ps
CPU time 10.07 seconds
Started Aug 08 06:09:45 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 219140 kb
Host smart-7f20559b-fccc-4b32-9f1d-39c71800fe22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991379737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1991379737
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2287409285
Short name T117
Test name
Test status
Simulation time 19450619203 ps
CPU time 282.33 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 239740 kb
Host smart-6089dc79-2f44-49b5-bab6-e4b4a6226238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287409285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2287409285
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2855981071
Short name T232
Test name
Test status
Simulation time 1982381786 ps
CPU time 23.26 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:09:59 PM PDT 24
Peak memory 220100 kb
Host smart-cb2f890d-54aa-46b6-bb89-56d2252ee06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855981071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2855981071
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1288853071
Short name T296
Test name
Test status
Simulation time 282640131 ps
CPU time 12.4 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:09:48 PM PDT 24
Peak memory 220128 kb
Host smart-f2bfc66b-78ef-40f8-ad91-f8f4de503049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288853071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1288853071
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.490603186
Short name T121
Test name
Test status
Simulation time 808830267 ps
CPU time 35.02 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:10:11 PM PDT 24
Peak memory 220012 kb
Host smart-cc93c06f-5638-46fc-9833-2aa34f585b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490603186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.490603186
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2636443177
Short name T134
Test name
Test status
Simulation time 660521634 ps
CPU time 8.4 seconds
Started Aug 08 06:09:39 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 219608 kb
Host smart-435aaf64-5028-415e-80ff-3d659a2bfb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636443177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2636443177
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.789437709
Short name T116
Test name
Test status
Simulation time 79858936548 ps
CPU time 499.9 seconds
Started Aug 08 06:09:38 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 234676 kb
Host smart-9745e3e1-a693-41f0-9f3b-d3cfea8fb9b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789437709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.789437709
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2356357062
Short name T249
Test name
Test status
Simulation time 1594927464 ps
CPU time 22.45 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:09:58 PM PDT 24
Peak memory 220076 kb
Host smart-03e764ed-bffe-4af0-97be-cd4faea17f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356357062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2356357062
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1004416364
Short name T317
Test name
Test status
Simulation time 882707330 ps
CPU time 11.94 seconds
Started Aug 08 06:09:40 PM PDT 24
Finished Aug 08 06:09:52 PM PDT 24
Peak memory 220068 kb
Host smart-21b22843-9373-484e-a25a-abee08e4675d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004416364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1004416364
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.461589539
Short name T195
Test name
Test status
Simulation time 1102180937 ps
CPU time 15.7 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220008 kb
Host smart-8b27795e-0f22-48c4-a7e1-3c30972a8de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461589539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.461589539
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2344442372
Short name T174
Test name
Test status
Simulation time 688579882 ps
CPU time 8.45 seconds
Started Aug 08 06:09:37 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 219060 kb
Host smart-db620fc0-136e-47a8-b1fb-db7a16a15fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344442372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2344442372
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3085333907
Short name T256
Test name
Test status
Simulation time 4519546737 ps
CPU time 243.39 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:13:50 PM PDT 24
Peak memory 238476 kb
Host smart-93ec4364-e18c-47f7-9017-9ce55d10e7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085333907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3085333907
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1620542873
Short name T150
Test name
Test status
Simulation time 342851430 ps
CPU time 19.19 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 220108 kb
Host smart-05819c83-2f4f-435d-b248-dc072e13ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620542873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1620542873
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1354680725
Short name T167
Test name
Test status
Simulation time 184873533 ps
CPU time 10.46 seconds
Started Aug 08 06:09:44 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 220080 kb
Host smart-358c24f2-d91b-47ad-a4cc-14b4274dbafb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354680725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1354680725
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3950668259
Short name T276
Test name
Test status
Simulation time 574089675 ps
CPU time 25.13 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 220072 kb
Host smart-ad59e8e5-0024-4ad4-a185-2df766f6eb96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950668259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3950668259
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2865735186
Short name T24
Test name
Test status
Simulation time 1076485661 ps
CPU time 10.02 seconds
Started Aug 08 06:09:40 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 219844 kb
Host smart-609ab9b7-4629-4b2f-82c0-0109d22e081d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865735186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2865735186
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2188891939
Short name T323
Test name
Test status
Simulation time 13502172892 ps
CPU time 278.63 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:14:13 PM PDT 24
Peak memory 241180 kb
Host smart-578c8b6d-4d79-4c16-9044-00cf91690502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188891939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2188891939
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.664549530
Short name T288
Test name
Test status
Simulation time 332507975 ps
CPU time 19.11 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:10:05 PM PDT 24
Peak memory 220060 kb
Host smart-2bc70acf-071f-4d5e-b31b-84a20f136057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664549530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.664549530
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1172191556
Short name T136
Test name
Test status
Simulation time 1036550541 ps
CPU time 12.36 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 218976 kb
Host smart-91155b52-365d-4d28-8916-828cac1219f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172191556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1172191556
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1703857560
Short name T254
Test name
Test status
Simulation time 1402838921 ps
CPU time 13.1 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:10:00 PM PDT 24
Peak memory 220028 kb
Host smart-d7e6e8eb-b011-4396-9ff3-a8d9acfd0fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703857560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1703857560
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3488514856
Short name T52
Test name
Test status
Simulation time 518484411985 ps
CPU time 1384.75 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:32:41 PM PDT 24
Peak memory 240664 kb
Host smart-887b7a22-c47f-4696-a1b6-4b7c09a03163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488514856 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3488514856
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.113218337
Short name T165
Test name
Test status
Simulation time 989535424 ps
CPU time 10.22 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:45 PM PDT 24
Peak memory 218044 kb
Host smart-99a0b8c7-b10e-421e-8646-d1cef5d58ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113218337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.113218337
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1035263060
Short name T210
Test name
Test status
Simulation time 2186501659 ps
CPU time 128.18 seconds
Started Aug 08 06:09:39 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 236120 kb
Host smart-e7827ce9-2ef6-4e1c-9ddf-0284b96a3df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035263060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1035263060
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2067829982
Short name T128
Test name
Test status
Simulation time 1455174038 ps
CPU time 22.24 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 220060 kb
Host smart-32dd4c29-23d3-42a2-821b-d6600cd1331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067829982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2067829982
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.634142350
Short name T164
Test name
Test status
Simulation time 1072572178 ps
CPU time 12.52 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:09:59 PM PDT 24
Peak memory 220112 kb
Host smart-46eb7122-e21d-485c-8721-6b68562b20dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634142350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.634142350
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2836888483
Short name T193
Test name
Test status
Simulation time 5974907994 ps
CPU time 37.65 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 220196 kb
Host smart-d748964a-1861-4d4c-999e-7296dd1d21a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836888483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2836888483
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2596081933
Short name T47
Test name
Test status
Simulation time 161909233491 ps
CPU time 3475.14 seconds
Started Aug 08 06:09:43 PM PDT 24
Finished Aug 08 07:07:39 PM PDT 24
Peak memory 254328 kb
Host smart-44005d6d-171b-4615-bf5b-cd77a64ec9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596081933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2596081933
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1994739451
Short name T186
Test name
Test status
Simulation time 338884177 ps
CPU time 8.4 seconds
Started Aug 08 06:09:38 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 219116 kb
Host smart-aadc1105-233d-4552-8a09-22a8bec92fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994739451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1994739451
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1528283569
Short name T151
Test name
Test status
Simulation time 19838392139 ps
CPU time 299.08 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 239788 kb
Host smart-a1f56362-2a6b-4743-a004-5aa25f97a533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528283569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1528283569
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.612844994
Short name T207
Test name
Test status
Simulation time 1379308604 ps
CPU time 19.43 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:12 PM PDT 24
Peak memory 220128 kb
Host smart-89ef2ea2-e47b-41a3-a571-da383bd11c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612844994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.612844994
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4267545735
Short name T102
Test name
Test status
Simulation time 266798819 ps
CPU time 12.01 seconds
Started Aug 08 06:09:38 PM PDT 24
Finished Aug 08 06:09:51 PM PDT 24
Peak memory 220008 kb
Host smart-6fe6ec61-523c-49db-9f4b-ecc8302273d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267545735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4267545735
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1874098638
Short name T191
Test name
Test status
Simulation time 400985308 ps
CPU time 27.65 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 220104 kb
Host smart-19d2cfc9-6106-4daa-b100-5fc72b6d07f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874098638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1874098638
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1841229341
Short name T234
Test name
Test status
Simulation time 1032791114 ps
CPU time 10.12 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 219220 kb
Host smart-0e58f0f8-23fc-4da5-82b6-cd5cbcdacb9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841229341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1841229341
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2864383253
Short name T123
Test name
Test status
Simulation time 14819532857 ps
CPU time 195.39 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 239584 kb
Host smart-78611c08-6cd2-4e2b-91a3-6cc6d3ed95ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864383253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2864383253
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2373878334
Short name T42
Test name
Test status
Simulation time 346237878 ps
CPU time 18.79 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 220136 kb
Host smart-075b2932-493a-4c72-81df-7b04e601b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373878334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2373878334
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4023906801
Short name T293
Test name
Test status
Simulation time 690744430 ps
CPU time 10.33 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:31 PM PDT 24
Peak memory 220084 kb
Host smart-f401daf9-631b-4dcc-850f-0930d09f03e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023906801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4023906801
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.113862366
Short name T28
Test name
Test status
Simulation time 546939654 ps
CPU time 228.23 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:13:11 PM PDT 24
Peak memory 239896 kb
Host smart-df0795bf-d711-41f6-8015-8c32e6788b8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113862366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.113862366
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3632496980
Short name T1
Test name
Test status
Simulation time 1046880625 ps
CPU time 16.87 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:47 PM PDT 24
Peak memory 220108 kb
Host smart-c3f9f498-00b5-466b-ba0a-88ee71af7ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632496980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3632496980
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4194280055
Short name T233
Test name
Test status
Simulation time 830393516 ps
CPU time 22.14 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 219944 kb
Host smart-396923be-464d-4a33-820d-a0a765d526e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194280055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4194280055
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1167353543
Short name T64
Test name
Test status
Simulation time 2055558555 ps
CPU time 10.42 seconds
Started Aug 08 06:10:02 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 219164 kb
Host smart-0788f8cd-75c5-4b20-8f59-4b2a352bced5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167353543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1167353543
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1492906388
Short name T242
Test name
Test status
Simulation time 21157463745 ps
CPU time 268.21 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:14:24 PM PDT 24
Peak memory 225304 kb
Host smart-e154e819-29b7-4f8b-a81f-15feeb6aaa97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492906388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1492906388
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4043838330
Short name T131
Test name
Test status
Simulation time 511557276 ps
CPU time 22.68 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:09:58 PM PDT 24
Peak memory 220112 kb
Host smart-9f10a1ef-fd62-4d12-bbee-dca648c76ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043838330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4043838330
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.143174263
Short name T236
Test name
Test status
Simulation time 1013505009 ps
CPU time 10.41 seconds
Started Aug 08 06:09:35 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 220100 kb
Host smart-833bd5e4-16ce-4ba8-9e19-47f4e8529d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143174263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.143174263
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1675194916
Short name T222
Test name
Test status
Simulation time 2069532845 ps
CPU time 26.71 seconds
Started Aug 08 06:09:36 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220072 kb
Host smart-2298b372-1786-41a3-a8b3-4b100dbb73e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675194916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1675194916
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4223267358
Short name T156
Test name
Test status
Simulation time 1031613245 ps
CPU time 9.83 seconds
Started Aug 08 06:09:48 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 219200 kb
Host smart-03a320cd-a3bf-48ed-b932-09020ca78ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223267358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4223267358
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4131351920
Short name T11
Test name
Test status
Simulation time 4531013243 ps
CPU time 318.91 seconds
Started Aug 08 06:09:49 PM PDT 24
Finished Aug 08 06:15:09 PM PDT 24
Peak memory 243152 kb
Host smart-27df9479-9a34-44f5-ad03-3452307b771c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131351920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4131351920
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4042677635
Short name T257
Test name
Test status
Simulation time 3946507764 ps
CPU time 32.53 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 220192 kb
Host smart-df74309e-25e0-421e-8bef-928cc7c613ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042677635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4042677635
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1710361373
Short name T310
Test name
Test status
Simulation time 2146867462 ps
CPU time 12.4 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:09:59 PM PDT 24
Peak memory 220100 kb
Host smart-5caad69a-9e50-412f-a031-42e0b8e22993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710361373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1710361373
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1506316618
Short name T18
Test name
Test status
Simulation time 369904385 ps
CPU time 24.15 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 220020 kb
Host smart-126d950d-88eb-47e7-9016-05741b4ac33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506316618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1506316618
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2035192775
Short name T315
Test name
Test status
Simulation time 262705492 ps
CPU time 9.96 seconds
Started Aug 08 06:09:44 PM PDT 24
Finished Aug 08 06:09:54 PM PDT 24
Peak memory 219128 kb
Host smart-40a494f8-74b5-43de-b670-f3bb0f7e6542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035192775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2035192775
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1942989421
Short name T255
Test name
Test status
Simulation time 4122792620 ps
CPU time 220 seconds
Started Aug 08 06:09:49 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 239948 kb
Host smart-a0b82d91-f22d-42a8-a4cc-5753ab5e7a85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942989421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1942989421
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2034229111
Short name T41
Test name
Test status
Simulation time 1320148427 ps
CPU time 19 seconds
Started Aug 08 06:09:50 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 220132 kb
Host smart-bfd5b2ee-0187-405b-94e7-39aa70d683f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034229111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2034229111
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2609193179
Short name T225
Test name
Test status
Simulation time 1346013293 ps
CPU time 10.77 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220140 kb
Host smart-0e7e7760-ec2d-479c-bdef-998843bc9b80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609193179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2609193179
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2039313510
Short name T251
Test name
Test status
Simulation time 572685678 ps
CPU time 19.91 seconds
Started Aug 08 06:09:51 PM PDT 24
Finished Aug 08 06:10:11 PM PDT 24
Peak memory 220024 kb
Host smart-90207d1a-6e2a-4e5d-a169-fdd494bb2b63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039313510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2039313510
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.920999854
Short name T173
Test name
Test status
Simulation time 971514613 ps
CPU time 8.67 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:00 PM PDT 24
Peak memory 219096 kb
Host smart-98591c26-fd0e-43f3-982b-ab7d9a5ecc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920999854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.920999854
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3003233673
Short name T129
Test name
Test status
Simulation time 5337416845 ps
CPU time 272.7 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:14:26 PM PDT 24
Peak memory 234580 kb
Host smart-fae27697-c9e0-4ee2-b64f-1ce0c56df370
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003233673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3003233673
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3228837891
Short name T135
Test name
Test status
Simulation time 2609073073 ps
CPU time 22.86 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 220220 kb
Host smart-a848f00d-c880-4d96-a164-f29300070101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228837891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3228837891
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1970032858
Short name T34
Test name
Test status
Simulation time 352112627 ps
CPU time 10.34 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 220116 kb
Host smart-f8d48241-36c9-4210-a024-6335aecb77cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970032858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1970032858
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4087031958
Short name T15
Test name
Test status
Simulation time 59105164031 ps
CPU time 2251.16 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:47:19 PM PDT 24
Peak memory 244900 kb
Host smart-b1d343fd-6732-4bfa-b33d-a14be0de2495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087031958 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4087031958
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1604482981
Short name T175
Test name
Test status
Simulation time 1173880932 ps
CPU time 9.99 seconds
Started Aug 08 06:09:55 PM PDT 24
Finished Aug 08 06:10:05 PM PDT 24
Peak memory 219148 kb
Host smart-678f9ebe-b2b4-41ca-b959-623ed0236c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604482981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1604482981
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.421776757
Short name T248
Test name
Test status
Simulation time 19958536655 ps
CPU time 394.49 seconds
Started Aug 08 06:09:48 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 234556 kb
Host smart-ee82392f-dbc1-4c10-a73c-688206dd15d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421776757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.421776757
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2931890169
Short name T132
Test name
Test status
Simulation time 1975620576 ps
CPU time 22.9 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 220060 kb
Host smart-055cc42b-f06c-44f2-831f-8aa73bd47a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931890169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2931890169
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.826047501
Short name T118
Test name
Test status
Simulation time 628657738 ps
CPU time 10.75 seconds
Started Aug 08 06:09:44 PM PDT 24
Finished Aug 08 06:09:54 PM PDT 24
Peak memory 220016 kb
Host smart-24b82617-4e96-4410-8a8b-91e43a42d0fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826047501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.826047501
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.403434721
Short name T203
Test name
Test status
Simulation time 1102042876 ps
CPU time 43.28 seconds
Started Aug 08 06:09:50 PM PDT 24
Finished Aug 08 06:10:33 PM PDT 24
Peak memory 219980 kb
Host smart-ab5de671-7a62-49a1-8f84-f1cb87621f66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403434721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.403434721
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2407706298
Short name T3
Test name
Test status
Simulation time 787243509 ps
CPU time 8.4 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:10:05 PM PDT 24
Peak memory 219140 kb
Host smart-0c7cdc37-e204-4646-adfa-bfbb0a8224b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407706298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2407706298
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1542616844
Short name T152
Test name
Test status
Simulation time 38044793714 ps
CPU time 398.09 seconds
Started Aug 08 06:09:51 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 234636 kb
Host smart-7bf43199-7243-4f89-9866-deb7361f1cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542616844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1542616844
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1774405561
Short name T37
Test name
Test status
Simulation time 2761257688 ps
CPU time 19.35 seconds
Started Aug 08 06:09:44 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220228 kb
Host smart-9dfe54e7-fc4c-469a-9ad4-ed939384b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774405561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1774405561
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2793870277
Short name T244
Test name
Test status
Simulation time 180190045 ps
CPU time 10.45 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220000 kb
Host smart-15478d82-d162-468d-bae9-d00c0b6a4df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793870277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2793870277
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2710733549
Short name T31
Test name
Test status
Simulation time 766733614 ps
CPU time 38.67 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 220068 kb
Host smart-153d6fbb-5912-4a16-b5e6-75af44be7ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710733549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2710733549
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2009653801
Short name T155
Test name
Test status
Simulation time 505927013 ps
CPU time 10.07 seconds
Started Aug 08 06:09:50 PM PDT 24
Finished Aug 08 06:10:00 PM PDT 24
Peak memory 219116 kb
Host smart-2924bbed-ce9e-4216-a50a-da205112d0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009653801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2009653801
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2100950100
Short name T122
Test name
Test status
Simulation time 14840161078 ps
CPU time 219.14 seconds
Started Aug 08 06:09:45 PM PDT 24
Finished Aug 08 06:13:24 PM PDT 24
Peak memory 225788 kb
Host smart-62eba468-ec5e-4f25-8aaf-8000ff70006b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100950100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2100950100
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.220557574
Short name T304
Test name
Test status
Simulation time 2740354585 ps
CPU time 22.47 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 220292 kb
Host smart-1747ee12-b9d1-4481-9c42-6f20aec07fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220557574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.220557574
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.261212546
Short name T302
Test name
Test status
Simulation time 1076784873 ps
CPU time 12.23 seconds
Started Aug 08 06:09:47 PM PDT 24
Finished Aug 08 06:09:59 PM PDT 24
Peak memory 220072 kb
Host smart-3baa0e39-d7b4-4734-a3a2-9d3f8a897258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261212546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.261212546
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4026028161
Short name T287
Test name
Test status
Simulation time 552069969 ps
CPU time 31.36 seconds
Started Aug 08 06:09:48 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 220072 kb
Host smart-6cfa4d97-2d83-46ff-b208-af1d52ad3b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026028161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4026028161
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.137444199
Short name T171
Test name
Test status
Simulation time 989661363 ps
CPU time 10.23 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 219080 kb
Host smart-f6e5cbc8-666e-4058-9aa7-012ae9ba54fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137444199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.137444199
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.517573348
Short name T6
Test name
Test status
Simulation time 4568398419 ps
CPU time 276.31 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 243784 kb
Host smart-75a508a3-61be-4c86-99f4-158d9f099f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517573348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.517573348
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.256422957
Short name T4
Test name
Test status
Simulation time 3294665313 ps
CPU time 23.3 seconds
Started Aug 08 06:09:55 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 220176 kb
Host smart-cd633425-5394-48fc-bdf5-98c223da4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256422957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.256422957
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.786606504
Short name T283
Test name
Test status
Simulation time 263569123 ps
CPU time 12.62 seconds
Started Aug 08 06:09:55 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 220132 kb
Host smart-54ec921e-0587-44ed-9127-11a27e550723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786606504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.786606504
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3338410012
Short name T78
Test name
Test status
Simulation time 8075636982 ps
CPU time 50.92 seconds
Started Aug 08 06:09:46 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 222052 kb
Host smart-ecec8f33-98b5-409a-877c-9ddc6a73f425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338410012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3338410012
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1558514613
Short name T5
Test name
Test status
Simulation time 869793111 ps
CPU time 8.36 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 219036 kb
Host smart-a97bd489-938c-4a12-ab3c-9cfd382dd614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558514613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1558514613
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2647827695
Short name T39
Test name
Test status
Simulation time 3676015223 ps
CPU time 257.96 seconds
Started Aug 08 06:09:57 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 242756 kb
Host smart-273b6d1b-a0b9-448c-82b3-40a7f58acf73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647827695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2647827695
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3192026695
Short name T213
Test name
Test status
Simulation time 7846727691 ps
CPU time 32.87 seconds
Started Aug 08 06:09:59 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 220164 kb
Host smart-4d9cbbf2-ec2d-4dfe-b23c-a2a53e1fa57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192026695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3192026695
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1255688598
Short name T160
Test name
Test status
Simulation time 1022741052 ps
CPU time 12.37 seconds
Started Aug 08 06:09:57 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 220120 kb
Host smart-edde3886-cbdd-40ff-9369-1c0e26ac56da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255688598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1255688598
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1919214197
Short name T319
Test name
Test status
Simulation time 2469185283 ps
CPU time 24.71 seconds
Started Aug 08 06:09:54 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 220180 kb
Host smart-45f75193-da51-4a16-8c9f-1d66959c1eee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919214197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1919214197
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.901970699
Short name T137
Test name
Test status
Simulation time 170772925 ps
CPU time 8.7 seconds
Started Aug 08 06:09:58 PM PDT 24
Finished Aug 08 06:10:07 PM PDT 24
Peak memory 218884 kb
Host smart-073d1317-b2df-4d59-aedc-2cc1e91f2d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901970699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.901970699
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2310325899
Short name T176
Test name
Test status
Simulation time 5049819690 ps
CPU time 284.62 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 235488 kb
Host smart-a5760a18-4e79-4a25-b78c-f6f3b4c8b63f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310325899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2310325899
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2563923373
Short name T235
Test name
Test status
Simulation time 497251981 ps
CPU time 22.27 seconds
Started Aug 08 06:09:57 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 220012 kb
Host smart-37f2aba7-f30d-4482-8acb-b00bbe8ff4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563923373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2563923373
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2752477581
Short name T158
Test name
Test status
Simulation time 277012275 ps
CPU time 11.91 seconds
Started Aug 08 06:10:08 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 220084 kb
Host smart-eea76f4d-dfc2-4215-935d-94f79c419ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752477581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2752477581
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3096697667
Short name T278
Test name
Test status
Simulation time 1312535398 ps
CPU time 59.75 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 220812 kb
Host smart-569cf4db-43cc-43e9-9ab5-56757731ec9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096697667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3096697667
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.639503589
Short name T130
Test name
Test status
Simulation time 920140654 ps
CPU time 10.01 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 219152 kb
Host smart-9033d299-0b94-4d3a-9b9b-2e3dedaf2ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639503589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.639503589
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.277982785
Short name T40
Test name
Test status
Simulation time 5851661103 ps
CPU time 267.9 seconds
Started Aug 08 06:09:19 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 220052 kb
Host smart-eec4c70e-a7c5-4af7-b633-3798e5632425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277982785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.277982785
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.191272165
Short name T272
Test name
Test status
Simulation time 2207581190 ps
CPU time 18.69 seconds
Started Aug 08 06:09:22 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 220188 kb
Host smart-caf84086-9c71-4b0f-8230-cb71237c99d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191272165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.191272165
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1433493761
Short name T219
Test name
Test status
Simulation time 409757077 ps
CPU time 12.5 seconds
Started Aug 08 06:09:16 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 220128 kb
Host smart-525e30d1-5cfc-445a-a531-f8e6be3b19ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433493761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1433493761
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.868341547
Short name T27
Test name
Test status
Simulation time 333625420 ps
CPU time 118.78 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 236036 kb
Host smart-da1ad736-3872-423c-a62d-56e09d78e944
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868341547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.868341547
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.440489098
Short name T230
Test name
Test status
Simulation time 366061481 ps
CPU time 10.27 seconds
Started Aug 08 06:09:24 PM PDT 24
Finished Aug 08 06:09:34 PM PDT 24
Peak memory 220064 kb
Host smart-f3a33a4f-f638-45cf-b4a1-d832d072f521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440489098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.440489098
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3361826781
Short name T316
Test name
Test status
Simulation time 1345399097 ps
CPU time 24.13 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 220048 kb
Host smart-ec1777fb-e79e-413d-b39c-ffa9594d6bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361826781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3361826781
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3485179784
Short name T106
Test name
Test status
Simulation time 37992034640 ps
CPU time 731.97 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 232416 kb
Host smart-e5d02c35-ba99-4dc3-b25b-3b8e22688fdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485179784 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3485179784
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.592403390
Short name T33
Test name
Test status
Simulation time 170753400 ps
CPU time 8.22 seconds
Started Aug 08 06:09:55 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 219188 kb
Host smart-c003ec79-8495-4fc6-b2b3-dd0459456f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592403390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.592403390
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1452113579
Short name T322
Test name
Test status
Simulation time 38768608670 ps
CPU time 430.1 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 240096 kb
Host smart-642a15a1-3f8b-4db3-8e85-bd628a15ca2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452113579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1452113579
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.841873615
Short name T264
Test name
Test status
Simulation time 1440819060 ps
CPU time 19.05 seconds
Started Aug 08 06:09:54 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 220112 kb
Host smart-9539e9a7-6f34-40dd-b733-ebc772b677af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841873615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.841873615
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3285715746
Short name T289
Test name
Test status
Simulation time 735793904 ps
CPU time 10.71 seconds
Started Aug 08 06:09:55 PM PDT 24
Finished Aug 08 06:10:06 PM PDT 24
Peak memory 220080 kb
Host smart-bbf3ff9a-7b96-451a-bdba-3b63812462d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285715746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3285715746
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.740212969
Short name T306
Test name
Test status
Simulation time 230859103 ps
CPU time 19.64 seconds
Started Aug 08 06:10:03 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 220032 kb
Host smart-cd487ff2-a4a8-459d-a952-b7137c1450d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740212969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.740212969
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4117457046
Short name T53
Test name
Test status
Simulation time 49299492197 ps
CPU time 9519.92 seconds
Started Aug 08 06:09:57 PM PDT 24
Finished Aug 08 08:48:38 PM PDT 24
Peak memory 235928 kb
Host smart-f86cc2ec-a9c5-413f-bf15-4fe84fa09dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117457046 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.4117457046
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3020417654
Short name T240
Test name
Test status
Simulation time 518191564 ps
CPU time 10.08 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:10:06 PM PDT 24
Peak memory 219100 kb
Host smart-35cc7966-af08-4b55-9ce3-08c453ccb0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020417654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3020417654
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3536511411
Short name T163
Test name
Test status
Simulation time 1759724453 ps
CPU time 126.78 seconds
Started Aug 08 06:09:58 PM PDT 24
Finished Aug 08 06:12:05 PM PDT 24
Peak memory 220180 kb
Host smart-2b8347f8-93ef-4edf-895e-dddaa8a16ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536511411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3536511411
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4032984513
Short name T147
Test name
Test status
Simulation time 336533656 ps
CPU time 19.89 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 219988 kb
Host smart-0b9a26d8-236a-47d3-8118-877ea0e3f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032984513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4032984513
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2104788588
Short name T281
Test name
Test status
Simulation time 264317850 ps
CPU time 10.36 seconds
Started Aug 08 06:09:52 PM PDT 24
Finished Aug 08 06:10:03 PM PDT 24
Peak memory 220068 kb
Host smart-62ef4155-29c5-4c38-aa08-a0069a1e5320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104788588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2104788588
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1260607129
Short name T265
Test name
Test status
Simulation time 365684307 ps
CPU time 20.07 seconds
Started Aug 08 06:09:59 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 220044 kb
Host smart-aca77321-c8e7-490a-af69-353e55061981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260607129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1260607129
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1176139815
Short name T321
Test name
Test status
Simulation time 160288971244 ps
CPU time 1693.14 seconds
Started Aug 08 06:09:53 PM PDT 24
Finished Aug 08 06:38:07 PM PDT 24
Peak memory 244892 kb
Host smart-57dc5eb3-8283-42cb-89e6-f2bc62278372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176139815 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1176139815
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.309235850
Short name T200
Test name
Test status
Simulation time 663088333 ps
CPU time 8.59 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 219192 kb
Host smart-05bbe030-edf3-47c5-a0b9-3e717809eec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309235850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.309235850
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3625246527
Short name T19
Test name
Test status
Simulation time 3125482188 ps
CPU time 244.47 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 235280 kb
Host smart-75718832-0b70-4559-8654-d22979c54691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625246527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3625246527
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3778900432
Short name T275
Test name
Test status
Simulation time 1440865396 ps
CPU time 19.29 seconds
Started Aug 08 06:10:01 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 220072 kb
Host smart-ed708dff-4c08-40df-abd1-ba1b40554912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778900432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3778900432
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4257114293
Short name T262
Test name
Test status
Simulation time 185526603 ps
CPU time 10.76 seconds
Started Aug 08 06:09:57 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 220104 kb
Host smart-b4348ede-8b1f-4022-a1b2-a5fc2bb1617a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257114293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4257114293
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.726424597
Short name T250
Test name
Test status
Simulation time 44545304373 ps
CPU time 1898.12 seconds
Started Aug 08 06:09:56 PM PDT 24
Finished Aug 08 06:41:35 PM PDT 24
Peak memory 244860 kb
Host smart-9ee06043-4f45-4c3c-bb5e-eb3430e8f058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726424597 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.726424597
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1114984862
Short name T314
Test name
Test status
Simulation time 345372263 ps
CPU time 8.35 seconds
Started Aug 08 06:10:02 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 219144 kb
Host smart-cb57c644-45c2-4710-a18e-d795dda0b140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114984862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1114984862
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.543674718
Short name T300
Test name
Test status
Simulation time 4496521569 ps
CPU time 265.32 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 238968 kb
Host smart-e1d1b342-b01c-4978-8858-f6f58c490ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543674718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.543674718
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.827060529
Short name T303
Test name
Test status
Simulation time 1648499199 ps
CPU time 19.4 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 220108 kb
Host smart-0d686e31-d8c5-4b42-8ecc-9b7b6bfaa206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827060529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.827060529
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.659433261
Short name T318
Test name
Test status
Simulation time 696354486 ps
CPU time 10.65 seconds
Started Aug 08 06:10:03 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 220036 kb
Host smart-6dd0b8b1-fe45-488d-8767-0ec064319f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659433261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.659433261
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4093735401
Short name T205
Test name
Test status
Simulation time 1073556776 ps
CPU time 36.96 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 220312 kb
Host smart-66b98ff4-e1df-44da-9af5-7819fa55151c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093735401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4093735401
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2281102469
Short name T61
Test name
Test status
Simulation time 539619292 ps
CPU time 10.37 seconds
Started Aug 08 06:10:03 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 219280 kb
Host smart-073efc36-56e3-4c85-8edb-0973486880e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281102469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2281102469
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.864615046
Short name T20
Test name
Test status
Simulation time 2980117235 ps
CPU time 225.96 seconds
Started Aug 08 06:10:01 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 235304 kb
Host smart-bd2725ab-a84f-4d97-9e09-c0b929af168e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864615046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.864615046
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.243024605
Short name T215
Test name
Test status
Simulation time 333072871 ps
CPU time 19.25 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 220000 kb
Host smart-0ef76a3d-9d76-42e9-8b63-1985ef8ed0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243024605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.243024605
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2201577455
Short name T211
Test name
Test status
Simulation time 260476689 ps
CPU time 12.64 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:17 PM PDT 24
Peak memory 220144 kb
Host smart-a6a48969-c738-4e88-9c39-f2ec3d541116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201577455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2201577455
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3503712389
Short name T120
Test name
Test status
Simulation time 361364338 ps
CPU time 21.15 seconds
Started Aug 08 06:10:03 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 220080 kb
Host smart-e22c75f4-7192-4515-bdb7-94fdd70cbdbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503712389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3503712389
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1711277435
Short name T142
Test name
Test status
Simulation time 170849734 ps
CPU time 8.16 seconds
Started Aug 08 06:10:08 PM PDT 24
Finished Aug 08 06:10:17 PM PDT 24
Peak memory 219040 kb
Host smart-c4565f7e-fd50-4e47-8317-baf7d76e34e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711277435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1711277435
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2038228539
Short name T12
Test name
Test status
Simulation time 5770797571 ps
CPU time 283.47 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 218932 kb
Host smart-f797321a-64c0-4689-83cb-6212fd036d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038228539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2038228539
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2211229577
Short name T178
Test name
Test status
Simulation time 1331048559 ps
CPU time 10.35 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 220076 kb
Host smart-46fad63e-a012-48df-853a-8b0caa618054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211229577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2211229577
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3903378395
Short name T196
Test name
Test status
Simulation time 2415885246 ps
CPU time 20.67 seconds
Started Aug 08 06:10:01 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 220220 kb
Host smart-b9d7236f-3365-4191-a02f-b8b144b16b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903378395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3903378395
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.936496864
Short name T309
Test name
Test status
Simulation time 19170450323 ps
CPU time 701.85 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 230792 kb
Host smart-ac4de40e-69a7-4438-b918-f2fdf41bc5c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936496864 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.936496864
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2788604619
Short name T194
Test name
Test status
Simulation time 1026437164 ps
CPU time 10.2 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 219088 kb
Host smart-e56026a6-d99e-47be-954b-dcdfff3a1ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788604619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2788604619
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.400647607
Short name T149
Test name
Test status
Simulation time 14726514800 ps
CPU time 293.64 seconds
Started Aug 08 06:10:03 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 220376 kb
Host smart-48a52421-f2b9-4490-9b7d-eca47f0eb3cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400647607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.400647607
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.459256649
Short name T25
Test name
Test status
Simulation time 5504450852 ps
CPU time 19.4 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 220184 kb
Host smart-b7dcc21a-2c5e-4c4d-afe0-ccf6ae8139a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459256649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.459256649
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3375010097
Short name T274
Test name
Test status
Simulation time 505711257 ps
CPU time 10.74 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 220168 kb
Host smart-de3b5826-f3d2-4882-86b8-1637ff84deff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375010097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3375010097
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3325824073
Short name T282
Test name
Test status
Simulation time 807226435 ps
CPU time 42.3 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:51 PM PDT 24
Peak memory 220044 kb
Host smart-25abc48d-2772-4348-8d40-9d8e64980d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325824073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3325824073
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.344675097
Short name T49
Test name
Test status
Simulation time 12738021888 ps
CPU time 490.43 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 229872 kb
Host smart-06aa1fc3-7d36-4234-8e50-d4801b7ea728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344675097 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.344675097
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.716993387
Short name T124
Test name
Test status
Simulation time 263102163 ps
CPU time 10.03 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 218944 kb
Host smart-19ff6024-b357-4284-95ef-48e1aab00b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716993387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.716993387
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1506988553
Short name T38
Test name
Test status
Simulation time 3089579772 ps
CPU time 181 seconds
Started Aug 08 06:10:00 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 238432 kb
Host smart-974e6503-a48b-4f7e-a294-2e6cda764dca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506988553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1506988553
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1806658887
Short name T212
Test name
Test status
Simulation time 2602251396 ps
CPU time 23.05 seconds
Started Aug 08 06:10:02 PM PDT 24
Finished Aug 08 06:10:25 PM PDT 24
Peak memory 220264 kb
Host smart-77280d68-78b4-4614-bc12-297269d5d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806658887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1806658887
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1054913641
Short name T202
Test name
Test status
Simulation time 262165612 ps
CPU time 12.07 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 220072 kb
Host smart-bcb44a3a-2234-4cc5-8c6a-0511a986228a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054913641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1054913641
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2883440667
Short name T258
Test name
Test status
Simulation time 1065450928 ps
CPU time 27.77 seconds
Started Aug 08 06:10:01 PM PDT 24
Finished Aug 08 06:10:29 PM PDT 24
Peak memory 220072 kb
Host smart-6f215dbe-7758-4cad-bb87-7e0ada7cad3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883440667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2883440667
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1012131538
Short name T311
Test name
Test status
Simulation time 167380849 ps
CPU time 8.57 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 219136 kb
Host smart-80859935-2c52-4432-9e6d-50855b9fe02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012131538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1012131538
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1539759841
Short name T139
Test name
Test status
Simulation time 12334272746 ps
CPU time 377.28 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:16:27 PM PDT 24
Peak memory 239512 kb
Host smart-8f63ff13-adc2-456e-9361-a1d42568f88f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539759841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1539759841
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1005020784
Short name T223
Test name
Test status
Simulation time 6182589125 ps
CPU time 23.49 seconds
Started Aug 08 06:10:02 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 220236 kb
Host smart-23c0befc-b986-46a6-bd0b-ca9c4dabe235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005020784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1005020784
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.845619791
Short name T286
Test name
Test status
Simulation time 561970485 ps
CPU time 11.93 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:17 PM PDT 24
Peak memory 220056 kb
Host smart-2254783b-aaa4-4298-9bd1-7b9ed7b5312d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845619791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.845619791
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1002138966
Short name T214
Test name
Test status
Simulation time 2007871859 ps
CPU time 33.18 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:10:39 PM PDT 24
Peak memory 220056 kb
Host smart-538146b5-ee04-4286-88b7-88a6080da56a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002138966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1002138966
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3306165949
Short name T62
Test name
Test status
Simulation time 517742484 ps
CPU time 10.2 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 219976 kb
Host smart-e72c08e2-156d-407b-b8cb-9f637f7c3273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306165949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3306165949
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.838514783
Short name T209
Test name
Test status
Simulation time 4132832227 ps
CPU time 221.72 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:13:57 PM PDT 24
Peak memory 238588 kb
Host smart-7f3e1944-2707-4559-a6fa-b7be0abd7bd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838514783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.838514783
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3886937539
Short name T267
Test name
Test status
Simulation time 345891292 ps
CPU time 18.88 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 220152 kb
Host smart-91678b71-75ba-4ceb-966d-75a608a478dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886937539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3886937539
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2574772061
Short name T243
Test name
Test status
Simulation time 1039355510 ps
CPU time 16.74 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 219552 kb
Host smart-de22bf40-e235-4869-8600-137b94a67f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574772061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2574772061
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3753648363
Short name T79
Test name
Test status
Simulation time 838671404 ps
CPU time 43.54 seconds
Started Aug 08 06:10:08 PM PDT 24
Finished Aug 08 06:10:52 PM PDT 24
Peak memory 220548 kb
Host smart-425bec88-42ea-49ec-80f5-3cb44e58c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753648363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3753648363
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.785058825
Short name T185
Test name
Test status
Simulation time 661649856 ps
CPU time 8.54 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 219092 kb
Host smart-e50fcd1f-168f-42e2-bc83-0d27cb52dd0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785058825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.785058825
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.750591823
Short name T179
Test name
Test status
Simulation time 4892943229 ps
CPU time 120.65 seconds
Started Aug 08 06:09:22 PM PDT 24
Finished Aug 08 06:11:23 PM PDT 24
Peak memory 235556 kb
Host smart-34781b80-a9d0-4c42-af15-e542226f578a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750591823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.750591823
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1950729879
Short name T140
Test name
Test status
Simulation time 510661947 ps
CPU time 22.68 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:09:40 PM PDT 24
Peak memory 220092 kb
Host smart-56319d46-617b-4f98-958e-496b2f1c2aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950729879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1950729879
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2628280635
Short name T239
Test name
Test status
Simulation time 518629669 ps
CPU time 12.25 seconds
Started Aug 08 06:09:21 PM PDT 24
Finished Aug 08 06:09:34 PM PDT 24
Peak memory 220140 kb
Host smart-da0cde24-d204-476c-9ec0-c8c3790432d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628280635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2628280635
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3232799506
Short name T10
Test name
Test status
Simulation time 1099096169 ps
CPU time 12.07 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 220100 kb
Host smart-8e2930e5-d064-46cd-84df-a787f4e341a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232799506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3232799506
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3622780691
Short name T325
Test name
Test status
Simulation time 3341799198 ps
CPU time 38.89 seconds
Started Aug 08 06:09:17 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 220220 kb
Host smart-3b6bbb41-8941-42dd-848b-c2867c99bbff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622780691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3622780691
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.834839167
Short name T290
Test name
Test status
Simulation time 1169797335 ps
CPU time 10.01 seconds
Started Aug 08 06:09:26 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 219200 kb
Host smart-0a4b2145-54f9-453e-b2f1-7f8fce0d661e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834839167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.834839167
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.798774632
Short name T206
Test name
Test status
Simulation time 7749039393 ps
CPU time 240.86 seconds
Started Aug 08 06:09:19 PM PDT 24
Finished Aug 08 06:13:20 PM PDT 24
Peak memory 239688 kb
Host smart-acad290d-6eb7-47e4-a474-4a4388f77f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798774632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.798774632
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2898423056
Short name T201
Test name
Test status
Simulation time 677096883 ps
CPU time 19.68 seconds
Started Aug 08 06:09:33 PM PDT 24
Finished Aug 08 06:09:53 PM PDT 24
Peak memory 220132 kb
Host smart-3d3cc507-91b8-4d23-9d05-595c7293a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898423056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2898423056
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.417607335
Short name T103
Test name
Test status
Simulation time 175457586 ps
CPU time 10.49 seconds
Started Aug 08 06:09:30 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 220072 kb
Host smart-4aa0cf13-c383-42d2-8e25-af6644373fd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417607335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.417607335
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2788336312
Short name T75
Test name
Test status
Simulation time 181231009 ps
CPU time 10.75 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:31 PM PDT 24
Peak memory 220092 kb
Host smart-10b414f8-ca4e-43c6-aa09-6a56d17bff75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788336312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2788336312
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2174000310
Short name T279
Test name
Test status
Simulation time 663603717 ps
CPU time 8.43 seconds
Started Aug 08 06:09:21 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 219132 kb
Host smart-3caaaf12-3b1d-4374-9521-f9b33786bbb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174000310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2174000310
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2680968652
Short name T252
Test name
Test status
Simulation time 2176083505 ps
CPU time 139.67 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 220388 kb
Host smart-dc9d8a79-fdb6-4eea-8e44-0f2911551e6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680968652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2680968652
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2561997764
Short name T172
Test name
Test status
Simulation time 1980796801 ps
CPU time 22.2 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:09:41 PM PDT 24
Peak memory 220080 kb
Host smart-2e5bf139-4d8b-4079-9cac-040bad608d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561997764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2561997764
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2551048230
Short name T208
Test name
Test status
Simulation time 280229389 ps
CPU time 11.89 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:37 PM PDT 24
Peak memory 220160 kb
Host smart-90bcaab7-504d-433c-a186-6e2e6c81fd1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2551048230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2551048230
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.729935706
Short name T246
Test name
Test status
Simulation time 597367476 ps
CPU time 12.55 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 220280 kb
Host smart-4411eb0e-ff83-4e9d-95c7-727740374ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729935706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.729935706
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1612626993
Short name T169
Test name
Test status
Simulation time 4366391543 ps
CPU time 23.73 seconds
Started Aug 08 06:09:28 PM PDT 24
Finished Aug 08 06:09:52 PM PDT 24
Peak memory 220048 kb
Host smart-ce6f39cb-3ffb-4834-b0e4-b6f482c21a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612626993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1612626993
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1374336481
Short name T320
Test name
Test status
Simulation time 332270184 ps
CPU time 8.4 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:38 PM PDT 24
Peak memory 219024 kb
Host smart-fe719c1c-e7b5-41d9-8597-cf7a0d848d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374336481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1374336481
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.795217687
Short name T9
Test name
Test status
Simulation time 4792162496 ps
CPU time 332.04 seconds
Started Aug 08 06:09:18 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 238956 kb
Host smart-1b4c78e2-5610-448f-9104-b99598a16ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795217687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.795217687
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1151901705
Short name T180
Test name
Test status
Simulation time 336479082 ps
CPU time 19.31 seconds
Started Aug 08 06:09:25 PM PDT 24
Finished Aug 08 06:09:44 PM PDT 24
Peak memory 220072 kb
Host smart-ee20b64c-1847-439a-b6b2-dca62da7cde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151901705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1151901705
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2067272388
Short name T170
Test name
Test status
Simulation time 1017133273 ps
CPU time 11.82 seconds
Started Aug 08 06:09:19 PM PDT 24
Finished Aug 08 06:09:31 PM PDT 24
Peak memory 220092 kb
Host smart-5b10a27f-3d17-41c1-a83f-72f0a80eb9ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067272388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2067272388
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1617768304
Short name T260
Test name
Test status
Simulation time 1167445208 ps
CPU time 10.34 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:31 PM PDT 24
Peak memory 220080 kb
Host smart-e69516d1-23e6-4992-8334-5fdadad60609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617768304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1617768304
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1677864783
Short name T77
Test name
Test status
Simulation time 386038605 ps
CPU time 27.94 seconds
Started Aug 08 06:09:31 PM PDT 24
Finished Aug 08 06:09:59 PM PDT 24
Peak memory 220080 kb
Host smart-bf4e7a5b-a317-4a6a-9607-504bd2b2f66a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677864783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1677864783
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1096236867
Short name T157
Test name
Test status
Simulation time 496842122 ps
CPU time 22.28 seconds
Started Aug 08 06:09:34 PM PDT 24
Finished Aug 08 06:09:56 PM PDT 24
Peak memory 220100 kb
Host smart-ab63ea1d-1c64-4cfb-b1b8-2bc8993e356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096236867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1096236867
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4131416699
Short name T326
Test name
Test status
Simulation time 272338442 ps
CPU time 12.43 seconds
Started Aug 08 06:09:23 PM PDT 24
Finished Aug 08 06:09:35 PM PDT 24
Peak memory 220128 kb
Host smart-4731d404-0b15-4fbe-8e2a-b1a6ffe88fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131416699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4131416699
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2893008635
Short name T182
Test name
Test status
Simulation time 289296960 ps
CPU time 9.97 seconds
Started Aug 08 06:09:29 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 219996 kb
Host smart-1d359fb7-dfb8-4251-8ecb-0981c65a67a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893008635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2893008635
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2537459754
Short name T76
Test name
Test status
Simulation time 293402953 ps
CPU time 16.92 seconds
Started Aug 08 06:09:20 PM PDT 24
Finished Aug 08 06:09:37 PM PDT 24
Peak memory 220068 kb
Host smart-d5f9f92b-394b-4bf5-b872-fe1d67ef290e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537459754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2537459754
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2098751888
Short name T50
Test name
Test status
Simulation time 296108221823 ps
CPU time 2779.38 seconds
Started Aug 08 06:09:22 PM PDT 24
Finished Aug 08 06:55:42 PM PDT 24
Peak memory 253000 kb
Host smart-b71aed40-3153-4999-9a18-c128fbcc3d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098751888 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2098751888
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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