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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 96.89 91.85 97.68 100.00 98.28 97.30 98.37


Total test records in report: 430
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T294 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1396427249 Aug 09 05:48:34 PM PDT 24 Aug 09 06:11:37 PM PDT 24 240553274244 ps
T295 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1303953912 Aug 09 05:48:14 PM PDT 24 Aug 09 05:48:36 PM PDT 24 2154760494 ps
T296 /workspace/coverage/default/11.rom_ctrl_stress_all.1210305290 Aug 09 05:47:19 PM PDT 24 Aug 09 05:47:33 PM PDT 24 200345683 ps
T297 /workspace/coverage/default/12.rom_ctrl_stress_all.2536297969 Aug 09 05:47:23 PM PDT 24 Aug 09 05:47:53 PM PDT 24 1076917304 ps
T298 /workspace/coverage/default/27.rom_ctrl_alert_test.3721170571 Aug 09 05:48:09 PM PDT 24 Aug 09 05:48:19 PM PDT 24 265377021 ps
T299 /workspace/coverage/default/6.rom_ctrl_stress_all.1112171081 Aug 09 05:46:56 PM PDT 24 Aug 09 05:47:23 PM PDT 24 4309132731 ps
T300 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2747584339 Aug 09 05:48:34 PM PDT 24 Aug 09 05:48:56 PM PDT 24 501574038 ps
T301 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2571219611 Aug 09 05:48:23 PM PDT 24 Aug 09 05:48:42 PM PDT 24 336857838 ps
T302 /workspace/coverage/default/40.rom_ctrl_stress_all.2165494195 Aug 09 05:48:33 PM PDT 24 Aug 09 05:48:50 PM PDT 24 315991472 ps
T303 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.362234628 Aug 09 05:47:48 PM PDT 24 Aug 09 05:50:07 PM PDT 24 2149085998 ps
T304 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3616341059 Aug 09 05:47:28 PM PDT 24 Aug 09 05:47:52 PM PDT 24 515978233 ps
T305 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1157561345 Aug 09 05:47:17 PM PDT 24 Aug 09 05:47:37 PM PDT 24 333073006 ps
T306 /workspace/coverage/default/26.rom_ctrl_alert_test.1734278285 Aug 09 05:47:59 PM PDT 24 Aug 09 05:48:09 PM PDT 24 1027729641 ps
T307 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.377646434 Aug 09 05:48:58 PM PDT 24 Aug 09 05:49:10 PM PDT 24 1227605571 ps
T308 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1957513589 Aug 09 05:48:10 PM PDT 24 Aug 09 05:48:33 PM PDT 24 2738801812 ps
T309 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1775252317 Aug 09 05:47:57 PM PDT 24 Aug 09 05:48:16 PM PDT 24 332503108 ps
T310 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1008073870 Aug 09 05:48:59 PM PDT 24 Aug 09 05:49:19 PM PDT 24 1376545830 ps
T311 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.289924039 Aug 09 05:47:36 PM PDT 24 Aug 09 05:47:47 PM PDT 24 696290423 ps
T312 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2812771613 Aug 09 05:48:09 PM PDT 24 Aug 09 06:01:58 PM PDT 24 20665021765 ps
T313 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1231965023 Aug 09 05:48:10 PM PDT 24 Aug 09 05:51:59 PM PDT 24 41898247792 ps
T314 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1725973938 Aug 09 05:48:10 PM PDT 24 Aug 09 05:48:42 PM PDT 24 1974789450 ps
T315 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2698807855 Aug 09 05:46:50 PM PDT 24 Aug 09 05:52:36 PM PDT 24 17729989835 ps
T316 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.657885821 Aug 09 05:48:26 PM PDT 24 Aug 09 05:48:36 PM PDT 24 371032613 ps
T317 /workspace/coverage/default/39.rom_ctrl_alert_test.2390142974 Aug 09 05:48:38 PM PDT 24 Aug 09 05:48:47 PM PDT 24 459386229 ps
T318 /workspace/coverage/default/20.rom_ctrl_alert_test.4102543781 Aug 09 05:47:42 PM PDT 24 Aug 09 05:47:52 PM PDT 24 259196688 ps
T319 /workspace/coverage/default/0.rom_ctrl_smoke.965539698 Aug 09 05:46:33 PM PDT 24 Aug 09 05:46:46 PM PDT 24 565225862 ps
T320 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1062616048 Aug 09 05:47:54 PM PDT 24 Aug 09 05:48:14 PM PDT 24 1224599749 ps
T321 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3404132328 Aug 09 05:48:02 PM PDT 24 Aug 09 05:48:21 PM PDT 24 333612967 ps
T322 /workspace/coverage/default/12.rom_ctrl_alert_test.3963733203 Aug 09 05:47:23 PM PDT 24 Aug 09 05:47:33 PM PDT 24 253919587 ps
T323 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.733683719 Aug 09 05:48:08 PM PDT 24 Aug 09 05:50:23 PM PDT 24 13670833647 ps
T324 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2253126313 Aug 09 05:47:44 PM PDT 24 Aug 09 06:35:17 PM PDT 24 296932304629 ps
T325 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2946786294 Aug 09 05:48:23 PM PDT 24 Aug 09 05:48:33 PM PDT 24 703676848 ps
T326 /workspace/coverage/default/35.rom_ctrl_stress_all.2358856508 Aug 09 05:48:22 PM PDT 24 Aug 09 05:48:49 PM PDT 24 1919659302 ps
T327 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3437964711 Aug 09 05:47:03 PM PDT 24 Aug 09 05:47:16 PM PDT 24 2586044724 ps
T328 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3981668549 Aug 09 05:47:50 PM PDT 24 Aug 09 05:48:13 PM PDT 24 1033545443 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2604363801 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:21 PM PDT 24 171526272 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1210870544 Aug 09 07:15:16 PM PDT 24 Aug 09 07:16:42 PM PDT 24 1275377331 ps
T329 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1729673012 Aug 09 07:15:13 PM PDT 24 Aug 09 07:15:28 PM PDT 24 1457417350 ps
T70 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1936787064 Aug 09 07:16:34 PM PDT 24 Aug 09 07:16:42 PM PDT 24 220267378 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2384087729 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:23 PM PDT 24 1899920487 ps
T330 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2809692731 Aug 09 07:15:34 PM PDT 24 Aug 09 07:15:45 PM PDT 24 271464172 ps
T331 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3951352845 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:45 PM PDT 24 1034369258 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2152650823 Aug 09 07:15:58 PM PDT 24 Aug 09 07:17:33 PM PDT 24 24761080439 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2818340668 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:41 PM PDT 24 707256399 ps
T332 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.874253726 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:56 PM PDT 24 347820562 ps
T333 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3705981890 Aug 09 07:15:33 PM PDT 24 Aug 09 07:15:42 PM PDT 24 1223879635 ps
T81 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2369309934 Aug 09 07:15:20 PM PDT 24 Aug 09 07:15:28 PM PDT 24 688504687 ps
T64 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3663462633 Aug 09 07:15:33 PM PDT 24 Aug 09 07:18:08 PM PDT 24 4281497046 ps
T82 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.258349401 Aug 09 07:16:34 PM PDT 24 Aug 09 07:16:44 PM PDT 24 251659798 ps
T111 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2861917231 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:46 PM PDT 24 3933712402 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.88159313 Aug 09 07:15:21 PM PDT 24 Aug 09 07:15:29 PM PDT 24 194611347 ps
T334 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.347812901 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:40 PM PDT 24 727976633 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1868410587 Aug 09 07:15:52 PM PDT 24 Aug 09 07:18:30 PM PDT 24 635859122 ps
T335 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.988690260 Aug 09 07:16:35 PM PDT 24 Aug 09 07:16:46 PM PDT 24 282989665 ps
T84 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3334085901 Aug 09 07:15:40 PM PDT 24 Aug 09 07:15:48 PM PDT 24 338763341 ps
T336 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3913036546 Aug 09 07:15:39 PM PDT 24 Aug 09 07:15:49 PM PDT 24 579106783 ps
T337 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3596580524 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:40 PM PDT 24 254496962 ps
T338 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2090800976 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:42 PM PDT 24 260744314 ps
T120 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4118611470 Aug 09 07:15:17 PM PDT 24 Aug 09 07:16:40 PM PDT 24 1109795861 ps
T339 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.317495004 Aug 09 07:15:39 PM PDT 24 Aug 09 07:15:49 PM PDT 24 491360639 ps
T340 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.708724279 Aug 09 07:15:39 PM PDT 24 Aug 09 07:15:53 PM PDT 24 997919900 ps
T341 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.373665465 Aug 09 07:15:23 PM PDT 24 Aug 09 07:15:33 PM PDT 24 250239325 ps
T342 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.553495986 Aug 09 07:15:29 PM PDT 24 Aug 09 07:15:38 PM PDT 24 189788038 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3354996226 Aug 09 07:15:11 PM PDT 24 Aug 09 07:15:20 PM PDT 24 176217284 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1838022320 Aug 09 07:15:28 PM PDT 24 Aug 09 07:15:38 PM PDT 24 1300638393 ps
T343 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1300688339 Aug 09 07:15:16 PM PDT 24 Aug 09 07:15:32 PM PDT 24 1030371949 ps
T344 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2998794529 Aug 09 07:15:17 PM PDT 24 Aug 09 07:15:31 PM PDT 24 264930628 ps
T345 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.39907775 Aug 09 07:15:22 PM PDT 24 Aug 09 07:15:34 PM PDT 24 511312124 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.557726238 Aug 09 07:15:18 PM PDT 24 Aug 09 07:16:02 PM PDT 24 2112794845 ps
T346 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2760934856 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:22 PM PDT 24 260713239 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.115618246 Aug 09 07:15:23 PM PDT 24 Aug 09 07:17:59 PM PDT 24 334522709 ps
T347 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4191094726 Aug 09 07:15:13 PM PDT 24 Aug 09 07:15:25 PM PDT 24 167356794 ps
T348 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1205011003 Aug 09 07:15:08 PM PDT 24 Aug 09 07:15:18 PM PDT 24 399303516 ps
T349 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3820710420 Aug 09 07:15:11 PM PDT 24 Aug 09 07:15:20 PM PDT 24 682359594 ps
T350 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3895299293 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:54 PM PDT 24 3295902814 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.418897738 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:56 PM PDT 24 174308089 ps
T351 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3818955504 Aug 09 07:16:35 PM PDT 24 Aug 09 07:16:49 PM PDT 24 1077688870 ps
T113 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.17407576 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:44 PM PDT 24 539307779 ps
T352 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3676499980 Aug 09 07:15:37 PM PDT 24 Aug 09 07:15:48 PM PDT 24 1033351365 ps
T353 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.393325938 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:28 PM PDT 24 261422649 ps
T354 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2742418124 Aug 09 07:15:09 PM PDT 24 Aug 09 07:15:20 PM PDT 24 251171536 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3212028475 Aug 09 07:15:31 PM PDT 24 Aug 09 07:16:16 PM PDT 24 1018774536 ps
T119 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1515466965 Aug 09 07:16:24 PM PDT 24 Aug 09 07:18:55 PM PDT 24 1685565356 ps
T96 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3290864597 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:39 PM PDT 24 1033648289 ps
T355 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3220268417 Aug 09 07:15:58 PM PDT 24 Aug 09 07:16:08 PM PDT 24 281486668 ps
T356 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3937813073 Aug 09 07:15:07 PM PDT 24 Aug 09 07:15:17 PM PDT 24 989171202 ps
T357 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1868883469 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:41 PM PDT 24 497078161 ps
T358 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2821969906 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:30 PM PDT 24 346932003 ps
T359 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3917491842 Aug 09 07:15:29 PM PDT 24 Aug 09 07:15:42 PM PDT 24 172604144 ps
T360 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.803696237 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:21 PM PDT 24 1207576810 ps
T361 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4117391538 Aug 09 07:15:33 PM PDT 24 Aug 09 07:15:47 PM PDT 24 4112935863 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3678281811 Aug 09 07:15:16 PM PDT 24 Aug 09 07:15:25 PM PDT 24 173684600 ps
T363 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3256813010 Aug 09 07:15:29 PM PDT 24 Aug 09 07:18:05 PM PDT 24 341958061 ps
T364 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1891776824 Aug 09 07:15:28 PM PDT 24 Aug 09 07:15:41 PM PDT 24 262000986 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2512717938 Aug 09 07:15:27 PM PDT 24 Aug 09 07:15:38 PM PDT 24 1908697681 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1351947448 Aug 09 07:15:15 PM PDT 24 Aug 09 07:15:25 PM PDT 24 254602831 ps
T117 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1948210560 Aug 09 07:15:44 PM PDT 24 Aug 09 07:18:21 PM PDT 24 1975856062 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2734955839 Aug 09 07:15:17 PM PDT 24 Aug 09 07:15:28 PM PDT 24 175067761 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.584765937 Aug 09 07:15:34 PM PDT 24 Aug 09 07:15:45 PM PDT 24 1075996843 ps
T118 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1902381035 Aug 09 07:15:18 PM PDT 24 Aug 09 07:18:01 PM PDT 24 1513601841 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2260472506 Aug 09 07:15:28 PM PDT 24 Aug 09 07:18:04 PM PDT 24 1445157678 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1989384511 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:58 PM PDT 24 332250121 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1232082383 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:39 PM PDT 24 719046099 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1411267145 Aug 09 07:15:22 PM PDT 24 Aug 09 07:15:33 PM PDT 24 263135559 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3077742952 Aug 09 07:15:20 PM PDT 24 Aug 09 07:15:30 PM PDT 24 527320078 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1293418499 Aug 09 07:15:32 PM PDT 24 Aug 09 07:15:42 PM PDT 24 496022687 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.113821131 Aug 09 07:15:13 PM PDT 24 Aug 09 07:15:23 PM PDT 24 986844885 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4290939712 Aug 09 07:16:24 PM PDT 24 Aug 09 07:16:38 PM PDT 24 249767186 ps
T377 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.850467550 Aug 09 07:15:20 PM PDT 24 Aug 09 07:16:41 PM PDT 24 1366890768 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.680637383 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:27 PM PDT 24 828363875 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1488229731 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:26 PM PDT 24 689745239 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1368970084 Aug 09 07:15:28 PM PDT 24 Aug 09 07:15:36 PM PDT 24 414032446 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4201786868 Aug 09 07:15:20 PM PDT 24 Aug 09 07:15:29 PM PDT 24 496811744 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1818410617 Aug 09 07:15:35 PM PDT 24 Aug 09 07:15:52 PM PDT 24 265654514 ps
T382 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3639105985 Aug 09 07:15:29 PM PDT 24 Aug 09 07:15:43 PM PDT 24 991627579 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2763262891 Aug 09 07:15:41 PM PDT 24 Aug 09 07:15:52 PM PDT 24 1105517003 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1307882348 Aug 09 07:15:24 PM PDT 24 Aug 09 07:15:36 PM PDT 24 363986806 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.661827744 Aug 09 07:15:16 PM PDT 24 Aug 09 07:15:26 PM PDT 24 1032079778 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2371131005 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:21 PM PDT 24 185071492 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2690075695 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:33 PM PDT 24 178883713 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3694625563 Aug 09 07:15:23 PM PDT 24 Aug 09 07:15:34 PM PDT 24 275036776 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1776192721 Aug 09 07:15:28 PM PDT 24 Aug 09 07:15:38 PM PDT 24 1182419342 ps
T99 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1993950359 Aug 09 07:15:19 PM PDT 24 Aug 09 07:15:56 PM PDT 24 724111220 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1310977929 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:41 PM PDT 24 252583669 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1597285601 Aug 09 07:15:39 PM PDT 24 Aug 09 07:15:49 PM PDT 24 260127121 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.154877022 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:42 PM PDT 24 522086083 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3769032908 Aug 09 07:15:15 PM PDT 24 Aug 09 07:15:52 PM PDT 24 4042757141 ps
T391 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.755281948 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:53 PM PDT 24 729369516 ps
T106 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.169614060 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:46 PM PDT 24 1419525784 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3303388216 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:43 PM PDT 24 984051409 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1865287652 Aug 09 07:15:18 PM PDT 24 Aug 09 07:15:32 PM PDT 24 259847211 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3062244369 Aug 09 07:15:20 PM PDT 24 Aug 09 07:15:29 PM PDT 24 338574125 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3993218503 Aug 09 07:15:19 PM PDT 24 Aug 09 07:15:28 PM PDT 24 922087342 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1882994373 Aug 09 07:15:19 PM PDT 24 Aug 09 07:16:43 PM PDT 24 346717298 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4043919246 Aug 09 07:15:08 PM PDT 24 Aug 09 07:15:22 PM PDT 24 663399117 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3024661764 Aug 09 07:15:31 PM PDT 24 Aug 09 07:15:43 PM PDT 24 562538493 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4067341226 Aug 09 07:15:15 PM PDT 24 Aug 09 07:15:23 PM PDT 24 689673110 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2395424197 Aug 09 07:15:07 PM PDT 24 Aug 09 07:15:17 PM PDT 24 2070011623 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2562172277 Aug 09 07:15:12 PM PDT 24 Aug 09 07:15:22 PM PDT 24 1032136211 ps
T399 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1851089086 Aug 09 07:15:36 PM PDT 24 Aug 09 07:18:20 PM PDT 24 1144761804 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3437756752 Aug 09 07:15:31 PM PDT 24 Aug 09 07:16:56 PM PDT 24 1544668234 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1791708623 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:57 PM PDT 24 1024256002 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2722058102 Aug 09 07:15:39 PM PDT 24 Aug 09 07:15:49 PM PDT 24 261442404 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1239333081 Aug 09 07:15:09 PM PDT 24 Aug 09 07:16:34 PM PDT 24 468680918 ps
T103 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1270215678 Aug 09 07:15:17 PM PDT 24 Aug 09 07:16:01 PM PDT 24 1028440606 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2004012301 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:40 PM PDT 24 520712157 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1986863857 Aug 09 07:15:15 PM PDT 24 Aug 09 07:15:25 PM PDT 24 1030353937 ps
T123 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.130174956 Aug 09 07:16:35 PM PDT 24 Aug 09 07:19:05 PM PDT 24 496658313 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3494143173 Aug 09 07:15:31 PM PDT 24 Aug 09 07:16:15 PM PDT 24 2599537010 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.203386059 Aug 09 07:15:29 PM PDT 24 Aug 09 07:15:41 PM PDT 24 340858787 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1302395393 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:40 PM PDT 24 514499264 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.248514455 Aug 09 07:15:29 PM PDT 24 Aug 09 07:16:26 PM PDT 24 4122731003 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.167198929 Aug 09 07:15:13 PM PDT 24 Aug 09 07:16:19 PM PDT 24 6109140176 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3703368291 Aug 09 07:15:33 PM PDT 24 Aug 09 07:15:41 PM PDT 24 339794067 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4268587849 Aug 09 07:15:38 PM PDT 24 Aug 09 07:16:16 PM PDT 24 2878401671 ps
T411 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4181855959 Aug 09 07:16:24 PM PDT 24 Aug 09 07:17:07 PM PDT 24 1245621211 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.117838354 Aug 09 07:15:18 PM PDT 24 Aug 09 07:16:25 PM PDT 24 10844632696 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1010302725 Aug 09 07:16:35 PM PDT 24 Aug 09 07:17:37 PM PDT 24 5427757326 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3375659591 Aug 09 07:15:39 PM PDT 24 Aug 09 07:16:25 PM PDT 24 7811966516 ps
T412 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.937293493 Aug 09 07:15:27 PM PDT 24 Aug 09 07:15:39 PM PDT 24 174368138 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2529270174 Aug 09 07:15:33 PM PDT 24 Aug 09 07:15:43 PM PDT 24 515411187 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2494966860 Aug 09 07:15:54 PM PDT 24 Aug 09 07:16:09 PM PDT 24 257642118 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3699384649 Aug 09 07:15:29 PM PDT 24 Aug 09 07:15:40 PM PDT 24 257581644 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2322566429 Aug 09 07:15:42 PM PDT 24 Aug 09 07:15:50 PM PDT 24 1186080030 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.372361962 Aug 09 07:15:37 PM PDT 24 Aug 09 07:15:51 PM PDT 24 274340319 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1927012503 Aug 09 07:16:24 PM PDT 24 Aug 09 07:16:37 PM PDT 24 176997670 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3415730930 Aug 09 07:15:28 PM PDT 24 Aug 09 07:16:53 PM PDT 24 319536086 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4149086850 Aug 09 07:15:27 PM PDT 24 Aug 09 07:16:50 PM PDT 24 5853859480 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.455054813 Aug 09 07:15:13 PM PDT 24 Aug 09 07:15:58 PM PDT 24 14467827464 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.358567917 Aug 09 07:15:38 PM PDT 24 Aug 09 07:15:48 PM PDT 24 656553701 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.339765 Aug 09 07:15:22 PM PDT 24 Aug 09 07:16:44 PM PDT 24 1021878257 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1757493350 Aug 09 07:15:10 PM PDT 24 Aug 09 07:15:25 PM PDT 24 750967246 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3552808807 Aug 09 07:15:53 PM PDT 24 Aug 09 07:16:56 PM PDT 24 24734972246 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.598849461 Aug 09 07:15:31 PM PDT 24 Aug 09 07:16:35 PM PDT 24 15845150065 ps
T105 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.668924903 Aug 09 07:15:18 PM PDT 24 Aug 09 07:16:24 PM PDT 24 1790318221 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.712156135 Aug 09 07:15:30 PM PDT 24 Aug 09 07:15:38 PM PDT 24 3297625221 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3570800141 Aug 09 07:15:21 PM PDT 24 Aug 09 07:15:33 PM PDT 24 177031694 ps
T429 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1453716551 Aug 09 07:15:44 PM PDT 24 Aug 09 07:16:22 PM PDT 24 1379707131 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.564308989 Aug 09 07:16:34 PM PDT 24 Aug 09 07:16:45 PM PDT 24 186062535 ps
T122 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.952771207 Aug 09 07:15:31 PM PDT 24 Aug 09 07:16:57 PM PDT 24 1191582350 ps

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3655568713
Short name T4
Test name
Test status
Simulation time 4256666105 ps
CPU time 294.07 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:52:12 PM PDT 24
Peak memory 226564 kb
Host smart-4f0ac298-6cf4-4afa-a898-bd0122f7d641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655568713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3655568713
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.489489484
Short name T12
Test name
Test status
Simulation time 53957225843 ps
CPU time 497.51 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:55:36 PM PDT 24
Peak memory 230928 kb
Host smart-89527179-77ed-4891-a4ad-aaecea191aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489489484 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.489489484
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3469306434
Short name T6
Test name
Test status
Simulation time 21097646042 ps
CPU time 275.52 seconds
Started Aug 09 05:48:26 PM PDT 24
Finished Aug 09 05:53:02 PM PDT 24
Peak memory 220324 kb
Host smart-bde55de0-b0cf-41ba-8e4e-77513e7081ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469306434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3469306434
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.115618246
Short name T116
Test name
Test status
Simulation time 334522709 ps
CPU time 156.26 seconds
Started Aug 09 07:15:23 PM PDT 24
Finished Aug 09 07:17:59 PM PDT 24
Peak memory 219512 kb
Host smart-ba9aedf5-dcd8-4a2d-aeed-3994b3695382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115618246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.115618246
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1861239592
Short name T47
Test name
Test status
Simulation time 4672224810 ps
CPU time 263.19 seconds
Started Aug 09 05:47:11 PM PDT 24
Finished Aug 09 05:51:34 PM PDT 24
Peak memory 234468 kb
Host smart-8be6a423-7086-4d10-bdf6-158700d11b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861239592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1861239592
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1106985936
Short name T13
Test name
Test status
Simulation time 202900782 ps
CPU time 17.29 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:56 PM PDT 24
Peak memory 220036 kb
Host smart-ef22752e-0ba2-4dac-894c-33ce94a20e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106985936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1106985936
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.172059998
Short name T30
Test name
Test status
Simulation time 4726793678 ps
CPU time 37.75 seconds
Started Aug 09 05:47:57 PM PDT 24
Finished Aug 09 05:48:34 PM PDT 24
Peak memory 221544 kb
Host smart-e7ae71ad-6d0a-4d34-8e5f-a316474d6260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172059998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.172059998
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2861267511
Short name T22
Test name
Test status
Simulation time 1474100167 ps
CPU time 227.76 seconds
Started Aug 09 05:46:35 PM PDT 24
Finished Aug 09 05:50:23 PM PDT 24
Peak memory 239888 kb
Host smart-e4faf28c-7ec0-4e65-973a-36ac280d25d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861267511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2861267511
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2152650823
Short name T80
Test name
Test status
Simulation time 24761080439 ps
CPU time 95.71 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:17:33 PM PDT 24
Peak memory 216328 kb
Host smart-3caffa27-1353-42d8-9922-c56c41d4a047
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152650823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2152650823
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.519823519
Short name T125
Test name
Test status
Simulation time 3805280992 ps
CPU time 15.2 seconds
Started Aug 09 05:48:27 PM PDT 24
Finished Aug 09 05:48:42 PM PDT 24
Peak memory 219184 kb
Host smart-26f3deba-3626-4b82-9011-6771c064d88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519823519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.519823519
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3090141039
Short name T25
Test name
Test status
Simulation time 502801358 ps
CPU time 22.7 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:47:41 PM PDT 24
Peak memory 219964 kb
Host smart-3e663fd0-d75c-4bab-8c3d-3ea422c9f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090141039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3090141039
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4007127760
Short name T29
Test name
Test status
Simulation time 332112294 ps
CPU time 19.18 seconds
Started Aug 09 05:47:30 PM PDT 24
Finished Aug 09 05:47:49 PM PDT 24
Peak memory 220020 kb
Host smart-975a2ea0-efd7-439e-9435-91564dc065fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007127760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4007127760
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3415730930
Short name T419
Test name
Test status
Simulation time 319536086 ps
CPU time 84.81 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:16:53 PM PDT 24
Peak memory 219496 kb
Host smart-34568147-91ca-49bc-b733-1c41cdd4c484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415730930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3415730930
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1902381035
Short name T118
Test name
Test status
Simulation time 1513601841 ps
CPU time 162.85 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 214884 kb
Host smart-fb142f5f-da47-451d-b311-6a6a58ffd1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902381035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1902381035
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3262651466
Short name T9
Test name
Test status
Simulation time 13136014393 ps
CPU time 196.32 seconds
Started Aug 09 05:46:33 PM PDT 24
Finished Aug 09 05:49:49 PM PDT 24
Peak memory 238536 kb
Host smart-4ee208a1-725c-4655-8a75-697c1ef6660a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262651466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3262651466
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1515466965
Short name T119
Test name
Test status
Simulation time 1685565356 ps
CPU time 150.14 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:18:55 PM PDT 24
Peak memory 212880 kb
Host smart-380e4168-3cfc-468b-ab11-ab97f10c9d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515466965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1515466965
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1868410587
Short name T65
Test name
Test status
Simulation time 635859122 ps
CPU time 158.48 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 214992 kb
Host smart-b8d81782-fe20-4cec-b4b9-ea0d822c0ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868410587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1868410587
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3375659591
Short name T114
Test name
Test status
Simulation time 7811966516 ps
CPU time 45.9 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:16:25 PM PDT 24
Peak memory 215228 kb
Host smart-4f78fcc0-85f1-4bc8-8e97-4a1aa87cff85
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375659591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3375659591
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1239333081
Short name T115
Test name
Test status
Simulation time 468680918 ps
CPU time 85.14 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:16:34 PM PDT 24
Peak memory 215552 kb
Host smart-6379b7e5-7e0c-4945-af28-f887d0bb8fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239333081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1239333081
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1543666986
Short name T14
Test name
Test status
Simulation time 53719368033 ps
CPU time 506.16 seconds
Started Aug 09 05:47:47 PM PDT 24
Finished Aug 09 05:56:14 PM PDT 24
Peak memory 231156 kb
Host smart-b9a43012-7ec8-42a9-8c77-fe2baecd6101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543666986 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1543666986
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.393325938
Short name T353
Test name
Test status
Simulation time 261422649 ps
CPU time 10.09 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 211444 kb
Host smart-c519ed94-d4d5-46c5-b2a2-0c6801c4aeb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393325938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.393325938
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3937813073
Short name T356
Test name
Test status
Simulation time 989171202 ps
CPU time 10.01 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:17 PM PDT 24
Peak memory 211468 kb
Host smart-bbc1e87e-6b33-43ef-86fc-31c8e21a4313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937813073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3937813073
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3570800141
Short name T428
Test name
Test status
Simulation time 177031694 ps
CPU time 11.79 seconds
Started Aug 09 07:15:21 PM PDT 24
Finished Aug 09 07:15:33 PM PDT 24
Peak memory 211372 kb
Host smart-32f3350f-caaf-435a-b207-77157e486800
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570800141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3570800141
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3303388216
Short name T392
Test name
Test status
Simulation time 984051409 ps
CPU time 11.81 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 218456 kb
Host smart-8512dd9b-0675-43d5-ad65-12d1faf007a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303388216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3303388216
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.661827744
Short name T385
Test name
Test status
Simulation time 1032079778 ps
CPU time 10.06 seconds
Started Aug 09 07:15:16 PM PDT 24
Finished Aug 09 07:15:26 PM PDT 24
Peak memory 211604 kb
Host smart-e2eef35c-1f7a-44ff-97fe-158aad033d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661827744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.661827744
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.113821131
Short name T375
Test name
Test status
Simulation time 986844885 ps
CPU time 9.72 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:23 PM PDT 24
Peak memory 211208 kb
Host smart-3cd45a0e-0be8-4136-8b33-fe41b2dabdf9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113821131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.113821131
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.373665465
Short name T341
Test name
Test status
Simulation time 250239325 ps
CPU time 9.95 seconds
Started Aug 09 07:15:23 PM PDT 24
Finished Aug 09 07:15:33 PM PDT 24
Peak memory 211164 kb
Host smart-0e43944c-e26b-4289-9475-0de33b808e27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373665465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
373665465
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.557726238
Short name T86
Test name
Test status
Simulation time 2112794845 ps
CPU time 44.27 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 214460 kb
Host smart-b5cc4eac-c2a9-4454-88d7-8ef367bcd70c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557726238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.557726238
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1351947448
Short name T366
Test name
Test status
Simulation time 254602831 ps
CPU time 10.23 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 211964 kb
Host smart-227cb65f-a741-41ef-be35-a98eb066a3ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351947448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1351947448
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4043919246
Short name T395
Test name
Test status
Simulation time 663399117 ps
CPU time 14.06 seconds
Started Aug 09 07:15:08 PM PDT 24
Finished Aug 09 07:15:22 PM PDT 24
Peak memory 218372 kb
Host smart-73aa9f3b-b22a-46cd-bcb2-c1014297fc35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043919246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4043919246
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2384087729
Short name T79
Test name
Test status
Simulation time 1899920487 ps
CPU time 10.07 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:23 PM PDT 24
Peak memory 211512 kb
Host smart-f5920b72-a7a6-4808-800c-4dc76fb1ea34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384087729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2384087729
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.358567917
Short name T422
Test name
Test status
Simulation time 656553701 ps
CPU time 10.1 seconds
Started Aug 09 07:15:38 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 211288 kb
Host smart-11d21e93-0caf-453a-8e57-d40b40e4ada0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358567917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.358567917
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.708724279
Short name T340
Test name
Test status
Simulation time 997919900 ps
CPU time 13.46 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 211300 kb
Host smart-ba5cc183-823e-43bc-94e4-cbbf0330cf36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708724279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.708724279
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3820710420
Short name T349
Test name
Test status
Simulation time 682359594 ps
CPU time 8.57 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:20 PM PDT 24
Peak memory 214844 kb
Host smart-948bf3ff-2162-49ee-b211-fe89152f1add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820710420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3820710420
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.88159313
Short name T83
Test name
Test status
Simulation time 194611347 ps
CPU time 8.28 seconds
Started Aug 09 07:15:21 PM PDT 24
Finished Aug 09 07:15:29 PM PDT 24
Peak memory 211496 kb
Host smart-3a411f4e-e06f-47ff-bff3-0dc54b4d8fa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88159313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.88159313
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3895299293
Short name T350
Test name
Test status
Simulation time 3295902814 ps
CPU time 8.09 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:54 PM PDT 24
Peak memory 211204 kb
Host smart-77839d37-23d2-48de-897e-602303253fd7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895299293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3895299293
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2395424197
Short name T397
Test name
Test status
Simulation time 2070011623 ps
CPU time 9.86 seconds
Started Aug 09 07:15:07 PM PDT 24
Finished Aug 09 07:15:17 PM PDT 24
Peak memory 211232 kb
Host smart-a7708daf-cafb-4342-9fac-377baa486a97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395424197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2395424197
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3769032908
Short name T101
Test name
Test status
Simulation time 4042757141 ps
CPU time 37.5 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 214836 kb
Host smart-33c90b1c-c533-4257-a681-e74a15966705
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769032908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3769032908
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1307882348
Short name T384
Test name
Test status
Simulation time 363986806 ps
CPU time 11.88 seconds
Started Aug 09 07:15:24 PM PDT 24
Finished Aug 09 07:15:36 PM PDT 24
Peak memory 213196 kb
Host smart-c1ef6e12-4a56-4282-9875-de5c2223d7c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307882348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1307882348
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1729673012
Short name T329
Test name
Test status
Simulation time 1457417350 ps
CPU time 14.74 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 218300 kb
Host smart-a4ff5d74-b306-4072-97f2-0b7a772a2b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729673012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1729673012
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3705981890
Short name T333
Test name
Test status
Simulation time 1223879635 ps
CPU time 8.54 seconds
Started Aug 09 07:15:33 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 215572 kb
Host smart-2b982a18-81c5-4e53-bdc9-2e5adfd2c0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705981890 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3705981890
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2861917231
Short name T111
Test name
Test status
Simulation time 3933712402 ps
CPU time 14.63 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 212032 kb
Host smart-36e42af4-ee69-40d4-8f3e-475e4fcf1904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861917231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2861917231
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1270215678
Short name T103
Test name
Test status
Simulation time 1028440606 ps
CPU time 43.5 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 214444 kb
Host smart-3aa16c9b-b7a5-450e-a39a-0bec0aaaddf7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270215678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1270215678
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1597285601
Short name T389
Test name
Test status
Simulation time 260127121 ps
CPU time 10.31 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 212384 kb
Host smart-3518e784-b29d-4532-8146-3b96ab9835a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597285601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1597285601
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2821969906
Short name T358
Test name
Test status
Simulation time 346932003 ps
CPU time 11.82 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:30 PM PDT 24
Peak memory 218264 kb
Host smart-1fb58520-dc02-4e9d-b53c-ff1a40c048f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821969906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2821969906
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.850467550
Short name T377
Test name
Test status
Simulation time 1366890768 ps
CPU time 81.69 seconds
Started Aug 09 07:15:20 PM PDT 24
Finished Aug 09 07:16:41 PM PDT 24
Peak memory 214616 kb
Host smart-83303ce9-5f38-4b1f-b89f-bd1ad289d9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850467550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.850467550
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1411267145
Short name T372
Test name
Test status
Simulation time 263135559 ps
CPU time 10.35 seconds
Started Aug 09 07:15:22 PM PDT 24
Finished Aug 09 07:15:33 PM PDT 24
Peak memory 216616 kb
Host smart-5b221a6e-1cf0-482e-a7ef-5a14fc2e0790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411267145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1411267145
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4067341226
Short name T107
Test name
Test status
Simulation time 689673110 ps
CPU time 8.17 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:23 PM PDT 24
Peak memory 211468 kb
Host smart-bf6636e3-f70b-4cb3-a160-ddee1db0a870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067341226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4067341226
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1010302725
Short name T108
Test name
Test status
Simulation time 5427757326 ps
CPU time 61.19 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 215424 kb
Host smart-2469abe0-834b-4326-a2a6-348a41df1297
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010302725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1010302725
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2529270174
Short name T413
Test name
Test status
Simulation time 515411187 ps
CPU time 9.63 seconds
Started Aug 09 07:15:33 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 211920 kb
Host smart-6a8ea6b4-9725-4b3d-a148-23f8add4999c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529270174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2529270174
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1927012503
Short name T418
Test name
Test status
Simulation time 176997670 ps
CPU time 11.78 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:16:37 PM PDT 24
Peak memory 216472 kb
Host smart-7382ebcc-6dd2-47f8-a6c1-14ddf3e6f9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927012503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1927012503
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2809692731
Short name T330
Test name
Test status
Simulation time 271464172 ps
CPU time 10.85 seconds
Started Aug 09 07:15:34 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 216764 kb
Host smart-8acbcc57-36b2-474b-b160-4113ea3a327f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809692731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2809692731
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3334085901
Short name T84
Test name
Test status
Simulation time 338763341 ps
CPU time 8.21 seconds
Started Aug 09 07:15:40 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 211268 kb
Host smart-afa4f336-7fd9-4584-b748-7b2b91621b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334085901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3334085901
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.167198929
Short name T408
Test name
Test status
Simulation time 6109140176 ps
CPU time 66.6 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:16:19 PM PDT 24
Peak memory 215544 kb
Host smart-fc5fb8f2-d0d8-4f58-aaa7-cdc908d5e5a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167198929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.167198929
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3220268417
Short name T355
Test name
Test status
Simulation time 281486668 ps
CPU time 9.88 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:08 PM PDT 24
Peak memory 211840 kb
Host smart-2e9e07aa-929c-4141-84b5-6b15e0ae7580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220268417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3220268417
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1865287652
Short name T393
Test name
Test status
Simulation time 259847211 ps
CPU time 14.66 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:32 PM PDT 24
Peak memory 219368 kb
Host smart-54fc56b4-a196-4442-ae6c-c7a29b60fb27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865287652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1865287652
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.317495004
Short name T339
Test name
Test status
Simulation time 491360639 ps
CPU time 10.78 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 217588 kb
Host smart-07ababbd-0a2c-47bb-b880-3bb2501417c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317495004 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.317495004
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.169614060
Short name T106
Test name
Test status
Simulation time 1419525784 ps
CPU time 14.87 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 211292 kb
Host smart-62ea6b1b-e343-4f4b-a660-b4383a0df4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169614060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.169614060
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4268587849
Short name T410
Test name
Test status
Simulation time 2878401671 ps
CPU time 38.15 seconds
Started Aug 09 07:15:38 PM PDT 24
Finished Aug 09 07:16:16 PM PDT 24
Peak memory 214652 kb
Host smart-fab7786e-5a04-41d1-b173-ebd92b568407
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268587849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4268587849
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1868883469
Short name T357
Test name
Test status
Simulation time 497078161 ps
CPU time 10.58 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 211996 kb
Host smart-6d3c0fdd-090d-4913-9543-55cb9511b864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868883469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1868883469
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3639105985
Short name T382
Test name
Test status
Simulation time 991627579 ps
CPU time 13.4 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 218000 kb
Host smart-df369e0e-76a8-40cc-be8a-95a654727a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639105985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3639105985
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3437756752
Short name T400
Test name
Test status
Simulation time 1544668234 ps
CPU time 84.31 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:16:56 PM PDT 24
Peak memory 214576 kb
Host smart-0b3b0399-215d-4d6b-85ee-a6d3573bcf6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437756752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3437756752
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.347812901
Short name T334
Test name
Test status
Simulation time 727976633 ps
CPU time 9.2 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:40 PM PDT 24
Peak memory 217196 kb
Host smart-23d1e02f-50c9-4b7c-943c-0f2074b35942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347812901 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.347812901
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3913036546
Short name T336
Test name
Test status
Simulation time 579106783 ps
CPU time 10.09 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 211572 kb
Host smart-d50f7fe0-7ba2-44ee-af8d-1dcce92cec81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913036546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3913036546
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.598849461
Short name T426
Test name
Test status
Simulation time 15845150065 ps
CPU time 63.92 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:16:35 PM PDT 24
Peak memory 215544 kb
Host smart-2965b2b5-aad9-46bb-bf34-69822c4c8c65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598849461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.598849461
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.372361962
Short name T417
Test name
Test status
Simulation time 274340319 ps
CPU time 13.92 seconds
Started Aug 09 07:15:37 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 212900 kb
Host smart-2226cecc-2031-4292-a26e-0b22288ece0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372361962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.372361962
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2494966860
Short name T414
Test name
Test status
Simulation time 257642118 ps
CPU time 15.11 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:16:09 PM PDT 24
Peak memory 219432 kb
Host smart-4f36d1d2-8b13-4bc3-b8db-c3c713bc4111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494966860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2494966860
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.952771207
Short name T122
Test name
Test status
Simulation time 1191582350 ps
CPU time 86.22 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:16:57 PM PDT 24
Peak memory 212960 kb
Host smart-defd7fbc-d7d6-43fa-bb79-a737b903a2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952771207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.952771207
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3024661764
Short name T396
Test name
Test status
Simulation time 562538493 ps
CPU time 11.76 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 218316 kb
Host smart-bbc9c798-50d8-4c81-b71b-76a8138c7aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024661764 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3024661764
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1232082383
Short name T371
Test name
Test status
Simulation time 719046099 ps
CPU time 8.14 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:39 PM PDT 24
Peak memory 211492 kb
Host smart-a3891866-9c97-4dae-9681-5a546ec1cd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232082383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1232082383
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3212028475
Short name T95
Test name
Test status
Simulation time 1018774536 ps
CPU time 44.47 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:16:16 PM PDT 24
Peak memory 214464 kb
Host smart-0770ca22-4d2f-41e3-b9f9-48bb9c91e761
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212028475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3212028475
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4117391538
Short name T361
Test name
Test status
Simulation time 4112935863 ps
CPU time 14.75 seconds
Started Aug 09 07:15:33 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 212212 kb
Host smart-73811d84-73f5-436b-b6dc-34458ffdfd6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117391538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4117391538
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.937293493
Short name T412
Test name
Test status
Simulation time 174368138 ps
CPU time 11.41 seconds
Started Aug 09 07:15:27 PM PDT 24
Finished Aug 09 07:15:39 PM PDT 24
Peak memory 219160 kb
Host smart-0e6034db-e0b8-45b4-a3a5-caa692251f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937293493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.937293493
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2763262891
Short name T383
Test name
Test status
Simulation time 1105517003 ps
CPU time 11.02 seconds
Started Aug 09 07:15:41 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 217952 kb
Host smart-d998885f-5d8e-4b96-8ff0-f5d77da9fcf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763262891 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2763262891
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2322566429
Short name T416
Test name
Test status
Simulation time 1186080030 ps
CPU time 8.27 seconds
Started Aug 09 07:15:42 PM PDT 24
Finished Aug 09 07:15:50 PM PDT 24
Peak memory 211476 kb
Host smart-a2a1cf28-bd72-4243-8299-eaacb9126d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322566429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2322566429
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2722058102
Short name T402
Test name
Test status
Simulation time 261442404 ps
CPU time 9.83 seconds
Started Aug 09 07:15:39 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 212008 kb
Host smart-738b8d3c-47f3-4e8a-9478-625fe0f844ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722058102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2722058102
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1891776824
Short name T364
Test name
Test status
Simulation time 262000986 ps
CPU time 13.03 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 218068 kb
Host smart-0247d404-5f15-44d9-a72a-91ec0af435f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891776824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1891776824
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4149086850
Short name T420
Test name
Test status
Simulation time 5853859480 ps
CPU time 82.6 seconds
Started Aug 09 07:15:27 PM PDT 24
Finished Aug 09 07:16:50 PM PDT 24
Peak memory 219576 kb
Host smart-20ce3e71-4b38-4ed5-b5ff-e0f10fdaa0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149086850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4149086850
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.755281948
Short name T391
Test name
Test status
Simulation time 729369516 ps
CPU time 8.76 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 217332 kb
Host smart-176ebb70-a07b-4de4-b9e2-11d411d9c849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755281948 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.755281948
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1310977929
Short name T100
Test name
Test status
Simulation time 252583669 ps
CPU time 10.04 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 211396 kb
Host smart-776ab373-b0ea-41b4-8c7c-bf3f993139b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310977929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1310977929
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3552808807
Short name T425
Test name
Test status
Simulation time 24734972246 ps
CPU time 62.6 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:16:56 PM PDT 24
Peak memory 214816 kb
Host smart-93443acf-f759-42a0-808e-5b35afa99462
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552808807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3552808807
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3699384649
Short name T415
Test name
Test status
Simulation time 257581644 ps
CPU time 10.11 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:15:40 PM PDT 24
Peak memory 212260 kb
Host smart-58eb52b4-cb7c-421c-919f-c96dae57e5be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699384649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3699384649
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3917491842
Short name T359
Test name
Test status
Simulation time 172604144 ps
CPU time 13.34 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 218284 kb
Host smart-69abe076-dd53-42c6-aff7-6cb3b57ddabb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917491842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3917491842
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1851089086
Short name T399
Test name
Test status
Simulation time 1144761804 ps
CPU time 163.52 seconds
Started Aug 09 07:15:36 PM PDT 24
Finished Aug 09 07:18:20 PM PDT 24
Peak memory 219480 kb
Host smart-2f954da4-c8d5-4465-95a8-48f5ebad61aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851089086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1851089086
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.553495986
Short name T342
Test name
Test status
Simulation time 189788038 ps
CPU time 9.34 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:15:38 PM PDT 24
Peak memory 217880 kb
Host smart-f1647a70-7e29-467f-9912-83ea918f1d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553495986 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.553495986
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3290864597
Short name T96
Test name
Test status
Simulation time 1033648289 ps
CPU time 8.36 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:39 PM PDT 24
Peak memory 211544 kb
Host smart-c4920e27-910c-4309-8d4c-71f7d2bf29c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290864597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3290864597
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1453716551
Short name T429
Test name
Test status
Simulation time 1379707131 ps
CPU time 38.4 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:16:22 PM PDT 24
Peak memory 214880 kb
Host smart-6cd5f524-1ebe-4bf5-9518-c7feb5ce6fe6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453716551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1453716551
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.418897738
Short name T87
Test name
Test status
Simulation time 174308089 ps
CPU time 8.26 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 211896 kb
Host smart-26de66ae-9eb7-4e87-b34b-f9aaace159e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418897738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.418897738
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.203386059
Short name T405
Test name
Test status
Simulation time 340858787 ps
CPU time 12.01 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 217960 kb
Host smart-485556dd-5f6c-470e-9fe1-c0cf01ecfd61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203386059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.203386059
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1948210560
Short name T117
Test name
Test status
Simulation time 1975856062 ps
CPU time 157.16 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 219432 kb
Host smart-cd5a3234-1a45-47df-b47a-275137c6b5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948210560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1948210560
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.874253726
Short name T332
Test name
Test status
Simulation time 347820562 ps
CPU time 10.51 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 214884 kb
Host smart-cd4e3228-ca00-4c92-9f3e-5068b80db8b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874253726 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.874253726
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1368970084
Short name T380
Test name
Test status
Simulation time 414032446 ps
CPU time 8.27 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:15:36 PM PDT 24
Peak memory 211544 kb
Host smart-4a5e077f-a5e3-44bc-811e-ae6e38423094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368970084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1368970084
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.712156135
Short name T427
Test name
Test status
Simulation time 3297625221 ps
CPU time 8.51 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:38 PM PDT 24
Peak memory 211888 kb
Host smart-6d655815-91fd-46c3-9c18-713d9e66d39f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712156135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.712156135
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1989384511
Short name T370
Test name
Test status
Simulation time 332250121 ps
CPU time 11.7 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 218000 kb
Host smart-ea41e48a-50f3-4f91-83ee-941ce6141f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989384511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1989384511
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3663462633
Short name T64
Test name
Test status
Simulation time 4281497046 ps
CPU time 154.89 seconds
Started Aug 09 07:15:33 PM PDT 24
Finished Aug 09 07:18:08 PM PDT 24
Peak memory 219568 kb
Host smart-7faf6bc0-7f3f-4cdf-9c72-daa938e7eb68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663462633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3663462633
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3062244369
Short name T102
Test name
Test status
Simulation time 338574125 ps
CPU time 8.22 seconds
Started Aug 09 07:15:20 PM PDT 24
Finished Aug 09 07:15:29 PM PDT 24
Peak memory 211240 kb
Host smart-fd8f5c88-1cb0-4da1-9158-0234661f1c4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062244369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3062244369
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1300688339
Short name T343
Test name
Test status
Simulation time 1030371949 ps
CPU time 10.54 seconds
Started Aug 09 07:15:16 PM PDT 24
Finished Aug 09 07:15:32 PM PDT 24
Peak memory 211624 kb
Host smart-719f7cd3-e3f4-4d20-ac35-0a770d68d72d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300688339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1300688339
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2998794529
Short name T344
Test name
Test status
Simulation time 264930628 ps
CPU time 13.51 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:15:31 PM PDT 24
Peak memory 212304 kb
Host smart-5520db3f-757f-45fd-8089-0d356d9fe2be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998794529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2998794529
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2371131005
Short name T386
Test name
Test status
Simulation time 185071492 ps
CPU time 8.92 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:21 PM PDT 24
Peak memory 218092 kb
Host smart-0309b618-d61d-4efd-99d2-4dd9a5d5c42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371131005 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2371131005
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3354996226
Short name T112
Test name
Test status
Simulation time 176217284 ps
CPU time 8.46 seconds
Started Aug 09 07:15:11 PM PDT 24
Finished Aug 09 07:15:20 PM PDT 24
Peak memory 211276 kb
Host smart-3d069e51-6a8c-4a13-814f-990efc90f22b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354996226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3354996226
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2760934856
Short name T346
Test name
Test status
Simulation time 260713239 ps
CPU time 9.75 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:22 PM PDT 24
Peak memory 211208 kb
Host smart-93e70645-84dd-4a1c-98b1-6a195a689f2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760934856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2760934856
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3596580524
Short name T337
Test name
Test status
Simulation time 254496962 ps
CPU time 10.02 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:40 PM PDT 24
Peak memory 211440 kb
Host smart-4c05a08a-9c97-493e-84c9-f6f67d194643
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596580524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3596580524
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.668924903
Short name T105
Test name
Test status
Simulation time 1790318221 ps
CPU time 65.47 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:16:24 PM PDT 24
Peak memory 215508 kb
Host smart-08aa5f74-a552-4d7b-b65c-26a9d0fde38f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668924903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.668924903
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2604363801
Short name T69
Test name
Test status
Simulation time 171526272 ps
CPU time 8.4 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:21 PM PDT 24
Peak memory 212076 kb
Host smart-71c1017c-289a-4052-82af-bd05d9000f52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604363801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2604363801
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4191094726
Short name T347
Test name
Test status
Simulation time 167356794 ps
CPU time 11.27 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 217944 kb
Host smart-c6c33631-dc7f-4fd9-9463-c85bf067e1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191094726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4191094726
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3256813010
Short name T363
Test name
Test status
Simulation time 341958061 ps
CPU time 155.79 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 214956 kb
Host smart-5d98bc1a-224b-4084-a397-ed34d73a691f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256813010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3256813010
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2742418124
Short name T354
Test name
Test status
Simulation time 251171536 ps
CPU time 10.2 seconds
Started Aug 09 07:15:09 PM PDT 24
Finished Aug 09 07:15:20 PM PDT 24
Peak memory 211268 kb
Host smart-67ceeeae-e45e-431c-a444-edd0ce44afd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742418124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2742418124
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1205011003
Short name T348
Test name
Test status
Simulation time 399303516 ps
CPU time 9.91 seconds
Started Aug 09 07:15:08 PM PDT 24
Finished Aug 09 07:15:18 PM PDT 24
Peak memory 211292 kb
Host smart-de6c17eb-e3da-4fd8-901f-7120dd8526e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205011003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1205011003
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2690075695
Short name T98
Test name
Test status
Simulation time 178883713 ps
CPU time 15.36 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:33 PM PDT 24
Peak memory 212144 kb
Host smart-bf5b5045-1d48-405a-b7cf-5689e6834d53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690075695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2690075695
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2090800976
Short name T338
Test name
Test status
Simulation time 260744314 ps
CPU time 10.21 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 215312 kb
Host smart-3e255289-556e-472a-8a01-71baaf4832a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090800976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2090800976
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3678281811
Short name T362
Test name
Test status
Simulation time 173684600 ps
CPU time 8.32 seconds
Started Aug 09 07:15:16 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 211548 kb
Host smart-8ea19f9a-e0eb-4768-b0e5-cae1277be91f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678281811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3678281811
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1986863857
Short name T404
Test name
Test status
Simulation time 1030353937 ps
CPU time 9.61 seconds
Started Aug 09 07:15:15 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 211252 kb
Host smart-95294c63-15f3-43f0-9e23-46e8ea204acc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986863857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1986863857
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2562172277
Short name T398
Test name
Test status
Simulation time 1032136211 ps
CPU time 10.14 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:22 PM PDT 24
Peak memory 211220 kb
Host smart-19db0bb5-7a1e-41de-9b4c-e7b3cf697a31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562172277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2562172277
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.455054813
Short name T421
Test name
Test status
Simulation time 14467827464 ps
CPU time 45.23 seconds
Started Aug 09 07:15:13 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 214684 kb
Host smart-f468f458-e38b-409d-a248-e472e4e19724
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455054813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.455054813
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2818340668
Short name T110
Test name
Test status
Simulation time 707256399 ps
CPU time 10.02 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 212244 kb
Host smart-7df7680a-bd6f-432d-a0e1-2f608056c1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818340668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2818340668
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.39907775
Short name T345
Test name
Test status
Simulation time 511312124 ps
CPU time 12.77 seconds
Started Aug 09 07:15:22 PM PDT 24
Finished Aug 09 07:15:34 PM PDT 24
Peak memory 218008 kb
Host smart-9b3bfe43-1724-4b54-ba77-3274d7ebc5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39907775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.39907775
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1210870544
Short name T63
Test name
Test status
Simulation time 1275377331 ps
CPU time 86.1 seconds
Started Aug 09 07:15:16 PM PDT 24
Finished Aug 09 07:16:42 PM PDT 24
Peak memory 213428 kb
Host smart-1a4b2064-5cb6-444d-97e5-4765bbbb9ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210870544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1210870544
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3703368291
Short name T409
Test name
Test status
Simulation time 339794067 ps
CPU time 8.19 seconds
Started Aug 09 07:15:33 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 211312 kb
Host smart-c5fe5dd1-5613-4c92-9865-c428e47944df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703368291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3703368291
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1302395393
Short name T406
Test name
Test status
Simulation time 514499264 ps
CPU time 10.19 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:40 PM PDT 24
Peak memory 211312 kb
Host smart-e2f9a9ee-ee29-43a8-81cb-3fccb21ff7dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302395393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1302395393
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1818410617
Short name T97
Test name
Test status
Simulation time 265654514 ps
CPU time 17.07 seconds
Started Aug 09 07:15:35 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 211632 kb
Host smart-e129fd1c-a1b6-4b8c-806c-1ed335c4d3a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818410617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1818410617
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.154877022
Short name T390
Test name
Test status
Simulation time 522086083 ps
CPU time 11.24 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 218428 kb
Host smart-8d781f7d-b6c2-4921-b3ab-751bb79d97d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154877022 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.154877022
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2512717938
Short name T365
Test name
Test status
Simulation time 1908697681 ps
CPU time 10.12 seconds
Started Aug 09 07:15:27 PM PDT 24
Finished Aug 09 07:15:38 PM PDT 24
Peak memory 211668 kb
Host smart-d3eb5ed2-9ae9-4937-8e9e-5535bee2503e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512717938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2512717938
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3993218503
Short name T394
Test name
Test status
Simulation time 922087342 ps
CPU time 8.16 seconds
Started Aug 09 07:15:19 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 211228 kb
Host smart-7db7a5dd-f1d6-4489-9fd7-fac321cb0a5f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993218503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3993218503
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4201786868
Short name T381
Test name
Test status
Simulation time 496811744 ps
CPU time 9.56 seconds
Started Aug 09 07:15:20 PM PDT 24
Finished Aug 09 07:15:29 PM PDT 24
Peak memory 211256 kb
Host smart-f433e809-74b1-409e-b4e5-13678a3ad7f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201786868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4201786868
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1791708623
Short name T401
Test name
Test status
Simulation time 1024256002 ps
CPU time 46.31 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 214472 kb
Host smart-50b99a63-76cd-41a2-a79e-77d0982ab4be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791708623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1791708623
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.680637383
Short name T378
Test name
Test status
Simulation time 828363875 ps
CPU time 8.23 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:27 PM PDT 24
Peak memory 211996 kb
Host smart-d3101504-43b9-4bed-a25a-bcdd026d2d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680637383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.680637383
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1757493350
Short name T424
Test name
Test status
Simulation time 750967246 ps
CPU time 14.5 seconds
Started Aug 09 07:15:10 PM PDT 24
Finished Aug 09 07:15:25 PM PDT 24
Peak memory 218332 kb
Host smart-f5cf5c9c-0f83-41eb-9ee9-4a34f3a0fcc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757493350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1757493350
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.584765937
Short name T368
Test name
Test status
Simulation time 1075996843 ps
CPU time 10.53 seconds
Started Aug 09 07:15:34 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 217384 kb
Host smart-d71dfcef-2940-4464-9b98-85f9aa1c90ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584765937 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.584765937
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2004012301
Short name T403
Test name
Test status
Simulation time 520712157 ps
CPU time 9.77 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:40 PM PDT 24
Peak memory 211288 kb
Host smart-3a2d51d4-ccc2-4df5-bff2-6fee8f9d088c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004012301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2004012301
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.248514455
Short name T407
Test name
Test status
Simulation time 4122731003 ps
CPU time 56.43 seconds
Started Aug 09 07:15:29 PM PDT 24
Finished Aug 09 07:16:26 PM PDT 24
Peak memory 214896 kb
Host smart-f6545677-2f04-4097-89f8-e17694583e96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248514455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.248514455
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1838022320
Short name T85
Test name
Test status
Simulation time 1300638393 ps
CPU time 10.18 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:15:38 PM PDT 24
Peak memory 211624 kb
Host smart-6f8de671-f405-4d43-89d2-d8ce47b4082e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838022320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1838022320
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3818955504
Short name T351
Test name
Test status
Simulation time 1077688870 ps
CPU time 13.12 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 217804 kb
Host smart-de68b005-c7fd-4085-b317-f5d738436a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818955504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3818955504
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.130174956
Short name T123
Test name
Test status
Simulation time 496658313 ps
CPU time 149.23 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:19:05 PM PDT 24
Peak memory 214468 kb
Host smart-fde4ea12-7b47-4325-8b80-2fd006bacb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130174956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.130174956
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3694625563
Short name T387
Test name
Test status
Simulation time 275036776 ps
CPU time 10.93 seconds
Started Aug 09 07:15:23 PM PDT 24
Finished Aug 09 07:15:34 PM PDT 24
Peak memory 218084 kb
Host smart-08762c14-bb88-4aad-a89e-f80c2fecc8b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694625563 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3694625563
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1776192721
Short name T388
Test name
Test status
Simulation time 1182419342 ps
CPU time 9.88 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:15:38 PM PDT 24
Peak memory 210996 kb
Host smart-ed9de133-16d8-4b17-9465-1b75b860f8b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776192721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1776192721
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.117838354
Short name T109
Test name
Test status
Simulation time 10844632696 ps
CPU time 67.04 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:16:25 PM PDT 24
Peak memory 216592 kb
Host smart-626b19f5-c474-4c1e-b68d-15577e31b21d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117838354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.117838354
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1293418499
Short name T374
Test name
Test status
Simulation time 496022687 ps
CPU time 9.85 seconds
Started Aug 09 07:15:32 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 211732 kb
Host smart-62a44651-9cfe-4a51-af92-c6040c9806a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293418499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1293418499
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3951352845
Short name T331
Test name
Test status
Simulation time 1034369258 ps
CPU time 14.91 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 218408 kb
Host smart-746f0335-7716-468d-99dc-39bc12159726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951352845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3951352845
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2260472506
Short name T369
Test name
Test status
Simulation time 1445157678 ps
CPU time 156.01 seconds
Started Aug 09 07:15:28 PM PDT 24
Finished Aug 09 07:18:04 PM PDT 24
Peak memory 214904 kb
Host smart-12b6296c-78cb-4440-a06f-d0e9716bdd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260472506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2260472506
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.803696237
Short name T360
Test name
Test status
Simulation time 1207576810 ps
CPU time 8.84 seconds
Started Aug 09 07:15:12 PM PDT 24
Finished Aug 09 07:15:21 PM PDT 24
Peak memory 217324 kb
Host smart-31b89b73-6dec-46c2-95e6-95b7797c3403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803696237 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.803696237
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2369309934
Short name T81
Test name
Test status
Simulation time 688504687 ps
CPU time 8.26 seconds
Started Aug 09 07:15:20 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 211876 kb
Host smart-cee96820-9415-4122-84f6-fea82ed726d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369309934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2369309934
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3494143173
Short name T104
Test name
Test status
Simulation time 2599537010 ps
CPU time 43.74 seconds
Started Aug 09 07:15:31 PM PDT 24
Finished Aug 09 07:16:15 PM PDT 24
Peak memory 214524 kb
Host smart-5755a5a4-4b47-4fd9-822a-a55a8df3453b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494143173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3494143173
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1936787064
Short name T70
Test name
Test status
Simulation time 220267378 ps
CPU time 7.93 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:16:42 PM PDT 24
Peak memory 211964 kb
Host smart-733648ee-aa49-4bcd-97e2-41ac1a5d790b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936787064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1936787064
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4290939712
Short name T376
Test name
Test status
Simulation time 249767186 ps
CPU time 12.86 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:16:38 PM PDT 24
Peak memory 215748 kb
Host smart-bff7b51b-db3e-4b2c-911c-104483cb7ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290939712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4290939712
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.339765
Short name T423
Test name
Test status
Simulation time 1021878257 ps
CPU time 81.78 seconds
Started Aug 09 07:15:22 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 214268 kb
Host smart-65b7c98e-c50d-44a6-bb3f-ebfe65345b24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_e
rr.339765
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3077742952
Short name T373
Test name
Test status
Simulation time 527320078 ps
CPU time 10.36 seconds
Started Aug 09 07:15:20 PM PDT 24
Finished Aug 09 07:15:30 PM PDT 24
Peak memory 217836 kb
Host smart-3596062c-69a1-4c0b-ae53-dee82e78f680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077742952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3077742952
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1488229731
Short name T379
Test name
Test status
Simulation time 689745239 ps
CPU time 8.16 seconds
Started Aug 09 07:15:18 PM PDT 24
Finished Aug 09 07:15:26 PM PDT 24
Peak memory 211696 kb
Host smart-56176569-6786-451e-a1a4-e3059d734492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488229731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1488229731
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4181855959
Short name T411
Test name
Test status
Simulation time 1245621211 ps
CPU time 42.15 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:17:07 PM PDT 24
Peak memory 212468 kb
Host smart-46ded57a-8b66-452a-9dcd-f8c6cf864c51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181855959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4181855959
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.17407576
Short name T113
Test name
Test status
Simulation time 539307779 ps
CPU time 13.72 seconds
Started Aug 09 07:15:30 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 213220 kb
Host smart-3138f2f1-1d8a-489a-af71-65b98bf88083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17407576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.17407576
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3676499980
Short name T352
Test name
Test status
Simulation time 1033351365 ps
CPU time 10.94 seconds
Started Aug 09 07:15:37 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 217968 kb
Host smart-e242b0b9-bda4-458b-9f2f-06e550bbdc10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676499980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3676499980
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4118611470
Short name T120
Test name
Test status
Simulation time 1109795861 ps
CPU time 83.28 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:16:40 PM PDT 24
Peak memory 215180 kb
Host smart-0d57500f-7608-4675-a622-6cf93e99b8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118611470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4118611470
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.988690260
Short name T335
Test name
Test status
Simulation time 282989665 ps
CPU time 10.41 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:46 PM PDT 24
Peak memory 217776 kb
Host smart-2df058d7-6519-4be9-b5b9-2754ccd3ca90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988690260 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.988690260
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.258349401
Short name T82
Test name
Test status
Simulation time 251659798 ps
CPU time 9.51 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 211064 kb
Host smart-4bb68113-4e47-4486-bce1-3125a3ae8833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258349401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.258349401
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1993950359
Short name T99
Test name
Test status
Simulation time 724111220 ps
CPU time 36.87 seconds
Started Aug 09 07:15:19 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 214720 kb
Host smart-b223baf6-ca4e-498c-bfda-80f753a6e7b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993950359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1993950359
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.564308989
Short name T430
Test name
Test status
Simulation time 186062535 ps
CPU time 11.73 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:16:45 PM PDT 24
Peak memory 212004 kb
Host smart-af917682-f262-463a-93f7-d8ceacbd4513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564308989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.564308989
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2734955839
Short name T367
Test name
Test status
Simulation time 175067761 ps
CPU time 11.16 seconds
Started Aug 09 07:15:17 PM PDT 24
Finished Aug 09 07:15:28 PM PDT 24
Peak memory 217820 kb
Host smart-761992dd-bd42-46be-8b27-009c02b26561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734955839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2734955839
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1882994373
Short name T121
Test name
Test status
Simulation time 346717298 ps
CPU time 83.7 seconds
Started Aug 09 07:15:19 PM PDT 24
Finished Aug 09 07:16:43 PM PDT 24
Peak memory 219500 kb
Host smart-13c2aacf-7f45-4358-885a-c1d58cc4bb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882994373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1882994373
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2999861469
Short name T203
Test name
Test status
Simulation time 308120667 ps
CPU time 9.95 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:49 PM PDT 24
Peak memory 219160 kb
Host smart-cc5b83c2-5f5e-43cd-9135-a434f2a18a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999861469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2999861469
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2277228915
Short name T205
Test name
Test status
Simulation time 415617724 ps
CPU time 19.24 seconds
Started Aug 09 05:46:32 PM PDT 24
Finished Aug 09 05:46:51 PM PDT 24
Peak memory 220036 kb
Host smart-e5587414-d877-45d0-a8e7-43453e3e9f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277228915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2277228915
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3767341941
Short name T252
Test name
Test status
Simulation time 526943977 ps
CPU time 11.79 seconds
Started Aug 09 05:46:31 PM PDT 24
Finished Aug 09 05:46:43 PM PDT 24
Peak memory 220060 kb
Host smart-c543f89b-7ab4-41c6-a749-a9810ee3b1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767341941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3767341941
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.965539698
Short name T319
Test name
Test status
Simulation time 565225862 ps
CPU time 12.54 seconds
Started Aug 09 05:46:33 PM PDT 24
Finished Aug 09 05:46:46 PM PDT 24
Peak memory 219972 kb
Host smart-7661d62f-2c33-4236-a129-b6f49a356653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965539698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.965539698
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1438012184
Short name T225
Test name
Test status
Simulation time 542549747 ps
CPU time 33.66 seconds
Started Aug 09 05:46:33 PM PDT 24
Finished Aug 09 05:47:07 PM PDT 24
Peak memory 220000 kb
Host smart-33521252-f0e1-49cb-b387-c875c97d4bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438012184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1438012184
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1981711181
Short name T207
Test name
Test status
Simulation time 718939767 ps
CPU time 8.51 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:48 PM PDT 24
Peak memory 219004 kb
Host smart-1d0f57aa-c7fa-475b-b5d7-58e5cda937f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981711181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1981711181
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2912145611
Short name T38
Test name
Test status
Simulation time 4881544299 ps
CPU time 249.89 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:50:49 PM PDT 24
Peak memory 242864 kb
Host smart-8091d966-eec2-44da-a471-2c647a2fa4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912145611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2912145611
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2013299799
Short name T239
Test name
Test status
Simulation time 523702469 ps
CPU time 22.55 seconds
Started Aug 09 05:46:38 PM PDT 24
Finished Aug 09 05:47:01 PM PDT 24
Peak memory 219980 kb
Host smart-de99d307-de63-4ced-b054-671fa6aefcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013299799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2013299799
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3006772031
Short name T59
Test name
Test status
Simulation time 494930225 ps
CPU time 11.8 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:51 PM PDT 24
Peak memory 220080 kb
Host smart-6c34b2e7-c3cf-4179-a8ae-e7293ecebedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006772031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3006772031
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2057480131
Short name T28
Test name
Test status
Simulation time 1938915993 ps
CPU time 224.1 seconds
Started Aug 09 05:46:38 PM PDT 24
Finished Aug 09 05:50:22 PM PDT 24
Peak memory 239684 kb
Host smart-60142eac-8073-48e9-997e-8e60deb5323b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057480131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2057480131
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2665042318
Short name T66
Test name
Test status
Simulation time 1130245820 ps
CPU time 11.97 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:51 PM PDT 24
Peak memory 219904 kb
Host smart-72a6cb34-497f-4133-af1a-91fa4d6c35ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665042318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2665042318
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1935255534
Short name T224
Test name
Test status
Simulation time 6568593135 ps
CPU time 15.21 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:47:34 PM PDT 24
Peak memory 219544 kb
Host smart-e6682d80-13eb-405e-b844-785b214b7056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935255534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1935255534
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1157561345
Short name T305
Test name
Test status
Simulation time 333073006 ps
CPU time 19.35 seconds
Started Aug 09 05:47:17 PM PDT 24
Finished Aug 09 05:47:37 PM PDT 24
Peak memory 220012 kb
Host smart-dd2956a5-1169-4999-9997-ffa30d1c779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157561345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1157561345
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1507519512
Short name T136
Test name
Test status
Simulation time 1073892907 ps
CPU time 12.36 seconds
Started Aug 09 05:47:17 PM PDT 24
Finished Aug 09 05:47:29 PM PDT 24
Peak memory 220296 kb
Host smart-75be8edb-4fc2-497d-905d-d247ef0209b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507519512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1507519512
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.357810583
Short name T234
Test name
Test status
Simulation time 314500885 ps
CPU time 24.26 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:47:43 PM PDT 24
Peak memory 219928 kb
Host smart-c25749f2-4be1-42df-beb8-1d0539ae6091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357810583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.357810583
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.982507574
Short name T286
Test name
Test status
Simulation time 201511903 ps
CPU time 8.32 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 05:47:31 PM PDT 24
Peak memory 218824 kb
Host smart-e2f50d7b-3333-42cf-b235-57ae50a390de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982507574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.982507574
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1092000946
Short name T184
Test name
Test status
Simulation time 1858204045 ps
CPU time 128.45 seconds
Started Aug 09 05:47:17 PM PDT 24
Finished Aug 09 05:49:25 PM PDT 24
Peak memory 245624 kb
Host smart-42ecce46-530b-4623-8b54-a18e26e0887c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092000946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1092000946
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.257466522
Short name T200
Test name
Test status
Simulation time 272422618 ps
CPU time 12.02 seconds
Started Aug 09 05:47:20 PM PDT 24
Finished Aug 09 05:47:32 PM PDT 24
Peak memory 219944 kb
Host smart-fe90ebfd-c765-4789-9b5f-ba0e6915a5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257466522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.257466522
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1210305290
Short name T296
Test name
Test status
Simulation time 200345683 ps
CPU time 14.34 seconds
Started Aug 09 05:47:19 PM PDT 24
Finished Aug 09 05:47:33 PM PDT 24
Peak memory 219760 kb
Host smart-3ada8372-8785-436e-9886-52f3eae16244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210305290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1210305290
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3712488740
Short name T285
Test name
Test status
Simulation time 201005373809 ps
CPU time 1033.48 seconds
Started Aug 09 05:47:19 PM PDT 24
Finished Aug 09 06:04:33 PM PDT 24
Peak memory 236520 kb
Host smart-55285295-23ad-4d92-8615-db38d53b6047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712488740 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3712488740
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3963733203
Short name T322
Test name
Test status
Simulation time 253919587 ps
CPU time 10.17 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 05:47:33 PM PDT 24
Peak memory 219048 kb
Host smart-fb871f27-53f8-4c0b-a385-4af35b252d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963733203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3963733203
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2762130722
Short name T161
Test name
Test status
Simulation time 4864170741 ps
CPU time 313.7 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 05:52:37 PM PDT 24
Peak memory 236360 kb
Host smart-774c10cd-acc3-451f-8706-c735a3301907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762130722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2762130722
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1685561895
Short name T219
Test name
Test status
Simulation time 498255185 ps
CPU time 22.71 seconds
Started Aug 09 05:47:24 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 219996 kb
Host smart-2e2ad3f1-b916-43bd-9040-ab5fc1f57495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685561895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1685561895
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4064117505
Short name T222
Test name
Test status
Simulation time 1720218222 ps
CPU time 10.32 seconds
Started Aug 09 05:47:24 PM PDT 24
Finished Aug 09 05:47:34 PM PDT 24
Peak memory 220056 kb
Host smart-c9184b45-6944-4237-af13-f1bacb7d7557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064117505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4064117505
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2536297969
Short name T297
Test name
Test status
Simulation time 1076917304 ps
CPU time 29.41 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 05:47:53 PM PDT 24
Peak memory 219928 kb
Host smart-ee5228be-2707-4491-a02b-1235845608c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536297969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2536297969
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1274903231
Short name T50
Test name
Test status
Simulation time 24053541221 ps
CPU time 7116.14 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 07:46:00 PM PDT 24
Peak memory 236512 kb
Host smart-3b5a3dfa-ddfc-4c4b-9840-b35fd87a7338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274903231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1274903231
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1610178916
Short name T172
Test name
Test status
Simulation time 250296163 ps
CPU time 10.13 seconds
Started Aug 09 05:47:27 PM PDT 24
Finished Aug 09 05:47:37 PM PDT 24
Peak memory 219040 kb
Host smart-127493e2-158c-414e-b2d4-7a9c97745538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610178916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1610178916
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2618952414
Short name T144
Test name
Test status
Simulation time 2555203305 ps
CPU time 117.2 seconds
Started Aug 09 05:47:29 PM PDT 24
Finished Aug 09 05:49:27 PM PDT 24
Peak memory 240552 kb
Host smart-861fefaf-08a2-4879-a6f0-6f2a08be6412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618952414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2618952414
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3616341059
Short name T304
Test name
Test status
Simulation time 515978233 ps
CPU time 23.07 seconds
Started Aug 09 05:47:28 PM PDT 24
Finished Aug 09 05:47:52 PM PDT 24
Peak memory 220004 kb
Host smart-d6ad7411-87d8-42d8-bb42-5c4479b51974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616341059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3616341059
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3461127725
Short name T280
Test name
Test status
Simulation time 1023801222 ps
CPU time 11.87 seconds
Started Aug 09 05:47:24 PM PDT 24
Finished Aug 09 05:47:36 PM PDT 24
Peak memory 220060 kb
Host smart-c30a4736-5d0e-4e0e-a788-02935281d65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461127725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3461127725
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2020863089
Short name T68
Test name
Test status
Simulation time 302084067 ps
CPU time 12.78 seconds
Started Aug 09 05:47:23 PM PDT 24
Finished Aug 09 05:47:36 PM PDT 24
Peak memory 219960 kb
Host smart-140a8c1d-0b5a-4369-af49-fb444bf0e5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020863089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2020863089
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1918384437
Short name T21
Test name
Test status
Simulation time 253690452 ps
CPU time 10.24 seconds
Started Aug 09 05:47:31 PM PDT 24
Finished Aug 09 05:47:41 PM PDT 24
Peak memory 219068 kb
Host smart-52a58637-53bd-449d-86f9-9ae7eb70ba7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918384437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1918384437
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2438845142
Short name T265
Test name
Test status
Simulation time 25719409706 ps
CPU time 323.67 seconds
Started Aug 09 05:47:30 PM PDT 24
Finished Aug 09 05:52:54 PM PDT 24
Peak memory 236664 kb
Host smart-ad693bbc-75d0-4734-8a2f-9f82268a3e7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438845142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2438845142
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2427851674
Short name T34
Test name
Test status
Simulation time 1011334517 ps
CPU time 22.5 seconds
Started Aug 09 05:47:28 PM PDT 24
Finished Aug 09 05:47:50 PM PDT 24
Peak memory 220048 kb
Host smart-b886562e-4115-4d34-a73c-d2a9baf69901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427851674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2427851674
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.233735888
Short name T245
Test name
Test status
Simulation time 1029215996 ps
CPU time 12.26 seconds
Started Aug 09 05:47:30 PM PDT 24
Finished Aug 09 05:47:42 PM PDT 24
Peak memory 220104 kb
Host smart-244b850f-a549-4a1a-bcba-0a315c44faac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233735888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.233735888
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1598043293
Short name T243
Test name
Test status
Simulation time 3538151614 ps
CPU time 41.17 seconds
Started Aug 09 05:47:29 PM PDT 24
Finished Aug 09 05:48:10 PM PDT 24
Peak memory 220180 kb
Host smart-733258e4-52ea-48e1-a6b0-167e1d57bc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598043293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1598043293
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1812283868
Short name T178
Test name
Test status
Simulation time 688554108 ps
CPU time 8.43 seconds
Started Aug 09 05:47:31 PM PDT 24
Finished Aug 09 05:47:39 PM PDT 24
Peak memory 219108 kb
Host smart-79f7dfe0-e3a2-4dff-bbf1-942817edef8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812283868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1812283868
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1711312216
Short name T210
Test name
Test status
Simulation time 3974184970 ps
CPU time 211.02 seconds
Started Aug 09 05:47:29 PM PDT 24
Finished Aug 09 05:51:00 PM PDT 24
Peak memory 238000 kb
Host smart-4fa3267c-2d16-438d-9534-8e4776f81750
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711312216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1711312216
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.840602225
Short name T155
Test name
Test status
Simulation time 1073587848 ps
CPU time 11.88 seconds
Started Aug 09 05:47:31 PM PDT 24
Finished Aug 09 05:47:42 PM PDT 24
Peak memory 219988 kb
Host smart-830244ae-bacb-4b50-ac78-975f6d4bfe46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840602225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.840602225
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1272531549
Short name T5
Test name
Test status
Simulation time 2182222144 ps
CPU time 18.05 seconds
Started Aug 09 05:47:28 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 220100 kb
Host smart-e8b1adef-b462-4bc5-8bb4-300c79cbff29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272531549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1272531549
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3911856813
Short name T175
Test name
Test status
Simulation time 332734638 ps
CPU time 8.22 seconds
Started Aug 09 05:47:38 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 219124 kb
Host smart-cad8f332-7eb7-4bd6-b294-55f05c3e5080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911856813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3911856813
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4171103622
Short name T18
Test name
Test status
Simulation time 3770426362 ps
CPU time 290.22 seconds
Started Aug 09 05:47:36 PM PDT 24
Finished Aug 09 05:52:27 PM PDT 24
Peak memory 239644 kb
Host smart-7b8c40d4-5f35-4acd-876f-98dccd65501c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171103622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4171103622
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1903102000
Short name T152
Test name
Test status
Simulation time 2997242583 ps
CPU time 19.89 seconds
Started Aug 09 05:47:37 PM PDT 24
Finished Aug 09 05:47:57 PM PDT 24
Peak memory 220196 kb
Host smart-012d917d-12d9-4e82-be0b-ca21e541c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903102000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1903102000
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2811162681
Short name T130
Test name
Test status
Simulation time 1164569858 ps
CPU time 11.81 seconds
Started Aug 09 05:47:38 PM PDT 24
Finished Aug 09 05:47:50 PM PDT 24
Peak memory 220076 kb
Host smart-33413cdb-c36b-41a9-a2e5-8a1fdab0c0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811162681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2811162681
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4207546005
Short name T261
Test name
Test status
Simulation time 5218396000 ps
CPU time 27.94 seconds
Started Aug 09 05:47:35 PM PDT 24
Finished Aug 09 05:48:04 PM PDT 24
Peak memory 220112 kb
Host smart-2c3a8aa5-2fb1-41eb-a233-9937960488b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207546005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4207546005
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2444636096
Short name T153
Test name
Test status
Simulation time 249730258 ps
CPU time 10.01 seconds
Started Aug 09 05:47:35 PM PDT 24
Finished Aug 09 05:47:46 PM PDT 24
Peak memory 219188 kb
Host smart-1d4ec8f7-b283-4569-9961-76e21162fcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444636096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2444636096
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1839235337
Short name T255
Test name
Test status
Simulation time 6590884959 ps
CPU time 198.39 seconds
Started Aug 09 05:47:39 PM PDT 24
Finished Aug 09 05:50:57 PM PDT 24
Peak memory 238328 kb
Host smart-93b0859e-25ec-4c63-b97a-6279369ebd30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839235337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1839235337
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2128729794
Short name T126
Test name
Test status
Simulation time 4017902707 ps
CPU time 32.86 seconds
Started Aug 09 05:47:37 PM PDT 24
Finished Aug 09 05:48:09 PM PDT 24
Peak memory 219740 kb
Host smart-601a42da-699c-4306-bc3d-ae31d5cb643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128729794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2128729794
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.289924039
Short name T311
Test name
Test status
Simulation time 696290423 ps
CPU time 10.37 seconds
Started Aug 09 05:47:36 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 220024 kb
Host smart-396611ba-a874-4418-8b6e-997ddbb54e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289924039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.289924039
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1372959340
Short name T35
Test name
Test status
Simulation time 423108672 ps
CPU time 11.16 seconds
Started Aug 09 05:47:37 PM PDT 24
Finished Aug 09 05:47:49 PM PDT 24
Peak memory 220036 kb
Host smart-84622e7b-9e81-4eb3-8dc9-1df092c4270e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372959340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1372959340
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.617607961
Short name T159
Test name
Test status
Simulation time 346265115 ps
CPU time 8.45 seconds
Started Aug 09 05:47:43 PM PDT 24
Finished Aug 09 05:47:52 PM PDT 24
Peak memory 219148 kb
Host smart-6e73b357-653f-417a-a376-4376ecace1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617607961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.617607961
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2018402215
Short name T214
Test name
Test status
Simulation time 12212028848 ps
CPU time 208.36 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:51:17 PM PDT 24
Peak memory 220288 kb
Host smart-3298fdf9-0a66-4bc8-9eb0-a4f5bd5a514f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018402215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2018402215
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.237213802
Short name T77
Test name
Test status
Simulation time 2146566207 ps
CPU time 22.96 seconds
Started Aug 09 05:47:42 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 220088 kb
Host smart-6d6d43a4-28ac-47a7-9797-fb95b2cdfc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237213802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.237213802
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2433408610
Short name T74
Test name
Test status
Simulation time 180343914 ps
CPU time 10.26 seconds
Started Aug 09 05:47:35 PM PDT 24
Finished Aug 09 05:47:46 PM PDT 24
Peak memory 219960 kb
Host smart-d0e0d6c0-53bf-4033-8b1b-f960cef32355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433408610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2433408610
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3505628314
Short name T7
Test name
Test status
Simulation time 419603932 ps
CPU time 15.08 seconds
Started Aug 09 05:47:37 PM PDT 24
Finished Aug 09 05:47:52 PM PDT 24
Peak memory 220032 kb
Host smart-4afa3cab-c5ba-48bf-900d-7887c53ea982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505628314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3505628314
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3373738691
Short name T192
Test name
Test status
Simulation time 2381268902 ps
CPU time 14.92 seconds
Started Aug 09 05:47:45 PM PDT 24
Finished Aug 09 05:48:00 PM PDT 24
Peak memory 219168 kb
Host smart-8a7b88ca-3dc3-4275-a1a5-ab5e6fc3e73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373738691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3373738691
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2177415425
Short name T233
Test name
Test status
Simulation time 24298788594 ps
CPU time 354.32 seconds
Started Aug 09 05:47:50 PM PDT 24
Finished Aug 09 05:53:44 PM PDT 24
Peak memory 243096 kb
Host smart-3ff34525-263f-4d14-b226-c77ff7b28366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177415425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2177415425
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4246835257
Short name T129
Test name
Test status
Simulation time 9895411586 ps
CPU time 22.33 seconds
Started Aug 09 05:47:42 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 220180 kb
Host smart-d280b1ce-0999-4100-8a7a-9f66c5d03418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246835257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4246835257
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2283742782
Short name T174
Test name
Test status
Simulation time 3420689995 ps
CPU time 17.01 seconds
Started Aug 09 05:47:45 PM PDT 24
Finished Aug 09 05:48:02 PM PDT 24
Peak memory 219804 kb
Host smart-c0a15e52-633c-4d5a-9ce6-968bebf5030c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283742782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2283742782
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.965555399
Short name T181
Test name
Test status
Simulation time 275592610 ps
CPU time 16.4 seconds
Started Aug 09 05:47:43 PM PDT 24
Finished Aug 09 05:47:59 PM PDT 24
Peak memory 220028 kb
Host smart-8f626ead-e231-4861-956a-2ab09641d2ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965555399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.965555399
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.30214125
Short name T271
Test name
Test status
Simulation time 4076119159 ps
CPU time 15.2 seconds
Started Aug 09 05:46:46 PM PDT 24
Finished Aug 09 05:47:02 PM PDT 24
Peak memory 219184 kb
Host smart-23d6aed3-2130-4b71-a294-da18eba250f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.30214125
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2464563782
Short name T268
Test name
Test status
Simulation time 4048302883 ps
CPU time 266.5 seconds
Started Aug 09 05:46:44 PM PDT 24
Finished Aug 09 05:51:11 PM PDT 24
Peak memory 239680 kb
Host smart-91cb148c-1c3a-4998-9310-98a207f3dc35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464563782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2464563782
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.338528529
Short name T142
Test name
Test status
Simulation time 346209986 ps
CPU time 19.54 seconds
Started Aug 09 05:46:45 PM PDT 24
Finished Aug 09 05:47:05 PM PDT 24
Peak memory 220092 kb
Host smart-b8b882e4-acac-463d-9e2a-7e6a055f6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338528529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.338528529
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.716384848
Short name T131
Test name
Test status
Simulation time 1095051796 ps
CPU time 10.42 seconds
Started Aug 09 05:46:45 PM PDT 24
Finished Aug 09 05:46:55 PM PDT 24
Peak memory 220108 kb
Host smart-7bcffae6-887f-4301-880c-2089b4e32c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716384848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.716384848
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2638045742
Short name T27
Test name
Test status
Simulation time 236595562 ps
CPU time 115.69 seconds
Started Aug 09 05:46:45 PM PDT 24
Finished Aug 09 05:48:41 PM PDT 24
Peak memory 239068 kb
Host smart-b351357e-e954-41e5-8764-951ed3c5f9d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638045742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2638045742
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.585820142
Short name T264
Test name
Test status
Simulation time 179384549 ps
CPU time 10.51 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:49 PM PDT 24
Peak memory 220060 kb
Host smart-305a2893-0972-4cc9-803a-c0173cab1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585820142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.585820142
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.283233227
Short name T92
Test name
Test status
Simulation time 216760784 ps
CPU time 14.97 seconds
Started Aug 09 05:46:39 PM PDT 24
Finished Aug 09 05:46:54 PM PDT 24
Peak memory 219984 kb
Host smart-90038f3b-da10-40b8-918b-dbeea93dc359
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283233227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.283233227
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4102543781
Short name T318
Test name
Test status
Simulation time 259196688 ps
CPU time 9.88 seconds
Started Aug 09 05:47:42 PM PDT 24
Finished Aug 09 05:47:52 PM PDT 24
Peak memory 218944 kb
Host smart-7ad0812e-ba90-4bb6-a29f-e89adf3c5bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102543781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4102543781
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1852214094
Short name T193
Test name
Test status
Simulation time 59062501218 ps
CPU time 285.89 seconds
Started Aug 09 05:47:44 PM PDT 24
Finished Aug 09 05:52:30 PM PDT 24
Peak memory 239572 kb
Host smart-4e4225b9-20bc-4da1-b6d2-c021be2af1f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852214094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1852214094
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3074745066
Short name T250
Test name
Test status
Simulation time 1975267487 ps
CPU time 22.94 seconds
Started Aug 09 05:47:42 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 219976 kb
Host smart-0e5c686c-ad36-47d5-b1cf-eed0bfeea36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074745066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3074745066
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2247905000
Short name T217
Test name
Test status
Simulation time 1121311162 ps
CPU time 11.86 seconds
Started Aug 09 05:47:50 PM PDT 24
Finished Aug 09 05:48:02 PM PDT 24
Peak memory 219972 kb
Host smart-46e4ab9a-378d-4b9c-8fce-8ebd1c03699d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247905000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2247905000
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1880490742
Short name T17
Test name
Test status
Simulation time 219133911 ps
CPU time 14.73 seconds
Started Aug 09 05:47:41 PM PDT 24
Finished Aug 09 05:47:56 PM PDT 24
Peak memory 219952 kb
Host smart-0b8a5781-e06b-4557-98c1-0c4ede067faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880490742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1880490742
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2253126313
Short name T324
Test name
Test status
Simulation time 296932304629 ps
CPU time 2853.19 seconds
Started Aug 09 05:47:44 PM PDT 24
Finished Aug 09 06:35:17 PM PDT 24
Peak memory 245464 kb
Host smart-5647de75-5fc1-4028-9bf7-d8f0308552f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253126313 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2253126313
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1472398827
Short name T62
Test name
Test status
Simulation time 4908571276 ps
CPU time 9.98 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:47:58 PM PDT 24
Peak memory 219244 kb
Host smart-0d0ddfc7-588a-4ea5-aaff-ee39aa51c37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472398827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1472398827
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.362234628
Short name T303
Test name
Test status
Simulation time 2149085998 ps
CPU time 138.05 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:50:07 PM PDT 24
Peak memory 229140 kb
Host smart-b422cb46-338c-4cb5-8380-361aa6a1f75f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362234628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.362234628
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3981668549
Short name T328
Test name
Test status
Simulation time 1033545443 ps
CPU time 23.11 seconds
Started Aug 09 05:47:50 PM PDT 24
Finished Aug 09 05:48:13 PM PDT 24
Peak memory 220044 kb
Host smart-d0f4cb9b-c2a4-4ebd-b499-5f9101aa3d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981668549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3981668549
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2300953491
Short name T270
Test name
Test status
Simulation time 816489197 ps
CPU time 12.02 seconds
Started Aug 09 05:47:53 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 220008 kb
Host smart-d6f47885-785f-43d8-a0c9-a07a762d551c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300953491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2300953491
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1468115510
Short name T73
Test name
Test status
Simulation time 207002380 ps
CPU time 14.6 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:48:02 PM PDT 24
Peak memory 219916 kb
Host smart-e458bf29-1477-46df-8d8a-01708a9f1d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468115510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1468115510
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2838637764
Short name T51
Test name
Test status
Simulation time 375197116809 ps
CPU time 3736.2 seconds
Started Aug 09 05:47:50 PM PDT 24
Finished Aug 09 06:50:07 PM PDT 24
Peak memory 261180 kb
Host smart-5096d9b7-579b-4d45-b28d-facfeb6ddf1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838637764 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2838637764
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3591733023
Short name T10
Test name
Test status
Simulation time 591418532 ps
CPU time 8.32 seconds
Started Aug 09 05:47:54 PM PDT 24
Finished Aug 09 05:48:03 PM PDT 24
Peak memory 219020 kb
Host smart-8326d0d7-c915-42a5-a194-2f194e46f7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591733023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3591733023
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.595589767
Short name T195
Test name
Test status
Simulation time 38061430026 ps
CPU time 372.99 seconds
Started Aug 09 05:47:49 PM PDT 24
Finished Aug 09 05:54:02 PM PDT 24
Peak memory 239748 kb
Host smart-59b6c8f5-332d-47cf-aab8-92f19437c1c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595589767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.595589767
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1775252317
Short name T309
Test name
Test status
Simulation time 332503108 ps
CPU time 19.48 seconds
Started Aug 09 05:47:57 PM PDT 24
Finished Aug 09 05:48:16 PM PDT 24
Peak memory 219968 kb
Host smart-9ef716ad-eb49-49ce-a057-496fc016a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775252317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1775252317
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1276830029
Short name T198
Test name
Test status
Simulation time 186272519 ps
CPU time 10.55 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:47:59 PM PDT 24
Peak memory 220016 kb
Host smart-67042940-ab0a-48ec-b631-b047d924b0cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276830029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1276830029
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.958692051
Short name T204
Test name
Test status
Simulation time 662459004 ps
CPU time 17.15 seconds
Started Aug 09 05:47:48 PM PDT 24
Finished Aug 09 05:48:06 PM PDT 24
Peak memory 212792 kb
Host smart-7e5cb02c-3487-4a7e-b4f8-63ae14dd8865
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958692051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.958692051
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.796430895
Short name T61
Test name
Test status
Simulation time 885122848 ps
CPU time 10.03 seconds
Started Aug 09 05:47:54 PM PDT 24
Finished Aug 09 05:48:04 PM PDT 24
Peak memory 219060 kb
Host smart-eb4c6916-cc81-49f1-9a53-341c25a6b919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796430895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.796430895
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2675435193
Short name T41
Test name
Test status
Simulation time 58397530509 ps
CPU time 342.55 seconds
Started Aug 09 05:47:54 PM PDT 24
Finished Aug 09 05:53:37 PM PDT 24
Peak memory 231264 kb
Host smart-4a29c2a7-8f5c-4508-89e0-486ffdcd8529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675435193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2675435193
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1062616048
Short name T320
Test name
Test status
Simulation time 1224599749 ps
CPU time 19.28 seconds
Started Aug 09 05:47:54 PM PDT 24
Finished Aug 09 05:48:14 PM PDT 24
Peak memory 219960 kb
Host smart-1fff2fa4-d27e-48f6-8a11-c59eb52b582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062616048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1062616048
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2740219343
Short name T8
Test name
Test status
Simulation time 718558322 ps
CPU time 10.49 seconds
Started Aug 09 05:47:54 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 220056 kb
Host smart-780c8a46-217c-4a40-8a20-a11d7267c459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740219343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2740219343
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1668506302
Short name T91
Test name
Test status
Simulation time 343133898 ps
CPU time 23.23 seconds
Started Aug 09 05:47:57 PM PDT 24
Finished Aug 09 05:48:20 PM PDT 24
Peak memory 219972 kb
Host smart-7f97f600-83f8-4663-bde7-bcd34ca5f6b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668506302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1668506302
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2054988105
Short name T251
Test name
Test status
Simulation time 2248048598 ps
CPU time 10.21 seconds
Started Aug 09 05:48:04 PM PDT 24
Finished Aug 09 05:48:15 PM PDT 24
Peak memory 219292 kb
Host smart-aed4f662-ccfd-43fb-a111-0160d79667f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054988105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2054988105
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.733683719
Short name T323
Test name
Test status
Simulation time 13670833647 ps
CPU time 134.88 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:50:23 PM PDT 24
Peak memory 220284 kb
Host smart-4058677a-9bcb-431f-ac62-10b5a72a8c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733683719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.733683719
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3404132328
Short name T321
Test name
Test status
Simulation time 333612967 ps
CPU time 19.11 seconds
Started Aug 09 05:48:02 PM PDT 24
Finished Aug 09 05:48:21 PM PDT 24
Peak memory 220036 kb
Host smart-3deae4b1-63e1-45c1-b71b-53890df92c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404132328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3404132328
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1508872254
Short name T147
Test name
Test status
Simulation time 877185132 ps
CPU time 10.34 seconds
Started Aug 09 05:47:55 PM PDT 24
Finished Aug 09 05:48:05 PM PDT 24
Peak memory 220088 kb
Host smart-ae8af514-b212-49a0-bdff-8c678042a9df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508872254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1508872254
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3504229446
Short name T60
Test name
Test status
Simulation time 339391279 ps
CPU time 8.14 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:16 PM PDT 24
Peak memory 219048 kb
Host smart-0dc775dd-3610-4e12-8860-b246a7da9073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504229446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3504229446
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4191534682
Short name T40
Test name
Test status
Simulation time 18316111517 ps
CPU time 260.16 seconds
Started Aug 09 05:47:59 PM PDT 24
Finished Aug 09 05:52:19 PM PDT 24
Peak memory 225592 kb
Host smart-0737dcd0-897b-4d0d-82d5-b48151af30fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191534682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4191534682
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1265424355
Short name T256
Test name
Test status
Simulation time 1435334141 ps
CPU time 19.04 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:27 PM PDT 24
Peak memory 219984 kb
Host smart-70db53d0-df67-4638-a1c2-520a5db0e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265424355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1265424355
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1830904206
Short name T157
Test name
Test status
Simulation time 532478114 ps
CPU time 12.12 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:48:21 PM PDT 24
Peak memory 220020 kb
Host smart-93b6d6b5-914d-4407-a423-bf01a1ecd683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830904206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1830904206
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1148234772
Short name T281
Test name
Test status
Simulation time 352922229 ps
CPU time 23.72 seconds
Started Aug 09 05:48:04 PM PDT 24
Finished Aug 09 05:48:28 PM PDT 24
Peak memory 220004 kb
Host smart-232e12e8-350a-46b7-bcc1-d5bf31dcfdc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148234772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1148234772
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3021393258
Short name T56
Test name
Test status
Simulation time 63353167484 ps
CPU time 2900.61 seconds
Started Aug 09 05:48:01 PM PDT 24
Finished Aug 09 06:36:22 PM PDT 24
Peak memory 233920 kb
Host smart-04f48d0c-9a0c-42bc-a6fa-3d6a1d202bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021393258 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3021393258
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1734278285
Short name T306
Test name
Test status
Simulation time 1027729641 ps
CPU time 10.09 seconds
Started Aug 09 05:47:59 PM PDT 24
Finished Aug 09 05:48:09 PM PDT 24
Peak memory 219144 kb
Host smart-f9dd1877-edda-40fb-84fe-7dec38594032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734278285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1734278285
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.403090158
Short name T19
Test name
Test status
Simulation time 4643228462 ps
CPU time 338.91 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:53:49 PM PDT 24
Peak memory 239676 kb
Host smart-abdf210b-1c04-4b5a-9718-71e5d97b450b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403090158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.403090158
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1224031228
Short name T244
Test name
Test status
Simulation time 340941179 ps
CPU time 19.24 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:48:29 PM PDT 24
Peak memory 219976 kb
Host smart-7a4c22c4-74ce-4c2c-bc2c-185e9aab1df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224031228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1224031228
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3797433276
Short name T194
Test name
Test status
Simulation time 272033800 ps
CPU time 12.3 seconds
Started Aug 09 05:48:01 PM PDT 24
Finished Aug 09 05:48:14 PM PDT 24
Peak memory 220040 kb
Host smart-7143a393-57cf-4bc7-8cf0-6e0bfefa8ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797433276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3797433276
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2025293447
Short name T241
Test name
Test status
Simulation time 2220383016 ps
CPU time 27.95 seconds
Started Aug 09 05:48:01 PM PDT 24
Finished Aug 09 05:48:29 PM PDT 24
Peak memory 220156 kb
Host smart-29407905-8308-4b97-b124-01af1714a645
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025293447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2025293447
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2812771613
Short name T312
Test name
Test status
Simulation time 20665021765 ps
CPU time 828.72 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 06:01:58 PM PDT 24
Peak memory 231452 kb
Host smart-e83fce74-cbdc-4b86-adcc-73e8b5487280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812771613 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2812771613
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3721170571
Short name T298
Test name
Test status
Simulation time 265377021 ps
CPU time 10.08 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:48:19 PM PDT 24
Peak memory 219044 kb
Host smart-d47d7137-ef3b-4583-bf75-68f82233d6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721170571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3721170571
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3514848081
Short name T166
Test name
Test status
Simulation time 34583378035 ps
CPU time 288.65 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:52:58 PM PDT 24
Peak memory 239220 kb
Host smart-2c20d361-896b-484b-8f34-5b2c93056c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514848081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3514848081
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1709776742
Short name T248
Test name
Test status
Simulation time 339145355 ps
CPU time 19.11 seconds
Started Aug 09 05:48:00 PM PDT 24
Finished Aug 09 05:48:19 PM PDT 24
Peak memory 220060 kb
Host smart-6efa5cd1-69ca-4378-b846-e21c7e592e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709776742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1709776742
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3072257833
Short name T180
Test name
Test status
Simulation time 347885121 ps
CPU time 10.55 seconds
Started Aug 09 05:48:02 PM PDT 24
Finished Aug 09 05:48:12 PM PDT 24
Peak memory 220020 kb
Host smart-d9ae4a43-4bc3-4d7f-83f5-c999106d4ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072257833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3072257833
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2690536702
Short name T211
Test name
Test status
Simulation time 362296045 ps
CPU time 10.61 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:48:20 PM PDT 24
Peak memory 219952 kb
Host smart-30676966-7636-49da-9e0c-6edf5ed3f569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690536702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2690536702
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3635886139
Short name T1
Test name
Test status
Simulation time 175274507 ps
CPU time 8.36 seconds
Started Aug 09 05:48:11 PM PDT 24
Finished Aug 09 05:48:19 PM PDT 24
Peak memory 219048 kb
Host smart-912811f9-dbb8-4371-9e9a-e1a7b6569703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635886139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3635886139
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.256870140
Short name T170
Test name
Test status
Simulation time 2158046363 ps
CPU time 127.64 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:50:17 PM PDT 24
Peak memory 229188 kb
Host smart-b4e33e3a-c042-43a0-aa38-77ce5b6e0925
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256870140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.256870140
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1957513589
Short name T308
Test name
Test status
Simulation time 2738801812 ps
CPU time 22.77 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 220160 kb
Host smart-14e9384d-ee03-40b7-b7a8-eb84009c530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957513589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1957513589
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2393622982
Short name T254
Test name
Test status
Simulation time 259707415 ps
CPU time 12.15 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:21 PM PDT 24
Peak memory 220064 kb
Host smart-cc8caaf5-d7ce-4a46-9676-08b918c6398f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393622982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2393622982
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2201392469
Short name T58
Test name
Test status
Simulation time 4495975944 ps
CPU time 23.86 seconds
Started Aug 09 05:48:07 PM PDT 24
Finished Aug 09 05:48:31 PM PDT 24
Peak memory 220168 kb
Host smart-43e58067-ab8a-444e-af8c-11a2fe0b1241
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201392469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2201392469
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3431017377
Short name T266
Test name
Test status
Simulation time 167986765 ps
CPU time 8.34 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 05:48:18 PM PDT 24
Peak memory 219132 kb
Host smart-c1229e57-3f3b-4fc8-ba50-573859166aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431017377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3431017377
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2558581733
Short name T188
Test name
Test status
Simulation time 3814894877 ps
CPU time 288.13 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:52:57 PM PDT 24
Peak memory 239556 kb
Host smart-30204d31-753b-4fba-9851-ded34920dae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558581733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2558581733
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1409950495
Short name T221
Test name
Test status
Simulation time 2055784989 ps
CPU time 21.64 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:29 PM PDT 24
Peak memory 220004 kb
Host smart-8099715e-a288-4589-91e8-9744337fe78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409950495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1409950495
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1646338850
Short name T208
Test name
Test status
Simulation time 469495668 ps
CPU time 12.39 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:48:23 PM PDT 24
Peak memory 220032 kb
Host smart-f7d43204-13be-407e-9948-e323ffc6c971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646338850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1646338850
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.634226569
Short name T160
Test name
Test status
Simulation time 544708822 ps
CPU time 30.76 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:39 PM PDT 24
Peak memory 219988 kb
Host smart-ecc20c33-b89a-4af7-abb3-b0fb5180e318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634226569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.634226569
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3476840217
Short name T278
Test name
Test status
Simulation time 105856672432 ps
CPU time 7196.15 seconds
Started Aug 09 05:48:09 PM PDT 24
Finished Aug 09 07:48:06 PM PDT 24
Peak memory 236632 kb
Host smart-48f56fbb-f3d8-4eb9-a5c6-67d009fff2a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476840217 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3476840217
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1442238047
Short name T183
Test name
Test status
Simulation time 1502510739 ps
CPU time 8.19 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:46:59 PM PDT 24
Peak memory 219000 kb
Host smart-068e6525-20b8-4c53-8b0b-b2bfa3a4fa0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442238047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1442238047
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1306666684
Short name T186
Test name
Test status
Simulation time 7674822611 ps
CPU time 207.83 seconds
Started Aug 09 05:46:44 PM PDT 24
Finished Aug 09 05:50:12 PM PDT 24
Peak memory 238028 kb
Host smart-62f15cb6-95bc-4ac3-9ef1-8f1f171c3605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306666684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1306666684
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1098381220
Short name T201
Test name
Test status
Simulation time 1029670803 ps
CPU time 22.99 seconds
Started Aug 09 05:46:49 PM PDT 24
Finished Aug 09 05:47:12 PM PDT 24
Peak memory 220064 kb
Host smart-cc885a3a-5d16-4e86-8d6e-711eb48f6b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098381220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1098381220
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4096068401
Short name T282
Test name
Test status
Simulation time 949800278 ps
CPU time 12.1 seconds
Started Aug 09 05:46:45 PM PDT 24
Finished Aug 09 05:46:57 PM PDT 24
Peak memory 220004 kb
Host smart-99e78974-b25c-4c8c-bcaf-26ee314e722f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096068401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4096068401
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3841208831
Short name T23
Test name
Test status
Simulation time 2061890373 ps
CPU time 116.74 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:48:48 PM PDT 24
Peak memory 238852 kb
Host smart-2be665f0-8fd0-4b19-a956-3e5cd446160f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841208831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3841208831
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1411643758
Short name T72
Test name
Test status
Simulation time 727221704 ps
CPU time 10.56 seconds
Started Aug 09 05:46:46 PM PDT 24
Finished Aug 09 05:46:57 PM PDT 24
Peak memory 220004 kb
Host smart-25d813d3-2d0f-4d67-b94a-b1d0fe9f50de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411643758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1411643758
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.550616578
Short name T242
Test name
Test status
Simulation time 645304599 ps
CPU time 19.86 seconds
Started Aug 09 05:46:45 PM PDT 24
Finished Aug 09 05:47:05 PM PDT 24
Peak memory 219972 kb
Host smart-61aafc3b-a53e-40b6-a211-83af787eb395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550616578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.550616578
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1218551358
Short name T128
Test name
Test status
Simulation time 2757460177 ps
CPU time 8.23 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:16 PM PDT 24
Peak memory 219180 kb
Host smart-cf81a880-1fc7-4f9f-a242-709f2e467d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218551358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1218551358
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1586078166
Short name T39
Test name
Test status
Simulation time 21820859587 ps
CPU time 284.31 seconds
Started Aug 09 05:48:11 PM PDT 24
Finished Aug 09 05:52:55 PM PDT 24
Peak memory 240500 kb
Host smart-c6578242-8c58-48bd-b682-3676048b1c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586078166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1586078166
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.602817527
Short name T240
Test name
Test status
Simulation time 664166631 ps
CPU time 19.21 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:48:30 PM PDT 24
Peak memory 220040 kb
Host smart-74ed9082-7ba6-49cb-96ba-08d849ad7a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602817527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.602817527
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1156839851
Short name T218
Test name
Test status
Simulation time 186192720 ps
CPU time 10.67 seconds
Started Aug 09 05:48:11 PM PDT 24
Finished Aug 09 05:48:22 PM PDT 24
Peak memory 219992 kb
Host smart-9b01b41c-b164-4943-bb41-5a009ffee864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156839851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1156839851
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3573317394
Short name T143
Test name
Test status
Simulation time 1063064608 ps
CPU time 15.24 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:48:26 PM PDT 24
Peak memory 219508 kb
Host smart-5c5e4f81-d229-4f40-958f-acb452c28d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573317394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3573317394
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3867067279
Short name T236
Test name
Test status
Simulation time 790977159 ps
CPU time 8.4 seconds
Started Aug 09 05:48:15 PM PDT 24
Finished Aug 09 05:48:23 PM PDT 24
Peak memory 218960 kb
Host smart-2d0d1a92-5e07-4bc4-be35-3a9572b43e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867067279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3867067279
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1231965023
Short name T313
Test name
Test status
Simulation time 41898247792 ps
CPU time 229.11 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:51:59 PM PDT 24
Peak memory 220352 kb
Host smart-a7216595-7c47-49b1-a8b3-4e7b6bf7c947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231965023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1231965023
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1725973938
Short name T314
Test name
Test status
Simulation time 1974789450 ps
CPU time 32.73 seconds
Started Aug 09 05:48:10 PM PDT 24
Finished Aug 09 05:48:42 PM PDT 24
Peak memory 219644 kb
Host smart-8c277ce7-2663-4c9a-8d7f-db4933c4a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725973938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1725973938
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1303542106
Short name T75
Test name
Test status
Simulation time 185751683 ps
CPU time 10.57 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:19 PM PDT 24
Peak memory 219932 kb
Host smart-bcdb0e9a-d7f6-45ea-9c2b-081171dc42f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303542106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1303542106
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2716950081
Short name T290
Test name
Test status
Simulation time 3922846401 ps
CPU time 27.17 seconds
Started Aug 09 05:48:08 PM PDT 24
Finished Aug 09 05:48:35 PM PDT 24
Peak memory 220128 kb
Host smart-812b5a82-ece1-4bc9-87a1-b9ac7a426c57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716950081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2716950081
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2200852497
Short name T15
Test name
Test status
Simulation time 42626036565 ps
CPU time 7384.38 seconds
Started Aug 09 05:48:15 PM PDT 24
Finished Aug 09 07:51:20 PM PDT 24
Peak memory 234184 kb
Host smart-035b5814-55c4-458b-8494-d6c9775b68fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200852497 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2200852497
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1232568705
Short name T177
Test name
Test status
Simulation time 259391090 ps
CPU time 10.36 seconds
Started Aug 09 05:48:14 PM PDT 24
Finished Aug 09 05:48:24 PM PDT 24
Peak memory 218948 kb
Host smart-4c012cca-09e7-4df4-b161-7c107bca15f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232568705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1232568705
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.19078959
Short name T37
Test name
Test status
Simulation time 2169566455 ps
CPU time 152.81 seconds
Started Aug 09 05:48:14 PM PDT 24
Finished Aug 09 05:50:47 PM PDT 24
Peak memory 238440 kb
Host smart-8c53e27f-9ccc-44e3-8a3c-9a75f9ebcae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_co
rrupt_sig_fatal_chk.19078959
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3625700527
Short name T231
Test name
Test status
Simulation time 481116253 ps
CPU time 19.28 seconds
Started Aug 09 05:48:15 PM PDT 24
Finished Aug 09 05:48:35 PM PDT 24
Peak memory 219996 kb
Host smart-0948043a-9cd8-40d1-8485-12c1b6804816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625700527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3625700527
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3949762131
Short name T76
Test name
Test status
Simulation time 365529090 ps
CPU time 10.22 seconds
Started Aug 09 05:48:13 PM PDT 24
Finished Aug 09 05:48:24 PM PDT 24
Peak memory 220056 kb
Host smart-a9d7e12c-c157-423a-ad25-d5b684f13192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949762131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3949762131
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1519093613
Short name T90
Test name
Test status
Simulation time 1343932345 ps
CPU time 12.83 seconds
Started Aug 09 05:48:14 PM PDT 24
Finished Aug 09 05:48:27 PM PDT 24
Peak memory 220032 kb
Host smart-62f55753-0e79-4b20-9c5a-9e5455cd7f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519093613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1519093613
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3175034962
Short name T196
Test name
Test status
Simulation time 172958799 ps
CPU time 8.39 seconds
Started Aug 09 05:48:15 PM PDT 24
Finished Aug 09 05:48:24 PM PDT 24
Peak memory 219068 kb
Host smart-e86fdd7f-0e21-44d0-b8b9-7fe6ad7c12a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175034962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3175034962
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.461939876
Short name T162
Test name
Test status
Simulation time 77764002097 ps
CPU time 295.54 seconds
Started Aug 09 05:48:14 PM PDT 24
Finished Aug 09 05:53:10 PM PDT 24
Peak memory 226676 kb
Host smart-2d9cfcf4-8594-467c-8e5a-4c7f315bbcfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461939876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.461939876
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1303953912
Short name T295
Test name
Test status
Simulation time 2154760494 ps
CPU time 22.31 seconds
Started Aug 09 05:48:14 PM PDT 24
Finished Aug 09 05:48:36 PM PDT 24
Peak memory 220148 kb
Host smart-8363ddb6-bc32-4fe7-b442-7c4fdb5dcf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303953912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1303953912
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1075650074
Short name T158
Test name
Test status
Simulation time 260773332 ps
CPU time 11.72 seconds
Started Aug 09 05:48:15 PM PDT 24
Finished Aug 09 05:48:26 PM PDT 24
Peak memory 220008 kb
Host smart-498176c1-543e-4640-a3bb-310e7c45fc4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075650074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1075650074
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.610820226
Short name T238
Test name
Test status
Simulation time 1925482364 ps
CPU time 34.61 seconds
Started Aug 09 05:48:16 PM PDT 24
Finished Aug 09 05:48:51 PM PDT 24
Peak memory 219984 kb
Host smart-355662f5-e7d4-4e44-b575-4386ffd1d626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610820226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.610820226
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.828115760
Short name T71
Test name
Test status
Simulation time 259242136 ps
CPU time 10.21 seconds
Started Aug 09 05:48:23 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 219076 kb
Host smart-c1d26125-d3c3-4cdd-aefe-a57d896e76da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828115760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.828115760
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1445536725
Short name T171
Test name
Test status
Simulation time 25402690575 ps
CPU time 358.1 seconds
Started Aug 09 05:48:23 PM PDT 24
Finished Aug 09 05:54:21 PM PDT 24
Peak memory 236584 kb
Host smart-851ae135-a49a-42c9-b5ef-de535e33054a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445536725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1445536725
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.748240790
Short name T228
Test name
Test status
Simulation time 661858646 ps
CPU time 23.15 seconds
Started Aug 09 05:48:23 PM PDT 24
Finished Aug 09 05:48:46 PM PDT 24
Peak memory 220092 kb
Host smart-47c26999-716a-45c2-8208-15cc3bad49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748240790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.748240790
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2531220845
Short name T57
Test name
Test status
Simulation time 364885055 ps
CPU time 10.47 seconds
Started Aug 09 05:48:21 PM PDT 24
Finished Aug 09 05:48:31 PM PDT 24
Peak memory 220060 kb
Host smart-dc19a0f2-dd36-4c06-9083-f13d62569e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531220845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2531220845
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2965803213
Short name T292
Test name
Test status
Simulation time 2172773161 ps
CPU time 31.88 seconds
Started Aug 09 05:48:22 PM PDT 24
Finished Aug 09 05:48:54 PM PDT 24
Peak memory 220132 kb
Host smart-62a881db-172b-4aa4-bb7a-658153c0406a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965803213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2965803213
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4094449819
Short name T148
Test name
Test status
Simulation time 689376292 ps
CPU time 8.36 seconds
Started Aug 09 05:48:22 PM PDT 24
Finished Aug 09 05:48:31 PM PDT 24
Peak memory 219120 kb
Host smart-faae61cf-1da7-484e-8f17-ffad462e2662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094449819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4094449819
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4201935677
Short name T199
Test name
Test status
Simulation time 15281442846 ps
CPU time 265.61 seconds
Started Aug 09 05:48:21 PM PDT 24
Finished Aug 09 05:52:46 PM PDT 24
Peak memory 227692 kb
Host smart-c7ad950f-375a-4f57-ab31-94fc6d73266d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201935677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4201935677
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1183039910
Short name T288
Test name
Test status
Simulation time 2058026827 ps
CPU time 22.74 seconds
Started Aug 09 05:48:22 PM PDT 24
Finished Aug 09 05:48:45 PM PDT 24
Peak memory 220048 kb
Host smart-fa6cb854-13fb-4bc3-ba87-778e160b4811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183039910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1183039910
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2946786294
Short name T325
Test name
Test status
Simulation time 703676848 ps
CPU time 10.31 seconds
Started Aug 09 05:48:23 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 220032 kb
Host smart-0d900828-8a7a-4197-8686-379a16ade327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946786294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2946786294
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2358856508
Short name T326
Test name
Test status
Simulation time 1919659302 ps
CPU time 26.84 seconds
Started Aug 09 05:48:22 PM PDT 24
Finished Aug 09 05:48:49 PM PDT 24
Peak memory 220036 kb
Host smart-6bd3b276-5c94-4a73-9613-bb97e4b04853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358856508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2358856508
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2634454430
Short name T287
Test name
Test status
Simulation time 89603388159 ps
CPU time 3316.08 seconds
Started Aug 09 05:48:19 PM PDT 24
Finished Aug 09 06:43:35 PM PDT 24
Peak memory 253908 kb
Host smart-bd354270-9b1b-457f-8c51-4ca1b0ff2db4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634454430 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2634454430
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2139180591
Short name T164
Test name
Test status
Simulation time 4795365926 ps
CPU time 195.87 seconds
Started Aug 09 05:48:24 PM PDT 24
Finished Aug 09 05:51:39 PM PDT 24
Peak memory 231456 kb
Host smart-06637ff8-bda2-4638-8e05-7a518f0507b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139180591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2139180591
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2571219611
Short name T301
Test name
Test status
Simulation time 336857838 ps
CPU time 19.56 seconds
Started Aug 09 05:48:23 PM PDT 24
Finished Aug 09 05:48:42 PM PDT 24
Peak memory 220084 kb
Host smart-cc4c85b0-dacd-4dc1-8262-aab209017303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571219611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2571219611
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1654015768
Short name T132
Test name
Test status
Simulation time 1019465889 ps
CPU time 12.1 seconds
Started Aug 09 05:48:21 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 220000 kb
Host smart-1368cdcb-db61-4522-afc1-a050c2038aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654015768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1654015768
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1385101901
Short name T272
Test name
Test status
Simulation time 533888329 ps
CPU time 23.89 seconds
Started Aug 09 05:48:24 PM PDT 24
Finished Aug 09 05:48:48 PM PDT 24
Peak memory 220000 kb
Host smart-4aa11576-d198-4788-a5b0-dc7ed5d5e1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385101901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1385101901
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3153098731
Short name T149
Test name
Test status
Simulation time 174619026 ps
CPU time 8.53 seconds
Started Aug 09 05:48:27 PM PDT 24
Finished Aug 09 05:48:35 PM PDT 24
Peak memory 219060 kb
Host smart-ece153e5-c4d0-48a1-825a-6a408d04b51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153098731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3153098731
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3864273885
Short name T124
Test name
Test status
Simulation time 24107570255 ps
CPU time 252.28 seconds
Started Aug 09 05:48:27 PM PDT 24
Finished Aug 09 05:52:39 PM PDT 24
Peak memory 235884 kb
Host smart-88b8e367-3a85-4020-98f6-01efe98041d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864273885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3864273885
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.322538813
Short name T213
Test name
Test status
Simulation time 3085223126 ps
CPU time 22.37 seconds
Started Aug 09 05:48:25 PM PDT 24
Finished Aug 09 05:48:48 PM PDT 24
Peak memory 220136 kb
Host smart-3b19d4c9-2f59-4b99-8c0f-a5a61b4c6e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322538813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.322538813
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.51873661
Short name T165
Test name
Test status
Simulation time 266205414 ps
CPU time 11.76 seconds
Started Aug 09 05:48:25 PM PDT 24
Finished Aug 09 05:48:37 PM PDT 24
Peak memory 220064 kb
Host smart-360d613c-4888-4f6f-bff7-84d2d40e81e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51873661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.51873661
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3059487868
Short name T94
Test name
Test status
Simulation time 528191338 ps
CPU time 27.45 seconds
Started Aug 09 05:48:26 PM PDT 24
Finished Aug 09 05:48:53 PM PDT 24
Peak memory 220024 kb
Host smart-870027ea-e192-423c-b43e-07bac43583f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059487868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3059487868
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.824565838
Short name T237
Test name
Test status
Simulation time 4478495041 ps
CPU time 15.26 seconds
Started Aug 09 05:48:28 PM PDT 24
Finished Aug 09 05:48:44 PM PDT 24
Peak memory 219116 kb
Host smart-1aa92595-45d4-418a-ba4a-16eadcd7d44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824565838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.824565838
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2617287273
Short name T212
Test name
Test status
Simulation time 2064376243 ps
CPU time 22.67 seconds
Started Aug 09 05:48:25 PM PDT 24
Finished Aug 09 05:48:48 PM PDT 24
Peak memory 220024 kb
Host smart-fa9a1d64-5120-4af7-96b9-be71f358bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617287273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2617287273
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.657885821
Short name T316
Test name
Test status
Simulation time 371032613 ps
CPU time 10.65 seconds
Started Aug 09 05:48:26 PM PDT 24
Finished Aug 09 05:48:36 PM PDT 24
Peak memory 220068 kb
Host smart-67e62d1a-a16d-49aa-95ea-c8caa73560c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657885821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.657885821
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1275692298
Short name T67
Test name
Test status
Simulation time 388369012 ps
CPU time 27.05 seconds
Started Aug 09 05:48:27 PM PDT 24
Finished Aug 09 05:48:54 PM PDT 24
Peak memory 219916 kb
Host smart-335f378e-6df4-46ad-a9ee-4744aad47600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275692298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1275692298
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1189691787
Short name T53
Test name
Test status
Simulation time 174065622495 ps
CPU time 1487.22 seconds
Started Aug 09 05:48:26 PM PDT 24
Finished Aug 09 06:13:13 PM PDT 24
Peak memory 247584 kb
Host smart-6e22a2ec-039a-4391-882d-5cdc571b7bd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189691787 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1189691787
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2390142974
Short name T317
Test name
Test status
Simulation time 459386229 ps
CPU time 8.69 seconds
Started Aug 09 05:48:38 PM PDT 24
Finished Aug 09 05:48:47 PM PDT 24
Peak memory 219048 kb
Host smart-d22d67ef-ef54-4f2f-a993-2c355f53df32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390142974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2390142974
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.237869789
Short name T42
Test name
Test status
Simulation time 9328508434 ps
CPU time 148.11 seconds
Started Aug 09 05:48:36 PM PDT 24
Finished Aug 09 05:51:04 PM PDT 24
Peak memory 220304 kb
Host smart-c6583022-8bba-4441-abe6-e8dbc5854f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237869789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.237869789
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2747584339
Short name T300
Test name
Test status
Simulation time 501574038 ps
CPU time 21.67 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 05:48:56 PM PDT 24
Peak memory 219956 kb
Host smart-a6068568-27a1-41dc-b694-ed6e94c0013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747584339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2747584339
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2309488887
Short name T154
Test name
Test status
Simulation time 350179745 ps
CPU time 10.38 seconds
Started Aug 09 05:48:26 PM PDT 24
Finished Aug 09 05:48:37 PM PDT 24
Peak memory 220028 kb
Host smart-24432cf7-f5dc-427a-a4e2-8caaa8a82b67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309488887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2309488887
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.430230166
Short name T258
Test name
Test status
Simulation time 1236654811 ps
CPU time 38.25 seconds
Started Aug 09 05:48:27 PM PDT 24
Finished Aug 09 05:49:05 PM PDT 24
Peak memory 219920 kb
Host smart-78867236-8176-4792-8876-1d1629f98042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430230166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.430230166
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1396427249
Short name T294
Test name
Test status
Simulation time 240553274244 ps
CPU time 1382.48 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 06:11:37 PM PDT 24
Peak memory 244728 kb
Host smart-f11a9227-18f7-4df8-98ab-14c2ef275fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396427249 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1396427249
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2657234724
Short name T169
Test name
Test status
Simulation time 497575762 ps
CPU time 10.17 seconds
Started Aug 09 05:46:52 PM PDT 24
Finished Aug 09 05:47:02 PM PDT 24
Peak memory 219148 kb
Host smart-f2cebe85-f299-4bdd-ad0d-fccddb130764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657234724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2657234724
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2698807855
Short name T315
Test name
Test status
Simulation time 17729989835 ps
CPU time 345.56 seconds
Started Aug 09 05:46:50 PM PDT 24
Finished Aug 09 05:52:36 PM PDT 24
Peak memory 235600 kb
Host smart-dd76ef97-5888-4178-ac6c-1193c78150bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698807855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2698807855
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2909126437
Short name T36
Test name
Test status
Simulation time 689960946 ps
CPU time 19.19 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:47:10 PM PDT 24
Peak memory 220068 kb
Host smart-0bad0dca-442c-45e3-8bcf-8476d85b6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909126437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2909126437
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.899727489
Short name T220
Test name
Test status
Simulation time 425136696 ps
CPU time 10.06 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:47:01 PM PDT 24
Peak memory 220100 kb
Host smart-0d6b0488-2657-4381-a7ce-2ab2dd211182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899727489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.899727489
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3432347105
Short name T24
Test name
Test status
Simulation time 439871650 ps
CPU time 226.49 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:50:38 PM PDT 24
Peak memory 239452 kb
Host smart-09951ef7-b7dd-40c1-9db0-24058ccc412d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432347105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3432347105
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2405805340
Short name T151
Test name
Test status
Simulation time 211411226 ps
CPU time 10.44 seconds
Started Aug 09 05:46:50 PM PDT 24
Finished Aug 09 05:47:01 PM PDT 24
Peak memory 219964 kb
Host smart-bbd47189-7f4c-4b5e-ac55-f0f0e9a40986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405805340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2405805340
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1009852679
Short name T93
Test name
Test status
Simulation time 2111158802 ps
CPU time 30.16 seconds
Started Aug 09 05:46:53 PM PDT 24
Finished Aug 09 05:47:23 PM PDT 24
Peak memory 220020 kb
Host smart-1aab5512-9047-4ebd-a833-1aca22fa7e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009852679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1009852679
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.244789777
Short name T263
Test name
Test status
Simulation time 4133937810 ps
CPU time 9.9 seconds
Started Aug 09 05:48:35 PM PDT 24
Finished Aug 09 05:48:45 PM PDT 24
Peak memory 219060 kb
Host smart-60310a30-f50b-4832-a150-be2a41c4a048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244789777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.244789777
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1167463874
Short name T43
Test name
Test status
Simulation time 18573125049 ps
CPU time 292.51 seconds
Started Aug 09 05:48:33 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 225916 kb
Host smart-8e051da9-065f-47ec-9a80-21774d25509e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167463874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1167463874
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2853177609
Short name T26
Test name
Test status
Simulation time 1098937377 ps
CPU time 22.69 seconds
Started Aug 09 05:48:35 PM PDT 24
Finished Aug 09 05:48:57 PM PDT 24
Peak memory 220028 kb
Host smart-950c0571-f423-4f83-9865-bd77c2cbc572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853177609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2853177609
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3848691911
Short name T273
Test name
Test status
Simulation time 3172578102 ps
CPU time 12.25 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 05:48:46 PM PDT 24
Peak memory 220140 kb
Host smart-2d86ba7c-c256-4faa-9ea3-5d8258ba0c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848691911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3848691911
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2165494195
Short name T302
Test name
Test status
Simulation time 315991472 ps
CPU time 17.04 seconds
Started Aug 09 05:48:33 PM PDT 24
Finished Aug 09 05:48:50 PM PDT 24
Peak memory 220056 kb
Host smart-8e4f43a8-dd3c-43ab-8452-078dba20b794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165494195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2165494195
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2655506490
Short name T55
Test name
Test status
Simulation time 71685614866 ps
CPU time 2960.55 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 06:37:55 PM PDT 24
Peak memory 249768 kb
Host smart-593fe2b8-bd04-49dd-b420-d3eeb81c8d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655506490 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2655506490
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3902664693
Short name T133
Test name
Test status
Simulation time 661509171 ps
CPU time 8.34 seconds
Started Aug 09 05:48:43 PM PDT 24
Finished Aug 09 05:48:52 PM PDT 24
Peak memory 219136 kb
Host smart-439ac7c4-8c2c-4cde-8a60-eb6f290186af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902664693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3902664693
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3235500403
Short name T226
Test name
Test status
Simulation time 107894620086 ps
CPU time 521.84 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 05:57:16 PM PDT 24
Peak memory 234704 kb
Host smart-c49b336a-1c02-46ea-a622-292cc766f591
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235500403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3235500403
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3730902411
Short name T46
Test name
Test status
Simulation time 1320836179 ps
CPU time 19.15 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:49:01 PM PDT 24
Peak memory 220008 kb
Host smart-aa1de95f-7313-464b-bc8a-a0e14244104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730902411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3730902411
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4027594343
Short name T230
Test name
Test status
Simulation time 1097680522 ps
CPU time 16.48 seconds
Started Aug 09 05:48:35 PM PDT 24
Finished Aug 09 05:48:52 PM PDT 24
Peak memory 219468 kb
Host smart-d8503ae5-f0a4-42d5-9d5b-2b1cdea852a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027594343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4027594343
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.739237506
Short name T185
Test name
Test status
Simulation time 278126143 ps
CPU time 11.61 seconds
Started Aug 09 05:48:34 PM PDT 24
Finished Aug 09 05:48:46 PM PDT 24
Peak memory 219980 kb
Host smart-b84408ad-5a26-44cd-8615-38d19f235bb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739237506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.739237506
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.157259056
Short name T291
Test name
Test status
Simulation time 3936368333 ps
CPU time 14.59 seconds
Started Aug 09 05:48:41 PM PDT 24
Finished Aug 09 05:48:56 PM PDT 24
Peak memory 219208 kb
Host smart-913c856e-1595-4c50-a687-3fd3e6449776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157259056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.157259056
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.585456134
Short name T189
Test name
Test status
Simulation time 3499307016 ps
CPU time 197.86 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:52:00 PM PDT 24
Peak memory 220012 kb
Host smart-f2787cd3-1b60-4999-adc2-345f013cc37f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585456134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.585456134
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.276454708
Short name T276
Test name
Test status
Simulation time 4952631807 ps
CPU time 22.88 seconds
Started Aug 09 05:48:41 PM PDT 24
Finished Aug 09 05:49:04 PM PDT 24
Peak memory 220040 kb
Host smart-aae26e73-b30b-4fc0-82e6-ebbbb3bc2c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276454708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.276454708
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1509550879
Short name T146
Test name
Test status
Simulation time 515878752 ps
CPU time 12.2 seconds
Started Aug 09 05:48:45 PM PDT 24
Finished Aug 09 05:48:57 PM PDT 24
Peak memory 219984 kb
Host smart-b6c612ab-02b1-4558-9dd4-d62ebf7b4802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509550879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1509550879
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4050428471
Short name T3
Test name
Test status
Simulation time 1940658339 ps
CPU time 27.03 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:49:09 PM PDT 24
Peak memory 219992 kb
Host smart-99db2b8d-16b8-4fae-860b-fc1d54cd7a6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050428471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4050428471
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4012943422
Short name T168
Test name
Test status
Simulation time 671508231 ps
CPU time 10.36 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:48:52 PM PDT 24
Peak memory 219056 kb
Host smart-b1464703-0d8d-4bb6-a4ef-fc150f38d612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012943422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4012943422
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2571526140
Short name T269
Test name
Test status
Simulation time 7327693834 ps
CPU time 233.46 seconds
Started Aug 09 05:48:45 PM PDT 24
Finished Aug 09 05:52:39 PM PDT 24
Peak memory 238228 kb
Host smart-c29a825c-e6b3-4411-b968-8a28de566dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571526140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2571526140
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2448468219
Short name T260
Test name
Test status
Simulation time 347411898 ps
CPU time 19.08 seconds
Started Aug 09 05:48:43 PM PDT 24
Finished Aug 09 05:49:02 PM PDT 24
Peak memory 219996 kb
Host smart-c62e5164-76ce-4522-815a-207db57c1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448468219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2448468219
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3117852168
Short name T20
Test name
Test status
Simulation time 1101685514 ps
CPU time 12.01 seconds
Started Aug 09 05:48:44 PM PDT 24
Finished Aug 09 05:48:56 PM PDT 24
Peak memory 220104 kb
Host smart-6bfab478-d661-4ca3-8cb4-abe26eb382ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117852168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3117852168
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1736208927
Short name T247
Test name
Test status
Simulation time 783457989 ps
CPU time 38.51 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:49:21 PM PDT 24
Peak memory 220044 kb
Host smart-4dd3e365-4ec5-43f6-b6c7-e513b3832c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736208927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1736208927
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2002077246
Short name T33
Test name
Test status
Simulation time 249204398 ps
CPU time 10.04 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:49:02 PM PDT 24
Peak memory 218968 kb
Host smart-885a1447-5ca7-467b-b47f-8482a01c249a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002077246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2002077246
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1572715471
Short name T187
Test name
Test status
Simulation time 5272824944 ps
CPU time 168.71 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:51:31 PM PDT 24
Peak memory 238712 kb
Host smart-1f96d491-a1f8-461b-883d-f8b5008ecf8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572715471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1572715471
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1821793771
Short name T232
Test name
Test status
Simulation time 516534549 ps
CPU time 22.41 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:49:04 PM PDT 24
Peak memory 220040 kb
Host smart-9f745b80-a7d0-4370-9d90-7495050e7e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821793771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1821793771
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3310396100
Short name T135
Test name
Test status
Simulation time 1695880164 ps
CPU time 11.86 seconds
Started Aug 09 05:48:44 PM PDT 24
Finished Aug 09 05:48:56 PM PDT 24
Peak memory 220080 kb
Host smart-a508df21-5b9a-48ba-8a64-745811bba928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310396100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3310396100
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1416147047
Short name T279
Test name
Test status
Simulation time 3315870355 ps
CPU time 27.93 seconds
Started Aug 09 05:48:42 PM PDT 24
Finished Aug 09 05:49:10 PM PDT 24
Peak memory 220120 kb
Host smart-a5da6aff-78d7-48f3-abd7-8e104fbf5abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416147047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1416147047
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3449776381
Short name T259
Test name
Test status
Simulation time 72713110642 ps
CPU time 1550.34 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 06:14:40 PM PDT 24
Peak memory 239436 kb
Host smart-62907fd7-efe2-414a-972b-d5a1d0aed1de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449776381 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3449776381
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2994699454
Short name T267
Test name
Test status
Simulation time 174503309 ps
CPU time 8.41 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:49:00 PM PDT 24
Peak memory 219092 kb
Host smart-21794cb4-6c04-4ad9-a86e-bed52369308a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994699454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2994699454
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3624209195
Short name T284
Test name
Test status
Simulation time 11351034229 ps
CPU time 185.47 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 05:51:56 PM PDT 24
Peak memory 244836 kb
Host smart-c3e512d2-af63-4b02-913e-ba14ccaec8ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624209195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3624209195
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1433101799
Short name T176
Test name
Test status
Simulation time 2063521479 ps
CPU time 22.49 seconds
Started Aug 09 05:48:49 PM PDT 24
Finished Aug 09 05:49:12 PM PDT 24
Peak memory 219924 kb
Host smart-5fb7647f-3843-485e-95b6-fc78ad40e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433101799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1433101799
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1991590351
Short name T277
Test name
Test status
Simulation time 1945303891 ps
CPU time 10.4 seconds
Started Aug 09 05:48:49 PM PDT 24
Finished Aug 09 05:49:00 PM PDT 24
Peak memory 220032 kb
Host smart-caa78b76-ff28-43a9-a4b1-17b2a1c9a591
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991590351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1991590351
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2013506342
Short name T139
Test name
Test status
Simulation time 1034830141 ps
CPU time 46.05 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 05:49:37 PM PDT 24
Peak memory 220104 kb
Host smart-36570b42-109e-43fb-9ef1-a81ee5717789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013506342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2013506342
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4194671860
Short name T274
Test name
Test status
Simulation time 24999092184 ps
CPU time 9393.15 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 08:25:24 PM PDT 24
Peak memory 235208 kb
Host smart-c4cb7219-a7c5-42ad-9384-144d75c2fc91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194671860 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.4194671860
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1064550103
Short name T202
Test name
Test status
Simulation time 311116681 ps
CPU time 10.21 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 05:49:00 PM PDT 24
Peak memory 219004 kb
Host smart-6e513cdb-f820-4765-8030-82eece033b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064550103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1064550103
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1601130867
Short name T145
Test name
Test status
Simulation time 3624235742 ps
CPU time 216.89 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:52:28 PM PDT 24
Peak memory 238556 kb
Host smart-8b4702af-a975-4d99-a1a6-c67755dbca85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601130867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1601130867
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1738186798
Short name T2
Test name
Test status
Simulation time 1010554342 ps
CPU time 22.8 seconds
Started Aug 09 05:48:50 PM PDT 24
Finished Aug 09 05:49:13 PM PDT 24
Peak memory 220056 kb
Host smart-34254fc4-3c53-4b4e-8f0e-578e8cc2006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738186798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1738186798
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.881194748
Short name T191
Test name
Test status
Simulation time 361937816 ps
CPU time 10.27 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:49:01 PM PDT 24
Peak memory 220032 kb
Host smart-a369609a-1b2f-4a6f-997a-c3cc0cfbc1df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881194748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.881194748
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2150503574
Short name T179
Test name
Test status
Simulation time 2826295512 ps
CPU time 28.96 seconds
Started Aug 09 05:48:53 PM PDT 24
Finished Aug 09 05:49:22 PM PDT 24
Peak memory 220184 kb
Host smart-259f07fb-6d9c-4ad4-83f9-c2b28445209f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150503574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2150503574
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2832365835
Short name T182
Test name
Test status
Simulation time 691059065 ps
CPU time 10.21 seconds
Started Aug 09 05:49:01 PM PDT 24
Finished Aug 09 05:49:11 PM PDT 24
Peak memory 219168 kb
Host smart-6ef04bd9-a9ee-411c-be0b-be245713d38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832365835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2832365835
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3625686532
Short name T229
Test name
Test status
Simulation time 79570118961 ps
CPU time 205.99 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:52:17 PM PDT 24
Peak memory 242688 kb
Host smart-9fd02d81-8b0c-43d4-bf0f-79d34801d503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625686532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3625686532
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3990918726
Short name T31
Test name
Test status
Simulation time 506408198 ps
CPU time 22.45 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:49:14 PM PDT 24
Peak memory 220028 kb
Host smart-37fe3fc2-517f-4e3f-9447-ef81f87233f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990918726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3990918726
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1750825608
Short name T32
Test name
Test status
Simulation time 175698580 ps
CPU time 10.28 seconds
Started Aug 09 05:48:49 PM PDT 24
Finished Aug 09 05:49:00 PM PDT 24
Peak memory 220056 kb
Host smart-88773f8e-b513-42cc-97a5-5f530efbafcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750825608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1750825608
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1156423153
Short name T163
Test name
Test status
Simulation time 796477380 ps
CPU time 27.44 seconds
Started Aug 09 05:48:51 PM PDT 24
Finished Aug 09 05:49:18 PM PDT 24
Peak memory 220024 kb
Host smart-220c25c1-ee31-480c-ac4b-8d9e1339e7b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156423153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1156423153
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3475024352
Short name T54
Test name
Test status
Simulation time 86473074096 ps
CPU time 1908.84 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 06:20:48 PM PDT 24
Peak memory 246032 kb
Host smart-7c59323d-dae9-42c9-8598-e97cc1095367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475024352 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3475024352
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1876951325
Short name T197
Test name
Test status
Simulation time 2464772866 ps
CPU time 9.98 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 05:49:09 PM PDT 24
Peak memory 219160 kb
Host smart-3b01397f-dd01-4459-9e19-627b3cc17425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876951325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1876951325
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.925584451
Short name T141
Test name
Test status
Simulation time 3225016382 ps
CPU time 212.79 seconds
Started Aug 09 05:49:00 PM PDT 24
Finished Aug 09 05:52:33 PM PDT 24
Peak memory 242628 kb
Host smart-4748f981-d6f8-4138-896e-39261dd86e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925584451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.925584451
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1008073870
Short name T310
Test name
Test status
Simulation time 1376545830 ps
CPU time 19.29 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 05:49:19 PM PDT 24
Peak memory 220024 kb
Host smart-d225a9b5-d6f0-48f7-b036-bca553c6a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008073870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1008073870
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3073156150
Short name T127
Test name
Test status
Simulation time 3953308264 ps
CPU time 16.93 seconds
Started Aug 09 05:48:58 PM PDT 24
Finished Aug 09 05:49:16 PM PDT 24
Peak memory 219904 kb
Host smart-16ff473c-5d00-4efd-ad7f-2e6b1b53b0cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073156150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3073156150
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1075076802
Short name T16
Test name
Test status
Simulation time 576331112 ps
CPU time 31.18 seconds
Started Aug 09 05:48:58 PM PDT 24
Finished Aug 09 05:49:29 PM PDT 24
Peak memory 219952 kb
Host smart-f92bf741-2681-4fb4-ae40-648cb0c54f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075076802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1075076802
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.879372837
Short name T275
Test name
Test status
Simulation time 241205925304 ps
CPU time 4945.45 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 07:11:26 PM PDT 24
Peak memory 264004 kb
Host smart-5750e6de-fa68-4f71-b525-d0ac3f0d1abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879372837 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.879372837
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2432625751
Short name T206
Test name
Test status
Simulation time 537667456 ps
CPU time 9.92 seconds
Started Aug 09 05:49:00 PM PDT 24
Finished Aug 09 05:49:10 PM PDT 24
Peak memory 219092 kb
Host smart-9f768581-1495-4449-b8f4-be1e9476ceb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432625751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2432625751
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3166317921
Short name T49
Test name
Test status
Simulation time 9998048677 ps
CPU time 155.6 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 05:51:35 PM PDT 24
Peak memory 220336 kb
Host smart-d8c727ae-8d4d-4f95-97ba-74f1c122201e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166317921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3166317921
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3265337845
Short name T45
Test name
Test status
Simulation time 3297626980 ps
CPU time 19.86 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 05:49:19 PM PDT 24
Peak memory 220188 kb
Host smart-235f62bc-dd94-483f-adbb-3f433db10b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265337845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3265337845
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.377646434
Short name T307
Test name
Test status
Simulation time 1227605571 ps
CPU time 11.88 seconds
Started Aug 09 05:48:58 PM PDT 24
Finished Aug 09 05:49:10 PM PDT 24
Peak memory 219936 kb
Host smart-c36a1e7e-c8c8-44bb-9862-1177f60072e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377646434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.377646434
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3405634103
Short name T150
Test name
Test status
Simulation time 1397990830 ps
CPU time 27 seconds
Started Aug 09 05:48:59 PM PDT 24
Finished Aug 09 05:49:26 PM PDT 24
Peak memory 219992 kb
Host smart-93c3911a-c542-4ff0-9191-5f1b8d4a0a8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405634103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3405634103
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3039662361
Short name T156
Test name
Test status
Simulation time 576527106 ps
CPU time 9.84 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 05:47:06 PM PDT 24
Peak memory 219100 kb
Host smart-078b488e-b9e6-4d31-af9f-95ed4e447efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039662361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3039662361
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3669028797
Short name T246
Test name
Test status
Simulation time 14351464003 ps
CPU time 204.47 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 05:50:20 PM PDT 24
Peak memory 237592 kb
Host smart-08b4f4a7-dc3b-405c-8bb5-f83b7c232d63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669028797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3669028797
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1556258985
Short name T235
Test name
Test status
Simulation time 2063684428 ps
CPU time 22.99 seconds
Started Aug 09 05:46:55 PM PDT 24
Finished Aug 09 05:47:18 PM PDT 24
Peak memory 220012 kb
Host smart-fc08c1c2-1b0e-4d25-9fb8-5e6912b836c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556258985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1556258985
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2351210747
Short name T167
Test name
Test status
Simulation time 682968377 ps
CPU time 10.83 seconds
Started Aug 09 05:46:51 PM PDT 24
Finished Aug 09 05:47:02 PM PDT 24
Peak memory 220064 kb
Host smart-d01d53cd-61ac-42c6-9044-b1fd504ed9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351210747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2351210747
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3983612891
Short name T227
Test name
Test status
Simulation time 709427269 ps
CPU time 12.27 seconds
Started Aug 09 05:46:50 PM PDT 24
Finished Aug 09 05:47:03 PM PDT 24
Peak memory 220000 kb
Host smart-12667aea-50e0-4137-9115-fd1bed5dbdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983612891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3983612891
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1601267993
Short name T88
Test name
Test status
Simulation time 372268236 ps
CPU time 11.42 seconds
Started Aug 09 05:46:52 PM PDT 24
Finished Aug 09 05:47:03 PM PDT 24
Peak memory 219996 kb
Host smart-5a21abd5-91e8-4679-947a-055470b89b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601267993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1601267993
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3500317128
Short name T283
Test name
Test status
Simulation time 76730209230 ps
CPU time 3137.9 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 06:39:15 PM PDT 24
Peak memory 252752 kb
Host smart-f6f88c82-fe17-4c3e-8b6d-192b594e5523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500317128 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3500317128
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2580072553
Short name T223
Test name
Test status
Simulation time 826379896 ps
CPU time 8.22 seconds
Started Aug 09 05:47:00 PM PDT 24
Finished Aug 09 05:47:08 PM PDT 24
Peak memory 218932 kb
Host smart-4217f66f-5305-4e7f-90c4-87980f9fb08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580072553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2580072553
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3594300616
Short name T48
Test name
Test status
Simulation time 9595165357 ps
CPU time 233.55 seconds
Started Aug 09 05:46:59 PM PDT 24
Finished Aug 09 05:50:52 PM PDT 24
Peak memory 220280 kb
Host smart-669ad94d-ba55-49d7-9e7f-483bc41d7d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594300616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3594300616
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4080040181
Short name T44
Test name
Test status
Simulation time 661248375 ps
CPU time 19 seconds
Started Aug 09 05:46:59 PM PDT 24
Finished Aug 09 05:47:18 PM PDT 24
Peak memory 219988 kb
Host smart-205edc0f-32f7-455b-8234-6dc6065aefb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080040181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4080040181
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.879416562
Short name T11
Test name
Test status
Simulation time 261155646 ps
CPU time 12.46 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 05:47:09 PM PDT 24
Peak memory 220108 kb
Host smart-e6ce7ae7-f106-40f1-b192-b83d80e24e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879416562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.879416562
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1181668177
Short name T190
Test name
Test status
Simulation time 1008850636 ps
CPU time 20.17 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 05:47:17 PM PDT 24
Peak memory 219988 kb
Host smart-10ac68f2-e364-4f28-8d30-280531e18824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181668177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1181668177
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1112171081
Short name T299
Test name
Test status
Simulation time 4309132731 ps
CPU time 27.46 seconds
Started Aug 09 05:46:56 PM PDT 24
Finished Aug 09 05:47:23 PM PDT 24
Peak memory 220132 kb
Host smart-0f5327f7-3bd9-4867-9390-2fca3e3ae3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112171081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1112171081
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4105458025
Short name T173
Test name
Test status
Simulation time 2062912566 ps
CPU time 10.18 seconds
Started Aug 09 05:47:04 PM PDT 24
Finished Aug 09 05:47:14 PM PDT 24
Peak memory 219120 kb
Host smart-5e91f103-b114-4418-9c0e-ea3d8db79b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105458025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4105458025
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3957164337
Short name T137
Test name
Test status
Simulation time 4191266742 ps
CPU time 147.7 seconds
Started Aug 09 05:47:04 PM PDT 24
Finished Aug 09 05:49:32 PM PDT 24
Peak memory 226720 kb
Host smart-238a17f1-0e48-4c49-937d-19c572b9dd4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957164337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3957164337
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1749468801
Short name T293
Test name
Test status
Simulation time 2065980839 ps
CPU time 22.68 seconds
Started Aug 09 05:47:03 PM PDT 24
Finished Aug 09 05:47:26 PM PDT 24
Peak memory 220088 kb
Host smart-9491c071-dd90-45a0-bf1e-8320ea241170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749468801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1749468801
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3437964711
Short name T327
Test name
Test status
Simulation time 2586044724 ps
CPU time 12.55 seconds
Started Aug 09 05:47:03 PM PDT 24
Finished Aug 09 05:47:16 PM PDT 24
Peak memory 220196 kb
Host smart-3037986a-5df3-488a-866c-ab3a222862a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437964711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3437964711
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.671656900
Short name T257
Test name
Test status
Simulation time 180656883 ps
CPU time 10.5 seconds
Started Aug 09 05:46:58 PM PDT 24
Finished Aug 09 05:47:08 PM PDT 24
Peak memory 220032 kb
Host smart-86be7653-33af-42b0-b11f-17641d33c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671656900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.671656900
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2257569669
Short name T253
Test name
Test status
Simulation time 544506468 ps
CPU time 19.34 seconds
Started Aug 09 05:47:03 PM PDT 24
Finished Aug 09 05:47:22 PM PDT 24
Peak memory 220020 kb
Host smart-08f301cb-27eb-4ec7-8117-b7abbdd7de0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257569669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2257569669
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.81742035
Short name T215
Test name
Test status
Simulation time 168403893 ps
CPU time 8.22 seconds
Started Aug 09 05:47:09 PM PDT 24
Finished Aug 09 05:47:18 PM PDT 24
Peak memory 219088 kb
Host smart-d7cb4ba1-077e-42f5-a782-232e9775fc97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81742035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.81742035
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3614582006
Short name T289
Test name
Test status
Simulation time 17651612841 ps
CPU time 240.57 seconds
Started Aug 09 05:47:10 PM PDT 24
Finished Aug 09 05:51:10 PM PDT 24
Peak memory 239760 kb
Host smart-18caa7ec-962a-46c7-b1a1-6e6de61a1449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614582006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3614582006
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.432535325
Short name T134
Test name
Test status
Simulation time 333464174 ps
CPU time 19.86 seconds
Started Aug 09 05:47:11 PM PDT 24
Finished Aug 09 05:47:31 PM PDT 24
Peak memory 220064 kb
Host smart-a2250ca1-a3fc-48b1-89ea-c0a3872b3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432535325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.432535325
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2711706518
Short name T140
Test name
Test status
Simulation time 181726267 ps
CPU time 10.88 seconds
Started Aug 09 05:47:09 PM PDT 24
Finished Aug 09 05:47:20 PM PDT 24
Peak memory 220064 kb
Host smart-e9e4c0c0-72a1-4bc9-bc98-42fa2583f2bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711706518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2711706518
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.109099745
Short name T78
Test name
Test status
Simulation time 1063387374 ps
CPU time 11.96 seconds
Started Aug 09 05:47:10 PM PDT 24
Finished Aug 09 05:47:22 PM PDT 24
Peak memory 220016 kb
Host smart-0b047953-b2ad-45a1-b5b1-32d31ce825cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109099745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.109099745
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.297138274
Short name T216
Test name
Test status
Simulation time 361554079 ps
CPU time 23.16 seconds
Started Aug 09 05:47:10 PM PDT 24
Finished Aug 09 05:47:33 PM PDT 24
Peak memory 219984 kb
Host smart-8f7a1588-769c-438f-875c-5ccc4c74fc3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297138274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.297138274
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.319199207
Short name T52
Test name
Test status
Simulation time 22492660833 ps
CPU time 2923.46 seconds
Started Aug 09 05:47:09 PM PDT 24
Finished Aug 09 06:35:53 PM PDT 24
Peak memory 230556 kb
Host smart-66c76af2-f61e-4daf-860e-d1c9a138827a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319199207 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.319199207
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2864366543
Short name T138
Test name
Test status
Simulation time 249007156 ps
CPU time 8.32 seconds
Started Aug 09 05:47:17 PM PDT 24
Finished Aug 09 05:47:26 PM PDT 24
Peak memory 219116 kb
Host smart-27aaa7c6-b583-482a-9104-5812b6d35913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864366543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2864366543
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.144672959
Short name T249
Test name
Test status
Simulation time 346367272 ps
CPU time 19.75 seconds
Started Aug 09 05:47:18 PM PDT 24
Finished Aug 09 05:47:38 PM PDT 24
Peak memory 220284 kb
Host smart-225f6006-8a61-48bc-8aeb-5838a1407b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144672959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.144672959
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1064793013
Short name T262
Test name
Test status
Simulation time 3949988439 ps
CPU time 17.03 seconds
Started Aug 09 05:47:10 PM PDT 24
Finished Aug 09 05:47:27 PM PDT 24
Peak memory 219856 kb
Host smart-790eb4aa-a0c1-4ffa-ac19-905c7fca73be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064793013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1064793013
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4254066986
Short name T89
Test name
Test status
Simulation time 1585612026 ps
CPU time 12.59 seconds
Started Aug 09 05:47:10 PM PDT 24
Finished Aug 09 05:47:23 PM PDT 24
Peak memory 219996 kb
Host smart-21d60ffa-b88e-4961-8af5-a43b243b2e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254066986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4254066986
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1953620518
Short name T209
Test name
Test status
Simulation time 234516444 ps
CPU time 19.19 seconds
Started Aug 09 05:47:09 PM PDT 24
Finished Aug 09 05:47:29 PM PDT 24
Peak memory 219912 kb
Host smart-20886877-9ae4-45ed-ba14-3c3243c68905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953620518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1953620518
Directory /workspace/9.rom_ctrl_stress_all/latest
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