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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.68 100.00 98.62 97.45 98.37


Total test records in report: 418
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T300 /workspace/coverage/default/34.rom_ctrl_stress_all.2308141527 Aug 10 05:28:37 PM PDT 24 Aug 10 05:28:59 PM PDT 24 3942279663 ps
T301 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1907323512 Aug 10 05:28:45 PM PDT 24 Aug 10 05:31:46 PM PDT 24 9608256681 ps
T302 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2672309059 Aug 10 05:27:38 PM PDT 24 Aug 10 05:27:58 PM PDT 24 346062376 ps
T303 /workspace/coverage/default/8.rom_ctrl_smoke.2426048869 Aug 10 05:27:46 PM PDT 24 Aug 10 05:27:58 PM PDT 24 266604142 ps
T304 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3860749244 Aug 10 05:27:38 PM PDT 24 Aug 10 05:27:49 PM PDT 24 180098456 ps
T305 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3970608516 Aug 10 05:28:45 PM PDT 24 Aug 10 05:29:08 PM PDT 24 596861482 ps
T306 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1726097656 Aug 10 05:28:33 PM PDT 24 Aug 10 05:30:43 PM PDT 24 1815035511 ps
T307 /workspace/coverage/default/45.rom_ctrl_alert_test.1099067667 Aug 10 05:28:43 PM PDT 24 Aug 10 05:28:52 PM PDT 24 167565521 ps
T308 /workspace/coverage/default/6.rom_ctrl_smoke.212434336 Aug 10 05:27:48 PM PDT 24 Aug 10 05:27:59 PM PDT 24 178950390 ps
T309 /workspace/coverage/default/22.rom_ctrl_alert_test.435054367 Aug 10 05:28:14 PM PDT 24 Aug 10 05:28:23 PM PDT 24 719808842 ps
T310 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2948874859 Aug 10 05:28:36 PM PDT 24 Aug 10 05:28:48 PM PDT 24 269730514 ps
T311 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3640456751 Aug 10 05:27:48 PM PDT 24 Aug 10 05:28:01 PM PDT 24 884597729 ps
T312 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2109578245 Aug 10 05:28:24 PM PDT 24 Aug 10 05:28:47 PM PDT 24 1034595206 ps
T313 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2681168198 Aug 10 05:27:56 PM PDT 24 Aug 10 05:28:13 PM PDT 24 995047982 ps
T314 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1099485729 Aug 10 05:28:09 PM PDT 24 Aug 10 05:28:29 PM PDT 24 348104650 ps
T315 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2889588618 Aug 10 05:28:12 PM PDT 24 Aug 10 05:31:42 PM PDT 24 7370997419 ps
T316 /workspace/coverage/default/46.rom_ctrl_stress_all.1700861511 Aug 10 05:28:47 PM PDT 24 Aug 10 05:29:11 PM PDT 24 1583144890 ps
T56 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.352408439 Aug 10 05:28:00 PM PDT 24 Aug 10 06:05:27 PM PDT 24 217008153948 ps
T317 /workspace/coverage/default/28.rom_ctrl_stress_all.3034734837 Aug 10 05:28:21 PM PDT 24 Aug 10 05:28:44 PM PDT 24 1435565542 ps
T318 /workspace/coverage/default/19.rom_ctrl_alert_test.1351867975 Aug 10 05:28:05 PM PDT 24 Aug 10 05:28:20 PM PDT 24 2005926989 ps
T319 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2872692414 Aug 10 05:27:39 PM PDT 24 Aug 10 05:27:59 PM PDT 24 346231239 ps
T320 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1239559693 Aug 10 05:28:45 PM PDT 24 Aug 10 05:33:29 PM PDT 24 4914718033 ps
T321 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4048827630 Aug 10 05:28:34 PM PDT 24 Aug 10 05:28:46 PM PDT 24 535310167 ps
T322 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.918755561 Aug 10 05:28:37 PM PDT 24 Aug 10 05:33:36 PM PDT 24 15780704301 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3974384712 Aug 10 05:29:20 PM PDT 24 Aug 10 05:30:17 PM PDT 24 4286629237 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3304945885 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:13 PM PDT 24 677041294 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.572097072 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:02 PM PDT 24 256639502 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3655775869 Aug 10 05:29:13 PM PDT 24 Aug 10 05:29:22 PM PDT 24 331634660 ps
T57 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3732500917 Aug 10 05:29:10 PM PDT 24 Aug 10 05:29:23 PM PDT 24 651392727 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2533349620 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:02 PM PDT 24 259223002 ps
T323 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1655623419 Aug 10 05:28:50 PM PDT 24 Aug 10 05:29:01 PM PDT 24 258756055 ps
T116 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3215703077 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:18 PM PDT 24 1029677222 ps
T324 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1830833721 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:10 PM PDT 24 1032411047 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1682201675 Aug 10 05:29:00 PM PDT 24 Aug 10 05:31:35 PM PDT 24 1066185307 ps
T325 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1243573142 Aug 10 05:29:20 PM PDT 24 Aug 10 05:29:33 PM PDT 24 3538416512 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.626852909 Aug 10 05:29:04 PM PDT 24 Aug 10 05:29:13 PM PDT 24 176671172 ps
T65 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1958489335 Aug 10 05:29:20 PM PDT 24 Aug 10 05:31:54 PM PDT 24 322624443 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2672971564 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:07 PM PDT 24 678974184 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1564291078 Aug 10 05:29:13 PM PDT 24 Aug 10 05:30:39 PM PDT 24 387387374 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1269535723 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:12 PM PDT 24 257854091 ps
T79 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3874098894 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:20 PM PDT 24 689341438 ps
T326 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3430347934 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:10 PM PDT 24 885875154 ps
T115 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3477775705 Aug 10 05:29:18 PM PDT 24 Aug 10 05:29:30 PM PDT 24 177574043 ps
T327 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1644585384 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:25 PM PDT 24 259772386 ps
T328 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.762681199 Aug 10 05:29:23 PM PDT 24 Aug 10 05:29:36 PM PDT 24 479191900 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2657787773 Aug 10 05:28:55 PM PDT 24 Aug 10 05:29:05 PM PDT 24 672905555 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3557474551 Aug 10 05:29:28 PM PDT 24 Aug 10 05:30:33 PM PDT 24 6094429445 ps
T329 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.523569333 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:10 PM PDT 24 1452134300 ps
T330 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3163249929 Aug 10 05:28:53 PM PDT 24 Aug 10 05:29:01 PM PDT 24 354010133 ps
T82 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1672534331 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:20 PM PDT 24 333463081 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.190670617 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:04 PM PDT 24 173928008 ps
T331 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2585238628 Aug 10 05:29:10 PM PDT 24 Aug 10 05:29:19 PM PDT 24 346942060 ps
T332 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1064066314 Aug 10 05:29:22 PM PDT 24 Aug 10 05:29:37 PM PDT 24 484226581 ps
T333 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1971255076 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:11 PM PDT 24 171381739 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.854918441 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:37 PM PDT 24 692629006 ps
T334 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2810269573 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:09 PM PDT 24 1005672295 ps
T335 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2576631586 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:32 PM PDT 24 289482655 ps
T126 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1659750920 Aug 10 05:29:01 PM PDT 24 Aug 10 05:30:24 PM PDT 24 356714501 ps
T336 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4028843731 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 262573652 ps
T337 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3560285508 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:01 PM PDT 24 191548442 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1108112564 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:08 PM PDT 24 192110679 ps
T338 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1973231732 Aug 10 05:29:20 PM PDT 24 Aug 10 05:29:28 PM PDT 24 292732359 ps
T339 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1576327174 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:37 PM PDT 24 345503233 ps
T340 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2295949818 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:11 PM PDT 24 607835044 ps
T341 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3827667348 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:01 PM PDT 24 1077318523 ps
T342 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3272394025 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:07 PM PDT 24 688976543 ps
T343 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2741177303 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:13 PM PDT 24 260270000 ps
T344 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3179538384 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:32 PM PDT 24 265134817 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2008278436 Aug 10 05:29:01 PM PDT 24 Aug 10 05:31:39 PM PDT 24 4668259907 ps
T345 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3496775282 Aug 10 05:29:13 PM PDT 24 Aug 10 05:29:28 PM PDT 24 1034489455 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.637646568 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:10 PM PDT 24 993252478 ps
T346 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.100473274 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:15 PM PDT 24 1024291679 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3556407155 Aug 10 05:29:03 PM PDT 24 Aug 10 05:29:12 PM PDT 24 253357967 ps
T348 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2048555364 Aug 10 05:28:55 PM PDT 24 Aug 10 05:29:03 PM PDT 24 167674213 ps
T349 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1192888118 Aug 10 05:28:53 PM PDT 24 Aug 10 05:29:03 PM PDT 24 300769550 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1042614811 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:21 PM PDT 24 1032754865 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.744277510 Aug 10 05:29:10 PM PDT 24 Aug 10 05:29:19 PM PDT 24 167514413 ps
T123 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.636922562 Aug 10 05:28:52 PM PDT 24 Aug 10 05:31:24 PM PDT 24 1618632128 ps
T94 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1589099204 Aug 10 05:29:00 PM PDT 24 Aug 10 05:30:06 PM PDT 24 8886054647 ps
T350 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3304429170 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:22 PM PDT 24 266591241 ps
T351 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1827081667 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:11 PM PDT 24 369519341 ps
T352 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.479548486 Aug 10 05:29:21 PM PDT 24 Aug 10 05:30:45 PM PDT 24 1100765251 ps
T353 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1331640687 Aug 10 05:29:29 PM PDT 24 Aug 10 05:30:51 PM PDT 24 321380308 ps
T354 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.172485255 Aug 10 05:29:04 PM PDT 24 Aug 10 05:29:16 PM PDT 24 660338785 ps
T355 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1250651987 Aug 10 05:29:19 PM PDT 24 Aug 10 05:29:31 PM PDT 24 386562376 ps
T129 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1117511231 Aug 10 05:29:11 PM PDT 24 Aug 10 05:30:33 PM PDT 24 1256489038 ps
T127 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4088518017 Aug 10 05:28:52 PM PDT 24 Aug 10 05:30:19 PM PDT 24 2140995582 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3216722463 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:15 PM PDT 24 589777495 ps
T357 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1187203567 Aug 10 05:29:19 PM PDT 24 Aug 10 05:29:32 PM PDT 24 1267801476 ps
T358 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3200078289 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:24 PM PDT 24 263509472 ps
T101 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4157055395 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:57 PM PDT 24 1080355811 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3645902686 Aug 10 05:28:50 PM PDT 24 Aug 10 05:29:28 PM PDT 24 2851397300 ps
T360 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2321346972 Aug 10 05:29:17 PM PDT 24 Aug 10 05:29:25 PM PDT 24 1503850877 ps
T130 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3137291912 Aug 10 05:29:21 PM PDT 24 Aug 10 05:30:46 PM PDT 24 335034223 ps
T361 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4294805767 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 248756844 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.443975218 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:20 PM PDT 24 689804280 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1777877605 Aug 10 05:29:17 PM PDT 24 Aug 10 05:30:13 PM PDT 24 4118717675 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2430713451 Aug 10 05:28:49 PM PDT 24 Aug 10 05:29:03 PM PDT 24 1008391202 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3783392720 Aug 10 05:29:20 PM PDT 24 Aug 10 05:29:35 PM PDT 24 252540815 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1739580643 Aug 10 05:28:48 PM PDT 24 Aug 10 05:29:32 PM PDT 24 2121791022 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4292379598 Aug 10 05:29:14 PM PDT 24 Aug 10 05:29:23 PM PDT 24 1946687911 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2338147079 Aug 10 05:29:20 PM PDT 24 Aug 10 05:29:31 PM PDT 24 273310966 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1403189362 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:32 PM PDT 24 681873904 ps
T128 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.326292224 Aug 10 05:29:28 PM PDT 24 Aug 10 05:32:05 PM PDT 24 1414648549 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2840497369 Aug 10 05:29:10 PM PDT 24 Aug 10 05:29:18 PM PDT 24 569805378 ps
T131 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1002690786 Aug 10 05:29:18 PM PDT 24 Aug 10 05:31:53 PM PDT 24 1612357644 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3438879731 Aug 10 05:28:55 PM PDT 24 Aug 10 05:29:05 PM PDT 24 991696697 ps
T370 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3910060687 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 265907370 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1444084571 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 381500629 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2940430859 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:21 PM PDT 24 1068545568 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2390165795 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:01 PM PDT 24 255414801 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2950428602 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:37 PM PDT 24 5974485969 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1926193715 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:07 PM PDT 24 169556886 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2269871720 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:37 PM PDT 24 170091054 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.918822735 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:01 PM PDT 24 670079924 ps
T99 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3641266391 Aug 10 05:29:09 PM PDT 24 Aug 10 05:29:48 PM PDT 24 720433338 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1598477730 Aug 10 05:29:21 PM PDT 24 Aug 10 05:30:07 PM PDT 24 11248962732 ps
T376 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.106228121 Aug 10 05:29:02 PM PDT 24 Aug 10 05:29:11 PM PDT 24 986489894 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.468484468 Aug 10 05:29:19 PM PDT 24 Aug 10 05:29:29 PM PDT 24 1072410134 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1706470645 Aug 10 05:29:22 PM PDT 24 Aug 10 05:30:07 PM PDT 24 4417399339 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.361339714 Aug 10 05:29:14 PM PDT 24 Aug 10 05:29:59 PM PDT 24 1498093641 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.436057413 Aug 10 05:28:53 PM PDT 24 Aug 10 05:29:02 PM PDT 24 661476726 ps
T124 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3608524704 Aug 10 05:29:11 PM PDT 24 Aug 10 05:31:44 PM PDT 24 844986319 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1965761067 Aug 10 05:29:04 PM PDT 24 Aug 10 05:29:21 PM PDT 24 4131217274 ps
T100 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2294903258 Aug 10 05:29:22 PM PDT 24 Aug 10 05:30:00 PM PDT 24 689719298 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2450238813 Aug 10 05:29:23 PM PDT 24 Aug 10 05:29:31 PM PDT 24 176395004 ps
T125 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1651818590 Aug 10 05:29:11 PM PDT 24 Aug 10 05:31:43 PM PDT 24 363777757 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4119070443 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:09 PM PDT 24 1027246681 ps
T383 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3107115712 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:08 PM PDT 24 581132363 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2484356711 Aug 10 05:29:11 PM PDT 24 Aug 10 05:30:33 PM PDT 24 1539441346 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2820093255 Aug 10 05:29:04 PM PDT 24 Aug 10 05:29:20 PM PDT 24 2172262086 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4192558035 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:09 PM PDT 24 260130012 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2776077021 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:10 PM PDT 24 689226343 ps
T388 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1055108356 Aug 10 05:29:22 PM PDT 24 Aug 10 05:29:31 PM PDT 24 334321413 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2364511887 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:10 PM PDT 24 1030637913 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1175071352 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:27 PM PDT 24 259782316 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.631933110 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 173491210 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1040208242 Aug 10 05:29:14 PM PDT 24 Aug 10 05:30:40 PM PDT 24 20637202658 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1685881212 Aug 10 05:28:52 PM PDT 24 Aug 10 05:29:36 PM PDT 24 1037988384 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4233303081 Aug 10 05:29:20 PM PDT 24 Aug 10 05:30:26 PM PDT 24 1639544984 ps
T132 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.171999057 Aug 10 05:29:02 PM PDT 24 Aug 10 05:31:38 PM PDT 24 1191976793 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.412819485 Aug 10 05:28:51 PM PDT 24 Aug 10 05:29:02 PM PDT 24 539567252 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3426006860 Aug 10 05:29:29 PM PDT 24 Aug 10 05:29:41 PM PDT 24 255860873 ps
T397 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1771704676 Aug 10 05:29:00 PM PDT 24 Aug 10 05:31:39 PM PDT 24 430025977 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3740279599 Aug 10 05:29:03 PM PDT 24 Aug 10 05:29:11 PM PDT 24 692759770 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2717329388 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:09 PM PDT 24 461331811 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2350090015 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:14 PM PDT 24 256575276 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1672039243 Aug 10 05:29:13 PM PDT 24 Aug 10 05:29:57 PM PDT 24 4213711658 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2770856555 Aug 10 05:29:03 PM PDT 24 Aug 10 05:29:13 PM PDT 24 1180851907 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1372728063 Aug 10 05:29:04 PM PDT 24 Aug 10 05:29:13 PM PDT 24 726782401 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4064643722 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:21 PM PDT 24 262472272 ps
T133 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2108431611 Aug 10 05:28:49 PM PDT 24 Aug 10 05:31:28 PM PDT 24 4341301376 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2549830313 Aug 10 05:28:50 PM PDT 24 Aug 10 05:29:00 PM PDT 24 250051887 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1753723833 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:20 PM PDT 24 359904413 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.611686468 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:46 PM PDT 24 4226676830 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2304161823 Aug 10 05:28:55 PM PDT 24 Aug 10 05:29:03 PM PDT 24 169517550 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3066429776 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:55 PM PDT 24 1320612796 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1368125072 Aug 10 05:28:59 PM PDT 24 Aug 10 05:29:13 PM PDT 24 495932436 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3209119493 Aug 10 05:29:18 PM PDT 24 Aug 10 05:29:26 PM PDT 24 2833769424 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3398942171 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:20 PM PDT 24 660988591 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4194159241 Aug 10 05:29:12 PM PDT 24 Aug 10 05:29:20 PM PDT 24 345948084 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2803234887 Aug 10 05:29:21 PM PDT 24 Aug 10 05:29:31 PM PDT 24 1543316509 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.390584413 Aug 10 05:29:00 PM PDT 24 Aug 10 05:29:11 PM PDT 24 992067806 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.203311863 Aug 10 05:28:53 PM PDT 24 Aug 10 05:29:06 PM PDT 24 916321556 ps
T104 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.817962707 Aug 10 05:29:02 PM PDT 24 Aug 10 05:30:08 PM PDT 24 1832910813 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2329867338 Aug 10 05:29:01 PM PDT 24 Aug 10 05:29:11 PM PDT 24 259896771 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1371238589 Aug 10 05:28:48 PM PDT 24 Aug 10 05:28:56 PM PDT 24 331940767 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.821598430 Aug 10 05:29:11 PM PDT 24 Aug 10 05:29:25 PM PDT 24 895712259 ps

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4160028411
Short name T5
Test name
Test status
Simulation time 548427199 ps
CPU time 32.85 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:22 PM PDT 24
Peak memory 219676 kb
Host smart-c7132fb2-3b9b-4a9a-aa40-3b65bd26add2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160028411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4160028411
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1248162517
Short name T13
Test name
Test status
Simulation time 26456778579 ps
CPU time 10662.9 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 08:25:47 PM PDT 24
Peak memory 236544 kb
Host smart-ed7cd4a6-24f5-43b7-8f82-ec2937ac19de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248162517 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1248162517
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.159276191
Short name T1
Test name
Test status
Simulation time 10801621056 ps
CPU time 231.83 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:32:06 PM PDT 24
Peak memory 238548 kb
Host smart-7838fb19-b1b3-45cc-b0c5-f12518a79838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159276191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.159276191
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1958489335
Short name T65
Test name
Test status
Simulation time 322624443 ps
CPU time 153.9 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:31:54 PM PDT 24
Peak memory 214808 kb
Host smart-2a99f9b3-54b5-42aa-a84d-8ae92761ebef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958489335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1958489335
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2344745780
Short name T40
Test name
Test status
Simulation time 12931291895 ps
CPU time 457.79 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:36:15 PM PDT 24
Peak memory 238672 kb
Host smart-1d1fd943-444b-4a17-a3ef-54fa77a6cd20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344745780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2344745780
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2577989558
Short name T12
Test name
Test status
Simulation time 657596431 ps
CPU time 10.53 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:49 PM PDT 24
Peak memory 220132 kb
Host smart-a513d403-2407-4aab-adbf-eab4282f7ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577989558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2577989558
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3169538553
Short name T24
Test name
Test status
Simulation time 352763098 ps
CPU time 226.69 seconds
Started Aug 10 05:27:52 PM PDT 24
Finished Aug 10 05:31:38 PM PDT 24
Peak memory 239968 kb
Host smart-0bcbcb54-f23b-4d3c-90f0-9d3acee5a0c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169538553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3169538553
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2672971564
Short name T78
Test name
Test status
Simulation time 678974184 ps
CPU time 15.66 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:07 PM PDT 24
Peak memory 212860 kb
Host smart-83906898-b438-4bc2-934e-792321c44a2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672971564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2672971564
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3668148156
Short name T75
Test name
Test status
Simulation time 4079601680 ps
CPU time 15.14 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:36 PM PDT 24
Peak memory 219124 kb
Host smart-81741ab6-0ce1-427f-91a4-f26925fe5c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668148156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3668148156
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4088518017
Short name T127
Test name
Test status
Simulation time 2140995582 ps
CPU time 87.24 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:30:19 PM PDT 24
Peak memory 214476 kb
Host smart-fb698f16-fa7b-423d-af11-a6e0cd4ee8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088518017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4088518017
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3958991171
Short name T11
Test name
Test status
Simulation time 4180547793 ps
CPU time 32.83 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:39 PM PDT 24
Peak memory 219440 kb
Host smart-d29d8a90-7588-40ff-980b-9f051f2ef6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958991171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3958991171
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3648447032
Short name T209
Test name
Test status
Simulation time 1981736541 ps
CPU time 22.8 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:20 PM PDT 24
Peak memory 220060 kb
Host smart-b955fc83-268b-4600-ba87-f5020041593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648447032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3648447032
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3240772254
Short name T49
Test name
Test status
Simulation time 3932365941 ps
CPU time 34.1 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 220156 kb
Host smart-4bcaaf3e-a725-4901-8942-135b721f49cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240772254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3240772254
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3557474551
Short name T81
Test name
Test status
Simulation time 6094429445 ps
CPU time 64.68 seconds
Started Aug 10 05:29:28 PM PDT 24
Finished Aug 10 05:30:33 PM PDT 24
Peak memory 215276 kb
Host smart-25cc1579-1953-4631-84b9-b08f01f139aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557474551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3557474551
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.765513227
Short name T63
Test name
Test status
Simulation time 429176089 ps
CPU time 11.8 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:28:10 PM PDT 24
Peak memory 219980 kb
Host smart-c7ab86aa-36a3-4d88-9d6f-5811b11190b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765513227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.765513227
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2108431611
Short name T133
Test name
Test status
Simulation time 4341301376 ps
CPU time 159.42 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:31:28 PM PDT 24
Peak memory 219556 kb
Host smart-a9d69e7d-6e3e-414a-82d5-861de141c8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108431611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2108431611
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1117511231
Short name T129
Test name
Test status
Simulation time 1256489038 ps
CPU time 82.29 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:30:33 PM PDT 24
Peak memory 219504 kb
Host smart-5257a0e9-0dbd-42ca-a216-cbd39b1b0fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117511231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1117511231
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3686380681
Short name T105
Test name
Test status
Simulation time 3529822477 ps
CPU time 38.35 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 220188 kb
Host smart-ec0d0c40-5b3e-40a5-a412-1b9451f70d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686380681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3686380681
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3438879731
Short name T96
Test name
Test status
Simulation time 991696697 ps
CPU time 10.13 seconds
Started Aug 10 05:28:55 PM PDT 24
Finished Aug 10 05:29:05 PM PDT 24
Peak memory 211472 kb
Host smart-aac77750-4d27-4b9c-8f9e-ad30177e46fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438879731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3438879731
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.572097072
Short name T69
Test name
Test status
Simulation time 256639502 ps
CPU time 10.15 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 211356 kb
Host smart-38276909-2af6-4935-b1b7-d86a8b5ea739
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572097072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.572097072
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2810269573
Short name T334
Test name
Test status
Simulation time 1005672295 ps
CPU time 9.59 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:09 PM PDT 24
Peak memory 217724 kb
Host smart-5b9bd1cc-df35-4bb1-8305-91212c67fb6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810269573 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2810269573
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2657787773
Short name T80
Test name
Test status
Simulation time 672905555 ps
CPU time 10.06 seconds
Started Aug 10 05:28:55 PM PDT 24
Finished Aug 10 05:29:05 PM PDT 24
Peak memory 211980 kb
Host smart-aa04dcdf-6362-4715-b09c-2326c3b62ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657787773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2657787773
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.436057413
Short name T379
Test name
Test status
Simulation time 661476726 ps
CPU time 8.01 seconds
Started Aug 10 05:28:53 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 211252 kb
Host smart-5df98721-a17f-4d01-a6bd-e1c38b79e415
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436057413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.436057413
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1371238589
Short name T417
Test name
Test status
Simulation time 331940767 ps
CPU time 7.98 seconds
Started Aug 10 05:28:48 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 211188 kb
Host smart-84298aca-f995-4e3d-a2b1-8abbb26c0185
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371238589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1371238589
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1739580643
Short name T365
Test name
Test status
Simulation time 2121791022 ps
CPU time 43.52 seconds
Started Aug 10 05:28:48 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 213340 kb
Host smart-1441ac55-a436-4f65-9be4-40815a821229
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739580643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1739580643
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.190670617
Short name T83
Test name
Test status
Simulation time 173928008 ps
CPU time 12.01 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:04 PM PDT 24
Peak memory 213176 kb
Host smart-c3ab0b16-6440-4cda-93ae-744a224d2368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190670617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.190670617
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2533349620
Short name T76
Test name
Test status
Simulation time 259223002 ps
CPU time 9.93 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 211316 kb
Host smart-4aa2c872-d07b-45ea-8147-12d80d5492b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533349620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2533349620
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3163249929
Short name T330
Test name
Test status
Simulation time 354010133 ps
CPU time 8.38 seconds
Started Aug 10 05:28:53 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 211456 kb
Host smart-a38949ff-5a13-4ec7-9acd-204430a0f163
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163249929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3163249929
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2430713451
Short name T363
Test name
Test status
Simulation time 1008391202 ps
CPU time 13.56 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 211440 kb
Host smart-54b1de8d-01c3-4d0e-804f-98526abaf47d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430713451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2430713451
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3560285508
Short name T337
Test name
Test status
Simulation time 191548442 ps
CPU time 9.19 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 217772 kb
Host smart-7be05764-1c81-4ddc-9a70-fa7c4e7773aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560285508 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3560285508
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2390165795
Short name T97
Test name
Test status
Simulation time 255414801 ps
CPU time 10 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 211404 kb
Host smart-1a7e0fec-499c-4db9-b02d-c3ec521fbdf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390165795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2390165795
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.918822735
Short name T375
Test name
Test status
Simulation time 670079924 ps
CPU time 9.73 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 211216 kb
Host smart-4209572e-f7e0-430b-9010-bb9078e804dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918822735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.918822735
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1192888118
Short name T349
Test name
Test status
Simulation time 300769550 ps
CPU time 9.93 seconds
Started Aug 10 05:28:53 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 211228 kb
Host smart-6bc03105-97e8-44af-8d95-f5c36e450285
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192888118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1192888118
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1685881212
Short name T393
Test name
Test status
Simulation time 1037988384 ps
CPU time 44.01 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:36 PM PDT 24
Peak memory 214484 kb
Host smart-dcc53194-205b-4297-817d-8e9ce69972d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685881212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1685881212
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3827667348
Short name T341
Test name
Test status
Simulation time 1077318523 ps
CPU time 9.78 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 211932 kb
Host smart-91284a11-8e90-41ee-b452-741426257c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827667348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3827667348
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.203311863
Short name T415
Test name
Test status
Simulation time 916321556 ps
CPU time 12.88 seconds
Started Aug 10 05:28:53 PM PDT 24
Finished Aug 10 05:29:06 PM PDT 24
Peak memory 218308 kb
Host smart-9ed0a96b-f352-45c9-b56e-502b4922431b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203311863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.203311863
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.636922562
Short name T123
Test name
Test status
Simulation time 1618632128 ps
CPU time 152.4 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:31:24 PM PDT 24
Peak memory 213764 kb
Host smart-e5c61559-d541-44e1-954d-7e8a8bec62b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636922562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.636922562
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1753723833
Short name T406
Test name
Test status
Simulation time 359904413 ps
CPU time 9.05 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 216220 kb
Host smart-b624abb8-a2fb-4fed-8c3a-7bcfde040442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753723833 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1753723833
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4064643722
Short name T404
Test name
Test status
Simulation time 262472272 ps
CPU time 10.07 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:21 PM PDT 24
Peak memory 211316 kb
Host smart-81b9e352-ae2c-47a7-ba64-8decd26265b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064643722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4064643722
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.361339714
Short name T378
Test name
Test status
Simulation time 1498093641 ps
CPU time 44.81 seconds
Started Aug 10 05:29:14 PM PDT 24
Finished Aug 10 05:29:59 PM PDT 24
Peak memory 214496 kb
Host smart-5599e4e2-f414-4102-a07e-355696776025
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361339714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.361339714
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3874098894
Short name T79
Test name
Test status
Simulation time 689341438 ps
CPU time 7.99 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 211756 kb
Host smart-1a930e5e-1f17-4985-af8a-739face7223b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874098894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3874098894
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3732500917
Short name T57
Test name
Test status
Simulation time 651392727 ps
CPU time 12.99 seconds
Started Aug 10 05:29:10 PM PDT 24
Finished Aug 10 05:29:23 PM PDT 24
Peak memory 219148 kb
Host smart-b08dc60a-e00a-4e49-a03f-d8506f5d8a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732500917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3732500917
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4292379598
Short name T366
Test name
Test status
Simulation time 1946687911 ps
CPU time 8.67 seconds
Started Aug 10 05:29:14 PM PDT 24
Finished Aug 10 05:29:23 PM PDT 24
Peak memory 216316 kb
Host smart-4a3e9d34-5343-4d1b-bf1c-dcdc9c18f2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292379598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4292379598
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1042614811
Short name T92
Test name
Test status
Simulation time 1032754865 ps
CPU time 9.68 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:21 PM PDT 24
Peak memory 211920 kb
Host smart-12040c2b-0547-48b3-b793-a15a67e4cdbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042614811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1042614811
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1777877605
Short name T95
Test name
Test status
Simulation time 4118717675 ps
CPU time 56.56 seconds
Started Aug 10 05:29:17 PM PDT 24
Finished Aug 10 05:30:13 PM PDT 24
Peak memory 215716 kb
Host smart-8e5c3cb6-91ab-47d2-887b-d1ec6ba30067
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777877605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1777877605
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.821598430
Short name T418
Test name
Test status
Simulation time 895712259 ps
CPU time 13.74 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:25 PM PDT 24
Peak memory 213136 kb
Host smart-2cc0933f-2ff3-4afd-be78-10614f5ee1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821598430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.821598430
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3200078289
Short name T358
Test name
Test status
Simulation time 263509472 ps
CPU time 12.97 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:24 PM PDT 24
Peak memory 218328 kb
Host smart-2a70e6c5-d497-49e5-ae78-bcb1c05ccf8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200078289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3200078289
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1564291078
Short name T66
Test name
Test status
Simulation time 387387374 ps
CPU time 85.54 seconds
Started Aug 10 05:29:13 PM PDT 24
Finished Aug 10 05:30:39 PM PDT 24
Peak memory 213532 kb
Host smart-0fed250a-a033-40fc-8614-e49b2bb5d568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564291078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1564291078
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2940430859
Short name T372
Test name
Test status
Simulation time 1068545568 ps
CPU time 10.32 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:21 PM PDT 24
Peak memory 216548 kb
Host smart-3f84b464-855c-4203-b6d5-f32eca562393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940430859 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2940430859
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.443975218
Short name T362
Test name
Test status
Simulation time 689804280 ps
CPU time 8.15 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 211812 kb
Host smart-219e0459-3602-4fcd-84cb-ceaaea5e5ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443975218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.443975218
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3066429776
Short name T409
Test name
Test status
Simulation time 1320612796 ps
CPU time 44.19 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:55 PM PDT 24
Peak memory 214528 kb
Host smart-3f68ee29-3a72-494b-b2b0-fea3edccd26a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066429776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3066429776
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3398942171
Short name T412
Test name
Test status
Simulation time 660988591 ps
CPU time 8.3 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 212016 kb
Host smart-22f9b1d4-12cc-45cf-8820-96230a39064a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398942171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3398942171
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1644585384
Short name T327
Test name
Test status
Simulation time 259772386 ps
CPU time 12.77 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:25 PM PDT 24
Peak memory 218912 kb
Host smart-99afdf02-05af-491a-8272-dcd734e3cb09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644585384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1644585384
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3608524704
Short name T124
Test name
Test status
Simulation time 844986319 ps
CPU time 152.52 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:31:44 PM PDT 24
Peak memory 219524 kb
Host smart-743ef041-c563-4a61-be23-39820b90d755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608524704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3608524704
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3209119493
Short name T411
Test name
Test status
Simulation time 2833769424 ps
CPU time 8.46 seconds
Started Aug 10 05:29:18 PM PDT 24
Finished Aug 10 05:29:26 PM PDT 24
Peak memory 215752 kb
Host smart-50f24487-ac62-4b91-8022-e9f878f775bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209119493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3209119493
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.744277510
Short name T93
Test name
Test status
Simulation time 167514413 ps
CPU time 8.07 seconds
Started Aug 10 05:29:10 PM PDT 24
Finished Aug 10 05:29:19 PM PDT 24
Peak memory 211620 kb
Host smart-cdfb9727-1f50-4797-af61-d371a24a6b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744277510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.744277510
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3641266391
Short name T99
Test name
Test status
Simulation time 720433338 ps
CPU time 38.32 seconds
Started Aug 10 05:29:09 PM PDT 24
Finished Aug 10 05:29:48 PM PDT 24
Peak memory 215408 kb
Host smart-c5894273-44ca-428a-bdc6-7761d3d8efb8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641266391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3641266391
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2321346972
Short name T360
Test name
Test status
Simulation time 1503850877 ps
CPU time 8.17 seconds
Started Aug 10 05:29:17 PM PDT 24
Finished Aug 10 05:29:25 PM PDT 24
Peak memory 211748 kb
Host smart-9a20cf93-6c64-4a70-a7f5-733660a5170b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321346972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2321346972
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3496775282
Short name T345
Test name
Test status
Simulation time 1034489455 ps
CPU time 15.39 seconds
Started Aug 10 05:29:13 PM PDT 24
Finished Aug 10 05:29:28 PM PDT 24
Peak memory 219056 kb
Host smart-0f85422e-be71-4547-b0b6-58b973d89368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496775282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3496775282
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1651818590
Short name T125
Test name
Test status
Simulation time 363777757 ps
CPU time 152.13 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:31:43 PM PDT 24
Peak memory 214868 kb
Host smart-4df5f72b-03e3-48cf-90a5-d74e842573e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651818590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1651818590
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2576631586
Short name T335
Test name
Test status
Simulation time 289482655 ps
CPU time 10.57 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216156 kb
Host smart-a9dfba20-823d-4986-90cf-af16449b2db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576631586 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2576631586
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1055108356
Short name T388
Test name
Test status
Simulation time 334321413 ps
CPU time 8.09 seconds
Started Aug 10 05:29:22 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 211392 kb
Host smart-07826aea-545e-46d6-b330-629c720d1dce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055108356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1055108356
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1598477730
Short name T102
Test name
Test status
Simulation time 11248962732 ps
CPU time 45.14 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 214388 kb
Host smart-5ca0da12-88ab-4066-be3a-3addb5987923
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598477730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1598477730
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1250651987
Short name T355
Test name
Test status
Simulation time 386562376 ps
CPU time 12.28 seconds
Started Aug 10 05:29:19 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 213264 kb
Host smart-75ecf953-8ee2-4313-821c-7d6277019797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250651987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1250651987
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3426006860
Short name T396
Test name
Test status
Simulation time 255860873 ps
CPU time 12.74 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:41 PM PDT 24
Peak memory 217824 kb
Host smart-af3eb23a-ffff-4559-b9b1-d9958990a442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426006860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3426006860
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1331640687
Short name T353
Test name
Test status
Simulation time 321380308 ps
CPU time 81.58 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:30:51 PM PDT 24
Peak memory 213564 kb
Host smart-9d841962-348d-422b-9a15-63bede530b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331640687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1331640687
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3910060687
Short name T370
Test name
Test status
Simulation time 265907370 ps
CPU time 10.09 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 215896 kb
Host smart-0d624567-9d5b-4a36-84ab-463279476d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910060687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3910060687
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.468484468
Short name T377
Test name
Test status
Simulation time 1072410134 ps
CPU time 9.7 seconds
Started Aug 10 05:29:19 PM PDT 24
Finished Aug 10 05:29:29 PM PDT 24
Peak memory 211472 kb
Host smart-eb816377-b415-49e1-a935-5f3653b35cda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468484468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.468484468
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1706470645
Short name T121
Test name
Test status
Simulation time 4417399339 ps
CPU time 44.68 seconds
Started Aug 10 05:29:22 PM PDT 24
Finished Aug 10 05:30:07 PM PDT 24
Peak memory 214224 kb
Host smart-0cf0f5f8-da95-4836-8d8b-e6e164352051
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706470645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1706470645
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3477775705
Short name T115
Test name
Test status
Simulation time 177574043 ps
CPU time 12.25 seconds
Started Aug 10 05:29:18 PM PDT 24
Finished Aug 10 05:29:30 PM PDT 24
Peak memory 213228 kb
Host smart-db51c467-b02e-4778-a2a8-a3d42827c221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477775705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3477775705
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1187203567
Short name T357
Test name
Test status
Simulation time 1267801476 ps
CPU time 12.27 seconds
Started Aug 10 05:29:19 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 218292 kb
Host smart-24b90539-ed5a-4b21-a03b-e3a122678ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187203567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1187203567
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3137291912
Short name T130
Test name
Test status
Simulation time 335034223 ps
CPU time 84.48 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:30:46 PM PDT 24
Peak memory 214280 kb
Host smart-6a48cc23-1c9e-4e03-9e32-8cdb34f1124b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137291912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3137291912
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.631933110
Short name T391
Test name
Test status
Simulation time 173491210 ps
CPU time 8.9 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 217596 kb
Host smart-631070fb-6054-497b-bace-4fc382172989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631933110 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.631933110
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2803234887
Short name T103
Test name
Test status
Simulation time 1543316509 ps
CPU time 9.42 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 211936 kb
Host smart-83bd863d-6ada-4891-a54f-76cd1083a3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803234887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2803234887
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3974384712
Short name T67
Test name
Test status
Simulation time 4286629237 ps
CPU time 56.47 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:30:17 PM PDT 24
Peak memory 215260 kb
Host smart-eb29209c-f227-4c07-b1c1-dd1db0be2e9f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974384712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3974384712
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1576327174
Short name T339
Test name
Test status
Simulation time 345503233 ps
CPU time 8.47 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 212172 kb
Host smart-3e7b988f-8a66-4f58-8a81-d3f4dc77a029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576327174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1576327174
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1243573142
Short name T325
Test name
Test status
Simulation time 3538416512 ps
CPU time 12.81 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:29:33 PM PDT 24
Peak memory 218028 kb
Host smart-340e2927-5015-4ea2-9f31-e93e4596bf59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243573142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1243573142
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1403189362
Short name T368
Test name
Test status
Simulation time 681873904 ps
CPU time 10.15 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 214612 kb
Host smart-c6b84083-2a59-4b65-b46b-afb2c9217e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403189362 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1403189362
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1973231732
Short name T338
Test name
Test status
Simulation time 292732359 ps
CPU time 8.04 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:29:28 PM PDT 24
Peak memory 211312 kb
Host smart-b04cf416-3b9a-4d0a-b93e-512ff077c3ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973231732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1973231732
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4233303081
Short name T394
Test name
Test status
Simulation time 1639544984 ps
CPU time 65.63 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:30:26 PM PDT 24
Peak memory 214500 kb
Host smart-d8fbd5db-3f92-49ac-8a84-b2f3c05d7458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233303081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4233303081
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4028843731
Short name T336
Test name
Test status
Simulation time 262573652 ps
CPU time 10.17 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 212272 kb
Host smart-6f250409-3182-4251-bf99-3e8890d5ce36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028843731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4028843731
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.762681199
Short name T328
Test name
Test status
Simulation time 479191900 ps
CPU time 13.33 seconds
Started Aug 10 05:29:23 PM PDT 24
Finished Aug 10 05:29:36 PM PDT 24
Peak memory 218164 kb
Host smart-8a898d07-e9d5-42ad-baea-3a457a9977c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762681199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.762681199
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.326292224
Short name T128
Test name
Test status
Simulation time 1414648549 ps
CPU time 156.45 seconds
Started Aug 10 05:29:28 PM PDT 24
Finished Aug 10 05:32:05 PM PDT 24
Peak memory 219532 kb
Host smart-98df5d7e-2d53-4106-b3d4-90e8f1db284d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326292224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.326292224
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3179538384
Short name T344
Test name
Test status
Simulation time 265134817 ps
CPU time 10.43 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:32 PM PDT 24
Peak memory 216764 kb
Host smart-c2d076bd-82a6-4361-b068-4b0fcb46c4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179538384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3179538384
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2450238813
Short name T381
Test name
Test status
Simulation time 176395004 ps
CPU time 8.25 seconds
Started Aug 10 05:29:23 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 211468 kb
Host smart-5e953fac-ea77-489a-8f43-6f2933897f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450238813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2450238813
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1444084571
Short name T371
Test name
Test status
Simulation time 381500629 ps
CPU time 9.89 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 211852 kb
Host smart-f93acb0c-4020-4648-8dca-a55ef39d3eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444084571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1444084571
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1064066314
Short name T332
Test name
Test status
Simulation time 484226581 ps
CPU time 15.08 seconds
Started Aug 10 05:29:22 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 218332 kb
Host smart-04dfc1fe-2ae1-420b-89bd-d715fbf99a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064066314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1064066314
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1002690786
Short name T131
Test name
Test status
Simulation time 1612357644 ps
CPU time 154.99 seconds
Started Aug 10 05:29:18 PM PDT 24
Finished Aug 10 05:31:53 PM PDT 24
Peak memory 219476 kb
Host smart-aa2021c6-127f-4cb2-bdff-d844e0bd1d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002690786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1002690786
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2338147079
Short name T367
Test name
Test status
Simulation time 273310966 ps
CPU time 10.61 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 216792 kb
Host smart-aa0f38a9-da3a-4973-9566-301159f145af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338147079 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2338147079
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4294805767
Short name T361
Test name
Test status
Simulation time 248756844 ps
CPU time 9.91 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:29:31 PM PDT 24
Peak memory 211324 kb
Host smart-74cb09a5-2df6-427b-bf05-5f0a039f6e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294805767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4294805767
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2294903258
Short name T100
Test name
Test status
Simulation time 689719298 ps
CPU time 37.66 seconds
Started Aug 10 05:29:22 PM PDT 24
Finished Aug 10 05:30:00 PM PDT 24
Peak memory 214488 kb
Host smart-b89acd0b-e3e7-4f9a-b81f-21fca3dcc315
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294903258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2294903258
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2269871720
Short name T374
Test name
Test status
Simulation time 170091054 ps
CPU time 8.18 seconds
Started Aug 10 05:29:29 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 212116 kb
Host smart-8eb72fa2-9650-423f-a19c-395158a530b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269871720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2269871720
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3783392720
Short name T364
Test name
Test status
Simulation time 252540815 ps
CPU time 14.67 seconds
Started Aug 10 05:29:20 PM PDT 24
Finished Aug 10 05:29:35 PM PDT 24
Peak memory 218032 kb
Host smart-1c461243-cfbc-431d-b6e6-19b9de272483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783392720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3783392720
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.479548486
Short name T352
Test name
Test status
Simulation time 1100765251 ps
CPU time 83.13 seconds
Started Aug 10 05:29:21 PM PDT 24
Finished Aug 10 05:30:45 PM PDT 24
Peak memory 219308 kb
Host smart-0ba3b017-281f-44c5-991b-704270984b30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479548486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.479548486
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4119070443
Short name T382
Test name
Test status
Simulation time 1027246681 ps
CPU time 9.65 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:09 PM PDT 24
Peak memory 211532 kb
Host smart-67e65189-0ed6-4e56-9df7-4be6e2b9e224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119070443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4119070443
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1655623419
Short name T323
Test name
Test status
Simulation time 258756055 ps
CPU time 10.25 seconds
Started Aug 10 05:28:50 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 211312 kb
Host smart-e17d54f1-178d-410e-b7b6-c12d086b703c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655623419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1655623419
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1108112564
Short name T90
Test name
Test status
Simulation time 192110679 ps
CPU time 15.79 seconds
Started Aug 10 05:28:52 PM PDT 24
Finished Aug 10 05:29:08 PM PDT 24
Peak memory 212480 kb
Host smart-6ce8015e-f534-4ee8-bf91-84c1a955d01d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108112564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1108112564
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.412819485
Short name T395
Test name
Test status
Simulation time 539567252 ps
CPU time 10.88 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 217800 kb
Host smart-10aff022-87aa-4f48-99a1-616d180b978d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412819485 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.412819485
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3272394025
Short name T342
Test name
Test status
Simulation time 688976543 ps
CPU time 8.07 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:07 PM PDT 24
Peak memory 211692 kb
Host smart-5ac352aa-d257-46a4-bdc2-75b7f29f46b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272394025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3272394025
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2549830313
Short name T405
Test name
Test status
Simulation time 250051887 ps
CPU time 9.74 seconds
Started Aug 10 05:28:50 PM PDT 24
Finished Aug 10 05:29:00 PM PDT 24
Peak memory 211144 kb
Host smart-8ca9cbc8-171e-404a-a024-e20fd0e184a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549830313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2549830313
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2304161823
Short name T408
Test name
Test status
Simulation time 169517550 ps
CPU time 8.28 seconds
Started Aug 10 05:28:55 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 211388 kb
Host smart-e7770ac6-79a2-4a7f-8e31-2c545929d815
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304161823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2304161823
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2950428602
Short name T98
Test name
Test status
Simulation time 5974485969 ps
CPU time 45.78 seconds
Started Aug 10 05:28:51 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 215556 kb
Host smart-e48c73e5-c169-4400-9ce4-503a0b59c7d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950428602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2950428602
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2048555364
Short name T348
Test name
Test status
Simulation time 167674213 ps
CPU time 8.28 seconds
Started Aug 10 05:28:55 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 212224 kb
Host smart-b1c3c43a-0c38-4296-b698-e626efdc90b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048555364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2048555364
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1368125072
Short name T410
Test name
Test status
Simulation time 495932436 ps
CPU time 14.1 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 217640 kb
Host smart-1cf78978-f5e0-4b8d-a7f0-7fa7416c8b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368125072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1368125072
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2364511887
Short name T389
Test name
Test status
Simulation time 1030637913 ps
CPU time 9.34 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211284 kb
Host smart-305d817e-9c35-432b-83cc-aca35310d6f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364511887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2364511887
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1926193715
Short name T373
Test name
Test status
Simulation time 169556886 ps
CPU time 8.23 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:07 PM PDT 24
Peak memory 211304 kb
Host smart-93092d88-1696-444c-80b1-90b774636855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926193715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1926193715
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3304945885
Short name T68
Test name
Test status
Simulation time 677041294 ps
CPU time 12 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 211192 kb
Host smart-69a29139-5bef-457c-8275-d1fadac8985a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304945885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3304945885
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2820093255
Short name T385
Test name
Test status
Simulation time 2172262086 ps
CPU time 16.13 seconds
Started Aug 10 05:29:04 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 218648 kb
Host smart-44d101cc-aecf-48e7-994a-942d5c27ffea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820093255 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2820093255
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3556407155
Short name T347
Test name
Test status
Simulation time 253357967 ps
CPU time 9.59 seconds
Started Aug 10 05:29:03 PM PDT 24
Finished Aug 10 05:29:12 PM PDT 24
Peak memory 211828 kb
Host smart-098676c7-98fe-4fce-8e39-fc772bd8f979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556407155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3556407155
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.523569333
Short name T329
Test name
Test status
Simulation time 1452134300 ps
CPU time 9.9 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211232 kb
Host smart-dd33c221-05dd-4f1f-bc71-cfa2f883e143
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523569333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.523569333
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1830833721
Short name T324
Test name
Test status
Simulation time 1032411047 ps
CPU time 10.06 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211216 kb
Host smart-e957518f-46fb-414a-b3eb-320ff8d6558d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830833721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1830833721
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3645902686
Short name T359
Test name
Test status
Simulation time 2851397300 ps
CPU time 37.6 seconds
Started Aug 10 05:28:50 PM PDT 24
Finished Aug 10 05:29:28 PM PDT 24
Peak memory 214508 kb
Host smart-4eb43c2b-675e-43da-86d5-3388f4cb90cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645902686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3645902686
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2741177303
Short name T343
Test name
Test status
Simulation time 260270000 ps
CPU time 10.14 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 212128 kb
Host smart-526d7e38-74b2-4ab5-8cbb-6cef2e9f768f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741177303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2741177303
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3216722463
Short name T356
Test name
Test status
Simulation time 589777495 ps
CPU time 13.71 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:15 PM PDT 24
Peak memory 218288 kb
Host smart-1efa1c5e-7bb7-4e5b-bce9-9763c145f392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216722463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3216722463
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.171999057
Short name T132
Test name
Test status
Simulation time 1191976793 ps
CPU time 154.98 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:31:38 PM PDT 24
Peak memory 214652 kb
Host smart-eb7b3831-edf4-41a9-83b5-c167f2b89534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171999057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.171999057
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.637646568
Short name T91
Test name
Test status
Simulation time 993252478 ps
CPU time 10.1 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211576 kb
Host smart-b2753fb1-0a72-44b7-afd6-aa666e4874e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637646568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.637646568
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1269535723
Short name T117
Test name
Test status
Simulation time 257854091 ps
CPU time 9.88 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:12 PM PDT 24
Peak memory 211324 kb
Host smart-4594c1ac-d4d2-4d8b-b778-66b732323634
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269535723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1269535723
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3215703077
Short name T116
Test name
Test status
Simulation time 1029677222 ps
CPU time 18.32 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:18 PM PDT 24
Peak memory 212388 kb
Host smart-46388f65-a7a7-41bd-9937-8e677066bfb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215703077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3215703077
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.390584413
Short name T414
Test name
Test status
Simulation time 992067806 ps
CPU time 10.86 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 218160 kb
Host smart-41c58ad0-3bb5-4e14-bafc-a936cf244c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390584413 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.390584413
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3740279599
Short name T398
Test name
Test status
Simulation time 692759770 ps
CPU time 8.24 seconds
Started Aug 10 05:29:03 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 211836 kb
Host smart-6cd38a98-019e-4fa6-a485-e69c0256818f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740279599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3740279599
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3430347934
Short name T326
Test name
Test status
Simulation time 885875154 ps
CPU time 9.73 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211228 kb
Host smart-45bde214-a24f-42eb-bf12-3c7cb0a07548
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430347934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3430347934
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2329867338
Short name T416
Test name
Test status
Simulation time 259896771 ps
CPU time 9.73 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 211228 kb
Host smart-0538bcce-b700-4ccd-80e0-05a56842c92c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329867338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2329867338
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.854918441
Short name T84
Test name
Test status
Simulation time 692629006 ps
CPU time 37.49 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:37 PM PDT 24
Peak memory 214476 kb
Host smart-228db2e9-1ad6-4968-87c1-89e8be640cbe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854918441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.854918441
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2295949818
Short name T340
Test name
Test status
Simulation time 607835044 ps
CPU time 11.54 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 213068 kb
Host smart-a684ddfd-58b5-418b-b10c-97f8b68c9b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295949818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2295949818
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2350090015
Short name T400
Test name
Test status
Simulation time 256575276 ps
CPU time 13.05 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:14 PM PDT 24
Peak memory 217960 kb
Host smart-b47e6b58-4d8f-44e3-8967-38a52994bc14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350090015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2350090015
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1659750920
Short name T126
Test name
Test status
Simulation time 356714501 ps
CPU time 82.84 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:30:24 PM PDT 24
Peak memory 214528 kb
Host smart-bdcc0e86-cb93-408c-9bb9-cfeafa87a90c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659750920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1659750920
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1827081667
Short name T351
Test name
Test status
Simulation time 369519341 ps
CPU time 8.71 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 216712 kb
Host smart-88e07cdb-686d-4029-9e99-aff51a69ae8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827081667 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1827081667
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2776077021
Short name T387
Test name
Test status
Simulation time 689226343 ps
CPU time 8.48 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:10 PM PDT 24
Peak memory 211928 kb
Host smart-67537dda-450b-493e-a63d-8f9065339047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776077021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2776077021
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4157055395
Short name T101
Test name
Test status
Simulation time 1080355811 ps
CPU time 57.88 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 214540 kb
Host smart-13bdaf5c-5fe0-4f91-948a-4e0b39a6f3c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157055395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4157055395
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4192558035
Short name T386
Test name
Test status
Simulation time 260130012 ps
CPU time 9.94 seconds
Started Aug 10 05:28:59 PM PDT 24
Finished Aug 10 05:29:09 PM PDT 24
Peak memory 211784 kb
Host smart-191feb94-1ae9-4545-9723-35fc81e827e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192558035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4192558035
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.100473274
Short name T346
Test name
Test status
Simulation time 1024291679 ps
CPU time 13.57 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:15 PM PDT 24
Peak memory 218168 kb
Host smart-5cf0931a-1785-4962-8c95-7c90cf3ecfb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100473274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.100473274
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2008278436
Short name T122
Test name
Test status
Simulation time 4668259907 ps
CPU time 157.8 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:31:39 PM PDT 24
Peak memory 215152 kb
Host smart-73de63ae-63f6-4a48-8653-46cfb6e3fb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008278436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2008278436
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3107115712
Short name T383
Test name
Test status
Simulation time 581132363 ps
CPU time 8.48 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:08 PM PDT 24
Peak memory 216804 kb
Host smart-1835eaf1-39c8-4225-97ab-56ef5580d69a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107115712 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3107115712
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2770856555
Short name T402
Test name
Test status
Simulation time 1180851907 ps
CPU time 10 seconds
Started Aug 10 05:29:03 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 211948 kb
Host smart-cd5d36a1-7877-4a94-9398-4af6d43c9995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770856555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2770856555
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.817962707
Short name T104
Test name
Test status
Simulation time 1832910813 ps
CPU time 65.7 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:30:08 PM PDT 24
Peak memory 215512 kb
Host smart-956d0fd1-5e70-4520-af87-351e193a345f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817962707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.817962707
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.106228121
Short name T376
Test name
Test status
Simulation time 986489894 ps
CPU time 9.74 seconds
Started Aug 10 05:29:02 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 212100 kb
Host smart-d31fb765-3eab-4e82-86e9-ae3f6287334f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106228121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.106228121
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1965761067
Short name T380
Test name
Test status
Simulation time 4131217274 ps
CPU time 17.57 seconds
Started Aug 10 05:29:04 PM PDT 24
Finished Aug 10 05:29:21 PM PDT 24
Peak memory 219192 kb
Host smart-a04bbe13-2b35-420d-abd0-ffceedabaf45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965761067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1965761067
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1682201675
Short name T64
Test name
Test status
Simulation time 1066185307 ps
CPU time 154.42 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:31:35 PM PDT 24
Peak memory 215924 kb
Host smart-e567a3d2-dcce-476e-a8f6-ceaa43a1ce26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682201675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1682201675
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1372728063
Short name T403
Test name
Test status
Simulation time 726782401 ps
CPU time 8.82 seconds
Started Aug 10 05:29:04 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 215568 kb
Host smart-d81a3659-20f5-4a0b-953c-7006a0862e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372728063 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1372728063
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2717329388
Short name T399
Test name
Test status
Simulation time 461331811 ps
CPU time 8.03 seconds
Started Aug 10 05:29:01 PM PDT 24
Finished Aug 10 05:29:09 PM PDT 24
Peak memory 211564 kb
Host smart-9643da6a-d5d7-4058-ac53-de5282023806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717329388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2717329388
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1589099204
Short name T94
Test name
Test status
Simulation time 8886054647 ps
CPU time 66.05 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:30:06 PM PDT 24
Peak memory 216652 kb
Host smart-c98eacb9-5d23-47a5-9d89-6b5fb2f9766e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589099204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1589099204
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.626852909
Short name T77
Test name
Test status
Simulation time 176671172 ps
CPU time 8.52 seconds
Started Aug 10 05:29:04 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 212176 kb
Host smart-be59a992-1b09-4170-a023-3620f699a54f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626852909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.626852909
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.172485255
Short name T354
Test name
Test status
Simulation time 660338785 ps
CPU time 12.63 seconds
Started Aug 10 05:29:04 PM PDT 24
Finished Aug 10 05:29:16 PM PDT 24
Peak memory 218252 kb
Host smart-49ab6ccc-5c16-4183-99da-497aad3ae1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172485255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.172485255
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1771704676
Short name T397
Test name
Test status
Simulation time 430025977 ps
CPU time 158.65 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:31:39 PM PDT 24
Peak memory 219532 kb
Host smart-2f1e3c2a-7673-4f95-b5cf-580fa7ade495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771704676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1771704676
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2585238628
Short name T331
Test name
Test status
Simulation time 346942060 ps
CPU time 9.11 seconds
Started Aug 10 05:29:10 PM PDT 24
Finished Aug 10 05:29:19 PM PDT 24
Peak memory 216500 kb
Host smart-56e93bd0-8d14-4189-b070-f6097ce34cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585238628 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2585238628
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4194159241
Short name T413
Test name
Test status
Simulation time 345948084 ps
CPU time 8 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 211416 kb
Host smart-96042f2f-3da8-4bed-987f-b1838b3ad459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194159241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4194159241
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.611686468
Short name T407
Test name
Test status
Simulation time 4226676830 ps
CPU time 45.34 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:46 PM PDT 24
Peak memory 214672 kb
Host smart-44dfb06a-65d7-4270-aa7f-0d09aca2b051
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611686468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.611686468
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3655775869
Short name T114
Test name
Test status
Simulation time 331634660 ps
CPU time 8.4 seconds
Started Aug 10 05:29:13 PM PDT 24
Finished Aug 10 05:29:22 PM PDT 24
Peak memory 211752 kb
Host smart-ce46e9a6-b695-4132-8b7e-3a91df599624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655775869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3655775869
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1971255076
Short name T333
Test name
Test status
Simulation time 171381739 ps
CPU time 11.04 seconds
Started Aug 10 05:29:00 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 217956 kb
Host smart-2af283be-5695-4516-b31e-cea30cd655ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971255076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1971255076
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2484356711
Short name T384
Test name
Test status
Simulation time 1539441346 ps
CPU time 81.37 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:30:33 PM PDT 24
Peak memory 214424 kb
Host smart-42aa51d6-1065-40f7-a84c-e8c5dd00894d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484356711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2484356711
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3304429170
Short name T350
Test name
Test status
Simulation time 266591241 ps
CPU time 11.21 seconds
Started Aug 10 05:29:11 PM PDT 24
Finished Aug 10 05:29:22 PM PDT 24
Peak memory 217768 kb
Host smart-fd9af0cb-3558-48cd-b8f3-f6625beb56fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304429170 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3304429170
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1672534331
Short name T82
Test name
Test status
Simulation time 333463081 ps
CPU time 8.22 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 211468 kb
Host smart-ac60f70c-783a-4a94-8175-5da4ba8d5998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672534331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1672534331
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1672039243
Short name T401
Test name
Test status
Simulation time 4213711658 ps
CPU time 44.05 seconds
Started Aug 10 05:29:13 PM PDT 24
Finished Aug 10 05:29:57 PM PDT 24
Peak memory 214492 kb
Host smart-3e70c17f-f97f-473a-86c4-df271977e1b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672039243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1672039243
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2840497369
Short name T369
Test name
Test status
Simulation time 569805378 ps
CPU time 8.18 seconds
Started Aug 10 05:29:10 PM PDT 24
Finished Aug 10 05:29:18 PM PDT 24
Peak memory 211868 kb
Host smart-a0687dda-9b4c-413e-ba01-4628c488c17d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840497369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2840497369
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1175071352
Short name T390
Test name
Test status
Simulation time 259782316 ps
CPU time 14.88 seconds
Started Aug 10 05:29:12 PM PDT 24
Finished Aug 10 05:29:27 PM PDT 24
Peak memory 218288 kb
Host smart-9721553c-d282-40e9-ac59-cbe518ae0b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175071352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1175071352
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1040208242
Short name T392
Test name
Test status
Simulation time 20637202658 ps
CPU time 86.32 seconds
Started Aug 10 05:29:14 PM PDT 24
Finished Aug 10 05:30:40 PM PDT 24
Peak memory 213780 kb
Host smart-d42bf518-4e11-415c-b091-f4a3816623ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040208242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1040208242
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2528044912
Short name T239
Test name
Test status
Simulation time 506978299 ps
CPU time 10.08 seconds
Started Aug 10 05:27:42 PM PDT 24
Finished Aug 10 05:27:52 PM PDT 24
Peak memory 219116 kb
Host smart-16cdee62-af9d-4adb-be08-52524136c52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528044912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2528044912
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2629801974
Short name T42
Test name
Test status
Simulation time 2210289724 ps
CPU time 158.71 seconds
Started Aug 10 05:27:38 PM PDT 24
Finished Aug 10 05:30:17 PM PDT 24
Peak memory 226084 kb
Host smart-baa145f8-b43d-4d6b-94b4-5b5039b9b06e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629801974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2629801974
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2672309059
Short name T302
Test name
Test status
Simulation time 346062376 ps
CPU time 19.47 seconds
Started Aug 10 05:27:38 PM PDT 24
Finished Aug 10 05:27:58 PM PDT 24
Peak memory 220060 kb
Host smart-c8dce9f2-bfb5-47f5-8143-5278285e3570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672309059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2672309059
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2855030574
Short name T141
Test name
Test status
Simulation time 1590476065 ps
CPU time 11.96 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:51 PM PDT 24
Peak memory 220104 kb
Host smart-5c9bed2a-3dc6-4e77-ab89-a0eca5484bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855030574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2855030574
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1347690095
Short name T25
Test name
Test status
Simulation time 362996691 ps
CPU time 226.33 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:31:26 PM PDT 24
Peak memory 239804 kb
Host smart-a90b2552-bd81-441f-aa8e-b38340328128
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347690095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1347690095
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3545290037
Short name T195
Test name
Test status
Simulation time 271354396 ps
CPU time 11.79 seconds
Started Aug 10 05:27:38 PM PDT 24
Finished Aug 10 05:27:50 PM PDT 24
Peak memory 219880 kb
Host smart-d72466e6-4714-46d0-a447-49361c95901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545290037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3545290037
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2615767842
Short name T85
Test name
Test status
Simulation time 519236749 ps
CPU time 28.17 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:28:07 PM PDT 24
Peak memory 220080 kb
Host smart-981cc3c3-ae27-4bf0-ad9c-caa2fe4c976a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615767842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2615767842
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2974548221
Short name T173
Test name
Test status
Simulation time 507707233 ps
CPU time 10.18 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:50 PM PDT 24
Peak memory 219112 kb
Host smart-de1c4954-3903-4358-b526-27567d9a7b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974548221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2974548221
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.626397951
Short name T45
Test name
Test status
Simulation time 9123434511 ps
CPU time 436.8 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:34:58 PM PDT 24
Peak memory 227312 kb
Host smart-6ef4c35e-e0dc-4246-bd44-c9641a988eac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626397951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.626397951
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2872692414
Short name T319
Test name
Test status
Simulation time 346231239 ps
CPU time 19.35 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:59 PM PDT 24
Peak memory 220068 kb
Host smart-08b425ef-61f1-4aea-8b11-75e260f7ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872692414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2872692414
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3860749244
Short name T304
Test name
Test status
Simulation time 180098456 ps
CPU time 10.59 seconds
Started Aug 10 05:27:38 PM PDT 24
Finished Aug 10 05:27:49 PM PDT 24
Peak memory 220036 kb
Host smart-cb42e57b-d7e5-4e5c-9a12-777c9c0d2230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860749244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3860749244
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.945320459
Short name T23
Test name
Test status
Simulation time 604765941 ps
CPU time 119.61 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:29:40 PM PDT 24
Peak memory 239340 kb
Host smart-ac5963f0-9cba-46c6-a1ff-e51855887ded
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945320459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.945320459
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1832216986
Short name T194
Test name
Test status
Simulation time 1084037650 ps
CPU time 25.65 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 220088 kb
Host smart-c0a101a3-9ff5-4721-add7-a1eb9d386635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832216986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1832216986
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.240971436
Short name T53
Test name
Test status
Simulation time 31957201124 ps
CPU time 313.94 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:32:55 PM PDT 24
Peak memory 230400 kb
Host smart-9bd944a1-59bd-4df4-bc6f-97e41260608f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240971436 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.240971436
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1056474654
Short name T26
Test name
Test status
Simulation time 474087689 ps
CPU time 8.32 seconds
Started Aug 10 05:27:58 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 219220 kb
Host smart-71df15ee-09eb-4ce1-89cc-5a4da0619ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056474654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1056474654
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1170582458
Short name T41
Test name
Test status
Simulation time 9669885171 ps
CPU time 279.84 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:32:39 PM PDT 24
Peak memory 225892 kb
Host smart-e34f649f-7774-4904-aba7-437b2bbb4320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170582458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1170582458
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3739673190
Short name T289
Test name
Test status
Simulation time 1505637462 ps
CPU time 18.78 seconds
Started Aug 10 05:28:02 PM PDT 24
Finished Aug 10 05:28:21 PM PDT 24
Peak memory 220068 kb
Host smart-5272b009-a67b-4dbe-b5e5-75b94b3e713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739673190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3739673190
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2085689635
Short name T7
Test name
Test status
Simulation time 733311147 ps
CPU time 10.5 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 219924 kb
Host smart-a02c4384-c26c-42be-b1a7-7728d465cffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2085689635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2085689635
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1314809961
Short name T296
Test name
Test status
Simulation time 799615346 ps
CPU time 15.19 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:12 PM PDT 24
Peak memory 219992 kb
Host smart-c16107f3-092c-4c99-8b1f-cb1f2e831ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314809961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1314809961
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2719683605
Short name T14
Test name
Test status
Simulation time 251868541 ps
CPU time 10.24 seconds
Started Aug 10 05:28:00 PM PDT 24
Finished Aug 10 05:28:10 PM PDT 24
Peak memory 219140 kb
Host smart-a664d227-d33d-422c-b320-dd43b2ef0c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719683605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2719683605
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1023819701
Short name T19
Test name
Test status
Simulation time 18880316288 ps
CPU time 185.6 seconds
Started Aug 10 05:28:02 PM PDT 24
Finished Aug 10 05:31:08 PM PDT 24
Peak memory 240252 kb
Host smart-6a576ad6-1f01-49c0-948c-2c277f3f0e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023819701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1023819701
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2368800447
Short name T257
Test name
Test status
Simulation time 346755281 ps
CPU time 19.51 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:17 PM PDT 24
Peak memory 220100 kb
Host smart-d1b0c4c2-6a9b-429b-808b-d420479bdf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368800447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2368800447
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3695640067
Short name T200
Test name
Test status
Simulation time 9043512823 ps
CPU time 17.5 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:15 PM PDT 24
Peak memory 220056 kb
Host smart-0e0c9a03-b5be-4cf0-b2b6-7a799df793ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695640067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3695640067
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1982546443
Short name T199
Test name
Test status
Simulation time 1080643424 ps
CPU time 28 seconds
Started Aug 10 05:27:58 PM PDT 24
Finished Aug 10 05:28:26 PM PDT 24
Peak memory 220060 kb
Host smart-73b90078-7a20-4391-84d7-d85f33aed7a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982546443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1982546443
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4108060054
Short name T73
Test name
Test status
Simulation time 354991430 ps
CPU time 10.37 seconds
Started Aug 10 05:27:55 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 219200 kb
Host smart-236c9d49-2b4a-486d-ba67-4569224b5f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108060054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4108060054
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1631638058
Short name T228
Test name
Test status
Simulation time 20071828595 ps
CPU time 243.98 seconds
Started Aug 10 05:28:00 PM PDT 24
Finished Aug 10 05:32:04 PM PDT 24
Peak memory 237152 kb
Host smart-394fef54-022a-44d1-8345-e41f84f12d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631638058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1631638058
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2681168198
Short name T313
Test name
Test status
Simulation time 995047982 ps
CPU time 16.26 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:13 PM PDT 24
Peak memory 220060 kb
Host smart-818de2e7-1646-4656-b62b-e1b22911235f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681168198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2681168198
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3756202998
Short name T264
Test name
Test status
Simulation time 3157475967 ps
CPU time 24.25 seconds
Started Aug 10 05:27:55 PM PDT 24
Finished Aug 10 05:28:19 PM PDT 24
Peak memory 220140 kb
Host smart-3a3a7dd6-a018-447a-ade4-c2e93a77611f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756202998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3756202998
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.352408439
Short name T56
Test name
Test status
Simulation time 217008153948 ps
CPU time 2246.89 seconds
Started Aug 10 05:28:00 PM PDT 24
Finished Aug 10 06:05:27 PM PDT 24
Peak memory 246324 kb
Host smart-7607936b-aa38-44bf-a9c8-4c02581f7323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352408439 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.352408439
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3401612196
Short name T21
Test name
Test status
Simulation time 261430689 ps
CPU time 9.8 seconds
Started Aug 10 05:27:55 PM PDT 24
Finished Aug 10 05:28:05 PM PDT 24
Peak memory 219836 kb
Host smart-962cba2b-fef9-4a3c-b1b4-dd5813ec1a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401612196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3401612196
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2814497787
Short name T37
Test name
Test status
Simulation time 154752247609 ps
CPU time 461.12 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:35:40 PM PDT 24
Peak memory 226244 kb
Host smart-4eacd69a-66ad-4831-91c3-dc8e30f1deca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814497787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2814497787
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1368664712
Short name T179
Test name
Test status
Simulation time 1973272628 ps
CPU time 32.25 seconds
Started Aug 10 05:28:02 PM PDT 24
Finished Aug 10 05:28:34 PM PDT 24
Peak memory 219332 kb
Host smart-6a8e0470-da51-4227-b444-e289231e408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368664712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1368664712
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1976274205
Short name T191
Test name
Test status
Simulation time 571674101 ps
CPU time 19.87 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:17 PM PDT 24
Peak memory 220064 kb
Host smart-123c625f-f725-4d90-a846-976356e6b79b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976274205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1976274205
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.737581425
Short name T250
Test name
Test status
Simulation time 992604910 ps
CPU time 10.32 seconds
Started Aug 10 05:27:58 PM PDT 24
Finished Aug 10 05:28:08 PM PDT 24
Peak memory 219140 kb
Host smart-f4f481f3-41ef-4140-94f4-be9e0237f141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737581425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.737581425
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3016188008
Short name T197
Test name
Test status
Simulation time 5860488692 ps
CPU time 325.65 seconds
Started Aug 10 05:27:58 PM PDT 24
Finished Aug 10 05:33:23 PM PDT 24
Peak memory 238988 kb
Host smart-6d659b92-5506-46ee-a112-0f96cb1387b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016188008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3016188008
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1851376574
Short name T235
Test name
Test status
Simulation time 990465308 ps
CPU time 22.93 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:28:22 PM PDT 24
Peak memory 220104 kb
Host smart-03430867-0d3c-44af-bd4b-bc736a9a5fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851376574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1851376574
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1488626340
Short name T137
Test name
Test status
Simulation time 731805408 ps
CPU time 10.79 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 220112 kb
Host smart-e1efc461-05ae-49f8-b42b-fc187833d7a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488626340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1488626340
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.213797138
Short name T10
Test name
Test status
Simulation time 292443845 ps
CPU time 16.31 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:13 PM PDT 24
Peak memory 220124 kb
Host smart-cf73531a-53ae-488f-a6e6-b27b4721e184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213797138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.213797138
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2887084071
Short name T148
Test name
Test status
Simulation time 687748075 ps
CPU time 8.1 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 05:28:12 PM PDT 24
Peak memory 219188 kb
Host smart-acddc02e-d5b7-4b90-a04c-e85537b9631c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887084071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2887084071
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3374086083
Short name T273
Test name
Test status
Simulation time 4347388980 ps
CPU time 232.4 seconds
Started Aug 10 05:27:58 PM PDT 24
Finished Aug 10 05:31:51 PM PDT 24
Peak memory 242268 kb
Host smart-44083a98-7fb0-4d45-af7c-6a157b03dfff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374086083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3374086083
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3529461631
Short name T107
Test name
Test status
Simulation time 342262588 ps
CPU time 19.18 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:28:18 PM PDT 24
Peak memory 220100 kb
Host smart-ea99cbb1-1893-4f26-a939-63181deb9c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529461631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3529461631
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3130770049
Short name T30
Test name
Test status
Simulation time 340430617 ps
CPU time 10.75 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:28:10 PM PDT 24
Peak memory 220092 kb
Host smart-c766d865-aa21-40d3-9bac-ff1437ee7340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130770049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3130770049
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2017838106
Short name T18
Test name
Test status
Simulation time 3141876963 ps
CPU time 37.08 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:33 PM PDT 24
Peak memory 220112 kb
Host smart-ffa02765-042d-4a91-9fc7-97a51452689d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017838106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2017838106
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2466816539
Short name T74
Test name
Test status
Simulation time 2365627771 ps
CPU time 8.69 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:14 PM PDT 24
Peak memory 219404 kb
Host smart-0e8ee5a3-ce5e-4fff-beeb-be894f40fc5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466816539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2466816539
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2410749865
Short name T181
Test name
Test status
Simulation time 12324547772 ps
CPU time 261.63 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 05:32:26 PM PDT 24
Peak memory 238624 kb
Host smart-e1c4bc53-0f9e-439c-9db2-13c439fe8dfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410749865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2410749865
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1099485729
Short name T314
Test name
Test status
Simulation time 348104650 ps
CPU time 19.69 seconds
Started Aug 10 05:28:09 PM PDT 24
Finished Aug 10 05:28:29 PM PDT 24
Peak memory 220060 kb
Host smart-205c7a1f-ea8d-4993-a95f-d5cfb792100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099485729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1099485729
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2843782948
Short name T140
Test name
Test status
Simulation time 823099071 ps
CPU time 11.71 seconds
Started Aug 10 05:28:07 PM PDT 24
Finished Aug 10 05:28:18 PM PDT 24
Peak memory 220116 kb
Host smart-3a1a90af-a41b-4cef-9295-b039219aee7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843782948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2843782948
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.580420654
Short name T139
Test name
Test status
Simulation time 1524478568 ps
CPU time 20.15 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:25 PM PDT 24
Peak memory 219972 kb
Host smart-3a25db69-2296-43e9-8dee-90dd54f38d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580420654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.580420654
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3500980757
Short name T266
Test name
Test status
Simulation time 174312518 ps
CPU time 8.26 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:13 PM PDT 24
Peak memory 219124 kb
Host smart-d4596800-ba2b-4eb9-a058-65d992cc1e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500980757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3500980757
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.61597334
Short name T31
Test name
Test status
Simulation time 4053254470 ps
CPU time 228.04 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:31:53 PM PDT 24
Peak memory 238556 kb
Host smart-d64edc90-07ca-4881-b142-d6a9dda62823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61597334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_co
rrupt_sig_fatal_chk.61597334
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2901998192
Short name T158
Test name
Test status
Simulation time 775336399 ps
CPU time 22.17 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:28 PM PDT 24
Peak memory 220116 kb
Host smart-95a8e431-6a4b-4c99-aaf1-4eff6d1367a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901998192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2901998192
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3725758193
Short name T247
Test name
Test status
Simulation time 260989609 ps
CPU time 12.42 seconds
Started Aug 10 05:28:09 PM PDT 24
Finished Aug 10 05:28:22 PM PDT 24
Peak memory 220084 kb
Host smart-0f7d53e5-aa02-48c7-84f4-59d87b85cfb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725758193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3725758193
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1702978130
Short name T201
Test name
Test status
Simulation time 858986547 ps
CPU time 22.31 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:29 PM PDT 24
Peak memory 219128 kb
Host smart-ae5b9b55-5e3f-4c04-85b1-09a21fc0d552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702978130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1702978130
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.119171315
Short name T215
Test name
Test status
Simulation time 660574478 ps
CPU time 8.58 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:14 PM PDT 24
Peak memory 219160 kb
Host smart-36e2d8b4-83c6-4090-8730-38b3a71a5d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119171315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.119171315
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.946609078
Short name T260
Test name
Test status
Simulation time 13251242056 ps
CPU time 353.78 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 05:33:57 PM PDT 24
Peak memory 240388 kb
Host smart-81bfeb53-ec1d-425e-9555-deedcaa0829e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946609078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.946609078
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2846269386
Short name T287
Test name
Test status
Simulation time 1975591309 ps
CPU time 31.79 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:37 PM PDT 24
Peak memory 219432 kb
Host smart-db83db81-82df-41ab-84a6-1c782a3576d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846269386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2846269386
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.600729251
Short name T270
Test name
Test status
Simulation time 259092839 ps
CPU time 11.94 seconds
Started Aug 10 05:28:07 PM PDT 24
Finished Aug 10 05:28:19 PM PDT 24
Peak memory 219972 kb
Host smart-a73d1004-3e19-4dd7-8c65-e4f63e5748ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600729251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.600729251
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.147883961
Short name T220
Test name
Test status
Simulation time 1074295588 ps
CPU time 34.64 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:41 PM PDT 24
Peak memory 220088 kb
Host smart-880fee14-f9f4-4d87-ab3f-6dde460e14e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147883961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.147883961
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1351867975
Short name T318
Test name
Test status
Simulation time 2005926989 ps
CPU time 14.87 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:20 PM PDT 24
Peak memory 219156 kb
Host smart-c2c19416-08d7-4178-a650-3ec3deb7ea4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351867975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1351867975
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.88950171
Short name T39
Test name
Test status
Simulation time 15428253418 ps
CPU time 247.2 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:32:14 PM PDT 24
Peak memory 220368 kb
Host smart-57638ab8-cede-4b9d-9844-558aaaabb03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88950171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co
rrupt_sig_fatal_chk.88950171
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.685479784
Short name T155
Test name
Test status
Simulation time 1576146557 ps
CPU time 19.54 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:26 PM PDT 24
Peak memory 220116 kb
Host smart-eb3c8544-04c8-431e-8364-3ec7b983304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685479784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.685479784
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.268226094
Short name T134
Test name
Test status
Simulation time 990745643 ps
CPU time 17.43 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:24 PM PDT 24
Peak memory 220136 kb
Host smart-931bf29d-38c7-41c1-af31-90b857331a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268226094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.268226094
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4172157387
Short name T218
Test name
Test status
Simulation time 362263872 ps
CPU time 17.55 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:24 PM PDT 24
Peak memory 220056 kb
Host smart-ff4bb952-9f3e-4c71-aa7e-35bcba77a27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172157387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4172157387
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3027015126
Short name T217
Test name
Test status
Simulation time 169037251 ps
CPU time 8.36 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:27:49 PM PDT 24
Peak memory 219128 kb
Host smart-72d404c9-69cb-4f93-80d6-b02f355ea4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027015126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3027015126
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2512798165
Short name T277
Test name
Test status
Simulation time 3479469557 ps
CPU time 174.15 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:30:33 PM PDT 24
Peak memory 234564 kb
Host smart-92b6fbb9-0e00-498c-805f-29214db4af0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512798165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2512798165
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2206477841
Short name T157
Test name
Test status
Simulation time 552790790 ps
CPU time 23.11 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:28:05 PM PDT 24
Peak memory 220160 kb
Host smart-543260d5-8ce8-4757-8ecd-a89a7511058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206477841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2206477841
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.284020931
Short name T282
Test name
Test status
Simulation time 5188360912 ps
CPU time 12.93 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:52 PM PDT 24
Peak memory 220208 kb
Host smart-6bcfa2a3-aa7d-44a9-badb-6007b99ee424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284020931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.284020931
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1835620024
Short name T28
Test name
Test status
Simulation time 714204713 ps
CPU time 220.04 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:31:20 PM PDT 24
Peak memory 239456 kb
Host smart-65d1ad9e-621f-4839-a1e5-bc2238950451
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835620024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1835620024
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2665500373
Short name T165
Test name
Test status
Simulation time 350138681 ps
CPU time 10.9 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:27:51 PM PDT 24
Peak memory 220128 kb
Host smart-1b28310a-a3bb-474a-8bb4-5f758aa7d9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665500373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2665500373
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.445919687
Short name T15
Test name
Test status
Simulation time 11189451867 ps
CPU time 38.13 seconds
Started Aug 10 05:27:38 PM PDT 24
Finished Aug 10 05:28:16 PM PDT 24
Peak memory 220284 kb
Host smart-7bb1dd9f-698c-47b6-9dd5-083112123e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445919687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.445919687
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2318429295
Short name T35
Test name
Test status
Simulation time 2741615359 ps
CPU time 8.33 seconds
Started Aug 10 05:28:05 PM PDT 24
Finished Aug 10 05:28:13 PM PDT 24
Peak memory 219104 kb
Host smart-20a770e4-bdc5-42a0-b2ac-8afb275aada8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318429295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2318429295
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2862958205
Short name T275
Test name
Test status
Simulation time 11951690158 ps
CPU time 165.5 seconds
Started Aug 10 05:28:10 PM PDT 24
Finished Aug 10 05:30:55 PM PDT 24
Peak memory 237344 kb
Host smart-41b4c1aa-d519-4b2d-90d0-bfcaa9ee7a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862958205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2862958205
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3648324767
Short name T119
Test name
Test status
Simulation time 185477028 ps
CPU time 10.62 seconds
Started Aug 10 05:28:09 PM PDT 24
Finished Aug 10 05:28:20 PM PDT 24
Peak memory 220084 kb
Host smart-7751e699-0fc7-47de-bcfc-8e3342587676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648324767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3648324767
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3860028527
Short name T174
Test name
Test status
Simulation time 2303877280 ps
CPU time 23.7 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 05:28:28 PM PDT 24
Peak memory 220128 kb
Host smart-713d7e81-05ae-40b6-bf66-80770b4035d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860028527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3860028527
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.998031303
Short name T268
Test name
Test status
Simulation time 485902476 ps
CPU time 10.06 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:24 PM PDT 24
Peak memory 219080 kb
Host smart-0406c330-28ff-4a61-9f41-d36cfa7593b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998031303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.998031303
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3012841915
Short name T246
Test name
Test status
Simulation time 3925976117 ps
CPU time 231.39 seconds
Started Aug 10 05:28:09 PM PDT 24
Finished Aug 10 05:32:00 PM PDT 24
Peak memory 238480 kb
Host smart-1521232d-9138-4951-8e28-25d163d51e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012841915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3012841915
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3671187367
Short name T151
Test name
Test status
Simulation time 2057581799 ps
CPU time 22.9 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:36 PM PDT 24
Peak memory 220104 kb
Host smart-a9fcef19-a3b1-408a-94be-20fcca0b047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671187367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3671187367
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3738600339
Short name T161
Test name
Test status
Simulation time 825066186 ps
CPU time 10.2 seconds
Started Aug 10 05:28:04 PM PDT 24
Finished Aug 10 05:28:14 PM PDT 24
Peak memory 220072 kb
Host smart-ea88119c-2c30-490e-be83-ebc0eed9acb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738600339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3738600339
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3322180670
Short name T162
Test name
Test status
Simulation time 169618636 ps
CPU time 13.51 seconds
Started Aug 10 05:28:06 PM PDT 24
Finished Aug 10 05:28:20 PM PDT 24
Peak memory 219672 kb
Host smart-8fe6c3bb-e18e-4421-97d6-4288796835bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322180670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3322180670
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.435054367
Short name T309
Test name
Test status
Simulation time 719808842 ps
CPU time 8.53 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:23 PM PDT 24
Peak memory 218080 kb
Host smart-4bd1ce19-f54a-45e0-8132-e495f18d3a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435054367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.435054367
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2305444781
Short name T22
Test name
Test status
Simulation time 5483250848 ps
CPU time 340.28 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:33:53 PM PDT 24
Peak memory 231296 kb
Host smart-449bfd5f-c732-46f6-9552-e00ad834f217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305444781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2305444781
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1165589721
Short name T222
Test name
Test status
Simulation time 346086332 ps
CPU time 19.38 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:34 PM PDT 24
Peak memory 220100 kb
Host smart-825c44f6-e29e-4855-884e-12b05ddc710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165589721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1165589721
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.106844722
Short name T187
Test name
Test status
Simulation time 272674352 ps
CPU time 12.3 seconds
Started Aug 10 05:28:15 PM PDT 24
Finished Aug 10 05:28:27 PM PDT 24
Peak memory 220068 kb
Host smart-621bcb1b-2621-4d3f-bda9-9112006bb662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106844722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.106844722
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.568289909
Short name T171
Test name
Test status
Simulation time 526112902 ps
CPU time 24.86 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:38 PM PDT 24
Peak memory 220064 kb
Host smart-bcb1d3e5-6a16-474b-ac56-3485ebcd0c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568289909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.568289909
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.608618405
Short name T241
Test name
Test status
Simulation time 507088219 ps
CPU time 10.12 seconds
Started Aug 10 05:28:12 PM PDT 24
Finished Aug 10 05:28:22 PM PDT 24
Peak memory 219268 kb
Host smart-c133d9ef-800d-4e2d-ad61-0f303bf16da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608618405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.608618405
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1448894477
Short name T111
Test name
Test status
Simulation time 2193438928 ps
CPU time 147.69 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:30:41 PM PDT 24
Peak memory 220284 kb
Host smart-a3977228-5280-4419-bf47-09b27474da6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448894477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1448894477
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.628768131
Short name T210
Test name
Test status
Simulation time 1033584799 ps
CPU time 22.19 seconds
Started Aug 10 05:28:16 PM PDT 24
Finished Aug 10 05:28:38 PM PDT 24
Peak memory 220100 kb
Host smart-d16c2a0e-886c-4c75-a8c7-f2824dda1864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628768131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.628768131
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2739541573
Short name T253
Test name
Test status
Simulation time 726404464 ps
CPU time 10.48 seconds
Started Aug 10 05:28:15 PM PDT 24
Finished Aug 10 05:28:26 PM PDT 24
Peak memory 220048 kb
Host smart-818b3b4e-1747-4968-ab12-4cd6a8b7bb5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739541573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2739541573
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2543382064
Short name T38
Test name
Test status
Simulation time 274425499 ps
CPU time 16.27 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:30 PM PDT 24
Peak memory 220016 kb
Host smart-4c4bf68d-fec8-4944-8ee7-a15ab4a39153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543382064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2543382064
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3513623436
Short name T51
Test name
Test status
Simulation time 60172633001 ps
CPU time 2439.67 seconds
Started Aug 10 05:28:17 PM PDT 24
Finished Aug 10 06:08:57 PM PDT 24
Peak memory 246688 kb
Host smart-1d723e61-affd-4144-bc47-379b4379d8cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513623436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3513623436
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2639391190
Short name T216
Test name
Test status
Simulation time 746142815 ps
CPU time 10.18 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:24 PM PDT 24
Peak memory 219172 kb
Host smart-2e134b5e-bacb-4dd4-9ba2-1dc0680d3061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639391190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2639391190
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2943533590
Short name T298
Test name
Test status
Simulation time 2237668856 ps
CPU time 140.28 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:30:34 PM PDT 24
Peak memory 239772 kb
Host smart-62a2ed33-704d-43dd-8f6f-48d03c03f140
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943533590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2943533590
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.445515486
Short name T9
Test name
Test status
Simulation time 1376090545 ps
CPU time 19.14 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:32 PM PDT 24
Peak memory 220084 kb
Host smart-21b4a098-da05-4d2c-b125-49be437ae876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445515486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.445515486
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.908081953
Short name T118
Test name
Test status
Simulation time 1601962155 ps
CPU time 12.02 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:26 PM PDT 24
Peak memory 219976 kb
Host smart-c986a27f-0d62-4b7b-9d52-baeac7069b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908081953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.908081953
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2644371377
Short name T166
Test name
Test status
Simulation time 278632097 ps
CPU time 13.03 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:28 PM PDT 24
Peak memory 220060 kb
Host smart-ddeba079-7712-4260-8aa0-e0eee9e9613c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644371377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2644371377
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3631795404
Short name T198
Test name
Test status
Simulation time 250109793 ps
CPU time 10.13 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:24 PM PDT 24
Peak memory 219164 kb
Host smart-7ee9ff57-bca7-43c9-95f3-e7a958759781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631795404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3631795404
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3469323389
Short name T149
Test name
Test status
Simulation time 990102163 ps
CPU time 22.87 seconds
Started Aug 10 05:28:16 PM PDT 24
Finished Aug 10 05:28:39 PM PDT 24
Peak memory 220084 kb
Host smart-2ed59646-e046-4cd1-8124-c4bff403cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469323389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3469323389
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2203928780
Short name T33
Test name
Test status
Simulation time 259661079 ps
CPU time 12.11 seconds
Started Aug 10 05:28:14 PM PDT 24
Finished Aug 10 05:28:26 PM PDT 24
Peak memory 220028 kb
Host smart-52262068-d8ab-45eb-9094-d549c8ee1ebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203928780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2203928780
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1497886728
Short name T59
Test name
Test status
Simulation time 374738082 ps
CPU time 24.21 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:37 PM PDT 24
Peak memory 220004 kb
Host smart-14cd7a95-b268-4a8b-9367-88cae961ce8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497886728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1497886728
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.661927241
Short name T110
Test name
Test status
Simulation time 3101599319 ps
CPU time 9.99 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:33 PM PDT 24
Peak memory 219320 kb
Host smart-3643cf32-cde2-4fe5-b5a9-934a877288f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661927241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.661927241
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2889588618
Short name T315
Test name
Test status
Simulation time 7370997419 ps
CPU time 210.46 seconds
Started Aug 10 05:28:12 PM PDT 24
Finished Aug 10 05:31:42 PM PDT 24
Peak memory 241676 kb
Host smart-c746ba72-e5c4-40b8-9520-864172d1faa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889588618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2889588618
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3096626625
Short name T142
Test name
Test status
Simulation time 1086573401 ps
CPU time 22.87 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 220132 kb
Host smart-f5fd2605-7723-4b58-8d4a-963ef6b2a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096626625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3096626625
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.823609193
Short name T8
Test name
Test status
Simulation time 2564648830 ps
CPU time 12.09 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:25 PM PDT 24
Peak memory 220236 kb
Host smart-221c2127-9259-4a11-adfd-059812bc9424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823609193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.823609193
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2312427065
Short name T147
Test name
Test status
Simulation time 544532517 ps
CPU time 31.63 seconds
Started Aug 10 05:28:13 PM PDT 24
Finished Aug 10 05:28:45 PM PDT 24
Peak memory 220208 kb
Host smart-9fccb975-3147-4fa4-ab4c-4e2edb66a493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312427065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2312427065
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.76159905
Short name T245
Test name
Test status
Simulation time 249918346 ps
CPU time 10.33 seconds
Started Aug 10 05:28:20 PM PDT 24
Finished Aug 10 05:28:31 PM PDT 24
Peak memory 218732 kb
Host smart-d997edb6-9eb0-439e-9bfc-70b9a6759be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76159905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.76159905
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2831741342
Short name T50
Test name
Test status
Simulation time 7320394871 ps
CPU time 105.5 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:30:09 PM PDT 24
Peak memory 220340 kb
Host smart-82397ef8-2e63-4fc9-94c2-0ac09ef9552d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831741342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2831741342
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1925170448
Short name T172
Test name
Test status
Simulation time 1321307598 ps
CPU time 19.45 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:28:41 PM PDT 24
Peak memory 220056 kb
Host smart-4b1d6240-9859-4fd1-ae94-9dafa731ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925170448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1925170448
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1301219532
Short name T178
Test name
Test status
Simulation time 264376360 ps
CPU time 11.91 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:28:34 PM PDT 24
Peak memory 220076 kb
Host smart-87c47a06-8e8f-44a5-a985-c57652b94b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301219532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1301219532
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3176986948
Short name T279
Test name
Test status
Simulation time 4134362477 ps
CPU time 50.69 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:29:14 PM PDT 24
Peak memory 220452 kb
Host smart-83e1d3c3-2eef-4509-b04b-7e472a3bd791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176986948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3176986948
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.721794577
Short name T252
Test name
Test status
Simulation time 517732855 ps
CPU time 10.07 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:33 PM PDT 24
Peak memory 219128 kb
Host smart-c9b3de24-82e1-4511-9588-d85e668bbecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721794577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.721794577
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2633758873
Short name T143
Test name
Test status
Simulation time 2616869425 ps
CPU time 169.38 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:31:12 PM PDT 24
Peak memory 239476 kb
Host smart-03d7e8f1-2a21-46d3-bc96-5a7c8e547ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633758873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2633758873
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3938204870
Short name T61
Test name
Test status
Simulation time 5519972716 ps
CPU time 19.24 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:41 PM PDT 24
Peak memory 220204 kb
Host smart-3b0b44fc-178a-411d-b392-f49346e15d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938204870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3938204870
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2585854210
Short name T295
Test name
Test status
Simulation time 830176626 ps
CPU time 12.5 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:34 PM PDT 24
Peak memory 220088 kb
Host smart-31855052-df4a-4d8e-8bef-a381f9564057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585854210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2585854210
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3034734837
Short name T317
Test name
Test status
Simulation time 1435565542 ps
CPU time 23.57 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:44 PM PDT 24
Peak memory 220048 kb
Host smart-40a9d429-0e3b-4039-a680-02687a0d5ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034734837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3034734837
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2040174210
Short name T52
Test name
Test status
Simulation time 42310020712 ps
CPU time 1697.21 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:56:39 PM PDT 24
Peak memory 244816 kb
Host smart-cf9dab84-3f21-4927-acd4-93056008efc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040174210 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2040174210
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2900316904
Short name T208
Test name
Test status
Simulation time 773695674 ps
CPU time 10.37 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:28:33 PM PDT 24
Peak memory 219212 kb
Host smart-4e3758a1-a3aa-44b1-9391-766d5f342002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900316904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2900316904
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.267313958
Short name T258
Test name
Test status
Simulation time 5462693771 ps
CPU time 174.73 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:31:17 PM PDT 24
Peak memory 231996 kb
Host smart-3ef28287-4dbc-4b46-9052-86037e39f24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267313958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.267313958
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3366641804
Short name T285
Test name
Test status
Simulation time 2471753832 ps
CPU time 23.19 seconds
Started Aug 10 05:28:24 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 220200 kb
Host smart-74b81b9e-340b-40ee-9028-5c1b865cf946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366641804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3366641804
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.488156063
Short name T120
Test name
Test status
Simulation time 794733337 ps
CPU time 10.77 seconds
Started Aug 10 05:28:26 PM PDT 24
Finished Aug 10 05:28:37 PM PDT 24
Peak memory 220088 kb
Host smart-a73dba9d-d4bc-4fbf-af4e-ab69b1ef2ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488156063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.488156063
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2516218510
Short name T164
Test name
Test status
Simulation time 2305820935 ps
CPU time 15.93 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:28:38 PM PDT 24
Peak memory 220104 kb
Host smart-f12a4799-fd12-40fe-aa22-5757f105d208
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516218510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2516218510
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3988277711
Short name T167
Test name
Test status
Simulation time 992139766 ps
CPU time 10.16 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:27:51 PM PDT 24
Peak memory 219104 kb
Host smart-b37cb156-5076-41c7-8a3c-01ff5283ca97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988277711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3988277711
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1086790756
Short name T109
Test name
Test status
Simulation time 3317347538 ps
CPU time 266.83 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:32:07 PM PDT 24
Peak memory 238432 kb
Host smart-109f0a9e-c2f5-43ac-bd2f-6bb8a980092c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086790756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1086790756
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4147822054
Short name T153
Test name
Test status
Simulation time 516517880 ps
CPU time 22.56 seconds
Started Aug 10 05:27:44 PM PDT 24
Finished Aug 10 05:28:07 PM PDT 24
Peak memory 220100 kb
Host smart-c4a113ea-84f7-42c3-a636-043925620575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147822054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4147822054
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3070299240
Short name T243
Test name
Test status
Simulation time 1286523610 ps
CPU time 12.28 seconds
Started Aug 10 05:27:42 PM PDT 24
Finished Aug 10 05:27:54 PM PDT 24
Peak memory 220048 kb
Host smart-6a0eaa7b-ee2e-47c6-a38c-418be7698e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070299240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3070299240
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.830690818
Short name T29
Test name
Test status
Simulation time 835750616 ps
CPU time 225.15 seconds
Started Aug 10 05:27:41 PM PDT 24
Finished Aug 10 05:31:26 PM PDT 24
Peak memory 235676 kb
Host smart-6f230f0a-3695-41ce-a073-bd9d2e7be13d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830690818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.830690818
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.199267368
Short name T58
Test name
Test status
Simulation time 179164528 ps
CPU time 10.46 seconds
Started Aug 10 05:27:44 PM PDT 24
Finished Aug 10 05:27:55 PM PDT 24
Peak memory 220112 kb
Host smart-6f0b99eb-e11b-4c92-9c52-4d995c663c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199267368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.199267368
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3534176666
Short name T229
Test name
Test status
Simulation time 751523475 ps
CPU time 45.34 seconds
Started Aug 10 05:27:44 PM PDT 24
Finished Aug 10 05:28:30 PM PDT 24
Peak memory 220784 kb
Host smart-5eb44639-dabb-407c-a890-167ae5dee9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534176666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3534176666
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3196665102
Short name T177
Test name
Test status
Simulation time 167729148 ps
CPU time 8.63 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:32 PM PDT 24
Peak memory 218568 kb
Host smart-3a2b982a-e94d-4ba6-b5ac-40cd16b0fddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196665102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3196665102
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3920547660
Short name T251
Test name
Test status
Simulation time 10001390618 ps
CPU time 185.58 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:31:27 PM PDT 24
Peak memory 243096 kb
Host smart-7508f51b-3821-4028-a8b5-9d21306729a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920547660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3920547660
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3046822426
Short name T27
Test name
Test status
Simulation time 519497112 ps
CPU time 22.84 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 220128 kb
Host smart-0b258486-801e-4757-97e5-f41ec5c6b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046822426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3046822426
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2826812627
Short name T204
Test name
Test status
Simulation time 370663439 ps
CPU time 10.44 seconds
Started Aug 10 05:28:23 PM PDT 24
Finished Aug 10 05:28:34 PM PDT 24
Peak memory 220108 kb
Host smart-7412f257-b8d7-48fa-a5c6-29c17ff2d76d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826812627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2826812627
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3388030545
Short name T255
Test name
Test status
Simulation time 802434205 ps
CPU time 11.19 seconds
Started Aug 10 05:28:24 PM PDT 24
Finished Aug 10 05:28:35 PM PDT 24
Peak memory 220016 kb
Host smart-2091363f-63c5-4ccc-9d9a-70ee18c4064e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388030545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3388030545
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3648420260
Short name T202
Test name
Test status
Simulation time 2436542269 ps
CPU time 129.26 seconds
Started Aug 10 05:28:26 PM PDT 24
Finished Aug 10 05:30:35 PM PDT 24
Peak memory 237436 kb
Host smart-5f12ee09-e748-48df-88f8-1a3377bc8bee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648420260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3648420260
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2109578245
Short name T312
Test name
Test status
Simulation time 1034595206 ps
CPU time 22.8 seconds
Started Aug 10 05:28:24 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 219148 kb
Host smart-cc2fbf48-ff34-434c-9a18-5e7cb02073a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109578245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2109578245
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2165520262
Short name T138
Test name
Test status
Simulation time 1061264052 ps
CPU time 11.9 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:33 PM PDT 24
Peak memory 220116 kb
Host smart-884f6371-6eb9-4a18-9230-7713b91dc117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165520262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2165520262
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.277016412
Short name T160
Test name
Test status
Simulation time 202322766 ps
CPU time 11.06 seconds
Started Aug 10 05:28:25 PM PDT 24
Finished Aug 10 05:28:36 PM PDT 24
Peak memory 220040 kb
Host smart-25ffceb2-c785-4f76-93e1-a33d84356bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277016412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.277016412
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1549910636
Short name T17
Test name
Test status
Simulation time 29256132897 ps
CPU time 10748.1 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 08:27:31 PM PDT 24
Peak memory 237468 kb
Host smart-d76a714b-f58c-4c70-8d2e-38355ba847d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549910636 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1549910636
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.632517511
Short name T213
Test name
Test status
Simulation time 264153573 ps
CPU time 10.43 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 219204 kb
Host smart-05fb5b32-1023-42b9-8fa5-d591b78c15a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632517511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.632517511
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3638605188
Short name T231
Test name
Test status
Simulation time 7264162165 ps
CPU time 236.16 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:32:18 PM PDT 24
Peak memory 242156 kb
Host smart-aa9c125a-0437-4830-8569-808ce0cc1ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638605188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3638605188
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.271162846
Short name T4
Test name
Test status
Simulation time 1054469028 ps
CPU time 22.5 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:44 PM PDT 24
Peak memory 220024 kb
Host smart-17e1ea45-6229-40b1-b28b-7b161626badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271162846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.271162846
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.645769118
Short name T62
Test name
Test status
Simulation time 179871067 ps
CPU time 10.7 seconds
Started Aug 10 05:28:21 PM PDT 24
Finished Aug 10 05:28:32 PM PDT 24
Peak memory 220024 kb
Host smart-2308e311-fc6f-4639-9850-075cc1961932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645769118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.645769118
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2098537628
Short name T265
Test name
Test status
Simulation time 1012782449 ps
CPU time 30.34 seconds
Started Aug 10 05:28:22 PM PDT 24
Finished Aug 10 05:28:53 PM PDT 24
Peak memory 220052 kb
Host smart-fd3708e4-42f2-4a99-b4d4-0196f32b0660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098537628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2098537628
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1818488669
Short name T71
Test name
Test status
Simulation time 2474989984 ps
CPU time 10.09 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:28:44 PM PDT 24
Peak memory 219284 kb
Host smart-2dd98445-b5e1-47c8-8d69-78ce9cd42355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818488669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1818488669
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1726097656
Short name T306
Test name
Test status
Simulation time 1815035511 ps
CPU time 129.56 seconds
Started Aug 10 05:28:33 PM PDT 24
Finished Aug 10 05:30:43 PM PDT 24
Peak memory 234340 kb
Host smart-16e92d80-1449-4230-b345-4c1b5c88f0ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726097656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1726097656
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2428246424
Short name T36
Test name
Test status
Simulation time 1902396687 ps
CPU time 22.74 seconds
Started Aug 10 05:28:33 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 220096 kb
Host smart-163f87df-db35-4d93-9b59-846fa3828c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428246424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2428246424
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.985433941
Short name T233
Test name
Test status
Simulation time 718908786 ps
CPU time 10.25 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 220140 kb
Host smart-95b7628b-3e4e-4a0c-8b05-bb1363b9fe88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985433941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.985433941
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3373105903
Short name T196
Test name
Test status
Simulation time 4114520866 ps
CPU time 38.33 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:29:13 PM PDT 24
Peak memory 220160 kb
Host smart-77b962b8-7fae-4d63-b872-5c2268d40e29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373105903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3373105903
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2317803496
Short name T236
Test name
Test status
Simulation time 508674375 ps
CPU time 10.17 seconds
Started Aug 10 05:28:32 PM PDT 24
Finished Aug 10 05:28:43 PM PDT 24
Peak memory 219160 kb
Host smart-6081bd6e-4424-427b-9296-00c9ce5d6058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317803496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2317803496
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.918755561
Short name T322
Test name
Test status
Simulation time 15780704301 ps
CPU time 298.48 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:33:36 PM PDT 24
Peak memory 239060 kb
Host smart-f9584b47-7a5b-4d9c-bca7-4eb0ab2ffabf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918755561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.918755561
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4052581336
Short name T261
Test name
Test status
Simulation time 2159364621 ps
CPU time 23.16 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:28:58 PM PDT 24
Peak memory 220204 kb
Host smart-1a299f4e-f122-4ddf-9457-99167c6190bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052581336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4052581336
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2948874859
Short name T310
Test name
Test status
Simulation time 269730514 ps
CPU time 12.21 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:48 PM PDT 24
Peak memory 220048 kb
Host smart-5ccaed3a-2db5-401a-af4d-e0052623948d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948874859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2948874859
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2308141527
Short name T300
Test name
Test status
Simulation time 3942279663 ps
CPU time 21.23 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:28:59 PM PDT 24
Peak memory 220180 kb
Host smart-4ed6e5dc-8407-4577-bae9-809622a210e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308141527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2308141527
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.200076650
Short name T175
Test name
Test status
Simulation time 172411294 ps
CPU time 8.14 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:28:43 PM PDT 24
Peak memory 219028 kb
Host smart-4805abca-116b-4f85-b29a-a1d03fdb4344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200076650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.200076650
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.490026360
Short name T190
Test name
Test status
Simulation time 16226208388 ps
CPU time 183.23 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:31:41 PM PDT 24
Peak memory 220408 kb
Host smart-99e27cb6-64e2-44a1-bce3-e5605a46eaa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490026360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.490026360
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4196920363
Short name T106
Test name
Test status
Simulation time 1378374716 ps
CPU time 19.78 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:28:54 PM PDT 24
Peak memory 220048 kb
Host smart-beb32454-426e-4bac-85cf-308521854561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196920363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4196920363
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.100452505
Short name T136
Test name
Test status
Simulation time 1082112217 ps
CPU time 12.33 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:28:48 PM PDT 24
Peak memory 220052 kb
Host smart-fcebab01-e9f4-4024-8bef-2388e09459fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100452505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.100452505
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.266825244
Short name T192
Test name
Test status
Simulation time 1988187277 ps
CPU time 25.75 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:29:01 PM PDT 24
Peak memory 220056 kb
Host smart-93b1d867-7d53-492e-9a73-3bf71361dd51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266825244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.266825244
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.664343900
Short name T16
Test name
Test status
Simulation time 86270301440 ps
CPU time 3442.47 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 06:25:57 PM PDT 24
Peak memory 254344 kb
Host smart-4a989bb0-6306-4726-ac4c-ff3af61a46ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664343900 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.664343900
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2017716668
Short name T262
Test name
Test status
Simulation time 262681301 ps
CPU time 10.15 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:28:45 PM PDT 24
Peak memory 218600 kb
Host smart-25266c17-3a2f-41df-89d9-00d0fdf5b6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017716668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2017716668
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3521066211
Short name T286
Test name
Test status
Simulation time 6087137857 ps
CPU time 325.22 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:34:01 PM PDT 24
Peak memory 219304 kb
Host smart-46de2cfd-d8e1-41ff-bf28-12dab04b6a7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521066211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3521066211
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.830480610
Short name T212
Test name
Test status
Simulation time 1374389851 ps
CPU time 19.15 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:28:53 PM PDT 24
Peak memory 219976 kb
Host smart-f5fdecb9-c69a-4219-8d17-2a2c5b0d402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830480610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.830480610
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.707608229
Short name T225
Test name
Test status
Simulation time 703612005 ps
CPU time 10.59 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 220024 kb
Host smart-55803184-ca27-4802-8c03-b091d5f71f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707608229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.707608229
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4059945145
Short name T156
Test name
Test status
Simulation time 36303304421 ps
CPU time 67.86 seconds
Started Aug 10 05:28:38 PM PDT 24
Finished Aug 10 05:29:45 PM PDT 24
Peak memory 220176 kb
Host smart-7310c30e-e0d6-4f79-94d9-da9dd4ebf1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059945145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4059945145
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.915680747
Short name T237
Test name
Test status
Simulation time 251580820 ps
CPU time 10.18 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 219108 kb
Host smart-2a761c76-aeeb-4250-9534-4c277615f6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915680747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.915680747
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1093418962
Short name T145
Test name
Test status
Simulation time 20083366456 ps
CPU time 195.47 seconds
Started Aug 10 05:28:33 PM PDT 24
Finished Aug 10 05:31:49 PM PDT 24
Peak memory 234596 kb
Host smart-3a2a058a-821b-40c9-b671-7dd532ed0927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093418962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1093418962
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2100115376
Short name T150
Test name
Test status
Simulation time 993254926 ps
CPU time 22.47 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:28:58 PM PDT 24
Peak memory 220100 kb
Host smart-e1076412-8cfa-457c-9dba-e23178091d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100115376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2100115376
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3772971686
Short name T207
Test name
Test status
Simulation time 1343570485 ps
CPU time 10.55 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 220112 kb
Host smart-013613ea-805c-4299-a863-66d9866d096e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772971686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3772971686
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1360123506
Short name T32
Test name
Test status
Simulation time 1654471345 ps
CPU time 42.15 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:29:17 PM PDT 24
Peak memory 220084 kb
Host smart-46e8acbe-ed1c-480a-bb74-b2f1335a707f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360123506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1360123506
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2149428578
Short name T186
Test name
Test status
Simulation time 517332911 ps
CPU time 10.39 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:47 PM PDT 24
Peak memory 218960 kb
Host smart-58f6f01f-5d80-4b19-8bcd-59273b7a6c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149428578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2149428578
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1451029035
Short name T44
Test name
Test status
Simulation time 24420694205 ps
CPU time 274.02 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:33:11 PM PDT 24
Peak memory 229328 kb
Host smart-1e559ad0-49fb-4657-9b7e-4b78c14f932f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451029035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1451029035
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2028567706
Short name T256
Test name
Test status
Simulation time 607830376 ps
CPU time 22.56 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:59 PM PDT 24
Peak memory 220096 kb
Host smart-23db34e2-cda4-46c8-8fae-380aefe008dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028567706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2028567706
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4048827630
Short name T321
Test name
Test status
Simulation time 535310167 ps
CPU time 12.06 seconds
Started Aug 10 05:28:34 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 220028 kb
Host smart-6603416a-6ca9-479a-958b-11bbdf3c0159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048827630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4048827630
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1750922081
Short name T55
Test name
Test status
Simulation time 13671173767 ps
CPU time 575.3 seconds
Started Aug 10 05:28:35 PM PDT 24
Finished Aug 10 05:38:10 PM PDT 24
Peak memory 231344 kb
Host smart-3e91ebc4-d566-4df1-a266-353bb00b6d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750922081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1750922081
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.49955798
Short name T72
Test name
Test status
Simulation time 268494843 ps
CPU time 10.24 seconds
Started Aug 10 05:28:36 PM PDT 24
Finished Aug 10 05:28:46 PM PDT 24
Peak memory 219220 kb
Host smart-7e10049b-97b7-45fb-b14a-c813f6cffb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49955798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.49955798
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3202864593
Short name T249
Test name
Test status
Simulation time 349442613 ps
CPU time 10.63 seconds
Started Aug 10 05:28:33 PM PDT 24
Finished Aug 10 05:28:44 PM PDT 24
Peak memory 220068 kb
Host smart-9225909a-2e1e-4db4-b602-37d42cd9ed43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202864593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3202864593
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2609948589
Short name T221
Test name
Test status
Simulation time 1456592710 ps
CPU time 24.93 seconds
Started Aug 10 05:28:37 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 219960 kb
Host smart-50d9411a-d35f-498e-ad9f-6db25ab74470
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609948589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2609948589
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3607875477
Short name T297
Test name
Test status
Simulation time 341253071 ps
CPU time 8.54 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:27:56 PM PDT 24
Peak memory 218164 kb
Host smart-c9bdae6b-c9d7-4143-999a-9fedb692051d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607875477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3607875477
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3422048322
Short name T293
Test name
Test status
Simulation time 16670939590 ps
CPU time 240.07 seconds
Started Aug 10 05:27:45 PM PDT 24
Finished Aug 10 05:31:46 PM PDT 24
Peak memory 240776 kb
Host smart-f7ea82d9-4342-49c0-b3f1-a710b0be80f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422048322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3422048322
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2037212334
Short name T180
Test name
Test status
Simulation time 661437215 ps
CPU time 19.28 seconds
Started Aug 10 05:27:53 PM PDT 24
Finished Aug 10 05:28:12 PM PDT 24
Peak memory 220116 kb
Host smart-f5dc3d18-2671-4980-87fd-4adbc2cda14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037212334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2037212334
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3640456751
Short name T311
Test name
Test status
Simulation time 884597729 ps
CPU time 12.37 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:28:01 PM PDT 24
Peak memory 220044 kb
Host smart-5831465d-00eb-470f-9c1b-41f9c58e08f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640456751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3640456751
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2708554585
Short name T267
Test name
Test status
Simulation time 234149960 ps
CPU time 10.31 seconds
Started Aug 10 05:27:39 PM PDT 24
Finished Aug 10 05:27:49 PM PDT 24
Peak memory 220084 kb
Host smart-20f9144d-ea37-4c0c-b314-9fa1c26d8232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708554585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2708554585
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3899217600
Short name T276
Test name
Test status
Simulation time 2781780578 ps
CPU time 24.06 seconds
Started Aug 10 05:27:40 PM PDT 24
Finished Aug 10 05:28:04 PM PDT 24
Peak memory 220196 kb
Host smart-b7df6daa-0b97-48e5-a153-ead521fe88d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899217600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3899217600
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2702917369
Short name T205
Test name
Test status
Simulation time 168243447 ps
CPU time 8.72 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:28:52 PM PDT 24
Peak memory 218624 kb
Host smart-40816917-f3ed-465b-b128-e17f35e3d75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702917369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2702917369
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4274000339
Short name T189
Test name
Test status
Simulation time 5096893044 ps
CPU time 150.59 seconds
Started Aug 10 05:28:48 PM PDT 24
Finished Aug 10 05:31:19 PM PDT 24
Peak memory 236672 kb
Host smart-51144b95-8e29-42af-895f-23685bfc7efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274000339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4274000339
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3028447233
Short name T244
Test name
Test status
Simulation time 2197279798 ps
CPU time 19.39 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:29:05 PM PDT 24
Peak memory 220120 kb
Host smart-0e21bdf2-9743-4cc7-a408-6cd394868813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028447233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3028447233
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2561640706
Short name T183
Test name
Test status
Simulation time 1686256623 ps
CPU time 12.13 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 220088 kb
Host smart-a5ca193c-daee-4607-bddb-0e6fd65a6a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561640706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2561640706
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1421490710
Short name T163
Test name
Test status
Simulation time 730268412 ps
CPU time 24.01 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:29:08 PM PDT 24
Peak memory 220060 kb
Host smart-0a2dd2a0-19d7-4cb8-b5c3-f9b032432451
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421490710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1421490710
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4173979883
Short name T159
Test name
Test status
Simulation time 249713448 ps
CPU time 10.18 seconds
Started Aug 10 05:28:46 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 219140 kb
Host smart-aa47939b-d9e0-4049-b857-273d0499d207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173979883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4173979883
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3105741387
Short name T188
Test name
Test status
Simulation time 13308795074 ps
CPU time 227.85 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:32:32 PM PDT 24
Peak memory 241416 kb
Host smart-2b903391-77be-4316-9e46-c4b252730794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105741387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3105741387
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3970608516
Short name T305
Test name
Test status
Simulation time 596861482 ps
CPU time 22.85 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:29:08 PM PDT 24
Peak memory 220116 kb
Host smart-c9c0a425-76e6-40df-86c6-9e89f66f02e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970608516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3970608516
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2376139743
Short name T219
Test name
Test status
Simulation time 185054745 ps
CPU time 10.5 seconds
Started Aug 10 05:28:48 PM PDT 24
Finished Aug 10 05:28:58 PM PDT 24
Peak memory 220092 kb
Host smart-3c9e95a2-3ed9-4984-bcf3-931e9ad3d5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376139743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2376139743
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2510296995
Short name T182
Test name
Test status
Simulation time 1058010306 ps
CPU time 34.14 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:29:22 PM PDT 24
Peak memory 220060 kb
Host smart-dc1cc3f4-deb1-4453-ac00-cc68b7bd4a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510296995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2510296995
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3888951960
Short name T203
Test name
Test status
Simulation time 986167019 ps
CPU time 15.16 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:29:04 PM PDT 24
Peak memory 219128 kb
Host smart-cd5ab998-04ec-40e2-bd8d-08024f8b9c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888951960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3888951960
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2494919764
Short name T242
Test name
Test status
Simulation time 13485881651 ps
CPU time 369.95 seconds
Started Aug 10 05:28:42 PM PDT 24
Finished Aug 10 05:34:52 PM PDT 24
Peak memory 240516 kb
Host smart-679f2b1e-be0a-46ad-8f10-17358cc05c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494919764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2494919764
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.964574992
Short name T232
Test name
Test status
Simulation time 511465084 ps
CPU time 23.02 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:29:08 PM PDT 24
Peak memory 220088 kb
Host smart-3b78cdc3-91c2-4a2f-91a1-b9906108e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964574992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.964574992
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3757649421
Short name T112
Test name
Test status
Simulation time 2152759095 ps
CPU time 10.18 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:28:59 PM PDT 24
Peak memory 220220 kb
Host smart-1d3564ee-4b4e-48ff-baa9-5d38f9148745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757649421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3757649421
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.219724221
Short name T284
Test name
Test status
Simulation time 2341016921 ps
CPU time 28.08 seconds
Started Aug 10 05:28:46 PM PDT 24
Finished Aug 10 05:29:14 PM PDT 24
Peak memory 219984 kb
Host smart-885cfc6c-9c5a-4b69-8ef9-3b342e02e05c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219724221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.219724221
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3228977584
Short name T294
Test name
Test status
Simulation time 257546697 ps
CPU time 10.2 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:28:57 PM PDT 24
Peak memory 218952 kb
Host smart-46ca26b5-e7e4-48cc-a65a-6710113d0c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228977584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3228977584
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1315854538
Short name T254
Test name
Test status
Simulation time 6045127126 ps
CPU time 327.73 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:34:17 PM PDT 24
Peak memory 240236 kb
Host smart-09c49849-5516-4a78-b9fd-5f8ccd63822d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315854538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1315854538
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3400855026
Short name T230
Test name
Test status
Simulation time 1649282928 ps
CPU time 19.09 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 219172 kb
Host smart-6e196ac6-e362-4484-b290-3c8d9ec24d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400855026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3400855026
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2978378681
Short name T20
Test name
Test status
Simulation time 521082042 ps
CPU time 11.93 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 220000 kb
Host smart-a700592b-be84-413c-a1c8-32918de0d7f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978378681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2978378681
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.353935096
Short name T263
Test name
Test status
Simulation time 2163399260 ps
CPU time 35.18 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:29:20 PM PDT 24
Peak memory 220196 kb
Host smart-9db94c9c-aeea-4a48-9485-3f23086d4d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353935096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.353935096
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3466842768
Short name T291
Test name
Test status
Simulation time 590071215 ps
CPU time 9.84 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:28:55 PM PDT 24
Peak memory 219140 kb
Host smart-9feeb268-1279-45be-8fe8-2393c714b14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466842768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3466842768
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1239559693
Short name T320
Test name
Test status
Simulation time 4914718033 ps
CPU time 284.24 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:33:29 PM PDT 24
Peak memory 239552 kb
Host smart-16a8d321-c94a-4b6d-ac05-99abf647e8ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239559693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1239559693
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.177575653
Short name T170
Test name
Test status
Simulation time 511749268 ps
CPU time 22.84 seconds
Started Aug 10 05:28:42 PM PDT 24
Finished Aug 10 05:29:05 PM PDT 24
Peak memory 220024 kb
Host smart-145b3643-6e61-46c7-84e2-63b9fd29a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177575653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.177575653
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1578829065
Short name T281
Test name
Test status
Simulation time 523143287 ps
CPU time 11.95 seconds
Started Aug 10 05:28:41 PM PDT 24
Finished Aug 10 05:28:53 PM PDT 24
Peak memory 220084 kb
Host smart-360d0a56-d67f-4f2b-8972-dd82fa4f29e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578829065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1578829065
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.748252884
Short name T248
Test name
Test status
Simulation time 280092535 ps
CPU time 16.39 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 219988 kb
Host smart-a4cc42ee-fd98-4927-8909-5d4e37a9011a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748252884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.748252884
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2084275632
Short name T54
Test name
Test status
Simulation time 166553726451 ps
CPU time 1811.41 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:58:54 PM PDT 24
Peak memory 253060 kb
Host smart-36adc143-3318-42f3-8a4a-cc5e1d31c4c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084275632 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2084275632
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1099067667
Short name T307
Test name
Test status
Simulation time 167565521 ps
CPU time 8.38 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:28:52 PM PDT 24
Peak memory 219116 kb
Host smart-f327c591-76af-46ee-bd40-4ee20f18067e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099067667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1099067667
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3958346329
Short name T227
Test name
Test status
Simulation time 38731792845 ps
CPU time 366.56 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:34:54 PM PDT 24
Peak memory 235956 kb
Host smart-61fae8f3-8e8f-4de8-9270-937353b03e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958346329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3958346329
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.206147697
Short name T280
Test name
Test status
Simulation time 343335573 ps
CPU time 19.3 seconds
Started Aug 10 05:28:42 PM PDT 24
Finished Aug 10 05:29:02 PM PDT 24
Peak memory 220080 kb
Host smart-e9b3653f-13cb-4e8d-b3b0-9df202ac6592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206147697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.206147697
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.856864929
Short name T34
Test name
Test status
Simulation time 996611662 ps
CPU time 17.58 seconds
Started Aug 10 05:28:46 PM PDT 24
Finished Aug 10 05:29:04 PM PDT 24
Peak memory 219488 kb
Host smart-6f5f25e8-5f5d-4694-9f07-d49d0ba698c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856864929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.856864929
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3487749807
Short name T144
Test name
Test status
Simulation time 530629942 ps
CPU time 30.39 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:29:16 PM PDT 24
Peak memory 220072 kb
Host smart-d963f534-1145-44ef-852e-4b3a1a192155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487749807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3487749807
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3906854594
Short name T168
Test name
Test status
Simulation time 332709738 ps
CPU time 10.02 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:28:57 PM PDT 24
Peak memory 219012 kb
Host smart-d6dd405e-0d28-4605-8ba5-ff8e9affdfe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906854594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3906854594
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.389122796
Short name T46
Test name
Test status
Simulation time 18012539466 ps
CPU time 335.12 seconds
Started Aug 10 05:28:46 PM PDT 24
Finished Aug 10 05:34:21 PM PDT 24
Peak memory 239540 kb
Host smart-4072bbef-58c3-4ccf-bb2a-13650cd57031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389122796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.389122796
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3118383483
Short name T108
Test name
Test status
Simulation time 1322959628 ps
CPU time 19.43 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:29:04 PM PDT 24
Peak memory 220100 kb
Host smart-7ba3e2d1-9d2e-4b24-b962-1d414030ad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118383483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3118383483
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1285545892
Short name T271
Test name
Test status
Simulation time 311855627 ps
CPU time 12.25 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:28:57 PM PDT 24
Peak memory 220108 kb
Host smart-07582724-d471-440e-a380-fb7a18339760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285545892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1285545892
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1700861511
Short name T316
Test name
Test status
Simulation time 1583144890 ps
CPU time 23.6 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:29:11 PM PDT 24
Peak memory 220084 kb
Host smart-62585515-dd21-4053-860b-9615b97f5578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700861511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1700861511
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1633124645
Short name T272
Test name
Test status
Simulation time 526212946 ps
CPU time 10.34 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:28:59 PM PDT 24
Peak memory 219136 kb
Host smart-482aec44-2327-416a-9dc5-e6770fe941f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633124645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1633124645
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4140905311
Short name T214
Test name
Test status
Simulation time 3388024533 ps
CPU time 190.69 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:31:55 PM PDT 24
Peak memory 238712 kb
Host smart-51b58a46-cb6a-4f7b-948f-288cc1363975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140905311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4140905311
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2116323582
Short name T223
Test name
Test status
Simulation time 1322733568 ps
CPU time 19.31 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:29:03 PM PDT 24
Peak memory 220176 kb
Host smart-139db936-637f-468c-a829-6d2639f2c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116323582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2116323582
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3836131557
Short name T152
Test name
Test status
Simulation time 261531265 ps
CPU time 11.99 seconds
Started Aug 10 05:28:44 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 220108 kb
Host smart-b7cb0dd6-e502-4028-9277-0f4cc8a7c385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836131557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3836131557
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3927241890
Short name T6
Test name
Test status
Simulation time 2204235790 ps
CPU time 29.75 seconds
Started Aug 10 05:28:49 PM PDT 24
Finished Aug 10 05:29:19 PM PDT 24
Peak memory 219996 kb
Host smart-6cba9dfe-f475-4b6f-8968-e1a5b0894402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927241890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3927241890
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2871677605
Short name T113
Test name
Test status
Simulation time 1383352490 ps
CPU time 10.43 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:28:58 PM PDT 24
Peak memory 219212 kb
Host smart-d0e9df5a-deee-4ae1-945c-7ff7cd2b210a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871677605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2871677605
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3767021329
Short name T259
Test name
Test status
Simulation time 19959760247 ps
CPU time 192.95 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:32:00 PM PDT 24
Peak memory 238712 kb
Host smart-f94df288-084e-4f4e-85d7-b2506028775c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767021329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3767021329
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1108915686
Short name T47
Test name
Test status
Simulation time 1321227174 ps
CPU time 19.12 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:29:04 PM PDT 24
Peak memory 219964 kb
Host smart-2bc9fa1d-62b6-45cc-a9f5-d04f076cdc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108915686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1108915686
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1948512534
Short name T226
Test name
Test status
Simulation time 1071003042 ps
CPU time 12.62 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:28:56 PM PDT 24
Peak memory 220088 kb
Host smart-40881f14-bc4d-42f3-b803-a362dc4a9a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948512534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1948512534
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1629767273
Short name T278
Test name
Test status
Simulation time 1287952167 ps
CPU time 16.25 seconds
Started Aug 10 05:28:43 PM PDT 24
Finished Aug 10 05:28:59 PM PDT 24
Peak memory 219992 kb
Host smart-4242a0ce-3e29-480a-acf9-98aa41729fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629767273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1629767273
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.153514136
Short name T288
Test name
Test status
Simulation time 884622285 ps
CPU time 9.97 seconds
Started Aug 10 05:28:48 PM PDT 24
Finished Aug 10 05:28:58 PM PDT 24
Peak memory 219140 kb
Host smart-61d01b54-a3ca-42d5-933f-7cf0180ff3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153514136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.153514136
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1907323512
Short name T301
Test name
Test status
Simulation time 9608256681 ps
CPU time 180.44 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:31:46 PM PDT 24
Peak memory 240300 kb
Host smart-4049d51a-b240-4a44-b9b0-31a63bfea89c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907323512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1907323512
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3995192678
Short name T211
Test name
Test status
Simulation time 1945600437 ps
CPU time 19.14 seconds
Started Aug 10 05:28:46 PM PDT 24
Finished Aug 10 05:29:05 PM PDT 24
Peak memory 220100 kb
Host smart-605b7ecc-5ac9-4ec0-9469-4c8866733ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995192678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3995192678
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3410783200
Short name T60
Test name
Test status
Simulation time 1494042550 ps
CPU time 12.15 seconds
Started Aug 10 05:28:47 PM PDT 24
Finished Aug 10 05:29:00 PM PDT 24
Peak memory 220060 kb
Host smart-9589e225-3cb1-4f32-86c5-a630de58e591
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410783200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3410783200
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2862857300
Short name T86
Test name
Test status
Simulation time 212721745 ps
CPU time 11.3 seconds
Started Aug 10 05:28:45 PM PDT 24
Finished Aug 10 05:28:57 PM PDT 24
Peak memory 220060 kb
Host smart-09d4fbf1-504f-49f5-8b0f-73f93370de41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862857300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2862857300
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1372516520
Short name T169
Test name
Test status
Simulation time 592819514 ps
CPU time 10.31 seconds
Started Aug 10 05:27:50 PM PDT 24
Finished Aug 10 05:28:01 PM PDT 24
Peak memory 219172 kb
Host smart-dbf6744c-8ff5-4504-9a65-bfe725c9b05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372516520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1372516520
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2604787621
Short name T43
Test name
Test status
Simulation time 18738190023 ps
CPU time 354.94 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:33:44 PM PDT 24
Peak memory 234728 kb
Host smart-2ebdc759-7639-4c92-95fe-94caec60e88d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604787621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2604787621
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3658415372
Short name T146
Test name
Test status
Simulation time 501288457 ps
CPU time 22.3 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:28:11 PM PDT 24
Peak memory 220020 kb
Host smart-86ad6701-583f-40cc-a39c-6303ffb09a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658415372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3658415372
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.586414694
Short name T135
Test name
Test status
Simulation time 1027561836 ps
CPU time 16.7 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 219568 kb
Host smart-404500b1-cc1b-450c-b5c8-0a2d5f142e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586414694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.586414694
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3578995322
Short name T2
Test name
Test status
Simulation time 1076984390 ps
CPU time 12.22 seconds
Started Aug 10 05:27:50 PM PDT 24
Finished Aug 10 05:28:02 PM PDT 24
Peak memory 220080 kb
Host smart-c9da1aa2-b895-444b-bed8-5f4e6ac413f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578995322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3578995322
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2948952109
Short name T184
Test name
Test status
Simulation time 2229994491 ps
CPU time 30.9 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:20 PM PDT 24
Peak memory 220032 kb
Host smart-23e18a30-438a-473f-afd1-c314ce83eefe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948952109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2948952109
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3585993403
Short name T269
Test name
Test status
Simulation time 260974933 ps
CPU time 10.49 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:00 PM PDT 24
Peak memory 218684 kb
Host smart-4cc6149d-bf09-4515-af33-5dc814d23b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585993403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3585993403
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2587890336
Short name T193
Test name
Test status
Simulation time 10044168946 ps
CPU time 282.07 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:32:30 PM PDT 24
Peak memory 225688 kb
Host smart-9004b045-04b7-46b0-a38d-5803d44689eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587890336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2587890336
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3793214328
Short name T290
Test name
Test status
Simulation time 1320963079 ps
CPU time 19.87 seconds
Started Aug 10 05:27:47 PM PDT 24
Finished Aug 10 05:28:07 PM PDT 24
Peak memory 220020 kb
Host smart-49d49080-4712-4ec2-a1c2-d9a6b8b7cfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793214328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3793214328
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3918477917
Short name T292
Test name
Test status
Simulation time 259057277 ps
CPU time 12.22 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:28:00 PM PDT 24
Peak memory 220128 kb
Host smart-6e4457b8-01d2-4383-b74c-5a5c98d8ba11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918477917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3918477917
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.212434336
Short name T308
Test name
Test status
Simulation time 178950390 ps
CPU time 10.63 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:27:59 PM PDT 24
Peak memory 219972 kb
Host smart-bbfd9311-3dd6-4e62-b1dc-97d43293bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212434336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.212434336
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4097288107
Short name T274
Test name
Test status
Simulation time 277391589 ps
CPU time 10.25 seconds
Started Aug 10 05:27:48 PM PDT 24
Finished Aug 10 05:27:58 PM PDT 24
Peak memory 219336 kb
Host smart-c1a0c577-3bb6-442b-9ab3-dceb39f77900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097288107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4097288107
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.214777817
Short name T224
Test name
Test status
Simulation time 6472369807 ps
CPU time 186.69 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:30:56 PM PDT 24
Peak memory 238692 kb
Host smart-fd1e62d2-692e-48ff-8c85-1c666dd4597d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214777817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.214777817
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1976322430
Short name T48
Test name
Test status
Simulation time 2055361925 ps
CPU time 22.19 seconds
Started Aug 10 05:27:52 PM PDT 24
Finished Aug 10 05:28:14 PM PDT 24
Peak memory 219976 kb
Host smart-58afc87c-1be5-4e7f-8fef-1fd85b60f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976322430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1976322430
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3888148367
Short name T238
Test name
Test status
Simulation time 268349500 ps
CPU time 12.08 seconds
Started Aug 10 05:27:51 PM PDT 24
Finished Aug 10 05:28:03 PM PDT 24
Peak memory 220088 kb
Host smart-e236b35c-7f1d-4d4d-8ee5-3b7611a1ba8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888148367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3888148367
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2369788248
Short name T240
Test name
Test status
Simulation time 676695737 ps
CPU time 10.56 seconds
Started Aug 10 05:27:47 PM PDT 24
Finished Aug 10 05:27:58 PM PDT 24
Peak memory 220052 kb
Host smart-22b30e46-218a-46bc-a399-8d922869fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369788248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2369788248
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1154630299
Short name T89
Test name
Test status
Simulation time 2391453060 ps
CPU time 38.58 seconds
Started Aug 10 05:27:50 PM PDT 24
Finished Aug 10 05:28:28 PM PDT 24
Peak memory 220220 kb
Host smart-08a94887-9fea-46f6-8ff3-e0a18bffbb9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154630299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1154630299
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.838401178
Short name T70
Test name
Test status
Simulation time 167541632 ps
CPU time 8.29 seconds
Started Aug 10 05:27:50 PM PDT 24
Finished Aug 10 05:27:58 PM PDT 24
Peak memory 219072 kb
Host smart-fa288a4c-80e4-4f03-9c0b-614ccda64b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838401178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.838401178
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2012661579
Short name T283
Test name
Test status
Simulation time 17251409619 ps
CPU time 213.93 seconds
Started Aug 10 05:27:52 PM PDT 24
Finished Aug 10 05:31:26 PM PDT 24
Peak memory 242804 kb
Host smart-cea67302-9219-48a6-b4e5-ed2546c5b5bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012661579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2012661579
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1114477336
Short name T299
Test name
Test status
Simulation time 1074764690 ps
CPU time 22.13 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:11 PM PDT 24
Peak memory 220044 kb
Host smart-46d95df6-7229-4136-9f1f-2bd109a2743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114477336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1114477336
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1221020914
Short name T185
Test name
Test status
Simulation time 691852028 ps
CPU time 10.27 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:28:00 PM PDT 24
Peak memory 220068 kb
Host smart-2f30f755-43fd-42cd-9fb4-30e83b0aca3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221020914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1221020914
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2426048869
Short name T303
Test name
Test status
Simulation time 266604142 ps
CPU time 12.64 seconds
Started Aug 10 05:27:46 PM PDT 24
Finished Aug 10 05:27:58 PM PDT 24
Peak memory 220072 kb
Host smart-bef32842-9829-4dad-a25b-8af2ea2082ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426048869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2426048869
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2406378057
Short name T88
Test name
Test status
Simulation time 2321041679 ps
CPU time 46.39 seconds
Started Aug 10 05:27:50 PM PDT 24
Finished Aug 10 05:28:36 PM PDT 24
Peak memory 220176 kb
Host smart-e1ae41ca-a828-4a77-9c52-9221947ea5dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406378057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2406378057
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.42431384
Short name T234
Test name
Test status
Simulation time 691674444 ps
CPU time 8.26 seconds
Started Aug 10 05:27:57 PM PDT 24
Finished Aug 10 05:28:06 PM PDT 24
Peak memory 219140 kb
Host smart-2bb7d302-5d2c-4501-aadf-55fd93e2f7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42431384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.42431384
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2136916064
Short name T206
Test name
Test status
Simulation time 16894373455 ps
CPU time 172.42 seconds
Started Aug 10 05:27:59 PM PDT 24
Finished Aug 10 05:30:52 PM PDT 24
Peak memory 239856 kb
Host smart-e7219d16-3845-4413-8028-bd14b17fabca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136916064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2136916064
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.610940713
Short name T3
Test name
Test status
Simulation time 2067122586 ps
CPU time 22.67 seconds
Started Aug 10 05:27:56 PM PDT 24
Finished Aug 10 05:28:19 PM PDT 24
Peak memory 220084 kb
Host smart-811080e1-b448-4f70-bf32-5c9a6f409167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610940713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.610940713
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2483843269
Short name T154
Test name
Test status
Simulation time 673540692 ps
CPU time 10.26 seconds
Started Aug 10 05:27:55 PM PDT 24
Finished Aug 10 05:28:05 PM PDT 24
Peak memory 220036 kb
Host smart-4d910880-64b4-42b6-9075-7d5bcee65575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483843269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2483843269
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3714392503
Short name T87
Test name
Test status
Simulation time 368805473 ps
CPU time 10.31 seconds
Started Aug 10 05:27:49 PM PDT 24
Finished Aug 10 05:27:59 PM PDT 24
Peak memory 220036 kb
Host smart-b155f5f7-8620-493c-9a01-40341b24b06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714392503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3714392503
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3410636819
Short name T176
Test name
Test status
Simulation time 362824578 ps
CPU time 20.1 seconds
Started Aug 10 05:27:55 PM PDT 24
Finished Aug 10 05:28:15 PM PDT 24
Peak memory 220064 kb
Host smart-0109e312-a62e-4c00-809c-32ffb255704f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410636819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3410636819
Directory /workspace/9.rom_ctrl_stress_all/latest
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