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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.68 100.00 98.62 97.45 98.37


Total test records in report: 423
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T304 /workspace/coverage/default/39.rom_ctrl_alert_test.1423741074 Aug 11 06:52:02 PM PDT 24 Aug 11 06:52:10 PM PDT 24 332379044 ps
T305 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3170020331 Aug 11 06:51:45 PM PDT 24 Aug 11 06:51:56 PM PDT 24 186575109 ps
T306 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.534540965 Aug 11 06:51:48 PM PDT 24 Aug 11 07:45:53 PM PDT 24 35981850607 ps
T307 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3268835975 Aug 11 06:51:39 PM PDT 24 Aug 11 06:51:52 PM PDT 24 1025097890 ps
T308 /workspace/coverage/default/0.rom_ctrl_smoke.4247641486 Aug 11 06:51:17 PM PDT 24 Aug 11 06:51:29 PM PDT 24 274163256 ps
T309 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2699746169 Aug 11 06:51:42 PM PDT 24 Aug 11 06:51:54 PM PDT 24 272342553 ps
T310 /workspace/coverage/default/19.rom_ctrl_stress_all.3603910799 Aug 11 06:51:46 PM PDT 24 Aug 11 06:52:05 PM PDT 24 573009097 ps
T311 /workspace/coverage/default/20.rom_ctrl_stress_all.125149246 Aug 11 06:51:46 PM PDT 24 Aug 11 06:52:21 PM PDT 24 2519990869 ps
T312 /workspace/coverage/default/8.rom_ctrl_stress_all.3931945022 Aug 11 06:51:30 PM PDT 24 Aug 11 06:52:05 PM PDT 24 2515745501 ps
T313 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4102714788 Aug 11 06:51:23 PM PDT 24 Aug 11 06:54:08 PM PDT 24 5918723374 ps
T314 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2247876474 Aug 11 06:51:42 PM PDT 24 Aug 11 06:54:54 PM PDT 24 13676423256 ps
T315 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2263336036 Aug 11 06:51:42 PM PDT 24 Aug 11 06:51:59 PM PDT 24 4562076510 ps
T316 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3527320408 Aug 11 06:51:38 PM PDT 24 Aug 11 06:51:48 PM PDT 24 182623024 ps
T317 /workspace/coverage/default/28.rom_ctrl_alert_test.3756708297 Aug 11 06:51:48 PM PDT 24 Aug 11 06:51:56 PM PDT 24 319114820 ps
T318 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2320132210 Aug 11 06:51:28 PM PDT 24 Aug 11 06:56:36 PM PDT 24 4889326561 ps
T94 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.838082795 Aug 11 06:51:52 PM PDT 24 Aug 11 06:52:02 PM PDT 24 697809600 ps
T95 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1237549597 Aug 11 06:51:28 PM PDT 24 Aug 11 06:51:40 PM PDT 24 1053648851 ps
T96 /workspace/coverage/default/35.rom_ctrl_alert_test.1979097810 Aug 11 06:51:58 PM PDT 24 Aug 11 06:52:06 PM PDT 24 169552694 ps
T97 /workspace/coverage/default/49.rom_ctrl_stress_all.3819209280 Aug 11 06:52:27 PM PDT 24 Aug 11 06:53:03 PM PDT 24 1109953611 ps
T98 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1596513005 Aug 11 06:51:40 PM PDT 24 Aug 11 06:51:52 PM PDT 24 269705298 ps
T99 /workspace/coverage/default/0.rom_ctrl_stress_all.1490750676 Aug 11 06:51:18 PM PDT 24 Aug 11 06:51:38 PM PDT 24 7576853712 ps
T100 /workspace/coverage/default/46.rom_ctrl_alert_test.3364848320 Aug 11 06:52:22 PM PDT 24 Aug 11 06:52:30 PM PDT 24 970435109 ps
T101 /workspace/coverage/default/33.rom_ctrl_stress_all.1622747146 Aug 11 06:51:53 PM PDT 24 Aug 11 06:52:46 PM PDT 24 11969159074 ps
T102 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.415285895 Aug 11 06:51:15 PM PDT 24 Aug 11 06:51:26 PM PDT 24 666457886 ps
T103 /workspace/coverage/default/41.rom_ctrl_alert_test.590471013 Aug 11 06:52:07 PM PDT 24 Aug 11 06:52:18 PM PDT 24 258765934 ps
T319 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4087439121 Aug 11 06:51:27 PM PDT 24 Aug 11 06:51:37 PM PDT 24 184060173 ps
T320 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3579411787 Aug 11 06:51:50 PM PDT 24 Aug 11 06:52:01 PM PDT 24 185256453 ps
T321 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2782875667 Aug 11 06:51:37 PM PDT 24 Aug 11 07:10:11 PM PDT 24 55132577396 ps
T322 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1653279572 Aug 11 06:17:39 PM PDT 24 Aug 11 06:17:49 PM PDT 24 1034684131 ps
T323 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1461574615 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:56 PM PDT 24 660812946 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3161097233 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:07 PM PDT 24 986099120 ps
T57 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2033327970 Aug 11 06:17:53 PM PDT 24 Aug 11 06:18:01 PM PDT 24 178853426 ps
T58 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1023761355 Aug 11 06:17:59 PM PDT 24 Aug 11 06:19:03 PM PDT 24 1523294099 ps
T324 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.576422955 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:53 PM PDT 24 267043014 ps
T325 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3755227269 Aug 11 06:18:01 PM PDT 24 Aug 11 06:18:10 PM PDT 24 360070139 ps
T326 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4203960168 Aug 11 06:17:39 PM PDT 24 Aug 11 06:17:49 PM PDT 24 986155358 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2709970612 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:52 PM PDT 24 248532620 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1953004785 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:03 PM PDT 24 353308904 ps
T327 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4106244538 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:52 PM PDT 24 498003841 ps
T53 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.120653183 Aug 11 06:17:31 PM PDT 24 Aug 11 06:20:11 PM PDT 24 394145605 ps
T54 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2291875569 Aug 11 06:17:40 PM PDT 24 Aug 11 06:20:18 PM PDT 24 389709652 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1019587712 Aug 11 06:17:34 PM PDT 24 Aug 11 06:20:09 PM PDT 24 386637806 ps
T328 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2169310147 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:09 PM PDT 24 953254863 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3413290720 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:12 PM PDT 24 533512046 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3701885536 Aug 11 06:17:48 PM PDT 24 Aug 11 06:17:58 PM PDT 24 2236617418 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1499598743 Aug 11 06:17:54 PM PDT 24 Aug 11 06:18:04 PM PDT 24 252753391 ps
T107 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1906480978 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:50 PM PDT 24 668372761 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3740420056 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:55 PM PDT 24 662880811 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3494188407 Aug 11 06:17:57 PM PDT 24 Aug 11 06:19:24 PM PDT 24 2185565369 ps
T329 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1820704344 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:41 PM PDT 24 721248159 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2234205038 Aug 11 06:17:51 PM PDT 24 Aug 11 06:18:05 PM PDT 24 2504387423 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1981080543 Aug 11 06:17:58 PM PDT 24 Aug 11 06:19:03 PM PDT 24 1587235077 ps
T72 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2298166880 Aug 11 06:17:49 PM PDT 24 Aug 11 06:18:33 PM PDT 24 1027370346 ps
T330 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2591454939 Aug 11 06:18:01 PM PDT 24 Aug 11 06:18:12 PM PDT 24 259726311 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3414011205 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:06 PM PDT 24 167621754 ps
T331 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3944603710 Aug 11 06:18:00 PM PDT 24 Aug 11 06:18:14 PM PDT 24 260446422 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2472600810 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:54 PM PDT 24 833056277 ps
T332 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.400806693 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:58 PM PDT 24 260908844 ps
T81 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1856880699 Aug 11 06:17:51 PM PDT 24 Aug 11 06:18:01 PM PDT 24 2060961472 ps
T333 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.971073387 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:50 PM PDT 24 1374261990 ps
T334 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1197867741 Aug 11 06:17:29 PM PDT 24 Aug 11 06:17:44 PM PDT 24 984923103 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3075893113 Aug 11 06:17:55 PM PDT 24 Aug 11 06:20:28 PM PDT 24 2770716193 ps
T335 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3411211808 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:06 PM PDT 24 183895597 ps
T336 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4167787494 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:04 PM PDT 24 591596421 ps
T337 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2705152409 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:07 PM PDT 24 168480651 ps
T338 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2482285415 Aug 11 06:18:04 PM PDT 24 Aug 11 06:18:13 PM PDT 24 702804347 ps
T339 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1190264064 Aug 11 06:17:47 PM PDT 24 Aug 11 06:18:01 PM PDT 24 347917694 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.431692380 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:57 PM PDT 24 1031794725 ps
T340 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4098376120 Aug 11 06:17:50 PM PDT 24 Aug 11 06:18:01 PM PDT 24 261358849 ps
T341 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4103125352 Aug 11 06:17:50 PM PDT 24 Aug 11 06:18:05 PM PDT 24 1065924581 ps
T89 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3556610240 Aug 11 06:18:03 PM PDT 24 Aug 11 06:19:00 PM PDT 24 1073773467 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3815595271 Aug 11 06:17:37 PM PDT 24 Aug 11 06:18:22 PM PDT 24 4060666687 ps
T342 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2235722838 Aug 11 06:18:02 PM PDT 24 Aug 11 06:18:11 PM PDT 24 257428787 ps
T343 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1684445782 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:07 PM PDT 24 674290301 ps
T344 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1667708002 Aug 11 06:17:49 PM PDT 24 Aug 11 06:18:02 PM PDT 24 486971354 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3285843625 Aug 11 06:17:57 PM PDT 24 Aug 11 06:19:21 PM PDT 24 393945758 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1360021731 Aug 11 06:18:00 PM PDT 24 Aug 11 06:18:08 PM PDT 24 1100571580 ps
T345 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.57237652 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:09 PM PDT 24 345083746 ps
T346 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2928819354 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:58 PM PDT 24 1219443836 ps
T347 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3467641353 Aug 11 06:17:53 PM PDT 24 Aug 11 06:18:04 PM PDT 24 534038496 ps
T348 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3106924676 Aug 11 06:17:34 PM PDT 24 Aug 11 06:17:48 PM PDT 24 983882536 ps
T349 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1057182518 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:57 PM PDT 24 251615432 ps
T350 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2844321768 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:53 PM PDT 24 279499834 ps
T118 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.201421034 Aug 11 06:17:47 PM PDT 24 Aug 11 06:19:08 PM PDT 24 275069966 ps
T351 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.866502099 Aug 11 06:17:33 PM PDT 24 Aug 11 06:17:43 PM PDT 24 189721548 ps
T352 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.186863456 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:48 PM PDT 24 1772686909 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.186261028 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:42 PM PDT 24 4227350753 ps
T353 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3726331945 Aug 11 06:17:41 PM PDT 24 Aug 11 06:17:56 PM PDT 24 983020934 ps
T121 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3051585298 Aug 11 06:17:47 PM PDT 24 Aug 11 06:20:23 PM PDT 24 334169747 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.383089877 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:49 PM PDT 24 175431101 ps
T355 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.748591114 Aug 11 06:17:46 PM PDT 24 Aug 11 06:17:58 PM PDT 24 234388821 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3246934998 Aug 11 06:17:44 PM PDT 24 Aug 11 06:17:55 PM PDT 24 1032484490 ps
T357 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.931488353 Aug 11 06:17:57 PM PDT 24 Aug 11 06:19:21 PM PDT 24 1674153500 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2883999755 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:48 PM PDT 24 2747750986 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2256498724 Aug 11 06:17:42 PM PDT 24 Aug 11 06:19:05 PM PDT 24 334801291 ps
T359 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2472546490 Aug 11 06:17:41 PM PDT 24 Aug 11 06:17:52 PM PDT 24 249065896 ps
T360 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.508751048 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:11 PM PDT 24 986785276 ps
T90 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3082739042 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:43 PM PDT 24 2072190842 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1071739974 Aug 11 06:17:44 PM PDT 24 Aug 11 06:17:54 PM PDT 24 261512674 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3967764943 Aug 11 06:17:49 PM PDT 24 Aug 11 06:17:59 PM PDT 24 250111757 ps
T363 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.69316966 Aug 11 06:18:00 PM PDT 24 Aug 11 06:18:10 PM PDT 24 249424652 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3526055816 Aug 11 06:17:30 PM PDT 24 Aug 11 06:17:38 PM PDT 24 168165454 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3786221529 Aug 11 06:17:50 PM PDT 24 Aug 11 06:18:28 PM PDT 24 1402066798 ps
T366 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1763461711 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:57 PM PDT 24 183781200 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1450869541 Aug 11 06:17:41 PM PDT 24 Aug 11 06:18:48 PM PDT 24 1561992993 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1488405259 Aug 11 06:17:49 PM PDT 24 Aug 11 06:17:57 PM PDT 24 2354586744 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3340187701 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:07 PM PDT 24 170713288 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2192051180 Aug 11 06:17:37 PM PDT 24 Aug 11 06:17:48 PM PDT 24 883732198 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1671131059 Aug 11 06:17:31 PM PDT 24 Aug 11 06:17:40 PM PDT 24 339963911 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3985041595 Aug 11 06:17:57 PM PDT 24 Aug 11 06:20:31 PM PDT 24 340626063 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.292134815 Aug 11 06:17:47 PM PDT 24 Aug 11 06:19:11 PM PDT 24 676688792 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2609031041 Aug 11 06:17:39 PM PDT 24 Aug 11 06:17:51 PM PDT 24 167613279 ps
T122 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1588688512 Aug 11 06:17:48 PM PDT 24 Aug 11 06:19:11 PM PDT 24 335122194 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.370133681 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:03 PM PDT 24 314754221 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1399592837 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:09 PM PDT 24 286381717 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.8351467 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:05 PM PDT 24 374106776 ps
T376 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3027407138 Aug 11 06:17:53 PM PDT 24 Aug 11 06:18:02 PM PDT 24 167411597 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2705737546 Aug 11 06:18:03 PM PDT 24 Aug 11 06:18:14 PM PDT 24 689601112 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3635259181 Aug 11 06:17:32 PM PDT 24 Aug 11 06:17:47 PM PDT 24 8865055946 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1578666693 Aug 11 06:17:47 PM PDT 24 Aug 11 06:18:01 PM PDT 24 985165831 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2408022160 Aug 11 06:17:48 PM PDT 24 Aug 11 06:18:01 PM PDT 24 665071341 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.919658819 Aug 11 06:17:54 PM PDT 24 Aug 11 06:18:51 PM PDT 24 4127247243 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2402382186 Aug 11 06:17:41 PM PDT 24 Aug 11 06:17:59 PM PDT 24 1497329575 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3554630484 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:03 PM PDT 24 661147334 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3272011952 Aug 11 06:17:54 PM PDT 24 Aug 11 06:18:06 PM PDT 24 688757478 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3192928626 Aug 11 06:17:39 PM PDT 24 Aug 11 06:17:49 PM PDT 24 260716150 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3594061180 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:56 PM PDT 24 172613385 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1908003969 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:12 PM PDT 24 1061360987 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1808727611 Aug 11 06:17:38 PM PDT 24 Aug 11 06:17:52 PM PDT 24 1249707353 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3121179230 Aug 11 06:17:49 PM PDT 24 Aug 11 06:17:57 PM PDT 24 183961806 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.470519477 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:50 PM PDT 24 174158677 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2245258850 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:08 PM PDT 24 249743439 ps
T119 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2807682068 Aug 11 06:17:57 PM PDT 24 Aug 11 06:20:38 PM PDT 24 6713322426 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2304724951 Aug 11 06:17:48 PM PDT 24 Aug 11 06:18:01 PM PDT 24 4136866957 ps
T91 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1523811727 Aug 11 06:17:55 PM PDT 24 Aug 11 06:19:03 PM PDT 24 7621115087 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1624593368 Aug 11 06:17:55 PM PDT 24 Aug 11 06:20:28 PM PDT 24 851689763 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4050625992 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:07 PM PDT 24 516243483 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3913453701 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:53 PM PDT 24 1051804795 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2899001347 Aug 11 06:17:58 PM PDT 24 Aug 11 06:19:04 PM PDT 24 1526553509 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1608016238 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:10 PM PDT 24 1086439834 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3981524530 Aug 11 06:17:49 PM PDT 24 Aug 11 06:17:59 PM PDT 24 986005746 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2388283753 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:05 PM PDT 24 192998217 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1310642453 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:57 PM PDT 24 187627074 ps
T396 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3105795479 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:06 PM PDT 24 273861353 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.711649963 Aug 11 06:17:57 PM PDT 24 Aug 11 06:18:09 PM PDT 24 248896776 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1204375545 Aug 11 06:17:49 PM PDT 24 Aug 11 06:18:02 PM PDT 24 487126411 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.339023998 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:13 PM PDT 24 1072688394 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2629046368 Aug 11 06:17:48 PM PDT 24 Aug 11 06:18:00 PM PDT 24 1874574451 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1252850269 Aug 11 06:17:51 PM PDT 24 Aug 11 06:19:14 PM PDT 24 1764935191 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.124008683 Aug 11 06:17:58 PM PDT 24 Aug 11 06:18:07 PM PDT 24 167598661 ps
T402 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1040327557 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:33 PM PDT 24 2771206102 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2677686651 Aug 11 06:18:02 PM PDT 24 Aug 11 06:18:12 PM PDT 24 985661411 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2191922795 Aug 11 06:17:56 PM PDT 24 Aug 11 06:18:11 PM PDT 24 1001840369 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4277423130 Aug 11 06:17:49 PM PDT 24 Aug 11 06:18:56 PM PDT 24 3119429768 ps
T405 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4027885245 Aug 11 06:18:01 PM PDT 24 Aug 11 06:18:39 PM PDT 24 726325933 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2082335790 Aug 11 06:17:54 PM PDT 24 Aug 11 06:18:04 PM PDT 24 261754617 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2799872957 Aug 11 06:17:58 PM PDT 24 Aug 11 06:19:19 PM PDT 24 1200036492 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1097057981 Aug 11 06:17:47 PM PDT 24 Aug 11 06:17:56 PM PDT 24 1267491479 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.832045462 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:09 PM PDT 24 174547901 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1291159849 Aug 11 06:17:31 PM PDT 24 Aug 11 06:18:09 PM PDT 24 715671483 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2908970512 Aug 11 06:18:03 PM PDT 24 Aug 11 06:19:24 PM PDT 24 2095013606 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2672370122 Aug 11 06:17:51 PM PDT 24 Aug 11 06:18:36 PM PDT 24 6349540330 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.531663293 Aug 11 06:17:48 PM PDT 24 Aug 11 06:17:58 PM PDT 24 1032798277 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.929864330 Aug 11 06:17:32 PM PDT 24 Aug 11 06:18:17 PM PDT 24 2081412853 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3366282351 Aug 11 06:17:58 PM PDT 24 Aug 11 06:19:22 PM PDT 24 381470223 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1142042119 Aug 11 06:17:46 PM PDT 24 Aug 11 06:17:59 PM PDT 24 252101771 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1326689017 Aug 11 06:17:53 PM PDT 24 Aug 11 06:18:03 PM PDT 24 547832898 ps
T418 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2736043624 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:40 PM PDT 24 2113172624 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2664968893 Aug 11 06:17:49 PM PDT 24 Aug 11 06:18:01 PM PDT 24 270843415 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2171445232 Aug 11 06:17:55 PM PDT 24 Aug 11 06:18:03 PM PDT 24 331970842 ps
T421 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2718912918 Aug 11 06:17:53 PM PDT 24 Aug 11 06:18:01 PM PDT 24 332485529 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4011041201 Aug 11 06:17:42 PM PDT 24 Aug 11 06:17:52 PM PDT 24 249884723 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2478255139 Aug 11 06:18:03 PM PDT 24 Aug 11 06:19:26 PM PDT 24 750391759 ps

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3254361172
Short name T7
Test name
Test status
Simulation time 40695826355 ps
CPU time 7293.11 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 08:53:29 PM PDT 24
Peak memory 233692 kb
Host smart-0deb5e39-5af4-482b-80ae-3b50ddf923f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254361172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3254361172
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2229564191
Short name T40
Test name
Test status
Simulation time 4914267711 ps
CPU time 334.29 seconds
Started Aug 11 06:51:49 PM PDT 24
Finished Aug 11 06:57:24 PM PDT 24
Peak memory 234884 kb
Host smart-d1ab5cc1-21ba-4634-96f4-39dd601805af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229564191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2229564191
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4045862334
Short name T3
Test name
Test status
Simulation time 20270316170 ps
CPU time 170.78 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:54:34 PM PDT 24
Peak memory 225344 kb
Host smart-77e3b36d-8d3a-4398-8c4b-97066e9e2346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045862334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4045862334
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2291875569
Short name T54
Test name
Test status
Simulation time 389709652 ps
CPU time 157.26 seconds
Started Aug 11 06:17:40 PM PDT 24
Finished Aug 11 06:20:18 PM PDT 24
Peak memory 215980 kb
Host smart-48a632cd-32e1-4869-9d0b-c73dd7a7a3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291875569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2291875569
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4293737736
Short name T22
Test name
Test status
Simulation time 1232819531 ps
CPU time 222.93 seconds
Started Aug 11 06:51:22 PM PDT 24
Finished Aug 11 06:55:05 PM PDT 24
Peak memory 239696 kb
Host smart-98ee229e-afd3-499a-a0fe-4455c307d53d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293737736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4293737736
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3740420056
Short name T69
Test name
Test status
Simulation time 662880811 ps
CPU time 8.28 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:55 PM PDT 24
Peak memory 211624 kb
Host smart-b60d9ea3-6025-469b-bf9c-3ff4122e2f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740420056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3740420056
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1019587712
Short name T55
Test name
Test status
Simulation time 386637806 ps
CPU time 155.08 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 219520 kb
Host smart-e30dcfda-0c4f-495d-837e-554cafdfe0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019587712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1019587712
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3415201993
Short name T60
Test name
Test status
Simulation time 1079341222 ps
CPU time 10.18 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:51:48 PM PDT 24
Peak memory 219136 kb
Host smart-fdbaa56b-5d0f-4210-9530-49cd64c02613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415201993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3415201993
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3285843625
Short name T113
Test name
Test status
Simulation time 393945758 ps
CPU time 84.05 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:19:21 PM PDT 24
Peak memory 214508 kb
Host smart-7e3b69c3-64fe-48b3-b5af-b9f05cb5a405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285843625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3285843625
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3759834987
Short name T143
Test name
Test status
Simulation time 507719024 ps
CPU time 23.09 seconds
Started Aug 11 06:51:17 PM PDT 24
Finished Aug 11 06:51:40 PM PDT 24
Peak memory 220032 kb
Host smart-21e094ca-3e96-4728-aea6-bbdf180f27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759834987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3759834987
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2755473797
Short name T230
Test name
Test status
Simulation time 3661360218 ps
CPU time 19.61 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:50 PM PDT 24
Peak memory 220180 kb
Host smart-1a2d5970-7c24-46b6-87d5-feeed7464592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755473797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2755473797
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2893217782
Short name T46
Test name
Test status
Simulation time 332560923 ps
CPU time 18.6 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220100 kb
Host smart-4137fcb4-4546-4965-8268-e33700c27fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893217782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2893217782
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3884736876
Short name T108
Test name
Test status
Simulation time 829350918 ps
CPU time 10.49 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 220060 kb
Host smart-79b4371d-b6fb-4be9-a028-3952f9a105ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884736876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3884736876
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.910686448
Short name T16
Test name
Test status
Simulation time 33526931884 ps
CPU time 618.74 seconds
Started Aug 11 06:51:20 PM PDT 24
Finished Aug 11 07:01:39 PM PDT 24
Peak memory 232564 kb
Host smart-b7cda716-60d1-419e-b6f0-697ed019ecd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910686448 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.910686448
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.186261028
Short name T112
Test name
Test status
Simulation time 4227350753 ps
CPU time 44.02 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:42 PM PDT 24
Peak memory 214876 kb
Host smart-2494fa5d-dce0-4d07-97ce-4d4f4582ab1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186261028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.186261028
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1678827980
Short name T30
Test name
Test status
Simulation time 606023038 ps
CPU time 31.44 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:52:18 PM PDT 24
Peak memory 220008 kb
Host smart-d62ab5fe-b470-43c5-9bdb-752e4c1303d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678827980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1678827980
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.838082795
Short name T94
Test name
Test status
Simulation time 697809600 ps
CPU time 10.67 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:02 PM PDT 24
Peak memory 220112 kb
Host smart-0c31d488-b0b1-489e-9509-a8f935817df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838082795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.838082795
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1197867741
Short name T334
Test name
Test status
Simulation time 984923103 ps
CPU time 14.51 seconds
Started Aug 11 06:17:29 PM PDT 24
Finished Aug 11 06:17:44 PM PDT 24
Peak memory 211460 kb
Host smart-2729cf1c-1e82-4ce3-810a-7fa04dacfc81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197867741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1197867741
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3635259181
Short name T378
Test name
Test status
Simulation time 8865055946 ps
CPU time 15.05 seconds
Started Aug 11 06:17:32 PM PDT 24
Finished Aug 11 06:17:47 PM PDT 24
Peak memory 211480 kb
Host smart-68467b32-ec5f-4a21-8de8-7477968db410
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635259181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3635259181
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1808727611
Short name T83
Test name
Test status
Simulation time 1249707353 ps
CPU time 13.4 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 211300 kb
Host smart-55f3d4e3-cbca-4a4c-a8ec-0a5faf51fd61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808727611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1808727611
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.866502099
Short name T351
Test name
Test status
Simulation time 189721548 ps
CPU time 10.3 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:43 PM PDT 24
Peak memory 218704 kb
Host smart-605560cd-54db-4e85-9395-ab473d129277
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866502099 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.866502099
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3526055816
Short name T364
Test name
Test status
Simulation time 168165454 ps
CPU time 8.5 seconds
Started Aug 11 06:17:30 PM PDT 24
Finished Aug 11 06:17:38 PM PDT 24
Peak memory 211344 kb
Host smart-42c6a3cb-b2b8-4b7c-a3a2-48a97094e78f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526055816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3526055816
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2192051180
Short name T369
Test name
Test status
Simulation time 883732198 ps
CPU time 10.13 seconds
Started Aug 11 06:17:37 PM PDT 24
Finished Aug 11 06:17:48 PM PDT 24
Peak memory 211220 kb
Host smart-a24320d8-0f7d-479c-979c-db8574ff1bcc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192051180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2192051180
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1820704344
Short name T329
Test name
Test status
Simulation time 721248159 ps
CPU time 7.99 seconds
Started Aug 11 06:17:33 PM PDT 24
Finished Aug 11 06:17:41 PM PDT 24
Peak memory 211252 kb
Host smart-1ce61bb8-3fde-47df-a585-7d4d535c9b6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820704344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1820704344
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1291159849
Short name T410
Test name
Test status
Simulation time 715671483 ps
CPU time 37.54 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 214460 kb
Host smart-36e98432-9470-47a7-b78e-85ac525031e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291159849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1291159849
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1671131059
Short name T370
Test name
Test status
Simulation time 339963911 ps
CPU time 8.49 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:17:40 PM PDT 24
Peak memory 211816 kb
Host smart-c9488556-9bd3-4f04-87aa-fc5337d7f4d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671131059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1671131059
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.383089877
Short name T354
Test name
Test status
Simulation time 175431101 ps
CPU time 11.27 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:49 PM PDT 24
Peak memory 218100 kb
Host smart-dce3176a-bdf4-463d-8849-ba36ab38db28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383089877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.383089877
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.120653183
Short name T53
Test name
Test status
Simulation time 394145605 ps
CPU time 159.71 seconds
Started Aug 11 06:17:31 PM PDT 24
Finished Aug 11 06:20:11 PM PDT 24
Peak memory 214960 kb
Host smart-a35bf24d-d459-488a-9ff6-55831ddc7663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120653183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.120653183
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.470519477
Short name T387
Test name
Test status
Simulation time 174158677 ps
CPU time 8.16 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:50 PM PDT 24
Peak memory 211392 kb
Host smart-f7cd817f-6ab8-4ae4-9955-5627eff7d55b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470519477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.470519477
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2472546490
Short name T359
Test name
Test status
Simulation time 249065896 ps
CPU time 10.45 seconds
Started Aug 11 06:17:41 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 211608 kb
Host smart-0b88f69d-a0f0-4c2b-801d-19c6f2821238
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472546490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2472546490
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2402382186
Short name T88
Test name
Test status
Simulation time 1497329575 ps
CPU time 17.29 seconds
Started Aug 11 06:17:41 PM PDT 24
Finished Aug 11 06:17:59 PM PDT 24
Peak memory 212472 kb
Host smart-fa975060-b9ed-4a63-98cb-a23b9c3d701b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402382186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2402382186
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2844321768
Short name T350
Test name
Test status
Simulation time 279499834 ps
CPU time 10.57 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:53 PM PDT 24
Peak memory 217152 kb
Host smart-99946604-8c06-4282-8c80-3ad6ea0bd6aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844321768 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2844321768
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1071739974
Short name T361
Test name
Test status
Simulation time 261512674 ps
CPU time 9.86 seconds
Started Aug 11 06:17:44 PM PDT 24
Finished Aug 11 06:17:54 PM PDT 24
Peak memory 211400 kb
Host smart-7fd9b626-6b92-45f3-bc7e-1ff90b18cb35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071739974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1071739974
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4011041201
Short name T422
Test name
Test status
Simulation time 249884723 ps
CPU time 9.88 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 211264 kb
Host smart-ff1c5087-69e0-458d-acdc-34dcc96e2f1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011041201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4011041201
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4106244538
Short name T327
Test name
Test status
Simulation time 498003841 ps
CPU time 9.89 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 211244 kb
Host smart-efcdf208-74f2-4d8a-b86b-aa84c7298171
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106244538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4106244538
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.929864330
Short name T414
Test name
Test status
Simulation time 2081412853 ps
CPU time 44.98 seconds
Started Aug 11 06:17:32 PM PDT 24
Finished Aug 11 06:18:17 PM PDT 24
Peak memory 214480 kb
Host smart-7023eb94-9162-4b55-9f46-fa88fe65fff6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929864330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.929864330
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3726331945
Short name T353
Test name
Test status
Simulation time 983020934 ps
CPU time 14.43 seconds
Started Aug 11 06:17:41 PM PDT 24
Finished Aug 11 06:17:56 PM PDT 24
Peak memory 211876 kb
Host smart-4aaff313-d6e0-4a5d-94c6-b02a22dd10b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726331945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3726331945
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3106924676
Short name T348
Test name
Test status
Simulation time 983882536 ps
CPU time 13.01 seconds
Started Aug 11 06:17:34 PM PDT 24
Finished Aug 11 06:17:48 PM PDT 24
Peak memory 217756 kb
Host smart-f7776275-995c-4c04-a61e-615eb6c2aea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106924676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3106924676
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2191922795
Short name T404
Test name
Test status
Simulation time 1001840369 ps
CPU time 15.29 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:11 PM PDT 24
Peak memory 216624 kb
Host smart-8b769f9b-836d-482c-9310-23596fcc9c4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191922795 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2191922795
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2718912918
Short name T421
Test name
Test status
Simulation time 332485529 ps
CPU time 8.17 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 211368 kb
Host smart-f25dc47d-8d58-43f7-bdc1-a31f27bf46b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718912918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2718912918
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1023761355
Short name T58
Test name
Test status
Simulation time 1523294099 ps
CPU time 64.52 seconds
Started Aug 11 06:17:59 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 214688 kb
Host smart-10cde61a-f0e0-4ccb-9631-f2ebbc452355
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023761355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1023761355
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1608016238
Short name T392
Test name
Test status
Simulation time 1086439834 ps
CPU time 13.5 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 213224 kb
Host smart-63435cec-0663-4a87-9097-5d79b17b5740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608016238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1608016238
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.339023998
Short name T399
Test name
Test status
Simulation time 1072688394 ps
CPU time 14.6 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:13 PM PDT 24
Peak memory 218180 kb
Host smart-82abc035-95d3-4f07-acb1-a470f8ce2cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339023998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.339023998
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3075893113
Short name T114
Test name
Test status
Simulation time 2770716193 ps
CPU time 152.68 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 214960 kb
Host smart-c08053d2-7201-408d-a5a8-223dad9d05ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075893113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3075893113
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1326689017
Short name T417
Test name
Test status
Simulation time 547832898 ps
CPU time 10.83 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 217336 kb
Host smart-510ab0f9-9d5a-40fb-87e6-9b278931be79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326689017 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1326689017
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1856880699
Short name T81
Test name
Test status
Simulation time 2060961472 ps
CPU time 9.72 seconds
Started Aug 11 06:17:51 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 211396 kb
Host smart-244f2b7c-58e8-44bb-aacd-94e854a7c98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856880699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1856880699
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1523811727
Short name T91
Test name
Test status
Simulation time 7621115087 ps
CPU time 66.98 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 216560 kb
Host smart-f8644148-89f7-465d-a7ab-b8c795789a00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523811727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1523811727
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2245258850
Short name T388
Test name
Test status
Simulation time 249743439 ps
CPU time 9.85 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 211728 kb
Host smart-930a1feb-be99-4864-9d18-ed48ae54b47b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245258850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2245258850
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3272011952
Short name T382
Test name
Test status
Simulation time 688757478 ps
CPU time 11.38 seconds
Started Aug 11 06:17:54 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 218368 kb
Host smart-8c21ba7f-dca5-4b65-ace5-b978f99ad132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272011952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3272011952
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3985041595
Short name T371
Test name
Test status
Simulation time 340626063 ps
CPU time 154.47 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:20:31 PM PDT 24
Peak memory 214780 kb
Host smart-5256ffb3-0bf6-40f8-a666-3f5cbf29694c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985041595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3985041595
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3105795479
Short name T396
Test name
Test status
Simulation time 273861353 ps
CPU time 10.67 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 214660 kb
Host smart-43508875-7c3d-44fa-85db-e229bf7c472a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105795479 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3105795479
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3027407138
Short name T376
Test name
Test status
Simulation time 167411597 ps
CPU time 8.1 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:18:02 PM PDT 24
Peak memory 211280 kb
Host smart-e78c8256-9c9a-4d09-abf6-b5d51a257c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027407138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3027407138
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.370133681
Short name T373
Test name
Test status
Simulation time 314754221 ps
CPU time 8.04 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 211436 kb
Host smart-d34cb2cc-c913-40bb-abdf-a4c094c3ce6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370133681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.370133681
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3340187701
Short name T368
Test name
Test status
Simulation time 170713288 ps
CPU time 11.48 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 217988 kb
Host smart-27ec1399-ecde-4a71-8e13-46dbbae1b490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340187701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3340187701
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2807682068
Short name T119
Test name
Test status
Simulation time 6713322426 ps
CPU time 161.23 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:20:38 PM PDT 24
Peak memory 215176 kb
Host smart-0f397ddf-c509-41cd-8e8d-f61d3236f94f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807682068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2807682068
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2082335790
Short name T406
Test name
Test status
Simulation time 261754617 ps
CPU time 10.57 seconds
Started Aug 11 06:17:54 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 216152 kb
Host smart-0db78891-e4a4-4939-8689-14b81bddf7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082335790 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2082335790
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3161097233
Short name T56
Test name
Test status
Simulation time 986099120 ps
CPU time 9.84 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 211548 kb
Host smart-4e38598a-773a-482b-92e9-64536a5d0e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161097233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3161097233
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.919658819
Short name T87
Test name
Test status
Simulation time 4127247243 ps
CPU time 56.48 seconds
Started Aug 11 06:17:54 PM PDT 24
Finished Aug 11 06:18:51 PM PDT 24
Peak memory 216572 kb
Host smart-1862cba2-1e08-47c1-b479-23f13c190e0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919658819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.919658819
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1953004785
Short name T104
Test name
Test status
Simulation time 353308904 ps
CPU time 8.47 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 212292 kb
Host smart-80aac193-5704-438f-9c47-e51b02b96d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953004785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1953004785
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2705152409
Short name T337
Test name
Test status
Simulation time 168480651 ps
CPU time 11.17 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 218108 kb
Host smart-abe684fc-d8f7-4922-a6dc-396928ef8150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705152409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2705152409
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3366282351
Short name T415
Test name
Test status
Simulation time 381470223 ps
CPU time 83.56 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:19:22 PM PDT 24
Peak memory 214392 kb
Host smart-0d2df35b-2e46-40f6-bc8e-471386434385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366282351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3366282351
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3411211808
Short name T335
Test name
Test status
Simulation time 183895597 ps
CPU time 8.95 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 217484 kb
Host smart-515390b2-4d75-4c48-99b8-dfb8109fd664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411211808 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3411211808
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.508751048
Short name T360
Test name
Test status
Simulation time 986785276 ps
CPU time 14.28 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:11 PM PDT 24
Peak memory 212080 kb
Host smart-1f114a5b-083f-4c2d-9538-4af9c08d46b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508751048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.508751048
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2899001347
Short name T391
Test name
Test status
Simulation time 1526553509 ps
CPU time 65.46 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:19:04 PM PDT 24
Peak memory 216552 kb
Host smart-332ce1c4-f464-443b-ad07-4e16c38b5cce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899001347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2899001347
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2171445232
Short name T420
Test name
Test status
Simulation time 331970842 ps
CPU time 8.32 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 211892 kb
Host smart-4a5d724a-7024-4704-9507-1d9d08f75c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171445232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2171445232
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1399592837
Short name T374
Test name
Test status
Simulation time 286381717 ps
CPU time 13.71 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 218200 kb
Host smart-1dd03639-52d2-4336-b9c7-babf59372642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399592837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1399592837
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3494188407
Short name T116
Test name
Test status
Simulation time 2185565369 ps
CPU time 86.72 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 213340 kb
Host smart-286a168d-c8e9-4fe7-8b51-d6b5c918349b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494188407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3494188407
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3467641353
Short name T347
Test name
Test status
Simulation time 534038496 ps
CPU time 10.44 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 217016 kb
Host smart-bf5c3d02-ee4e-4e91-bf4e-3ebe92552733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467641353 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3467641353
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.124008683
Short name T401
Test name
Test status
Simulation time 167598661 ps
CPU time 8.38 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 211276 kb
Host smart-1ce64353-968f-4639-9fcf-d19b0efe87f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124008683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.124008683
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3913453701
Short name T92
Test name
Test status
Simulation time 1051804795 ps
CPU time 54.83 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:53 PM PDT 24
Peak memory 215908 kb
Host smart-59bb4f53-4e42-4dd4-947b-8de39afe837d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913453701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3913453701
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4050625992
Short name T390
Test name
Test status
Simulation time 516243483 ps
CPU time 9.65 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 211948 kb
Host smart-0390f129-471a-48d0-8cc3-d618c0b7db59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050625992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4050625992
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.832045462
Short name T409
Test name
Test status
Simulation time 174547901 ps
CPU time 13.5 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 219404 kb
Host smart-d84afbe9-9512-4b63-8660-7c15761b0493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832045462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.832045462
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1624593368
Short name T123
Test name
Test status
Simulation time 851689763 ps
CPU time 152.82 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:20:28 PM PDT 24
Peak memory 214752 kb
Host smart-903e702c-79fc-4f8d-9262-2e656d7f2dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624593368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1624593368
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2388283753
Short name T394
Test name
Test status
Simulation time 192998217 ps
CPU time 10.3 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 218472 kb
Host smart-05bc4ff2-686f-4e45-a41e-8f02ffe2f6c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388283753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2388283753
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3414011205
Short name T105
Test name
Test status
Simulation time 167621754 ps
CPU time 8.12 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:06 PM PDT 24
Peak memory 211328 kb
Host smart-0af0f4ad-2258-40e4-aa0b-29d9cbdea80a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414011205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3414011205
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3082739042
Short name T90
Test name
Test status
Simulation time 2072190842 ps
CPU time 44.33 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:43 PM PDT 24
Peak memory 214380 kb
Host smart-05d6548b-f83f-4839-9d69-7a5da698a768
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082739042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3082739042
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3413290720
Short name T66
Test name
Test status
Simulation time 533512046 ps
CPU time 13.69 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 213116 kb
Host smart-88ba5778-ff08-4964-9214-7b766394a24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413290720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3413290720
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.711649963
Short name T397
Test name
Test status
Simulation time 248896776 ps
CPU time 12.5 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 217976 kb
Host smart-9a1c870d-4d52-4074-9b90-834f87b80c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711649963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.711649963
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.931488353
Short name T357
Test name
Test status
Simulation time 1674153500 ps
CPU time 83.86 seconds
Started Aug 11 06:17:57 PM PDT 24
Finished Aug 11 06:19:21 PM PDT 24
Peak memory 213404 kb
Host smart-f067086f-6011-4837-ab48-299ea6ca488e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931488353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.931488353
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2482285415
Short name T338
Test name
Test status
Simulation time 702804347 ps
CPU time 9.11 seconds
Started Aug 11 06:18:04 PM PDT 24
Finished Aug 11 06:18:13 PM PDT 24
Peak memory 217664 kb
Host smart-155f86ef-8dfa-4fcb-99a5-db52e2a1b139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482285415 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2482285415
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4167787494
Short name T336
Test name
Test status
Simulation time 591596421 ps
CPU time 8.18 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 211768 kb
Host smart-aa8bb959-9b61-435f-b734-b26a11022231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167787494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4167787494
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1981080543
Short name T71
Test name
Test status
Simulation time 1587235077 ps
CPU time 64.79 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:19:03 PM PDT 24
Peak memory 215912 kb
Host smart-c33494ff-9027-4f95-ba5a-c02ff9eac1ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981080543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1981080543
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1908003969
Short name T385
Test name
Test status
Simulation time 1061360987 ps
CPU time 13.89 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 213196 kb
Host smart-565f28f3-c22c-4997-b7b1-bbdd0088b24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908003969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1908003969
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2169310147
Short name T328
Test name
Test status
Simulation time 953254863 ps
CPU time 13.31 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 219348 kb
Host smart-4345cbdb-6f9f-4b41-8acb-3fa6b3f0357a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169310147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2169310147
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2591454939
Short name T330
Test name
Test status
Simulation time 259726311 ps
CPU time 10.42 seconds
Started Aug 11 06:18:01 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 216640 kb
Host smart-cbc3f243-3fe2-42c6-a01a-b47968890f4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591454939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2591454939
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2677686651
Short name T403
Test name
Test status
Simulation time 985661411 ps
CPU time 9.78 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:12 PM PDT 24
Peak memory 211168 kb
Host smart-3cf8e8d8-f7e2-4867-81ef-1e96192ae5de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677686651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2677686651
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3556610240
Short name T89
Test name
Test status
Simulation time 1073773467 ps
CPU time 57.05 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:19:00 PM PDT 24
Peak memory 215100 kb
Host smart-86aea128-4454-4b3d-841f-12d26a76af1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556610240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3556610240
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2235722838
Short name T342
Test name
Test status
Simulation time 257428787 ps
CPU time 9.78 seconds
Started Aug 11 06:18:02 PM PDT 24
Finished Aug 11 06:18:11 PM PDT 24
Peak memory 212136 kb
Host smart-3f7ab44a-2c46-4b1b-b225-f625b2735b3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235722838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2235722838
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3944603710
Short name T331
Test name
Test status
Simulation time 260446422 ps
CPU time 13.47 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 218212 kb
Host smart-6c435f4f-e09e-4592-9837-9b349ae2d6d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944603710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3944603710
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2478255139
Short name T423
Test name
Test status
Simulation time 750391759 ps
CPU time 82.54 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:19:26 PM PDT 24
Peak memory 214200 kb
Host smart-3985812b-ec68-4c1b-8932-43dda240a487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478255139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2478255139
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3755227269
Short name T325
Test name
Test status
Simulation time 360070139 ps
CPU time 8.72 seconds
Started Aug 11 06:18:01 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 216592 kb
Host smart-8102a12e-f9b5-4a3b-ad07-887cd197e2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755227269 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3755227269
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1360021731
Short name T85
Test name
Test status
Simulation time 1100571580 ps
CPU time 8.29 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:08 PM PDT 24
Peak memory 211740 kb
Host smart-c4564593-cb02-499b-9e6e-f9b963fbfd2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360021731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1360021731
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4027885245
Short name T405
Test name
Test status
Simulation time 726325933 ps
CPU time 38.3 seconds
Started Aug 11 06:18:01 PM PDT 24
Finished Aug 11 06:18:39 PM PDT 24
Peak memory 214436 kb
Host smart-9c8f21a4-3be2-4703-8407-25a9418adcd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027885245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4027885245
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.69316966
Short name T363
Test name
Test status
Simulation time 249424652 ps
CPU time 10.07 seconds
Started Aug 11 06:18:00 PM PDT 24
Finished Aug 11 06:18:10 PM PDT 24
Peak memory 211888 kb
Host smart-0f6d319d-cd20-43d4-8613-723d440259c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69316966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ct
rl_same_csr_outstanding.69316966
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2705737546
Short name T377
Test name
Test status
Simulation time 689601112 ps
CPU time 11.16 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:18:14 PM PDT 24
Peak memory 217988 kb
Host smart-1fd0f6fe-4916-498a-81a1-2b68ce28f9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705737546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2705737546
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2908970512
Short name T411
Test name
Test status
Simulation time 2095013606 ps
CPU time 80.97 seconds
Started Aug 11 06:18:03 PM PDT 24
Finished Aug 11 06:19:24 PM PDT 24
Peak memory 214580 kb
Host smart-4bcbb52c-9458-432e-aa85-99dd247c1703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908970512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2908970512
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.971073387
Short name T333
Test name
Test status
Simulation time 1374261990 ps
CPU time 8.38 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:50 PM PDT 24
Peak memory 211640 kb
Host smart-79dcda13-5e55-40ba-82a4-5d6f9f931d2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971073387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.971073387
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2883999755
Short name T358
Test name
Test status
Simulation time 2747750986 ps
CPU time 10.12 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:48 PM PDT 24
Peak memory 211368 kb
Host smart-67a084c9-0a41-4516-b502-91547d4719a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883999755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2883999755
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1906480978
Short name T107
Test name
Test status
Simulation time 668372761 ps
CPU time 11.78 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:50 PM PDT 24
Peak memory 212708 kb
Host smart-e7790877-9d8e-44f1-b693-b1cf6cdbe65e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906480978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1906480978
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.576422955
Short name T324
Test name
Test status
Simulation time 267043014 ps
CPU time 10.94 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:53 PM PDT 24
Peak memory 217128 kb
Host smart-2d700a06-635c-4ca2-87f1-ca6cc7d967a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576422955 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.576422955
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2709970612
Short name T65
Test name
Test status
Simulation time 248532620 ps
CPU time 9.63 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:52 PM PDT 24
Peak memory 211340 kb
Host smart-fb2bc366-7cd2-4575-b045-e9b26df65f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709970612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2709970612
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1653279572
Short name T322
Test name
Test status
Simulation time 1034684131 ps
CPU time 9.92 seconds
Started Aug 11 06:17:39 PM PDT 24
Finished Aug 11 06:17:49 PM PDT 24
Peak memory 211208 kb
Host smart-cd0edb10-d169-4c77-bc54-b54ed449fab1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653279572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1653279572
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4203960168
Short name T326
Test name
Test status
Simulation time 986155358 ps
CPU time 9.95 seconds
Started Aug 11 06:17:39 PM PDT 24
Finished Aug 11 06:17:49 PM PDT 24
Peak memory 211196 kb
Host smart-007282c9-58ef-45d9-813f-0c26c6655d39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203960168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4203960168
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3815595271
Short name T84
Test name
Test status
Simulation time 4060666687 ps
CPU time 44.78 seconds
Started Aug 11 06:17:37 PM PDT 24
Finished Aug 11 06:18:22 PM PDT 24
Peak memory 215480 kb
Host smart-aed06cee-78a1-4cf3-a5c2-60193709d818
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815595271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3815595271
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2472600810
Short name T106
Test name
Test status
Simulation time 833056277 ps
CPU time 12.1 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:54 PM PDT 24
Peak memory 213212 kb
Host smart-4c67d463-4ec6-454a-9970-f56178726562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472600810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2472600810
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3594061180
Short name T384
Test name
Test status
Simulation time 172613385 ps
CPU time 13.19 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:17:56 PM PDT 24
Peak memory 218260 kb
Host smart-ee74450d-c40f-4008-ba44-642067604d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594061180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3594061180
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2256498724
Short name T120
Test name
Test status
Simulation time 334801291 ps
CPU time 83.04 seconds
Started Aug 11 06:17:42 PM PDT 24
Finished Aug 11 06:19:05 PM PDT 24
Peak memory 213416 kb
Host smart-abdf4df4-65f1-471e-968a-d1237175dc5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256498724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2256498724
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.431692380
Short name T82
Test name
Test status
Simulation time 1031794725 ps
CPU time 9.69 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 211528 kb
Host smart-179dc2be-5bc7-41a6-80da-7db98f4728c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431692380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.431692380
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3246934998
Short name T356
Test name
Test status
Simulation time 1032484490 ps
CPU time 10.71 seconds
Started Aug 11 06:17:44 PM PDT 24
Finished Aug 11 06:17:55 PM PDT 24
Peak memory 211600 kb
Host smart-4d2616fa-38fe-4c7e-b0ac-392b1572e04c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246934998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3246934998
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.748591114
Short name T355
Test name
Test status
Simulation time 234388821 ps
CPU time 11.63 seconds
Started Aug 11 06:17:46 PM PDT 24
Finished Aug 11 06:17:58 PM PDT 24
Peak memory 212688 kb
Host smart-c0f6ed2d-e74a-4c41-923e-9858e136b56e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748591114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.748591114
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3121179230
Short name T386
Test name
Test status
Simulation time 183961806 ps
CPU time 8.87 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 217004 kb
Host smart-0b5047e3-2617-45bb-94dc-028e75dad6cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121179230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3121179230
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3192928626
Short name T383
Test name
Test status
Simulation time 260716150 ps
CPU time 10.12 seconds
Started Aug 11 06:17:39 PM PDT 24
Finished Aug 11 06:17:49 PM PDT 24
Peak memory 211172 kb
Host smart-4f49188a-089a-4208-b2de-7919ab49224a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192928626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3192928626
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.186863456
Short name T352
Test name
Test status
Simulation time 1772686909 ps
CPU time 9.5 seconds
Started Aug 11 06:17:38 PM PDT 24
Finished Aug 11 06:17:48 PM PDT 24
Peak memory 211200 kb
Host smart-d970019e-c421-4ed8-9c4a-5f172d60aa39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186863456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
186863456
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1450869541
Short name T86
Test name
Test status
Simulation time 1561992993 ps
CPU time 66.85 seconds
Started Aug 11 06:17:41 PM PDT 24
Finished Aug 11 06:18:48 PM PDT 24
Peak memory 214572 kb
Host smart-fa848b64-34c4-46f8-8d5d-8a96a42d23a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450869541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1450869541
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2629046368
Short name T400
Test name
Test status
Simulation time 1874574451 ps
CPU time 11.77 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:18:00 PM PDT 24
Peak memory 213308 kb
Host smart-1bf3002f-34a4-4cdd-ae5b-87ac4d48337a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629046368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2629046368
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2609031041
Short name T372
Test name
Test status
Simulation time 167613279 ps
CPU time 11.75 seconds
Started Aug 11 06:17:39 PM PDT 24
Finished Aug 11 06:17:51 PM PDT 24
Peak memory 218016 kb
Host smart-4c04b9f1-f48a-4a40-9864-1762dfae4b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609031041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2609031041
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3554630484
Short name T381
Test name
Test status
Simulation time 661147334 ps
CPU time 8.33 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:03 PM PDT 24
Peak memory 211628 kb
Host smart-14d3bde2-d6a6-44c1-9b9f-7b9cb1aee732
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554630484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3554630484
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.400806693
Short name T332
Test name
Test status
Simulation time 260908844 ps
CPU time 10.19 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:58 PM PDT 24
Peak memory 211328 kb
Host smart-0b79933b-671d-4074-ab93-1d516246e7d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400806693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.400806693
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2234205038
Short name T70
Test name
Test status
Simulation time 2504387423 ps
CPU time 13.22 seconds
Started Aug 11 06:17:51 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 211048 kb
Host smart-243eae31-edcc-440d-8daa-b478e4e11631
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234205038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2234205038
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1310642453
Short name T395
Test name
Test status
Simulation time 187627074 ps
CPU time 9.55 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 218324 kb
Host smart-6d8bf37a-0c13-49e2-aae1-cc8b95be256b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310642453 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1310642453
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3701885536
Short name T67
Test name
Test status
Simulation time 2236617418 ps
CPU time 9.96 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:17:58 PM PDT 24
Peak memory 211720 kb
Host smart-861a983b-ea31-42ee-8e9f-769c31959d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701885536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3701885536
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1488405259
Short name T367
Test name
Test status
Simulation time 2354586744 ps
CPU time 8.17 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 211304 kb
Host smart-5bb1751a-88a0-4107-8550-3c1d5f2c778f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488405259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1488405259
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1461574615
Short name T323
Test name
Test status
Simulation time 660812946 ps
CPU time 8.43 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:56 PM PDT 24
Peak memory 211260 kb
Host smart-3c73f7e2-b3d3-4e3b-b69a-4186117ab78e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461574615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1461574615
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3786221529
Short name T365
Test name
Test status
Simulation time 1402066798 ps
CPU time 37.43 seconds
Started Aug 11 06:17:50 PM PDT 24
Finished Aug 11 06:18:28 PM PDT 24
Peak memory 214364 kb
Host smart-0f5bf075-ee96-4d7b-bef7-eef910c9ed88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786221529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3786221529
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3967764943
Short name T362
Test name
Test status
Simulation time 250111757 ps
CPU time 10.02 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:17:59 PM PDT 24
Peak memory 211776 kb
Host smart-858580cd-3e88-492b-bc9f-ed3527b7cb09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967764943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3967764943
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2408022160
Short name T380
Test name
Test status
Simulation time 665071341 ps
CPU time 12.55 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 218176 kb
Host smart-342f9699-d01c-4768-a86b-f59e12699016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408022160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2408022160
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.292134815
Short name T115
Test name
Test status
Simulation time 676688792 ps
CPU time 84.24 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 213172 kb
Host smart-c744bc42-db5b-4c10-968a-7fcea7c19022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292134815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.292134815
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4103125352
Short name T341
Test name
Test status
Simulation time 1065924581 ps
CPU time 15.34 seconds
Started Aug 11 06:17:50 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 218772 kb
Host smart-7203ddfb-e5cc-4113-ab47-8e590ba11ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103125352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4103125352
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1097057981
Short name T408
Test name
Test status
Simulation time 1267491479 ps
CPU time 7.99 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:56 PM PDT 24
Peak memory 211704 kb
Host smart-c56273da-8126-48b4-aa45-cb30c4216d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097057981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1097057981
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4277423130
Short name T93
Test name
Test status
Simulation time 3119429768 ps
CPU time 67.18 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:18:56 PM PDT 24
Peak memory 215584 kb
Host smart-7b0c070a-cfe8-4ccf-8af7-9f5648382301
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277423130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4277423130
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1578666693
Short name T379
Test name
Test status
Simulation time 985165831 ps
CPU time 14.56 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 211984 kb
Host smart-866826e1-b5b5-4e39-aa39-57d1c7a1d1a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578666693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1578666693
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2304724951
Short name T389
Test name
Test status
Simulation time 4136866957 ps
CPU time 13.16 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 217932 kb
Host smart-3fea4938-7779-4002-a217-8ba341efb5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304724951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2304724951
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3051585298
Short name T121
Test name
Test status
Simulation time 334169747 ps
CPU time 155.96 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:20:23 PM PDT 24
Peak memory 214988 kb
Host smart-7e88ba1c-0e1f-412b-adb9-d6e8a0291d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051585298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3051585298
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2928819354
Short name T346
Test name
Test status
Simulation time 1219443836 ps
CPU time 10.88 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:58 PM PDT 24
Peak memory 218120 kb
Host smart-b8c5b5f4-6b3d-4e9a-8a64-7209d952747f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928819354 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2928819354
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3981524530
Short name T393
Test name
Test status
Simulation time 986005746 ps
CPU time 9.84 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:17:59 PM PDT 24
Peak memory 211360 kb
Host smart-234db3cd-aa34-492d-a65e-3f958dbe84ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981524530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3981524530
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2672370122
Short name T412
Test name
Test status
Simulation time 6349540330 ps
CPU time 44.1 seconds
Started Aug 11 06:17:51 PM PDT 24
Finished Aug 11 06:18:36 PM PDT 24
Peak memory 215048 kb
Host smart-a5715261-efd4-44d0-bdab-2b0f479c65a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672370122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2672370122
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1057182518
Short name T349
Test name
Test status
Simulation time 251615432 ps
CPU time 9.84 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 211776 kb
Host smart-a3946f34-a61a-4fc2-9b89-fd636b0cd0e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057182518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1057182518
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1667708002
Short name T344
Test name
Test status
Simulation time 486971354 ps
CPU time 12.29 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:18:02 PM PDT 24
Peak memory 218260 kb
Host smart-1a5534b9-0b55-4b98-b5d5-a4358d3791f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667708002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1667708002
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1588688512
Short name T122
Test name
Test status
Simulation time 335122194 ps
CPU time 83.02 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:19:11 PM PDT 24
Peak memory 219464 kb
Host smart-17d765d1-696b-44d7-ad52-016832109630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588688512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1588688512
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1763461711
Short name T366
Test name
Test status
Simulation time 183781200 ps
CPU time 9.78 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 218396 kb
Host smart-ef755340-03fd-4335-8aec-4dcfb82995ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763461711 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1763461711
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4098376120
Short name T340
Test name
Test status
Simulation time 261358849 ps
CPU time 10.03 seconds
Started Aug 11 06:17:50 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 211280 kb
Host smart-8b5685a0-a5a7-4e98-86b8-6d1ceedffff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098376120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4098376120
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2298166880
Short name T72
Test name
Test status
Simulation time 1027370346 ps
CPU time 43.78 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:18:33 PM PDT 24
Peak memory 214308 kb
Host smart-593aee3f-a0d4-40af-bbc8-1c6db9caf2f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298166880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2298166880
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1684445782
Short name T343
Test name
Test status
Simulation time 674290301 ps
CPU time 11.6 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:07 PM PDT 24
Peak memory 213072 kb
Host smart-76637171-940d-4474-ba89-c6da65fabf53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684445782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1684445782
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1204375545
Short name T398
Test name
Test status
Simulation time 487126411 ps
CPU time 13.59 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:18:02 PM PDT 24
Peak memory 218184 kb
Host smart-51bdcb5c-5dc7-4817-9eb5-b16e31974822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204375545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1204375545
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.201421034
Short name T118
Test name
Test status
Simulation time 275069966 ps
CPU time 81.07 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:19:08 PM PDT 24
Peak memory 219480 kb
Host smart-8096d82a-8a08-4995-b69f-6d0d8936fae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201421034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.201421034
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2664968893
Short name T419
Test name
Test status
Simulation time 270843415 ps
CPU time 11.64 seconds
Started Aug 11 06:17:49 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 218368 kb
Host smart-7cd13448-25ee-44fd-9fbc-5081906d045d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664968893 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2664968893
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.531663293
Short name T413
Test name
Test status
Simulation time 1032798277 ps
CPU time 9.8 seconds
Started Aug 11 06:17:48 PM PDT 24
Finished Aug 11 06:17:58 PM PDT 24
Peak memory 211660 kb
Host smart-00e2f574-e3ec-48bd-8375-f54f43593b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531663293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.531663293
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2736043624
Short name T418
Test name
Test status
Simulation time 2113172624 ps
CPU time 44.5 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:40 PM PDT 24
Peak memory 214684 kb
Host smart-dc147928-3d42-4de5-a91a-e2eeae1502fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736043624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2736043624
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1142042119
Short name T416
Test name
Test status
Simulation time 252101771 ps
CPU time 13.42 seconds
Started Aug 11 06:17:46 PM PDT 24
Finished Aug 11 06:17:59 PM PDT 24
Peak memory 213080 kb
Host smart-add7387a-5135-464c-bfc9-88063ec14fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142042119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1142042119
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1190264064
Short name T339
Test name
Test status
Simulation time 347917694 ps
CPU time 13.14 seconds
Started Aug 11 06:17:47 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 218316 kb
Host smart-75b9fb52-bdd1-419d-b58f-296a93d53fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190264064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1190264064
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1252850269
Short name T117
Test name
Test status
Simulation time 1764935191 ps
CPU time 82.4 seconds
Started Aug 11 06:17:51 PM PDT 24
Finished Aug 11 06:19:14 PM PDT 24
Peak memory 214476 kb
Host smart-3b3969d6-e3c9-4207-b981-f55843e26410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252850269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1252850269
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.8351467
Short name T375
Test name
Test status
Simulation time 374106776 ps
CPU time 9.01 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:05 PM PDT 24
Peak memory 217220 kb
Host smart-edb49133-7a50-42ea-927a-b89cc233669e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8351467 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.8351467
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2033327970
Short name T57
Test name
Test status
Simulation time 178853426 ps
CPU time 8.28 seconds
Started Aug 11 06:17:53 PM PDT 24
Finished Aug 11 06:18:01 PM PDT 24
Peak memory 211656 kb
Host smart-f6d5180d-d5b2-4297-a162-d5147b5fc611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033327970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2033327970
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1040327557
Short name T402
Test name
Test status
Simulation time 2771206102 ps
CPU time 38.22 seconds
Started Aug 11 06:17:55 PM PDT 24
Finished Aug 11 06:18:33 PM PDT 24
Peak memory 213488 kb
Host smart-da779d86-42d3-4842-b1cb-22ec3d688ee1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040327557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1040327557
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1499598743
Short name T68
Test name
Test status
Simulation time 252753391 ps
CPU time 9.95 seconds
Started Aug 11 06:17:54 PM PDT 24
Finished Aug 11 06:18:04 PM PDT 24
Peak memory 212168 kb
Host smart-a4d0804f-88e5-4ffc-8265-49924b332d82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499598743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1499598743
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.57237652
Short name T345
Test name
Test status
Simulation time 345083746 ps
CPU time 12.6 seconds
Started Aug 11 06:17:56 PM PDT 24
Finished Aug 11 06:18:09 PM PDT 24
Peak memory 217948 kb
Host smart-bc009ee8-1daa-4cf8-80cb-b63bf95db806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57237652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.57237652
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2799872957
Short name T407
Test name
Test status
Simulation time 1200036492 ps
CPU time 81.33 seconds
Started Aug 11 06:17:58 PM PDT 24
Finished Aug 11 06:19:19 PM PDT 24
Peak memory 213112 kb
Host smart-d5567853-cb3c-43f8-adfe-7092cfb0b7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799872957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2799872957
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1243132999
Short name T169
Test name
Test status
Simulation time 405756832 ps
CPU time 8.43 seconds
Started Aug 11 06:51:19 PM PDT 24
Finished Aug 11 06:51:28 PM PDT 24
Peak memory 219152 kb
Host smart-6638b60c-1883-41dd-826a-74b4093859d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243132999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1243132999
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1422631945
Short name T124
Test name
Test status
Simulation time 15609622488 ps
CPU time 200.65 seconds
Started Aug 11 06:51:20 PM PDT 24
Finished Aug 11 06:54:40 PM PDT 24
Peak memory 237824 kb
Host smart-7f304c37-f23f-47ee-b07c-4fab1b5ae270
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422631945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1422631945
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1130889755
Short name T173
Test name
Test status
Simulation time 258513820 ps
CPU time 11.94 seconds
Started Aug 11 06:51:15 PM PDT 24
Finished Aug 11 06:51:27 PM PDT 24
Peak memory 220092 kb
Host smart-10c33ead-d4ad-4779-9fde-ab5923076374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130889755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1130889755
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2687988049
Short name T23
Test name
Test status
Simulation time 658584251 ps
CPU time 227.09 seconds
Started Aug 11 06:51:21 PM PDT 24
Finished Aug 11 06:55:08 PM PDT 24
Peak memory 236956 kb
Host smart-03758f2b-ae7f-4d9e-9640-873c854b2502
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687988049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2687988049
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4247641486
Short name T308
Test name
Test status
Simulation time 274163256 ps
CPU time 12.16 seconds
Started Aug 11 06:51:17 PM PDT 24
Finished Aug 11 06:51:29 PM PDT 24
Peak memory 220080 kb
Host smart-1520a0e3-27fd-4f01-aa30-fb9e9855fc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247641486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4247641486
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1490750676
Short name T99
Test name
Test status
Simulation time 7576853712 ps
CPU time 20.22 seconds
Started Aug 11 06:51:18 PM PDT 24
Finished Aug 11 06:51:38 PM PDT 24
Peak memory 220144 kb
Host smart-3917b744-d49f-4cf4-95fa-bfa27cec9208
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490750676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1490750676
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3378716199
Short name T292
Test name
Test status
Simulation time 507551692 ps
CPU time 10.39 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:27 PM PDT 24
Peak memory 219140 kb
Host smart-9c5f4ccc-b660-437f-8ad8-ac697a48cd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378716199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3378716199
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4068179050
Short name T12
Test name
Test status
Simulation time 37985770750 ps
CPU time 287.79 seconds
Started Aug 11 06:51:17 PM PDT 24
Finished Aug 11 06:56:05 PM PDT 24
Peak memory 240640 kb
Host smart-976a5ad1-e5bb-40b0-b9f0-ea7bb7856b45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068179050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4068179050
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4134481596
Short name T164
Test name
Test status
Simulation time 675880866 ps
CPU time 19.38 seconds
Started Aug 11 06:51:15 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 220100 kb
Host smart-abb581a1-af27-4de4-a703-46f7d16a7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134481596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4134481596
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.415285895
Short name T102
Test name
Test status
Simulation time 666457886 ps
CPU time 10.65 seconds
Started Aug 11 06:51:15 PM PDT 24
Finished Aug 11 06:51:26 PM PDT 24
Peak memory 220092 kb
Host smart-681ada5d-0278-4720-85a8-8b6915dff649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415285895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.415285895
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.489019469
Short name T28
Test name
Test status
Simulation time 302503245 ps
CPU time 114.59 seconds
Started Aug 11 06:51:21 PM PDT 24
Finished Aug 11 06:53:16 PM PDT 24
Peak memory 240088 kb
Host smart-440158a7-a6d1-4883-bbc8-f60df2006fef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489019469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.489019469
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3331199322
Short name T133
Test name
Test status
Simulation time 538781953 ps
CPU time 12.25 seconds
Started Aug 11 06:51:17 PM PDT 24
Finished Aug 11 06:51:29 PM PDT 24
Peak memory 220096 kb
Host smart-74dedd5e-312b-4cd9-8163-9d8bb6ddc92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331199322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3331199322
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3215984215
Short name T245
Test name
Test status
Simulation time 1081975169 ps
CPU time 38.53 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 219868 kb
Host smart-a91c98d1-6682-42eb-805e-efa92cc0df1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215984215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3215984215
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4087439121
Short name T319
Test name
Test status
Simulation time 184060173 ps
CPU time 10.48 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:37 PM PDT 24
Peak memory 220300 kb
Host smart-1ac3063b-2270-4289-b77e-01d5d7891c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087439121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4087439121
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.545079549
Short name T203
Test name
Test status
Simulation time 2408351842 ps
CPU time 12.5 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:39 PM PDT 24
Peak memory 220084 kb
Host smart-67769d31-a0b6-4ce3-b28b-1ad3ea054af5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545079549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.545079549
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2398873069
Short name T202
Test name
Test status
Simulation time 172753237 ps
CPU time 8.36 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:51:46 PM PDT 24
Peak memory 218972 kb
Host smart-970dab62-3b81-40a3-9f9f-457a37aebbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398873069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2398873069
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2320132210
Short name T318
Test name
Test status
Simulation time 4889326561 ps
CPU time 308.32 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:56:36 PM PDT 24
Peak memory 237148 kb
Host smart-090f1abd-64c8-4f29-a88b-81d8a5394ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320132210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2320132210
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.645596269
Short name T156
Test name
Test status
Simulation time 991761513 ps
CPU time 22.77 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:51:51 PM PDT 24
Peak memory 220068 kb
Host smart-5c489d2f-7eea-48de-9ad1-8b229b23e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645596269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.645596269
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.981947920
Short name T144
Test name
Test status
Simulation time 179360507 ps
CPU time 10.43 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 220112 kb
Host smart-07afcd51-4e07-49f2-b2bb-a37ad43fb7e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981947920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.981947920
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1329223773
Short name T127
Test name
Test status
Simulation time 392391186 ps
CPU time 17.65 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 220056 kb
Host smart-2f4e5c72-45d0-4d27-8629-5c0aca9bdb21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329223773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1329223773
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3602005294
Short name T138
Test name
Test status
Simulation time 167629781 ps
CPU time 8.4 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 219104 kb
Host smart-a762edf7-e4dd-4e17-95f5-2a8824820ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602005294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3602005294
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1031339434
Short name T241
Test name
Test status
Simulation time 2687118310 ps
CPU time 167.23 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:54:25 PM PDT 24
Peak memory 220348 kb
Host smart-4f543f0e-8175-4728-a784-04c5f46309cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031339434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1031339434
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2918935270
Short name T26
Test name
Test status
Simulation time 519164949 ps
CPU time 22.41 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:49 PM PDT 24
Peak memory 220024 kb
Host smart-b6e9d4ea-93d1-4aa4-b085-d6f0d388d440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918935270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2918935270
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3335921760
Short name T219
Test name
Test status
Simulation time 1069987031 ps
CPU time 23.45 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:50 PM PDT 24
Peak memory 220028 kb
Host smart-853f7663-634a-4d68-8246-2871b676f765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335921760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3335921760
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3399219492
Short name T196
Test name
Test status
Simulation time 174848197 ps
CPU time 8.55 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 219180 kb
Host smart-66367539-942d-476a-a7bc-9ed08f2fa38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399219492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3399219492
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3784332823
Short name T289
Test name
Test status
Simulation time 11476064636 ps
CPU time 212.75 seconds
Started Aug 11 06:51:36 PM PDT 24
Finished Aug 11 06:55:09 PM PDT 24
Peak memory 234556 kb
Host smart-9b812cc8-3770-4b5c-9809-acf11635f803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784332823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3784332823
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2709197862
Short name T251
Test name
Test status
Simulation time 517447641 ps
CPU time 22.5 seconds
Started Aug 11 06:51:39 PM PDT 24
Finished Aug 11 06:52:01 PM PDT 24
Peak memory 220096 kb
Host smart-cfd2927d-143e-48cc-b84b-3759f3c8329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709197862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2709197862
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3268835975
Short name T307
Test name
Test status
Simulation time 1025097890 ps
CPU time 12.77 seconds
Started Aug 11 06:51:39 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 220040 kb
Host smart-1efe1bd7-f299-40b7-b9dc-e814a5f39947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268835975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3268835975
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1502521851
Short name T257
Test name
Test status
Simulation time 2261494548 ps
CPU time 31.53 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:52:10 PM PDT 24
Peak memory 220012 kb
Host smart-b78324b4-0aef-4d1f-a176-29a700c4d7bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502521851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1502521851
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3573798937
Short name T232
Test name
Test status
Simulation time 951530899 ps
CPU time 10.1 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 219036 kb
Host smart-c09f3d28-d36e-4e74-8976-377061f03f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573798937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3573798937
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2333813287
Short name T295
Test name
Test status
Simulation time 5892837979 ps
CPU time 100.83 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:53:19 PM PDT 24
Peak memory 220356 kb
Host smart-c84bb4a5-6a23-477c-bcbc-34c6e159e69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333813287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2333813287
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1400254725
Short name T184
Test name
Test status
Simulation time 333583074 ps
CPU time 18.86 seconds
Started Aug 11 06:51:36 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 220088 kb
Host smart-87c8e5aa-c418-495c-a8c1-dc093ba0ebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400254725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1400254725
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2713510994
Short name T214
Test name
Test status
Simulation time 179623987 ps
CPU time 10.7 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:51:53 PM PDT 24
Peak memory 220040 kb
Host smart-79d995f2-2ae1-489b-9469-38369a27d90b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713510994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2713510994
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3026677195
Short name T14
Test name
Test status
Simulation time 26861739938 ps
CPU time 1854.64 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 07:22:37 PM PDT 24
Peak memory 230616 kb
Host smart-69668d67-9686-4f9f-a3cb-ada3da51f4a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026677195 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3026677195
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2950729035
Short name T226
Test name
Test status
Simulation time 354802254 ps
CPU time 8.42 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 219028 kb
Host smart-74700b66-0019-460b-ac81-28e61c0731e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950729035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2950729035
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3021654966
Short name T231
Test name
Test status
Simulation time 4330225971 ps
CPU time 117.38 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:53:42 PM PDT 24
Peak memory 239736 kb
Host smart-64ca1a61-fff5-44dd-acea-1252258d9a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021654966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3021654966
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2442929789
Short name T264
Test name
Test status
Simulation time 4117502709 ps
CPU time 32.36 seconds
Started Aug 11 06:51:36 PM PDT 24
Finished Aug 11 06:52:08 PM PDT 24
Peak memory 220216 kb
Host smart-b9accb6d-c190-4713-ac5e-ce558f75b015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442929789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2442929789
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3527320408
Short name T316
Test name
Test status
Simulation time 182623024 ps
CPU time 9.99 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:51:48 PM PDT 24
Peak memory 220028 kb
Host smart-2c159157-b4c4-4328-b80a-f2935b4ac10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527320408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3527320408
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2115230458
Short name T79
Test name
Test status
Simulation time 1431905921 ps
CPU time 27.73 seconds
Started Aug 11 06:51:40 PM PDT 24
Finished Aug 11 06:52:08 PM PDT 24
Peak memory 220060 kb
Host smart-a44e28e8-7aed-43d1-ad71-e9c8d39e2ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115230458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2115230458
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2782875667
Short name T321
Test name
Test status
Simulation time 55132577396 ps
CPU time 1113.49 seconds
Started Aug 11 06:51:37 PM PDT 24
Finished Aug 11 07:10:11 PM PDT 24
Peak memory 236668 kb
Host smart-09722b4b-f8ac-4c59-9c35-ba0e6cf5c422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782875667 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2782875667
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3602835040
Short name T61
Test name
Test status
Simulation time 1275469336 ps
CPU time 8.56 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 219128 kb
Host smart-57d529ea-ae53-46f5-983a-170599af6595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602835040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3602835040
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1122533710
Short name T160
Test name
Test status
Simulation time 9346140966 ps
CPU time 156.57 seconds
Started Aug 11 06:51:38 PM PDT 24
Finished Aug 11 06:54:15 PM PDT 24
Peak memory 238448 kb
Host smart-8cb8cebd-a615-413a-9bb7-7c5c2f9becaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122533710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1122533710
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2919218035
Short name T186
Test name
Test status
Simulation time 1657393153 ps
CPU time 19.48 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220092 kb
Host smart-49677977-daa2-46bb-9698-094f018a71fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919218035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2919218035
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2699746169
Short name T309
Test name
Test status
Simulation time 272342553 ps
CPU time 12 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:51:54 PM PDT 24
Peak memory 220072 kb
Host smart-4903cd9c-d5d3-4d84-ae56-b3322a7c02d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699746169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2699746169
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.883490662
Short name T271
Test name
Test status
Simulation time 1557262139 ps
CPU time 37.68 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:52:23 PM PDT 24
Peak memory 220052 kb
Host smart-5f96aa54-b54d-48e8-9c75-3ba8e53ef01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883490662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.883490662
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1906378964
Short name T243
Test name
Test status
Simulation time 1029860623 ps
CPU time 10.25 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:51:54 PM PDT 24
Peak memory 219196 kb
Host smart-5c70313b-82f1-4cc9-883a-18b6a448b4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906378964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1906378964
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2247876474
Short name T314
Test name
Test status
Simulation time 13676423256 ps
CPU time 191.61 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:54:54 PM PDT 24
Peak memory 235836 kb
Host smart-153d2c15-1d7b-4b55-9fe3-3fb3df703d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247876474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2247876474
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4017822254
Short name T147
Test name
Test status
Simulation time 2066961253 ps
CPU time 22.75 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:52:07 PM PDT 24
Peak memory 220072 kb
Host smart-4b470761-e36e-446d-8902-b1e6331f7452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017822254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4017822254
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2263336036
Short name T315
Test name
Test status
Simulation time 4562076510 ps
CPU time 16.83 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:51:59 PM PDT 24
Peak memory 220192 kb
Host smart-ec7e9347-8eca-427a-a0d8-ba5e8adeb4a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263336036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2263336036
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.898689803
Short name T279
Test name
Test status
Simulation time 172842440 ps
CPU time 9.84 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 220068 kb
Host smart-11ff65eb-ad92-4172-921e-f824215fd57b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898689803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.898689803
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1065211175
Short name T296
Test name
Test status
Simulation time 95683777054 ps
CPU time 951.11 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 07:07:33 PM PDT 24
Peak memory 236596 kb
Host smart-7a35b224-1a82-4c1a-8c41-7ace63d81ded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065211175 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1065211175
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1690640311
Short name T35
Test name
Test status
Simulation time 1376336291 ps
CPU time 10.21 seconds
Started Aug 11 06:51:39 PM PDT 24
Finished Aug 11 06:51:49 PM PDT 24
Peak memory 219088 kb
Host smart-3996dd85-ee04-4c1a-9789-841e2f27eb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690640311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1690640311
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3340860393
Short name T175
Test name
Test status
Simulation time 8341288558 ps
CPU time 319.17 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:57:05 PM PDT 24
Peak memory 239380 kb
Host smart-0e3e6389-5827-4560-9a92-7cefe25b7278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340860393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3340860393
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2533533517
Short name T285
Test name
Test status
Simulation time 993943643 ps
CPU time 22.78 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:52:09 PM PDT 24
Peak memory 219984 kb
Host smart-a9e7585c-4540-4577-b403-3db532ec4004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533533517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2533533517
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4027369435
Short name T111
Test name
Test status
Simulation time 365878422 ps
CPU time 10.39 seconds
Started Aug 11 06:51:40 PM PDT 24
Finished Aug 11 06:51:50 PM PDT 24
Peak memory 219912 kb
Host smart-507f4729-c67d-4ece-bd82-27f73f3d0ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027369435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4027369435
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.129910947
Short name T267
Test name
Test status
Simulation time 731679384 ps
CPU time 28.22 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:52:13 PM PDT 24
Peak memory 220096 kb
Host smart-2dd895c3-bfab-4f05-a2c9-9acb25988de9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129910947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.129910947
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3366974655
Short name T62
Test name
Test status
Simulation time 174659004 ps
CPU time 8.62 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:51:59 PM PDT 24
Peak memory 219148 kb
Host smart-bd529593-772a-4b18-9b32-4dd1afc70ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366974655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3366974655
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3857353952
Short name T297
Test name
Test status
Simulation time 21457778116 ps
CPU time 271.49 seconds
Started Aug 11 06:51:41 PM PDT 24
Finished Aug 11 06:56:12 PM PDT 24
Peak memory 226876 kb
Host smart-d7e49d58-62b8-439a-929d-6aedab31a181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857353952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3857353952
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.166841432
Short name T32
Test name
Test status
Simulation time 2068009904 ps
CPU time 22.28 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:52:07 PM PDT 24
Peak memory 220136 kb
Host smart-2fc0a74e-0289-4805-9098-8ca509cd3ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166841432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.166841432
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.407302068
Short name T166
Test name
Test status
Simulation time 177055912 ps
CPU time 10.08 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 220128 kb
Host smart-7b0fa744-0f39-46a4-929b-7ad4684669ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407302068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.407302068
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3603910799
Short name T310
Test name
Test status
Simulation time 573009097 ps
CPU time 19.04 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 219948 kb
Host smart-e81f0ad5-ab92-4c3a-907d-1affe501d80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603910799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3603910799
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3559487082
Short name T259
Test name
Test status
Simulation time 178234525 ps
CPU time 8.39 seconds
Started Aug 11 06:51:24 PM PDT 24
Finished Aug 11 06:51:33 PM PDT 24
Peak memory 219036 kb
Host smart-9cf95c03-5e3f-4e6d-ad20-c74810a0e4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559487082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3559487082
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4062725326
Short name T41
Test name
Test status
Simulation time 17490535137 ps
CPU time 449.01 seconds
Started Aug 11 06:51:20 PM PDT 24
Finished Aug 11 06:58:49 PM PDT 24
Peak memory 238908 kb
Host smart-1fc3bdbe-7197-4ffb-a959-cdda3fc522ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062725326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4062725326
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1441637507
Short name T159
Test name
Test status
Simulation time 518508903 ps
CPU time 22.49 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:45 PM PDT 24
Peak memory 220028 kb
Host smart-9fc78415-3874-4a49-9f58-713241ae7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441637507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1441637507
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1803315520
Short name T180
Test name
Test status
Simulation time 436034553 ps
CPU time 10.24 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 220076 kb
Host smart-a13e5ae4-e38b-492c-b160-b9f0e30f0b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803315520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1803315520
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2465477768
Short name T24
Test name
Test status
Simulation time 320733166 ps
CPU time 119.35 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:53:23 PM PDT 24
Peak memory 239152 kb
Host smart-ffe3f9d1-ac71-4076-adf9-d8c2abe6e782
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465477768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2465477768
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2962493271
Short name T300
Test name
Test status
Simulation time 358430099 ps
CPU time 10.44 seconds
Started Aug 11 06:51:24 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 220088 kb
Host smart-06347151-28cd-4534-9a84-d0ec9c81f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962493271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2962493271
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1578049789
Short name T75
Test name
Test status
Simulation time 9170427508 ps
CPU time 38.75 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:52:02 PM PDT 24
Peak memory 220168 kb
Host smart-78b8125c-756d-4014-9156-1797a517e427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578049789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1578049789
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1128067275
Short name T277
Test name
Test status
Simulation time 62166744328 ps
CPU time 1265.01 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 07:12:29 PM PDT 24
Peak memory 236656 kb
Host smart-b3bc347c-8a42-479e-bf70-a34d21fc182f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128067275 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1128067275
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2359525533
Short name T249
Test name
Test status
Simulation time 250812824 ps
CPU time 10.42 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 219068 kb
Host smart-245facf0-92ba-4fe8-8f7f-47de10922c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359525533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2359525533
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1653955603
Short name T290
Test name
Test status
Simulation time 13331947448 ps
CPU time 222.44 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:55:25 PM PDT 24
Peak memory 242840 kb
Host smart-3d406395-b0ce-4ae5-945a-32667b987767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653955603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1653955603
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.679816746
Short name T252
Test name
Test status
Simulation time 2203741923 ps
CPU time 19.66 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:52:06 PM PDT 24
Peak memory 220184 kb
Host smart-48ec1c4b-c5fc-430a-8260-7976e2d39ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679816746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.679816746
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1353003583
Short name T266
Test name
Test status
Simulation time 185748147 ps
CPU time 10.78 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:51:54 PM PDT 24
Peak memory 220112 kb
Host smart-4fe46f01-449d-4abf-a0ce-daac44600a89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353003583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1353003583
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.125149246
Short name T311
Test name
Test status
Simulation time 2519990869 ps
CPU time 34.72 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:52:21 PM PDT 24
Peak memory 220292 kb
Host smart-f1bdaced-f6b5-4305-a84d-7da108214f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125149246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.125149246
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.26071866
Short name T212
Test name
Test status
Simulation time 259308073 ps
CPU time 10.17 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:51:53 PM PDT 24
Peak memory 219080 kb
Host smart-21f156ec-60fa-4c22-aebc-aa9593ff28f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.26071866
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3293144253
Short name T125
Test name
Test status
Simulation time 2308998723 ps
CPU time 155.31 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:54:20 PM PDT 24
Peak memory 228932 kb
Host smart-7c0e5a9c-4977-4a33-ae43-809f0b552619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293144253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3293144253
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3606363236
Short name T171
Test name
Test status
Simulation time 518887715 ps
CPU time 22.88 seconds
Started Aug 11 06:51:42 PM PDT 24
Finished Aug 11 06:52:06 PM PDT 24
Peak memory 220096 kb
Host smart-dd95e25d-2382-46ef-aed3-5f3ea2a95da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606363236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3606363236
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1596513005
Short name T98
Test name
Test status
Simulation time 269705298 ps
CPU time 12.09 seconds
Started Aug 11 06:51:40 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 220032 kb
Host smart-ffe178f9-e8bd-4b29-8c2f-0df77573b476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596513005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1596513005
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2543700025
Short name T301
Test name
Test status
Simulation time 1048210576 ps
CPU time 23.67 seconds
Started Aug 11 06:51:40 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220004 kb
Host smart-cab548d2-0cdb-4af5-958b-d996f5679d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543700025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2543700025
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1116509993
Short name T59
Test name
Test status
Simulation time 498669968 ps
CPU time 9.92 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 219076 kb
Host smart-a59011c5-0bdc-46d4-836e-f5be8935201f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116509993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1116509993
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1633992829
Short name T135
Test name
Test status
Simulation time 3308967620 ps
CPU time 18.96 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:52:03 PM PDT 24
Peak memory 220240 kb
Host smart-b2a09fff-3be2-4252-91b1-00228c030858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633992829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1633992829
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2280124113
Short name T229
Test name
Test status
Simulation time 696513444 ps
CPU time 10.36 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 220096 kb
Host smart-afeb7d6d-e5b9-4a72-925e-7afc57c703ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280124113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2280124113
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3979536177
Short name T17
Test name
Test status
Simulation time 788330566 ps
CPU time 28.67 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:52:12 PM PDT 24
Peak memory 220048 kb
Host smart-4e5b4445-8272-47f2-abae-4a496d506cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979536177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3979536177
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3616251050
Short name T276
Test name
Test status
Simulation time 507186530 ps
CPU time 9.74 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:02 PM PDT 24
Peak memory 219032 kb
Host smart-1f6db8e4-e052-4b0c-af97-f43480d5b0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616251050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3616251050
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3259361031
Short name T188
Test name
Test status
Simulation time 18930788979 ps
CPU time 338.37 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:57:31 PM PDT 24
Peak memory 239812 kb
Host smart-5656598e-2ca8-4cef-8b5b-dc4c53710a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259361031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3259361031
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4047295334
Short name T225
Test name
Test status
Simulation time 4508162401 ps
CPU time 22.94 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:15 PM PDT 24
Peak memory 220164 kb
Host smart-270f5a77-e14a-4ff1-b29a-d9fa196d2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047295334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4047295334
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2056384790
Short name T129
Test name
Test status
Simulation time 498537999 ps
CPU time 12.26 seconds
Started Aug 11 06:51:43 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 220080 kb
Host smart-7a31cd77-3474-4753-b5e6-b48f76695132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056384790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2056384790
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1791849592
Short name T216
Test name
Test status
Simulation time 559357321 ps
CPU time 19.52 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220052 kb
Host smart-f8b601b5-432e-4de0-a334-9180c2ce0458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791849592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1791849592
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.534540965
Short name T306
Test name
Test status
Simulation time 35981850607 ps
CPU time 3244.37 seconds
Started Aug 11 06:51:48 PM PDT 24
Finished Aug 11 07:45:53 PM PDT 24
Peak memory 232368 kb
Host smart-50a5394a-7d3d-4203-ba38-b4361ff2fe0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534540965 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.534540965
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.792430438
Short name T5
Test name
Test status
Simulation time 687674378 ps
CPU time 8.13 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 219108 kb
Host smart-3be319b4-e178-4963-9ecd-b3303d9b24ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792430438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.792430438
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1484320312
Short name T177
Test name
Test status
Simulation time 35181875129 ps
CPU time 193.08 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:55:00 PM PDT 24
Peak memory 239940 kb
Host smart-5a9ca92d-c90b-4895-90db-012d4b706c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484320312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1484320312
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1819694564
Short name T220
Test name
Test status
Simulation time 443437882 ps
CPU time 19.01 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 06:52:14 PM PDT 24
Peak memory 220044 kb
Host smart-dda47a69-1af9-4e60-8293-14f3dbe5e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819694564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1819694564
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.257405280
Short name T161
Test name
Test status
Simulation time 1081055409 ps
CPU time 12.21 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:57 PM PDT 24
Peak memory 220104 kb
Host smart-fe7b5cc2-1a07-4b93-958a-16d4b3bee134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257405280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.257405280
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3787948780
Short name T205
Test name
Test status
Simulation time 1613827025 ps
CPU time 30.99 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:52:18 PM PDT 24
Peak memory 220020 kb
Host smart-90658d73-ccf9-48e8-8923-b9e81decf0b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787948780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3787948780
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1176833808
Short name T242
Test name
Test status
Simulation time 256922744 ps
CPU time 10.09 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:00 PM PDT 24
Peak memory 219200 kb
Host smart-70529484-c886-4a68-9475-b611395cec88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176833808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1176833808
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2802812133
Short name T263
Test name
Test status
Simulation time 9670352959 ps
CPU time 145.17 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:54:11 PM PDT 24
Peak memory 220076 kb
Host smart-f97ea952-1a9b-4c2c-8173-3d88bb23a684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802812133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2802812133
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3995271211
Short name T176
Test name
Test status
Simulation time 1829678016 ps
CPU time 23.17 seconds
Started Aug 11 06:51:44 PM PDT 24
Finished Aug 11 06:52:07 PM PDT 24
Peak memory 220000 kb
Host smart-2104a72b-07e9-4258-8965-d27898936cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995271211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3995271211
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3579411787
Short name T320
Test name
Test status
Simulation time 185256453 ps
CPU time 10.61 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:01 PM PDT 24
Peak memory 220076 kb
Host smart-039f50b4-64cb-416f-ab25-86be0b2b71c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579411787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3579411787
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.209010331
Short name T77
Test name
Test status
Simulation time 1470625885 ps
CPU time 20.39 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 06:52:15 PM PDT 24
Peak memory 220024 kb
Host smart-8264c531-e4ef-4660-b822-0fae6365ace4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209010331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.209010331
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3610900648
Short name T286
Test name
Test status
Simulation time 414466506 ps
CPU time 8.25 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:51:55 PM PDT 24
Peak memory 219096 kb
Host smart-3c8e16e8-75fc-4b70-af89-b8b2d29bf090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610900648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3610900648
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.465140697
Short name T33
Test name
Test status
Simulation time 3537104352 ps
CPU time 250.77 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:56:01 PM PDT 24
Peak memory 238164 kb
Host smart-8fee1d27-11d5-4b34-a099-f67114280623
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465140697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.465140697
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1753841473
Short name T275
Test name
Test status
Simulation time 1981969430 ps
CPU time 22.48 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:16 PM PDT 24
Peak memory 220072 kb
Host smart-12f9bf82-a23c-47e8-bb66-43eff8dc4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753841473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1753841473
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.126880623
Short name T247
Test name
Test status
Simulation time 356003565 ps
CPU time 10.47 seconds
Started Aug 11 06:51:48 PM PDT 24
Finished Aug 11 06:51:58 PM PDT 24
Peak memory 220080 kb
Host smart-68073628-83ca-4501-ba01-e397b85dedfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126880623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.126880623
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3681241213
Short name T262
Test name
Test status
Simulation time 1096968443 ps
CPU time 12.59 seconds
Started Aug 11 06:51:46 PM PDT 24
Finished Aug 11 06:51:59 PM PDT 24
Peak memory 220036 kb
Host smart-f34f163b-e90b-4485-a7c3-1f8ff269f0b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681241213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3681241213
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3762642070
Short name T141
Test name
Test status
Simulation time 1175251449 ps
CPU time 10.06 seconds
Started Aug 11 06:51:54 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 219148 kb
Host smart-ec546c6e-c633-4f71-869f-80b2e63c6881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762642070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3762642070
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.156792165
Short name T45
Test name
Test status
Simulation time 8457327323 ps
CPU time 251.02 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:55:58 PM PDT 24
Peak memory 225756 kb
Host smart-3884b599-aa80-40af-95a6-fff1833b4b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156792165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.156792165
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2994558129
Short name T137
Test name
Test status
Simulation time 336640513 ps
CPU time 19.05 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:52:06 PM PDT 24
Peak memory 220096 kb
Host smart-2ecb67c4-d55c-4944-bd38-f0c6d3b2d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994558129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2994558129
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3170020331
Short name T305
Test name
Test status
Simulation time 186575109 ps
CPU time 10.3 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 220036 kb
Host smart-26b3df59-5238-48e3-97a2-03a1e8b3f857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170020331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3170020331
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4053927561
Short name T15
Test name
Test status
Simulation time 1674670559 ps
CPU time 20.36 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:52:12 PM PDT 24
Peak memory 220024 kb
Host smart-79a709bb-4400-4601-b134-6506a470e878
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053927561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4053927561
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.214752821
Short name T49
Test name
Test status
Simulation time 135553759900 ps
CPU time 2859.55 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 07:39:27 PM PDT 24
Peak memory 253056 kb
Host smart-102bc4d1-8d42-4c19-aaaf-cc0f97fb1d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214752821 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.214752821
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3756708297
Short name T317
Test name
Test status
Simulation time 319114820 ps
CPU time 8.55 seconds
Started Aug 11 06:51:48 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 219056 kb
Host smart-7df16687-6394-40c2-a3e7-54001c4bc92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756708297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3756708297
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3800052159
Short name T150
Test name
Test status
Simulation time 694821262 ps
CPU time 10.37 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 220068 kb
Host smart-8e292006-8a61-4557-90f2-9accd146a185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800052159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3800052159
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3177425179
Short name T44
Test name
Test status
Simulation time 560003618 ps
CPU time 27.57 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:20 PM PDT 24
Peak memory 220028 kb
Host smart-faac271f-d481-443f-9695-ec1e0d57cfee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177425179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3177425179
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1893655542
Short name T13
Test name
Test status
Simulation time 381602933493 ps
CPU time 3692.71 seconds
Started Aug 11 06:51:48 PM PDT 24
Finished Aug 11 07:53:21 PM PDT 24
Peak memory 249148 kb
Host smart-1630e9bb-6a4d-49d1-96c7-86d8c1d24c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893655542 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1893655542
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3219299927
Short name T9
Test name
Test status
Simulation time 172671263 ps
CPU time 8.35 seconds
Started Aug 11 06:51:48 PM PDT 24
Finished Aug 11 06:51:56 PM PDT 24
Peak memory 219140 kb
Host smart-90a60b00-30c1-4aff-9085-9c4e0eb22239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219299927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3219299927
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4016352425
Short name T21
Test name
Test status
Simulation time 9860427365 ps
CPU time 140.07 seconds
Started Aug 11 06:51:54 PM PDT 24
Finished Aug 11 06:54:14 PM PDT 24
Peak memory 220336 kb
Host smart-c962125d-92d4-465d-a3d5-e105cf955e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016352425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4016352425
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3138564911
Short name T190
Test name
Test status
Simulation time 1417963565 ps
CPU time 22.4 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:12 PM PDT 24
Peak memory 220064 kb
Host smart-5c35abc9-7bde-4868-ae17-338b208e9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138564911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3138564911
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.685961275
Short name T302
Test name
Test status
Simulation time 702381758 ps
CPU time 11.42 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220064 kb
Host smart-e6c1c083-5b59-4a64-851c-e52b5aa74d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685961275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.685961275
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1885474108
Short name T201
Test name
Test status
Simulation time 2089840868 ps
CPU time 26.92 seconds
Started Aug 11 06:51:45 PM PDT 24
Finished Aug 11 06:52:12 PM PDT 24
Peak memory 220064 kb
Host smart-050cb527-b86d-45cd-b3d1-1b1575f3545a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885474108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1885474108
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1823113782
Short name T139
Test name
Test status
Simulation time 170797784 ps
CPU time 8.53 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:32 PM PDT 24
Peak memory 219120 kb
Host smart-2d9d6ab7-99dc-47c0-b90f-28ff468a68dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823113782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1823113782
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2898110303
Short name T256
Test name
Test status
Simulation time 11724304099 ps
CPU time 169.17 seconds
Started Aug 11 06:51:21 PM PDT 24
Finished Aug 11 06:54:10 PM PDT 24
Peak memory 237772 kb
Host smart-9d5c54ab-73e5-4fbe-8c9a-cf828192978e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898110303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2898110303
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4090675080
Short name T298
Test name
Test status
Simulation time 337273476 ps
CPU time 19.51 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:51:44 PM PDT 24
Peak memory 220100 kb
Host smart-fe93b7ea-1c3b-4a4f-a3d1-05f389cb8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090675080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4090675080
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4047214573
Short name T208
Test name
Test status
Simulation time 1050406989 ps
CPU time 11.97 seconds
Started Aug 11 06:51:24 PM PDT 24
Finished Aug 11 06:51:36 PM PDT 24
Peak memory 220088 kb
Host smart-85100a82-7f00-4209-9b73-b2eaa775e38d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047214573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4047214573
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1230814219
Short name T178
Test name
Test status
Simulation time 261265462 ps
CPU time 11.99 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 220008 kb
Host smart-cfcc88a6-67e0-49ef-ae62-402d3b4a3644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230814219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1230814219
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.623156068
Short name T80
Test name
Test status
Simulation time 3224016235 ps
CPU time 40.5 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220108 kb
Host smart-89031667-bf81-4b92-9e66-bd89c8a0f602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623156068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.623156068
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4177805070
Short name T131
Test name
Test status
Simulation time 991015363 ps
CPU time 10.09 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 219172 kb
Host smart-4f247461-d715-4583-9f45-2dd5bee18e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177805070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4177805070
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4003483949
Short name T19
Test name
Test status
Simulation time 2157099984 ps
CPU time 173.32 seconds
Started Aug 11 06:51:47 PM PDT 24
Finished Aug 11 06:54:40 PM PDT 24
Peak memory 229116 kb
Host smart-cf90e923-d26c-4ff1-90b1-376c13175055
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003483949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4003483949
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1905338006
Short name T284
Test name
Test status
Simulation time 515175871 ps
CPU time 22.99 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:13 PM PDT 24
Peak memory 220092 kb
Host smart-f14d9bb9-84af-4ed6-bcec-fd3f82c3ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905338006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1905338006
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4246300820
Short name T239
Test name
Test status
Simulation time 268291518 ps
CPU time 11.8 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:52:03 PM PDT 24
Peak memory 220020 kb
Host smart-738990c2-bd9d-4bd5-8680-05614cbd4184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246300820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4246300820
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1984738867
Short name T236
Test name
Test status
Simulation time 1049942870 ps
CPU time 27.68 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:20 PM PDT 24
Peak memory 220208 kb
Host smart-efd37cb1-398b-431b-a7e4-03e12fb1a004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984738867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1984738867
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1155726480
Short name T142
Test name
Test status
Simulation time 249806695 ps
CPU time 10.25 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:01 PM PDT 24
Peak memory 219200 kb
Host smart-fc198700-d64c-47fe-a707-8e812aa3c8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155726480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1155726480
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.454058426
Short name T167
Test name
Test status
Simulation time 6886386362 ps
CPU time 215.49 seconds
Started Aug 11 06:51:54 PM PDT 24
Finished Aug 11 06:55:30 PM PDT 24
Peak memory 228392 kb
Host smart-87c6d144-f7a4-49ee-aff9-17a44795b7d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454058426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.454058426
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2421871979
Short name T25
Test name
Test status
Simulation time 1033975233 ps
CPU time 22.8 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:14 PM PDT 24
Peak memory 220084 kb
Host smart-6b9410f3-317e-4c60-9197-61c2b4da74c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421871979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2421871979
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4016743771
Short name T250
Test name
Test status
Simulation time 3194266028 ps
CPU time 12.49 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 220444 kb
Host smart-701a37e3-e972-4698-9087-2911f8eb32ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016743771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4016743771
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3579760403
Short name T76
Test name
Test status
Simulation time 5274989156 ps
CPU time 28.72 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:52:19 PM PDT 24
Peak memory 220120 kb
Host smart-8b1b9cba-27d7-4575-8af0-4a3d6f52c098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579760403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3579760403
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.224273136
Short name T140
Test name
Test status
Simulation time 953594569 ps
CPU time 10.08 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:03 PM PDT 24
Peak memory 218796 kb
Host smart-1bfcf71a-aad2-47ea-afd9-9f689ccc574e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224273136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.224273136
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.960005534
Short name T34
Test name
Test status
Simulation time 2831764696 ps
CPU time 190.08 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:55:01 PM PDT 24
Peak memory 220388 kb
Host smart-a9a99005-12e5-4165-b6bc-1236f2e9e8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960005534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.960005534
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1285608665
Short name T37
Test name
Test status
Simulation time 529996375 ps
CPU time 22.12 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:52:13 PM PDT 24
Peak memory 220024 kb
Host smart-ea26f75b-af3e-4fd1-92d0-31645cfa2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285608665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1285608665
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3044871059
Short name T157
Test name
Test status
Simulation time 885078075 ps
CPU time 10.38 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:03 PM PDT 24
Peak memory 220104 kb
Host smart-cbf810cf-fc5b-4e77-b576-3534ecfd776e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044871059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3044871059
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3847841537
Short name T73
Test name
Test status
Simulation time 2666284001 ps
CPU time 23.76 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 06:52:19 PM PDT 24
Peak memory 220348 kb
Host smart-c33ca1bb-d803-48ba-a74b-530105a143e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847841537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3847841537
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.4133231450
Short name T51
Test name
Test status
Simulation time 185116464116 ps
CPU time 1926.34 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 07:23:58 PM PDT 24
Peak memory 239628 kb
Host smart-f629271d-3b6d-4b4e-9f7a-1be9779dab79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133231450 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.4133231450
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2166095197
Short name T227
Test name
Test status
Simulation time 528166183 ps
CPU time 10.2 seconds
Started Aug 11 06:51:55 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 219368 kb
Host smart-3594f8b8-4f71-4b34-8220-d2e64420fb1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166095197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2166095197
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1998883560
Short name T6
Test name
Test status
Simulation time 8213659810 ps
CPU time 137.24 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:54:10 PM PDT 24
Peak memory 231108 kb
Host smart-856105d8-e7ea-4f70-a141-d8d3f5d1fd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998883560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1998883560
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2400902913
Short name T148
Test name
Test status
Simulation time 551103233 ps
CPU time 22.97 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:16 PM PDT 24
Peak memory 219916 kb
Host smart-b24b086f-3f99-435d-8876-dbfa02624c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400902913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2400902913
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3644445493
Short name T255
Test name
Test status
Simulation time 499428574 ps
CPU time 12.72 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 220092 kb
Host smart-e849c0f0-a208-401f-9e3f-eb00a66bba61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644445493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3644445493
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1622747146
Short name T101
Test name
Test status
Simulation time 11969159074 ps
CPU time 53.07 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 220460 kb
Host smart-2a6f3efc-e161-4e9a-bf24-55dea4fcada8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622747146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1622747146
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4149518089
Short name T38
Test name
Test status
Simulation time 3529247135 ps
CPU time 9.95 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:02 PM PDT 24
Peak memory 219344 kb
Host smart-e1f0ce03-d07c-4450-a7b8-16ae04492189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149518089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4149518089
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2236501867
Short name T36
Test name
Test status
Simulation time 268356426874 ps
CPU time 370.07 seconds
Started Aug 11 06:51:50 PM PDT 24
Finished Aug 11 06:58:01 PM PDT 24
Peak memory 242788 kb
Host smart-e05d3ed4-a96f-4310-aef2-e0197816dd20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236501867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2236501867
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2345556902
Short name T145
Test name
Test status
Simulation time 2479864624 ps
CPU time 22.05 seconds
Started Aug 11 06:51:52 PM PDT 24
Finished Aug 11 06:52:14 PM PDT 24
Peak memory 220240 kb
Host smart-b885c4d3-b8cf-4dc0-a759-eac7588b967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345556902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2345556902
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2619505603
Short name T253
Test name
Test status
Simulation time 1509351512 ps
CPU time 34.71 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 220064 kb
Host smart-0eb58bc0-b7c5-4400-8c71-e26fde57d793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619505603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2619505603
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1979097810
Short name T96
Test name
Test status
Simulation time 169552694 ps
CPU time 8.28 seconds
Started Aug 11 06:51:58 PM PDT 24
Finished Aug 11 06:52:06 PM PDT 24
Peak memory 219188 kb
Host smart-0235726b-ec1b-4ff3-9d94-97a20f2bd0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979097810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1979097810
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3144955411
Short name T213
Test name
Test status
Simulation time 4346015298 ps
CPU time 216.05 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:55:29 PM PDT 24
Peak memory 239676 kb
Host smart-58b2c48d-3bdb-4f57-83c6-0a0c40dbe929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144955411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3144955411
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1670151345
Short name T283
Test name
Test status
Simulation time 1984737646 ps
CPU time 32.52 seconds
Started Aug 11 06:51:51 PM PDT 24
Finished Aug 11 06:52:24 PM PDT 24
Peak memory 220052 kb
Host smart-04d7ba38-44fe-442f-96be-8c4dd269609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670151345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1670151345
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2050214209
Short name T189
Test name
Test status
Simulation time 179114156 ps
CPU time 10.57 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:04 PM PDT 24
Peak memory 220052 kb
Host smart-5912df5d-5bec-498a-bcb5-4bc6dfa5a8ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050214209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2050214209
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3451124863
Short name T273
Test name
Test status
Simulation time 8719638934 ps
CPU time 43.41 seconds
Started Aug 11 06:51:53 PM PDT 24
Finished Aug 11 06:52:37 PM PDT 24
Peak memory 220080 kb
Host smart-c8975d16-0ae3-4e04-9cc4-f81df985bf58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451124863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3451124863
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.190463459
Short name T64
Test name
Test status
Simulation time 2740619353 ps
CPU time 10.3 seconds
Started Aug 11 06:51:58 PM PDT 24
Finished Aug 11 06:52:09 PM PDT 24
Peak memory 219248 kb
Host smart-caec73cd-d219-4ace-aaef-2ec7a09d8e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190463459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.190463459
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2401609663
Short name T39
Test name
Test status
Simulation time 2936505950 ps
CPU time 179.06 seconds
Started Aug 11 06:51:56 PM PDT 24
Finished Aug 11 06:54:55 PM PDT 24
Peak memory 235292 kb
Host smart-d3ecc9dd-de09-4d03-b669-70e95350a4b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401609663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2401609663
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1935409116
Short name T132
Test name
Test status
Simulation time 505503125 ps
CPU time 21.75 seconds
Started Aug 11 06:51:57 PM PDT 24
Finished Aug 11 06:52:19 PM PDT 24
Peak memory 220052 kb
Host smart-57ea1e7b-0c7b-45e5-8c13-53febfdf79fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935409116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1935409116
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1125022583
Short name T20
Test name
Test status
Simulation time 358002792 ps
CPU time 10.56 seconds
Started Aug 11 06:51:56 PM PDT 24
Finished Aug 11 06:52:07 PM PDT 24
Peak memory 220100 kb
Host smart-55c1578a-038c-4f80-a587-8697e00bd5c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125022583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1125022583
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2698053531
Short name T293
Test name
Test status
Simulation time 409816035 ps
CPU time 15.37 seconds
Started Aug 11 06:51:56 PM PDT 24
Finished Aug 11 06:52:12 PM PDT 24
Peak memory 220000 kb
Host smart-0a86461f-252c-477c-adad-d2121d0647f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698053531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2698053531
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.748207367
Short name T211
Test name
Test status
Simulation time 4936847207 ps
CPU time 10.03 seconds
Started Aug 11 06:51:59 PM PDT 24
Finished Aug 11 06:52:09 PM PDT 24
Peak memory 219324 kb
Host smart-5fd1060e-2ad3-4eba-818e-784f486d8a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748207367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.748207367
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.830947597
Short name T191
Test name
Test status
Simulation time 11396431307 ps
CPU time 199.73 seconds
Started Aug 11 06:51:59 PM PDT 24
Finished Aug 11 06:55:19 PM PDT 24
Peak memory 225744 kb
Host smart-ddd3e9df-c599-4ed1-aaa4-1ca81a47d24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830947597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.830947597
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1435085
Short name T170
Test name
Test status
Simulation time 494940646 ps
CPU time 22.61 seconds
Started Aug 11 06:51:59 PM PDT 24
Finished Aug 11 06:52:22 PM PDT 24
Peak memory 220036 kb
Host smart-65965197-78dc-4386-a5cb-214089cb20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1435085
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1422648624
Short name T110
Test name
Test status
Simulation time 1074886051 ps
CPU time 12.21 seconds
Started Aug 11 06:51:56 PM PDT 24
Finished Aug 11 06:52:08 PM PDT 24
Peak memory 220084 kb
Host smart-e4b1ccdf-e969-4b02-93ef-2af098d4f590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422648624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1422648624
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1895766714
Short name T268
Test name
Test status
Simulation time 1031598593 ps
CPU time 25.01 seconds
Started Aug 11 06:51:57 PM PDT 24
Finished Aug 11 06:52:22 PM PDT 24
Peak memory 220084 kb
Host smart-1ef60ba6-a926-4e00-b517-41c1e5045451
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895766714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1895766714
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3339806377
Short name T195
Test name
Test status
Simulation time 172514515 ps
CPU time 8.5 seconds
Started Aug 11 06:52:11 PM PDT 24
Finished Aug 11 06:52:19 PM PDT 24
Peak memory 219112 kb
Host smart-7de23880-58dc-40cc-bfaa-3dfe9d7f26dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339806377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3339806377
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2447960524
Short name T130
Test name
Test status
Simulation time 3843881727 ps
CPU time 178.94 seconds
Started Aug 11 06:52:00 PM PDT 24
Finished Aug 11 06:54:59 PM PDT 24
Peak memory 229300 kb
Host smart-b2b57d5e-ddee-418f-9088-bf12a2a93473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447960524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2447960524
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3219881378
Short name T155
Test name
Test status
Simulation time 1973222110 ps
CPU time 23.05 seconds
Started Aug 11 06:51:57 PM PDT 24
Finished Aug 11 06:52:21 PM PDT 24
Peak memory 220036 kb
Host smart-61694657-93bd-44ac-a2bb-2456b7683e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219881378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3219881378
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3008588197
Short name T265
Test name
Test status
Simulation time 518283517 ps
CPU time 12.1 seconds
Started Aug 11 06:51:57 PM PDT 24
Finished Aug 11 06:52:09 PM PDT 24
Peak memory 220108 kb
Host smart-916f7f92-82e2-4de3-8a7f-b0978f43911a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008588197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3008588197
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1892106318
Short name T228
Test name
Test status
Simulation time 6109757987 ps
CPU time 36.15 seconds
Started Aug 11 06:51:57 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 220940 kb
Host smart-453dbd41-d19d-4448-a12d-8d50d7f40eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892106318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1892106318
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1423741074
Short name T304
Test name
Test status
Simulation time 332379044 ps
CPU time 8.54 seconds
Started Aug 11 06:52:02 PM PDT 24
Finished Aug 11 06:52:10 PM PDT 24
Peak memory 219148 kb
Host smart-08989e01-cc73-40d6-815b-35c25b918ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423741074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1423741074
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3832747065
Short name T280
Test name
Test status
Simulation time 1057185133 ps
CPU time 22.4 seconds
Started Aug 11 06:52:02 PM PDT 24
Finished Aug 11 06:52:24 PM PDT 24
Peak memory 220072 kb
Host smart-11f0c407-16d3-4268-9a24-d19e2e7b9931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832747065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3832747065
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2788543987
Short name T183
Test name
Test status
Simulation time 2497342634 ps
CPU time 10.41 seconds
Started Aug 11 06:52:04 PM PDT 24
Finished Aug 11 06:52:14 PM PDT 24
Peak memory 220064 kb
Host smart-ecd6f81c-1001-4f59-b9b7-dd97c198f018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788543987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2788543987
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.436976257
Short name T134
Test name
Test status
Simulation time 198883924 ps
CPU time 14 seconds
Started Aug 11 06:52:04 PM PDT 24
Finished Aug 11 06:52:18 PM PDT 24
Peak memory 219760 kb
Host smart-d956476d-6f43-432f-8cad-a21772793bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436976257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.436976257
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.947929836
Short name T237
Test name
Test status
Simulation time 1029570671 ps
CPU time 10.11 seconds
Started Aug 11 06:51:22 PM PDT 24
Finished Aug 11 06:51:32 PM PDT 24
Peak memory 219004 kb
Host smart-45f8000b-95e4-4220-af6e-cbc5379a70dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947929836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.947929836
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4102714788
Short name T313
Test name
Test status
Simulation time 5918723374 ps
CPU time 164.62 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:54:08 PM PDT 24
Peak memory 220392 kb
Host smart-7f93536a-5669-4391-bcef-c4815f7ccff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102714788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4102714788
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1291538223
Short name T200
Test name
Test status
Simulation time 885518970 ps
CPU time 22.72 seconds
Started Aug 11 06:51:24 PM PDT 24
Finished Aug 11 06:51:47 PM PDT 24
Peak memory 220060 kb
Host smart-117a30e8-7070-4c92-a1e5-35ebdb9fe476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291538223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1291538223
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1883826485
Short name T4
Test name
Test status
Simulation time 4133407221 ps
CPU time 17.39 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:40 PM PDT 24
Peak memory 219900 kb
Host smart-6c1dfd57-ca7d-4fce-b089-5a7e5856c0fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883826485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1883826485
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2574413261
Short name T27
Test name
Test status
Simulation time 4455792629 ps
CPU time 122.15 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:53:26 PM PDT 24
Peak memory 239564 kb
Host smart-fb9e2b81-9859-4a6d-a818-94d4f55e49e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574413261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2574413261
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1126159107
Short name T199
Test name
Test status
Simulation time 268136173 ps
CPU time 12.86 seconds
Started Aug 11 06:51:26 PM PDT 24
Finished Aug 11 06:51:39 PM PDT 24
Peak memory 220052 kb
Host smart-894d6407-0e6f-49df-b06f-0eff338249d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126159107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1126159107
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3658669521
Short name T11
Test name
Test status
Simulation time 1101395546 ps
CPU time 35.93 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:52:01 PM PDT 24
Peak memory 220068 kb
Host smart-c1675807-8264-4b71-a336-1ba01a1923bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658669521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3658669521
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1053507308
Short name T215
Test name
Test status
Simulation time 1767554224 ps
CPU time 10.31 seconds
Started Aug 11 06:52:09 PM PDT 24
Finished Aug 11 06:52:20 PM PDT 24
Peak memory 219892 kb
Host smart-95efeda2-7882-49b2-8ddb-4def6a302d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053507308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1053507308
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3425582556
Short name T153
Test name
Test status
Simulation time 3342875734 ps
CPU time 192.08 seconds
Started Aug 11 06:52:03 PM PDT 24
Finished Aug 11 06:55:15 PM PDT 24
Peak memory 238092 kb
Host smart-3d445dec-caec-4c80-9c21-3e015bd53365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425582556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3425582556
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3346195628
Short name T163
Test name
Test status
Simulation time 333790864 ps
CPU time 18.91 seconds
Started Aug 11 06:52:04 PM PDT 24
Finished Aug 11 06:52:23 PM PDT 24
Peak memory 220004 kb
Host smart-5743a31f-62ef-424e-bc6e-5bf0c3c6a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346195628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3346195628
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.160736131
Short name T235
Test name
Test status
Simulation time 956679327 ps
CPU time 12.13 seconds
Started Aug 11 06:52:03 PM PDT 24
Finished Aug 11 06:52:15 PM PDT 24
Peak memory 220116 kb
Host smart-0df9ac51-37a2-4004-a1bf-2d62c7a019e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160736131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.160736131
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2271012330
Short name T210
Test name
Test status
Simulation time 705208996 ps
CPU time 10.55 seconds
Started Aug 11 06:52:04 PM PDT 24
Finished Aug 11 06:52:14 PM PDT 24
Peak memory 220020 kb
Host smart-2cedeaa0-cf2e-494a-b99f-78874c18e807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271012330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2271012330
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.590471013
Short name T103
Test name
Test status
Simulation time 258765934 ps
CPU time 9.99 seconds
Started Aug 11 06:52:07 PM PDT 24
Finished Aug 11 06:52:18 PM PDT 24
Peak memory 218616 kb
Host smart-53b09aaa-7967-462a-a56b-badd778c34af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590471013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.590471013
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3848921656
Short name T194
Test name
Test status
Simulation time 57806704936 ps
CPU time 225.19 seconds
Started Aug 11 06:52:07 PM PDT 24
Finished Aug 11 06:55:53 PM PDT 24
Peak memory 242660 kb
Host smart-5aee3478-d5d8-4dcd-b64b-3ccaa1bd3ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848921656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3848921656
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3410727985
Short name T274
Test name
Test status
Simulation time 4027019343 ps
CPU time 33.04 seconds
Started Aug 11 06:52:09 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 219900 kb
Host smart-148d57a3-d8c5-426f-a454-f974daed869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410727985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3410727985
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3800261693
Short name T192
Test name
Test status
Simulation time 702208963 ps
CPU time 10.57 seconds
Started Aug 11 06:52:11 PM PDT 24
Finished Aug 11 06:52:22 PM PDT 24
Peak memory 220040 kb
Host smart-df5c3d2f-c213-4198-bcb3-ab82d1647f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800261693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3800261693
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2498333235
Short name T207
Test name
Test status
Simulation time 1154838456 ps
CPU time 19.82 seconds
Started Aug 11 06:52:09 PM PDT 24
Finished Aug 11 06:52:29 PM PDT 24
Peak memory 219976 kb
Host smart-fa5de74d-6991-4bbd-95ac-1d38a3a59c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498333235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2498333235
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2490303101
Short name T204
Test name
Test status
Simulation time 167540136 ps
CPU time 8.25 seconds
Started Aug 11 06:52:15 PM PDT 24
Finished Aug 11 06:52:23 PM PDT 24
Peak memory 219132 kb
Host smart-6a89404a-7648-4ea7-bd40-70629e50b129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490303101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2490303101
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1740208236
Short name T165
Test name
Test status
Simulation time 9057460944 ps
CPU time 250.21 seconds
Started Aug 11 06:52:07 PM PDT 24
Finished Aug 11 06:56:17 PM PDT 24
Peak memory 229476 kb
Host smart-e09301dd-e467-4e43-afe1-d4acf8303120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740208236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1740208236
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3812899821
Short name T42
Test name
Test status
Simulation time 4117819769 ps
CPU time 19.26 seconds
Started Aug 11 06:52:08 PM PDT 24
Finished Aug 11 06:52:27 PM PDT 24
Peak memory 220188 kb
Host smart-9948eedb-13b9-4f26-b6bf-10e4d793d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812899821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3812899821
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2149881861
Short name T185
Test name
Test status
Simulation time 922788192 ps
CPU time 10.37 seconds
Started Aug 11 06:52:09 PM PDT 24
Finished Aug 11 06:52:20 PM PDT 24
Peak memory 220092 kb
Host smart-ac7a7ec3-5d26-4d32-a7bf-325ccd28c687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149881861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2149881861
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2620269788
Short name T78
Test name
Test status
Simulation time 7678073997 ps
CPU time 32.07 seconds
Started Aug 11 06:52:10 PM PDT 24
Finished Aug 11 06:52:43 PM PDT 24
Peak memory 220136 kb
Host smart-c1e7dc22-ab3d-43ae-8b8e-2ab2d7ce9dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620269788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2620269788
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.911824042
Short name T299
Test name
Test status
Simulation time 867829984 ps
CPU time 8.18 seconds
Started Aug 11 06:52:13 PM PDT 24
Finished Aug 11 06:52:22 PM PDT 24
Peak memory 219032 kb
Host smart-d24d408c-8647-48ba-b006-f67af7a6cc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911824042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.911824042
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1314021404
Short name T168
Test name
Test status
Simulation time 20949546909 ps
CPU time 390.32 seconds
Started Aug 11 06:52:15 PM PDT 24
Finished Aug 11 06:58:46 PM PDT 24
Peak memory 239596 kb
Host smart-14ce21d5-bb60-48c6-9919-60d1e79afb3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314021404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1314021404
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1064938374
Short name T181
Test name
Test status
Simulation time 2069741292 ps
CPU time 22.38 seconds
Started Aug 11 06:52:16 PM PDT 24
Finished Aug 11 06:52:38 PM PDT 24
Peak memory 220100 kb
Host smart-6e9a7694-568f-4b15-bad0-c341b2ce065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064938374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1064938374
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3198179878
Short name T260
Test name
Test status
Simulation time 259334386 ps
CPU time 12.01 seconds
Started Aug 11 06:52:15 PM PDT 24
Finished Aug 11 06:52:27 PM PDT 24
Peak memory 220056 kb
Host smart-29b01b45-dbbe-4c21-9c7f-707597108302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198179878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3198179878
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.984795972
Short name T261
Test name
Test status
Simulation time 381379329 ps
CPU time 24.62 seconds
Started Aug 11 06:52:15 PM PDT 24
Finished Aug 11 06:52:39 PM PDT 24
Peak memory 220024 kb
Host smart-0cd521ef-463c-49ac-a82f-2c421975633f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984795972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.984795972
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1702932860
Short name T272
Test name
Test status
Simulation time 15314678829 ps
CPU time 6413.52 seconds
Started Aug 11 06:52:13 PM PDT 24
Finished Aug 11 08:39:07 PM PDT 24
Peak memory 228684 kb
Host smart-f827c574-34d5-4c61-980f-1a0c35c4a56f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702932860 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1702932860
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3073281102
Short name T303
Test name
Test status
Simulation time 989981294 ps
CPU time 15.23 seconds
Started Aug 11 06:52:14 PM PDT 24
Finished Aug 11 06:52:29 PM PDT 24
Peak memory 218532 kb
Host smart-64a5280a-1a74-4efe-bed9-e4dd05a3ff63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073281102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3073281102
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.242469979
Short name T248
Test name
Test status
Simulation time 25054409449 ps
CPU time 278.56 seconds
Started Aug 11 06:52:16 PM PDT 24
Finished Aug 11 06:56:55 PM PDT 24
Peak memory 238580 kb
Host smart-0223d479-d516-45fe-8ff0-7f0eb50e8065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242469979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.242469979
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3345892732
Short name T221
Test name
Test status
Simulation time 993025612 ps
CPU time 22.69 seconds
Started Aug 11 06:52:14 PM PDT 24
Finished Aug 11 06:52:37 PM PDT 24
Peak memory 220016 kb
Host smart-b19b2127-3ea8-4ab8-9ff6-c84dea24821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345892732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3345892732
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2417851375
Short name T291
Test name
Test status
Simulation time 262599211 ps
CPU time 12.24 seconds
Started Aug 11 06:52:13 PM PDT 24
Finished Aug 11 06:52:26 PM PDT 24
Peak memory 220080 kb
Host smart-87a9fc28-dadf-4a7f-9711-a2d71de0d835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417851375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2417851375
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1006773096
Short name T238
Test name
Test status
Simulation time 2159516685 ps
CPU time 33.07 seconds
Started Aug 11 06:52:16 PM PDT 24
Finished Aug 11 06:52:49 PM PDT 24
Peak memory 220180 kb
Host smart-5b67bbf4-57ee-4bdb-9992-f74f11a3f8f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006773096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1006773096
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3777955424
Short name T198
Test name
Test status
Simulation time 661416870 ps
CPU time 8.48 seconds
Started Aug 11 06:52:13 PM PDT 24
Finished Aug 11 06:52:22 PM PDT 24
Peak memory 219096 kb
Host smart-bc54152f-2293-4c6b-8023-74656a6814d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777955424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3777955424
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4193903095
Short name T1
Test name
Test status
Simulation time 7290904668 ps
CPU time 129.83 seconds
Started Aug 11 06:52:16 PM PDT 24
Finished Aug 11 06:54:26 PM PDT 24
Peak memory 234744 kb
Host smart-a8b7fbde-5768-48e6-8090-fe65e11d981b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193903095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4193903095
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2611648173
Short name T2
Test name
Test status
Simulation time 430468295 ps
CPU time 18.77 seconds
Started Aug 11 06:52:17 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 220032 kb
Host smart-4115a530-a370-4e50-9add-0e7b79f27338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611648173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2611648173
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3399501040
Short name T29
Test name
Test status
Simulation time 1244445660 ps
CPU time 10.54 seconds
Started Aug 11 06:52:17 PM PDT 24
Finished Aug 11 06:52:27 PM PDT 24
Peak memory 220084 kb
Host smart-0dd8a4e2-3cff-412c-8b76-d491bfca6529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3399501040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3399501040
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1154269036
Short name T74
Test name
Test status
Simulation time 462301452 ps
CPU time 27.51 seconds
Started Aug 11 06:52:16 PM PDT 24
Finished Aug 11 06:52:44 PM PDT 24
Peak memory 220040 kb
Host smart-051a4178-831b-4851-9f2e-36efaba3f3d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154269036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1154269036
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3364848320
Short name T100
Test name
Test status
Simulation time 970435109 ps
CPU time 8.27 seconds
Started Aug 11 06:52:22 PM PDT 24
Finished Aug 11 06:52:30 PM PDT 24
Peak memory 219068 kb
Host smart-d6c0a41e-2eb5-452e-83bf-fd54512c82f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364848320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3364848320
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4040143710
Short name T31
Test name
Test status
Simulation time 5757449084 ps
CPU time 278.48 seconds
Started Aug 11 06:52:19 PM PDT 24
Finished Aug 11 06:56:57 PM PDT 24
Peak memory 234612 kb
Host smart-611c952b-3a14-4d55-9d5e-2a9082513172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040143710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4040143710
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1419786619
Short name T270
Test name
Test status
Simulation time 4074862908 ps
CPU time 32.67 seconds
Started Aug 11 06:52:21 PM PDT 24
Finished Aug 11 06:52:54 PM PDT 24
Peak memory 219528 kb
Host smart-f70b81c4-1b13-4bf5-bab5-64c88bcf697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419786619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1419786619
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2282142267
Short name T109
Test name
Test status
Simulation time 3662465620 ps
CPU time 12.1 seconds
Started Aug 11 06:52:19 PM PDT 24
Finished Aug 11 06:52:32 PM PDT 24
Peak memory 220228 kb
Host smart-89e3f430-5948-4a6b-8311-c5bfcacb5b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282142267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2282142267
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3356011036
Short name T233
Test name
Test status
Simulation time 531494150 ps
CPU time 32.99 seconds
Started Aug 11 06:52:23 PM PDT 24
Finished Aug 11 06:52:56 PM PDT 24
Peak memory 220044 kb
Host smart-be59d97e-5ac1-4d99-bff9-a5ca809ab130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356011036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3356011036
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1815409043
Short name T47
Test name
Test status
Simulation time 34711334316 ps
CPU time 1382.25 seconds
Started Aug 11 06:52:22 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 236768 kb
Host smart-b66f663b-cc78-4693-bc2c-8318b079db74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815409043 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1815409043
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1133942333
Short name T128
Test name
Test status
Simulation time 251008924 ps
CPU time 10.01 seconds
Started Aug 11 06:52:19 PM PDT 24
Finished Aug 11 06:52:29 PM PDT 24
Peak memory 219052 kb
Host smart-5a42e1fd-cd64-4866-9c9f-9455fed3790e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133942333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1133942333
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3751990156
Short name T288
Test name
Test status
Simulation time 7818943972 ps
CPU time 152.13 seconds
Started Aug 11 06:52:19 PM PDT 24
Finished Aug 11 06:54:52 PM PDT 24
Peak memory 225316 kb
Host smart-9dc2baad-2d3e-4ce8-9b67-077295934ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751990156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3751990156
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1947054533
Short name T294
Test name
Test status
Simulation time 4139969774 ps
CPU time 19.11 seconds
Started Aug 11 06:52:22 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 220220 kb
Host smart-c2b0a379-ad23-4d1a-9737-299970ddf023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947054533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1947054533
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.325928097
Short name T179
Test name
Test status
Simulation time 726692839 ps
CPU time 10.12 seconds
Started Aug 11 06:52:20 PM PDT 24
Finished Aug 11 06:52:30 PM PDT 24
Peak memory 220064 kb
Host smart-6e438c84-c2ee-4ad9-8a1c-f57cc1d36d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325928097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.325928097
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.609397858
Short name T281
Test name
Test status
Simulation time 761917258 ps
CPU time 24.08 seconds
Started Aug 11 06:52:21 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 220064 kb
Host smart-8affbac4-187e-4efa-84eb-854221d7469d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609397858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.609397858
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1515291222
Short name T50
Test name
Test status
Simulation time 47150024008 ps
CPU time 1967.91 seconds
Started Aug 11 06:52:24 PM PDT 24
Finished Aug 11 07:25:12 PM PDT 24
Peak memory 251288 kb
Host smart-b0000721-bfb6-4e2a-a53e-407624b01928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515291222 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1515291222
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.348253605
Short name T10
Test name
Test status
Simulation time 176131774 ps
CPU time 8.36 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 219328 kb
Host smart-9627841e-b609-4dcf-8c2f-457a359c1514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348253605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.348253605
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3307106830
Short name T282
Test name
Test status
Simulation time 4088992892 ps
CPU time 236.65 seconds
Started Aug 11 06:52:20 PM PDT 24
Finished Aug 11 06:56:17 PM PDT 24
Peak memory 234468 kb
Host smart-da102df1-d7de-43fd-a39e-4392e3af6e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307106830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3307106830
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3651251475
Short name T43
Test name
Test status
Simulation time 690036797 ps
CPU time 18.79 seconds
Started Aug 11 06:52:26 PM PDT 24
Finished Aug 11 06:52:45 PM PDT 24
Peak memory 220000 kb
Host smart-bbf70f70-2478-43de-ac40-a567c5ed9dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651251475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3651251475
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.572177373
Short name T158
Test name
Test status
Simulation time 268364532 ps
CPU time 12.82 seconds
Started Aug 11 06:52:22 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 220076 kb
Host smart-e6568ceb-6773-4e5f-919c-3f8a363650c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572177373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.572177373
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3331571063
Short name T222
Test name
Test status
Simulation time 7538663734 ps
CPU time 34.53 seconds
Started Aug 11 06:52:21 PM PDT 24
Finished Aug 11 06:52:56 PM PDT 24
Peak memory 220128 kb
Host smart-7b2bf49e-82f0-4e64-9fa7-f4280a4299af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331571063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3331571063
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3507153083
Short name T197
Test name
Test status
Simulation time 1028639214 ps
CPU time 9.97 seconds
Started Aug 11 06:52:26 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 219020 kb
Host smart-45c2968a-596f-4203-85e7-518c309104e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507153083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3507153083
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3886972976
Short name T187
Test name
Test status
Simulation time 3212823396 ps
CPU time 147.34 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:54:52 PM PDT 24
Peak memory 237812 kb
Host smart-5bea2b37-cfc6-4d36-aeef-2105b262ae52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886972976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3886972976
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.790290458
Short name T174
Test name
Test status
Simulation time 1017621473 ps
CPU time 22.4 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 219944 kb
Host smart-d55f20e7-123f-4d42-b7f8-477a39e4f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790290458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.790290458
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.723068562
Short name T234
Test name
Test status
Simulation time 314884644 ps
CPU time 12.45 seconds
Started Aug 11 06:52:27 PM PDT 24
Finished Aug 11 06:52:39 PM PDT 24
Peak memory 220052 kb
Host smart-af29fccb-e3fb-463d-aa0e-e23822c5de5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723068562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.723068562
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3819209280
Short name T97
Test name
Test status
Simulation time 1109953611 ps
CPU time 35.61 seconds
Started Aug 11 06:52:27 PM PDT 24
Finished Aug 11 06:53:03 PM PDT 24
Peak memory 219872 kb
Host smart-f8dd76fb-80ae-42ee-bed1-224b2f5191f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819209280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3819209280
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1564586831
Short name T152
Test name
Test status
Simulation time 325658347 ps
CPU time 8.63 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:51:37 PM PDT 24
Peak memory 219048 kb
Host smart-6b6a3305-f65b-4b41-a27c-6e8caa212ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564586831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1564586831
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.341467723
Short name T18
Test name
Test status
Simulation time 4179005311 ps
CPU time 241.87 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:55:33 PM PDT 24
Peak memory 239072 kb
Host smart-e05466bd-4299-4e01-9e63-b77bc95e5fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341467723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.341467723
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4022600741
Short name T209
Test name
Test status
Simulation time 4128699493 ps
CPU time 22.92 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:46 PM PDT 24
Peak memory 220264 kb
Host smart-4f10baa5-2c81-4201-93b9-a78a452ae254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022600741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4022600741
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1983257836
Short name T287
Test name
Test status
Simulation time 2351254216 ps
CPU time 12.28 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:43 PM PDT 24
Peak memory 220172 kb
Host smart-b4c8130f-9f3d-44e8-8036-bc19944e2e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983257836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1983257836
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4177148140
Short name T63
Test name
Test status
Simulation time 267945745 ps
CPU time 12.21 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:51:38 PM PDT 24
Peak memory 220000 kb
Host smart-4d3519e0-371d-47d1-9a2c-c1d9643c523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177148140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4177148140
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.198214669
Short name T223
Test name
Test status
Simulation time 2264645413 ps
CPU time 28.73 seconds
Started Aug 11 06:51:23 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 220092 kb
Host smart-13b3ac62-167d-437c-b933-e81f7d4240f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198214669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.198214669
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1484844783
Short name T48
Test name
Test status
Simulation time 24178271045 ps
CPU time 903 seconds
Started Aug 11 06:51:22 PM PDT 24
Finished Aug 11 07:06:25 PM PDT 24
Peak memory 236704 kb
Host smart-2e8030ee-cf61-454f-9095-a3dba2fac301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484844783 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1484844783
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2790944443
Short name T224
Test name
Test status
Simulation time 175325394 ps
CPU time 8.55 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:39 PM PDT 24
Peak memory 219080 kb
Host smart-a721ded9-88f4-4d89-9d12-5088b9434e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790944443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2790944443
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2150038189
Short name T126
Test name
Test status
Simulation time 5330541713 ps
CPU time 289.24 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:56:20 PM PDT 24
Peak memory 244148 kb
Host smart-2b791ee2-f8ca-4a56-bcf8-7f04b7a18ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150038189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2150038189
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.462249912
Short name T154
Test name
Test status
Simulation time 693248179 ps
CPU time 19.49 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:51:50 PM PDT 24
Peak memory 220052 kb
Host smart-b0cb497e-dcb6-489e-bb0a-f25a0d1bc863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462249912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.462249912
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2496181978
Short name T172
Test name
Test status
Simulation time 1167691563 ps
CPU time 10.67 seconds
Started Aug 11 06:51:22 PM PDT 24
Finished Aug 11 06:51:33 PM PDT 24
Peak memory 220092 kb
Host smart-e31e66fe-10df-4f89-a29d-2e3576d61bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496181978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2496181978
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1945689594
Short name T146
Test name
Test status
Simulation time 1709845019 ps
CPU time 10.22 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 220040 kb
Host smart-c78bef1f-cfa3-475e-a861-83a62f7e1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945689594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1945689594
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2781462043
Short name T8
Test name
Test status
Simulation time 1086620779 ps
CPU time 19.7 seconds
Started Aug 11 06:51:27 PM PDT 24
Finished Aug 11 06:51:46 PM PDT 24
Peak memory 219968 kb
Host smart-44293a24-5c17-48af-8387-b5ab9e026397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781462043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2781462043
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4044086644
Short name T52
Test name
Test status
Simulation time 111950092237 ps
CPU time 2105.9 seconds
Started Aug 11 06:51:22 PM PDT 24
Finished Aug 11 07:26:28 PM PDT 24
Peak memory 245396 kb
Host smart-b416a442-6389-40cd-9393-42f08777222c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044086644 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4044086644
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1078873145
Short name T240
Test name
Test status
Simulation time 255121443 ps
CPU time 10.06 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 219080 kb
Host smart-966c9e47-7a85-409b-95bb-71a4843818d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078873145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1078873145
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2476888744
Short name T244
Test name
Test status
Simulation time 2980224518 ps
CPU time 207.24 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:54:58 PM PDT 24
Peak memory 238004 kb
Host smart-aba54043-2e0e-4ce8-9af7-efe56c9e82c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476888744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2476888744
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.417987246
Short name T193
Test name
Test status
Simulation time 2057890661 ps
CPU time 22 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:51:47 PM PDT 24
Peak memory 220092 kb
Host smart-dfcec8b4-6007-44c5-a6db-a5897c5a318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417987246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.417987246
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.904081704
Short name T254
Test name
Test status
Simulation time 1063444358 ps
CPU time 11.85 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:51:43 PM PDT 24
Peak memory 220052 kb
Host smart-9f59e625-09e0-4172-b940-28a70771149f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904081704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.904081704
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3700694400
Short name T246
Test name
Test status
Simulation time 771868763 ps
CPU time 10.63 seconds
Started Aug 11 06:51:24 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 220064 kb
Host smart-0c81974e-dc2a-4d1a-9ba9-021abd818cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700694400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3700694400
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1672123476
Short name T149
Test name
Test status
Simulation time 535149196 ps
CPU time 27.62 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:58 PM PDT 24
Peak memory 220052 kb
Host smart-888c98f2-926c-48d5-a63b-f6c72e3aded3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672123476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1672123476
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1188558948
Short name T269
Test name
Test status
Simulation time 507477398 ps
CPU time 10.17 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:51:39 PM PDT 24
Peak memory 219036 kb
Host smart-ace04489-b0e8-4a06-9ccc-96f9f837f4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188558948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1188558948
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2907739621
Short name T151
Test name
Test status
Simulation time 3537032044 ps
CPU time 180.9 seconds
Started Aug 11 06:51:35 PM PDT 24
Finished Aug 11 06:54:36 PM PDT 24
Peak memory 241656 kb
Host smart-6b8f896c-f805-4b92-ad3d-d3d410bb434e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907739621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2907739621
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2739923609
Short name T182
Test name
Test status
Simulation time 2159818752 ps
CPU time 22.94 seconds
Started Aug 11 06:51:29 PM PDT 24
Finished Aug 11 06:51:52 PM PDT 24
Peak memory 220152 kb
Host smart-ded5885c-cc2c-4867-8116-04816cc5e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739923609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2739923609
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1490940904
Short name T162
Test name
Test status
Simulation time 701982937 ps
CPU time 10.23 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:51:35 PM PDT 24
Peak memory 220088 kb
Host smart-b34bec63-b8eb-4524-9dfb-b5e1cf14b27b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490940904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1490940904
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1222576266
Short name T258
Test name
Test status
Simulation time 603991097 ps
CPU time 12.23 seconds
Started Aug 11 06:51:25 PM PDT 24
Finished Aug 11 06:51:37 PM PDT 24
Peak memory 220096 kb
Host smart-1320bffe-a14c-495a-8908-b82714c032d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222576266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1222576266
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3931945022
Short name T312
Test name
Test status
Simulation time 2515745501 ps
CPU time 34.69 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 220148 kb
Host smart-8a117a63-a5b9-4f9b-b377-a59df7ab5913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931945022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3931945022
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4272093217
Short name T218
Test name
Test status
Simulation time 261051392 ps
CPU time 10.1 seconds
Started Aug 11 06:51:31 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 219176 kb
Host smart-35153b4b-8f17-4c6b-9666-a699b8e209d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272093217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4272093217
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2262974117
Short name T206
Test name
Test status
Simulation time 8507255133 ps
CPU time 304.58 seconds
Started Aug 11 06:51:35 PM PDT 24
Finished Aug 11 06:56:39 PM PDT 24
Peak memory 226488 kb
Host smart-6a55beb8-4e7b-4ed2-b4d7-e4c5d935435f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262974117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2262974117
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.738140509
Short name T278
Test name
Test status
Simulation time 734834478 ps
CPU time 19.23 seconds
Started Aug 11 06:51:30 PM PDT 24
Finished Aug 11 06:51:50 PM PDT 24
Peak memory 220080 kb
Host smart-7be33897-c38a-48f3-aa55-3d1dc621963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738140509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.738140509
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1237549597
Short name T95
Test name
Test status
Simulation time 1053648851 ps
CPU time 11.79 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:51:40 PM PDT 24
Peak memory 220064 kb
Host smart-78db4019-a418-4fbd-8e4e-2ef7a0521219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237549597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1237549597
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2646571601
Short name T217
Test name
Test status
Simulation time 3656032336 ps
CPU time 11.97 seconds
Started Aug 11 06:51:29 PM PDT 24
Finished Aug 11 06:51:41 PM PDT 24
Peak memory 220128 kb
Host smart-52768246-fad8-4aec-ba7d-16b6ecccf9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646571601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2646571601
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2509464516
Short name T136
Test name
Test status
Simulation time 4257461914 ps
CPU time 22.94 seconds
Started Aug 11 06:51:28 PM PDT 24
Finished Aug 11 06:51:51 PM PDT 24
Peak memory 220196 kb
Host smart-5d67610d-476b-4b1d-abaa-1bc8e32cfd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509464516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2509464516
Directory /workspace/9.rom_ctrl_stress_all/latest
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