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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.48 96.65 88.34 97.68 100.00 96.90 97.45 98.37


Total test records in report: 409
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T306 /workspace/coverage/default/37.rom_ctrl_stress_all.655882255 Aug 13 05:12:49 PM PDT 24 Aug 13 05:13:02 PM PDT 24 925000310 ps
T307 /workspace/coverage/default/24.rom_ctrl_alert_test.219303660 Aug 13 05:12:26 PM PDT 24 Aug 13 05:12:36 PM PDT 24 592995237 ps
T308 /workspace/coverage/default/23.rom_ctrl_alert_test.1581262113 Aug 13 05:12:24 PM PDT 24 Aug 13 05:12:35 PM PDT 24 262309793 ps
T309 /workspace/coverage/default/28.rom_ctrl_stress_all.3198754976 Aug 13 05:12:35 PM PDT 24 Aug 13 05:13:10 PM PDT 24 1089826576 ps
T310 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3086790752 Aug 13 05:12:57 PM PDT 24 Aug 13 05:13:07 PM PDT 24 362069040 ps
T311 /workspace/coverage/default/16.rom_ctrl_alert_test.776643006 Aug 13 05:12:10 PM PDT 24 Aug 13 05:12:19 PM PDT 24 338392667 ps
T123 /workspace/coverage/default/21.rom_ctrl_stress_all.1458558111 Aug 13 05:12:29 PM PDT 24 Aug 13 05:13:01 PM PDT 24 1151069067 ps
T312 /workspace/coverage/default/8.rom_ctrl_stress_all.742977349 Aug 13 05:12:06 PM PDT 24 Aug 13 05:12:40 PM PDT 24 539390292 ps
T313 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2403968054 Aug 13 05:13:01 PM PDT 24 Aug 13 05:13:12 PM PDT 24 353374796 ps
T314 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1298787151 Aug 13 05:12:04 PM PDT 24 Aug 13 05:14:49 PM PDT 24 2561021109 ps
T315 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3687330926 Aug 13 05:12:25 PM PDT 24 Aug 13 05:12:38 PM PDT 24 516978325 ps
T316 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2225537686 Aug 13 05:12:03 PM PDT 24 Aug 13 05:16:17 PM PDT 24 14497766804 ps
T317 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3946427702 Aug 13 05:12:15 PM PDT 24 Aug 13 05:14:48 PM PDT 24 28247025264 ps
T318 /workspace/coverage/default/47.rom_ctrl_alert_test.424489132 Aug 13 05:12:57 PM PDT 24 Aug 13 05:13:07 PM PDT 24 496726974 ps
T23 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4105697504 Aug 13 04:46:24 PM PDT 24 Aug 13 04:47:48 PM PDT 24 594929910 ps
T24 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.638607570 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:37 PM PDT 24 346057786 ps
T48 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.609409926 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:29 PM PDT 24 661067826 ps
T49 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1946455501 Aug 13 04:46:29 PM PDT 24 Aug 13 04:46:39 PM PDT 24 259777013 ps
T25 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2678757515 Aug 13 04:46:11 PM PDT 24 Aug 13 04:47:32 PM PDT 24 453166521 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2494316386 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:33 PM PDT 24 1103267699 ps
T26 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1411704415 Aug 13 04:46:18 PM PDT 24 Aug 13 04:49:00 PM PDT 24 476675311 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1266995494 Aug 13 04:46:28 PM PDT 24 Aug 13 04:47:25 PM PDT 24 1091376681 ps
T39 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2036699331 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:32 PM PDT 24 1042203594 ps
T40 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1372381410 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:38 PM PDT 24 172919136 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.127061297 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:34 PM PDT 24 663613529 ps
T42 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1422078823 Aug 13 04:46:25 PM PDT 24 Aug 13 04:47:51 PM PDT 24 421802824 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2363155892 Aug 13 04:46:19 PM PDT 24 Aug 13 04:46:29 PM PDT 24 1546338646 ps
T43 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3929947993 Aug 13 04:46:24 PM PDT 24 Aug 13 04:48:59 PM PDT 24 711479481 ps
T44 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3282804529 Aug 13 04:46:24 PM PDT 24 Aug 13 04:46:35 PM PDT 24 272886895 ps
T98 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.898624482 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:35 PM PDT 24 1653246369 ps
T45 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2849741586 Aug 13 04:46:33 PM PDT 24 Aug 13 04:46:46 PM PDT 24 345452136 ps
T66 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2214872542 Aug 13 04:46:24 PM PDT 24 Aug 13 04:48:01 PM PDT 24 27029035604 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3144425085 Aug 13 04:46:32 PM PDT 24 Aug 13 04:46:42 PM PDT 24 508404645 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2415101404 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:30 PM PDT 24 459960655 ps
T319 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1269498728 Aug 13 04:46:13 PM PDT 24 Aug 13 04:46:21 PM PDT 24 174235162 ps
T320 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.87121412 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:31 PM PDT 24 263435366 ps
T321 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.148522229 Aug 13 04:46:26 PM PDT 24 Aug 13 04:46:34 PM PDT 24 346263027 ps
T322 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4162266396 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 444192833 ps
T323 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1503756609 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 1031185415 ps
T324 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2698360905 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:19 PM PDT 24 690712065 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2735617576 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:20 PM PDT 24 603710488 ps
T57 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3185746594 Aug 13 04:46:27 PM PDT 24 Aug 13 04:46:37 PM PDT 24 1003764565 ps
T58 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1499066770 Aug 13 04:46:18 PM PDT 24 Aug 13 04:46:29 PM PDT 24 1068594689 ps
T325 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1971740398 Aug 13 04:46:13 PM PDT 24 Aug 13 04:46:31 PM PDT 24 265906861 ps
T60 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3238439629 Aug 13 04:46:22 PM PDT 24 Aug 13 04:47:44 PM PDT 24 908573440 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.30241789 Aug 13 04:46:26 PM PDT 24 Aug 13 04:49:09 PM PDT 24 861245741 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1907655605 Aug 13 04:46:27 PM PDT 24 Aug 13 04:46:40 PM PDT 24 1769812186 ps
T326 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1855255430 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:32 PM PDT 24 249418401 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.128949932 Aug 13 04:46:12 PM PDT 24 Aug 13 04:47:10 PM PDT 24 1078302972 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2825067222 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:59 PM PDT 24 9821938900 ps
T327 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1727008141 Aug 13 04:46:09 PM PDT 24 Aug 13 04:47:17 PM PDT 24 6107569443 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.814280034 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 534717246 ps
T72 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1160578608 Aug 13 04:46:28 PM PDT 24 Aug 13 04:46:38 PM PDT 24 508383523 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4180753681 Aug 13 04:46:08 PM PDT 24 Aug 13 04:47:05 PM PDT 24 1032416596 ps
T328 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2509658168 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:34 PM PDT 24 206223401 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1397443792 Aug 13 04:46:19 PM PDT 24 Aug 13 04:46:31 PM PDT 24 178745660 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.965581814 Aug 13 04:46:25 PM PDT 24 Aug 13 04:49:05 PM PDT 24 549541623 ps
T329 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4214657329 Aug 13 04:46:18 PM PDT 24 Aug 13 04:46:28 PM PDT 24 260000334 ps
T330 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1663379599 Aug 13 04:46:13 PM PDT 24 Aug 13 04:46:21 PM PDT 24 719246019 ps
T100 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4079841595 Aug 13 04:46:23 PM PDT 24 Aug 13 04:46:31 PM PDT 24 167945529 ps
T331 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1198181197 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:31 PM PDT 24 167321613 ps
T332 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2439353455 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:40 PM PDT 24 1971072937 ps
T333 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2847935852 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:34 PM PDT 24 518202369 ps
T334 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2403762732 Aug 13 04:46:20 PM PDT 24 Aug 13 04:46:31 PM PDT 24 269608157 ps
T335 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1750767176 Aug 13 04:46:27 PM PDT 24 Aug 13 04:46:42 PM PDT 24 279957945 ps
T336 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.395454385 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:33 PM PDT 24 172570142 ps
T337 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3703104202 Aug 13 04:46:13 PM PDT 24 Aug 13 04:46:21 PM PDT 24 173456032 ps
T338 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3358340213 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:31 PM PDT 24 3523210248 ps
T339 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1928946255 Aug 13 04:46:12 PM PDT 24 Aug 13 04:46:28 PM PDT 24 260513556 ps
T340 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3770810287 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:19 PM PDT 24 917068763 ps
T341 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1554938253 Aug 13 04:46:24 PM PDT 24 Aug 13 04:46:39 PM PDT 24 257605816 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2421385372 Aug 13 04:46:14 PM PDT 24 Aug 13 04:46:26 PM PDT 24 212592273 ps
T342 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2115587945 Aug 13 04:46:20 PM PDT 24 Aug 13 04:46:40 PM PDT 24 2141356287 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3130842804 Aug 13 04:46:27 PM PDT 24 Aug 13 04:49:06 PM PDT 24 1130127646 ps
T343 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2507585262 Aug 13 04:46:23 PM PDT 24 Aug 13 04:46:32 PM PDT 24 368958819 ps
T344 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3851263411 Aug 13 04:46:24 PM PDT 24 Aug 13 04:46:34 PM PDT 24 185662801 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.248037123 Aug 13 04:46:21 PM PDT 24 Aug 13 04:48:57 PM PDT 24 1167745628 ps
T345 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.29777257 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 197720799 ps
T346 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1053947451 Aug 13 04:46:27 PM PDT 24 Aug 13 04:46:38 PM PDT 24 270570565 ps
T347 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1957661423 Aug 13 04:46:33 PM PDT 24 Aug 13 04:47:39 PM PDT 24 6339955170 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3123919761 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 250407274 ps
T348 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2972019806 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:36 PM PDT 24 571260457 ps
T349 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3489691502 Aug 13 04:46:20 PM PDT 24 Aug 13 04:47:42 PM PDT 24 4720627081 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1729639517 Aug 13 04:46:28 PM PDT 24 Aug 13 04:49:10 PM PDT 24 602207225 ps
T350 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3715951754 Aug 13 04:46:23 PM PDT 24 Aug 13 04:46:35 PM PDT 24 346167374 ps
T351 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1469965228 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:19 PM PDT 24 176478951 ps
T352 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3529710220 Aug 13 04:46:20 PM PDT 24 Aug 13 04:46:28 PM PDT 24 661564968 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1401851100 Aug 13 04:46:27 PM PDT 24 Aug 13 04:47:34 PM PDT 24 10090233703 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1340789388 Aug 13 04:46:33 PM PDT 24 Aug 13 04:46:41 PM PDT 24 663324235 ps
T353 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1125172121 Aug 13 04:46:24 PM PDT 24 Aug 13 04:46:34 PM PDT 24 179409722 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.110202141 Aug 13 04:46:13 PM PDT 24 Aug 13 04:49:00 PM PDT 24 1763747143 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4009641407 Aug 13 04:46:19 PM PDT 24 Aug 13 04:47:03 PM PDT 24 1056818806 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1830733362 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:20 PM PDT 24 990956986 ps
T355 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1669111296 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:34 PM PDT 24 1031590878 ps
T356 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.206254597 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:20 PM PDT 24 168044267 ps
T357 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2312766113 Aug 13 04:46:20 PM PDT 24 Aug 13 04:46:30 PM PDT 24 3093244842 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2995910430 Aug 13 04:46:10 PM PDT 24 Aug 13 04:47:07 PM PDT 24 1071209054 ps
T359 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.198558586 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:18 PM PDT 24 1375376594 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4176565981 Aug 13 04:46:19 PM PDT 24 Aug 13 04:46:29 PM PDT 24 250466343 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3288825086 Aug 13 04:46:26 PM PDT 24 Aug 13 04:46:36 PM PDT 24 1892564406 ps
T361 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3423438407 Aug 13 04:46:32 PM PDT 24 Aug 13 04:46:40 PM PDT 24 174782037 ps
T362 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.275221121 Aug 13 04:46:26 PM PDT 24 Aug 13 04:46:37 PM PDT 24 167509565 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1409781695 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:21 PM PDT 24 269423315 ps
T364 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1139974964 Aug 13 04:46:19 PM PDT 24 Aug 13 04:46:30 PM PDT 24 1066088578 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1116110341 Aug 13 04:46:28 PM PDT 24 Aug 13 04:46:39 PM PDT 24 1015802225 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.424421747 Aug 13 04:46:28 PM PDT 24 Aug 13 04:47:06 PM PDT 24 2287877387 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2998677478 Aug 13 04:46:23 PM PDT 24 Aug 13 04:46:36 PM PDT 24 249850650 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1167224636 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:24 PM PDT 24 279221580 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1749262826 Aug 13 04:46:32 PM PDT 24 Aug 13 04:46:42 PM PDT 24 369955896 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3272208008 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:23 PM PDT 24 1035697349 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3682632075 Aug 13 04:46:14 PM PDT 24 Aug 13 04:48:51 PM PDT 24 1559930147 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2080358574 Aug 13 04:46:13 PM PDT 24 Aug 13 04:46:23 PM PDT 24 492667635 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.251946007 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:20 PM PDT 24 347791567 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3348187625 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:23 PM PDT 24 176619741 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1727132537 Aug 13 04:46:19 PM PDT 24 Aug 13 04:47:04 PM PDT 24 9247442125 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3354413167 Aug 13 04:46:26 PM PDT 24 Aug 13 04:47:49 PM PDT 24 1291014755 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4045954010 Aug 13 04:46:18 PM PDT 24 Aug 13 04:46:30 PM PDT 24 699519900 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.382244239 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:35 PM PDT 24 254551180 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1534327020 Aug 13 04:46:12 PM PDT 24 Aug 13 04:46:24 PM PDT 24 265320047 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.192439319 Aug 13 04:46:09 PM PDT 24 Aug 13 04:46:23 PM PDT 24 1033177632 ps
T89 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2318064921 Aug 13 04:46:23 PM PDT 24 Aug 13 04:47:01 PM PDT 24 1640396090 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3101331252 Aug 13 04:46:08 PM PDT 24 Aug 13 04:46:18 PM PDT 24 1028461465 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3862492828 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:21 PM PDT 24 250201127 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2546259733 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:20 PM PDT 24 250007607 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.131326870 Aug 13 04:46:20 PM PDT 24 Aug 13 04:47:04 PM PDT 24 6342542652 ps
T381 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.346241237 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:30 PM PDT 24 397098139 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.552586900 Aug 13 04:46:24 PM PDT 24 Aug 13 04:46:34 PM PDT 24 519268504 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4106624131 Aug 13 04:46:27 PM PDT 24 Aug 13 04:47:12 PM PDT 24 4216406644 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2216388220 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:35 PM PDT 24 1033932648 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.988135936 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:36 PM PDT 24 496231699 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3038831662 Aug 13 04:46:12 PM PDT 24 Aug 13 04:46:22 PM PDT 24 253295928 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.322052782 Aug 13 04:46:31 PM PDT 24 Aug 13 04:46:40 PM PDT 24 933020410 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1841255087 Aug 13 04:46:22 PM PDT 24 Aug 13 04:46:33 PM PDT 24 1057128452 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1253675516 Aug 13 04:46:20 PM PDT 24 Aug 13 04:48:56 PM PDT 24 1413527287 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3835108140 Aug 13 04:46:18 PM PDT 24 Aug 13 04:46:30 PM PDT 24 1060712868 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3003779165 Aug 13 04:46:10 PM PDT 24 Aug 13 04:47:34 PM PDT 24 557646590 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3904690350 Aug 13 04:46:17 PM PDT 24 Aug 13 04:48:59 PM PDT 24 1098479495 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1664409293 Aug 13 04:46:13 PM PDT 24 Aug 13 04:47:49 PM PDT 24 11913962144 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1276759454 Aug 13 04:46:26 PM PDT 24 Aug 13 04:46:36 PM PDT 24 517305407 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3916510876 Aug 13 04:46:19 PM PDT 24 Aug 13 04:46:31 PM PDT 24 410996493 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1608550889 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:39 PM PDT 24 3080929255 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.835051819 Aug 13 04:46:12 PM PDT 24 Aug 13 04:46:20 PM PDT 24 416152305 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1301562633 Aug 13 04:46:14 PM PDT 24 Aug 13 04:46:25 PM PDT 24 1032773999 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1473088241 Aug 13 04:46:21 PM PDT 24 Aug 13 04:46:30 PM PDT 24 358418214 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2687648801 Aug 13 04:46:29 PM PDT 24 Aug 13 04:46:37 PM PDT 24 340658604 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1096514531 Aug 13 04:46:27 PM PDT 24 Aug 13 04:47:55 PM PDT 24 428866922 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3373879750 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:20 PM PDT 24 478243452 ps
T400 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3196116242 Aug 13 04:46:23 PM PDT 24 Aug 13 04:47:19 PM PDT 24 1052316262 ps
T401 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1643831419 Aug 13 04:46:12 PM PDT 24 Aug 13 04:46:29 PM PDT 24 258492382 ps
T402 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3997859333 Aug 13 04:46:28 PM PDT 24 Aug 13 04:46:38 PM PDT 24 443384607 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4142258947 Aug 13 04:46:10 PM PDT 24 Aug 13 04:46:20 PM PDT 24 4913815304 ps
T88 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2907107804 Aug 13 04:46:23 PM PDT 24 Aug 13 04:47:19 PM PDT 24 2099780699 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1618944796 Aug 13 04:46:11 PM PDT 24 Aug 13 04:46:27 PM PDT 24 1314195095 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.859853280 Aug 13 04:46:20 PM PDT 24 Aug 13 04:46:58 PM PDT 24 2028284239 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2378433591 Aug 13 04:46:21 PM PDT 24 Aug 13 04:47:27 PM PDT 24 3534866231 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1807853261 Aug 13 04:46:28 PM PDT 24 Aug 13 04:46:37 PM PDT 24 206050060 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3858041245 Aug 13 04:46:25 PM PDT 24 Aug 13 04:46:38 PM PDT 24 1912597213 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3346095621 Aug 13 04:46:28 PM PDT 24 Aug 13 04:46:37 PM PDT 24 589987203 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1718357886 Aug 13 04:46:24 PM PDT 24 Aug 13 04:47:49 PM PDT 24 371127813 ps

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2315799415
Short name T8
Test name
Test status
Simulation time 727159335 ps
CPU time 41.25 seconds
Started Aug 13 05:12:16 PM PDT 24
Finished Aug 13 05:12:58 PM PDT 24
Peak memory 219232 kb
Host smart-948bc788-23bc-48a7-9645-887d034bf0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315799415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2315799415
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3345323111
Short name T6
Test name
Test status
Simulation time 5039718241 ps
CPU time 252.95 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:16:48 PM PDT 24
Peak memory 242728 kb
Host smart-0c3d1059-07a5-402b-ba22-8d24fa74c51e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345323111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3345323111
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1372381410
Short name T40
Test name
Test status
Simulation time 172919136 ps
CPU time 13.52 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:38 PM PDT 24
Peak memory 217696 kb
Host smart-dc162e74-918e-40b8-b21f-c177b6ffa062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372381410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1372381410
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.381679393
Short name T91
Test name
Test status
Simulation time 179072222 ps
CPU time 10.57 seconds
Started Aug 13 05:12:07 PM PDT 24
Finished Aug 13 05:12:18 PM PDT 24
Peak memory 219160 kb
Host smart-17cc6534-b5a3-4a18-9a00-e91f3481a775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381679393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.381679393
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2687724179
Short name T11
Test name
Test status
Simulation time 397717304 ps
CPU time 29.12 seconds
Started Aug 13 05:12:37 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 219368 kb
Host smart-52613b9a-ef39-47f9-802d-0760a9aa3923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687724179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2687724179
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2678757515
Short name T25
Test name
Test status
Simulation time 453166521 ps
CPU time 81.01 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:47:32 PM PDT 24
Peak memory 213924 kb
Host smart-7c388043-3c7f-44db-b72f-5a3470ff6197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678757515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2678757515
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3780952057
Short name T54
Test name
Test status
Simulation time 506655521 ps
CPU time 10.22 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:12:52 PM PDT 24
Peak memory 218520 kb
Host smart-74ae5401-ee7b-40b6-869b-9325954c7397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780952057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3780952057
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.763297736
Short name T16
Test name
Test status
Simulation time 806986032 ps
CPU time 12.38 seconds
Started Aug 13 05:12:55 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 219212 kb
Host smart-549a38e9-6a96-43c1-8c21-4f69db30f4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763297736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.763297736
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.28182108
Short name T20
Test name
Test status
Simulation time 733514059 ps
CPU time 223.43 seconds
Started Aug 13 05:11:54 PM PDT 24
Finished Aug 13 05:15:37 PM PDT 24
Peak memory 238932 kb
Host smart-87a88b90-34b9-44cd-86cb-c5da05c15143
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.28182108
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1411704415
Short name T26
Test name
Test status
Simulation time 476675311 ps
CPU time 161.59 seconds
Started Aug 13 04:46:18 PM PDT 24
Finished Aug 13 04:49:00 PM PDT 24
Peak memory 214388 kb
Host smart-2e462e40-b244-4b72-94d4-5a7f73aef147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411704415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1411704415
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.858798682
Short name T75
Test name
Test status
Simulation time 2079695917 ps
CPU time 36.07 seconds
Started Aug 13 05:11:50 PM PDT 24
Finished Aug 13 05:12:27 PM PDT 24
Peak memory 219308 kb
Host smart-f791b4a1-5222-43f1-bb11-7ddd47c8c474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858798682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.858798682
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1216971516
Short name T127
Test name
Test status
Simulation time 10688757558 ps
CPU time 283.14 seconds
Started Aug 13 05:12:16 PM PDT 24
Finished Aug 13 05:16:59 PM PDT 24
Peak memory 239276 kb
Host smart-3659d663-03a0-4cc3-92ef-203420a54a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216971516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1216971516
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1266995494
Short name T65
Test name
Test status
Simulation time 1091376681 ps
CPU time 57.46 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:47:25 PM PDT 24
Peak memory 214256 kb
Host smart-e46ece50-3508-473b-91b1-a46e79e30bb2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266995494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1266995494
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3131480335
Short name T78
Test name
Test status
Simulation time 560474670 ps
CPU time 20.42 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:12:55 PM PDT 24
Peak memory 219244 kb
Host smart-b1918313-43ce-432e-8f9c-77517b8a5371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131480335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3131480335
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3701974366
Short name T113
Test name
Test status
Simulation time 4287309700 ps
CPU time 208.48 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 237936 kb
Host smart-cac94d48-d8d1-4cab-99a7-16e96e4abf50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701974366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3701974366
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2825067222
Short name T71
Test name
Test status
Simulation time 9821938900 ps
CPU time 38.21 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:59 PM PDT 24
Peak memory 215184 kb
Host smart-4afc345b-a799-4d73-b074-004c2df388d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825067222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2825067222
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2312491908
Short name T176
Test name
Test status
Simulation time 1013043526 ps
CPU time 22.82 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219432 kb
Host smart-dad75dfe-213d-4009-a740-59cae403d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312491908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2312491908
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1393770280
Short name T30
Test name
Test status
Simulation time 5053588219 ps
CPU time 193.51 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:16:03 PM PDT 24
Peak memory 229664 kb
Host smart-d3963f29-ddcc-4b04-92f2-062a0a533526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393770280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1393770280
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2330142560
Short name T240
Test name
Test status
Simulation time 4712210930 ps
CPU time 19.84 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 219540 kb
Host smart-eaee166c-edee-46c2-a4eb-1add08266741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330142560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2330142560
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1729639517
Short name T105
Test name
Test status
Simulation time 602207225 ps
CPU time 161.61 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:49:10 PM PDT 24
Peak memory 219104 kb
Host smart-73ff0cce-ec9c-4a1b-95ac-08ed3058eeba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729639517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1729639517
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3417754552
Short name T228
Test name
Test status
Simulation time 184394950 ps
CPU time 11.17 seconds
Started Aug 13 05:12:11 PM PDT 24
Finished Aug 13 05:12:22 PM PDT 24
Peak memory 219308 kb
Host smart-8933c2a4-64f0-48e7-88e8-297671f6c6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417754552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3417754552
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.110202141
Short name T112
Test name
Test status
Simulation time 1763747143 ps
CPU time 166.47 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:49:00 PM PDT 24
Peak memory 215676 kb
Host smart-93a6d2b9-e90a-4623-87f4-cb007dadc2af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110202141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.110202141
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3003779165
Short name T108
Test name
Test status
Simulation time 557646590 ps
CPU time 83.69 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:47:34 PM PDT 24
Peak memory 212916 kb
Host smart-1590e091-7367-49ca-b597-94dc4ddea5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003779165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3003779165
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3929947993
Short name T43
Test name
Test status
Simulation time 711479481 ps
CPU time 153.94 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:48:59 PM PDT 24
Peak memory 214300 kb
Host smart-4c9b45f7-daf5-4a11-84cf-057bf3243435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929947993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3929947993
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2786072565
Short name T56
Test name
Test status
Simulation time 636531054 ps
CPU time 8.4 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:05 PM PDT 24
Peak memory 218288 kb
Host smart-d7b707dc-a3a8-42af-818e-00803b3dc842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786072565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2786072565
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2129484911
Short name T238
Test name
Test status
Simulation time 711946498 ps
CPU time 10.79 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:21 PM PDT 24
Peak memory 219280 kb
Host smart-8acae891-aeae-489a-a924-d66000dccb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129484911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2129484911
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4176485231
Short name T297
Test name
Test status
Simulation time 297623184 ps
CPU time 20.87 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:12:46 PM PDT 24
Peak memory 219324 kb
Host smart-e1dbe565-f795-43c2-aa3f-a88367007d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176485231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4176485231
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.251946007
Short name T86
Test name
Test status
Simulation time 347791567 ps
CPU time 8.24 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 210948 kb
Host smart-ef391208-0d53-4631-9367-dd24d9515e0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251946007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.251946007
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2698360905
Short name T324
Test name
Test status
Simulation time 690712065 ps
CPU time 8.79 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:19 PM PDT 24
Peak memory 210956 kb
Host smart-3a248bcf-778f-45f8-ab86-153781b78b7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698360905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2698360905
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2421385372
Short name T80
Test name
Test status
Simulation time 212592273 ps
CPU time 11.79 seconds
Started Aug 13 04:46:14 PM PDT 24
Finished Aug 13 04:46:26 PM PDT 24
Peak memory 211028 kb
Host smart-d8a1f4f8-3950-4287-93dc-0370f910fab1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421385372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2421385372
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.814280034
Short name T62
Test name
Test status
Simulation time 534717246 ps
CPU time 10.63 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 215948 kb
Host smart-d7eb383b-775c-49ba-b62a-a7bbcda724a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814280034 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.814280034
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2080358574
Short name T370
Test name
Test status
Simulation time 492667635 ps
CPU time 10.01 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:46:23 PM PDT 24
Peak memory 211148 kb
Host smart-1b0f10d1-6410-442f-b556-c4fe5197e2a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080358574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2080358574
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1830733362
Short name T354
Test name
Test status
Simulation time 990956986 ps
CPU time 9.43 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 210736 kb
Host smart-1af844c6-b29e-41f9-a6f7-a1c704f58e92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830733362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1830733362
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1469965228
Short name T351
Test name
Test status
Simulation time 176478951 ps
CPU time 7.98 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:19 PM PDT 24
Peak memory 210800 kb
Host smart-052ae64d-0ce8-4d19-9cb8-e07f65840ced
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469965228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1469965228
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1727008141
Short name T327
Test name
Test status
Simulation time 6107569443 ps
CPU time 67.36 seconds
Started Aug 13 04:46:09 PM PDT 24
Finished Aug 13 04:47:17 PM PDT 24
Peak memory 215660 kb
Host smart-e1931887-48a2-4124-a77f-de2789dcc380
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727008141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1727008141
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2735617576
Short name T69
Test name
Test status
Simulation time 603710488 ps
CPU time 9.92 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 211456 kb
Host smart-ebfb5bea-b1a8-4794-ad4d-e8bd1ce05a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735617576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2735617576
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1928946255
Short name T339
Test name
Test status
Simulation time 260513556 ps
CPU time 16.13 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:46:28 PM PDT 24
Peak memory 217884 kb
Host smart-da144c94-ac36-4251-8adc-513c0c776695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928946255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1928946255
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3123919761
Short name T81
Test name
Test status
Simulation time 250407274 ps
CPU time 10.05 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210956 kb
Host smart-b469a6e4-f256-42b8-b64a-639bcdd5c05b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123919761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3123919761
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1946455501
Short name T49
Test name
Test status
Simulation time 259777013 ps
CPU time 10.16 seconds
Started Aug 13 04:46:29 PM PDT 24
Finished Aug 13 04:46:39 PM PDT 24
Peak memory 210948 kb
Host smart-a0e8b47f-005a-43ba-93e5-9dbd9064788e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946455501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1946455501
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1618944796
Short name T403
Test name
Test status
Simulation time 1314195095 ps
CPU time 15.76 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:27 PM PDT 24
Peak memory 211308 kb
Host smart-280eb3f1-e994-4056-a519-5a36fddff5e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618944796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1618944796
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1409781695
Short name T363
Test name
Test status
Simulation time 269423315 ps
CPU time 11.46 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 219100 kb
Host smart-d4e29b8e-e03c-4521-b68b-f055b88ac2b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409781695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1409781695
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.198558586
Short name T359
Test name
Test status
Simulation time 1375376594 ps
CPU time 8.32 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:18 PM PDT 24
Peak memory 211452 kb
Host smart-de5fcc38-ca44-43dc-b0b5-3bc0602746a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198558586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.198558586
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3770810287
Short name T340
Test name
Test status
Simulation time 917068763 ps
CPU time 8.15 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:19 PM PDT 24
Peak memory 210748 kb
Host smart-f680c701-470f-4bb8-955e-ce183efbb574
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770810287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3770810287
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.206254597
Short name T356
Test name
Test status
Simulation time 168044267 ps
CPU time 8.22 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 210836 kb
Host smart-65dfe6a9-731c-45e1-a48b-84edb8be0b78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206254597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
206254597
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2995910430
Short name T358
Test name
Test status
Simulation time 1071209054 ps
CPU time 56.88 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:47:07 PM PDT 24
Peak memory 215208 kb
Host smart-c68049ab-36af-49f3-b07b-10f0f6e5d94a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995910430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2995910430
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3373879750
Short name T399
Test name
Test status
Simulation time 478243452 ps
CPU time 10.08 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 211740 kb
Host smart-adb74829-76dc-4dcb-a962-6e98445fcf45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373879750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3373879750
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3348187625
Short name T371
Test name
Test status
Simulation time 176619741 ps
CPU time 11.54 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:23 PM PDT 24
Peak memory 217808 kb
Host smart-676c493b-494b-4391-81e3-fd2ac89efedf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348187625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3348187625
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3282804529
Short name T44
Test name
Test status
Simulation time 272886895 ps
CPU time 10.86 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 217376 kb
Host smart-9846fb82-3fd0-4c42-94ac-7d3602d49941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282804529 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3282804529
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.898624482
Short name T98
Test name
Test status
Simulation time 1653246369 ps
CPU time 9.93 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 211292 kb
Host smart-7df0c482-edb8-4bdc-a930-513ac9543c6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898624482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.898624482
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.424421747
Short name T104
Test name
Test status
Simulation time 2287877387 ps
CPU time 37.8 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:47:06 PM PDT 24
Peak memory 214176 kb
Host smart-ca82fe5c-77f5-408c-a04e-d244d01249c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424421747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.424421747
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1276759454
Short name T391
Test name
Test status
Simulation time 517305407 ps
CPU time 9.88 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:46:36 PM PDT 24
Peak memory 211684 kb
Host smart-6b480264-3de6-4704-861a-2ca6d916396c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276759454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1276759454
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1608550889
Short name T393
Test name
Test status
Simulation time 3080929255 ps
CPU time 13.04 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:39 PM PDT 24
Peak memory 217720 kb
Host smart-94963cb2-2a31-4f53-97d3-7b5c1beb660f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608550889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1608550889
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.30241789
Short name T59
Test name
Test status
Simulation time 861245741 ps
CPU time 162.3 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:49:09 PM PDT 24
Peak memory 214416 kb
Host smart-e41a7237-f272-4ecc-812f-fa44a51aa0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30241789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_int
g_err.30241789
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1125172121
Short name T353
Test name
Test status
Simulation time 179409722 ps
CPU time 9.45 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 217760 kb
Host smart-f6172973-7b3a-40f3-8670-1b7365d683a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125172121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1125172121
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2439353455
Short name T332
Test name
Test status
Simulation time 1971072937 ps
CPU time 14.92 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:40 PM PDT 24
Peak memory 210900 kb
Host smart-26b2f5e2-e0a6-4446-a88b-fc62a48a7a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439353455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2439353455
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1401851100
Short name T82
Test name
Test status
Simulation time 10090233703 ps
CPU time 66.1 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:47:34 PM PDT 24
Peak memory 216024 kb
Host smart-8aab5d5f-bb48-4ea9-a7db-b7aab4bcc005
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401851100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1401851100
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2494316386
Short name T95
Test name
Test status
Simulation time 1103267699 ps
CPU time 8.38 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:33 PM PDT 24
Peak memory 211320 kb
Host smart-62f5544f-1a08-45db-b87e-22be27400dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494316386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2494316386
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1750767176
Short name T335
Test name
Test status
Simulation time 279957945 ps
CPU time 14.86 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:46:42 PM PDT 24
Peak memory 217852 kb
Host smart-7d2c3770-f0eb-4663-8705-ff521d4d5d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750767176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1750767176
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.965581814
Short name T109
Test name
Test status
Simulation time 549541623 ps
CPU time 159.84 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:49:05 PM PDT 24
Peak memory 213128 kb
Host smart-048c5cae-b657-4e2b-9a50-7b162e0fcacc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965581814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.965581814
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3185746594
Short name T57
Test name
Test status
Simulation time 1003764565 ps
CPU time 10.16 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 213584 kb
Host smart-9c951c61-f67c-4c66-ad7b-e992e84c2905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185746594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3185746594
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3288825086
Short name T360
Test name
Test status
Simulation time 1892564406 ps
CPU time 9.85 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:46:36 PM PDT 24
Peak memory 210960 kb
Host smart-8984c3aa-4272-443b-ba5d-c18532d271c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288825086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3288825086
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2214872542
Short name T66
Test name
Test status
Simulation time 27029035604 ps
CPU time 97.31 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:48:01 PM PDT 24
Peak memory 215372 kb
Host smart-30486347-2237-41c4-b0f6-acf757dc1f6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214872542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2214872542
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.127061297
Short name T96
Test name
Test status
Simulation time 663613529 ps
CPU time 8.31 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 210308 kb
Host smart-3ab0b01c-f62a-4b72-9f50-e751fdce4c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127061297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.127061297
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1907655605
Short name T61
Test name
Test status
Simulation time 1769812186 ps
CPU time 13.08 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:46:40 PM PDT 24
Peak memory 217724 kb
Host smart-5de8393a-efe8-48a4-840f-1d1c5d811822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907655605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1907655605
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1096514531
Short name T398
Test name
Test status
Simulation time 428866922 ps
CPU time 87.47 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:47:55 PM PDT 24
Peak memory 214096 kb
Host smart-22d1462e-2a5e-4036-b09e-80897ef773ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096514531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1096514531
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1749262826
Short name T368
Test name
Test status
Simulation time 369955896 ps
CPU time 9.93 seconds
Started Aug 13 04:46:32 PM PDT 24
Finished Aug 13 04:46:42 PM PDT 24
Peak memory 219076 kb
Host smart-8bb50a7b-8fb0-42a3-977e-20c425e40d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749262826 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1749262826
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1160578608
Short name T72
Test name
Test status
Simulation time 508383523 ps
CPU time 10 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:46:38 PM PDT 24
Peak memory 210964 kb
Host smart-5a5d1ce2-7a39-4e85-b775-191a1e88728d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160578608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1160578608
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4106624131
Short name T90
Test name
Test status
Simulation time 4216406644 ps
CPU time 44.77 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:47:12 PM PDT 24
Peak memory 215188 kb
Host smart-49c800d7-9092-4a0a-bdd4-be82c1c66f0c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106624131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4106624131
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2687648801
Short name T397
Test name
Test status
Simulation time 340658604 ps
CPU time 8.13 seconds
Started Aug 13 04:46:29 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 211492 kb
Host smart-0cb2556a-1fd2-46d3-a825-e09baca6d544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687648801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2687648801
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3858041245
Short name T407
Test name
Test status
Simulation time 1912597213 ps
CPU time 12.94 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:38 PM PDT 24
Peak memory 216380 kb
Host smart-4b4325e2-d082-401b-84cb-1bfed3903881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858041245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3858041245
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3835108140
Short name T389
Test name
Test status
Simulation time 1060712868 ps
CPU time 11.83 seconds
Started Aug 13 04:46:18 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 218048 kb
Host smart-bfee7792-379c-4889-ab06-ebc63ea17f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835108140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3835108140
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.148522229
Short name T321
Test name
Test status
Simulation time 346263027 ps
CPU time 8.24 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 211292 kb
Host smart-1df585be-ec84-446b-9ee7-604db41871b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148522229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.148522229
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1397443792
Short name T99
Test name
Test status
Simulation time 178745660 ps
CPU time 12.16 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 212900 kb
Host smart-16419f33-f289-4326-966b-a9d84c82fcee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397443792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1397443792
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1554938253
Short name T341
Test name
Test status
Simulation time 257605816 ps
CPU time 15.08 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:46:39 PM PDT 24
Peak memory 216872 kb
Host smart-90049c04-59f4-4839-96d5-ed2cf1129c25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554938253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1554938253
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3130842804
Short name T111
Test name
Test status
Simulation time 1130127646 ps
CPU time 159.4 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:49:06 PM PDT 24
Peak memory 215364 kb
Host smart-c0ea67d5-8e67-479c-8114-df788371df4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130842804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3130842804
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2403762732
Short name T334
Test name
Test status
Simulation time 269608157 ps
CPU time 10.8 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 217240 kb
Host smart-49fcf032-e99b-4b9c-89aa-f8ef1ac2608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403762732 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2403762732
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4214657329
Short name T329
Test name
Test status
Simulation time 260000334 ps
CPU time 9.84 seconds
Started Aug 13 04:46:18 PM PDT 24
Finished Aug 13 04:46:28 PM PDT 24
Peak memory 210960 kb
Host smart-175b8e38-6501-4cab-9fda-f82ffcd5aed0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214657329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4214657329
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3196116242
Short name T400
Test name
Test status
Simulation time 1052316262 ps
CPU time 56.52 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:47:19 PM PDT 24
Peak memory 215380 kb
Host smart-9c64062e-60d1-4ba1-8905-89eddd849a26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196116242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3196116242
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.346241237
Short name T381
Test name
Test status
Simulation time 397098139 ps
CPU time 8.32 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 211316 kb
Host smart-1951455f-16b6-4c5b-a591-2f56445d3991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346241237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.346241237
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2972019806
Short name T348
Test name
Test status
Simulation time 571260457 ps
CPU time 13.2 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:36 PM PDT 24
Peak memory 217860 kb
Host smart-2e9c3f3d-05e6-4aa7-8661-a7e9052fa128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972019806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2972019806
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.248037123
Short name T110
Test name
Test status
Simulation time 1167745628 ps
CPU time 155.84 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:48:57 PM PDT 24
Peak memory 213456 kb
Host smart-4490171b-6042-44c5-8b06-fd25da0bbe55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248037123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.248037123
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3851263411
Short name T344
Test name
Test status
Simulation time 185662801 ps
CPU time 9.33 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 217616 kb
Host smart-0d8d4ba1-488d-49cc-a740-f44a5800d3a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851263411 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3851263411
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3346095621
Short name T408
Test name
Test status
Simulation time 589987203 ps
CPU time 8 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 211064 kb
Host smart-0f98d92f-41df-49bc-9a0d-5cced150075a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346095621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3346095621
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4009641407
Short name T84
Test name
Test status
Simulation time 1056818806 ps
CPU time 43.41 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:47:03 PM PDT 24
Peak memory 214048 kb
Host smart-fd855d32-9917-441d-8a65-818a83873ea3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009641407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4009641407
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3529710220
Short name T352
Test name
Test status
Simulation time 661564968 ps
CPU time 8.25 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:46:28 PM PDT 24
Peak memory 211220 kb
Host smart-6a3c070f-bcd2-4314-95b9-8dcf1f9967f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529710220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3529710220
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2115587945
Short name T342
Test name
Test status
Simulation time 2141356287 ps
CPU time 19.54 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:46:40 PM PDT 24
Peak memory 218748 kb
Host smart-fa5e3bc7-e8ab-4e0f-ab82-fd909d6faf09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115587945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2115587945
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3489691502
Short name T349
Test name
Test status
Simulation time 4720627081 ps
CPU time 81.53 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:47:42 PM PDT 24
Peak memory 215144 kb
Host smart-ef395ac5-460d-482e-bdc7-4c28391058e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489691502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3489691502
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1841255087
Short name T387
Test name
Test status
Simulation time 1057128452 ps
CPU time 10.76 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:33 PM PDT 24
Peak memory 216700 kb
Host smart-f05ec787-7c6e-4213-b835-781070aac43a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841255087 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1841255087
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.395454385
Short name T336
Test name
Test status
Simulation time 172570142 ps
CPU time 8.32 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:33 PM PDT 24
Peak memory 211384 kb
Host smart-99702c0a-afcd-4893-9c2d-5e75ee72c5e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395454385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.395454385
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.131326870
Short name T103
Test name
Test status
Simulation time 6342542652 ps
CPU time 44.09 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:47:04 PM PDT 24
Peak memory 215216 kb
Host smart-500aef97-e457-4dda-b401-c2790c58f1dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131326870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.131326870
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.382244239
Short name T375
Test name
Test status
Simulation time 254551180 ps
CPU time 9.88 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 211548 kb
Host smart-064a2867-9f3c-4adc-9240-c2bcb7d9f330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382244239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.382244239
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4105697504
Short name T23
Test name
Test status
Simulation time 594929910 ps
CPU time 84.02 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:47:48 PM PDT 24
Peak memory 212928 kb
Host smart-5783b9f1-5aab-46c7-963d-56da173b0ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105697504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4105697504
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1116110341
Short name T365
Test name
Test status
Simulation time 1015802225 ps
CPU time 10.68 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:46:39 PM PDT 24
Peak memory 217140 kb
Host smart-baa77a45-46c0-4142-8f46-9b013833ba01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116110341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1116110341
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3423438407
Short name T361
Test name
Test status
Simulation time 174782037 ps
CPU time 8.15 seconds
Started Aug 13 04:46:32 PM PDT 24
Finished Aug 13 04:46:40 PM PDT 24
Peak memory 211056 kb
Host smart-80799033-6e72-43e9-ab95-cb4bb0f993a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423438407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3423438407
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2907107804
Short name T88
Test name
Test status
Simulation time 2099780699 ps
CPU time 56.08 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:47:19 PM PDT 24
Peak memory 215148 kb
Host smart-162740a0-5cfe-45f6-a156-986f7c08dfe0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907107804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2907107804
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1807853261
Short name T406
Test name
Test status
Simulation time 206050060 ps
CPU time 8.24 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 211352 kb
Host smart-cc46df47-90d9-49b4-bd77-cb62444e2a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807853261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1807853261
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3715951754
Short name T350
Test name
Test status
Simulation time 346167374 ps
CPU time 11.65 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 217700 kb
Host smart-5fb2fcd1-0048-4a09-9a04-4d85adb69186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715951754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3715951754
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1718357886
Short name T409
Test name
Test status
Simulation time 371127813 ps
CPU time 84.97 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:47:49 PM PDT 24
Peak memory 215072 kb
Host smart-8265d641-cae0-46b6-9821-c925828599bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718357886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1718357886
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.322052782
Short name T386
Test name
Test status
Simulation time 933020410 ps
CPU time 9.39 seconds
Started Aug 13 04:46:31 PM PDT 24
Finished Aug 13 04:46:40 PM PDT 24
Peak memory 217488 kb
Host smart-a15f8c76-aa0c-42cf-af6e-76bf05785845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322052782 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.322052782
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1340789388
Short name T83
Test name
Test status
Simulation time 663324235 ps
CPU time 8.21 seconds
Started Aug 13 04:46:33 PM PDT 24
Finished Aug 13 04:46:41 PM PDT 24
Peak memory 211352 kb
Host smart-5e86d955-1bb3-45e8-b8a2-d3efa3002846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340789388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1340789388
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1957661423
Short name T347
Test name
Test status
Simulation time 6339955170 ps
CPU time 65.84 seconds
Started Aug 13 04:46:33 PM PDT 24
Finished Aug 13 04:47:39 PM PDT 24
Peak memory 215204 kb
Host smart-b7a30287-b83c-40bf-b246-910805b9357c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957661423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1957661423
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3144425085
Short name T67
Test name
Test status
Simulation time 508404645 ps
CPU time 9.77 seconds
Started Aug 13 04:46:32 PM PDT 24
Finished Aug 13 04:46:42 PM PDT 24
Peak memory 211716 kb
Host smart-b6686ee2-f648-4eab-b209-ddd63475e8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144425085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3144425085
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2849741586
Short name T45
Test name
Test status
Simulation time 345452136 ps
CPU time 12.59 seconds
Started Aug 13 04:46:33 PM PDT 24
Finished Aug 13 04:46:46 PM PDT 24
Peak memory 217624 kb
Host smart-4dbc60d2-2545-4bba-a609-12d0378b82d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849741586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2849741586
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1422078823
Short name T42
Test name
Test status
Simulation time 421802824 ps
CPU time 86 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:47:51 PM PDT 24
Peak memory 214916 kb
Host smart-f4bbe67d-aeff-41f0-ade8-94d028b8c46c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422078823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1422078823
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1663379599
Short name T330
Test name
Test status
Simulation time 719246019 ps
CPU time 8.55 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210984 kb
Host smart-81d023c1-3d3e-4faf-b5c2-8a616bcbb842
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663379599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1663379599
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3038831662
Short name T385
Test name
Test status
Simulation time 253295928 ps
CPU time 10.27 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:46:22 PM PDT 24
Peak memory 210948 kb
Host smart-e2ef72e4-e149-4043-be75-7c2aec4dd98f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038831662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3038831662
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1643831419
Short name T401
Test name
Test status
Simulation time 258492382 ps
CPU time 17.28 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:46:29 PM PDT 24
Peak memory 212484 kb
Host smart-9f43e474-b022-43e9-aceb-ea635bc8bfa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643831419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1643831419
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.29777257
Short name T345
Test name
Test status
Simulation time 197720799 ps
CPU time 9.65 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 217120 kb
Host smart-864af668-ad95-495d-86ae-9d75bf7b6bc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29777257 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.29777257
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2546259733
Short name T380
Test name
Test status
Simulation time 250007607 ps
CPU time 9.83 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 211112 kb
Host smart-08b06485-0539-42d6-8305-8140104601f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546259733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2546259733
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3101331252
Short name T378
Test name
Test status
Simulation time 1028461465 ps
CPU time 9.77 seconds
Started Aug 13 04:46:08 PM PDT 24
Finished Aug 13 04:46:18 PM PDT 24
Peak memory 210764 kb
Host smart-195d1d40-574d-4e13-8391-2552772edc26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101331252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3101331252
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4162266396
Short name T322
Test name
Test status
Simulation time 444192833 ps
CPU time 9.86 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210840 kb
Host smart-380cfd00-8394-44c7-a0b7-20ca2d6d8078
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162266396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4162266396
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.128949932
Short name T70
Test name
Test status
Simulation time 1078302972 ps
CPU time 58.02 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:47:10 PM PDT 24
Peak memory 215312 kb
Host smart-f2023a95-12cb-40f6-ab39-e705d8c0a710
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128949932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.128949932
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3862492828
Short name T379
Test name
Test status
Simulation time 250201127 ps
CPU time 9.79 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 211528 kb
Host smart-5deb1e65-3e16-4003-baac-429ad3cae098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862492828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3862492828
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.192439319
Short name T377
Test name
Test status
Simulation time 1033177632 ps
CPU time 13.42 seconds
Started Aug 13 04:46:09 PM PDT 24
Finished Aug 13 04:46:23 PM PDT 24
Peak memory 217708 kb
Host smart-7f987fda-4511-4b45-b81e-45871b23efd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192439319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.192439319
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.835051819
Short name T394
Test name
Test status
Simulation time 416152305 ps
CPU time 8.4 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 210904 kb
Host smart-2c880283-7ced-41b4-97da-77b7c704725d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835051819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.835051819
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1269498728
Short name T319
Test name
Test status
Simulation time 174235162 ps
CPU time 8.22 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210972 kb
Host smart-b49ee7ac-40cd-4669-8f2b-3db44ec64139
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269498728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1269498728
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1971740398
Short name T325
Test name
Test status
Simulation time 265906861 ps
CPU time 17.54 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 210948 kb
Host smart-479524d1-eda0-4b5a-85f0-1bdb0b48dba1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971740398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1971740398
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1534327020
Short name T376
Test name
Test status
Simulation time 265320047 ps
CPU time 11.64 seconds
Started Aug 13 04:46:12 PM PDT 24
Finished Aug 13 04:46:24 PM PDT 24
Peak memory 218128 kb
Host smart-c90229b9-a458-4abb-938d-a6895f9425af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534327020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1534327020
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4142258947
Short name T87
Test name
Test status
Simulation time 4913815304 ps
CPU time 9.78 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:20 PM PDT 24
Peak memory 211352 kb
Host smart-bcf8cacf-e042-4216-b6af-ba6c29ccbc99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142258947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4142258947
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3703104202
Short name T337
Test name
Test status
Simulation time 173456032 ps
CPU time 8.22 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210756 kb
Host smart-72de1044-2b45-4fb9-a2d4-0a65c2763abd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703104202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3703104202
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1503756609
Short name T323
Test name
Test status
Simulation time 1031185415 ps
CPU time 9.67 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:21 PM PDT 24
Peak memory 210804 kb
Host smart-1e962337-226b-4fb7-bd0c-0706145e754a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503756609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1503756609
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4180753681
Short name T73
Test name
Test status
Simulation time 1032416596 ps
CPU time 56.6 seconds
Started Aug 13 04:46:08 PM PDT 24
Finished Aug 13 04:47:05 PM PDT 24
Peak memory 214112 kb
Host smart-c3d110b7-1821-4913-9ebd-9d5d190a7586
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180753681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4180753681
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1167224636
Short name T367
Test name
Test status
Simulation time 279221580 ps
CPU time 13.69 seconds
Started Aug 13 04:46:11 PM PDT 24
Finished Aug 13 04:46:24 PM PDT 24
Peak memory 212592 kb
Host smart-e4f46b36-3f67-43f5-a522-a7ae129cd2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167224636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1167224636
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3272208008
Short name T369
Test name
Test status
Simulation time 1035697349 ps
CPU time 13.34 seconds
Started Aug 13 04:46:10 PM PDT 24
Finished Aug 13 04:46:23 PM PDT 24
Peak memory 217460 kb
Host smart-0a3ab01d-5fa5-4532-8074-289e8cf3fab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272208008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3272208008
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3682632075
Short name T106
Test name
Test status
Simulation time 1559930147 ps
CPU time 156.76 seconds
Started Aug 13 04:46:14 PM PDT 24
Finished Aug 13 04:48:51 PM PDT 24
Peak memory 214572 kb
Host smart-dff920b2-7b90-4412-bc9d-621c1285e9e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682632075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3682632075
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2415101404
Short name T68
Test name
Test status
Simulation time 459960655 ps
CPU time 8.26 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 210836 kb
Host smart-79c30c71-68ef-4dd3-b706-06f1ca6d2dd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415101404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2415101404
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1855255430
Short name T326
Test name
Test status
Simulation time 249418401 ps
CPU time 10.23 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:32 PM PDT 24
Peak memory 211156 kb
Host smart-285fbbcb-3f37-4a46-ac3b-c260999fdb6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855255430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1855255430
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4045954010
Short name T374
Test name
Test status
Simulation time 699519900 ps
CPU time 11.82 seconds
Started Aug 13 04:46:18 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 211036 kb
Host smart-514f9c32-26f9-4c3f-97ff-581a2aa9009f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045954010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4045954010
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1473088241
Short name T396
Test name
Test status
Simulation time 358418214 ps
CPU time 8.85 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 216408 kb
Host smart-61c59b71-bc28-4210-b9b7-0f5acc465515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473088241 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1473088241
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.609409926
Short name T48
Test name
Test status
Simulation time 661067826 ps
CPU time 8.19 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:29 PM PDT 24
Peak memory 211136 kb
Host smart-b8db79fc-f25c-4b4f-86ad-7df1562a8e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609409926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.609409926
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2312766113
Short name T357
Test name
Test status
Simulation time 3093244842 ps
CPU time 10.05 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 210804 kb
Host smart-0230b078-b861-4b8d-940f-8c8c01356c96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312766113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2312766113
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1198181197
Short name T331
Test name
Test status
Simulation time 167321613 ps
CPU time 8.33 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 210824 kb
Host smart-cef1a95e-a8ca-4dfe-a0b3-1aa31825842b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198181197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1198181197
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1664409293
Short name T390
Test name
Test status
Simulation time 11913962144 ps
CPU time 96.21 seconds
Started Aug 13 04:46:13 PM PDT 24
Finished Aug 13 04:47:49 PM PDT 24
Peak memory 216440 kb
Host smart-f0fbd4b1-0433-4f9a-a3b4-01e53f983738
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664409293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1664409293
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2363155892
Short name T97
Test name
Test status
Simulation time 1546338646 ps
CPU time 10.36 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:46:29 PM PDT 24
Peak memory 211512 kb
Host smart-2461051b-cda2-4217-ad18-c43e1e13da0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363155892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2363155892
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1301562633
Short name T395
Test name
Test status
Simulation time 1032773999 ps
CPU time 11.56 seconds
Started Aug 13 04:46:14 PM PDT 24
Finished Aug 13 04:46:25 PM PDT 24
Peak memory 217648 kb
Host smart-59982494-9e2f-47af-ac79-a10ae9e09aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301562633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1301562633
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3354413167
Short name T373
Test name
Test status
Simulation time 1291014755 ps
CPU time 82.84 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:47:49 PM PDT 24
Peak memory 214032 kb
Host smart-5a9baf14-fe2d-445d-9c0b-48810655c2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354413167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3354413167
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1499066770
Short name T58
Test name
Test status
Simulation time 1068594689 ps
CPU time 10.95 seconds
Started Aug 13 04:46:18 PM PDT 24
Finished Aug 13 04:46:29 PM PDT 24
Peak memory 217948 kb
Host smart-ca10e3ba-f82d-40de-850e-b3889851fa7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499066770 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1499066770
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3358340213
Short name T338
Test name
Test status
Simulation time 3523210248 ps
CPU time 9.88 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 211084 kb
Host smart-4ba494ac-63f5-4513-a420-578f10120b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358340213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3358340213
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1727132537
Short name T372
Test name
Test status
Simulation time 9247442125 ps
CPU time 44.72 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:47:04 PM PDT 24
Peak memory 214104 kb
Host smart-f80622c7-b701-407a-8772-4607b7f3eb96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727132537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1727132537
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.552586900
Short name T382
Test name
Test status
Simulation time 519268504 ps
CPU time 9.87 seconds
Started Aug 13 04:46:24 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 211100 kb
Host smart-25bb921e-1439-4fa2-b1f8-fd2ecfc18e98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552586900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.552586900
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2998677478
Short name T366
Test name
Test status
Simulation time 249850650 ps
CPU time 13.47 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:46:36 PM PDT 24
Peak memory 218808 kb
Host smart-4834a040-df33-4828-a501-b77c2dc28f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998677478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2998677478
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1139974964
Short name T364
Test name
Test status
Simulation time 1066088578 ps
CPU time 10.42 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:46:30 PM PDT 24
Peak memory 215820 kb
Host smart-547eb9da-a8ab-487b-90f9-96b78d7e72e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139974964 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1139974964
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4176565981
Short name T85
Test name
Test status
Simulation time 250466343 ps
CPU time 9.82 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:46:29 PM PDT 24
Peak memory 211104 kb
Host smart-096d3329-3970-4322-bf17-bfec586ffea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176565981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4176565981
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.859853280
Short name T404
Test name
Test status
Simulation time 2028284239 ps
CPU time 37.37 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:46:58 PM PDT 24
Peak memory 214108 kb
Host smart-7a83f310-c592-4227-8bdf-ad1f97ccf980
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859853280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.859853280
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4079841595
Short name T100
Test name
Test status
Simulation time 167945529 ps
CPU time 8.38 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 211604 kb
Host smart-35ef164d-aaac-49e9-b0ce-b88ad7955edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079841595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4079841595
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.638607570
Short name T24
Test name
Test status
Simulation time 346057786 ps
CPU time 15.2 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 217588 kb
Host smart-473c345d-5637-43c6-abb1-e0976f79ac5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638607570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.638607570
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3916510876
Short name T392
Test name
Test status
Simulation time 410996493 ps
CPU time 11.75 seconds
Started Aug 13 04:46:19 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 217700 kb
Host smart-bf5f0a42-089a-4e40-b5bc-8f5c05653311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916510876 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3916510876
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2507585262
Short name T343
Test name
Test status
Simulation time 368958819 ps
CPU time 8.32 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:46:32 PM PDT 24
Peak memory 211160 kb
Host smart-af3a205b-d032-4474-ac59-3eddfa9b8c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507585262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2507585262
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2378433591
Short name T405
Test name
Test status
Simulation time 3534866231 ps
CPU time 66.72 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:47:27 PM PDT 24
Peak memory 215772 kb
Host smart-ca6efed5-0a0f-4ec1-a0db-feeade6af80c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378433591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2378433591
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1669111296
Short name T355
Test name
Test status
Simulation time 1031590878 ps
CPU time 8.17 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 211396 kb
Host smart-581ca6a0-76e6-430e-8ca0-3a66da3bb61e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669111296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1669111296
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2509658168
Short name T328
Test name
Test status
Simulation time 206223401 ps
CPU time 12.88 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 218876 kb
Host smart-9cb0cbbb-bf62-45fb-a88a-dc6ae02ec91b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509658168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2509658168
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3904690350
Short name T107
Test name
Test status
Simulation time 1098479495 ps
CPU time 161.47 seconds
Started Aug 13 04:46:17 PM PDT 24
Finished Aug 13 04:48:59 PM PDT 24
Peak memory 214324 kb
Host smart-4b319b80-c5bd-4ac1-bd11-1d417a382f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904690350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3904690350
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2036699331
Short name T39
Test name
Test status
Simulation time 1042203594 ps
CPU time 11.15 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:32 PM PDT 24
Peak memory 217848 kb
Host smart-43f49755-c9fc-4f98-882e-5c18bf909807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036699331 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2036699331
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.87121412
Short name T320
Test name
Test status
Simulation time 263435366 ps
CPU time 9.92 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:31 PM PDT 24
Peak memory 211276 kb
Host smart-eac55100-e935-48af-88be-9b76099851f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87121412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.87121412
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2318064921
Short name T89
Test name
Test status
Simulation time 1640396090 ps
CPU time 37.44 seconds
Started Aug 13 04:46:23 PM PDT 24
Finished Aug 13 04:47:01 PM PDT 24
Peak memory 214040 kb
Host smart-addbcf1e-e4b3-4214-86d0-e83a4f41c957
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318064921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2318064921
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.988135936
Short name T384
Test name
Test status
Simulation time 496231699 ps
CPU time 13.93 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:46:36 PM PDT 24
Peak memory 212832 kb
Host smart-e31c8bdd-08db-4063-a38c-d37cb02e8752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988135936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.988135936
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2847935852
Short name T333
Test name
Test status
Simulation time 518202369 ps
CPU time 13.17 seconds
Started Aug 13 04:46:21 PM PDT 24
Finished Aug 13 04:46:34 PM PDT 24
Peak memory 217736 kb
Host smart-4d60fc47-6c0c-4c60-b0b0-10e61a90fb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847935852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2847935852
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1253675516
Short name T388
Test name
Test status
Simulation time 1413527287 ps
CPU time 156.13 seconds
Started Aug 13 04:46:20 PM PDT 24
Finished Aug 13 04:48:56 PM PDT 24
Peak memory 214476 kb
Host smart-36b7498b-373d-4abb-ac8b-6491ca5518d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253675516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1253675516
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1053947451
Short name T346
Test name
Test status
Simulation time 270570565 ps
CPU time 10.55 seconds
Started Aug 13 04:46:27 PM PDT 24
Finished Aug 13 04:46:38 PM PDT 24
Peak memory 217452 kb
Host smart-2d9a0e5f-bdeb-4d69-9171-fd9d26c85126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053947451 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1053947451
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2216388220
Short name T383
Test name
Test status
Simulation time 1033932648 ps
CPU time 9.84 seconds
Started Aug 13 04:46:25 PM PDT 24
Finished Aug 13 04:46:35 PM PDT 24
Peak memory 210892 kb
Host smart-709f03b4-774b-45ff-ab55-a98a389128b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216388220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2216388220
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3997859333
Short name T402
Test name
Test status
Simulation time 443384607 ps
CPU time 9.59 seconds
Started Aug 13 04:46:28 PM PDT 24
Finished Aug 13 04:46:38 PM PDT 24
Peak memory 211572 kb
Host smart-12ff0ce7-4e81-45a7-bc2b-96eea20e1c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997859333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3997859333
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.275221121
Short name T362
Test name
Test status
Simulation time 167509565 ps
CPU time 11.74 seconds
Started Aug 13 04:46:26 PM PDT 24
Finished Aug 13 04:46:37 PM PDT 24
Peak memory 217468 kb
Host smart-dd73e793-f1b6-4763-b0ad-6a19749beb97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275221121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.275221121
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3238439629
Short name T60
Test name
Test status
Simulation time 908573440 ps
CPU time 82.14 seconds
Started Aug 13 04:46:22 PM PDT 24
Finished Aug 13 04:47:44 PM PDT 24
Peak memory 214044 kb
Host smart-6f6d94d2-6a94-4552-b8f1-5e95a45dd8bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238439629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3238439629
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2691115805
Short name T277
Test name
Test status
Simulation time 168069977 ps
CPU time 8.25 seconds
Started Aug 13 05:11:52 PM PDT 24
Finished Aug 13 05:12:00 PM PDT 24
Peak memory 218380 kb
Host smart-ead1ffee-922a-4bab-8392-fdce45c890b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691115805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2691115805
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3673336736
Short name T137
Test name
Test status
Simulation time 12198461783 ps
CPU time 306.25 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:17:04 PM PDT 24
Peak memory 240296 kb
Host smart-3916a60d-3240-4820-bcd2-d0839193d115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673336736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3673336736
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3068171730
Short name T243
Test name
Test status
Simulation time 518953281 ps
CPU time 22.55 seconds
Started Aug 13 05:11:54 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 219356 kb
Host smart-0f3e117c-a063-4c38-9bfc-8fc5779a89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068171730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3068171730
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3613455886
Short name T94
Test name
Test status
Simulation time 531809595 ps
CPU time 12.42 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:08 PM PDT 24
Peak memory 219316 kb
Host smart-4eb16ece-b087-4364-af9b-60636c7e4045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613455886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3613455886
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4188693041
Short name T2
Test name
Test status
Simulation time 375043908 ps
CPU time 121.03 seconds
Started Aug 13 05:11:53 PM PDT 24
Finished Aug 13 05:13:55 PM PDT 24
Peak memory 239164 kb
Host smart-c59a8980-66ff-46ca-8865-549d7026d37a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188693041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4188693041
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3192729936
Short name T242
Test name
Test status
Simulation time 5164552303 ps
CPU time 12.64 seconds
Started Aug 13 05:11:50 PM PDT 24
Finished Aug 13 05:12:02 PM PDT 24
Peak memory 219368 kb
Host smart-1333407f-b160-4127-92bf-dcc1123eb6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192729936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3192729936
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3119184227
Short name T46
Test name
Test status
Simulation time 5226408792 ps
CPU time 38.75 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:36 PM PDT 24
Peak memory 219496 kb
Host smart-db9518dd-d2fa-4db1-9fe8-77075223fc0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119184227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3119184227
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.634432650
Short name T32
Test name
Test status
Simulation time 5476337899 ps
CPU time 241.52 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:15:58 PM PDT 24
Peak memory 241932 kb
Host smart-9ee052e7-d61e-4eef-8794-00395ffa8fd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634432650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.634432650
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.534209486
Short name T222
Test name
Test status
Simulation time 478789818 ps
CPU time 12.5 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:08 PM PDT 24
Peak memory 219184 kb
Host smart-525b52b2-ccd6-4de0-b82a-5437774ba52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534209486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.534209486
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3805946734
Short name T28
Test name
Test status
Simulation time 241423497 ps
CPU time 117.58 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:13:53 PM PDT 24
Peak memory 235576 kb
Host smart-a01cf386-47f8-4e26-9bea-557219252527
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805946734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3805946734
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1863561558
Short name T10
Test name
Test status
Simulation time 757262995 ps
CPU time 10.53 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:07 PM PDT 24
Peak memory 219368 kb
Host smart-baf8d3a9-43b2-4121-b3e8-8b4b4e57c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863561558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1863561558
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.586010475
Short name T118
Test name
Test status
Simulation time 819815171 ps
CPU time 21.47 seconds
Started Aug 13 05:11:52 PM PDT 24
Finished Aug 13 05:12:13 PM PDT 24
Peak memory 219236 kb
Host smart-16c8ed2a-fae1-4f67-9f21-4639be6e3457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586010475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.586010475
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3140689422
Short name T224
Test name
Test status
Simulation time 3291791745 ps
CPU time 8.69 seconds
Started Aug 13 05:12:07 PM PDT 24
Finished Aug 13 05:12:16 PM PDT 24
Peak memory 218416 kb
Host smart-30085f74-e6d9-4505-ac82-895b9b90a765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140689422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3140689422
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3599000611
Short name T157
Test name
Test status
Simulation time 8789481978 ps
CPU time 176.28 seconds
Started Aug 13 05:12:02 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 244820 kb
Host smart-d9a9bc9b-6551-4300-96b9-6d23329cbdbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599000611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3599000611
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1764456587
Short name T220
Test name
Test status
Simulation time 8574013969 ps
CPU time 31.42 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:34 PM PDT 24
Peak memory 218936 kb
Host smart-0697c997-ec63-4212-9b14-be0051d36406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764456587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1764456587
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3014872508
Short name T263
Test name
Test status
Simulation time 267212030 ps
CPU time 11.9 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:16 PM PDT 24
Peak memory 219220 kb
Host smart-92cb0e2e-44a6-4e90-9294-7339d03c884c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014872508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3014872508
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2346250071
Short name T134
Test name
Test status
Simulation time 1088962070 ps
CPU time 27.57 seconds
Started Aug 13 05:12:11 PM PDT 24
Finished Aug 13 05:12:39 PM PDT 24
Peak memory 219260 kb
Host smart-d421e1b0-150a-41b7-a32f-ca5744367ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346250071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2346250071
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.569568320
Short name T181
Test name
Test status
Simulation time 255954206 ps
CPU time 10.37 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:15 PM PDT 24
Peak memory 218416 kb
Host smart-a025036c-b785-4ac3-8b1c-3b3bfe68dea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569568320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.569568320
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.963115511
Short name T38
Test name
Test status
Simulation time 12512937463 ps
CPU time 197.11 seconds
Started Aug 13 05:12:02 PM PDT 24
Finished Aug 13 05:15:19 PM PDT 24
Peak memory 230896 kb
Host smart-be306273-c753-4953-8328-e61ad9446e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963115511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.963115511
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.421015362
Short name T271
Test name
Test status
Simulation time 527595736 ps
CPU time 19.5 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:22 PM PDT 24
Peak memory 219380 kb
Host smart-fce8c3ad-83d2-47ae-bb68-8cbb103e3e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421015362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.421015362
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2383163012
Short name T246
Test name
Test status
Simulation time 3128093321 ps
CPU time 56.28 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 219572 kb
Host smart-6574906e-612b-4c0b-a0c7-c734e9e0c137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383163012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2383163012
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3279497739
Short name T251
Test name
Test status
Simulation time 176320392 ps
CPU time 8.26 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:12 PM PDT 24
Peak memory 218496 kb
Host smart-043fcdb2-45f6-47a4-8334-e1cfb52bba4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279497739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3279497739
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3614688303
Short name T41
Test name
Test status
Simulation time 4341360714 ps
CPU time 119.79 seconds
Started Aug 13 05:12:01 PM PDT 24
Finished Aug 13 05:14:01 PM PDT 24
Peak memory 229136 kb
Host smart-d7455e90-39ee-4922-9ff9-9e27d57a06f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614688303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3614688303
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2736746964
Short name T210
Test name
Test status
Simulation time 502914578 ps
CPU time 22.47 seconds
Started Aug 13 05:12:13 PM PDT 24
Finished Aug 13 05:12:35 PM PDT 24
Peak memory 219284 kb
Host smart-b1b665e2-b56d-4f98-94a3-8f20f0ed3e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736746964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2736746964
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3532835642
Short name T285
Test name
Test status
Simulation time 265458545 ps
CPU time 12.43 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:15 PM PDT 24
Peak memory 219272 kb
Host smart-925b56fc-2630-43df-800c-904d87b32bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532835642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3532835642
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.79728839
Short name T281
Test name
Test status
Simulation time 1097913324 ps
CPU time 32.65 seconds
Started Aug 13 05:12:06 PM PDT 24
Finished Aug 13 05:12:39 PM PDT 24
Peak memory 219376 kb
Host smart-a393fa37-2d2c-43ae-a457-a8431a52e798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79728839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.rom_ctrl_stress_all.79728839
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1578971735
Short name T136
Test name
Test status
Simulation time 167691072 ps
CPU time 8.32 seconds
Started Aug 13 05:12:09 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 218344 kb
Host smart-37ebca9e-edf5-4dcf-9b80-a5b61567e5c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578971735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1578971735
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3946427702
Short name T317
Test name
Test status
Simulation time 28247025264 ps
CPU time 152.29 seconds
Started Aug 13 05:12:15 PM PDT 24
Finished Aug 13 05:14:48 PM PDT 24
Peak memory 219272 kb
Host smart-419db24f-2aca-438a-b79d-9d1f5ad1e739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946427702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3946427702
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.220286275
Short name T172
Test name
Test status
Simulation time 1342452647 ps
CPU time 22.94 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:33 PM PDT 24
Peak memory 219420 kb
Host smart-dc101ee9-945e-4bbe-a7a7-d716054969f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220286275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.220286275
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1175434977
Short name T19
Test name
Test status
Simulation time 536616757 ps
CPU time 12.29 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:16 PM PDT 24
Peak memory 219332 kb
Host smart-563a07e1-58e6-4309-8e26-55ca5e4bc436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175434977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1175434977
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.867806282
Short name T291
Test name
Test status
Simulation time 364095039 ps
CPU time 23.75 seconds
Started Aug 13 05:12:05 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219228 kb
Host smart-cf758418-4686-4eae-909e-1a3c553e9815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867806282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.867806282
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2861237290
Short name T154
Test name
Test status
Simulation time 260304779 ps
CPU time 10.16 seconds
Started Aug 13 05:12:11 PM PDT 24
Finished Aug 13 05:12:22 PM PDT 24
Peak memory 218464 kb
Host smart-0be6c924-163f-4326-92b5-018c62ba29b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861237290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2861237290
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.229180110
Short name T17
Test name
Test status
Simulation time 3380305979 ps
CPU time 217.67 seconds
Started Aug 13 05:12:12 PM PDT 24
Finished Aug 13 05:15:50 PM PDT 24
Peak memory 225080 kb
Host smart-ef5672a2-f887-494b-8499-5e6ddfd5edc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229180110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.229180110
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4256313081
Short name T187
Test name
Test status
Simulation time 1980055272 ps
CPU time 22.8 seconds
Started Aug 13 05:12:12 PM PDT 24
Finished Aug 13 05:12:35 PM PDT 24
Peak memory 219324 kb
Host smart-73647aee-839c-4e6b-82cb-77293547e79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256313081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4256313081
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1539726783
Short name T301
Test name
Test status
Simulation time 550834567 ps
CPU time 35.56 seconds
Started Aug 13 05:12:09 PM PDT 24
Finished Aug 13 05:12:45 PM PDT 24
Peak memory 219372 kb
Host smart-08f051f0-1ba8-44f7-8c7e-33186473a7ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539726783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1539726783
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.555991775
Short name T50
Test name
Test status
Simulation time 404419474 ps
CPU time 8.4 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:18 PM PDT 24
Peak memory 218312 kb
Host smart-bc53d03c-3152-4af6-889d-019dff38dae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555991775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.555991775
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2348306789
Short name T141
Test name
Test status
Simulation time 8087647462 ps
CPU time 437.04 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:19:27 PM PDT 24
Peak memory 236484 kb
Host smart-16c7e6d7-ac63-4264-b4d7-65f94ce89498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348306789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2348306789
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2557249633
Short name T177
Test name
Test status
Simulation time 1330474003 ps
CPU time 19.27 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219396 kb
Host smart-ca41196c-0c0d-4d8a-974d-5630f9976352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557249633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2557249633
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1707195215
Short name T142
Test name
Test status
Simulation time 2060188585 ps
CPU time 48.59 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 219504 kb
Host smart-b1f7048b-1100-441b-a2bb-fb82c58024ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707195215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1707195215
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.776643006
Short name T311
Test name
Test status
Simulation time 338392667 ps
CPU time 8.56 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:19 PM PDT 24
Peak memory 218412 kb
Host smart-f532fcc9-2e31-45f6-9afa-594c9c0e6c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776643006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.776643006
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2642155509
Short name T194
Test name
Test status
Simulation time 4557161154 ps
CPU time 136.27 seconds
Started Aug 13 05:12:08 PM PDT 24
Finished Aug 13 05:14:25 PM PDT 24
Peak memory 237888 kb
Host smart-de06f142-16fb-4944-9a18-e80705932252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642155509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2642155509
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1613660933
Short name T15
Test name
Test status
Simulation time 1826510048 ps
CPU time 22.72 seconds
Started Aug 13 05:12:09 PM PDT 24
Finished Aug 13 05:12:32 PM PDT 24
Peak memory 219308 kb
Host smart-6be4d05b-d81b-4742-896d-cc6d8b952c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613660933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1613660933
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.880704718
Short name T193
Test name
Test status
Simulation time 188500554 ps
CPU time 10.68 seconds
Started Aug 13 05:12:10 PM PDT 24
Finished Aug 13 05:12:21 PM PDT 24
Peak memory 219312 kb
Host smart-01ea6420-88b8-45ce-aff5-ff87717bf503
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880704718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.880704718
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3500062131
Short name T221
Test name
Test status
Simulation time 736618090 ps
CPU time 27.74 seconds
Started Aug 13 05:12:12 PM PDT 24
Finished Aug 13 05:12:40 PM PDT 24
Peak memory 219296 kb
Host smart-97340b0c-2b8b-41e6-b555-2a253318fb17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500062131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3500062131
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4158803338
Short name T152
Test name
Test status
Simulation time 255353834 ps
CPU time 10.31 seconds
Started Aug 13 05:12:16 PM PDT 24
Finished Aug 13 05:12:27 PM PDT 24
Peak memory 218396 kb
Host smart-98985986-423f-4334-9bd0-4428e08d187d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158803338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4158803338
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2320303739
Short name T276
Test name
Test status
Simulation time 2046967322 ps
CPU time 110.36 seconds
Started Aug 13 05:12:20 PM PDT 24
Finished Aug 13 05:14:10 PM PDT 24
Peak memory 219432 kb
Host smart-8be71c0e-8756-4911-adb6-8586cefa8908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320303739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2320303739
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.76148436
Short name T190
Test name
Test status
Simulation time 1022670188 ps
CPU time 23.85 seconds
Started Aug 13 05:12:18 PM PDT 24
Finished Aug 13 05:12:42 PM PDT 24
Peak memory 220776 kb
Host smart-227e52f4-9ae1-4b52-a719-4dfbaee6587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76148436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.76148436
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2413637306
Short name T192
Test name
Test status
Simulation time 827535694 ps
CPU time 10.47 seconds
Started Aug 13 05:12:12 PM PDT 24
Finished Aug 13 05:12:23 PM PDT 24
Peak memory 219332 kb
Host smart-7584d299-6a42-4116-883a-103cb1c203cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413637306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2413637306
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2446167727
Short name T147
Test name
Test status
Simulation time 218273496 ps
CPU time 18.51 seconds
Started Aug 13 05:12:09 PM PDT 24
Finished Aug 13 05:12:28 PM PDT 24
Peak memory 219260 kb
Host smart-153b302c-01d1-4d0d-b9fe-85ccc06f51af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446167727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2446167727
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2565464489
Short name T270
Test name
Test status
Simulation time 174787437 ps
CPU time 8.5 seconds
Started Aug 13 05:12:23 PM PDT 24
Finished Aug 13 05:12:31 PM PDT 24
Peak memory 218428 kb
Host smart-7d4ab0ff-d060-46a1-bbe1-64ff5756cc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565464489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2565464489
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1182307705
Short name T33
Test name
Test status
Simulation time 3870524306 ps
CPU time 271.87 seconds
Started Aug 13 05:12:18 PM PDT 24
Finished Aug 13 05:16:50 PM PDT 24
Peak memory 226300 kb
Host smart-2c71b3ba-0b52-48ff-9f34-a07b2fd24170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182307705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1182307705
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1101157645
Short name T195
Test name
Test status
Simulation time 4134255309 ps
CPU time 19.45 seconds
Started Aug 13 05:12:17 PM PDT 24
Finished Aug 13 05:12:36 PM PDT 24
Peak memory 219356 kb
Host smart-3045ea2b-d2de-48e8-8dc0-2ea11e053720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101157645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1101157645
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.20824014
Short name T116
Test name
Test status
Simulation time 1024796083 ps
CPU time 12 seconds
Started Aug 13 05:12:17 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219240 kb
Host smart-a4687c7a-9aea-49a7-95ac-5c6e0ab4fdbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20824014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.20824014
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1899232189
Short name T149
Test name
Test status
Simulation time 790159992 ps
CPU time 14.86 seconds
Started Aug 13 05:12:18 PM PDT 24
Finished Aug 13 05:12:33 PM PDT 24
Peak memory 219348 kb
Host smart-c8706e9f-9fef-44fe-8ce3-c99962933f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899232189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1899232189
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1437997769
Short name T303
Test name
Test status
Simulation time 518180536 ps
CPU time 10.2 seconds
Started Aug 13 05:12:16 PM PDT 24
Finished Aug 13 05:12:26 PM PDT 24
Peak memory 218340 kb
Host smart-8d84b958-3558-4edd-842c-3616a42b3702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437997769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1437997769
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2436432508
Short name T268
Test name
Test status
Simulation time 2096854548 ps
CPU time 132.13 seconds
Started Aug 13 05:12:19 PM PDT 24
Finished Aug 13 05:14:31 PM PDT 24
Peak memory 234944 kb
Host smart-eca8f0f3-59a7-4ec3-b5ec-a03fa15cc738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436432508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2436432508
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4211787374
Short name T262
Test name
Test status
Simulation time 2054200500 ps
CPU time 22.98 seconds
Started Aug 13 05:12:16 PM PDT 24
Finished Aug 13 05:12:39 PM PDT 24
Peak memory 219380 kb
Host smart-e0c2d2ba-471a-4d9b-8899-0da077fe16c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211787374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4211787374
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4251554762
Short name T257
Test name
Test status
Simulation time 1158184083 ps
CPU time 12.02 seconds
Started Aug 13 05:12:17 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219332 kb
Host smart-551da202-4ce4-48d2-939c-eae5131e77b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251554762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4251554762
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3292223536
Short name T21
Test name
Test status
Simulation time 3088426375 ps
CPU time 10.09 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:07 PM PDT 24
Peak memory 218460 kb
Host smart-460322dd-8729-472f-89a1-f92b608e0c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292223536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3292223536
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3332167010
Short name T145
Test name
Test status
Simulation time 12529497502 ps
CPU time 193.29 seconds
Started Aug 13 05:11:56 PM PDT 24
Finished Aug 13 05:15:09 PM PDT 24
Peak memory 238988 kb
Host smart-6870423f-3534-43b9-915a-ba317c92d8ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332167010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3332167010
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2746780383
Short name T295
Test name
Test status
Simulation time 2904256842 ps
CPU time 22.51 seconds
Started Aug 13 05:11:53 PM PDT 24
Finished Aug 13 05:12:15 PM PDT 24
Peak memory 219376 kb
Host smart-805ef751-192b-494a-9cbf-9cea84602c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746780383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2746780383
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.889191037
Short name T4
Test name
Test status
Simulation time 279648059 ps
CPU time 12.47 seconds
Started Aug 13 05:11:50 PM PDT 24
Finished Aug 13 05:12:02 PM PDT 24
Peak memory 219252 kb
Host smart-4236a2d7-b17a-4544-b459-fc3c7a36f807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889191037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.889191037
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.73813239
Short name T9
Test name
Test status
Simulation time 367842688 ps
CPU time 10.57 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:06 PM PDT 24
Peak memory 219288 kb
Host smart-fdf976c9-f84a-4dbc-8def-fde886bc72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73813239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.73813239
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2503459223
Short name T302
Test name
Test status
Simulation time 991338087 ps
CPU time 10.2 seconds
Started Aug 13 05:12:29 PM PDT 24
Finished Aug 13 05:12:39 PM PDT 24
Peak memory 218480 kb
Host smart-3ae1e782-e2e7-49d1-8946-1c9ad063b4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503459223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2503459223
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2503765584
Short name T5
Test name
Test status
Simulation time 1011322024 ps
CPU time 22.05 seconds
Started Aug 13 05:12:22 PM PDT 24
Finished Aug 13 05:12:44 PM PDT 24
Peak memory 219424 kb
Host smart-ec8286aa-98c9-45a8-9d00-e400733f3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503765584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2503765584
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2492442985
Short name T230
Test name
Test status
Simulation time 311818362 ps
CPU time 10.71 seconds
Started Aug 13 05:12:18 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219216 kb
Host smart-28b97037-02d0-4404-b532-a5a9af4990cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492442985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2492442985
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4181829154
Short name T244
Test name
Test status
Simulation time 841789100 ps
CPU time 25.17 seconds
Started Aug 13 05:12:20 PM PDT 24
Finished Aug 13 05:12:45 PM PDT 24
Peak memory 219136 kb
Host smart-3344aa16-e521-4044-883a-2f0ba7760d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181829154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4181829154
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2097476252
Short name T236
Test name
Test status
Simulation time 332502510 ps
CPU time 8.71 seconds
Started Aug 13 05:12:24 PM PDT 24
Finished Aug 13 05:12:33 PM PDT 24
Peak memory 218400 kb
Host smart-7e45612e-818e-4757-a9f3-aac9356aaa56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097476252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2097476252
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.238748095
Short name T122
Test name
Test status
Simulation time 2744970178 ps
CPU time 148.41 seconds
Started Aug 13 05:12:28 PM PDT 24
Finished Aug 13 05:14:57 PM PDT 24
Peak memory 241412 kb
Host smart-ce314052-e1fd-46da-92c4-5ae4fd0b6601
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238748095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.238748095
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3731038829
Short name T182
Test name
Test status
Simulation time 1906313779 ps
CPU time 23.02 seconds
Started Aug 13 05:12:24 PM PDT 24
Finished Aug 13 05:12:48 PM PDT 24
Peak memory 219424 kb
Host smart-aa532c90-8b6e-4df6-bbab-8b247bc942c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731038829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3731038829
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3687330926
Short name T315
Test name
Test status
Simulation time 516978325 ps
CPU time 12.28 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:12:38 PM PDT 24
Peak memory 219252 kb
Host smart-ad7e680e-23a4-4a84-a40b-645dc9e3bd54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687330926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3687330926
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1458558111
Short name T123
Test name
Test status
Simulation time 1151069067 ps
CPU time 31.81 seconds
Started Aug 13 05:12:29 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 219272 kb
Host smart-534e27cf-651f-474d-8104-9af29dcc22ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458558111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1458558111
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2839604715
Short name T207
Test name
Test status
Simulation time 661100971 ps
CPU time 8.53 seconds
Started Aug 13 05:12:29 PM PDT 24
Finished Aug 13 05:12:37 PM PDT 24
Peak memory 218404 kb
Host smart-b5124fdd-73fa-41c9-9682-873fcd5f2f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839604715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2839604715
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2398198303
Short name T128
Test name
Test status
Simulation time 2164806636 ps
CPU time 176.27 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:15:22 PM PDT 24
Peak memory 235676 kb
Host smart-6451f6a8-2094-4d92-b91d-55333ab0903a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398198303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2398198303
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3792420762
Short name T101
Test name
Test status
Simulation time 4946689451 ps
CPU time 17.08 seconds
Started Aug 13 05:12:26 PM PDT 24
Finished Aug 13 05:12:43 PM PDT 24
Peak memory 219356 kb
Host smart-0250de08-a999-4c4f-ab60-43c0cff8ca95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792420762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3792420762
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1581262113
Short name T308
Test name
Test status
Simulation time 262309793 ps
CPU time 10.45 seconds
Started Aug 13 05:12:24 PM PDT 24
Finished Aug 13 05:12:35 PM PDT 24
Peak memory 218472 kb
Host smart-a50a4ee8-744c-402d-9d59-732587e15eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581262113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1581262113
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3096526332
Short name T237
Test name
Test status
Simulation time 2801987042 ps
CPU time 168.73 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:15:14 PM PDT 24
Peak memory 228560 kb
Host smart-83ce054e-3c1a-4a60-9c91-3c19d0126e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096526332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3096526332
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3939384679
Short name T273
Test name
Test status
Simulation time 1227348178 ps
CPU time 19.4 seconds
Started Aug 13 05:12:30 PM PDT 24
Finished Aug 13 05:12:49 PM PDT 24
Peak memory 219308 kb
Host smart-4f962d58-ad2b-4315-b05e-225a264a1bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939384679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3939384679
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2488165118
Short name T290
Test name
Test status
Simulation time 264013053 ps
CPU time 12.74 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:12:37 PM PDT 24
Peak memory 219332 kb
Host smart-16fc1274-43f8-474e-a787-212b57f08faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488165118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2488165118
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2494049626
Short name T151
Test name
Test status
Simulation time 1100850746 ps
CPU time 28.49 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:12:54 PM PDT 24
Peak memory 219376 kb
Host smart-5b60e036-88bb-428d-a187-13f94e3e48a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494049626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2494049626
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.219303660
Short name T307
Test name
Test status
Simulation time 592995237 ps
CPU time 10.19 seconds
Started Aug 13 05:12:26 PM PDT 24
Finished Aug 13 05:12:36 PM PDT 24
Peak memory 218412 kb
Host smart-99f920d4-f464-4a3e-852b-3bb36ccbe14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219303660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.219303660
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3801096690
Short name T120
Test name
Test status
Simulation time 26685147321 ps
CPU time 325.24 seconds
Started Aug 13 05:12:23 PM PDT 24
Finished Aug 13 05:17:49 PM PDT 24
Peak memory 218172 kb
Host smart-d1e5a620-f20a-469f-834f-df19367fa509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801096690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3801096690
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2374360546
Short name T283
Test name
Test status
Simulation time 1323947447 ps
CPU time 19.57 seconds
Started Aug 13 05:12:30 PM PDT 24
Finished Aug 13 05:12:49 PM PDT 24
Peak memory 219332 kb
Host smart-2daa58aa-4d1f-4946-9927-48cf343efe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374360546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2374360546
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4159966984
Short name T196
Test name
Test status
Simulation time 364638978 ps
CPU time 10.6 seconds
Started Aug 13 05:12:26 PM PDT 24
Finished Aug 13 05:12:37 PM PDT 24
Peak memory 219232 kb
Host smart-9aa5eb5e-b3ad-448e-befe-6b539aa4cf36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159966984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4159966984
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1879076006
Short name T124
Test name
Test status
Simulation time 8505739292 ps
CPU time 46.84 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 220536 kb
Host smart-4b89e17e-6f5f-4f84-b4f4-c691f096eb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879076006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1879076006
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.537316704
Short name T298
Test name
Test status
Simulation time 1033328305 ps
CPU time 10.09 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:12:44 PM PDT 24
Peak memory 218396 kb
Host smart-c2e1aca4-a0d8-43b0-8189-ffeb33786357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537316704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.537316704
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.432811082
Short name T173
Test name
Test status
Simulation time 2181365935 ps
CPU time 102.96 seconds
Started Aug 13 05:12:26 PM PDT 24
Finished Aug 13 05:14:09 PM PDT 24
Peak memory 240848 kb
Host smart-c70f4af8-83be-4b77-ac1a-5d5f75c35523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432811082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.432811082
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2642751805
Short name T226
Test name
Test status
Simulation time 349775821 ps
CPU time 19.32 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:12:56 PM PDT 24
Peak memory 219308 kb
Host smart-b75f57d2-6625-40fa-9c17-78f2ea5c3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642751805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2642751805
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.653515702
Short name T215
Test name
Test status
Simulation time 180859675 ps
CPU time 10.5 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:12:36 PM PDT 24
Peak memory 219316 kb
Host smart-34dc97b4-dff2-442f-a2de-dcf94ed094c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653515702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.653515702
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.357595978
Short name T212
Test name
Test status
Simulation time 2048866910 ps
CPU time 37.28 seconds
Started Aug 13 05:12:25 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 219244 kb
Host smart-629082f7-0d1c-4559-9716-6643bf7448c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357595978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.357595978
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3720542366
Short name T217
Test name
Test status
Simulation time 1032239891 ps
CPU time 10.23 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:12:47 PM PDT 24
Peak memory 218488 kb
Host smart-31a2e630-05f9-4d53-9676-5d5d14113cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720542366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3720542366
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1113701649
Short name T153
Test name
Test status
Simulation time 27086362823 ps
CPU time 381.33 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:18:56 PM PDT 24
Peak memory 239000 kb
Host smart-6faf5441-3f10-4640-b518-c56e989a8038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113701649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1113701649
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3245210093
Short name T211
Test name
Test status
Simulation time 1832422201 ps
CPU time 19.45 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:12:53 PM PDT 24
Peak memory 219400 kb
Host smart-798fc285-87e5-4d63-a156-1bbba54177f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245210093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3245210093
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2605498025
Short name T231
Test name
Test status
Simulation time 2551059029 ps
CPU time 12.01 seconds
Started Aug 13 05:12:39 PM PDT 24
Finished Aug 13 05:12:51 PM PDT 24
Peak memory 219368 kb
Host smart-d706fcc1-7280-4cf2-a2b9-4c05eb8c107e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605498025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2605498025
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1130056812
Short name T144
Test name
Test status
Simulation time 767430906 ps
CPU time 23.96 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 219308 kb
Host smart-84bf1656-4a70-4e7e-89bc-40ba5ba8a8ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130056812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1130056812
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1169466894
Short name T155
Test name
Test status
Simulation time 394519694 ps
CPU time 8.31 seconds
Started Aug 13 05:12:38 PM PDT 24
Finished Aug 13 05:12:46 PM PDT 24
Peak memory 218464 kb
Host smart-fe7a482a-1b4e-43a4-a53a-6561a5c7c151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169466894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1169466894
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2985272473
Short name T130
Test name
Test status
Simulation time 2714702188 ps
CPU time 193.8 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:15:50 PM PDT 24
Peak memory 224928 kb
Host smart-1ac31641-acc1-4b74-a984-b6682a44b136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985272473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2985272473
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.431370150
Short name T234
Test name
Test status
Simulation time 1321585800 ps
CPU time 19.16 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:12:55 PM PDT 24
Peak memory 219372 kb
Host smart-bc386167-0857-4d71-93e7-04ca221b01ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431370150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.431370150
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3437834902
Short name T278
Test name
Test status
Simulation time 1125702838 ps
CPU time 12.7 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:12:47 PM PDT 24
Peak memory 219268 kb
Host smart-6dadf210-4777-4fbd-bb10-23c3e4e68b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437834902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3437834902
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.850878652
Short name T22
Test name
Test status
Simulation time 1123055827 ps
CPU time 9.99 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:12:44 PM PDT 24
Peak memory 218432 kb
Host smart-f5a836b4-313c-4a17-af02-58bc7740e00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850878652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.850878652
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2683249029
Short name T168
Test name
Test status
Simulation time 7944000081 ps
CPU time 146.01 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:15:02 PM PDT 24
Peak memory 229900 kb
Host smart-550e8c09-f20b-401d-bf00-283f9e76b610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683249029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2683249029
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1594435382
Short name T36
Test name
Test status
Simulation time 826602947 ps
CPU time 19.23 seconds
Started Aug 13 05:12:37 PM PDT 24
Finished Aug 13 05:12:56 PM PDT 24
Peak memory 219320 kb
Host smart-0613b0e6-9586-4a35-9ec4-2d0cdb64d6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594435382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1594435382
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3027060167
Short name T255
Test name
Test status
Simulation time 264139306 ps
CPU time 12.36 seconds
Started Aug 13 05:12:37 PM PDT 24
Finished Aug 13 05:12:50 PM PDT 24
Peak memory 219308 kb
Host smart-529c3fd1-dbcd-4051-9df5-d1cb61479e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027060167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3027060167
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3198754976
Short name T309
Test name
Test status
Simulation time 1089826576 ps
CPU time 35.39 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:13:10 PM PDT 24
Peak memory 219288 kb
Host smart-11042a1b-78a5-4168-b423-a65fe72766a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198754976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3198754976
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3028851833
Short name T198
Test name
Test status
Simulation time 692232584 ps
CPU time 8.18 seconds
Started Aug 13 05:12:38 PM PDT 24
Finished Aug 13 05:12:46 PM PDT 24
Peak memory 218420 kb
Host smart-548a2146-7662-4c86-bc4a-6860d82693f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028851833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3028851833
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1770723281
Short name T199
Test name
Test status
Simulation time 2147916909 ps
CPU time 23.67 seconds
Started Aug 13 05:12:33 PM PDT 24
Finished Aug 13 05:12:57 PM PDT 24
Peak memory 219340 kb
Host smart-fdda1267-01cc-4d2a-b90c-c234571f31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770723281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1770723281
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2375579608
Short name T253
Test name
Test status
Simulation time 685292545 ps
CPU time 10.52 seconds
Started Aug 13 05:12:38 PM PDT 24
Finished Aug 13 05:12:49 PM PDT 24
Peak memory 219336 kb
Host smart-4ab5274c-64e8-4550-8951-4a9f04845436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375579608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2375579608
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3880752527
Short name T117
Test name
Test status
Simulation time 1711952321 ps
CPU time 37.8 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 219236 kb
Host smart-ad3f23ff-c8d5-4cab-acaa-fbeade0d528d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880752527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3880752527
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3263872464
Short name T259
Test name
Test status
Simulation time 787819860 ps
CPU time 8.56 seconds
Started Aug 13 05:11:59 PM PDT 24
Finished Aug 13 05:12:07 PM PDT 24
Peak memory 218448 kb
Host smart-250e2bfc-163c-4ddf-bf0b-366c151ee13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263872464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3263872464
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2333825515
Short name T284
Test name
Test status
Simulation time 5087528959 ps
CPU time 248.43 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:16:05 PM PDT 24
Peak memory 219016 kb
Host smart-fa220afe-2e49-46ad-9c59-251ead9788f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333825515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2333825515
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2166562320
Short name T214
Test name
Test status
Simulation time 1322730491 ps
CPU time 19.12 seconds
Started Aug 13 05:11:52 PM PDT 24
Finished Aug 13 05:12:11 PM PDT 24
Peak memory 219304 kb
Host smart-601ff237-933b-4913-8d8b-9c25c05ac754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166562320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2166562320
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.306441063
Short name T114
Test name
Test status
Simulation time 1021544849 ps
CPU time 17.16 seconds
Started Aug 13 05:11:52 PM PDT 24
Finished Aug 13 05:12:10 PM PDT 24
Peak memory 219292 kb
Host smart-21ca5e3e-4629-4c5d-8025-fbbaff7d2ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306441063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.306441063
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.572517062
Short name T14
Test name
Test status
Simulation time 790299065 ps
CPU time 231.25 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:15:49 PM PDT 24
Peak memory 238436 kb
Host smart-16a70a3a-e19c-44cd-8ce3-ede6a23e1a4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572517062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.572517062
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1740305909
Short name T304
Test name
Test status
Simulation time 186671865 ps
CPU time 10.63 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:07 PM PDT 24
Peak memory 219368 kb
Host smart-f7cc3164-ae11-45f3-b70c-5c5dabc9786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740305909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1740305909
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2589853738
Short name T133
Test name
Test status
Simulation time 1041814307 ps
CPU time 27.47 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:12:25 PM PDT 24
Peak memory 219380 kb
Host smart-19980d79-af82-4cf2-a72f-3dd2577535e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589853738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2589853738
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4102926060
Short name T216
Test name
Test status
Simulation time 3086515688 ps
CPU time 10.3 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:12:47 PM PDT 24
Peak memory 218416 kb
Host smart-74f66155-c8ae-4a7c-94f5-6c2ec2b97bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102926060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4102926060
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3418130709
Short name T266
Test name
Test status
Simulation time 15860889717 ps
CPU time 225.78 seconds
Started Aug 13 05:12:37 PM PDT 24
Finished Aug 13 05:16:23 PM PDT 24
Peak memory 219632 kb
Host smart-ffbcb4bd-5bf4-49e6-a38a-2a6346a48000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418130709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3418130709
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2842735907
Short name T265
Test name
Test status
Simulation time 1374671904 ps
CPU time 19.38 seconds
Started Aug 13 05:12:40 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 219400 kb
Host smart-1212d008-13d0-48d1-ad39-ac66594ffbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842735907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2842735907
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.473168399
Short name T205
Test name
Test status
Simulation time 179278249 ps
CPU time 10.32 seconds
Started Aug 13 05:12:34 PM PDT 24
Finished Aug 13 05:12:45 PM PDT 24
Peak memory 219360 kb
Host smart-f5efe702-98ff-4de9-9b0d-ee5c8309a0db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473168399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.473168399
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2557203749
Short name T167
Test name
Test status
Simulation time 1377155604 ps
CPU time 27.41 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219328 kb
Host smart-e61a9fe6-8d9b-4e6b-b64b-3ae72c2b0f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557203749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2557203749
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.861947454
Short name T1
Test name
Test status
Simulation time 260636196 ps
CPU time 10.31 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:12:46 PM PDT 24
Peak memory 218404 kb
Host smart-aee2c3bb-c94f-457d-b985-270b73f38605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861947454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.861947454
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1956614316
Short name T135
Test name
Test status
Simulation time 13700600643 ps
CPU time 358.02 seconds
Started Aug 13 05:12:33 PM PDT 24
Finished Aug 13 05:18:31 PM PDT 24
Peak memory 225840 kb
Host smart-e7b6185f-feb6-46d8-b0ff-6786a9d7c7f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956614316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1956614316
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.910036127
Short name T164
Test name
Test status
Simulation time 530963381 ps
CPU time 22.88 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:12:58 PM PDT 24
Peak memory 219280 kb
Host smart-c40b3909-7aca-49bc-b599-59681ded131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910036127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.910036127
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.30246855
Short name T206
Test name
Test status
Simulation time 526732496 ps
CPU time 12.47 seconds
Started Aug 13 05:12:38 PM PDT 24
Finished Aug 13 05:12:50 PM PDT 24
Peak memory 219320 kb
Host smart-89109b26-88c3-400b-8ee3-7ccb17791d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30246855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.30246855
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3588142760
Short name T202
Test name
Test status
Simulation time 1042978072 ps
CPU time 31.58 seconds
Started Aug 13 05:12:36 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 219192 kb
Host smart-86f6795f-6151-40e2-bc69-c6c55222416f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588142760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3588142760
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4276853997
Short name T235
Test name
Test status
Simulation time 258033388 ps
CPU time 10.12 seconds
Started Aug 13 05:12:44 PM PDT 24
Finished Aug 13 05:12:55 PM PDT 24
Peak memory 218484 kb
Host smart-92cc26f8-b9e8-4d7e-a4f2-23b173c4af7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276853997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4276853997
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3979100531
Short name T174
Test name
Test status
Simulation time 6445170364 ps
CPU time 126.61 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:14:47 PM PDT 24
Peak memory 238924 kb
Host smart-8058f8ab-8aa7-4de9-9784-a897e4c5faed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979100531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3979100531
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.764946107
Short name T267
Test name
Test status
Simulation time 1028678465 ps
CPU time 22.76 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219372 kb
Host smart-dbec6ca4-1929-43a9-bbe4-2219038192ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764946107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.764946107
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2721426102
Short name T288
Test name
Test status
Simulation time 523555076 ps
CPU time 12.05 seconds
Started Aug 13 05:12:35 PM PDT 24
Finished Aug 13 05:12:48 PM PDT 24
Peak memory 219320 kb
Host smart-368c40a7-b226-413d-b0a0-e5e5abedbaa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721426102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2721426102
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.901035672
Short name T300
Test name
Test status
Simulation time 803217095 ps
CPU time 10.23 seconds
Started Aug 13 05:12:42 PM PDT 24
Finished Aug 13 05:12:52 PM PDT 24
Peak memory 218408 kb
Host smart-3ff31b2e-c11c-456d-8098-70783f59c27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901035672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.901035672
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1857131183
Short name T31
Test name
Test status
Simulation time 10784112172 ps
CPU time 325.88 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:18:15 PM PDT 24
Peak memory 234176 kb
Host smart-22ced13e-5c9a-4556-8a94-ae5415f288e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857131183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1857131183
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3304970666
Short name T218
Test name
Test status
Simulation time 2247868607 ps
CPU time 23.28 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219448 kb
Host smart-3583ab48-e764-4411-8a3c-303507354f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304970666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3304970666
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2243643925
Short name T250
Test name
Test status
Simulation time 269343315 ps
CPU time 11.82 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:12:53 PM PDT 24
Peak memory 219332 kb
Host smart-2622ec93-5e0c-4deb-9b89-32bf95479f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243643925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2243643925
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.582166884
Short name T169
Test name
Test status
Simulation time 1051572918 ps
CPU time 56.32 seconds
Started Aug 13 05:12:43 PM PDT 24
Finished Aug 13 05:13:39 PM PDT 24
Peak memory 219272 kb
Host smart-776c7730-9cbc-4f7b-abc9-8230544da9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582166884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.582166884
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.748637357
Short name T249
Test name
Test status
Simulation time 660853706 ps
CPU time 8.36 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:12:58 PM PDT 24
Peak memory 218104 kb
Host smart-166990af-7c00-494d-ab42-2e5c1029a16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748637357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.748637357
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.870839628
Short name T129
Test name
Test status
Simulation time 1720028924 ps
CPU time 132.24 seconds
Started Aug 13 05:12:46 PM PDT 24
Finished Aug 13 05:14:58 PM PDT 24
Peak memory 238956 kb
Host smart-059c8eb8-445b-45a0-8ea0-fdcf6994e333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870839628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.870839628
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4205200754
Short name T241
Test name
Test status
Simulation time 497703195 ps
CPU time 22.78 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219372 kb
Host smart-def257e4-ef5d-4092-9429-c0b647bf4abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205200754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4205200754
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4168095580
Short name T119
Test name
Test status
Simulation time 351707197 ps
CPU time 10.11 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:12:51 PM PDT 24
Peak memory 219276 kb
Host smart-25bf15e5-2668-4751-b581-8e3c660c4202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168095580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4168095580
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3128942812
Short name T12
Test name
Test status
Simulation time 742309292 ps
CPU time 20.52 seconds
Started Aug 13 05:12:44 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219316 kb
Host smart-3aa6890a-898b-4d86-8cf0-bf00a10cab43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128942812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3128942812
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.943866388
Short name T293
Test name
Test status
Simulation time 174369030 ps
CPU time 8.65 seconds
Started Aug 13 05:12:42 PM PDT 24
Finished Aug 13 05:12:51 PM PDT 24
Peak memory 218296 kb
Host smart-af8e56d5-38ca-41ec-bce9-e55a3fb5e3ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943866388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.943866388
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2622158372
Short name T146
Test name
Test status
Simulation time 4255525985 ps
CPU time 271.03 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:17:16 PM PDT 24
Peak memory 228608 kb
Host smart-06f7d411-1807-48d5-9a53-87713187cf9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622158372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2622158372
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2196407102
Short name T166
Test name
Test status
Simulation time 5485767930 ps
CPU time 22.76 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 219516 kb
Host smart-e7ca3e47-2298-4ee3-9070-bacd87dd3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196407102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2196407102
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2178046143
Short name T183
Test name
Test status
Simulation time 335964384 ps
CPU time 12.15 seconds
Started Aug 13 05:12:40 PM PDT 24
Finished Aug 13 05:12:52 PM PDT 24
Peak memory 219304 kb
Host smart-a6bc10e0-12f7-4405-bc8c-cdc46afa27a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178046143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2178046143
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1617181763
Short name T47
Test name
Test status
Simulation time 299529383 ps
CPU time 19.9 seconds
Started Aug 13 05:12:43 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 219300 kb
Host smart-803b39be-6f98-4f9a-8fbe-2b3b1fdddfe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617181763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1617181763
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3245288520
Short name T233
Test name
Test status
Simulation time 9226103634 ps
CPU time 225.17 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:16:31 PM PDT 24
Peak memory 219612 kb
Host smart-90076861-97b5-4efb-949d-e6233c68ea48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245288520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3245288520
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3524210696
Short name T178
Test name
Test status
Simulation time 874450951 ps
CPU time 19.46 seconds
Started Aug 13 05:12:44 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 219420 kb
Host smart-194d78e1-7dc9-4413-bbc1-0e70c85cc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524210696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3524210696
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2009125990
Short name T269
Test name
Test status
Simulation time 530190183 ps
CPU time 12.19 seconds
Started Aug 13 05:12:42 PM PDT 24
Finished Aug 13 05:12:54 PM PDT 24
Peak memory 219272 kb
Host smart-3e1faf01-4ca5-499f-8267-0b0ce020639c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009125990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2009125990
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.591311509
Short name T131
Test name
Test status
Simulation time 375267963 ps
CPU time 27.6 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:18 PM PDT 24
Peak memory 219360 kb
Host smart-d39e2dd4-e061-4e71-aafd-33ff88eb0dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591311509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.591311509
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.548620781
Short name T175
Test name
Test status
Simulation time 1373859813 ps
CPU time 8.45 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:12:53 PM PDT 24
Peak memory 218360 kb
Host smart-76e1ba83-bed9-4389-acd0-51a291d63513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548620781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.548620781
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4022556142
Short name T229
Test name
Test status
Simulation time 4253757060 ps
CPU time 12.37 seconds
Started Aug 13 05:12:47 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 219392 kb
Host smart-51538645-43c5-4619-94f2-577c00d0bae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022556142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4022556142
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.655882255
Short name T306
Test name
Test status
Simulation time 925000310 ps
CPU time 11.9 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 219268 kb
Host smart-e40db041-2cbe-447f-8853-299a3298fa90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655882255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.655882255
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.670685517
Short name T132
Test name
Test status
Simulation time 168440913 ps
CPU time 8.31 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:12:54 PM PDT 24
Peak memory 219252 kb
Host smart-45fbc5ea-6af6-47d0-93a2-aa22e84cb0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670685517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.670685517
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1836550831
Short name T37
Test name
Test status
Simulation time 16886941991 ps
CPU time 349.46 seconds
Started Aug 13 05:12:41 PM PDT 24
Finished Aug 13 05:18:31 PM PDT 24
Peak memory 242432 kb
Host smart-d4f6fc34-b214-4fd2-8257-8bad9501ef13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836550831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1836550831
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3496255438
Short name T239
Test name
Test status
Simulation time 511580116 ps
CPU time 22.77 seconds
Started Aug 13 05:12:43 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 219372 kb
Host smart-48a3b466-0740-4a0a-868a-eda1b3bfd9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496255438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3496255438
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4158618817
Short name T179
Test name
Test status
Simulation time 568428932 ps
CPU time 10.65 seconds
Started Aug 13 05:12:45 PM PDT 24
Finished Aug 13 05:12:56 PM PDT 24
Peak memory 219316 kb
Host smart-a72494dc-527d-4545-aaff-77224cc56b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158618817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4158618817
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3061537415
Short name T225
Test name
Test status
Simulation time 2078806195 ps
CPU time 20.64 seconds
Started Aug 13 05:12:42 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 219224 kb
Host smart-1bf1f0a7-b8a6-4148-be1a-e6843f627b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061537415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3061537415
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3463376123
Short name T53
Test name
Test status
Simulation time 996402398 ps
CPU time 10.13 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 218488 kb
Host smart-8d51fb3e-10e2-4bf4-b01b-164915b1c895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463376123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3463376123
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3395835896
Short name T292
Test name
Test status
Simulation time 37558258535 ps
CPU time 313.47 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:18:02 PM PDT 24
Peak memory 234264 kb
Host smart-d44a4a8e-9d89-40ec-b59b-e5370b8dc872
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395835896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3395835896
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.983483623
Short name T296
Test name
Test status
Simulation time 3533792281 ps
CPU time 22.92 seconds
Started Aug 13 05:12:51 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 219480 kb
Host smart-5ccc2aad-f47c-4438-9a86-a06ffc3309d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983483623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.983483623
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2633794987
Short name T185
Test name
Test status
Simulation time 266046878 ps
CPU time 12.38 seconds
Started Aug 13 05:12:43 PM PDT 24
Finished Aug 13 05:12:55 PM PDT 24
Peak memory 219316 kb
Host smart-2d0e3075-0e83-4309-b814-126dedaa09e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633794987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2633794987
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1550640855
Short name T76
Test name
Test status
Simulation time 3148321303 ps
CPU time 56.9 seconds
Started Aug 13 05:12:44 PM PDT 24
Finished Aug 13 05:13:41 PM PDT 24
Peak memory 219392 kb
Host smart-bbf772a8-39d6-4993-85b6-005ec5ee201f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550640855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1550640855
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3806611504
Short name T148
Test name
Test status
Simulation time 249281049 ps
CPU time 10.27 seconds
Started Aug 13 05:11:59 PM PDT 24
Finished Aug 13 05:12:09 PM PDT 24
Peak memory 218416 kb
Host smart-7092052a-cf97-475e-b756-58ea8d9df24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806611504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3806611504
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.172372952
Short name T180
Test name
Test status
Simulation time 7637295769 ps
CPU time 238.9 seconds
Started Aug 13 05:11:56 PM PDT 24
Finished Aug 13 05:15:55 PM PDT 24
Peak memory 225720 kb
Host smart-d0334d3f-1f37-47af-875e-7d31b8d1f5bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172372952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.172372952
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2751147520
Short name T289
Test name
Test status
Simulation time 345926269 ps
CPU time 19.44 seconds
Started Aug 13 05:11:56 PM PDT 24
Finished Aug 13 05:12:16 PM PDT 24
Peak memory 219400 kb
Host smart-ee328cc1-bc80-48f6-8b9b-93d4afe14ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751147520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2751147520
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3525948061
Short name T3
Test name
Test status
Simulation time 200876281 ps
CPU time 10.79 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:12:09 PM PDT 24
Peak memory 219264 kb
Host smart-89262f90-e751-440f-a6a8-c60ad396a18f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525948061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3525948061
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.975540681
Short name T27
Test name
Test status
Simulation time 572292524 ps
CPU time 231.67 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:15:56 PM PDT 24
Peak memory 233672 kb
Host smart-5c23821b-22ab-4819-bca8-251bbf7e38f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975540681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.975540681
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3391623962
Short name T160
Test name
Test status
Simulation time 185626832 ps
CPU time 10.46 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:12:08 PM PDT 24
Peak memory 219360 kb
Host smart-00613a18-b8f0-4058-b46a-91f88d1a28ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391623962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3391623962
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.280471522
Short name T77
Test name
Test status
Simulation time 545732536 ps
CPU time 34.96 seconds
Started Aug 13 05:11:56 PM PDT 24
Finished Aug 13 05:12:31 PM PDT 24
Peak memory 219200 kb
Host smart-6904e9c2-6a8b-4d7e-be93-591b86f2c343
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280471522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.280471522
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1034748896
Short name T252
Test name
Test status
Simulation time 1015939130 ps
CPU time 15.43 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 218372 kb
Host smart-3d435a01-ab5f-49ff-be6e-b447d0e36029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034748896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1034748896
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1070469513
Short name T282
Test name
Test status
Simulation time 5668165171 ps
CPU time 228.45 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:16:36 PM PDT 24
Peak memory 225888 kb
Host smart-ada79e5c-247c-4aee-861f-ec5684c752ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070469513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1070469513
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2088766959
Short name T186
Test name
Test status
Simulation time 1373992577 ps
CPU time 19.92 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:13:08 PM PDT 24
Peak memory 219400 kb
Host smart-f6d15739-c248-44de-b817-4c16deb47647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088766959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2088766959
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2958031302
Short name T286
Test name
Test status
Simulation time 1023782134 ps
CPU time 12.29 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 219248 kb
Host smart-56128eae-cdc1-4de4-81e5-c647a904965c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958031302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2958031302
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.290701941
Short name T254
Test name
Test status
Simulation time 2092045671 ps
CPU time 31.91 seconds
Started Aug 13 05:12:51 PM PDT 24
Finished Aug 13 05:13:23 PM PDT 24
Peak memory 219332 kb
Host smart-997b4f55-2eb5-40b3-b06b-2f2d1da536f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290701941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.290701941
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.754384192
Short name T52
Test name
Test status
Simulation time 180375064 ps
CPU time 8.39 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:12:58 PM PDT 24
Peak memory 218368 kb
Host smart-28733786-349c-49b9-91c1-01eb89799feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754384192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.754384192
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.677796121
Short name T92
Test name
Test status
Simulation time 2360909914 ps
CPU time 23.39 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 219476 kb
Host smart-9a65ce53-d2e3-4cd3-b0e1-099a62027e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677796121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.677796121
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.339328538
Short name T275
Test name
Test status
Simulation time 1074227688 ps
CPU time 12.26 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 219276 kb
Host smart-a7cb9538-23ab-4594-9f66-36df2c8095d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339328538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.339328538
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1926945722
Short name T219
Test name
Test status
Simulation time 587666785 ps
CPU time 13.28 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:03 PM PDT 24
Peak memory 219260 kb
Host smart-2dc5d0a8-9a65-4d87-b9c6-b64487565f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926945722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1926945722
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4070907357
Short name T258
Test name
Test status
Simulation time 987611223 ps
CPU time 10.18 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 218460 kb
Host smart-a8f763f0-8d2f-4bc6-bafc-8b7659193083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070907357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4070907357
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2778232715
Short name T150
Test name
Test status
Simulation time 1926080756 ps
CPU time 110.42 seconds
Started Aug 13 05:12:47 PM PDT 24
Finished Aug 13 05:14:38 PM PDT 24
Peak memory 236140 kb
Host smart-e1bf1018-08d4-403f-a2df-b995b9d0d537
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778232715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2778232715
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2551134403
Short name T159
Test name
Test status
Simulation time 1323177592 ps
CPU time 19.41 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:09 PM PDT 24
Peak memory 219368 kb
Host smart-9fa54015-fafa-4914-b4ec-4fd744bcb146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551134403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2551134403
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2077776
Short name T115
Test name
Test status
Simulation time 695844656 ps
CPU time 12.34 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 219312 kb
Host smart-97c27010-e272-474d-88d7-8e75303df335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2077776
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2459881733
Short name T163
Test name
Test status
Simulation time 403637852 ps
CPU time 24.82 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 219268 kb
Host smart-39454e7e-06a5-432d-829e-1552da287a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459881733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2459881733
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3564175316
Short name T125
Test name
Test status
Simulation time 718273714 ps
CPU time 8.44 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:12:56 PM PDT 24
Peak memory 218408 kb
Host smart-92732ca9-766c-48b9-8add-aa235680e52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564175316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3564175316
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2071163245
Short name T18
Test name
Test status
Simulation time 17427579902 ps
CPU time 173.38 seconds
Started Aug 13 05:12:53 PM PDT 24
Finished Aug 13 05:15:46 PM PDT 24
Peak memory 235016 kb
Host smart-b568e33d-ea2b-4870-8068-2306648a4d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071163245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2071163245
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1073974808
Short name T13
Test name
Test status
Simulation time 6185728367 ps
CPU time 22.87 seconds
Started Aug 13 05:12:51 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 219484 kb
Host smart-44d579c1-7617-4004-8759-efef2cd47f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073974808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1073974808
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1172591081
Short name T102
Test name
Test status
Simulation time 180630729 ps
CPU time 10.85 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:01 PM PDT 24
Peak memory 219360 kb
Host smart-49f27511-79bc-4a11-b9dc-33aa16ea6e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172591081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1172591081
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1618282768
Short name T138
Test name
Test status
Simulation time 2241640514 ps
CPU time 37.9 seconds
Started Aug 13 05:12:48 PM PDT 24
Finished Aug 13 05:13:26 PM PDT 24
Peak memory 219364 kb
Host smart-bc18c9bc-5f58-4419-b421-6b68b319ba37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618282768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1618282768
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1317393298
Short name T140
Test name
Test status
Simulation time 690960926 ps
CPU time 8.3 seconds
Started Aug 13 05:12:51 PM PDT 24
Finished Aug 13 05:12:59 PM PDT 24
Peak memory 218328 kb
Host smart-30d7b8e5-9f8f-41f5-a5e7-c6c10855ab0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317393298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1317393298
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3155283787
Short name T171
Test name
Test status
Simulation time 9895855683 ps
CPU time 197.68 seconds
Started Aug 13 05:12:51 PM PDT 24
Finished Aug 13 05:16:09 PM PDT 24
Peak memory 225816 kb
Host smart-245ff6c4-c4f6-4132-90eb-b327fc60764c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155283787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3155283787
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3905548724
Short name T200
Test name
Test status
Simulation time 1991403207 ps
CPU time 23.18 seconds
Started Aug 13 05:12:50 PM PDT 24
Finished Aug 13 05:13:13 PM PDT 24
Peak memory 219364 kb
Host smart-5c35b83b-6ae8-4ca1-8657-87441d3f3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905548724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3905548724
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3309671467
Short name T260
Test name
Test status
Simulation time 178074913 ps
CPU time 10.58 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:00 PM PDT 24
Peak memory 219308 kb
Host smart-ba86a89b-11c1-4304-954d-abd2224f7a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309671467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3309671467
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1592922123
Short name T197
Test name
Test status
Simulation time 695541058 ps
CPU time 17.97 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 219224 kb
Host smart-9e646c7e-cc25-44e0-a954-50c5e13eab3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592922123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1592922123
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.931915080
Short name T213
Test name
Test status
Simulation time 688307454 ps
CPU time 8.4 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:13:05 PM PDT 24
Peak memory 218364 kb
Host smart-863ef0d0-4761-4664-8915-704b29ccddf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931915080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.931915080
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.419639356
Short name T121
Test name
Test status
Simulation time 3103827997 ps
CPU time 255.39 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:17:12 PM PDT 24
Peak memory 237828 kb
Host smart-6363d7b6-a0c7-41d7-a7a6-6108d03fd3d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419639356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.419639356
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2223566496
Short name T34
Test name
Test status
Simulation time 1319734122 ps
CPU time 19.68 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:13:15 PM PDT 24
Peak memory 219328 kb
Host smart-358b1ab6-e1da-4cd3-9831-c1b94f44c63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223566496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2223566496
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1624763168
Short name T203
Test name
Test status
Simulation time 798707070 ps
CPU time 10.57 seconds
Started Aug 13 05:12:52 PM PDT 24
Finished Aug 13 05:13:02 PM PDT 24
Peak memory 219328 kb
Host smart-a6b222e8-02bc-4e18-a596-430b08651380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624763168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1624763168
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2341283548
Short name T227
Test name
Test status
Simulation time 2054696748 ps
CPU time 14.48 seconds
Started Aug 13 05:12:49 PM PDT 24
Finished Aug 13 05:13:04 PM PDT 24
Peak memory 219308 kb
Host smart-03d36e7e-bb7b-49ad-abdf-6217f1ddc743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341283548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2341283548
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2043968624
Short name T55
Test name
Test status
Simulation time 1965671898 ps
CPU time 14.92 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:14 PM PDT 24
Peak memory 218332 kb
Host smart-b3701b03-41fa-4cb6-a485-821960d0733b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043968624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2043968624
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.717327386
Short name T256
Test name
Test status
Simulation time 6749453658 ps
CPU time 359.53 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:19:00 PM PDT 24
Peak memory 239624 kb
Host smart-907347a3-1048-4113-b1d6-611849350543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717327386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.717327386
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.566087939
Short name T139
Test name
Test status
Simulation time 497238932 ps
CPU time 22.49 seconds
Started Aug 13 05:13:04 PM PDT 24
Finished Aug 13 05:13:26 PM PDT 24
Peak memory 218556 kb
Host smart-4c3bc430-f339-4910-835f-8b7e9a92fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566087939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.566087939
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2403968054
Short name T313
Test name
Test status
Simulation time 353374796 ps
CPU time 10.87 seconds
Started Aug 13 05:13:01 PM PDT 24
Finished Aug 13 05:13:12 PM PDT 24
Peak memory 219368 kb
Host smart-86999d7d-a54c-461f-9a03-bf36403ffeac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403968054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2403968054
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3378939789
Short name T156
Test name
Test status
Simulation time 671323231 ps
CPU time 24.23 seconds
Started Aug 13 05:12:59 PM PDT 24
Finished Aug 13 05:13:23 PM PDT 24
Peak memory 219220 kb
Host smart-f65914d5-7cc8-445b-b619-c57c0c33524a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378939789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3378939789
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.424489132
Short name T318
Test name
Test status
Simulation time 496726974 ps
CPU time 10.17 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 218440 kb
Host smart-550e35da-25b8-4fc9-97f6-11fec7387c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424489132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.424489132
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1515997704
Short name T161
Test name
Test status
Simulation time 12983488891 ps
CPU time 258.91 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:17:21 PM PDT 24
Peak memory 217944 kb
Host smart-9917da7c-b1bc-46ac-b0ca-74e3619fdf8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515997704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1515997704
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3533878874
Short name T299
Test name
Test status
Simulation time 1389608056 ps
CPU time 19.6 seconds
Started Aug 13 05:12:56 PM PDT 24
Finished Aug 13 05:13:16 PM PDT 24
Peak memory 219392 kb
Host smart-419a0a90-9364-46f4-bbb8-e011a79c38eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533878874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3533878874
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4252244769
Short name T232
Test name
Test status
Simulation time 219034752 ps
CPU time 10.69 seconds
Started Aug 13 05:12:55 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 219300 kb
Host smart-05150a34-7fd8-47ec-a807-8996a46f9dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252244769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4252244769
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2395937298
Short name T63
Test name
Test status
Simulation time 759653680 ps
CPU time 13.83 seconds
Started Aug 13 05:13:02 PM PDT 24
Finished Aug 13 05:13:16 PM PDT 24
Peak memory 219132 kb
Host smart-a06bf4e8-539c-4737-8186-a2c017870e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395937298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2395937298
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4209376953
Short name T274
Test name
Test status
Simulation time 1656623032 ps
CPU time 8.01 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 218336 kb
Host smart-4aface5b-edd7-49ff-a35c-d4ee5567df40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209376953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4209376953
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3987247345
Short name T223
Test name
Test status
Simulation time 13088497917 ps
CPU time 191.34 seconds
Started Aug 13 05:13:01 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 218772 kb
Host smart-e2a08426-1b12-4725-9189-dfeb283e4dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987247345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3987247345
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.324792194
Short name T245
Test name
Test status
Simulation time 3543880511 ps
CPU time 22.9 seconds
Started Aug 13 05:13:00 PM PDT 24
Finished Aug 13 05:13:23 PM PDT 24
Peak memory 219392 kb
Host smart-174177eb-7579-4817-8793-f28305d21ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324792194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.324792194
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3086790752
Short name T310
Test name
Test status
Simulation time 362069040 ps
CPU time 10.14 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:13:07 PM PDT 24
Peak memory 219232 kb
Host smart-9475224f-25e4-4aa0-b851-e27717b15d68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086790752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3086790752
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2839621143
Short name T162
Test name
Test status
Simulation time 4507481433 ps
CPU time 57.13 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:13:54 PM PDT 24
Peak memory 220876 kb
Host smart-a8fcea31-0760-4281-aaa9-d3c65c6353ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839621143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2839621143
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.696193527
Short name T51
Test name
Test status
Simulation time 687570148 ps
CPU time 8.31 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:13:06 PM PDT 24
Peak memory 218392 kb
Host smart-611aad03-b6ae-41c5-8e72-054b7cc26762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696193527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.696193527
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2349033790
Short name T261
Test name
Test status
Simulation time 3913901594 ps
CPU time 261.95 seconds
Started Aug 13 05:12:57 PM PDT 24
Finished Aug 13 05:17:19 PM PDT 24
Peak memory 238324 kb
Host smart-178091d6-6557-40ec-bb9d-57ec9d0573a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349033790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2349033790
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3330691777
Short name T35
Test name
Test status
Simulation time 1077804770 ps
CPU time 22.2 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:21 PM PDT 24
Peak memory 219424 kb
Host smart-6f808b01-0448-4bcb-9169-edd7512a60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330691777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3330691777
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3295112631
Short name T188
Test name
Test status
Simulation time 273854525 ps
CPU time 13.14 seconds
Started Aug 13 05:12:58 PM PDT 24
Finished Aug 13 05:13:11 PM PDT 24
Peak memory 219352 kb
Host smart-2133161e-d631-4d79-a3b3-7da3ebcd175b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295112631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3295112631
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.695824042
Short name T208
Test name
Test status
Simulation time 167620175 ps
CPU time 8.59 seconds
Started Aug 13 05:12:01 PM PDT 24
Finished Aug 13 05:12:09 PM PDT 24
Peak memory 218080 kb
Host smart-fc1302ad-d958-400c-8e1a-08cf1010e8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695824042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.695824042
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1818794946
Short name T248
Test name
Test status
Simulation time 6800878411 ps
CPU time 382.17 seconds
Started Aug 13 05:11:54 PM PDT 24
Finished Aug 13 05:18:17 PM PDT 24
Peak memory 239212 kb
Host smart-ed72f4d3-90af-4b38-ab0e-374fe2e756e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818794946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1818794946
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1743884644
Short name T184
Test name
Test status
Simulation time 345893802 ps
CPU time 19.23 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 219356 kb
Host smart-c4572a5f-42d7-40f4-b418-18204e155494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743884644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1743884644
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2656752720
Short name T191
Test name
Test status
Simulation time 267417774 ps
CPU time 12.08 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:08 PM PDT 24
Peak memory 219244 kb
Host smart-d5233e84-73fb-448f-84ee-bc38a7025835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656752720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2656752720
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.921652125
Short name T201
Test name
Test status
Simulation time 1027731783 ps
CPU time 12.26 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 218780 kb
Host smart-d11b466f-362a-4c0b-93b9-cb47ba55bc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921652125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.921652125
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1156228631
Short name T79
Test name
Test status
Simulation time 381873202 ps
CPU time 24.93 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:20 PM PDT 24
Peak memory 219276 kb
Host smart-6ee37aca-f138-4a4c-8462-ac3c2b3fff1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156228631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1156228631
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2037541545
Short name T209
Test name
Test status
Simulation time 174346177 ps
CPU time 8.45 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:13 PM PDT 24
Peak memory 218352 kb
Host smart-8cd1e256-8617-4214-a6ab-6ad24bd31b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037541545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2037541545
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.767165520
Short name T29
Test name
Test status
Simulation time 10635341282 ps
CPU time 275.02 seconds
Started Aug 13 05:11:58 PM PDT 24
Finished Aug 13 05:16:33 PM PDT 24
Peak memory 244616 kb
Host smart-757274f7-b55f-4aa9-8c4d-1efb80c3ddca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767165520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.767165520
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1321530582
Short name T272
Test name
Test status
Simulation time 1380883365 ps
CPU time 18.83 seconds
Started Aug 13 05:12:06 PM PDT 24
Finished Aug 13 05:12:24 PM PDT 24
Peak memory 219224 kb
Host smart-52f14eeb-0ac7-463c-ac79-5fd7c3a5fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321530582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1321530582
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3630838774
Short name T204
Test name
Test status
Simulation time 184849693 ps
CPU time 10.66 seconds
Started Aug 13 05:12:01 PM PDT 24
Finished Aug 13 05:12:11 PM PDT 24
Peak memory 219264 kb
Host smart-5fefc84f-300e-417c-8382-fb7a0677d575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630838774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3630838774
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4038834789
Short name T7
Test name
Test status
Simulation time 943135562 ps
CPU time 12.82 seconds
Started Aug 13 05:11:56 PM PDT 24
Finished Aug 13 05:12:09 PM PDT 24
Peak memory 219208 kb
Host smart-d6a5e62b-805a-4a6c-b161-02ac9803bafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038834789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4038834789
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2288944355
Short name T126
Test name
Test status
Simulation time 382233473 ps
CPU time 27.65 seconds
Started Aug 13 05:11:55 PM PDT 24
Finished Aug 13 05:12:23 PM PDT 24
Peak memory 219272 kb
Host smart-b40d7ace-fee0-42c6-a549-03ce888a3aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288944355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2288944355
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2730459301
Short name T143
Test name
Test status
Simulation time 826749311 ps
CPU time 8.36 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:11 PM PDT 24
Peak memory 218272 kb
Host smart-6efecd0c-93bb-4ed9-9c8b-7770575eff88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730459301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2730459301
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1298787151
Short name T314
Test name
Test status
Simulation time 2561021109 ps
CPU time 164.47 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:14:49 PM PDT 24
Peak memory 240252 kb
Host smart-b55f8f41-6237-465d-9302-fd7eb8d6488f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298787151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1298787151
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.967160309
Short name T158
Test name
Test status
Simulation time 3093185981 ps
CPU time 23.1 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:28 PM PDT 24
Peak memory 219380 kb
Host smart-3cb32ab7-b8b4-4f3f-bc47-0f3510ec1a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967160309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.967160309
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.494230555
Short name T279
Test name
Test status
Simulation time 377309661 ps
CPU time 10.59 seconds
Started Aug 13 05:11:57 PM PDT 24
Finished Aug 13 05:12:07 PM PDT 24
Peak memory 219316 kb
Host smart-59c30171-c6a8-423d-84c5-8bd4b09a86a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494230555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.494230555
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.907692440
Short name T305
Test name
Test status
Simulation time 269002721 ps
CPU time 12.15 seconds
Started Aug 13 05:12:05 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 219336 kb
Host smart-3ef49ecb-0e10-442a-9e5d-2b322e250fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907692440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.907692440
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2795522957
Short name T170
Test name
Test status
Simulation time 1286650160 ps
CPU time 27.66 seconds
Started Aug 13 05:12:05 PM PDT 24
Finished Aug 13 05:12:32 PM PDT 24
Peak memory 219176 kb
Host smart-aea472a0-03af-4f22-a798-c346d169c504
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795522957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2795522957
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3497682422
Short name T280
Test name
Test status
Simulation time 3072619153 ps
CPU time 9.64 seconds
Started Aug 13 05:12:07 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 218376 kb
Host smart-3c3ae31b-b016-48f7-abcc-39ba665643c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497682422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3497682422
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3699675104
Short name T294
Test name
Test status
Simulation time 4572621829 ps
CPU time 251.29 seconds
Started Aug 13 05:12:02 PM PDT 24
Finished Aug 13 05:16:13 PM PDT 24
Peak memory 228616 kb
Host smart-f3cfe348-f7e3-44e2-a9ca-9d94d953f594
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699675104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3699675104
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1839772780
Short name T189
Test name
Test status
Simulation time 1900961647 ps
CPU time 22.95 seconds
Started Aug 13 05:12:06 PM PDT 24
Finished Aug 13 05:12:29 PM PDT 24
Peak memory 219284 kb
Host smart-c84a30d7-b630-4937-81d5-aef97b823fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839772780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1839772780
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3496747458
Short name T287
Test name
Test status
Simulation time 1533753345 ps
CPU time 12.9 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:16 PM PDT 24
Peak memory 219272 kb
Host smart-b1786fb4-43aa-4698-8082-389f6f89b0a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496747458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3496747458
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3741114420
Short name T264
Test name
Test status
Simulation time 417032216 ps
CPU time 10.11 seconds
Started Aug 13 05:12:02 PM PDT 24
Finished Aug 13 05:12:13 PM PDT 24
Peak memory 219392 kb
Host smart-23994040-4219-48ec-ad36-89987e941c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741114420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3741114420
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.742977349
Short name T312
Test name
Test status
Simulation time 539390292 ps
CPU time 33.76 seconds
Started Aug 13 05:12:06 PM PDT 24
Finished Aug 13 05:12:40 PM PDT 24
Peak memory 219376 kb
Host smart-208c67ea-f5f8-4b9e-9dcd-137016be8ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742977349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.742977349
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3778095158
Short name T165
Test name
Test status
Simulation time 167683002 ps
CPU time 8.33 seconds
Started Aug 13 05:12:04 PM PDT 24
Finished Aug 13 05:12:13 PM PDT 24
Peak memory 218316 kb
Host smart-f099462d-4b48-4695-a9ae-f03c668cf4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778095158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3778095158
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2225537686
Short name T316
Test name
Test status
Simulation time 14497766804 ps
CPU time 253.9 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:16:17 PM PDT 24
Peak memory 219584 kb
Host smart-0cbb45a3-e87c-46a0-9ec4-1d5ef0a3d60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225537686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2225537686
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1869965037
Short name T247
Test name
Test status
Simulation time 1381620891 ps
CPU time 19.49 seconds
Started Aug 13 05:12:03 PM PDT 24
Finished Aug 13 05:12:22 PM PDT 24
Peak memory 219400 kb
Host smart-ad1dfd01-184b-4410-b895-d253aa625ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869965037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1869965037
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2137197430
Short name T64
Test name
Test status
Simulation time 272363215 ps
CPU time 12.43 seconds
Started Aug 13 05:12:05 PM PDT 24
Finished Aug 13 05:12:17 PM PDT 24
Peak memory 219308 kb
Host smart-8433dd4d-7655-4df7-b379-feba48b3cc04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137197430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2137197430
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2268688508
Short name T74
Test name
Test status
Simulation time 1037650730 ps
CPU time 12.81 seconds
Started Aug 13 05:12:07 PM PDT 24
Finished Aug 13 05:12:20 PM PDT 24
Peak memory 219368 kb
Host smart-c880c928-0a48-412f-81f5-14e35de17919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268688508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2268688508
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3969665304
Short name T93
Test name
Test status
Simulation time 865384831 ps
CPU time 19.7 seconds
Started Aug 13 05:12:12 PM PDT 24
Finished Aug 13 05:12:32 PM PDT 24
Peak memory 219252 kb
Host smart-6b0646cc-45a6-4b7f-8f6f-b92be6f875b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969665304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3969665304
Directory /workspace/9.rom_ctrl_stress_all/latest
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