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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 96.89 91.85 97.68 100.00 98.28 97.30 98.14


Total test records in report: 411
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T304 /workspace/coverage/default/21.rom_ctrl_stress_all.771560649 Aug 14 05:24:19 PM PDT 24 Aug 14 05:24:46 PM PDT 24 1363795193 ps
T305 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.79656058 Aug 14 05:25:09 PM PDT 24 Aug 14 05:25:28 PM PDT 24 1379882075 ps
T158 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2402070131 Aug 14 05:24:39 PM PDT 24 Aug 14 05:29:55 PM PDT 24 5591764842 ps
T306 /workspace/coverage/default/5.rom_ctrl_stress_all.888581053 Aug 14 05:23:20 PM PDT 24 Aug 14 05:23:46 PM PDT 24 2108247791 ps
T307 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.453942197 Aug 14 05:23:08 PM PDT 24 Aug 14 05:23:31 PM PDT 24 2752920836 ps
T308 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.829820316 Aug 14 05:25:12 PM PDT 24 Aug 14 05:28:46 PM PDT 24 15785040519 ps
T309 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.106615303 Aug 14 05:23:16 PM PDT 24 Aug 14 05:27:25 PM PDT 24 7342390554 ps
T310 /workspace/coverage/default/18.rom_ctrl_alert_test.407213909 Aug 14 05:24:13 PM PDT 24 Aug 14 05:24:22 PM PDT 24 339652619 ps
T311 /workspace/coverage/default/1.rom_ctrl_alert_test.504670151 Aug 14 05:23:01 PM PDT 24 Aug 14 05:23:11 PM PDT 24 258072109 ps
T312 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.32883722 Aug 14 05:24:12 PM PDT 24 Aug 14 05:24:35 PM PDT 24 508271815 ps
T313 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.734707290 Aug 14 05:24:05 PM PDT 24 Aug 14 05:24:16 PM PDT 24 185616922 ps
T314 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.805789459 Aug 14 05:23:23 PM PDT 24 Aug 14 05:26:51 PM PDT 24 4262566587 ps
T315 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4162355074 Aug 14 05:23:40 PM PDT 24 Aug 14 05:23:50 PM PDT 24 181854093 ps
T316 /workspace/coverage/default/38.rom_ctrl_alert_test.3067857616 Aug 14 05:25:00 PM PDT 24 Aug 14 05:25:09 PM PDT 24 168384400 ps
T317 /workspace/coverage/default/3.rom_ctrl_smoke.2571402333 Aug 14 05:23:00 PM PDT 24 Aug 14 05:23:18 PM PDT 24 4101679761 ps
T318 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1111678117 Aug 14 05:23:47 PM PDT 24 Aug 14 05:24:06 PM PDT 24 1033383511 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2298617079 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:53 PM PDT 24 3442231309 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2730719864 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:15 PM PDT 24 1035374032 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1607994791 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:09 PM PDT 24 986631038 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2192928349 Aug 14 04:43:10 PM PDT 24 Aug 14 04:44:15 PM PDT 24 6296311816 ps
T26 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.319588759 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:15 PM PDT 24 167309522 ps
T27 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1478483222 Aug 14 04:43:17 PM PDT 24 Aug 14 04:45:55 PM PDT 24 488318252 ps
T29 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2953131650 Aug 14 04:42:53 PM PDT 24 Aug 14 04:43:05 PM PDT 24 271230663 ps
T48 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2581264645 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:36 PM PDT 24 176899550 ps
T319 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.401888543 Aug 14 04:43:10 PM PDT 24 Aug 14 04:43:18 PM PDT 24 362523729 ps
T82 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1041004957 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:49 PM PDT 24 2551700179 ps
T49 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3472167727 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:28 PM PDT 24 1030716483 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1203484663 Aug 14 04:43:06 PM PDT 24 Aug 14 04:43:45 PM PDT 24 722420992 ps
T50 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3246426901 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:08 PM PDT 24 1578207048 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3778728353 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:27 PM PDT 24 249248922 ps
T85 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3345704769 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:19 PM PDT 24 306608351 ps
T51 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.347047753 Aug 14 04:43:08 PM PDT 24 Aug 14 04:43:16 PM PDT 24 1739655426 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1893985167 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:27 PM PDT 24 261433697 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3148167896 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:25 PM PDT 24 1308452118 ps
T320 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3100557241 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:21 PM PDT 24 981635666 ps
T321 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2863833615 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:13 PM PDT 24 1772645595 ps
T322 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1737721362 Aug 14 04:42:52 PM PDT 24 Aug 14 04:43:30 PM PDT 24 691618549 ps
T323 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2484949554 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:29 PM PDT 24 1373144421 ps
T52 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4176487686 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:15 PM PDT 24 260521398 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3842765535 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:19 PM PDT 24 1029062787 ps
T53 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.684385333 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:11 PM PDT 24 990110796 ps
T80 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.758334057 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:26 PM PDT 24 4094912352 ps
T63 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3039796896 Aug 14 04:43:13 PM PDT 24 Aug 14 04:45:41 PM PDT 24 1126404871 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3193638277 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:20 PM PDT 24 168489346 ps
T324 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2819871998 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:30 PM PDT 24 504409309 ps
T104 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1763939291 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:14 PM PDT 24 262681506 ps
T325 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1985771582 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:15 PM PDT 24 255035638 ps
T326 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2902876425 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:27 PM PDT 24 1542832673 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3822299527 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:30 PM PDT 24 1031249268 ps
T327 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2511378137 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:50 PM PDT 24 1074809733 ps
T106 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3947543971 Aug 14 04:43:20 PM PDT 24 Aug 14 04:43:28 PM PDT 24 333241339 ps
T328 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3883847670 Aug 14 04:42:56 PM PDT 24 Aug 14 04:43:11 PM PDT 24 1830525168 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2288603294 Aug 14 04:43:03 PM PDT 24 Aug 14 04:44:23 PM PDT 24 444314329 ps
T107 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.428011483 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:16 PM PDT 24 254262341 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3809494677 Aug 14 04:43:11 PM PDT 24 Aug 14 04:45:54 PM PDT 24 2281465855 ps
T329 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1902038803 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:26 PM PDT 24 250765097 ps
T330 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3231423893 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:12 PM PDT 24 529056096 ps
T331 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.981349428 Aug 14 04:43:24 PM PDT 24 Aug 14 04:43:38 PM PDT 24 1273175271 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.238447147 Aug 14 04:43:15 PM PDT 24 Aug 14 04:44:00 PM PDT 24 4080535888 ps
T115 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1694349149 Aug 14 04:42:56 PM PDT 24 Aug 14 04:45:36 PM PDT 24 1735023824 ps
T332 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1105031281 Aug 14 04:43:07 PM PDT 24 Aug 14 04:43:20 PM PDT 24 250366715 ps
T333 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1934076459 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:15 PM PDT 24 2582390149 ps
T334 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.470292030 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:28 PM PDT 24 982665676 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.99844046 Aug 14 04:43:10 PM PDT 24 Aug 14 04:44:15 PM PDT 24 6091153494 ps
T335 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.532025348 Aug 14 04:42:52 PM PDT 24 Aug 14 04:43:09 PM PDT 24 1000418087 ps
T113 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.65405687 Aug 14 04:42:59 PM PDT 24 Aug 14 04:43:38 PM PDT 24 2873024113 ps
T336 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2834727254 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:11 PM PDT 24 444325930 ps
T337 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3110939640 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:23 PM PDT 24 175428460 ps
T338 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3378681122 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:07 PM PDT 24 823067063 ps
T339 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.577715619 Aug 14 04:43:08 PM PDT 24 Aug 14 04:43:17 PM PDT 24 748850192 ps
T340 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2129206123 Aug 14 04:42:59 PM PDT 24 Aug 14 04:44:20 PM PDT 24 4582245126 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4231799807 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:13 PM PDT 24 992554662 ps
T121 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1753128885 Aug 14 04:42:59 PM PDT 24 Aug 14 04:44:21 PM PDT 24 937670038 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.629729655 Aug 14 04:43:18 PM PDT 24 Aug 14 04:43:28 PM PDT 24 1026930108 ps
T341 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2577189636 Aug 14 04:43:12 PM PDT 24 Aug 14 04:43:25 PM PDT 24 636343000 ps
T342 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.218824466 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:28 PM PDT 24 257730224 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2987195640 Aug 14 04:43:04 PM PDT 24 Aug 14 04:44:26 PM PDT 24 467606190 ps
T343 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1055479618 Aug 14 04:43:22 PM PDT 24 Aug 14 04:45:59 PM PDT 24 769962674 ps
T344 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.63581554 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:25 PM PDT 24 564783732 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.377287355 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:49 PM PDT 24 7243506910 ps
T345 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1831003355 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:15 PM PDT 24 2053150351 ps
T346 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.8743589 Aug 14 04:42:56 PM PDT 24 Aug 14 04:43:11 PM PDT 24 5202445562 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.272263743 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:12 PM PDT 24 255847610 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2473840315 Aug 14 04:43:02 PM PDT 24 Aug 14 04:43:48 PM PDT 24 1021505729 ps
T348 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3739499265 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:19 PM PDT 24 1031588696 ps
T349 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1639083591 Aug 14 04:42:50 PM PDT 24 Aug 14 04:43:05 PM PDT 24 269822389 ps
T118 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.21978521 Aug 14 04:43:04 PM PDT 24 Aug 14 04:45:41 PM PDT 24 408834719 ps
T350 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3752569195 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:05 PM PDT 24 175247286 ps
T122 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3821410662 Aug 14 04:43:15 PM PDT 24 Aug 14 04:45:58 PM PDT 24 690843146 ps
T351 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2568206506 Aug 14 04:43:12 PM PDT 24 Aug 14 04:43:24 PM PDT 24 667717416 ps
T352 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.572107438 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:07 PM PDT 24 2059465578 ps
T353 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.103358100 Aug 14 04:43:06 PM PDT 24 Aug 14 04:43:16 PM PDT 24 260716125 ps
T354 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2691782123 Aug 14 04:43:16 PM PDT 24 Aug 14 04:43:24 PM PDT 24 660647201 ps
T355 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2851193225 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:12 PM PDT 24 168755044 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3705406167 Aug 14 04:43:11 PM PDT 24 Aug 14 04:45:48 PM PDT 24 610405536 ps
T356 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1809187061 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:15 PM PDT 24 990126042 ps
T357 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.7771140 Aug 14 04:43:06 PM PDT 24 Aug 14 04:43:17 PM PDT 24 3684826376 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4140956215 Aug 14 04:42:49 PM PDT 24 Aug 14 04:43:28 PM PDT 24 692430609 ps
T358 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.887365494 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:10 PM PDT 24 718252319 ps
T359 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2605956404 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:07 PM PDT 24 1238121843 ps
T360 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4136738016 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:13 PM PDT 24 636404389 ps
T361 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.444855856 Aug 14 04:43:06 PM PDT 24 Aug 14 04:43:21 PM PDT 24 2059518561 ps
T362 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.964935219 Aug 14 04:43:30 PM PDT 24 Aug 14 04:43:40 PM PDT 24 260915304 ps
T363 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2713469299 Aug 14 04:43:17 PM PDT 24 Aug 14 04:43:35 PM PDT 24 4147865252 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2610231627 Aug 14 04:43:02 PM PDT 24 Aug 14 04:43:46 PM PDT 24 1027300810 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1370477467 Aug 14 04:43:42 PM PDT 24 Aug 14 04:44:26 PM PDT 24 3631487666 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3093250723 Aug 14 04:43:25 PM PDT 24 Aug 14 04:44:20 PM PDT 24 2346560425 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.969165963 Aug 14 04:43:38 PM PDT 24 Aug 14 04:43:50 PM PDT 24 365345256 ps
T366 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2957983086 Aug 14 04:43:12 PM PDT 24 Aug 14 04:43:23 PM PDT 24 179959038 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2781277221 Aug 14 04:43:08 PM PDT 24 Aug 14 04:44:30 PM PDT 24 241816402 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1776849304 Aug 14 04:42:46 PM PDT 24 Aug 14 04:42:57 PM PDT 24 167795665 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2563884379 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:55 PM PDT 24 2561998090 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3914565789 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:21 PM PDT 24 692298536 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1118121017 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:24 PM PDT 24 3933888239 ps
T98 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.801798761 Aug 14 04:43:07 PM PDT 24 Aug 14 04:43:15 PM PDT 24 1648542289 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4207371636 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:22 PM PDT 24 528445855 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3804873761 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:24 PM PDT 24 250545868 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1340657251 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:25 PM PDT 24 689447045 ps
T375 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3262687971 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:29 PM PDT 24 176275204 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2349785027 Aug 14 04:43:19 PM PDT 24 Aug 14 04:43:33 PM PDT 24 515942755 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2450296551 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:08 PM PDT 24 167543416 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3983193825 Aug 14 04:42:57 PM PDT 24 Aug 14 04:44:00 PM PDT 24 15840031119 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4233383195 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:08 PM PDT 24 498025437 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2795458766 Aug 14 04:43:11 PM PDT 24 Aug 14 04:43:25 PM PDT 24 251487716 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3626688913 Aug 14 04:43:13 PM PDT 24 Aug 14 04:44:12 PM PDT 24 1036045074 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.312486073 Aug 14 04:43:02 PM PDT 24 Aug 14 04:43:13 PM PDT 24 251078988 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2384828572 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:08 PM PDT 24 504875377 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4210515641 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:12 PM PDT 24 1271055157 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1311388212 Aug 14 04:42:41 PM PDT 24 Aug 14 04:42:50 PM PDT 24 662821987 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1054560346 Aug 14 04:43:22 PM PDT 24 Aug 14 04:43:33 PM PDT 24 250833671 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.804286703 Aug 14 04:43:15 PM PDT 24 Aug 14 04:44:37 PM PDT 24 233354927 ps
T120 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3628540959 Aug 14 04:42:43 PM PDT 24 Aug 14 04:45:19 PM PDT 24 1367218966 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2109739241 Aug 14 04:43:15 PM PDT 24 Aug 14 04:43:25 PM PDT 24 261351124 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3714272672 Aug 14 04:42:50 PM PDT 24 Aug 14 04:43:00 PM PDT 24 291429557 ps
T390 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1240567307 Aug 14 04:43:19 PM PDT 24 Aug 14 04:44:04 PM PDT 24 4079042155 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2704023349 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:26 PM PDT 24 1673984218 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.776176282 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:13 PM PDT 24 174565885 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3343313725 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:11 PM PDT 24 1127758042 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2968046220 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:22 PM PDT 24 167511397 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3504324678 Aug 14 04:43:09 PM PDT 24 Aug 14 04:44:11 PM PDT 24 18012264309 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3451395082 Aug 14 04:43:12 PM PDT 24 Aug 14 04:43:23 PM PDT 24 275140564 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3743156808 Aug 14 04:42:53 PM PDT 24 Aug 14 04:43:06 PM PDT 24 1898799138 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1819619102 Aug 14 04:42:49 PM PDT 24 Aug 14 04:43:06 PM PDT 24 1054747435 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2846795764 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:24 PM PDT 24 460123922 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1348680379 Aug 14 04:43:14 PM PDT 24 Aug 14 04:43:22 PM PDT 24 352829004 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1145852157 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:22 PM PDT 24 181870268 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.127832198 Aug 14 04:43:14 PM PDT 24 Aug 14 04:45:52 PM PDT 24 3242570502 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1066149129 Aug 14 04:43:10 PM PDT 24 Aug 14 04:43:19 PM PDT 24 688917927 ps
T124 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.28215395 Aug 14 04:43:10 PM PDT 24 Aug 14 04:45:49 PM PDT 24 544513593 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.698036151 Aug 14 04:42:54 PM PDT 24 Aug 14 04:43:04 PM PDT 24 250660808 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2732497769 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:17 PM PDT 24 167550886 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2027148206 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:16 PM PDT 24 1034722741 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2336545284 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:12 PM PDT 24 2743517076 ps
T123 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2347244603 Aug 14 04:43:05 PM PDT 24 Aug 14 04:45:41 PM PDT 24 3397072668 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1950061158 Aug 14 04:42:53 PM PDT 24 Aug 14 04:43:04 PM PDT 24 935405643 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2664886371 Aug 14 04:42:48 PM PDT 24 Aug 14 04:43:00 PM PDT 24 693836746 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2438682701 Aug 14 04:43:18 PM PDT 24 Aug 14 04:45:56 PM PDT 24 503289479 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3965978777 Aug 14 04:43:42 PM PDT 24 Aug 14 04:45:06 PM PDT 24 903580337 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780860296 Aug 14 04:42:59 PM PDT 24 Aug 14 04:43:12 PM PDT 24 509243062 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1392828114 Aug 14 04:43:13 PM PDT 24 Aug 14 04:43:23 PM PDT 24 1014542106 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2155125731 Aug 14 04:42:50 PM PDT 24 Aug 14 04:42:59 PM PDT 24 249473135 ps

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2287313897
Short name T6
Test name
Test status
Simulation time 4483906260 ps
CPU time 157.93 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:25:38 PM PDT 24
Peak memory 228896 kb
Host smart-e0d926c6-e4d6-4c46-a5e8-0e47b42d57c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287313897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2287313897
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2528715881
Short name T15
Test name
Test status
Simulation time 2007052446 ps
CPU time 55.07 seconds
Started Aug 14 05:25:12 PM PDT 24
Finished Aug 14 05:26:07 PM PDT 24
Peak memory 227896 kb
Host smart-556e01a2-f00d-4889-811f-2245015038ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528715881 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2528715881
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1137795916
Short name T112
Test name
Test status
Simulation time 1442810797 ps
CPU time 20.1 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:23:20 PM PDT 24
Peak memory 219316 kb
Host smart-264159c9-1b8b-4e62-bfc5-4fbff1bd2be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137795916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1137795916
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1308688860
Short name T20
Test name
Test status
Simulation time 530915165 ps
CPU time 12.52 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:25:22 PM PDT 24
Peak memory 219320 kb
Host smart-8bf9bc88-38c4-4016-a82b-144c9608b39f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308688860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1308688860
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1641545718
Short name T12
Test name
Test status
Simulation time 5613582952 ps
CPU time 322.41 seconds
Started Aug 14 05:24:38 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 225272 kb
Host smart-27c397bb-e124-4081-91f4-66d42f35af4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641545718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1641545718
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2879052173
Short name T14
Test name
Test status
Simulation time 662392547 ps
CPU time 8.27 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:23:08 PM PDT 24
Peak memory 218432 kb
Host smart-a8aed542-6207-4e84-848b-6ab501fe2879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879052173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2879052173
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1478483222
Short name T27
Test name
Test status
Simulation time 488318252 ps
CPU time 157.36 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:45:55 PM PDT 24
Peak memory 219188 kb
Host smart-f67175e2-9744-4a94-a146-759a0b32b16e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478483222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1478483222
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1637484599
Short name T255
Test name
Test status
Simulation time 31313620796 ps
CPU time 323.12 seconds
Started Aug 14 05:24:50 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 239164 kb
Host smart-39cb9fdf-bbfc-45f6-9605-2a331876a1b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637484599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1637484599
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.517968278
Short name T17
Test name
Test status
Simulation time 575164661 ps
CPU time 25 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:25:35 PM PDT 24
Peak memory 219328 kb
Host smart-0594ba5a-af43-4c8f-8c7a-901930aa5b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517968278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.517968278
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2252937520
Short name T128
Test name
Test status
Simulation time 789732796 ps
CPU time 10.39 seconds
Started Aug 14 05:22:52 PM PDT 24
Finished Aug 14 05:23:02 PM PDT 24
Peak memory 219312 kb
Host smart-4d19f48b-a66c-4afd-a511-1bd38a5ffdd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252937520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2252937520
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2298617079
Short name T73
Test name
Test status
Simulation time 3442231309 ps
CPU time 37.8 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 214152 kb
Host smart-573a2736-87de-415c-843f-6d311ce91e67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298617079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2298617079
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1415496650
Short name T22
Test name
Test status
Simulation time 353041759 ps
CPU time 226.25 seconds
Started Aug 14 05:23:14 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 239048 kb
Host smart-c7515137-d85c-461d-b6f5-17fbd964adfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415496650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1415496650
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4219519976
Short name T66
Test name
Test status
Simulation time 4993834083 ps
CPU time 47.09 seconds
Started Aug 14 05:22:51 PM PDT 24
Finished Aug 14 05:23:39 PM PDT 24
Peak memory 220416 kb
Host smart-5b45ce08-349a-4e10-90a9-9db4814cde16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219519976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4219519976
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1412910876
Short name T205
Test name
Test status
Simulation time 3929547906 ps
CPU time 31.91 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:25:07 PM PDT 24
Peak memory 219480 kb
Host smart-f5bd3927-9884-4ddd-8361-c88060e3e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412910876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1412910876
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1694349149
Short name T115
Test name
Test status
Simulation time 1735023824 ps
CPU time 159.87 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:45:36 PM PDT 24
Peak memory 214568 kb
Host smart-85b47a58-bfc3-4db9-8641-0fe908eccbee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694349149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1694349149
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3671770077
Short name T88
Test name
Test status
Simulation time 363751754 ps
CPU time 27.31 seconds
Started Aug 14 05:24:29 PM PDT 24
Finished Aug 14 05:24:57 PM PDT 24
Peak memory 219156 kb
Host smart-a1514265-60aa-4be5-a444-cfc657295887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671770077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3671770077
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.734122895
Short name T1
Test name
Test status
Simulation time 511144922 ps
CPU time 22.69 seconds
Started Aug 14 05:23:03 PM PDT 24
Finished Aug 14 05:23:26 PM PDT 24
Peak memory 219196 kb
Host smart-faca543b-9b8d-4884-a0b4-ac084fe173ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734122895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.734122895
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1908617580
Short name T39
Test name
Test status
Simulation time 260492753 ps
CPU time 10.47 seconds
Started Aug 14 05:24:05 PM PDT 24
Finished Aug 14 05:24:16 PM PDT 24
Peak memory 218524 kb
Host smart-e3bebdcf-e2a3-473c-8f3e-ff9d4a010704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908617580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1908617580
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4140956215
Short name T101
Test name
Test status
Simulation time 692430609 ps
CPU time 38.03 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 214180 kb
Host smart-82d41b3f-2ea7-4cf1-a81a-ca2d706d9641
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140956215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4140956215
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2656592692
Short name T126
Test name
Test status
Simulation time 20779811764 ps
CPU time 399.13 seconds
Started Aug 14 05:24:04 PM PDT 24
Finished Aug 14 05:30:43 PM PDT 24
Peak memory 238668 kb
Host smart-846a68a6-1d47-4811-ad93-058e734b5130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656592692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2656592692
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3628540959
Short name T120
Test name
Test status
Simulation time 1367218966 ps
CPU time 156.21 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 214284 kb
Host smart-6cd5e2fa-d82d-4586-b1ea-08c29bd1b81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628540959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3628540959
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3821410662
Short name T122
Test name
Test status
Simulation time 690843146 ps
CPU time 163.04 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:45:58 PM PDT 24
Peak memory 215456 kb
Host smart-558b191c-d4b2-4c02-b1c9-a51f34165ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821410662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3821410662
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.127832198
Short name T117
Test name
Test status
Simulation time 3242570502 ps
CPU time 157.29 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:45:52 PM PDT 24
Peak memory 214392 kb
Host smart-7e3ee109-47ab-4b7f-8eac-31fe01d03a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127832198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.127832198
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1203484663
Short name T83
Test name
Test status
Simulation time 722420992 ps
CPU time 38.39 seconds
Started Aug 14 04:43:06 PM PDT 24
Finished Aug 14 04:43:45 PM PDT 24
Peak memory 214244 kb
Host smart-ba6bea85-bb83-4ef0-a21d-b8d0f053fe6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203484663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1203484663
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2581264645
Short name T48
Test name
Test status
Simulation time 176899550 ps
CPU time 13.67 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 216976 kb
Host smart-bd14c108-850d-455c-bf74-88670f6198ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581264645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2581264645
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1311388212
Short name T385
Test name
Test status
Simulation time 662821987 ps
CPU time 8.54 seconds
Started Aug 14 04:42:41 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 209872 kb
Host smart-131dbf20-8dfd-4299-95ec-ccfe49f6d0b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311388212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1311388212
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1831003355
Short name T345
Test name
Test status
Simulation time 2053150351 ps
CPU time 14.99 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 211184 kb
Host smart-cf6814bd-984b-4dcd-bd67-c0632ff0282a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831003355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1831003355
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.532025348
Short name T335
Test name
Test status
Simulation time 1000418087 ps
CPU time 17.09 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:43:09 PM PDT 24
Peak memory 212596 kb
Host smart-25622ecc-e80b-41f2-88ea-ecf74fe36a2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532025348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.532025348
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3378681122
Short name T338
Test name
Test status
Simulation time 823067063 ps
CPU time 9.06 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 219164 kb
Host smart-bc7058b7-e678-4ce1-b4a6-1934d6b8e433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378681122 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3378681122
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.698036151
Short name T401
Test name
Test status
Simulation time 250660808 ps
CPU time 9.77 seconds
Started Aug 14 04:42:54 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 210920 kb
Host smart-c1653355-f30c-40a6-8800-820adc9447ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698036151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.698036151
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2155125731
Short name T411
Test name
Test status
Simulation time 249473135 ps
CPU time 9.8 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 210872 kb
Host smart-8073df91-5de1-4a67-abcc-819d757c5d2b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155125731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2155125731
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.572107438
Short name T352
Test name
Test status
Simulation time 2059465578 ps
CPU time 10 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 210960 kb
Host smart-7ca60cfc-bedc-4750-9611-b4dee0dc50a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572107438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
572107438
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4233383195
Short name T379
Test name
Test status
Simulation time 498025437 ps
CPU time 9.81 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 211320 kb
Host smart-431dd27a-0445-4a60-b071-a590c604afaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233383195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4233383195
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3743156808
Short name T395
Test name
Test status
Simulation time 1898799138 ps
CPU time 12.93 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 217712 kb
Host smart-3eee417a-64c9-4b41-aa41-b624ad1bcca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743156808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3743156808
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2129206123
Short name T340
Test name
Test status
Simulation time 4582245126 ps
CPU time 81.78 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 214420 kb
Host smart-928c3657-add2-4d10-8ab6-888e541b7a94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129206123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2129206123
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2336545284
Short name T404
Test name
Test status
Simulation time 2743517076 ps
CPU time 8.33 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 211172 kb
Host smart-bde7a95f-daaf-44de-9d64-d85c283f3050
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336545284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2336545284
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3883847670
Short name T328
Test name
Test status
Simulation time 1830525168 ps
CPU time 15.09 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 210988 kb
Host smart-30156bd4-c7f2-4913-a9af-e3956fc2e7a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883847670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3883847670
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1819619102
Short name T396
Test name
Test status
Simulation time 1054747435 ps
CPU time 17.03 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 212304 kb
Host smart-b40f9f92-4849-470d-b47c-11e516ed33e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819619102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1819619102
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3246426901
Short name T50
Test name
Test status
Simulation time 1578207048 ps
CPU time 10.2 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 214612 kb
Host smart-b496c782-802b-4033-992a-8c67ae8a31ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246426901 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3246426901
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.8743589
Short name T346
Test name
Test status
Simulation time 5202445562 ps
CPU time 14.72 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 211956 kb
Host smart-4af7cc5e-f3b5-4260-b458-663eeac73f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8743589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.8743589
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2605956404
Short name T359
Test name
Test status
Simulation time 1238121843 ps
CPU time 9.56 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 210852 kb
Host smart-9efd00c7-55b6-48fb-8d5c-ce21c24ee86e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605956404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2605956404
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.776176282
Short name T392
Test name
Test status
Simulation time 174565885 ps
CPU time 7.9 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:13 PM PDT 24
Peak memory 210928 kb
Host smart-0f6298b0-dd84-4374-8649-57481154c57a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776176282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
776176282
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2473840315
Short name T96
Test name
Test status
Simulation time 1021505729 ps
CPU time 45.28 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:48 PM PDT 24
Peak memory 214076 kb
Host smart-0ba00cc3-74a2-461a-b93e-64242b5314ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473840315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2473840315
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1809187061
Short name T356
Test name
Test status
Simulation time 990126042 ps
CPU time 10.18 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 211704 kb
Host smart-cc498d71-8f81-449e-ba19-a1f4f140d697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809187061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1809187061
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4176487686
Short name T52
Test name
Test status
Simulation time 260521398 ps
CPU time 12.7 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 217496 kb
Host smart-141195b1-e19a-42cc-a1d2-a90b570c7af7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176487686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4176487686
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.7771140
Short name T357
Test name
Test status
Simulation time 3684826376 ps
CPU time 10.45 seconds
Started Aug 14 04:43:06 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 216576 kb
Host smart-3e3fa6d9-7361-465a-bd49-3d8320856142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7771140 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.7771140
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2109739241
Short name T388
Test name
Test status
Simulation time 261351124 ps
CPU time 9.83 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 211124 kb
Host smart-1c976136-f0a0-4f33-9c45-ae56dac8f5e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109739241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2109739241
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2563884379
Short name T369
Test name
Test status
Simulation time 2561998090 ps
CPU time 37.45 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 215256 kb
Host smart-5ec5ed6c-e5cf-485b-9218-a715542ac248
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563884379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2563884379
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2713469299
Short name T363
Test name
Test status
Simulation time 4147865252 ps
CPU time 18.69 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 212940 kb
Host smart-fd98cf08-d439-4fbe-b44f-346da9939f9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713469299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2713469299
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2795458766
Short name T380
Test name
Test status
Simulation time 251487716 ps
CPU time 13.3 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 217380 kb
Host smart-90f3c6d6-86b0-4a25-8805-f5ca788bb843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795458766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2795458766
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2987195640
Short name T116
Test name
Test status
Simulation time 467606190 ps
CPU time 81.29 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 213052 kb
Host smart-529bea7a-2017-422b-91f8-d8c38b35e993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987195640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2987195640
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4207371636
Short name T372
Test name
Test status
Simulation time 528445855 ps
CPU time 10.69 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 216728 kb
Host smart-bb42d316-13f1-4e2b-be6d-239bfe050511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207371636 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4207371636
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.444855856
Short name T361
Test name
Test status
Simulation time 2059518561 ps
CPU time 15.18 seconds
Started Aug 14 04:43:06 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 211280 kb
Host smart-47b178c8-4df6-4705-8b8d-24ef68da51ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444855856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.444855856
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3914565789
Short name T370
Test name
Test status
Simulation time 692298536 ps
CPU time 8.65 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 211680 kb
Host smart-20ad33da-6261-43c4-ac5e-c921f6a15a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914565789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3914565789
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2349785027
Short name T376
Test name
Test status
Simulation time 515942755 ps
CPU time 13.72 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 217772 kb
Host smart-7da436c2-141d-46ee-90b3-b9d263ac16a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349785027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2349785027
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2834727254
Short name T336
Test name
Test status
Simulation time 444325930 ps
CPU time 10.84 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 217064 kb
Host smart-967a4103-44f9-4f73-943e-3e0415e6e22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834727254 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2834727254
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.964935219
Short name T362
Test name
Test status
Simulation time 260915304 ps
CPU time 10.22 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 211012 kb
Host smart-5c58389f-d085-497f-9330-a664f478c4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964935219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.964935219
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2511378137
Short name T327
Test name
Test status
Simulation time 1074809733 ps
CPU time 44.36 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 213972 kb
Host smart-6b821a12-2e1c-4662-a79f-ad87039d24e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511378137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2511378137
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1763939291
Short name T104
Test name
Test status
Simulation time 262681506 ps
CPU time 10.14 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:14 PM PDT 24
Peak memory 211476 kb
Host smart-37226994-8e5a-49d4-ace1-374ea1d63441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763939291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1763939291
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3110939640
Short name T337
Test name
Test status
Simulation time 175428460 ps
CPU time 11.61 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 217664 kb
Host smart-8d92bc60-a4d2-47b3-a4c4-2a41fcdc7e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110939640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3110939640
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1118121017
Short name T371
Test name
Test status
Simulation time 3933888239 ps
CPU time 15.05 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 217112 kb
Host smart-0e5cfe92-6735-4607-a849-c17e56b9d774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118121017 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1118121017
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1348680379
Short name T398
Test name
Test status
Simulation time 352829004 ps
CPU time 8.03 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 211352 kb
Host smart-acb97e49-04e9-4270-ba09-72f5e30f3188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348680379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1348680379
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1041004957
Short name T82
Test name
Test status
Simulation time 2551700179 ps
CPU time 37.13 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 215580 kb
Host smart-3cd33afd-672e-4e63-be1b-8635dda8cb60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041004957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1041004957
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4231799807
Short name T108
Test name
Test status
Simulation time 992554662 ps
CPU time 9.97 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:13 PM PDT 24
Peak memory 211576 kb
Host smart-6d594318-8d7d-4cea-a5d2-e86f8026f848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231799807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4231799807
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3262687971
Short name T375
Test name
Test status
Simulation time 176275204 ps
CPU time 13.52 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 217760 kb
Host smart-d331d3aa-20c4-4f71-86b7-1d93627235dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262687971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3262687971
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3809494677
Short name T114
Test name
Test status
Simulation time 2281465855 ps
CPU time 163.61 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:45:54 PM PDT 24
Peak memory 214132 kb
Host smart-514edae3-d8d0-4f36-b084-313b57fecc85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809494677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3809494677
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.470292030
Short name T334
Test name
Test status
Simulation time 982665676 ps
CPU time 10.84 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 217744 kb
Host smart-986b1457-4c9e-41a3-bfcb-dc690530e306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470292030 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.470292030
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.981349428
Short name T331
Test name
Test status
Simulation time 1273175271 ps
CPU time 8.28 seconds
Started Aug 14 04:43:24 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 211100 kb
Host smart-ecf9adde-b0b8-4f3a-ab06-6e882e9c15a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981349428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.981349428
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4136738016
Short name T360
Test name
Test status
Simulation time 636404389 ps
CPU time 10.03 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:13 PM PDT 24
Peak memory 211788 kb
Host smart-43476e2b-fe7f-4961-84de-354a7ebd77d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136738016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4136738016
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1105031281
Short name T332
Test name
Test status
Simulation time 250366715 ps
CPU time 13.07 seconds
Started Aug 14 04:43:07 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 218700 kb
Host smart-44fe5299-15ff-46ae-be2a-2b34917a13c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105031281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1105031281
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.28215395
Short name T124
Test name
Test status
Simulation time 544513593 ps
CPU time 159.06 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:45:49 PM PDT 24
Peak memory 214312 kb
Host smart-b4481454-585f-44a7-a391-798747601bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.28215395
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.347047753
Short name T51
Test name
Test status
Simulation time 1739655426 ps
CPU time 8.86 seconds
Started Aug 14 04:43:08 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 217516 kb
Host smart-0f80b66d-c9fe-41cc-a13c-2f86155a98cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347047753 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.347047753
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3822299527
Short name T105
Test name
Test status
Simulation time 1031249268 ps
CPU time 9.77 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 211180 kb
Host smart-a720d0dd-4678-4f92-8c1b-2beaf62e5982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822299527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3822299527
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1370477467
Short name T102
Test name
Test status
Simulation time 3631487666 ps
CPU time 44.37 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 214480 kb
Host smart-89b9ec46-6740-4976-bbea-c61cae1aeeb0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370477467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1370477467
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.969165963
Short name T365
Test name
Test status
Simulation time 365345256 ps
CPU time 12.29 seconds
Started Aug 14 04:43:38 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 212972 kb
Host smart-1277fc4d-fc9f-4b39-bd4e-b5182767b55d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969165963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.969165963
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2781277221
Short name T367
Test name
Test status
Simulation time 241816402 ps
CPU time 82.25 seconds
Started Aug 14 04:43:08 PM PDT 24
Finished Aug 14 04:44:30 PM PDT 24
Peak memory 213696 kb
Host smart-ae6140ca-c34a-462c-b854-c6ff87c2c1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781277221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2781277221
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.577715619
Short name T339
Test name
Test status
Simulation time 748850192 ps
CPU time 8.92 seconds
Started Aug 14 04:43:08 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 216928 kb
Host smart-bd3262c4-064a-41ad-ab6b-899577a64ba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577715619 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.577715619
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3345704769
Short name T85
Test name
Test status
Simulation time 306608351 ps
CPU time 9.78 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 211196 kb
Host smart-69a04d2e-e227-42ab-9ede-0d1c6892d317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345704769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3345704769
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.99844046
Short name T93
Test name
Test status
Simulation time 6091153494 ps
CPU time 65.02 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 215420 kb
Host smart-595091db-3068-4955-8494-02d03c40c86b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99844046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.99844046
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2968046220
Short name T393
Test name
Test status
Simulation time 167511397 ps
CPU time 8.42 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 211252 kb
Host smart-84a7fd94-d788-4e30-a0fe-5b943a9e25b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968046220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2968046220
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2732497769
Short name T402
Test name
Test status
Simulation time 167550886 ps
CPU time 12.86 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 217868 kb
Host smart-4db61663-72b3-4ab2-a893-bcd95eb7936c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732497769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2732497769
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3039796896
Short name T63
Test name
Test status
Simulation time 1126404871 ps
CPU time 147.49 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 214312 kb
Host smart-3087f7fc-c018-4753-a775-650426a6267c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039796896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3039796896
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3739499265
Short name T348
Test name
Test status
Simulation time 1031588696 ps
CPU time 10.49 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 216572 kb
Host smart-40cde125-8c93-487f-996c-35c9ea6637f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739499265 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3739499265
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3148167896
Short name T109
Test name
Test status
Simulation time 1308452118 ps
CPU time 9.91 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 211516 kb
Host smart-70fe03fc-c719-45b0-939d-a72fa2885851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148167896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3148167896
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2192928349
Short name T81
Test name
Test status
Simulation time 6296311816 ps
CPU time 65.26 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 216196 kb
Host smart-68ebff71-63f8-4981-a4f2-597ef29b8172
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192928349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2192928349
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3947543971
Short name T106
Test name
Test status
Simulation time 333241339 ps
CPU time 8.06 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 211536 kb
Host smart-136cb686-0a0f-405b-8832-42e427e2846e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947543971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3947543971
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2957983086
Short name T366
Test name
Test status
Simulation time 179959038 ps
CPU time 10.86 seconds
Started Aug 14 04:43:12 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 218696 kb
Host smart-c7d837e0-3f54-4d23-8b1d-613c5e28b406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957983086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2957983086
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1055479618
Short name T343
Test name
Test status
Simulation time 769962674 ps
CPU time 156.67 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:45:59 PM PDT 24
Peak memory 214424 kb
Host smart-caa9a775-fee9-43f9-a847-7f0bf372a8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055479618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1055479618
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3451395082
Short name T394
Test name
Test status
Simulation time 275140564 ps
CPU time 10.59 seconds
Started Aug 14 04:43:12 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 216292 kb
Host smart-12ce1a15-8ee7-4efb-856f-a1763213aedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451395082 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3451395082
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.801798761
Short name T98
Test name
Test status
Simulation time 1648542289 ps
CPU time 8.33 seconds
Started Aug 14 04:43:07 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 211152 kb
Host smart-4cb5008a-4fbb-499d-aaee-b8d4f1a4f424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801798761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.801798761
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.238447147
Short name T92
Test name
Test status
Simulation time 4080535888 ps
CPU time 45.21 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 215232 kb
Host smart-8ff1f631-1842-48ec-a2bb-70cd3d6045cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238447147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.238447147
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2846795764
Short name T397
Test name
Test status
Simulation time 460123922 ps
CPU time 9.79 seconds
Started Aug 14 04:43:14 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 211668 kb
Host smart-85a0821a-89c6-447b-8002-ab696c0fe261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846795764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2846795764
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3472167727
Short name T49
Test name
Test status
Simulation time 1030716483 ps
CPU time 14.51 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 217904 kb
Host smart-61db4993-8f87-4c05-9986-7489e1451f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472167727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3472167727
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2438682701
Short name T407
Test name
Test status
Simulation time 503289479 ps
CPU time 157.07 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:45:56 PM PDT 24
Peak memory 214456 kb
Host smart-1aab7c2d-bf92-4c92-8426-84ae08965013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438682701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2438682701
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1392828114
Short name T410
Test name
Test status
Simulation time 1014542106 ps
CPU time 9.12 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 217156 kb
Host smart-813fc923-eddc-4dcc-83a2-19af2f2bf840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392828114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1392828114
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1902038803
Short name T329
Test name
Test status
Simulation time 250765097 ps
CPU time 9.87 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 211000 kb
Host smart-28a85232-0160-458f-99b8-2e8744262e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902038803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1902038803
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3093250723
Short name T364
Test name
Test status
Simulation time 2346560425 ps
CPU time 54.87 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 215284 kb
Host smart-ca993c8e-6b89-4fed-9bcd-734afbb55e53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093250723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3093250723
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.63581554
Short name T344
Test name
Test status
Simulation time 564783732 ps
CPU time 10.03 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 211420 kb
Host smart-5eb8f1b7-cf7a-4803-987d-303056e9dcd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63581554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ct
rl_same_csr_outstanding.63581554
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.218824466
Short name T342
Test name
Test status
Simulation time 257730224 ps
CPU time 13.26 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 217572 kb
Host smart-715a07ec-51af-41d2-8a9f-e6390875b0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218824466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.218824466
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3965978777
Short name T408
Test name
Test status
Simulation time 903580337 ps
CPU time 84.26 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 213764 kb
Host smart-3bbc4d1e-a711-44bd-8bf3-5deccb6fc137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965978777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3965978777
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4210515641
Short name T384
Test name
Test status
Simulation time 1271055157 ps
CPU time 8.34 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 211104 kb
Host smart-e176e6da-ebde-46f0-91ae-e550c67be433
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210515641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4210515641
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1054560346
Short name T386
Test name
Test status
Simulation time 250833671 ps
CPU time 10.33 seconds
Started Aug 14 04:43:22 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 210996 kb
Host smart-a9af8af2-304c-4e23-8590-02f84b7f6a45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054560346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1054560346
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2568206506
Short name T351
Test name
Test status
Simulation time 667717416 ps
CPU time 11.84 seconds
Started Aug 14 04:43:12 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 211280 kb
Host smart-c17d31db-8b59-43c1-8687-445cbb1cf8f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568206506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2568206506
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2953131650
Short name T29
Test name
Test status
Simulation time 271230663 ps
CPU time 11.12 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 218072 kb
Host smart-4287d27f-bc6c-40db-b12a-ec15c501c99d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953131650 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2953131650
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2484949554
Short name T323
Test name
Test status
Simulation time 1373144421 ps
CPU time 8.49 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 211144 kb
Host smart-1d5802a9-c376-4b64-800d-dac33551fa40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484949554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2484949554
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2863833615
Short name T321
Test name
Test status
Simulation time 1772645595 ps
CPU time 9.97 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:13 PM PDT 24
Peak memory 210872 kb
Host smart-a2f6bbb3-3f6e-49f6-b8d8-e16a1bab5a12
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863833615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2863833615
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.401888543
Short name T319
Test name
Test status
Simulation time 362523729 ps
CPU time 8.19 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:43:18 PM PDT 24
Peak memory 210820 kb
Host smart-b96fc951-ef71-4079-bf47-e2bddb9dca82
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401888543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
401888543
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3983193825
Short name T378
Test name
Test status
Simulation time 15840031119 ps
CPU time 63.26 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 214760 kb
Host smart-1ac53859-6bed-4f75-aa32-76ecb835cf89
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983193825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3983193825
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1639083591
Short name T349
Test name
Test status
Simulation time 269822389 ps
CPU time 13.94 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 212632 kb
Host smart-30f80c0d-d687-415e-ab87-fe5726dc3a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639083591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1639083591
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1776849304
Short name T368
Test name
Test status
Simulation time 167795665 ps
CPU time 11.09 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 217760 kb
Host smart-e3804f1e-aafe-4ec7-b260-5bd8bd280fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776849304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1776849304
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3705406167
Short name T119
Test name
Test status
Simulation time 610405536 ps
CPU time 156.68 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:45:48 PM PDT 24
Peak memory 214604 kb
Host smart-eb340213-d11f-4ba5-a901-21127a042b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705406167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3705406167
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1985771582
Short name T325
Test name
Test status
Simulation time 255035638 ps
CPU time 10.18 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 211032 kb
Host smart-a885e0f7-a680-4981-b3a0-e1966d990bdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985771582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1985771582
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2384828572
Short name T383
Test name
Test status
Simulation time 504875377 ps
CPU time 10.44 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 210984 kb
Host smart-61da5b13-be13-436b-9fb3-10ef39ce84ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384828572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2384828572
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2027148206
Short name T403
Test name
Test status
Simulation time 1034722741 ps
CPU time 18.53 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 210904 kb
Host smart-5b67e181-c66f-46a1-950b-fe5d41c1ef9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027148206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2027148206
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2819871998
Short name T324
Test name
Test status
Simulation time 504409309 ps
CPU time 10.1 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 214016 kb
Host smart-205d9bc4-4cff-4b27-aefa-1bf13bf17803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819871998 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2819871998
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2450296551
Short name T377
Test name
Test status
Simulation time 167543416 ps
CPU time 8.25 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 210932 kb
Host smart-c44c9cce-20a5-4460-abc8-6b47505f159b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450296551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2450296551
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3714272672
Short name T389
Test name
Test status
Simulation time 291429557 ps
CPU time 10.16 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 210852 kb
Host smart-cd95f46d-fe73-4e9b-8c63-779460ae6526
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714272672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3714272672
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3752569195
Short name T350
Test name
Test status
Simulation time 175247286 ps
CPU time 7.88 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 210924 kb
Host smart-08f88815-b0a5-4a11-afc2-9d2e3dade9f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752569195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3752569195
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3504324678
Short name T100
Test name
Test status
Simulation time 18012264309 ps
CPU time 62.68 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 214128 kb
Host smart-9d508111-1b4d-4581-ac9f-b36d449e25ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504324678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3504324678
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3193638277
Short name T103
Test name
Test status
Simulation time 168489346 ps
CPU time 8.37 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 211800 kb
Host smart-4f6b6964-0852-4fd1-8b73-8fc284849c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193638277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3193638277
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.272263743
Short name T347
Test name
Test status
Simulation time 255847610 ps
CPU time 13.36 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 217832 kb
Host smart-a9ce3dd9-1f87-4a33-b964-00901d6f0729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272263743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.272263743
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2288603294
Short name T64
Test name
Test status
Simulation time 444314329 ps
CPU time 79.36 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 214184 kb
Host smart-3cf09fc4-7358-4a54-bd5e-98f2e79843bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288603294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2288603294
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2730719864
Short name T74
Test name
Test status
Simulation time 1035374032 ps
CPU time 10.08 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 211292 kb
Host smart-87e7acca-4780-4838-8ff1-7c19f42bfc1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730719864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2730719864
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3842765535
Short name T87
Test name
Test status
Simulation time 1029062787 ps
CPU time 10.15 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 211016 kb
Host smart-2ba64b17-6333-4da6-b77e-1d8fb194b1bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842765535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3842765535
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2704023349
Short name T391
Test name
Test status
Simulation time 1673984218 ps
CPU time 17.42 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 212520 kb
Host smart-b5547f7d-1d8d-41f4-9af9-67089e1a3b87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704023349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2704023349
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1950061158
Short name T405
Test name
Test status
Simulation time 935405643 ps
CPU time 11.32 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 217956 kb
Host smart-7bf3e220-e178-4b91-ac1d-f15a220e17db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950061158 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1950061158
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1893985167
Short name T86
Test name
Test status
Simulation time 261433697 ps
CPU time 9.76 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 211328 kb
Host smart-4587e743-11a8-426b-bc7e-75e6c5ad95cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893985167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1893985167
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3100557241
Short name T320
Test name
Test status
Simulation time 981635666 ps
CPU time 15.26 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 210872 kb
Host smart-458856cc-bb7f-4000-ab67-f170d53b3888
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100557241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3100557241
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2691782123
Short name T354
Test name
Test status
Simulation time 660647201 ps
CPU time 8.32 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 210880 kb
Host smart-1d270b39-0b64-4d56-b8b3-138b97c4df47
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691782123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2691782123
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.65405687
Short name T113
Test name
Test status
Simulation time 2873024113 ps
CPU time 38.44 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 214252 kb
Host smart-48084a48-1a09-4eee-9486-ea591084fae1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65405687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pass
thru_mem_tl_intg_err.65405687
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.312486073
Short name T382
Test name
Test status
Simulation time 251078988 ps
CPU time 10.14 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:13 PM PDT 24
Peak memory 211488 kb
Host smart-1d9c21df-2601-496f-a2b0-117049dea849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312486073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.312486073
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2851193225
Short name T355
Test name
Test status
Simulation time 168755044 ps
CPU time 11.17 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 217652 kb
Host smart-ddde6b46-3cd6-4d06-a201-bf1d5ceb5069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851193225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2851193225
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2347244603
Short name T123
Test name
Test status
Simulation time 3397072668 ps
CPU time 155.76 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 214556 kb
Host smart-4a94f38c-6726-4262-a793-c397e7e2e38b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347244603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2347244603
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3231423893
Short name T330
Test name
Test status
Simulation time 529056096 ps
CPU time 10.58 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 215124 kb
Host smart-eb060102-08b8-4b3e-aec8-92aa33addcd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231423893 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3231423893
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2902876425
Short name T326
Test name
Test status
Simulation time 1542832673 ps
CPU time 10.09 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 210920 kb
Host smart-a36538d8-1add-4049-b2b0-c158a22e88da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902876425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2902876425
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2610231627
Short name T97
Test name
Test status
Simulation time 1027300810 ps
CPU time 44.79 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 214532 kb
Host smart-29dd9d65-9556-4104-b724-5fc3e555be37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610231627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2610231627
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2664886371
Short name T406
Test name
Test status
Simulation time 693836746 ps
CPU time 12.13 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 212940 kb
Host smart-5ac65f8d-3c81-4a67-9a81-8b1c73b7d413
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664886371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2664886371
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.319588759
Short name T26
Test name
Test status
Simulation time 167309522 ps
CPU time 11.67 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 217680 kb
Host smart-cd744560-7bd4-4112-bf35-70a089d57714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319588759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.319588759
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1753128885
Short name T121
Test name
Test status
Simulation time 937670038 ps
CPU time 81.93 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 214052 kb
Host smart-faa60fa1-30f9-4080-a07a-8e418010bcab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753128885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1753128885
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.887365494
Short name T358
Test name
Test status
Simulation time 718252319 ps
CPU time 9.03 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:10 PM PDT 24
Peak memory 216924 kb
Host smart-2ca4dbd7-0ec7-4e88-ac35-d7d00e089f46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887365494 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.887365494
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.103358100
Short name T353
Test name
Test status
Simulation time 260716125 ps
CPU time 9.82 seconds
Started Aug 14 04:43:06 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 211296 kb
Host smart-6b54e50f-4081-4a99-a57b-e06a40a6d096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103358100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.103358100
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1240567307
Short name T390
Test name
Test status
Simulation time 4079042155 ps
CPU time 44.69 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 214460 kb
Host smart-c14c0f4d-ceea-45a3-8f7c-e858b111f437
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240567307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1240567307
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1607994791
Short name T75
Test name
Test status
Simulation time 986631038 ps
CPU time 10.49 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:09 PM PDT 24
Peak memory 211868 kb
Host smart-41ad9229-2e71-4d10-b154-03e312cde50c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607994791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1607994791
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3804873761
Short name T373
Test name
Test status
Simulation time 250545868 ps
CPU time 13.48 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 217768 kb
Host smart-f0e3ac5d-92b0-4faf-a99a-427f902dafd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804873761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3804873761
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1145852157
Short name T399
Test name
Test status
Simulation time 181870268 ps
CPU time 9.54 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:43:22 PM PDT 24
Peak memory 217864 kb
Host smart-55a66d57-7bb9-4235-8cc1-5b826daa1bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145852157 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1145852157
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3343313725
Short name T99
Test name
Test status
Simulation time 1127758042 ps
CPU time 9.9 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 211264 kb
Host smart-752212af-ad4d-44c3-b325-75d025e6cc54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343313725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3343313725
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.377287355
Short name T95
Test name
Test status
Simulation time 7243506910 ps
CPU time 45.16 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 215168 kb
Host smart-2266d670-fc3d-4833-9eb9-38055953ce9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377287355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.377287355
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1340657251
Short name T374
Test name
Test status
Simulation time 689447045 ps
CPU time 8.26 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 211540 kb
Host smart-86ae5bab-3361-4597-ad22-93592e2d2570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340657251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1340657251
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780860296
Short name T409
Test name
Test status
Simulation time 509243062 ps
CPU time 12.89 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 217492 kb
Host smart-514d6b33-1ffc-453e-8298-92d52e98d54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780860296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1780860296
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.21978521
Short name T118
Test name
Test status
Simulation time 408834719 ps
CPU time 157.29 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 214436 kb
Host smart-aa2da1c7-f411-4f60-8c9c-42c0316296d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg
_err.21978521
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.758334057
Short name T80
Test name
Test status
Simulation time 4094912352 ps
CPU time 15.15 seconds
Started Aug 14 04:43:11 PM PDT 24
Finished Aug 14 04:43:26 PM PDT 24
Peak memory 214504 kb
Host smart-39727d49-a7fe-4563-b547-9a544a77caa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758334057 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.758334057
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.629729655
Short name T94
Test name
Test status
Simulation time 1026930108 ps
CPU time 9.87 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 211012 kb
Host smart-1536e39e-176b-4392-b66b-1818c22afdc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629729655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.629729655
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1737721362
Short name T322
Test name
Test status
Simulation time 691618549 ps
CPU time 38.28 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:43:30 PM PDT 24
Peak memory 214120 kb
Host smart-b9a953b1-b3a7-4a24-9f05-1c1550479bd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737721362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1737721362
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.428011483
Short name T107
Test name
Test status
Simulation time 254262341 ps
CPU time 9.95 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:16 PM PDT 24
Peak memory 211564 kb
Host smart-1c9bd078-4082-46d1-908e-bb63c4e0c879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428011483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.428011483
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.684385333
Short name T53
Test name
Test status
Simulation time 990110796 ps
CPU time 12.75 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 217608 kb
Host smart-517a0bf0-6c30-4b11-a870-3dafd09787e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684385333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.684385333
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1934076459
Short name T333
Test name
Test status
Simulation time 2582390149 ps
CPU time 11.02 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 217408 kb
Host smart-a72ef3c6-c185-40fd-9cd4-77e73bf5e7c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934076459 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1934076459
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3778728353
Short name T84
Test name
Test status
Simulation time 249248922 ps
CPU time 10.23 seconds
Started Aug 14 04:43:17 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 211312 kb
Host smart-5cf8a1e6-ab3b-4b7e-9b42-f6661ccb99eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778728353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3778728353
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3626688913
Short name T381
Test name
Test status
Simulation time 1036045074 ps
CPU time 58.27 seconds
Started Aug 14 04:43:13 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 215160 kb
Host smart-3a738485-473b-4960-9653-5c315998fe66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626688913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3626688913
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1066149129
Short name T400
Test name
Test status
Simulation time 688917927 ps
CPU time 8.27 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:43:19 PM PDT 24
Peak memory 211768 kb
Host smart-bdc07aec-47aa-435f-9963-f5646aaaa25e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066149129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1066149129
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2577189636
Short name T341
Test name
Test status
Simulation time 636343000 ps
CPU time 13.01 seconds
Started Aug 14 04:43:12 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 218936 kb
Host smart-2012338b-4762-4d33-b4ac-a57a8abc9ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577189636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2577189636
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.804286703
Short name T387
Test name
Test status
Simulation time 233354927 ps
CPU time 81.87 seconds
Started Aug 14 04:43:15 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 214192 kb
Host smart-065556cb-f25d-42e0-850c-995c4083c654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804286703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.804286703
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3004016850
Short name T37
Test name
Test status
Simulation time 252688907 ps
CPU time 10.31 seconds
Started Aug 14 05:22:50 PM PDT 24
Finished Aug 14 05:23:01 PM PDT 24
Peak memory 218480 kb
Host smart-f8524edf-fc66-4f23-8666-5ad6c2916f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004016850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3004016850
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.278507027
Short name T54
Test name
Test status
Simulation time 2541009143 ps
CPU time 145.7 seconds
Started Aug 14 05:22:46 PM PDT 24
Finished Aug 14 05:25:11 PM PDT 24
Peak memory 219632 kb
Host smart-9a885c4f-bf40-4bce-a3ca-4e1f5600a78d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278507027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.278507027
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1746458237
Short name T259
Test name
Test status
Simulation time 500326318 ps
CPU time 22.89 seconds
Started Aug 14 05:22:46 PM PDT 24
Finished Aug 14 05:23:09 PM PDT 24
Peak memory 219404 kb
Host smart-376c4d19-1ac5-4b37-9291-2079b4b39bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746458237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1746458237
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1990023695
Short name T290
Test name
Test status
Simulation time 526653032 ps
CPU time 12.04 seconds
Started Aug 14 05:22:45 PM PDT 24
Finished Aug 14 05:22:58 PM PDT 24
Peak memory 219360 kb
Host smart-a83f18c4-d894-4475-b13d-dff63ba21e02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990023695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1990023695
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2281056347
Short name T30
Test name
Test status
Simulation time 1894687463 ps
CPU time 227.51 seconds
Started Aug 14 05:22:52 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 238712 kb
Host smart-965cc954-20f5-463f-90b3-aba47082064e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281056347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2281056347
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3853632038
Short name T136
Test name
Test status
Simulation time 1070172943 ps
CPU time 11.67 seconds
Started Aug 14 05:22:45 PM PDT 24
Finished Aug 14 05:22:57 PM PDT 24
Peak memory 219276 kb
Host smart-e75c885e-4a78-4bd0-8aa4-4d5c12b7c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853632038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3853632038
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2083969859
Short name T253
Test name
Test status
Simulation time 511694617 ps
CPU time 32.99 seconds
Started Aug 14 05:22:45 PM PDT 24
Finished Aug 14 05:23:18 PM PDT 24
Peak memory 219368 kb
Host smart-5224d42d-dca8-4500-93d3-0353314fe8b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083969859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2083969859
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.504670151
Short name T311
Test name
Test status
Simulation time 258072109 ps
CPU time 10.19 seconds
Started Aug 14 05:23:01 PM PDT 24
Finished Aug 14 05:23:11 PM PDT 24
Peak memory 218220 kb
Host smart-83074a2a-df25-468f-942c-4835059fbdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504670151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.504670151
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4096882663
Short name T144
Test name
Test status
Simulation time 2969549961 ps
CPU time 215.18 seconds
Started Aug 14 05:22:51 PM PDT 24
Finished Aug 14 05:26:27 PM PDT 24
Peak memory 242052 kb
Host smart-676f9fbb-31b7-4f8b-8de0-329413b6d0fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096882663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4096882663
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.785899910
Short name T260
Test name
Test status
Simulation time 510030438 ps
CPU time 22.7 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:23:23 PM PDT 24
Peak memory 219424 kb
Host smart-f4318d60-f7d7-429a-9028-d9919a8a2b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785899910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.785899910
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4214833665
Short name T21
Test name
Test status
Simulation time 221868899 ps
CPU time 116.86 seconds
Started Aug 14 05:22:59 PM PDT 24
Finished Aug 14 05:24:56 PM PDT 24
Peak memory 239300 kb
Host smart-c253ebcd-b071-4aad-b41c-a0938fc38422
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214833665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4214833665
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2889932025
Short name T182
Test name
Test status
Simulation time 177670422 ps
CPU time 10.19 seconds
Started Aug 14 05:22:52 PM PDT 24
Finished Aug 14 05:23:02 PM PDT 24
Peak memory 219384 kb
Host smart-6fa2a74d-ff99-44d2-835e-fbf8225d8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889932025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2889932025
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2031407575
Short name T203
Test name
Test status
Simulation time 257640319 ps
CPU time 10.15 seconds
Started Aug 14 05:23:47 PM PDT 24
Finished Aug 14 05:23:58 PM PDT 24
Peak memory 218488 kb
Host smart-e3406965-e842-4bae-953f-0a00495d3f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031407575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2031407575
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4155638232
Short name T139
Test name
Test status
Simulation time 15860709791 ps
CPU time 289.58 seconds
Started Aug 14 05:23:40 PM PDT 24
Finished Aug 14 05:28:30 PM PDT 24
Peak memory 234108 kb
Host smart-a55e6295-578a-4b3b-a7c3-384e4998d8ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155638232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4155638232
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2221583168
Short name T281
Test name
Test status
Simulation time 1976729546 ps
CPU time 22.56 seconds
Started Aug 14 05:23:40 PM PDT 24
Finished Aug 14 05:24:03 PM PDT 24
Peak memory 219432 kb
Host smart-a804a9bb-631c-425a-943c-be7014a58ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221583168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2221583168
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4162355074
Short name T315
Test name
Test status
Simulation time 181854093 ps
CPU time 10.37 seconds
Started Aug 14 05:23:40 PM PDT 24
Finished Aug 14 05:23:50 PM PDT 24
Peak memory 219400 kb
Host smart-dd2a8616-b924-45b8-a4ae-af0121045c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162355074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4162355074
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2472427753
Short name T55
Test name
Test status
Simulation time 547191539 ps
CPU time 28.46 seconds
Started Aug 14 05:23:39 PM PDT 24
Finished Aug 14 05:24:08 PM PDT 24
Peak memory 219304 kb
Host smart-e25e46b3-7716-4183-9bad-32894740cceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472427753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2472427753
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3479747800
Short name T78
Test name
Test status
Simulation time 607504723 ps
CPU time 9.74 seconds
Started Aug 14 05:23:54 PM PDT 24
Finished Aug 14 05:24:04 PM PDT 24
Peak memory 218452 kb
Host smart-8fccadf0-111c-4959-9cb2-ec084ca9a319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479747800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3479747800
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3492606972
Short name T271
Test name
Test status
Simulation time 54655451397 ps
CPU time 282.53 seconds
Started Aug 14 05:23:54 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 224860 kb
Host smart-335b8567-e3ce-4eab-a204-75789e126dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492606972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3492606972
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1111678117
Short name T318
Test name
Test status
Simulation time 1033383511 ps
CPU time 19.08 seconds
Started Aug 14 05:23:47 PM PDT 24
Finished Aug 14 05:24:06 PM PDT 24
Peak memory 219364 kb
Host smart-f0de0200-6160-4029-9180-3a6ca7930e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111678117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1111678117
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1270760519
Short name T176
Test name
Test status
Simulation time 261151695 ps
CPU time 12.13 seconds
Started Aug 14 05:23:46 PM PDT 24
Finished Aug 14 05:23:59 PM PDT 24
Peak memory 219280 kb
Host smart-ce423c92-ed08-4473-9283-a4b3105b3f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270760519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1270760519
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4085810971
Short name T265
Test name
Test status
Simulation time 4978611104 ps
CPU time 47.62 seconds
Started Aug 14 05:23:46 PM PDT 24
Finished Aug 14 05:24:34 PM PDT 24
Peak memory 219496 kb
Host smart-2ccab07f-a9fe-41e3-ad2f-60fb9b3de991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085810971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4085810971
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1947808566
Short name T252
Test name
Test status
Simulation time 258705749 ps
CPU time 9.81 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:05 PM PDT 24
Peak memory 218384 kb
Host smart-dcf9fff2-7fc0-4816-9771-f61d2f7442d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947808566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1947808566
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1241424900
Short name T224
Test name
Test status
Simulation time 278224630582 ps
CPU time 295.82 seconds
Started Aug 14 05:23:47 PM PDT 24
Finished Aug 14 05:28:43 PM PDT 24
Peak memory 225204 kb
Host smart-c78609d8-c9d1-47f2-9243-52630cb98268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241424900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1241424900
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2485011947
Short name T187
Test name
Test status
Simulation time 1320949791 ps
CPU time 19.43 seconds
Started Aug 14 05:23:50 PM PDT 24
Finished Aug 14 05:24:09 PM PDT 24
Peak memory 219420 kb
Host smart-f44d15a5-a442-409e-9370-5a58266b7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485011947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2485011947
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3225070870
Short name T134
Test name
Test status
Simulation time 524800957 ps
CPU time 12.3 seconds
Started Aug 14 05:23:48 PM PDT 24
Finished Aug 14 05:24:00 PM PDT 24
Peak memory 219272 kb
Host smart-ad8fbda8-1f09-4629-9661-92314c18c255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225070870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3225070870
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.693181766
Short name T240
Test name
Test status
Simulation time 1142363840 ps
CPU time 21.99 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:17 PM PDT 24
Peak memory 219176 kb
Host smart-0f060466-de8d-4665-9316-12514282597c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693181766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.693181766
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1749247305
Short name T206
Test name
Test status
Simulation time 1030170078 ps
CPU time 10.27 seconds
Started Aug 14 05:23:46 PM PDT 24
Finished Aug 14 05:23:57 PM PDT 24
Peak memory 218444 kb
Host smart-94c75a3b-c8df-48db-a1dc-ff9b93bc97a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749247305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1749247305
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.378991470
Short name T196
Test name
Test status
Simulation time 13300980912 ps
CPU time 168.77 seconds
Started Aug 14 05:23:47 PM PDT 24
Finished Aug 14 05:26:36 PM PDT 24
Peak memory 234032 kb
Host smart-5beafe44-90c5-428a-a9fe-91c3400dba72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378991470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.378991470
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1876399432
Short name T184
Test name
Test status
Simulation time 496610840 ps
CPU time 22.82 seconds
Started Aug 14 05:23:46 PM PDT 24
Finished Aug 14 05:24:09 PM PDT 24
Peak memory 219588 kb
Host smart-dc04121c-b08a-41ec-9f74-054e91d7bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876399432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1876399432
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3406235704
Short name T209
Test name
Test status
Simulation time 361168092 ps
CPU time 10.57 seconds
Started Aug 14 05:23:48 PM PDT 24
Finished Aug 14 05:23:58 PM PDT 24
Peak memory 219336 kb
Host smart-61973704-f65e-4fd2-8731-ac95276b12a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406235704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3406235704
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.481191228
Short name T222
Test name
Test status
Simulation time 1076535479 ps
CPU time 31.3 seconds
Started Aug 14 05:23:47 PM PDT 24
Finished Aug 14 05:24:19 PM PDT 24
Peak memory 219364 kb
Host smart-5f8f4ee1-77ce-4796-819f-f077ec97e144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481191228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.481191228
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.48458278
Short name T282
Test name
Test status
Simulation time 612387604 ps
CPU time 8.26 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:04 PM PDT 24
Peak memory 218212 kb
Host smart-0af215fe-173f-4f93-b8fe-09164ace36c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48458278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.48458278
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4219248395
Short name T166
Test name
Test status
Simulation time 9097140221 ps
CPU time 325 seconds
Started Aug 14 05:23:56 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 240752 kb
Host smart-15cd41b4-48a6-438a-97a0-a9f33bc49166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219248395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4219248395
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1717551253
Short name T38
Test name
Test status
Simulation time 637456216 ps
CPU time 18.9 seconds
Started Aug 14 05:23:59 PM PDT 24
Finished Aug 14 05:24:18 PM PDT 24
Peak memory 219396 kb
Host smart-42fde243-5c02-4059-9d38-ee7e32664b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717551253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1717551253
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1252187987
Short name T32
Test name
Test status
Simulation time 266250780 ps
CPU time 12.7 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:08 PM PDT 24
Peak memory 219400 kb
Host smart-4a527c29-a792-43e6-a2a3-ce1f58c2943c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252187987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1252187987
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3009000994
Short name T297
Test name
Test status
Simulation time 1458500114 ps
CPU time 34.09 seconds
Started Aug 14 05:23:57 PM PDT 24
Finished Aug 14 05:24:31 PM PDT 24
Peak memory 219320 kb
Host smart-80d587e4-f848-4b32-8f70-285a23dfa4c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009000994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3009000994
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3683176802
Short name T250
Test name
Test status
Simulation time 1019828256 ps
CPU time 14.74 seconds
Started Aug 14 05:24:03 PM PDT 24
Finished Aug 14 05:24:17 PM PDT 24
Peak memory 218300 kb
Host smart-c2b366e7-017f-4cf1-af36-2b1e45493fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683176802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3683176802
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.934952099
Short name T236
Test name
Test status
Simulation time 5406329213 ps
CPU time 129.34 seconds
Started Aug 14 05:23:56 PM PDT 24
Finished Aug 14 05:26:05 PM PDT 24
Peak memory 238088 kb
Host smart-0d548124-3fea-49a3-97ac-9eb5d5843cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934952099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.934952099
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1565098253
Short name T183
Test name
Test status
Simulation time 1012681878 ps
CPU time 22.72 seconds
Started Aug 14 05:23:58 PM PDT 24
Finished Aug 14 05:24:20 PM PDT 24
Peak memory 219404 kb
Host smart-d8978168-7272-4291-94f6-a1763bad14ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565098253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1565098253
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1618734219
Short name T251
Test name
Test status
Simulation time 267573583 ps
CPU time 12.19 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:07 PM PDT 24
Peak memory 219352 kb
Host smart-301898d0-48ad-40f3-bb5e-3d714e01ad7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618734219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1618734219
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2217381529
Short name T90
Test name
Test status
Simulation time 1056636786 ps
CPU time 49.88 seconds
Started Aug 14 05:23:55 PM PDT 24
Finished Aug 14 05:24:45 PM PDT 24
Peak memory 219380 kb
Host smart-718c4a5a-cf41-49e7-baef-1d562b690486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217381529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2217381529
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.281692260
Short name T161
Test name
Test status
Simulation time 508427581 ps
CPU time 10.45 seconds
Started Aug 14 05:24:05 PM PDT 24
Finished Aug 14 05:24:16 PM PDT 24
Peak memory 218572 kb
Host smart-db511d6f-a480-4fdd-aa82-0e1345091722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281692260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.281692260
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3375306151
Short name T189
Test name
Test status
Simulation time 2417917707 ps
CPU time 183 seconds
Started Aug 14 05:24:04 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 236480 kb
Host smart-9e219452-9fc0-48f7-919b-6d9721d7e833
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375306151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3375306151
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.935880790
Short name T60
Test name
Test status
Simulation time 1773973498 ps
CPU time 23.18 seconds
Started Aug 14 05:24:07 PM PDT 24
Finished Aug 14 05:24:30 PM PDT 24
Peak memory 219348 kb
Host smart-f7c7a626-904d-42f6-8266-ea7ecf54a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935880790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.935880790
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2285429430
Short name T180
Test name
Test status
Simulation time 355858090 ps
CPU time 10.24 seconds
Started Aug 14 05:24:04 PM PDT 24
Finished Aug 14 05:24:15 PM PDT 24
Peak memory 219312 kb
Host smart-bacb412d-494e-4b52-96fd-f50b347ec9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285429430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2285429430
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.895751904
Short name T254
Test name
Test status
Simulation time 1407221513 ps
CPU time 44.1 seconds
Started Aug 14 05:24:07 PM PDT 24
Finished Aug 14 05:24:51 PM PDT 24
Peak memory 219264 kb
Host smart-317f8c22-fbf7-4d56-9b42-53ee47bed9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895751904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.895751904
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3967731129
Short name T45
Test name
Test status
Simulation time 1500405275 ps
CPU time 19.37 seconds
Started Aug 14 05:24:03 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 219368 kb
Host smart-6422cab8-93e4-43a2-b931-7382dadf9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967731129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3967731129
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.734707290
Short name T313
Test name
Test status
Simulation time 185616922 ps
CPU time 10.89 seconds
Started Aug 14 05:24:05 PM PDT 24
Finished Aug 14 05:24:16 PM PDT 24
Peak memory 219364 kb
Host smart-e6cf0123-df69-4a37-822c-371c9c61307e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734707290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.734707290
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1997733616
Short name T170
Test name
Test status
Simulation time 195492174 ps
CPU time 11.14 seconds
Started Aug 14 05:24:09 PM PDT 24
Finished Aug 14 05:24:20 PM PDT 24
Peak memory 219400 kb
Host smart-37359e65-f31a-4e9e-9e64-f1af0d75fd8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997733616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1997733616
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.407213909
Short name T310
Test name
Test status
Simulation time 339652619 ps
CPU time 8.32 seconds
Started Aug 14 05:24:13 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 218456 kb
Host smart-d55e87d2-4e3e-479a-af9e-5ec6cde5a1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407213909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.407213909
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1201590006
Short name T235
Test name
Test status
Simulation time 2579109168 ps
CPU time 192.48 seconds
Started Aug 14 05:24:02 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 228304 kb
Host smart-3f841f97-f06c-410b-a964-21a203a42294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201590006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1201590006
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4223905682
Short name T215
Test name
Test status
Simulation time 1321074385 ps
CPU time 19.18 seconds
Started Aug 14 05:24:03 PM PDT 24
Finished Aug 14 05:24:22 PM PDT 24
Peak memory 219428 kb
Host smart-b947f2fc-b552-45e8-b035-fbe56a240c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223905682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4223905682
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1437009177
Short name T200
Test name
Test status
Simulation time 264234347 ps
CPU time 12.29 seconds
Started Aug 14 05:24:03 PM PDT 24
Finished Aug 14 05:24:15 PM PDT 24
Peak memory 219384 kb
Host smart-55721be8-3a49-4370-b86c-f00c24e40362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437009177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1437009177
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.157932422
Short name T59
Test name
Test status
Simulation time 3989641455 ps
CPU time 50.67 seconds
Started Aug 14 05:24:03 PM PDT 24
Finished Aug 14 05:24:53 PM PDT 24
Peak memory 219524 kb
Host smart-b2503587-9c93-485c-bf18-2505eeb58c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157932422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.157932422
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1751556668
Short name T142
Test name
Test status
Simulation time 689206729 ps
CPU time 8.02 seconds
Started Aug 14 05:24:12 PM PDT 24
Finished Aug 14 05:24:21 PM PDT 24
Peak memory 218444 kb
Host smart-2d8eadf8-23a1-4ba2-8869-d5f86a8c474b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751556668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1751556668
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1804295946
Short name T256
Test name
Test status
Simulation time 6060305048 ps
CPU time 329.16 seconds
Started Aug 14 05:24:10 PM PDT 24
Finished Aug 14 05:29:40 PM PDT 24
Peak memory 235336 kb
Host smart-e372e86e-58af-4f51-a2a5-a5f6853cf117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804295946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1804295946
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.32883722
Short name T312
Test name
Test status
Simulation time 508271815 ps
CPU time 22.32 seconds
Started Aug 14 05:24:12 PM PDT 24
Finished Aug 14 05:24:35 PM PDT 24
Peak memory 219408 kb
Host smart-4bc6dba9-a6cb-410f-a053-de333fe2b72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32883722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.32883722
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4068133303
Short name T263
Test name
Test status
Simulation time 1568508107 ps
CPU time 10.57 seconds
Started Aug 14 05:24:13 PM PDT 24
Finished Aug 14 05:24:24 PM PDT 24
Peak memory 219376 kb
Host smart-98290043-b64d-4ecb-b311-2fa453e4b472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068133303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4068133303
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1262727075
Short name T218
Test name
Test status
Simulation time 2202217645 ps
CPU time 27.12 seconds
Started Aug 14 05:24:14 PM PDT 24
Finished Aug 14 05:24:41 PM PDT 24
Peak memory 219448 kb
Host smart-7dcf88b2-64ff-4748-9dc6-8d99bcdcd3cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262727075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1262727075
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2369367995
Short name T267
Test name
Test status
Simulation time 180773764 ps
CPU time 10.71 seconds
Started Aug 14 05:23:03 PM PDT 24
Finished Aug 14 05:23:13 PM PDT 24
Peak memory 219152 kb
Host smart-15684216-45a4-4868-8d8b-f0f8fb1cdd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369367995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2369367995
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3963466828
Short name T31
Test name
Test status
Simulation time 1210881380 ps
CPU time 119.75 seconds
Started Aug 14 05:23:01 PM PDT 24
Finished Aug 14 05:25:01 PM PDT 24
Peak memory 233332 kb
Host smart-18c867bd-e6d4-41ce-bc47-669a6b8538fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963466828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3963466828
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1632763653
Short name T223
Test name
Test status
Simulation time 1418933897 ps
CPU time 12.53 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:23:12 PM PDT 24
Peak memory 219356 kb
Host smart-d64de82c-a883-488c-a73b-c4c3e8b7cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632763653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1632763653
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3383874782
Short name T229
Test name
Test status
Simulation time 332554805 ps
CPU time 8.68 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:28 PM PDT 24
Peak memory 218436 kb
Host smart-4582e947-504c-434b-80b6-88870eff6895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383874782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3383874782
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2542717144
Short name T292
Test name
Test status
Simulation time 27363700983 ps
CPU time 375.74 seconds
Started Aug 14 05:24:11 PM PDT 24
Finished Aug 14 05:30:27 PM PDT 24
Peak memory 219684 kb
Host smart-42ecc516-c913-4af0-817b-21e4f00cb660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542717144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2542717144
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.926250151
Short name T28
Test name
Test status
Simulation time 2150192931 ps
CPU time 23.23 seconds
Started Aug 14 05:24:11 PM PDT 24
Finished Aug 14 05:24:34 PM PDT 24
Peak memory 219488 kb
Host smart-8d3f1274-f3f2-447b-a8b0-dd5c033ac43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926250151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.926250151
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.512722652
Short name T226
Test name
Test status
Simulation time 1448616657 ps
CPU time 10.65 seconds
Started Aug 14 05:24:10 PM PDT 24
Finished Aug 14 05:24:21 PM PDT 24
Peak memory 219348 kb
Host smart-de013488-6273-4d70-bbab-85dfce4883d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512722652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.512722652
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2997382375
Short name T156
Test name
Test status
Simulation time 268629910 ps
CPU time 15.9 seconds
Started Aug 14 05:24:10 PM PDT 24
Finished Aug 14 05:24:26 PM PDT 24
Peak memory 219324 kb
Host smart-70a98a95-9b84-4a34-bdea-240e89aba10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997382375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2997382375
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1362544291
Short name T268
Test name
Test status
Simulation time 172793471 ps
CPU time 8.36 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:28 PM PDT 24
Peak memory 217928 kb
Host smart-fc093713-92d9-4b7b-a2b4-dee0c37f49b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362544291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1362544291
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3306459806
Short name T68
Test name
Test status
Simulation time 2783124260 ps
CPU time 139.23 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:26:41 PM PDT 24
Peak memory 229208 kb
Host smart-4b605947-4211-44f2-851d-6fc8d35d6be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306459806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3306459806
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3374610583
Short name T217
Test name
Test status
Simulation time 2145165502 ps
CPU time 22.36 seconds
Started Aug 14 05:24:20 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 219428 kb
Host smart-9090fb29-7311-4442-99fe-231215a6d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374610583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3374610583
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3177157117
Short name T177
Test name
Test status
Simulation time 392932325 ps
CPU time 10.6 seconds
Started Aug 14 05:24:20 PM PDT 24
Finished Aug 14 05:24:31 PM PDT 24
Peak memory 219372 kb
Host smart-7aeed0e6-af2b-4e8c-a801-336d252895a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177157117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3177157117
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.771560649
Short name T304
Test name
Test status
Simulation time 1363795193 ps
CPU time 26.61 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:46 PM PDT 24
Peak memory 219364 kb
Host smart-36bda334-9d7b-4ed8-959a-8181835b725f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771560649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.771560649
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.465819305
Short name T190
Test name
Test status
Simulation time 690008318 ps
CPU time 8.48 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:24:31 PM PDT 24
Peak memory 218432 kb
Host smart-fbf75374-5a4f-4755-9923-8c39e53c3919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465819305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.465819305
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.785066007
Short name T225
Test name
Test status
Simulation time 3491299343 ps
CPU time 177.02 seconds
Started Aug 14 05:24:18 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 233980 kb
Host smart-3c038ee8-86b4-4e15-b1e2-7d08e7775186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785066007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.785066007
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.533402200
Short name T295
Test name
Test status
Simulation time 2360992978 ps
CPU time 20.02 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:24:42 PM PDT 24
Peak memory 219380 kb
Host smart-fb3b8a2a-e274-4ce2-9217-174ac67d6bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533402200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.533402200
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1767772312
Short name T212
Test name
Test status
Simulation time 178306523 ps
CPU time 10.81 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:30 PM PDT 24
Peak memory 219348 kb
Host smart-94a5082b-0d74-4816-ae5e-14a3ac912ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767772312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1767772312
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2493186144
Short name T135
Test name
Test status
Simulation time 3052295152 ps
CPU time 41.92 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:25:01 PM PDT 24
Peak memory 219456 kb
Host smart-2f3476b3-741c-4053-81b7-2bb4181cc3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493186144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2493186144
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1641935384
Short name T243
Test name
Test status
Simulation time 1030907031 ps
CPU time 14.73 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:34 PM PDT 24
Peak memory 217912 kb
Host smart-5057f0fd-3c67-419a-99fd-fa7db7163e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641935384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1641935384
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3213691765
Short name T275
Test name
Test status
Simulation time 13184479848 ps
CPU time 193.56 seconds
Started Aug 14 05:24:18 PM PDT 24
Finished Aug 14 05:27:31 PM PDT 24
Peak memory 234092 kb
Host smart-140bfd33-c3de-4eac-811d-d3903dbf0b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213691765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3213691765
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.332776161
Short name T211
Test name
Test status
Simulation time 343434665 ps
CPU time 19.3 seconds
Started Aug 14 05:24:19 PM PDT 24
Finished Aug 14 05:24:39 PM PDT 24
Peak memory 219368 kb
Host smart-d822df6a-bf8f-4ac5-97d3-7a8dbfb1964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332776161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.332776161
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2102578039
Short name T111
Test name
Test status
Simulation time 342309991 ps
CPU time 11.03 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:24:33 PM PDT 24
Peak memory 219232 kb
Host smart-1c0ad9b9-0bf1-4def-a4df-8bc6cf08d982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102578039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2102578039
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.675069939
Short name T138
Test name
Test status
Simulation time 7470398532 ps
CPU time 30.24 seconds
Started Aug 14 05:24:21 PM PDT 24
Finished Aug 14 05:24:51 PM PDT 24
Peak memory 219468 kb
Host smart-8ae209d8-4fe1-4028-afe0-591447f42b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675069939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.675069939
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1230903288
Short name T192
Test name
Test status
Simulation time 172791416 ps
CPU time 8.13 seconds
Started Aug 14 05:24:28 PM PDT 24
Finished Aug 14 05:24:36 PM PDT 24
Peak memory 218504 kb
Host smart-df0a259c-0c0c-4f2d-8b12-a5a49d200306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230903288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1230903288
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1658011177
Short name T298
Test name
Test status
Simulation time 7649882580 ps
CPU time 219.99 seconds
Started Aug 14 05:24:20 PM PDT 24
Finished Aug 14 05:28:00 PM PDT 24
Peak memory 219636 kb
Host smart-d50816d1-e015-4add-8ac7-c0de7c1c29d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658011177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1658011177
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3234115517
Short name T175
Test name
Test status
Simulation time 347485566 ps
CPU time 19.2 seconds
Started Aug 14 05:24:28 PM PDT 24
Finished Aug 14 05:24:47 PM PDT 24
Peak memory 219440 kb
Host smart-1e89c0c7-d1ef-45e0-8905-c8f0f4e0eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234115517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3234115517
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3924495532
Short name T3
Test name
Test status
Simulation time 2911969672 ps
CPU time 10.74 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:24:33 PM PDT 24
Peak memory 219460 kb
Host smart-6b5d3e2a-7a43-47f8-ba0e-5537125e3328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924495532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3924495532
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1428178863
Short name T72
Test name
Test status
Simulation time 2060301514 ps
CPU time 28.46 seconds
Started Aug 14 05:24:22 PM PDT 24
Finished Aug 14 05:24:51 PM PDT 24
Peak memory 219208 kb
Host smart-144e99c3-409a-4341-9164-43e28ea6e827
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428178863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1428178863
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2729688866
Short name T230
Test name
Test status
Simulation time 750912811 ps
CPU time 8.36 seconds
Started Aug 14 05:24:28 PM PDT 24
Finished Aug 14 05:24:36 PM PDT 24
Peak memory 218432 kb
Host smart-a9520c73-e2fe-4470-b025-2d576fcdfbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729688866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2729688866
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2376679791
Short name T42
Test name
Test status
Simulation time 6875536363 ps
CPU time 166.48 seconds
Started Aug 14 05:24:31 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 219428 kb
Host smart-0b08d345-61ce-4e46-8ee0-dca2b51a25e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376679791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2376679791
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1689684005
Short name T286
Test name
Test status
Simulation time 1940943264 ps
CPU time 19.65 seconds
Started Aug 14 05:24:29 PM PDT 24
Finished Aug 14 05:24:49 PM PDT 24
Peak memory 219464 kb
Host smart-135f7e1a-6a65-4942-bb7c-f3f86c95ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689684005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1689684005
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2928535556
Short name T129
Test name
Test status
Simulation time 2129452968 ps
CPU time 12.26 seconds
Started Aug 14 05:24:27 PM PDT 24
Finished Aug 14 05:24:39 PM PDT 24
Peak memory 219348 kb
Host smart-097bcc01-b937-4e95-9114-218b02d015ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928535556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2928535556
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1438309625
Short name T157
Test name
Test status
Simulation time 1419481195 ps
CPU time 43.08 seconds
Started Aug 14 05:24:30 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 219832 kb
Host smart-2cea4a81-babc-41aa-90e4-50f8b007e674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438309625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1438309625
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1062609843
Short name T289
Test name
Test status
Simulation time 333022449 ps
CPU time 8.44 seconds
Started Aug 14 05:24:31 PM PDT 24
Finished Aug 14 05:24:39 PM PDT 24
Peak memory 218288 kb
Host smart-cda1823d-8ec4-48e6-bc84-250846954322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062609843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1062609843
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.80575653
Short name T231
Test name
Test status
Simulation time 27753778674 ps
CPU time 164.47 seconds
Started Aug 14 05:24:29 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 238080 kb
Host smart-0edee429-3843-44c5-beb5-33400ec1c6a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80575653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_co
rrupt_sig_fatal_chk.80575653
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1882975936
Short name T262
Test name
Test status
Simulation time 1378969277 ps
CPU time 19.57 seconds
Started Aug 14 05:24:26 PM PDT 24
Finished Aug 14 05:24:46 PM PDT 24
Peak memory 219420 kb
Host smart-853fadd2-51f7-47d5-9906-c57d69f8d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882975936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1882975936
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1559075071
Short name T127
Test name
Test status
Simulation time 714128726 ps
CPU time 10.33 seconds
Started Aug 14 05:24:27 PM PDT 24
Finished Aug 14 05:24:37 PM PDT 24
Peak memory 219336 kb
Host smart-f984d155-722a-4135-8c15-020ffb78629e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559075071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1559075071
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.181369662
Short name T300
Test name
Test status
Simulation time 174573860 ps
CPU time 8.18 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 218524 kb
Host smart-f7abee80-21fe-46a6-946e-49f905dcb3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181369662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.181369662
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3420706816
Short name T159
Test name
Test status
Simulation time 4399464886 ps
CPU time 222.85 seconds
Started Aug 14 05:24:36 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 237448 kb
Host smart-8a1821c8-8f97-461e-9b8d-1edcc3814eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420706816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3420706816
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3133591387
Short name T132
Test name
Test status
Simulation time 537949639 ps
CPU time 12.01 seconds
Started Aug 14 05:24:27 PM PDT 24
Finished Aug 14 05:24:40 PM PDT 24
Peak memory 219324 kb
Host smart-e2e25fa8-6974-4af2-a2ff-72a5cf285a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133591387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3133591387
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2086109928
Short name T91
Test name
Test status
Simulation time 1156651536 ps
CPU time 30.43 seconds
Started Aug 14 05:24:29 PM PDT 24
Finished Aug 14 05:24:59 PM PDT 24
Peak memory 219300 kb
Host smart-91b99e98-560f-45b6-99ff-9167b5cfe4bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086109928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2086109928
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1256452721
Short name T208
Test name
Test status
Simulation time 174486487 ps
CPU time 8.46 seconds
Started Aug 14 05:24:34 PM PDT 24
Finished Aug 14 05:24:43 PM PDT 24
Peak memory 218428 kb
Host smart-84d8ff0e-a63a-4ff5-a25e-634fae351270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256452721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1256452721
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2402070131
Short name T158
Test name
Test status
Simulation time 5591764842 ps
CPU time 316.14 seconds
Started Aug 14 05:24:39 PM PDT 24
Finished Aug 14 05:29:55 PM PDT 24
Peak memory 226288 kb
Host smart-612bd28d-1d49-497a-8216-2e577d844f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402070131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2402070131
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3978840880
Short name T197
Test name
Test status
Simulation time 689556177 ps
CPU time 19.58 seconds
Started Aug 14 05:24:36 PM PDT 24
Finished Aug 14 05:24:56 PM PDT 24
Peak memory 219560 kb
Host smart-f34dd824-64b0-4074-bd9b-47d4510052d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978840880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3978840880
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1260370704
Short name T178
Test name
Test status
Simulation time 185671172 ps
CPU time 10.91 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:24:47 PM PDT 24
Peak memory 219336 kb
Host smart-afde6570-4eb6-49f9-b5a9-09f2cc901374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260370704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1260370704
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2780677286
Short name T40
Test name
Test status
Simulation time 1200960372 ps
CPU time 22.97 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:24:58 PM PDT 24
Peak memory 219368 kb
Host smart-06cc5469-f19c-4cbe-95a5-346521b197a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780677286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2780677286
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2011742975
Short name T77
Test name
Test status
Simulation time 259653646 ps
CPU time 10.25 seconds
Started Aug 14 05:24:36 PM PDT 24
Finished Aug 14 05:24:47 PM PDT 24
Peak memory 218452 kb
Host smart-94c41d91-212b-4518-a374-5a7dc666e298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011742975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2011742975
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.352648231
Short name T245
Test name
Test status
Simulation time 14416157188 ps
CPU time 185.19 seconds
Started Aug 14 05:24:37 PM PDT 24
Finished Aug 14 05:27:42 PM PDT 24
Peak memory 229048 kb
Host smart-5fd4ffc0-009f-4c09-88cb-6628ab3a2c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352648231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.352648231
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.289362919
Short name T303
Test name
Test status
Simulation time 2012617944 ps
CPU time 33.11 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:25:08 PM PDT 24
Peak memory 218820 kb
Host smart-76e9aa9f-63fe-4f29-96e1-e483c1cd7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289362919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.289362919
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1685198573
Short name T130
Test name
Test status
Simulation time 2327224896 ps
CPU time 12.07 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:24:47 PM PDT 24
Peak memory 219420 kb
Host smart-26c7cef8-1961-4f19-9c4a-74b41959cdeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685198573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1685198573
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3577749054
Short name T270
Test name
Test status
Simulation time 295366492 ps
CPU time 13.32 seconds
Started Aug 14 05:24:39 PM PDT 24
Finished Aug 14 05:24:52 PM PDT 24
Peak memory 219360 kb
Host smart-3e1e4a6f-ee3d-4014-9010-a71c21976141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577749054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3577749054
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.853877013
Short name T145
Test name
Test status
Simulation time 345362965 ps
CPU time 8.27 seconds
Started Aug 14 05:23:09 PM PDT 24
Finished Aug 14 05:23:17 PM PDT 24
Peak memory 218080 kb
Host smart-fa743920-0beb-44c9-ab35-187e664bf849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853877013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.853877013
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4024491794
Short name T43
Test name
Test status
Simulation time 14218126979 ps
CPU time 274.5 seconds
Started Aug 14 05:23:08 PM PDT 24
Finished Aug 14 05:27:42 PM PDT 24
Peak memory 240204 kb
Host smart-151e2725-5b32-420a-a9ae-7dde1f3b07d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024491794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4024491794
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.762792593
Short name T36
Test name
Test status
Simulation time 870485441 ps
CPU time 18.98 seconds
Started Aug 14 05:23:08 PM PDT 24
Finished Aug 14 05:23:27 PM PDT 24
Peak memory 219404 kb
Host smart-3c62598f-31e2-4091-a2ae-f1d82ce2cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762792593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.762792593
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1083557374
Short name T19
Test name
Test status
Simulation time 320312703 ps
CPU time 12.25 seconds
Started Aug 14 05:23:08 PM PDT 24
Finished Aug 14 05:23:21 PM PDT 24
Peak memory 219152 kb
Host smart-8eec6726-34d3-49ef-b329-353102da91a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083557374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1083557374
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4017144559
Short name T23
Test name
Test status
Simulation time 257585369 ps
CPU time 117.67 seconds
Started Aug 14 05:23:07 PM PDT 24
Finished Aug 14 05:25:05 PM PDT 24
Peak memory 238852 kb
Host smart-3b2fd5f0-2af4-40db-ab24-b857afe5804c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017144559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4017144559
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2571402333
Short name T317
Test name
Test status
Simulation time 4101679761 ps
CPU time 18.42 seconds
Started Aug 14 05:23:00 PM PDT 24
Finished Aug 14 05:23:18 PM PDT 24
Peak memory 219460 kb
Host smart-a270b187-2bb8-40f2-8973-30cb253174d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571402333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2571402333
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1085372480
Short name T58
Test name
Test status
Simulation time 2145614522 ps
CPU time 23.94 seconds
Started Aug 14 05:23:03 PM PDT 24
Finished Aug 14 05:23:27 PM PDT 24
Peak memory 219416 kb
Host smart-5ab3377c-d71a-49a6-bf8c-210b3c01648d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085372480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1085372480
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3668147136
Short name T194
Test name
Test status
Simulation time 518297361 ps
CPU time 9.99 seconds
Started Aug 14 05:24:42 PM PDT 24
Finished Aug 14 05:24:52 PM PDT 24
Peak memory 218416 kb
Host smart-0b77fc45-2787-4de2-8cca-3e023cda43c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668147136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3668147136
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2276426558
Short name T278
Test name
Test status
Simulation time 1014180397 ps
CPU time 22.98 seconds
Started Aug 14 05:24:37 PM PDT 24
Finished Aug 14 05:25:00 PM PDT 24
Peak memory 219216 kb
Host smart-cc73afd7-d541-43cd-ba64-7f10a1951203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276426558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2276426558
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.670822614
Short name T249
Test name
Test status
Simulation time 1605158114 ps
CPU time 12.41 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:24:48 PM PDT 24
Peak memory 219348 kb
Host smart-2e4892d5-a8d6-4f23-94b4-dbda9455f702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670822614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.670822614
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1483944945
Short name T162
Test name
Test status
Simulation time 999173892 ps
CPU time 38.09 seconds
Started Aug 14 05:24:35 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 219352 kb
Host smart-aa1fd581-b852-4b99-b33c-6f9f04977a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483944945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1483944945
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.116168104
Short name T24
Test name
Test status
Simulation time 505316393 ps
CPU time 10.17 seconds
Started Aug 14 05:24:45 PM PDT 24
Finished Aug 14 05:24:55 PM PDT 24
Peak memory 218416 kb
Host smart-5a36482b-0d2e-48ba-90c3-598b624f6501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116168104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.116168104
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.331305144
Short name T152
Test name
Test status
Simulation time 20356580778 ps
CPU time 302.43 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 243436 kb
Host smart-9dab5819-c2e4-4eb0-9bc9-1fb0beddffed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331305144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.331305144
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4090507021
Short name T219
Test name
Test status
Simulation time 2050449929 ps
CPU time 22.35 seconds
Started Aug 14 05:24:42 PM PDT 24
Finished Aug 14 05:25:05 PM PDT 24
Peak memory 219396 kb
Host smart-d48c6cb9-81c1-4fa1-be55-b1e0ff18689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090507021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4090507021
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.891306583
Short name T110
Test name
Test status
Simulation time 5162721479 ps
CPU time 11.99 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:24:55 PM PDT 24
Peak memory 219396 kb
Host smart-e3863e62-6d73-4471-9e78-ccfde1872ce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891306583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.891306583
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2530874216
Short name T171
Test name
Test status
Simulation time 266847054 ps
CPU time 19.24 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 219012 kb
Host smart-bc7fa3f4-fd9a-47d5-829a-7f575e5d1e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530874216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2530874216
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4166711884
Short name T293
Test name
Test status
Simulation time 592287518 ps
CPU time 10.21 seconds
Started Aug 14 05:24:45 PM PDT 24
Finished Aug 14 05:24:55 PM PDT 24
Peak memory 218436 kb
Host smart-3d55c493-0836-4236-a65d-3001466f237f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166711884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4166711884
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2026177062
Short name T41
Test name
Test status
Simulation time 8464763400 ps
CPU time 237.42 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 228672 kb
Host smart-b905445b-3375-489a-b047-7931c8dc2f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026177062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2026177062
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2262339331
Short name T62
Test name
Test status
Simulation time 1435325114 ps
CPU time 18.92 seconds
Started Aug 14 05:24:44 PM PDT 24
Finished Aug 14 05:25:03 PM PDT 24
Peak memory 219376 kb
Host smart-af7590c3-ece9-4713-9e40-6ef5927852f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262339331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2262339331
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1771541212
Short name T238
Test name
Test status
Simulation time 1020792009 ps
CPU time 11.78 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:24:55 PM PDT 24
Peak memory 219336 kb
Host smart-3c166729-28aa-4d89-a952-9ead3ff4af9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771541212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1771541212
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3079408093
Short name T148
Test name
Test status
Simulation time 813184094 ps
CPU time 45.92 seconds
Started Aug 14 05:24:45 PM PDT 24
Finished Aug 14 05:25:31 PM PDT 24
Peak memory 219384 kb
Host smart-4040de64-5785-4cc3-8b8c-0d0a27b85c53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079408093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3079408093
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.521898301
Short name T273
Test name
Test status
Simulation time 194482366 ps
CPU time 8.22 seconds
Started Aug 14 05:24:51 PM PDT 24
Finished Aug 14 05:24:59 PM PDT 24
Peak memory 218532 kb
Host smart-d0fb6953-90ea-44bd-bfb9-972d6911fec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521898301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.521898301
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1695657481
Short name T154
Test name
Test status
Simulation time 2696296971 ps
CPU time 158.45 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 241248 kb
Host smart-5524beb4-0830-46cc-8d9b-586c3f8bb92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695657481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1695657481
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1669814748
Short name T167
Test name
Test status
Simulation time 1977798253 ps
CPU time 22.38 seconds
Started Aug 14 05:24:44 PM PDT 24
Finished Aug 14 05:25:07 PM PDT 24
Peak memory 219336 kb
Host smart-f18fb16c-8a25-4cb4-a501-12c3a516262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669814748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1669814748
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1644641766
Short name T131
Test name
Test status
Simulation time 365910886 ps
CPU time 10.5 seconds
Started Aug 14 05:24:43 PM PDT 24
Finished Aug 14 05:24:54 PM PDT 24
Peak memory 219360 kb
Host smart-4f2def65-6f71-4c75-aeb6-ad666304f50f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644641766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1644641766
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1251102956
Short name T287
Test name
Test status
Simulation time 1153016100 ps
CPU time 18.65 seconds
Started Aug 14 05:24:44 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 219276 kb
Host smart-e5c7fa8a-235b-4dcf-8371-fcc62c1333be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251102956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1251102956
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3495692497
Short name T204
Test name
Test status
Simulation time 4273928205 ps
CPU time 14.65 seconds
Started Aug 14 05:24:50 PM PDT 24
Finished Aug 14 05:25:05 PM PDT 24
Peak memory 218220 kb
Host smart-505e7bb7-b13d-4bc8-86fe-fd6e4f7fbdc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495692497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3495692497
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2540770795
Short name T47
Test name
Test status
Simulation time 13915324168 ps
CPU time 249.41 seconds
Started Aug 14 05:24:50 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 237832 kb
Host smart-389f6e32-eb01-4ea2-8d54-3a46a837cace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540770795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2540770795
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1095947324
Short name T173
Test name
Test status
Simulation time 1013035719 ps
CPU time 22.37 seconds
Started Aug 14 05:24:51 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 219404 kb
Host smart-9cfe8190-1115-49eb-841f-86d3b362c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095947324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1095947324
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3886522928
Short name T9
Test name
Test status
Simulation time 226456622 ps
CPU time 10.36 seconds
Started Aug 14 05:24:52 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 219280 kb
Host smart-9afcb676-ef56-44d7-8db6-fc15a78fc369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886522928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3886522928
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2292779057
Short name T291
Test name
Test status
Simulation time 546158463 ps
CPU time 27.97 seconds
Started Aug 14 05:24:50 PM PDT 24
Finished Aug 14 05:25:18 PM PDT 24
Peak memory 219304 kb
Host smart-b5b5fc08-8f7d-4e34-9f5d-d04dc47b2137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292779057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2292779057
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1528052393
Short name T5
Test name
Test status
Simulation time 1298719933 ps
CPU time 10.04 seconds
Started Aug 14 05:24:52 PM PDT 24
Finished Aug 14 05:25:02 PM PDT 24
Peak memory 218400 kb
Host smart-77e25c85-805c-439e-9923-6d1dd8641c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528052393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1528052393
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.264490234
Short name T2
Test name
Test status
Simulation time 29134653735 ps
CPU time 273.4 seconds
Started Aug 14 05:24:52 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 219452 kb
Host smart-a005f926-4af5-46eb-beab-3a9493a0055d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264490234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.264490234
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.982261783
Short name T210
Test name
Test status
Simulation time 1055799364 ps
CPU time 23.05 seconds
Started Aug 14 05:24:53 PM PDT 24
Finished Aug 14 05:25:16 PM PDT 24
Peak memory 219440 kb
Host smart-a0822030-d347-4252-91cd-eae8fdaa067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982261783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.982261783
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3020489179
Short name T191
Test name
Test status
Simulation time 732782062 ps
CPU time 10.48 seconds
Started Aug 14 05:24:51 PM PDT 24
Finished Aug 14 05:25:01 PM PDT 24
Peak memory 219496 kb
Host smart-c9aeacc7-a701-463e-b7dd-0237e19447f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020489179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3020489179
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2435170173
Short name T70
Test name
Test status
Simulation time 544155920 ps
CPU time 35.39 seconds
Started Aug 14 05:24:52 PM PDT 24
Finished Aug 14 05:25:27 PM PDT 24
Peak memory 219408 kb
Host smart-86f1ba48-3f6c-4916-9764-56df11f6b481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435170173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2435170173
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3183870440
Short name T284
Test name
Test status
Simulation time 264154084 ps
CPU time 9.77 seconds
Started Aug 14 05:24:57 PM PDT 24
Finished Aug 14 05:25:07 PM PDT 24
Peak memory 218540 kb
Host smart-7ad5c681-5b45-4086-8330-2508eb8d3de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183870440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3183870440
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4052587184
Short name T165
Test name
Test status
Simulation time 497203113 ps
CPU time 23.21 seconds
Started Aug 14 05:24:52 PM PDT 24
Finished Aug 14 05:25:16 PM PDT 24
Peak memory 219420 kb
Host smart-f3b4a0a8-fee0-4311-8074-e0d84ff0ee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052587184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4052587184
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1266543528
Short name T214
Test name
Test status
Simulation time 181577166 ps
CPU time 9.99 seconds
Started Aug 14 05:24:51 PM PDT 24
Finished Aug 14 05:25:01 PM PDT 24
Peak memory 219320 kb
Host smart-37853ccf-87bc-4234-bce2-4f76ad9f0519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266543528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1266543528
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1991518997
Short name T237
Test name
Test status
Simulation time 723057191 ps
CPU time 17.29 seconds
Started Aug 14 05:24:51 PM PDT 24
Finished Aug 14 05:25:08 PM PDT 24
Peak memory 219256 kb
Host smart-49ef6727-1b37-4221-a90b-b923d5643c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991518997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1991518997
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4285002469
Short name T25
Test name
Test status
Simulation time 274169131 ps
CPU time 10.2 seconds
Started Aug 14 05:24:58 PM PDT 24
Finished Aug 14 05:25:09 PM PDT 24
Peak memory 218384 kb
Host smart-8fa2cdfe-e86b-4cd3-ae27-2d5695fafa0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285002469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4285002469
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1113193023
Short name T46
Test name
Test status
Simulation time 6898666571 ps
CPU time 202.09 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:28:22 PM PDT 24
Peak memory 225120 kb
Host smart-92d3074d-3aff-441e-8dbd-7622032a895f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113193023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1113193023
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4136366381
Short name T160
Test name
Test status
Simulation time 1323421018 ps
CPU time 19.14 seconds
Started Aug 14 05:24:57 PM PDT 24
Finished Aug 14 05:25:16 PM PDT 24
Peak memory 219436 kb
Host smart-414c2c1c-26ba-4679-bdc0-b90adb92ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136366381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4136366381
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4235451058
Short name T174
Test name
Test status
Simulation time 640679828 ps
CPU time 10.48 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:11 PM PDT 24
Peak memory 219336 kb
Host smart-c2ac5b9d-42ae-4259-9969-4c92325179db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235451058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4235451058
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1735520221
Short name T285
Test name
Test status
Simulation time 1934970762 ps
CPU time 14.65 seconds
Started Aug 14 05:24:58 PM PDT 24
Finished Aug 14 05:25:13 PM PDT 24
Peak memory 219340 kb
Host smart-ff95c4a9-c0e7-455b-bf1a-340a0b8fd9cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735520221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1735520221
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3067857616
Short name T316
Test name
Test status
Simulation time 168384400 ps
CPU time 8.3 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:09 PM PDT 24
Peak memory 218472 kb
Host smart-2d82d692-e093-48f1-b64f-20ad269d9854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067857616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3067857616
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2664081611
Short name T8
Test name
Test status
Simulation time 8846030414 ps
CPU time 211.3 seconds
Started Aug 14 05:24:57 PM PDT 24
Finished Aug 14 05:28:29 PM PDT 24
Peak memory 230920 kb
Host smart-cd48dbf5-04a8-4cef-bab0-bcea4b1b43d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664081611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2664081611
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2346215966
Short name T7
Test name
Test status
Simulation time 1762012339 ps
CPU time 22.35 seconds
Started Aug 14 05:24:58 PM PDT 24
Finished Aug 14 05:25:21 PM PDT 24
Peak memory 219352 kb
Host smart-2b360e25-60a1-42ad-a075-be84b3cedc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346215966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2346215966
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.400115960
Short name T247
Test name
Test status
Simulation time 269289178 ps
CPU time 12.36 seconds
Started Aug 14 05:24:57 PM PDT 24
Finished Aug 14 05:25:10 PM PDT 24
Peak memory 219320 kb
Host smart-23226912-6478-483b-aad0-4fc32e766945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400115960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.400115960
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.776403304
Short name T71
Test name
Test status
Simulation time 1379558794 ps
CPU time 39.46 seconds
Started Aug 14 05:24:59 PM PDT 24
Finished Aug 14 05:25:39 PM PDT 24
Peak memory 219352 kb
Host smart-a85dba6e-be3c-49c9-ba67-6b49ccf6d1d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776403304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.776403304
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3009790252
Short name T79
Test name
Test status
Simulation time 316979048 ps
CPU time 10.3 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:10 PM PDT 24
Peak memory 218436 kb
Host smart-fe7e18e3-e43f-4d2a-b231-f7e67257d343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009790252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3009790252
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3906979866
Short name T266
Test name
Test status
Simulation time 28554061486 ps
CPU time 363.8 seconds
Started Aug 14 05:24:58 PM PDT 24
Finished Aug 14 05:31:02 PM PDT 24
Peak memory 243104 kb
Host smart-73c54db9-51e6-4579-8a92-acb320e86592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906979866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3906979866
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1460509536
Short name T155
Test name
Test status
Simulation time 501645142 ps
CPU time 23.22 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:23 PM PDT 24
Peak memory 219400 kb
Host smart-d894ce00-aaab-4162-81c1-5a8fecffa86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460509536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1460509536
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1438811144
Short name T195
Test name
Test status
Simulation time 273009988 ps
CPU time 12.45 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:12 PM PDT 24
Peak memory 219424 kb
Host smart-7ea8010b-e691-43f4-b22c-be65ff337e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438811144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1438811144
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1382444772
Short name T242
Test name
Test status
Simulation time 3536619553 ps
CPU time 38.44 seconds
Started Aug 14 05:25:04 PM PDT 24
Finished Aug 14 05:25:43 PM PDT 24
Peak memory 219448 kb
Host smart-70ec45a6-e02d-479b-8f52-399bf0eab564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382444772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1382444772
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.337603223
Short name T76
Test name
Test status
Simulation time 662298704 ps
CPU time 8.24 seconds
Started Aug 14 05:23:15 PM PDT 24
Finished Aug 14 05:23:23 PM PDT 24
Peak memory 218348 kb
Host smart-a7ef6342-0424-4469-886b-f6459b2a6f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337603223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.337603223
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1078810127
Short name T35
Test name
Test status
Simulation time 27523366171 ps
CPU time 412.37 seconds
Started Aug 14 05:23:07 PM PDT 24
Finished Aug 14 05:29:59 PM PDT 24
Peak memory 238160 kb
Host smart-a47b7bb2-39c5-439b-9aca-246fffb9f20e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078810127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1078810127
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.453942197
Short name T307
Test name
Test status
Simulation time 2752920836 ps
CPU time 22.97 seconds
Started Aug 14 05:23:08 PM PDT 24
Finished Aug 14 05:23:31 PM PDT 24
Peak memory 219512 kb
Host smart-1d5cc1d1-5b8a-4e4a-8dc6-c1676adc28c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453942197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.453942197
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2175416039
Short name T57
Test name
Test status
Simulation time 184571276 ps
CPU time 10.32 seconds
Started Aug 14 05:23:07 PM PDT 24
Finished Aug 14 05:23:17 PM PDT 24
Peak memory 219340 kb
Host smart-9e15902d-5037-4fc1-b444-b463d32bf871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175416039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2175416039
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1240116203
Short name T269
Test name
Test status
Simulation time 270286528 ps
CPU time 12.32 seconds
Started Aug 14 05:23:07 PM PDT 24
Finished Aug 14 05:23:19 PM PDT 24
Peak memory 219416 kb
Host smart-d973bb9e-fac9-4650-acc0-2f3b57a6c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240116203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1240116203
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3037093741
Short name T261
Test name
Test status
Simulation time 575046015 ps
CPU time 38.73 seconds
Started Aug 14 05:23:06 PM PDT 24
Finished Aug 14 05:23:45 PM PDT 24
Peak memory 219468 kb
Host smart-418eb4eb-22ec-4ad8-9c61-59e55a1c58b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037093741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3037093741
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.464407227
Short name T227
Test name
Test status
Simulation time 314559838 ps
CPU time 10.25 seconds
Started Aug 14 05:25:11 PM PDT 24
Finished Aug 14 05:25:21 PM PDT 24
Peak memory 218468 kb
Host smart-36e18a71-67f3-4e0f-a956-7557cfe73c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464407227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.464407227
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.629288660
Short name T141
Test name
Test status
Simulation time 23804777571 ps
CPU time 295.15 seconds
Started Aug 14 05:25:11 PM PDT 24
Finished Aug 14 05:30:06 PM PDT 24
Peak memory 219672 kb
Host smart-f5405fd2-eb61-4614-b69f-d3f8d327b7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629288660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.629288660
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2398874234
Short name T201
Test name
Test status
Simulation time 518814187 ps
CPU time 23.05 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:25:33 PM PDT 24
Peak memory 219388 kb
Host smart-d3dc1421-fef5-47ae-8204-3be264ca8340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398874234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2398874234
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.457549453
Short name T207
Test name
Test status
Simulation time 1075410239 ps
CPU time 10.27 seconds
Started Aug 14 05:25:00 PM PDT 24
Finished Aug 14 05:25:10 PM PDT 24
Peak memory 219280 kb
Host smart-ff08c403-c258-4a7e-a3b0-c20b57d6cf7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457549453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.457549453
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.410050671
Short name T18
Test name
Test status
Simulation time 3046605656 ps
CPU time 38.05 seconds
Started Aug 14 05:24:58 PM PDT 24
Finished Aug 14 05:25:36 PM PDT 24
Peak memory 219396 kb
Host smart-10288fb9-09fc-4b1e-ab83-a5012b3ab180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410050671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.410050671
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2399513298
Short name T181
Test name
Test status
Simulation time 1650667143 ps
CPU time 10.49 seconds
Started Aug 14 05:25:12 PM PDT 24
Finished Aug 14 05:25:22 PM PDT 24
Peak memory 218528 kb
Host smart-cd6380e1-44a8-4045-b268-7a1d22e1ed73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399513298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2399513298
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.829820316
Short name T308
Test name
Test status
Simulation time 15785040519 ps
CPU time 214.5 seconds
Started Aug 14 05:25:12 PM PDT 24
Finished Aug 14 05:28:46 PM PDT 24
Peak memory 243212 kb
Host smart-c789c0fa-07ce-4238-9551-afc04934b12b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829820316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.829820316
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.748614012
Short name T193
Test name
Test status
Simulation time 2060767032 ps
CPU time 19.75 seconds
Started Aug 14 05:25:11 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 219440 kb
Host smart-246b0a8d-97d2-407c-b05f-584c53e7981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748614012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.748614012
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1997323714
Short name T258
Test name
Test status
Simulation time 1169449399 ps
CPU time 12.21 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:25:22 PM PDT 24
Peak memory 219364 kb
Host smart-326232a4-286a-4d3e-8430-9f341fefe6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997323714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1997323714
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3042483636
Short name T153
Test name
Test status
Simulation time 800380281 ps
CPU time 10.1 seconds
Started Aug 14 05:25:11 PM PDT 24
Finished Aug 14 05:25:22 PM PDT 24
Peak memory 218460 kb
Host smart-556cc50f-e23d-4629-a372-568685460344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042483636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3042483636
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2363720600
Short name T143
Test name
Test status
Simulation time 69018538986 ps
CPU time 323.56 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:30:34 PM PDT 24
Peak memory 239216 kb
Host smart-90b4686a-2fbb-4b25-8502-0cadb18b7689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363720600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2363720600
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.79656058
Short name T305
Test name
Test status
Simulation time 1379882075 ps
CPU time 19.04 seconds
Started Aug 14 05:25:09 PM PDT 24
Finished Aug 14 05:25:28 PM PDT 24
Peak memory 219416 kb
Host smart-bb550422-848d-4421-86ba-ea2e99bd9a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79656058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.79656058
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1844485763
Short name T199
Test name
Test status
Simulation time 1067797084 ps
CPU time 12.33 seconds
Started Aug 14 05:25:09 PM PDT 24
Finished Aug 14 05:25:21 PM PDT 24
Peak memory 219336 kb
Host smart-ee99f12b-e198-4452-b962-c84f3538a7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844485763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1844485763
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2289800328
Short name T137
Test name
Test status
Simulation time 519909531 ps
CPU time 29.7 seconds
Started Aug 14 05:25:10 PM PDT 24
Finished Aug 14 05:25:40 PM PDT 24
Peak memory 219372 kb
Host smart-dc4453a7-2921-4ef4-aa07-6cadf58184a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289800328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2289800328
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3730982940
Short name T264
Test name
Test status
Simulation time 870356585 ps
CPU time 8.38 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:25:23 PM PDT 24
Peak memory 218500 kb
Host smart-92724381-28ea-4ac1-83e6-5b774cb5793d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730982940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3730982940
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2038548904
Short name T147
Test name
Test status
Simulation time 7896903691 ps
CPU time 220.32 seconds
Started Aug 14 05:25:12 PM PDT 24
Finished Aug 14 05:28:52 PM PDT 24
Peak memory 242392 kb
Host smart-ab6e4051-69e1-4a1f-a365-81220e246a2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038548904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2038548904
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1097386656
Short name T216
Test name
Test status
Simulation time 2064164970 ps
CPU time 22.96 seconds
Started Aug 14 05:25:11 PM PDT 24
Finished Aug 14 05:25:34 PM PDT 24
Peak memory 219452 kb
Host smart-7c058968-61a7-439b-ba25-8a87af6f9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097386656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1097386656
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.977557823
Short name T89
Test name
Test status
Simulation time 789427947 ps
CPU time 44.98 seconds
Started Aug 14 05:25:08 PM PDT 24
Finished Aug 14 05:25:53 PM PDT 24
Peak memory 219364 kb
Host smart-799ccf1d-46ab-4534-af4e-fcaf3f297175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977557823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.977557823
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2352878311
Short name T33
Test name
Test status
Simulation time 506418192 ps
CPU time 9.98 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:24 PM PDT 24
Peak memory 218452 kb
Host smart-40b82fa0-5f25-444c-ae08-c8e990995d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352878311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2352878311
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3926921346
Short name T34
Test name
Test status
Simulation time 12287378420 ps
CPU time 247.55 seconds
Started Aug 14 05:25:13 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 239116 kb
Host smart-173c8630-ba60-4d80-8c70-4b7db7e73f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926921346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3926921346
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3586866389
Short name T246
Test name
Test status
Simulation time 1320918958 ps
CPU time 19.25 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:34 PM PDT 24
Peak memory 219372 kb
Host smart-0cb76cf3-958a-4005-ae96-6f9342fc40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586866389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3586866389
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2189316667
Short name T65
Test name
Test status
Simulation time 266798626 ps
CPU time 12.07 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:26 PM PDT 24
Peak memory 219356 kb
Host smart-8dab384a-ce7e-4b2d-990e-9e87352d3c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189316667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2189316667
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.947796393
Short name T151
Test name
Test status
Simulation time 4530646574 ps
CPU time 19.85 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:34 PM PDT 24
Peak memory 219488 kb
Host smart-e25ba906-423d-49ba-8906-4fb7fdab859e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947796393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.947796393
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.846055114
Short name T274
Test name
Test status
Simulation time 1024263125 ps
CPU time 15.49 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 218324 kb
Host smart-1d275d77-9db9-4933-bd2f-220e406d1ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846055114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.846055114
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.865080339
Short name T241
Test name
Test status
Simulation time 9940826845 ps
CPU time 260.36 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:29:35 PM PDT 24
Peak memory 235148 kb
Host smart-561cf9d7-8714-4fd9-8d7f-70d2bb16eaa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865080339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.865080339
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3054328161
Short name T257
Test name
Test status
Simulation time 1101908278 ps
CPU time 22.28 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:25:37 PM PDT 24
Peak memory 219424 kb
Host smart-e110bf8e-0b2e-4e31-a88c-c6ab774d37bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054328161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3054328161
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4047246654
Short name T133
Test name
Test status
Simulation time 439503702 ps
CPU time 10.39 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:25:25 PM PDT 24
Peak memory 219324 kb
Host smart-c60f57f1-b5b9-44e5-9589-4543a96cefd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047246654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4047246654
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2174290674
Short name T302
Test name
Test status
Simulation time 997548141 ps
CPU time 19.33 seconds
Started Aug 14 05:25:16 PM PDT 24
Finished Aug 14 05:25:35 PM PDT 24
Peak memory 219260 kb
Host smart-09d9253c-91e4-47c0-9b78-fd38a57a40ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174290674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2174290674
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.681138050
Short name T299
Test name
Test status
Simulation time 1548938827 ps
CPU time 10.22 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:25 PM PDT 24
Peak memory 218492 kb
Host smart-9450747b-aa7c-4114-b152-6273f5951535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681138050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.681138050
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2265883379
Short name T146
Test name
Test status
Simulation time 4041401405 ps
CPU time 255.43 seconds
Started Aug 14 05:25:16 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 237948 kb
Host smart-1d298bbc-f86c-4eee-9f2f-4be4d9b0fc1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265883379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2265883379
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2017479435
Short name T296
Test name
Test status
Simulation time 39469328453 ps
CPU time 33.75 seconds
Started Aug 14 05:25:15 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 219508 kb
Host smart-ce98cbc0-a262-4fcb-8495-865b522822cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017479435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2017479435
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.955746031
Short name T188
Test name
Test status
Simulation time 610828883 ps
CPU time 12.55 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:27 PM PDT 24
Peak memory 219424 kb
Host smart-10db0f6a-0ba8-4d76-a46a-d118f7fd8875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955746031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.955746031
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1827322698
Short name T279
Test name
Test status
Simulation time 360764608 ps
CPU time 24.62 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:39 PM PDT 24
Peak memory 219372 kb
Host smart-3ea25da4-9cfb-469e-91ae-546aa3005fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827322698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1827322698
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2436901232
Short name T232
Test name
Test status
Simulation time 168323909 ps
CPU time 8.45 seconds
Started Aug 14 05:25:19 PM PDT 24
Finished Aug 14 05:25:27 PM PDT 24
Peak memory 218464 kb
Host smart-c44caf8f-2050-4230-9d8c-db72df6debc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436901232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2436901232
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.234525274
Short name T280
Test name
Test status
Simulation time 18390361539 ps
CPU time 239.73 seconds
Started Aug 14 05:25:20 PM PDT 24
Finished Aug 14 05:29:20 PM PDT 24
Peak memory 229880 kb
Host smart-7cdbe723-803f-45f7-be3b-a7725d81ed90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234525274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.234525274
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2966724240
Short name T234
Test name
Test status
Simulation time 551604963 ps
CPU time 21.86 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:25:52 PM PDT 24
Peak memory 219420 kb
Host smart-230bdf4f-cf74-4ea6-a4dd-cefd34ac6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966724240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2966724240
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1296741676
Short name T233
Test name
Test status
Simulation time 798898715 ps
CPU time 10.36 seconds
Started Aug 14 05:25:20 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 219128 kb
Host smart-72024c27-0198-4ffd-9583-9d57e9aacbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296741676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1296741676
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1701361656
Short name T16
Test name
Test status
Simulation time 1088390262 ps
CPU time 26.73 seconds
Started Aug 14 05:25:14 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 219372 kb
Host smart-1c9ea68e-9f3f-4400-8bfc-ec5b941c3e2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701361656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1701361656
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4151525108
Short name T169
Test name
Test status
Simulation time 250628717 ps
CPU time 9.8 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:25:39 PM PDT 24
Peak memory 218460 kb
Host smart-4e39793a-00f7-483a-ba33-18cc72589dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151525108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4151525108
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.125174187
Short name T186
Test name
Test status
Simulation time 4619718170 ps
CPU time 298.87 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 226852 kb
Host smart-c5352571-f58a-4cc7-ac3c-146e131664ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125174187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.125174187
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3657270227
Short name T150
Test name
Test status
Simulation time 1011702739 ps
CPU time 23.29 seconds
Started Aug 14 05:25:19 PM PDT 24
Finished Aug 14 05:25:43 PM PDT 24
Peak memory 219364 kb
Host smart-3a8cdd8f-1dc7-4f29-ad87-2a7a82e2ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657270227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3657270227
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2629462464
Short name T213
Test name
Test status
Simulation time 332061731 ps
CPU time 11.88 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:25:42 PM PDT 24
Peak memory 219344 kb
Host smart-ab470ea0-ca8c-4fb5-8e3d-0f91cbb5d6dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629462464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2629462464
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1115109344
Short name T220
Test name
Test status
Simulation time 1646014822 ps
CPU time 39.73 seconds
Started Aug 14 05:25:19 PM PDT 24
Finished Aug 14 05:25:59 PM PDT 24
Peak memory 219368 kb
Host smart-f9f205dd-80d1-4e5a-91d2-3d4cc24fcf11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115109344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1115109344
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1790937062
Short name T168
Test name
Test status
Simulation time 988999467 ps
CPU time 10.42 seconds
Started Aug 14 05:25:20 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 218552 kb
Host smart-c0efd5f9-52c5-4e8d-8e4e-095adbf7ae2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790937062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1790937062
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3670688926
Short name T11
Test name
Test status
Simulation time 10493473686 ps
CPU time 365.89 seconds
Started Aug 14 05:25:20 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 239068 kb
Host smart-8c39c6de-204d-4c4f-bdad-d80ba895dece
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670688926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3670688926
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3521180304
Short name T272
Test name
Test status
Simulation time 1029962264 ps
CPU time 22.24 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 219396 kb
Host smart-443158f7-2209-43d3-ad21-51998a7d4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521180304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3521180304
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1608484170
Short name T288
Test name
Test status
Simulation time 186157654 ps
CPU time 10.72 seconds
Started Aug 14 05:25:21 PM PDT 24
Finished Aug 14 05:25:32 PM PDT 24
Peak memory 219400 kb
Host smart-54c81c09-0c34-47fc-ac54-cef490d1d840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608484170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1608484170
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1847832962
Short name T163
Test name
Test status
Simulation time 2797097488 ps
CPU time 27.41 seconds
Started Aug 14 05:25:20 PM PDT 24
Finished Aug 14 05:25:48 PM PDT 24
Peak memory 219440 kb
Host smart-83635986-8816-49d8-81fe-f4c3798ec421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847832962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1847832962
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3761831251
Short name T276
Test name
Test status
Simulation time 464540201 ps
CPU time 10.1 seconds
Started Aug 14 05:23:22 PM PDT 24
Finished Aug 14 05:23:32 PM PDT 24
Peak memory 218436 kb
Host smart-2aaebe41-2f84-4e21-8952-3c590f1148f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761831251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3761831251
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.106615303
Short name T309
Test name
Test status
Simulation time 7342390554 ps
CPU time 248.64 seconds
Started Aug 14 05:23:16 PM PDT 24
Finished Aug 14 05:27:25 PM PDT 24
Peak memory 239120 kb
Host smart-5c38dc40-638b-4acf-a065-a6d973162991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106615303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.106615303
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.397063842
Short name T277
Test name
Test status
Simulation time 2364445215 ps
CPU time 19.07 seconds
Started Aug 14 05:23:15 PM PDT 24
Finished Aug 14 05:23:34 PM PDT 24
Peak memory 219512 kb
Host smart-ef4c290c-d731-41c5-bef2-6ea9db0258f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397063842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.397063842
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2260454281
Short name T244
Test name
Test status
Simulation time 686625580 ps
CPU time 10.35 seconds
Started Aug 14 05:23:16 PM PDT 24
Finished Aug 14 05:23:27 PM PDT 24
Peak memory 219324 kb
Host smart-1e5d4c5e-e55e-499c-b072-b5b7d0923a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260454281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2260454281
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.582229004
Short name T10
Test name
Test status
Simulation time 187319046 ps
CPU time 10.66 seconds
Started Aug 14 05:23:16 PM PDT 24
Finished Aug 14 05:23:26 PM PDT 24
Peak memory 219376 kb
Host smart-97cb6b73-9334-4bd0-9841-8f50fd947e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582229004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.582229004
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.888581053
Short name T306
Test name
Test status
Simulation time 2108247791 ps
CPU time 26.28 seconds
Started Aug 14 05:23:20 PM PDT 24
Finished Aug 14 05:23:46 PM PDT 24
Peak memory 219380 kb
Host smart-fa67baea-c268-4ed4-a5e9-007530a81d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888581053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.888581053
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.228041130
Short name T239
Test name
Test status
Simulation time 2044461528 ps
CPU time 14.94 seconds
Started Aug 14 05:23:25 PM PDT 24
Finished Aug 14 05:23:40 PM PDT 24
Peak memory 218224 kb
Host smart-2cb131d2-1dc4-4ac4-bba3-f94805b00056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228041130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.228041130
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.805789459
Short name T314
Test name
Test status
Simulation time 4262566587 ps
CPU time 208.23 seconds
Started Aug 14 05:23:23 PM PDT 24
Finished Aug 14 05:26:51 PM PDT 24
Peak memory 239136 kb
Host smart-60942254-6970-4cd9-a259-c2941491af1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805789459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.805789459
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.59783257
Short name T149
Test name
Test status
Simulation time 1983401094 ps
CPU time 22.47 seconds
Started Aug 14 05:23:22 PM PDT 24
Finished Aug 14 05:23:45 PM PDT 24
Peak memory 219420 kb
Host smart-7b1ec729-e3d5-458f-8d4e-9aa8d13f64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59783257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.59783257
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3698170656
Short name T61
Test name
Test status
Simulation time 2300322252 ps
CPU time 11.7 seconds
Started Aug 14 05:23:22 PM PDT 24
Finished Aug 14 05:23:34 PM PDT 24
Peak memory 219380 kb
Host smart-200f3bc1-ab08-4ccd-a7f3-e44f1613e88e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698170656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3698170656
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3569029496
Short name T4
Test name
Test status
Simulation time 223058297 ps
CPU time 10.45 seconds
Started Aug 14 05:23:23 PM PDT 24
Finished Aug 14 05:23:34 PM PDT 24
Peak memory 219408 kb
Host smart-d48f60dc-2c60-4e6c-b094-308755b58aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569029496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3569029496
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1148790499
Short name T164
Test name
Test status
Simulation time 1851428700 ps
CPU time 25.36 seconds
Started Aug 14 05:23:23 PM PDT 24
Finished Aug 14 05:23:48 PM PDT 24
Peak memory 219320 kb
Host smart-6e4ee416-88a4-44e4-b771-6dba63b334cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148790499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1148790499
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3293722438
Short name T248
Test name
Test status
Simulation time 264265316 ps
CPU time 10.06 seconds
Started Aug 14 05:23:33 PM PDT 24
Finished Aug 14 05:23:44 PM PDT 24
Peak memory 218416 kb
Host smart-9edfddd7-b22b-4861-85c9-f1d061e5970f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293722438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3293722438
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.694565381
Short name T44
Test name
Test status
Simulation time 3466592913 ps
CPU time 255.84 seconds
Started Aug 14 05:23:33 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 234924 kb
Host smart-b9a5fd59-f708-478d-86a5-d6522a01eb60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694565381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.694565381
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2876485481
Short name T179
Test name
Test status
Simulation time 988960630 ps
CPU time 22.06 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:53 PM PDT 24
Peak memory 219408 kb
Host smart-d8932633-fc7a-4b06-8f53-9ba82abf8a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876485481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2876485481
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1713058946
Short name T198
Test name
Test status
Simulation time 267029589 ps
CPU time 12.05 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:42 PM PDT 24
Peak memory 219272 kb
Host smart-a42ffc02-9e90-4239-8453-376c9bbcb39f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713058946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1713058946
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2203048063
Short name T67
Test name
Test status
Simulation time 3210147449 ps
CPU time 12.13 seconds
Started Aug 14 05:23:23 PM PDT 24
Finished Aug 14 05:23:35 PM PDT 24
Peak memory 219272 kb
Host smart-30453424-5a16-4d98-b3bb-9c345437a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203048063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2203048063
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3804340520
Short name T56
Test name
Test status
Simulation time 516022514 ps
CPU time 24.33 seconds
Started Aug 14 05:23:25 PM PDT 24
Finished Aug 14 05:23:49 PM PDT 24
Peak memory 219372 kb
Host smart-28d666b2-2c81-4154-9b6e-a975158c8841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804340520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3804340520
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2843397373
Short name T202
Test name
Test status
Simulation time 475428071 ps
CPU time 8.49 seconds
Started Aug 14 05:23:31 PM PDT 24
Finished Aug 14 05:23:39 PM PDT 24
Peak memory 218472 kb
Host smart-fd534e8f-24e5-4d94-a1e7-e0c1976cefb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843397373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2843397373
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1740365906
Short name T125
Test name
Test status
Simulation time 63458760154 ps
CPU time 207.37 seconds
Started Aug 14 05:23:34 PM PDT 24
Finished Aug 14 05:27:01 PM PDT 24
Peak memory 239192 kb
Host smart-6f4a8194-d705-4f74-8067-697ce860ebc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740365906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1740365906
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1955041287
Short name T172
Test name
Test status
Simulation time 661368639 ps
CPU time 22.46 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:53 PM PDT 24
Peak memory 219428 kb
Host smart-071b5457-0de3-4532-b0c7-436be7d58b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955041287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1955041287
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3039286332
Short name T185
Test name
Test status
Simulation time 188030279 ps
CPU time 10.68 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:41 PM PDT 24
Peak memory 219232 kb
Host smart-e345aec5-2996-4837-b3d3-ab581c89da35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039286332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3039286332
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.34203063
Short name T283
Test name
Test status
Simulation time 651016998 ps
CPU time 11 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:42 PM PDT 24
Peak memory 219444 kb
Host smart-f2d29b31-4f22-4502-9ea8-0076532b0108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34203063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.34203063
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1761985285
Short name T294
Test name
Test status
Simulation time 1333465858 ps
CPU time 26.02 seconds
Started Aug 14 05:23:30 PM PDT 24
Finished Aug 14 05:23:57 PM PDT 24
Peak memory 219372 kb
Host smart-1ea63140-4183-43c2-9ce6-fcf5eb2af487
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761985285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1761985285
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.275562580
Short name T69
Test name
Test status
Simulation time 346230230 ps
CPU time 8.4 seconds
Started Aug 14 05:23:40 PM PDT 24
Finished Aug 14 05:23:49 PM PDT 24
Peak memory 218264 kb
Host smart-025bf140-d57b-4112-b6ee-3b3e05d48bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275562580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.275562580
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2998330872
Short name T13
Test name
Test status
Simulation time 1566143215 ps
CPU time 115.86 seconds
Started Aug 14 05:23:39 PM PDT 24
Finished Aug 14 05:25:35 PM PDT 24
Peak memory 236932 kb
Host smart-a1ab75ae-7051-4c69-981d-5e554ef480b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998330872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2998330872
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3921900004
Short name T301
Test name
Test status
Simulation time 2911402149 ps
CPU time 21.8 seconds
Started Aug 14 05:23:39 PM PDT 24
Finished Aug 14 05:24:01 PM PDT 24
Peak memory 219472 kb
Host smart-16b2a9dd-b61c-4d1a-978d-2902db45dbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921900004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3921900004
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1705589631
Short name T228
Test name
Test status
Simulation time 538774945 ps
CPU time 11.97 seconds
Started Aug 14 05:23:38 PM PDT 24
Finished Aug 14 05:23:50 PM PDT 24
Peak memory 219348 kb
Host smart-11c053ee-0a5c-43ef-93dc-55ae5b5476c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705589631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1705589631
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2295141021
Short name T221
Test name
Test status
Simulation time 2838825406 ps
CPU time 11.92 seconds
Started Aug 14 05:23:39 PM PDT 24
Finished Aug 14 05:23:51 PM PDT 24
Peak memory 219436 kb
Host smart-61adeefe-370d-4f5b-824a-60d1c7fa831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295141021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2295141021
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3349812168
Short name T140
Test name
Test status
Simulation time 2350114354 ps
CPU time 23.1 seconds
Started Aug 14 05:23:39 PM PDT 24
Finished Aug 14 05:24:02 PM PDT 24
Peak memory 219460 kb
Host smart-49ec2b78-bc22-4603-9e51-b0654b45946b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349812168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3349812168
Directory /workspace/9.rom_ctrl_stress_all/latest
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