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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.47 96.89 92.28 97.68 100.00 98.62 97.75 99.06


Total test records in report: 459
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T296 /workspace/coverage/default/43.rom_ctrl_alert_test.2818611767 Aug 15 06:12:02 PM PDT 24 Aug 15 06:12:10 PM PDT 24 1178184174 ps
T297 /workspace/coverage/default/11.rom_ctrl_alert_test.1130850655 Aug 15 06:11:47 PM PDT 24 Aug 15 06:11:56 PM PDT 24 514286192 ps
T298 /workspace/coverage/default/5.rom_ctrl_smoke.3109460324 Aug 15 06:11:40 PM PDT 24 Aug 15 06:11:52 PM PDT 24 260720001 ps
T299 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3136499924 Aug 15 06:12:07 PM PDT 24 Aug 15 06:12:25 PM PDT 24 976328989 ps
T300 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1888228225 Aug 15 06:11:46 PM PDT 24 Aug 15 06:12:15 PM PDT 24 4103286910 ps
T301 /workspace/coverage/default/9.rom_ctrl_stress_all.83818955 Aug 15 06:11:50 PM PDT 24 Aug 15 06:12:32 PM PDT 24 2891990964 ps
T302 /workspace/coverage/default/4.rom_ctrl_smoke.924597786 Aug 15 06:11:35 PM PDT 24 Aug 15 06:11:46 PM PDT 24 176756049 ps
T303 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4012230582 Aug 15 06:11:55 PM PDT 24 Aug 15 06:16:39 PM PDT 24 22670004158 ps
T304 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3790567143 Aug 15 06:12:13 PM PDT 24 Aug 15 06:12:22 PM PDT 24 682889453 ps
T305 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2139856612 Aug 15 06:11:55 PM PDT 24 Aug 15 06:16:10 PM PDT 24 19949971817 ps
T306 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.377670731 Aug 15 06:12:15 PM PDT 24 Aug 15 06:12:27 PM PDT 24 1059771756 ps
T307 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1014284213 Aug 15 06:11:44 PM PDT 24 Aug 15 06:16:42 PM PDT 24 5233131531 ps
T308 /workspace/coverage/default/34.rom_ctrl_stress_all.4021500485 Aug 15 06:12:14 PM PDT 24 Aug 15 06:12:37 PM PDT 24 3214457119 ps
T309 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3499157364 Aug 15 06:11:59 PM PDT 24 Aug 15 06:12:11 PM PDT 24 3213238303 ps
T310 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.356571860 Aug 15 06:12:10 PM PDT 24 Aug 15 06:20:07 PM PDT 24 9809556055 ps
T311 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3916798323 Aug 15 06:12:00 PM PDT 24 Aug 15 06:12:19 PM PDT 24 1650891768 ps
T312 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.789416037 Aug 15 06:11:43 PM PDT 24 Aug 15 06:13:32 PM PDT 24 10871930497 ps
T313 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2742377785 Aug 15 06:12:15 PM PDT 24 Aug 15 06:14:18 PM PDT 24 2658096535 ps
T314 /workspace/coverage/default/36.rom_ctrl_stress_all.455723077 Aug 15 06:11:58 PM PDT 24 Aug 15 06:12:24 PM PDT 24 510543828 ps
T315 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1097591753 Aug 15 06:11:58 PM PDT 24 Aug 15 06:14:04 PM PDT 24 6494051258 ps
T316 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1879322353 Aug 15 06:12:07 PM PDT 24 Aug 15 06:18:48 PM PDT 24 33483760231 ps
T317 /workspace/coverage/default/22.rom_ctrl_stress_all.836150340 Aug 15 06:11:52 PM PDT 24 Aug 15 06:12:19 PM PDT 24 773729363 ps
T318 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1498714403 Aug 15 06:12:03 PM PDT 24 Aug 15 06:12:21 PM PDT 24 1500402313 ps
T319 /workspace/coverage/default/10.rom_ctrl_alert_test.598503156 Aug 15 06:11:49 PM PDT 24 Aug 15 06:11:58 PM PDT 24 1081663351 ps
T320 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3434779448 Aug 15 06:13:30 PM PDT 24 Aug 15 06:18:19 PM PDT 24 17852774508 ps
T321 /workspace/coverage/default/3.rom_ctrl_alert_test.758231642 Aug 15 06:11:42 PM PDT 24 Aug 15 06:11:52 PM PDT 24 1035094167 ps
T322 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1862369579 Aug 15 06:11:50 PM PDT 24 Aug 15 06:15:49 PM PDT 24 4074238236 ps
T323 /workspace/coverage/default/49.rom_ctrl_alert_test.2486858559 Aug 15 06:12:07 PM PDT 24 Aug 15 06:12:17 PM PDT 24 917739897 ps
T324 /workspace/coverage/default/30.rom_ctrl_stress_all.1011169517 Aug 15 06:12:06 PM PDT 24 Aug 15 06:12:24 PM PDT 24 692171541 ps
T325 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3960028909 Aug 15 06:12:04 PM PDT 24 Aug 15 06:13:42 PM PDT 24 9030829709 ps
T326 /workspace/coverage/default/26.rom_ctrl_alert_test.794861956 Aug 15 06:12:07 PM PDT 24 Aug 15 06:12:16 PM PDT 24 266140036 ps
T327 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1897751864 Aug 15 06:11:46 PM PDT 24 Aug 15 06:13:48 PM PDT 24 3235515124 ps
T328 /workspace/coverage/default/19.rom_ctrl_alert_test.3946313375 Aug 15 06:12:00 PM PDT 24 Aug 15 06:12:07 PM PDT 24 826787693 ps
T329 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.571027719 Aug 15 06:11:42 PM PDT 24 Aug 15 06:12:24 PM PDT 24 5884191531 ps
T330 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3522182591 Aug 15 06:12:10 PM PDT 24 Aug 15 06:12:28 PM PDT 24 3299970553 ps
T331 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4159504912 Aug 15 06:12:16 PM PDT 24 Aug 15 06:13:35 PM PDT 24 2050692988 ps
T332 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4191463938 Aug 15 06:11:39 PM PDT 24 Aug 15 06:11:51 PM PDT 24 2552981080 ps
T333 /workspace/coverage/default/20.rom_ctrl_stress_all.642387636 Aug 15 06:12:00 PM PDT 24 Aug 15 06:12:30 PM PDT 24 744603164 ps
T334 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1253990764 Aug 15 06:11:45 PM PDT 24 Aug 15 06:11:57 PM PDT 24 265969618 ps
T335 /workspace/coverage/default/10.rom_ctrl_stress_all.1379942122 Aug 15 06:11:45 PM PDT 24 Aug 15 06:12:06 PM PDT 24 2967703792 ps
T12 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.437242015 Aug 15 06:11:37 PM PDT 24 Aug 15 06:14:10 PM PDT 24 18450691217 ps
T336 /workspace/coverage/default/47.rom_ctrl_alert_test.1729465394 Aug 15 06:12:23 PM PDT 24 Aug 15 06:12:32 PM PDT 24 167791217 ps
T337 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2808599989 Aug 15 06:11:42 PM PDT 24 Aug 15 06:14:29 PM PDT 24 49451974158 ps
T338 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3328063027 Aug 15 06:12:14 PM PDT 24 Aug 15 06:12:27 PM PDT 24 1089767492 ps
T339 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.913091751 Aug 15 06:11:57 PM PDT 24 Aug 15 06:14:42 PM PDT 24 7111563078 ps
T340 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1623153816 Aug 15 06:12:12 PM PDT 24 Aug 15 06:15:31 PM PDT 24 7999762202 ps
T341 /workspace/coverage/default/35.rom_ctrl_alert_test.3616896152 Aug 15 06:12:16 PM PDT 24 Aug 15 06:12:26 PM PDT 24 1074917043 ps
T342 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2107899241 Aug 15 06:11:54 PM PDT 24 Aug 15 06:16:07 PM PDT 24 34529034484 ps
T343 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.26022481 Aug 15 06:12:02 PM PDT 24 Aug 15 06:12:13 PM PDT 24 1069614217 ps
T344 /workspace/coverage/default/0.rom_ctrl_alert_test.2584041666 Aug 15 06:11:45 PM PDT 24 Aug 15 06:11:54 PM PDT 24 1455028387 ps
T345 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4199195760 Aug 15 06:11:49 PM PDT 24 Aug 15 06:15:10 PM PDT 24 16723111029 ps
T346 /workspace/coverage/default/7.rom_ctrl_alert_test.3189696959 Aug 15 06:11:55 PM PDT 24 Aug 15 06:12:05 PM PDT 24 2255555008 ps
T347 /workspace/coverage/default/14.rom_ctrl_stress_all.1913450292 Aug 15 06:11:45 PM PDT 24 Aug 15 06:12:08 PM PDT 24 1425733289 ps
T348 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.347177842 Aug 15 06:11:55 PM PDT 24 Aug 15 06:12:10 PM PDT 24 4000393770 ps
T349 /workspace/coverage/default/34.rom_ctrl_alert_test.720116541 Aug 15 06:12:04 PM PDT 24 Aug 15 06:12:13 PM PDT 24 506237945 ps
T350 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2312124220 Aug 15 06:11:52 PM PDT 24 Aug 15 06:12:11 PM PDT 24 332496311 ps
T351 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3910697367 Aug 15 06:12:13 PM PDT 24 Aug 15 06:12:23 PM PDT 24 180689480 ps
T352 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3504662526 Aug 15 06:12:52 PM PDT 24 Aug 15 06:13:22 PM PDT 24 3940372457 ps
T353 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3248617143 Aug 15 06:12:09 PM PDT 24 Aug 15 06:13:36 PM PDT 24 2246146982 ps
T354 /workspace/coverage/default/2.rom_ctrl_alert_test.1670859107 Aug 15 06:11:37 PM PDT 24 Aug 15 06:11:47 PM PDT 24 262141058 ps
T355 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2040529204 Aug 15 06:11:48 PM PDT 24 Aug 15 06:14:37 PM PDT 24 8692599838 ps
T356 /workspace/coverage/default/37.rom_ctrl_alert_test.3155963471 Aug 15 06:12:17 PM PDT 24 Aug 15 06:12:27 PM PDT 24 250144931 ps
T357 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.495757592 Aug 15 06:11:36 PM PDT 24 Aug 15 06:14:31 PM PDT 24 10549964829 ps
T358 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.751795654 Aug 15 06:12:18 PM PDT 24 Aug 15 06:14:58 PM PDT 24 2838464262 ps
T52 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3170458717 Aug 15 05:52:59 PM PDT 24 Aug 15 05:55:33 PM PDT 24 833586625 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3082935020 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:56 PM PDT 24 539903148 ps
T56 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2464035873 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:53 PM PDT 24 270850403 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2030328238 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:54 PM PDT 24 1375734525 ps
T359 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4033380749 Aug 15 05:52:41 PM PDT 24 Aug 15 05:52:49 PM PDT 24 325495950 ps
T53 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2619225003 Aug 15 05:52:48 PM PDT 24 Aug 15 05:54:07 PM PDT 24 226853671 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2734133872 Aug 15 05:52:44 PM PDT 24 Aug 15 05:53:27 PM PDT 24 2119170518 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2012530977 Aug 15 05:52:45 PM PDT 24 Aug 15 05:53:00 PM PDT 24 180309770 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2984468171 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:52 PM PDT 24 497463454 ps
T65 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2557056347 Aug 15 05:52:55 PM PDT 24 Aug 15 05:53:59 PM PDT 24 1606396521 ps
T90 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2152283287 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:53 PM PDT 24 687707595 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.713679894 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:59 PM PDT 24 984032795 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3436491375 Aug 15 05:53:15 PM PDT 24 Aug 15 05:53:25 PM PDT 24 1899840445 ps
T360 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1525378061 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:54 PM PDT 24 275662179 ps
T361 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.509401335 Aug 15 05:52:47 PM PDT 24 Aug 15 05:52:56 PM PDT 24 1220734833 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1650742275 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:51 PM PDT 24 976444857 ps
T95 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1566521745 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:54 PM PDT 24 397201873 ps
T54 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1129184079 Aug 15 05:52:47 PM PDT 24 Aug 15 05:55:21 PM PDT 24 325500673 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3126540609 Aug 15 05:52:53 PM PDT 24 Aug 15 05:53:03 PM PDT 24 3526335717 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1768594087 Aug 15 05:52:51 PM PDT 24 Aug 15 05:53:27 PM PDT 24 2766985456 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1743380018 Aug 15 05:52:52 PM PDT 24 Aug 15 05:55:27 PM PDT 24 1338968569 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.175299456 Aug 15 05:53:10 PM PDT 24 Aug 15 05:53:19 PM PDT 24 496941944 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2776881306 Aug 15 05:52:41 PM PDT 24 Aug 15 05:52:51 PM PDT 24 1074619053 ps
T70 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1152154473 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:59 PM PDT 24 4102814133 ps
T362 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.821853761 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:52 PM PDT 24 179650195 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2284104100 Aug 15 05:52:44 PM PDT 24 Aug 15 05:54:05 PM PDT 24 1385670549 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1633744049 Aug 15 05:52:43 PM PDT 24 Aug 15 05:55:15 PM PDT 24 1237082227 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2502226094 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:51 PM PDT 24 4928954573 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1479561090 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:50 PM PDT 24 176483353 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1320159608 Aug 15 05:52:44 PM PDT 24 Aug 15 05:54:13 PM PDT 24 642031686 ps
T79 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2375179557 Aug 15 05:52:47 PM PDT 24 Aug 15 05:53:24 PM PDT 24 3110504961 ps
T363 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.405194165 Aug 15 05:52:44 PM PDT 24 Aug 15 05:52:54 PM PDT 24 506555592 ps
T364 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2535875676 Aug 15 05:53:00 PM PDT 24 Aug 15 05:53:10 PM PDT 24 4255470573 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.928286385 Aug 15 05:52:39 PM PDT 24 Aug 15 05:52:48 PM PDT 24 174625258 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.397500783 Aug 15 05:52:32 PM PDT 24 Aug 15 05:52:47 PM PDT 24 701248157 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3425201397 Aug 15 05:52:48 PM PDT 24 Aug 15 05:53:24 PM PDT 24 711648899 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.354587615 Aug 15 05:52:49 PM PDT 24 Aug 15 05:53:16 PM PDT 24 3139106896 ps
T81 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.718910534 Aug 15 05:52:44 PM PDT 24 Aug 15 05:53:27 PM PDT 24 1060783958 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3677777507 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:56 PM PDT 24 1034071175 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4015154721 Aug 15 05:53:02 PM PDT 24 Aug 15 05:53:12 PM PDT 24 272694153 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2319736821 Aug 15 05:52:44 PM PDT 24 Aug 15 05:52:53 PM PDT 24 174312696 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.161721219 Aug 15 05:52:45 PM PDT 24 Aug 15 05:53:21 PM PDT 24 710173015 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.851457021 Aug 15 05:52:33 PM PDT 24 Aug 15 05:52:43 PM PDT 24 1079640200 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.542256914 Aug 15 05:52:44 PM PDT 24 Aug 15 05:55:22 PM PDT 24 505624744 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.868114873 Aug 15 05:53:02 PM PDT 24 Aug 15 05:53:13 PM PDT 24 1081014031 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.787655349 Aug 15 05:52:54 PM PDT 24 Aug 15 05:53:07 PM PDT 24 174519439 ps
T374 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.172353608 Aug 15 05:52:50 PM PDT 24 Aug 15 05:53:00 PM PDT 24 262329128 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1088925682 Aug 15 05:52:42 PM PDT 24 Aug 15 05:53:36 PM PDT 24 1065651699 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2020736461 Aug 15 05:52:34 PM PDT 24 Aug 15 05:52:46 PM PDT 24 1035308482 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1506985594 Aug 15 05:52:41 PM PDT 24 Aug 15 05:52:49 PM PDT 24 174678369 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3930110089 Aug 15 05:52:40 PM PDT 24 Aug 15 05:52:49 PM PDT 24 340709754 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.504196866 Aug 15 05:52:52 PM PDT 24 Aug 15 05:54:13 PM PDT 24 815322218 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.34031839 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:54 PM PDT 24 976032122 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.684569103 Aug 15 05:52:32 PM PDT 24 Aug 15 05:53:54 PM PDT 24 1148384787 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4059302072 Aug 15 05:52:50 PM PDT 24 Aug 15 05:53:04 PM PDT 24 3976590613 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3993806422 Aug 15 05:52:41 PM PDT 24 Aug 15 05:55:14 PM PDT 24 374844907 ps
T83 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2650632316 Aug 15 05:52:48 PM PDT 24 Aug 15 05:53:50 PM PDT 24 6334023541 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2281004899 Aug 15 05:52:44 PM PDT 24 Aug 15 05:52:54 PM PDT 24 1375431345 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.423483017 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:52 PM PDT 24 249376464 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3953206446 Aug 15 05:52:59 PM PDT 24 Aug 15 05:53:09 PM PDT 24 1030465970 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1247251652 Aug 15 05:52:49 PM PDT 24 Aug 15 05:53:31 PM PDT 24 4223306950 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1522284172 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:54 PM PDT 24 174402962 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3237914998 Aug 15 05:52:33 PM PDT 24 Aug 15 05:52:41 PM PDT 24 173668157 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3581277461 Aug 15 05:52:46 PM PDT 24 Aug 15 05:54:13 PM PDT 24 1095761563 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1254184525 Aug 15 05:52:56 PM PDT 24 Aug 15 05:53:08 PM PDT 24 640163963 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1512564163 Aug 15 05:52:42 PM PDT 24 Aug 15 05:55:18 PM PDT 24 3064552183 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1563912571 Aug 15 05:53:02 PM PDT 24 Aug 15 05:53:10 PM PDT 24 176502138 ps
T84 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3693730571 Aug 15 05:52:46 PM PDT 24 Aug 15 05:53:39 PM PDT 24 2102242828 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.341596636 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:56 PM PDT 24 175423917 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.145842321 Aug 15 05:52:41 PM PDT 24 Aug 15 05:54:01 PM PDT 24 1406351396 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2677101987 Aug 15 05:52:54 PM PDT 24 Aug 15 05:53:04 PM PDT 24 508813588 ps
T392 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2394221635 Aug 15 05:53:12 PM PDT 24 Aug 15 05:53:25 PM PDT 24 172500987 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1514256527 Aug 15 05:52:47 PM PDT 24 Aug 15 05:54:08 PM PDT 24 918058113 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.90605923 Aug 15 05:52:52 PM PDT 24 Aug 15 05:53:36 PM PDT 24 9254378546 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3427683292 Aug 15 05:52:52 PM PDT 24 Aug 15 05:53:02 PM PDT 24 591482653 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2938017644 Aug 15 05:52:50 PM PDT 24 Aug 15 05:53:00 PM PDT 24 2227430541 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.29494677 Aug 15 05:52:42 PM PDT 24 Aug 15 05:55:12 PM PDT 24 764480231 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.993264729 Aug 15 05:52:41 PM PDT 24 Aug 15 05:52:53 PM PDT 24 290902426 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2298226842 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:55 PM PDT 24 309057811 ps
T399 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3832604411 Aug 15 05:53:01 PM PDT 24 Aug 15 05:53:11 PM PDT 24 1032484550 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1470599689 Aug 15 05:52:38 PM PDT 24 Aug 15 05:52:51 PM PDT 24 252773893 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3862435132 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:53 PM PDT 24 171413133 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1793073416 Aug 15 05:52:47 PM PDT 24 Aug 15 05:52:56 PM PDT 24 991500535 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1539738490 Aug 15 05:52:58 PM PDT 24 Aug 15 05:53:06 PM PDT 24 320356001 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1359286022 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:50 PM PDT 24 971784928 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2611955929 Aug 15 05:52:35 PM PDT 24 Aug 15 05:52:44 PM PDT 24 250160354 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3694662426 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:55 PM PDT 24 187431176 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2765558048 Aug 15 05:52:58 PM PDT 24 Aug 15 05:53:06 PM PDT 24 170372991 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2524456145 Aug 15 05:52:52 PM PDT 24 Aug 15 05:53:04 PM PDT 24 248402832 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2163087753 Aug 15 05:52:30 PM PDT 24 Aug 15 05:52:38 PM PDT 24 336889313 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1831987080 Aug 15 05:52:39 PM PDT 24 Aug 15 05:52:47 PM PDT 24 167715387 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1991794012 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:59 PM PDT 24 993263877 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1017007911 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:57 PM PDT 24 265499972 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2083130259 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:56 PM PDT 24 254270590 ps
T87 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3625212891 Aug 15 05:52:46 PM PDT 24 Aug 15 05:53:27 PM PDT 24 1016506398 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.501283299 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:58 PM PDT 24 1128579248 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1965654980 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:55 PM PDT 24 408605786 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1792107149 Aug 15 05:52:48 PM PDT 24 Aug 15 05:52:57 PM PDT 24 254964558 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2272998621 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:50 PM PDT 24 174783695 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4273827088 Aug 15 05:52:37 PM PDT 24 Aug 15 05:52:46 PM PDT 24 1074039761 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2174686728 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:51 PM PDT 24 688335280 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3299768664 Aug 15 05:52:54 PM PDT 24 Aug 15 05:53:02 PM PDT 24 167637547 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.370163446 Aug 15 05:52:44 PM PDT 24 Aug 15 05:53:21 PM PDT 24 708175633 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1045455409 Aug 15 05:53:02 PM PDT 24 Aug 15 05:55:36 PM PDT 24 415810305 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1318017953 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:51 PM PDT 24 174534386 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3196930889 Aug 15 05:52:39 PM PDT 24 Aug 15 05:52:49 PM PDT 24 262707143 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2225266095 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:57 PM PDT 24 518090567 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3445607720 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:54 PM PDT 24 259866472 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.370295301 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:55 PM PDT 24 691907022 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.728082804 Aug 15 05:52:53 PM PDT 24 Aug 15 05:53:01 PM PDT 24 719012442 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1778686969 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:54 PM PDT 24 353739674 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1566012057 Aug 15 05:52:47 PM PDT 24 Aug 15 05:53:01 PM PDT 24 1027746202 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.822959612 Aug 15 05:52:48 PM PDT 24 Aug 15 05:53:01 PM PDT 24 1456539444 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1919702642 Aug 15 05:52:41 PM PDT 24 Aug 15 05:53:18 PM PDT 24 2868833362 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2455044030 Aug 15 05:52:42 PM PDT 24 Aug 15 05:52:52 PM PDT 24 954429279 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4056002013 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:55 PM PDT 24 994038311 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2074482897 Aug 15 05:52:46 PM PDT 24 Aug 15 05:54:07 PM PDT 24 685287707 ps
T435 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3521333183 Aug 15 05:52:47 PM PDT 24 Aug 15 05:53:02 PM PDT 24 9139631468 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3559611372 Aug 15 05:52:58 PM PDT 24 Aug 15 05:53:08 PM PDT 24 283087722 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.198027193 Aug 15 05:52:48 PM PDT 24 Aug 15 05:52:57 PM PDT 24 253900116 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1951211604 Aug 15 05:52:41 PM PDT 24 Aug 15 05:52:49 PM PDT 24 167738842 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.768522286 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:55 PM PDT 24 1831978148 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1860100755 Aug 15 05:52:40 PM PDT 24 Aug 15 05:52:48 PM PDT 24 199605402 ps
T440 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2441830659 Aug 15 05:52:45 PM PDT 24 Aug 15 05:54:06 PM PDT 24 463559421 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1810534720 Aug 15 05:52:33 PM PDT 24 Aug 15 05:52:42 PM PDT 24 994822288 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3314001971 Aug 15 05:52:43 PM PDT 24 Aug 15 05:54:15 PM PDT 24 6072407147 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1125521701 Aug 15 05:52:47 PM PDT 24 Aug 15 05:53:00 PM PDT 24 689539615 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2047982340 Aug 15 05:52:47 PM PDT 24 Aug 15 05:52:55 PM PDT 24 177940491 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1599264498 Aug 15 05:52:43 PM PDT 24 Aug 15 05:53:47 PM PDT 24 1586985495 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3920715195 Aug 15 05:52:55 PM PDT 24 Aug 15 05:53:47 PM PDT 24 5146234093 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3406208853 Aug 15 05:53:01 PM PDT 24 Aug 15 05:53:11 PM PDT 24 526674505 ps
T446 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1332492680 Aug 15 05:52:39 PM PDT 24 Aug 15 05:52:52 PM PDT 24 251698761 ps
T447 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.794258933 Aug 15 05:52:46 PM PDT 24 Aug 15 05:53:00 PM PDT 24 1452106531 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3292887326 Aug 15 05:52:45 PM PDT 24 Aug 15 05:52:53 PM PDT 24 969971767 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4271027862 Aug 15 05:52:58 PM PDT 24 Aug 15 05:53:08 PM PDT 24 991666028 ps
T450 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1093142606 Aug 15 05:53:12 PM PDT 24 Aug 15 05:53:25 PM PDT 24 171096224 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3028860082 Aug 15 05:53:01 PM PDT 24 Aug 15 05:54:22 PM PDT 24 1710242162 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3218005194 Aug 15 05:52:47 PM PDT 24 Aug 15 05:53:29 PM PDT 24 1025580720 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2866288635 Aug 15 05:52:48 PM PDT 24 Aug 15 05:53:01 PM PDT 24 268348722 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3752528643 Aug 15 05:52:43 PM PDT 24 Aug 15 05:52:53 PM PDT 24 260533266 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4138224986 Aug 15 05:52:51 PM PDT 24 Aug 15 05:53:00 PM PDT 24 175679791 ps
T456 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2529549487 Aug 15 05:52:44 PM PDT 24 Aug 15 05:52:54 PM PDT 24 259658474 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2173073090 Aug 15 05:52:45 PM PDT 24 Aug 15 05:53:21 PM PDT 24 2384231330 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2350287998 Aug 15 05:52:53 PM PDT 24 Aug 15 05:53:02 PM PDT 24 171361273 ps
T459 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.903814965 Aug 15 05:52:46 PM PDT 24 Aug 15 05:52:54 PM PDT 24 670746848 ps

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.479194475
Short name T9
Test name
Test status
Simulation time 4232173423 ps
CPU time 170.48 seconds
Started Aug 15 06:11:56 PM PDT 24
Finished Aug 15 06:14:47 PM PDT 24
Peak memory 228092 kb
Host smart-457a0b8c-76ed-416d-938e-7b1029efb8a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479194475 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.479194475
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3231998939
Short name T10
Test name
Test status
Simulation time 34748231143 ps
CPU time 213.01 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:15:30 PM PDT 24
Peak memory 243368 kb
Host smart-5d7d673c-73a4-47c4-849f-5b1c6e113db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231998939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3231998939
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3537422999
Short name T23
Test name
Test status
Simulation time 2466129267 ps
CPU time 21.73 seconds
Started Aug 15 06:11:59 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 218968 kb
Host smart-c225fc42-4885-4baf-8530-68002d99788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537422999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3537422999
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1129184079
Short name T54
Test name
Test status
Simulation time 325500673 ps
CPU time 153.75 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:55:21 PM PDT 24
Peak memory 213884 kb
Host smart-a5c3ef2b-c763-4275-be63-b06e21c946d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129184079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1129184079
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.804828711
Short name T58
Test name
Test status
Simulation time 209057076 ps
CPU time 17.92 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:07 PM PDT 24
Peak memory 219200 kb
Host smart-edc63169-726e-4078-8c3b-d41d2816ab52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804828711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.804828711
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.532710494
Short name T26
Test name
Test status
Simulation time 471000173 ps
CPU time 228.08 seconds
Started Aug 15 06:11:41 PM PDT 24
Finished Aug 15 06:15:29 PM PDT 24
Peak memory 238344 kb
Host smart-6a1ba699-8a80-41a6-970c-d5266fec82d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532710494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.532710494
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2557056347
Short name T65
Test name
Test status
Simulation time 1606396521 ps
CPU time 63.87 seconds
Started Aug 15 05:52:55 PM PDT 24
Finished Aug 15 05:53:59 PM PDT 24
Peak memory 215520 kb
Host smart-99ff15f3-2e3a-44c1-a314-e22e486c09d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557056347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2557056347
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4101162654
Short name T57
Test name
Test status
Simulation time 1046281935 ps
CPU time 13.59 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218384 kb
Host smart-578f6ec0-e836-457d-8998-0de62e470c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101162654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4101162654
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3993806422
Short name T107
Test name
Test status
Simulation time 374844907 ps
CPU time 152.88 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:55:14 PM PDT 24
Peak memory 219588 kb
Host smart-a3a09799-8be0-446a-b9ae-f594e73ae47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993806422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3993806422
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3420359869
Short name T115
Test name
Test status
Simulation time 5050439940 ps
CPU time 97.5 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:13:24 PM PDT 24
Peak memory 226128 kb
Host smart-02e077bf-2839-4fef-8440-f60c02645ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420359869 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3420359869
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2391492835
Short name T17
Test name
Test status
Simulation time 4709920010 ps
CPU time 18.78 seconds
Started Aug 15 06:11:56 PM PDT 24
Finished Aug 15 06:12:15 PM PDT 24
Peak memory 219000 kb
Host smart-8abfb9f5-c33e-4cc8-8e18-c647c15bf005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391492835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2391492835
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2553885506
Short name T22
Test name
Test status
Simulation time 3792146949 ps
CPU time 28.97 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 219224 kb
Host smart-d5527c86-c2d6-4459-850a-b44b22ea371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553885506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2553885506
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1045455409
Short name T106
Test name
Test status
Simulation time 415810305 ps
CPU time 153.58 seconds
Started Aug 15 05:53:02 PM PDT 24
Finished Aug 15 05:55:36 PM PDT 24
Peak memory 219552 kb
Host smart-66d66e8a-2ab3-4abf-abdd-c10d357ae2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045455409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1045455409
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3256131089
Short name T59
Test name
Test status
Simulation time 563802493 ps
CPU time 16.16 seconds
Started Aug 15 06:12:46 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 219148 kb
Host smart-3de37340-ab11-4569-a0b2-67ad906c92ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256131089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3256131089
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.29494677
Short name T396
Test name
Test status
Simulation time 764480231 ps
CPU time 149.47 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:55:12 PM PDT 24
Peak memory 213576 kb
Host smart-b46c8ea8-dee1-4b36-90a2-da4ae8418132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29494677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.29494677
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.437242015
Short name T12
Test name
Test status
Simulation time 18450691217 ps
CPU time 153 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:14:10 PM PDT 24
Peak memory 235620 kb
Host smart-196eb7bd-cb11-4359-bf88-77c1e818fd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437242015 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.437242015
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1506985594
Short name T377
Test name
Test status
Simulation time 174678369 ps
CPU time 7.91 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 211692 kb
Host smart-e0eb4f3f-e31d-4c45-bcdc-68c744fc243e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506985594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1506985594
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1860100755
Short name T439
Test name
Test status
Simulation time 199605402 ps
CPU time 8.01 seconds
Started Aug 15 05:52:40 PM PDT 24
Finished Aug 15 05:52:48 PM PDT 24
Peak memory 211424 kb
Host smart-34a23203-9289-4c12-88bc-bfaefaa154b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860100755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1860100755
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1470599689
Short name T400
Test name
Test status
Simulation time 252773893 ps
CPU time 13.16 seconds
Started Aug 15 05:52:38 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 211428 kb
Host smart-5034e697-a994-49bc-8974-55e213af10f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470599689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1470599689
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2163087753
Short name T409
Test name
Test status
Simulation time 336889313 ps
CPU time 8.18 seconds
Started Aug 15 05:52:30 PM PDT 24
Finished Aug 15 05:52:38 PM PDT 24
Peak memory 216204 kb
Host smart-c96caf89-642c-4591-83e1-ea475e7e76ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163087753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2163087753
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1359286022
Short name T404
Test name
Test status
Simulation time 971784928 ps
CPU time 7.76 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:50 PM PDT 24
Peak memory 212020 kb
Host smart-7a45821d-6b7e-4007-a53e-4f57a4b345f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359286022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1359286022
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2272998621
Short name T417
Test name
Test status
Simulation time 174783695 ps
CPU time 7.82 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:50 PM PDT 24
Peak memory 211292 kb
Host smart-c5f901bd-17ea-410c-81c6-848f25756a00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272998621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2272998621
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4273827088
Short name T418
Test name
Test status
Simulation time 1074039761 ps
CPU time 9.36 seconds
Started Aug 15 05:52:37 PM PDT 24
Finished Aug 15 05:52:46 PM PDT 24
Peak memory 211320 kb
Host smart-6928e704-fa8c-4f4b-8d8d-d9ddf314e3ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273827088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4273827088
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1919702642
Short name T431
Test name
Test status
Simulation time 2868833362 ps
CPU time 36.39 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:53:18 PM PDT 24
Peak memory 214612 kb
Host smart-3f496fac-f050-4308-83dd-70e237a2fcff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919702642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1919702642
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1831987080
Short name T410
Test name
Test status
Simulation time 167715387 ps
CPU time 7.74 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 212132 kb
Host smart-c656ca09-1507-40c1-9f07-11d357b171c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831987080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1831987080
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.34031839
Short name T380
Test name
Test status
Simulation time 976032122 ps
CPU time 11.34 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 217988 kb
Host smart-157b0e7d-6a71-403e-8d4c-2de739d11320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.34031839
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1650742275
Short name T94
Test name
Test status
Simulation time 976444857 ps
CPU time 7.97 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 211400 kb
Host smart-720bff10-e050-4541-a46b-ef85f7bf39ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650742275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1650742275
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1539738490
Short name T403
Test name
Test status
Simulation time 320356001 ps
CPU time 7.92 seconds
Started Aug 15 05:52:58 PM PDT 24
Finished Aug 15 05:53:06 PM PDT 24
Peak memory 211424 kb
Host smart-992f9954-1520-4f2b-8ef7-d8c51ac84ac4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539738490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1539738490
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.397500783
Short name T80
Test name
Test status
Simulation time 701248157 ps
CPU time 14.71 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:52:47 PM PDT 24
Peak memory 212864 kb
Host smart-f2644d6d-593b-41fa-9087-fa685a1fa362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397500783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.397500783
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3082935020
Short name T55
Test name
Test status
Simulation time 539903148 ps
CPU time 10.88 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 219652 kb
Host smart-d9e5ddfd-6050-404b-8d16-8cad6fee30ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082935020 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3082935020
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1951211604
Short name T82
Test name
Test status
Simulation time 167738842 ps
CPU time 7.82 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 211492 kb
Host smart-abb299d0-edc4-4a1e-99ab-92c544ce1c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951211604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1951211604
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.198027193
Short name T437
Test name
Test status
Simulation time 253900116 ps
CPU time 9.27 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:52:57 PM PDT 24
Peak memory 211284 kb
Host smart-c1f0fdd4-fe97-4b15-be7f-7dd0fd321a47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198027193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.198027193
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.423483017
Short name T383
Test name
Test status
Simulation time 249376464 ps
CPU time 9.15 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:52 PM PDT 24
Peak memory 211372 kb
Host smart-aa48da4e-8c61-4bfd-9f13-09228ae8ebfa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423483017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
423483017
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1088925682
Short name T375
Test name
Test status
Simulation time 1065651699 ps
CPU time 54.23 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:53:36 PM PDT 24
Peak memory 214464 kb
Host smart-da98b068-9a87-40c8-95da-567957154270
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088925682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1088925682
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.768522286
Short name T438
Test name
Test status
Simulation time 1831978148 ps
CPU time 7.96 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 212296 kb
Host smart-7cad20a4-1761-4e67-a6b0-1bb722945ae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768522286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.768522286
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2020736461
Short name T376
Test name
Test status
Simulation time 1035308482 ps
CPU time 12.08 seconds
Started Aug 15 05:52:34 PM PDT 24
Finished Aug 15 05:52:46 PM PDT 24
Peak memory 218028 kb
Host smart-8b88f302-7b94-44a6-b78f-5e6987888294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020736461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2020736461
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.145842321
Short name T113
Test name
Test status
Simulation time 1406351396 ps
CPU time 79.35 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:54:01 PM PDT 24
Peak memory 213188 kb
Host smart-9ec21e5d-016c-4f2d-b8e3-34e491747e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145842321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.145842321
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.821853761
Short name T362
Test name
Test status
Simulation time 179650195 ps
CPU time 8.91 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:52 PM PDT 24
Peak memory 217820 kb
Host smart-54378748-2d0e-4d77-bd38-0e91616a1130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821853761 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.821853761
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1152154473
Short name T70
Test name
Test status
Simulation time 4102814133 ps
CPU time 13.28 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:59 PM PDT 24
Peak memory 211516 kb
Host smart-f1118852-1d62-4451-8e3a-b8b284e79f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152154473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1152154473
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3218005194
Short name T452
Test name
Test status
Simulation time 1025580720 ps
CPU time 41.67 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:53:29 PM PDT 24
Peak memory 214448 kb
Host smart-661db47a-250b-45a0-8657-16b85ed7caaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218005194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3218005194
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3292887326
Short name T448
Test name
Test status
Simulation time 969971767 ps
CPU time 7.73 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 212024 kb
Host smart-5e72ad88-efeb-40bd-ae5c-5d22929bd46b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292887326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3292887326
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2083130259
Short name T413
Test name
Test status
Simulation time 254270590 ps
CPU time 13.81 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 218216 kb
Host smart-bb2d3d6c-d90c-4423-8ad9-36452986aef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083130259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2083130259
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2765558048
Short name T407
Test name
Test status
Simulation time 170372991 ps
CPU time 8.03 seconds
Started Aug 15 05:52:58 PM PDT 24
Finished Aug 15 05:53:06 PM PDT 24
Peak memory 213912 kb
Host smart-7bf572f2-5f92-4c43-97d4-9b28c4eb8880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765558048 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2765558048
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2776881306
Short name T69
Test name
Test status
Simulation time 1074619053 ps
CPU time 9.19 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 211956 kb
Host smart-c25e4889-3c69-4e12-b64d-53c30752a54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776881306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2776881306
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3693730571
Short name T84
Test name
Test status
Simulation time 2102242828 ps
CPU time 53.44 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:53:39 PM PDT 24
Peak memory 214452 kb
Host smart-6aae5f3d-6c3e-4e56-964f-bf4a2e6cee00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693730571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3693730571
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.993264729
Short name T397
Test name
Test status
Simulation time 290902426 ps
CPU time 11.74 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 213260 kb
Host smart-4c9d7a73-9fa4-4476-8309-c9e21ddbc232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993264729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.993264729
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2524456145
Short name T408
Test name
Test status
Simulation time 248402832 ps
CPU time 11.97 seconds
Started Aug 15 05:52:52 PM PDT 24
Finished Aug 15 05:53:04 PM PDT 24
Peak memory 217960 kb
Host smart-56547b98-0268-4f24-8478-efaf424b5144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524456145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2524456145
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.903814965
Short name T459
Test name
Test status
Simulation time 670746848 ps
CPU time 8 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 216204 kb
Host smart-f4743d6b-9143-4735-9795-0aa96b63b1c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903814965 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.903814965
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4056002013
Short name T433
Test name
Test status
Simulation time 994038311 ps
CPU time 9.3 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 211868 kb
Host smart-f267434c-8398-488b-af65-c847c0bfcba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056002013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4056002013
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.718910534
Short name T81
Test name
Test status
Simulation time 1060783958 ps
CPU time 42.02 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:53:27 PM PDT 24
Peak memory 214504 kb
Host smart-af737a3a-06dc-4747-9e94-8b1a2a2c7b2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718910534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.718910534
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2152283287
Short name T90
Test name
Test status
Simulation time 687707595 ps
CPU time 7.93 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 211760 kb
Host smart-951a082f-f12d-4bec-9d9c-b56a743e1a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152283287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2152283287
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1017007911
Short name T412
Test name
Test status
Simulation time 265499972 ps
CPU time 10.74 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:57 PM PDT 24
Peak memory 218092 kb
Host smart-e58e665a-ac94-4851-a478-c1289e52111a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017007911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1017007911
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3581277461
Short name T111
Test name
Test status
Simulation time 1095761563 ps
CPU time 86.91 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:54:13 PM PDT 24
Peak memory 214156 kb
Host smart-52d403c9-c155-488e-8428-e500adb904a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581277461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3581277461
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3521333183
Short name T435
Test name
Test status
Simulation time 9139631468 ps
CPU time 14.74 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:53:02 PM PDT 24
Peak memory 218672 kb
Host smart-8f661ddf-7bcd-4efb-ac39-eedaf69d2c1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521333183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3521333183
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2298226842
Short name T398
Test name
Test status
Simulation time 309057811 ps
CPU time 7.93 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 212020 kb
Host smart-87bf627b-82e5-4b66-8a1b-2a9119bdc37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298226842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2298226842
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1599264498
Short name T88
Test name
Test status
Simulation time 1586985495 ps
CPU time 63.63 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:53:47 PM PDT 24
Peak memory 216548 kb
Host smart-44d371df-e068-4967-a840-e81257cdc00c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599264498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1599264498
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.175299456
Short name T68
Test name
Test status
Simulation time 496941944 ps
CPU time 9.3 seconds
Started Aug 15 05:53:10 PM PDT 24
Finished Aug 15 05:53:19 PM PDT 24
Peak memory 212100 kb
Host smart-4669d32c-d440-4dc5-9a73-bfc57002456b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175299456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.175299456
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2394221635
Short name T392
Test name
Test status
Simulation time 172500987 ps
CPU time 12.54 seconds
Started Aug 15 05:53:12 PM PDT 24
Finished Aug 15 05:53:25 PM PDT 24
Peak memory 218280 kb
Host smart-3ae1e05a-99f0-4778-af89-c469408c5056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394221635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2394221635
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2441830659
Short name T440
Test name
Test status
Simulation time 463559421 ps
CPU time 80.75 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:54:06 PM PDT 24
Peak memory 214520 kb
Host smart-b64328ec-39b2-41ff-abb2-de692330018a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441830659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2441830659
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3694662426
Short name T406
Test name
Test status
Simulation time 187431176 ps
CPU time 8.82 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 217768 kb
Host smart-ee786eb3-fe56-4743-b9b9-3bddfbbd6854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694662426 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3694662426
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1778686969
Short name T428
Test name
Test status
Simulation time 353739674 ps
CPU time 7.65 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 212056 kb
Host smart-49223e03-aa7b-4c47-9820-5eca1557352a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778686969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1778686969
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2375179557
Short name T79
Test name
Test status
Simulation time 3110504961 ps
CPU time 36.6 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:53:24 PM PDT 24
Peak memory 215600 kb
Host smart-32ecfff1-8943-4ff0-8d4d-efe4a3705809
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375179557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2375179557
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1793073416
Short name T402
Test name
Test status
Simulation time 991500535 ps
CPU time 9.33 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 212268 kb
Host smart-19ba5bc2-fb91-4877-b75f-e76faf768296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793073416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1793073416
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.794258933
Short name T447
Test name
Test status
Simulation time 1452106531 ps
CPU time 13.89 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 218300 kb
Host smart-c447f66a-645a-4279-a7a1-d4a2542b9b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794258933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.794258933
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3406208853
Short name T445
Test name
Test status
Simulation time 526674505 ps
CPU time 10.14 seconds
Started Aug 15 05:53:01 PM PDT 24
Finished Aug 15 05:53:11 PM PDT 24
Peak memory 219596 kb
Host smart-e585b143-74c4-45d4-8450-a67aa58f4973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406208853 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3406208853
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3299768664
Short name T420
Test name
Test status
Simulation time 167637547 ps
CPU time 7.93 seconds
Started Aug 15 05:52:54 PM PDT 24
Finished Aug 15 05:53:02 PM PDT 24
Peak memory 211580 kb
Host smart-4453d24a-9ec9-47c8-b4e0-13f5a4f30e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299768664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3299768664
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2734133872
Short name T62
Test name
Test status
Simulation time 2119170518 ps
CPU time 41.88 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:53:27 PM PDT 24
Peak memory 212828 kb
Host smart-561bcafe-b66f-4136-8e44-c6bf0f8bb473
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734133872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2734133872
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3427683292
Short name T394
Test name
Test status
Simulation time 591482653 ps
CPU time 9.62 seconds
Started Aug 15 05:52:52 PM PDT 24
Finished Aug 15 05:53:02 PM PDT 24
Peak memory 211936 kb
Host smart-13926da7-eb7c-4eb9-adbd-2eeacdb90728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427683292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3427683292
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.501283299
Short name T414
Test name
Test status
Simulation time 1128579248 ps
CPU time 12.75 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:58 PM PDT 24
Peak memory 217016 kb
Host smart-3514376c-ca6f-4b42-a41c-d1e24ca543fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501283299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.501283299
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2074482897
Short name T434
Test name
Test status
Simulation time 685287707 ps
CPU time 80.87 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:54:07 PM PDT 24
Peak memory 214256 kb
Host smart-f8928b0f-68e2-4273-b815-0e32265729e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074482897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2074482897
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3559611372
Short name T436
Test name
Test status
Simulation time 283087722 ps
CPU time 10.41 seconds
Started Aug 15 05:52:58 PM PDT 24
Finished Aug 15 05:53:08 PM PDT 24
Peak memory 219632 kb
Host smart-ad97b654-2540-4788-afbd-8f7174ae8517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559611372 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3559611372
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.172353608
Short name T374
Test name
Test status
Simulation time 262329128 ps
CPU time 9.16 seconds
Started Aug 15 05:52:50 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 211572 kb
Host smart-c9a358be-4add-41cb-8dde-8e64f08a6984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172353608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.172353608
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.90605923
Short name T393
Test name
Test status
Simulation time 9254378546 ps
CPU time 43.45 seconds
Started Aug 15 05:52:52 PM PDT 24
Finished Aug 15 05:53:36 PM PDT 24
Peak memory 214588 kb
Host smart-4c07507a-e27f-43c3-b7ab-9689f1f1a0b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90605923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.90605923
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1792107149
Short name T416
Test name
Test status
Simulation time 254964558 ps
CPU time 9.33 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:52:57 PM PDT 24
Peak memory 212048 kb
Host smart-f42bb997-b08a-44d5-8905-636859315784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792107149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1792107149
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.822959612
Short name T430
Test name
Test status
Simulation time 1456539444 ps
CPU time 13.15 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 216988 kb
Host smart-8d3af95a-1f2a-470d-9975-a0b18e1df097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822959612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.822959612
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3170458717
Short name T52
Test name
Test status
Simulation time 833586625 ps
CPU time 154.23 seconds
Started Aug 15 05:52:59 PM PDT 24
Finished Aug 15 05:55:33 PM PDT 24
Peak memory 214912 kb
Host smart-7bfe188f-c588-4c6f-81e6-732cd88bc82f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170458717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3170458717
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.509401335
Short name T361
Test name
Test status
Simulation time 1220734833 ps
CPU time 8.53 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 219664 kb
Host smart-ee2bd521-62b8-4ce1-9696-20aae743e9e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509401335 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.509401335
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2502226094
Short name T71
Test name
Test status
Simulation time 4928954573 ps
CPU time 9.24 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 212048 kb
Host smart-2bb1d7e2-9357-40e6-87c2-ca8cc8268b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502226094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2502226094
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2173073090
Short name T457
Test name
Test status
Simulation time 2384231330 ps
CPU time 35.86 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:53:21 PM PDT 24
Peak memory 213588 kb
Host smart-64fee41c-e345-4d40-84c0-a2c7fdbde011
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173073090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2173073090
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2319736821
Short name T370
Test name
Test status
Simulation time 174312696 ps
CPU time 8.01 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 212116 kb
Host smart-2344d58c-77c4-4a38-a0cc-9fee3e8d300a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319736821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2319736821
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1125521701
Short name T442
Test name
Test status
Simulation time 689539615 ps
CPU time 12.66 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 219660 kb
Host smart-57f8bc50-70f9-490c-b008-6495944f6bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125521701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1125521701
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1514256527
Short name T105
Test name
Test status
Simulation time 918058113 ps
CPU time 80.61 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:54:08 PM PDT 24
Peak memory 213260 kb
Host smart-f827245e-c6b1-46b9-a066-143f8384e356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514256527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1514256527
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2535875676
Short name T364
Test name
Test status
Simulation time 4255470573 ps
CPU time 9.97 seconds
Started Aug 15 05:53:00 PM PDT 24
Finished Aug 15 05:53:10 PM PDT 24
Peak memory 219744 kb
Host smart-37ad4bf4-809c-43fe-b28b-c4ededd501f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535875676 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2535875676
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3436491375
Short name T93
Test name
Test status
Simulation time 1899840445 ps
CPU time 9.34 seconds
Started Aug 15 05:53:15 PM PDT 24
Finished Aug 15 05:53:25 PM PDT 24
Peak memory 211508 kb
Host smart-977b8c9e-c9e5-4691-9d46-1b088a62f88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436491375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3436491375
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2650632316
Short name T83
Test name
Test status
Simulation time 6334023541 ps
CPU time 62.1 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:53:50 PM PDT 24
Peak memory 216204 kb
Host smart-7bde4eae-56e9-462d-b11d-c4ab127d34a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650632316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2650632316
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3832604411
Short name T399
Test name
Test status
Simulation time 1032484550 ps
CPU time 9.73 seconds
Started Aug 15 05:53:01 PM PDT 24
Finished Aug 15 05:53:11 PM PDT 24
Peak memory 212196 kb
Host smart-59476ba4-440d-4b4a-8d9a-b8d77a64768e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832604411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3832604411
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1254184525
Short name T388
Test name
Test status
Simulation time 640163963 ps
CPU time 11.4 seconds
Started Aug 15 05:52:56 PM PDT 24
Finished Aug 15 05:53:08 PM PDT 24
Peak memory 218140 kb
Host smart-f3eb8792-2e0c-4de9-bc63-e4e076cfeb1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254184525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1254184525
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1320159608
Short name T104
Test name
Test status
Simulation time 642031686 ps
CPU time 89.54 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:54:13 PM PDT 24
Peak memory 219568 kb
Host smart-d322fdcc-3d6b-4322-bbf1-0500a537b045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320159608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1320159608
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.868114873
Short name T372
Test name
Test status
Simulation time 1081014031 ps
CPU time 10.92 seconds
Started Aug 15 05:53:02 PM PDT 24
Finished Aug 15 05:53:13 PM PDT 24
Peak memory 218120 kb
Host smart-f58b4220-8564-4af1-8ccc-51bc0e0ac25e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868114873 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.868114873
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2350287998
Short name T458
Test name
Test status
Simulation time 171361273 ps
CPU time 7.85 seconds
Started Aug 15 05:52:53 PM PDT 24
Finished Aug 15 05:53:02 PM PDT 24
Peak memory 211488 kb
Host smart-4f3e8e4b-b136-4096-a19a-97614b1a379f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350287998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2350287998
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.713679894
Short name T66
Test name
Test status
Simulation time 984032795 ps
CPU time 13.13 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:59 PM PDT 24
Peak memory 212040 kb
Host smart-2b549b8a-b5c9-4db8-94a4-cec865ecf132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713679894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.713679894
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1093142606
Short name T450
Test name
Test status
Simulation time 171096224 ps
CPU time 12.43 seconds
Started Aug 15 05:53:12 PM PDT 24
Finished Aug 15 05:53:25 PM PDT 24
Peak memory 218316 kb
Host smart-ef3021e8-1761-4f77-a26b-d271b3facf67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093142606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1093142606
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3028860082
Short name T451
Test name
Test status
Simulation time 1710242162 ps
CPU time 80.62 seconds
Started Aug 15 05:53:01 PM PDT 24
Finished Aug 15 05:54:22 PM PDT 24
Peak memory 214412 kb
Host smart-75ccae7d-6c1b-47df-b362-8a24e9d015b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028860082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3028860082
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4059302072
Short name T381
Test name
Test status
Simulation time 3976590613 ps
CPU time 13.12 seconds
Started Aug 15 05:52:50 PM PDT 24
Finished Aug 15 05:53:04 PM PDT 24
Peak memory 219708 kb
Host smart-b7c78072-0fa2-44a6-b8fb-057b244d48b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059302072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4059302072
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1318017953
Short name T422
Test name
Test status
Simulation time 174534386 ps
CPU time 8.2 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 211448 kb
Host smart-8899eb95-8086-4850-982d-1444cfb103dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318017953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1318017953
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2012530977
Short name T63
Test name
Test status
Simulation time 180309770 ps
CPU time 15.32 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 212488 kb
Host smart-d03aeeca-069e-4de3-9567-704e3a0b65f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012530977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2012530977
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.851457021
Short name T371
Test name
Test status
Simulation time 1079640200 ps
CPU time 10.18 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:43 PM PDT 24
Peak memory 219648 kb
Host smart-61ccf911-7a3d-490f-aeed-ecd8645135fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851457021 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.851457021
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3196930889
Short name T423
Test name
Test status
Simulation time 262707143 ps
CPU time 9.38 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 211376 kb
Host smart-faeedf86-9436-4610-9f46-15e0c74ab7d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196930889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3196930889
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1810534720
Short name T441
Test name
Test status
Simulation time 994822288 ps
CPU time 9.43 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:42 PM PDT 24
Peak memory 211356 kb
Host smart-19b91273-fb25-43b1-b5d9-9205f333ad6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810534720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1810534720
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4033380749
Short name T359
Test name
Test status
Simulation time 325495950 ps
CPU time 7.62 seconds
Started Aug 15 05:52:41 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 211320 kb
Host smart-2a910798-0385-4257-99f5-c51f4d5168f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033380749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4033380749
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3425201397
Short name T366
Test name
Test status
Simulation time 711648899 ps
CPU time 36.15 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:53:24 PM PDT 24
Peak memory 213456 kb
Host smart-1ad12a56-9fce-4bd5-9932-deccf6d2070a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425201397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3425201397
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1479561090
Short name T92
Test name
Test status
Simulation time 176483353 ps
CPU time 7.86 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:50 PM PDT 24
Peak memory 212216 kb
Host smart-bf4fe281-dd87-48f7-be4e-6a58cfe570a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479561090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1479561090
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2225266095
Short name T424
Test name
Test status
Simulation time 518090567 ps
CPU time 14.9 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:57 PM PDT 24
Peak memory 218248 kb
Host smart-21d8a42c-2324-4360-8078-82599c6a19a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225266095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2225266095
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.684569103
Short name T110
Test name
Test status
Simulation time 1148384787 ps
CPU time 81.16 seconds
Started Aug 15 05:52:32 PM PDT 24
Finished Aug 15 05:53:54 PM PDT 24
Peak memory 213176 kb
Host smart-4d8a0e1b-8c67-476f-94be-0d60364cdce3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684569103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.684569103
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.405194165
Short name T363
Test name
Test status
Simulation time 506555592 ps
CPU time 9.42 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 211416 kb
Host smart-98811703-a7ed-4f29-b683-86f23f307041
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405194165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.405194165
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3930110089
Short name T378
Test name
Test status
Simulation time 340709754 ps
CPU time 8.06 seconds
Started Aug 15 05:52:40 PM PDT 24
Finished Aug 15 05:52:49 PM PDT 24
Peak memory 211412 kb
Host smart-94f2cba2-6d11-4d60-8851-03c14ccf3f59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930110089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3930110089
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1965654980
Short name T415
Test name
Test status
Simulation time 408605786 ps
CPU time 12.8 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 211400 kb
Host smart-ae3176b1-2ba7-472d-9f0a-38f60454c559
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965654980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1965654980
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4138224986
Short name T455
Test name
Test status
Simulation time 175679791 ps
CPU time 8.17 seconds
Started Aug 15 05:52:51 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 219600 kb
Host smart-2db82abf-0d99-4f3e-9433-ade80043070e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138224986 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4138224986
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2984468171
Short name T64
Test name
Test status
Simulation time 497463454 ps
CPU time 9.46 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:52 PM PDT 24
Peak memory 211640 kb
Host smart-904766fe-09ad-425b-8f58-8b2cb8ec2909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984468171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2984468171
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2455044030
Short name T432
Test name
Test status
Simulation time 954429279 ps
CPU time 9.33 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:52 PM PDT 24
Peak memory 211364 kb
Host smart-57b3e326-aa4d-41a1-be98-0b1b5f767f63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455044030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2455044030
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.728082804
Short name T427
Test name
Test status
Simulation time 719012442 ps
CPU time 7.66 seconds
Started Aug 15 05:52:53 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 211344 kb
Host smart-5174eb0a-d129-445f-b820-ac5067cab08b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728082804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
728082804
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3920715195
Short name T444
Test name
Test status
Simulation time 5146234093 ps
CPU time 52.48 seconds
Started Aug 15 05:52:55 PM PDT 24
Finished Aug 15 05:53:47 PM PDT 24
Peak memory 216620 kb
Host smart-93850df8-5ee3-4450-83ee-54aabc36156a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920715195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3920715195
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2866288635
Short name T453
Test name
Test status
Simulation time 268348722 ps
CPU time 13.51 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 213200 kb
Host smart-69590acc-e007-43d9-893e-8e76459f39fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866288635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2866288635
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1566012057
Short name T429
Test name
Test status
Simulation time 1027746202 ps
CPU time 14.03 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:53:01 PM PDT 24
Peak memory 219532 kb
Host smart-a64b584c-e05a-406b-82ba-51911269e6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566012057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1566012057
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1633744049
Short name T103
Test name
Test status
Simulation time 1237082227 ps
CPU time 151.98 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:55:15 PM PDT 24
Peak memory 214280 kb
Host smart-56b2dd9f-25b3-4a75-ad8c-27c1a9db10bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633744049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1633744049
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.928286385
Short name T365
Test name
Test status
Simulation time 174625258 ps
CPU time 7.97 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:48 PM PDT 24
Peak memory 211452 kb
Host smart-6516845d-d0d4-44de-9d9d-9e0f6fdfed4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928286385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.928286385
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3752528643
Short name T454
Test name
Test status
Simulation time 260533266 ps
CPU time 9.51 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 211376 kb
Host smart-b98296d7-e280-443c-bdd9-7928f4267d89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752528643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3752528643
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.354587615
Short name T367
Test name
Test status
Simulation time 3139106896 ps
CPU time 16.7 seconds
Started Aug 15 05:52:49 PM PDT 24
Finished Aug 15 05:53:16 PM PDT 24
Peak memory 212680 kb
Host smart-a0983934-596d-4cd0-bd1a-2711531f8a1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354587615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.354587615
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2677101987
Short name T391
Test name
Test status
Simulation time 508813588 ps
CPU time 9.78 seconds
Started Aug 15 05:52:54 PM PDT 24
Finished Aug 15 05:53:04 PM PDT 24
Peak memory 219664 kb
Host smart-8d068b0e-f93f-422e-bb54-241a9aaf29a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677101987 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2677101987
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3237914998
Short name T387
Test name
Test status
Simulation time 173668157 ps
CPU time 7.96 seconds
Started Aug 15 05:52:33 PM PDT 24
Finished Aug 15 05:52:41 PM PDT 24
Peak memory 211816 kb
Host smart-5bc57dda-e2ab-41bb-85b0-472d16e58425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237914998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3237914998
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3953206446
Short name T384
Test name
Test status
Simulation time 1030465970 ps
CPU time 9.45 seconds
Started Aug 15 05:52:59 PM PDT 24
Finished Aug 15 05:53:09 PM PDT 24
Peak memory 211284 kb
Host smart-2c54bf9f-69ba-4328-9d5f-281ffec38137
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953206446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3953206446
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2281004899
Short name T382
Test name
Test status
Simulation time 1375431345 ps
CPU time 9.09 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 211304 kb
Host smart-db6cc03d-8800-4077-a79f-468a04c1f173
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281004899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2281004899
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.161721219
Short name T86
Test name
Test status
Simulation time 710173015 ps
CPU time 35.68 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:53:21 PM PDT 24
Peak memory 214484 kb
Host smart-a01ca667-c0b1-4975-982e-543f9c0b88aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161721219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.161721219
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3677777507
Short name T368
Test name
Test status
Simulation time 1034071175 ps
CPU time 9.6 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 212220 kb
Host smart-eb5f9e86-5958-4458-9f11-7aedd53a1634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677777507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3677777507
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.341596636
Short name T390
Test name
Test status
Simulation time 175423917 ps
CPU time 11.06 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:56 PM PDT 24
Peak memory 218164 kb
Host smart-09865540-f540-4e48-be1f-964da1fe6444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341596636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.341596636
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.504196866
Short name T379
Test name
Test status
Simulation time 815322218 ps
CPU time 81.29 seconds
Started Aug 15 05:52:52 PM PDT 24
Finished Aug 15 05:54:13 PM PDT 24
Peak memory 214200 kb
Host smart-9ab94dfc-e019-4971-9f8d-329abf6aa771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504196866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.504196866
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2464035873
Short name T56
Test name
Test status
Simulation time 270850403 ps
CPU time 10.37 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 219584 kb
Host smart-13605067-873e-4c0c-b668-94bc342bb949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464035873 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2464035873
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1566521745
Short name T95
Test name
Test status
Simulation time 397201873 ps
CPU time 7.82 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 211432 kb
Host smart-01ceeca5-ec3f-41b2-b5f5-e1feb83d5990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566521745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1566521745
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1247251652
Short name T385
Test name
Test status
Simulation time 4223306950 ps
CPU time 41.69 seconds
Started Aug 15 05:52:49 PM PDT 24
Finished Aug 15 05:53:31 PM PDT 24
Peak memory 214616 kb
Host smart-e3850e24-a335-4383-8a11-755b87c563b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247251652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1247251652
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2030328238
Short name T89
Test name
Test status
Simulation time 1375734525 ps
CPU time 9.44 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 212216 kb
Host smart-b53029c5-7d29-49b4-b717-e2be3278bd04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030328238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2030328238
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1991794012
Short name T411
Test name
Test status
Simulation time 993263877 ps
CPU time 13.41 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:59 PM PDT 24
Peak memory 218004 kb
Host smart-82b5bcb2-09c1-45af-80cc-0016e206c042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991794012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1991794012
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1512564163
Short name T112
Test name
Test status
Simulation time 3064552183 ps
CPU time 154.98 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:55:18 PM PDT 24
Peak memory 214732 kb
Host smart-1bc65847-72e7-4edf-9cdd-76ce86e67521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512564163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1512564163
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1525378061
Short name T360
Test name
Test status
Simulation time 275662179 ps
CPU time 10.18 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 217900 kb
Host smart-7ad5e953-7dba-4af7-b7aa-4babcd6352dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525378061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1525378061
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3445607720
Short name T425
Test name
Test status
Simulation time 259866472 ps
CPU time 9.06 seconds
Started Aug 15 05:52:45 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 211344 kb
Host smart-9b45593a-6da6-4024-a86b-554873052a8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445607720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3445607720
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3314001971
Short name T85
Test name
Test status
Simulation time 6072407147 ps
CPU time 86.64 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:54:15 PM PDT 24
Peak memory 216220 kb
Host smart-122b2c75-f98a-4694-b380-b93dd62f6b6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314001971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3314001971
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4271027862
Short name T449
Test name
Test status
Simulation time 991666028 ps
CPU time 9.66 seconds
Started Aug 15 05:52:58 PM PDT 24
Finished Aug 15 05:53:08 PM PDT 24
Peak memory 211888 kb
Host smart-e1048391-ee4f-4d99-82f0-749e3ae1c4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271027862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4271027862
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.370295301
Short name T426
Test name
Test status
Simulation time 691907022 ps
CPU time 12.39 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 218320 kb
Host smart-01b55d81-9ae2-4311-8c92-52a041864c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370295301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.370295301
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2619225003
Short name T53
Test name
Test status
Simulation time 226853671 ps
CPU time 79.5 seconds
Started Aug 15 05:52:48 PM PDT 24
Finished Aug 15 05:54:07 PM PDT 24
Peak memory 214548 kb
Host smart-547ca63e-e4cf-48fa-9abe-945236c7911c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619225003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2619225003
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2938017644
Short name T395
Test name
Test status
Simulation time 2227430541 ps
CPU time 9.42 seconds
Started Aug 15 05:52:50 PM PDT 24
Finished Aug 15 05:53:00 PM PDT 24
Peak memory 219772 kb
Host smart-db4ff024-1af7-46fd-a840-3abae5e19339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938017644 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2938017644
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1563912571
Short name T389
Test name
Test status
Simulation time 176502138 ps
CPU time 7.94 seconds
Started Aug 15 05:53:02 PM PDT 24
Finished Aug 15 05:53:10 PM PDT 24
Peak memory 211436 kb
Host smart-db0ca9a8-1e62-4ab7-be78-cf97815b9f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563912571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1563912571
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1768594087
Short name T67
Test name
Test status
Simulation time 2766985456 ps
CPU time 36.26 seconds
Started Aug 15 05:52:51 PM PDT 24
Finished Aug 15 05:53:27 PM PDT 24
Peak memory 213584 kb
Host smart-fabed3d7-fbd7-41af-a96b-bc2b71285142
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768594087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1768594087
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1522284172
Short name T386
Test name
Test status
Simulation time 174402962 ps
CPU time 7.88 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 211844 kb
Host smart-02ddf91b-9cad-40e5-aecf-ea078046d81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522284172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1522284172
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1332492680
Short name T446
Test name
Test status
Simulation time 251698761 ps
CPU time 12.98 seconds
Started Aug 15 05:52:39 PM PDT 24
Finished Aug 15 05:52:52 PM PDT 24
Peak memory 217196 kb
Host smart-cf45bda6-fe61-465d-a68b-5b865edcc8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332492680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1332492680
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.542256914
Short name T109
Test name
Test status
Simulation time 505624744 ps
CPU time 157.01 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:55:22 PM PDT 24
Peak memory 213828 kb
Host smart-763cab8d-8f89-4679-97fd-0129bc523500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542256914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.542256914
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2047982340
Short name T443
Test name
Test status
Simulation time 177940491 ps
CPU time 8.26 seconds
Started Aug 15 05:52:47 PM PDT 24
Finished Aug 15 05:52:55 PM PDT 24
Peak memory 219668 kb
Host smart-5f82b71d-e816-485f-8320-e23a353a1be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047982340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2047982340
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2174686728
Short name T419
Test name
Test status
Simulation time 688335280 ps
CPU time 7.99 seconds
Started Aug 15 05:52:43 PM PDT 24
Finished Aug 15 05:52:51 PM PDT 24
Peak memory 211324 kb
Host smart-9a37120e-c510-48ed-8173-95bb81dfaae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174686728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2174686728
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3625212891
Short name T87
Test name
Test status
Simulation time 1016506398 ps
CPU time 40.73 seconds
Started Aug 15 05:52:46 PM PDT 24
Finished Aug 15 05:53:27 PM PDT 24
Peak memory 214500 kb
Host smart-b7030561-edb8-4a43-bba3-24084994bc80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625212891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3625212891
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2529549487
Short name T456
Test name
Test status
Simulation time 259658474 ps
CPU time 9.44 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:52:54 PM PDT 24
Peak memory 212220 kb
Host smart-4bf72cad-de34-478d-af36-b47091843385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529549487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2529549487
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.787655349
Short name T373
Test name
Test status
Simulation time 174519439 ps
CPU time 13.11 seconds
Started Aug 15 05:52:54 PM PDT 24
Finished Aug 15 05:53:07 PM PDT 24
Peak memory 218364 kb
Host smart-d41782f6-71ef-4b15-a589-d3b9753ebcd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787655349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.787655349
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2284104100
Short name T108
Test name
Test status
Simulation time 1385670549 ps
CPU time 80.91 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:54:05 PM PDT 24
Peak memory 214416 kb
Host smart-d9d2366b-00b3-491b-b378-ed132788497c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284104100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2284104100
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4015154721
Short name T369
Test name
Test status
Simulation time 272694153 ps
CPU time 9.66 seconds
Started Aug 15 05:53:02 PM PDT 24
Finished Aug 15 05:53:12 PM PDT 24
Peak memory 214804 kb
Host smart-204ddffb-7852-4e2f-95b7-337d73586b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015154721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4015154721
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2611955929
Short name T405
Test name
Test status
Simulation time 250160354 ps
CPU time 9.28 seconds
Started Aug 15 05:52:35 PM PDT 24
Finished Aug 15 05:52:44 PM PDT 24
Peak memory 211556 kb
Host smart-0e1ee749-73d0-4365-8eeb-5c5e576becd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611955929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2611955929
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.370163446
Short name T421
Test name
Test status
Simulation time 708175633 ps
CPU time 36.26 seconds
Started Aug 15 05:52:44 PM PDT 24
Finished Aug 15 05:53:21 PM PDT 24
Peak memory 213464 kb
Host smart-fd6c4f8f-b861-4ff0-91c9-2a382263a202
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370163446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.370163446
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3126540609
Short name T91
Test name
Test status
Simulation time 3526335717 ps
CPU time 9.65 seconds
Started Aug 15 05:52:53 PM PDT 24
Finished Aug 15 05:53:03 PM PDT 24
Peak memory 211988 kb
Host smart-43abcfdb-01a2-4b46-a62d-68d01333667a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126540609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3126540609
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3862435132
Short name T401
Test name
Test status
Simulation time 171413133 ps
CPU time 11.19 seconds
Started Aug 15 05:52:42 PM PDT 24
Finished Aug 15 05:52:53 PM PDT 24
Peak memory 216988 kb
Host smart-83948fea-de2d-400f-8d07-fb86b0e4f78e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862435132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3862435132
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1743380018
Short name T102
Test name
Test status
Simulation time 1338968569 ps
CPU time 155.29 seconds
Started Aug 15 05:52:52 PM PDT 24
Finished Aug 15 05:55:27 PM PDT 24
Peak memory 219588 kb
Host smart-bbed5f17-5ace-4c30-bebe-d2bfcfed1a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743380018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1743380018
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2584041666
Short name T344
Test name
Test status
Simulation time 1455028387 ps
CPU time 9.58 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:11:54 PM PDT 24
Peak memory 218436 kb
Host smart-93e74c9b-729f-4051-9032-796790c4b8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584041666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2584041666
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3737082702
Short name T178
Test name
Test status
Simulation time 11163782840 ps
CPU time 181.14 seconds
Started Aug 15 06:11:41 PM PDT 24
Finished Aug 15 06:14:42 PM PDT 24
Peak memory 218896 kb
Host smart-795a30d0-e14d-4b4a-aefa-01b9302f8ad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737082702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3737082702
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.806950050
Short name T189
Test name
Test status
Simulation time 504464739 ps
CPU time 20.95 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:15 PM PDT 24
Peak memory 218644 kb
Host smart-1006ecf4-2090-4904-8cad-f61d3843cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806950050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.806950050
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3624623368
Short name T252
Test name
Test status
Simulation time 950869023 ps
CPU time 9.81 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:11:57 PM PDT 24
Peak memory 218900 kb
Host smart-3b4da22c-bcb3-4397-9484-7d16a0351882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624623368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3624623368
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4162552314
Short name T32
Test name
Test status
Simulation time 1531326395 ps
CPU time 230.27 seconds
Started Aug 15 06:11:34 PM PDT 24
Finished Aug 15 06:15:24 PM PDT 24
Peak memory 238536 kb
Host smart-278a304d-5764-4fe1-b886-fb0757e92014
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162552314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4162552314
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2828239928
Short name T270
Test name
Test status
Simulation time 1085784126 ps
CPU time 11.88 seconds
Started Aug 15 06:11:41 PM PDT 24
Finished Aug 15 06:11:53 PM PDT 24
Peak memory 219168 kb
Host smart-758c4bcf-397b-4aa2-b289-febc715d3f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828239928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2828239928
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3435540187
Short name T250
Test name
Test status
Simulation time 957463767 ps
CPU time 15.59 seconds
Started Aug 15 06:11:29 PM PDT 24
Finished Aug 15 06:11:45 PM PDT 24
Peak memory 219168 kb
Host smart-60107b92-4fc4-4415-a8b9-5dfc41a336f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435540187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3435540187
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2808599989
Short name T337
Test name
Test status
Simulation time 49451974158 ps
CPU time 167.65 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:14:29 PM PDT 24
Peak memory 230380 kb
Host smart-3ca9e709-d0f5-431b-b491-558e12c771c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808599989 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2808599989
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3239093526
Short name T211
Test name
Test status
Simulation time 750703282 ps
CPU time 8.29 seconds
Started Aug 15 06:11:30 PM PDT 24
Finished Aug 15 06:11:38 PM PDT 24
Peak memory 218468 kb
Host smart-c79220b4-fd8a-4a7c-a5ec-ad47df071df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239093526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3239093526
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1698994156
Short name T44
Test name
Test status
Simulation time 6435530984 ps
CPU time 291.69 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:16:34 PM PDT 24
Peak memory 241400 kb
Host smart-f991f7a6-f009-4f4f-a10d-431a02506da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698994156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1698994156
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.736209823
Short name T281
Test name
Test status
Simulation time 518495376 ps
CPU time 21.7 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:03 PM PDT 24
Peak memory 218596 kb
Host smart-fd1ca0d7-b9b2-453f-91a2-011f92c5a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736209823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.736209823
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4194161562
Short name T226
Test name
Test status
Simulation time 4263714980 ps
CPU time 11.29 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:11:48 PM PDT 24
Peak memory 218884 kb
Host smart-6ce3b811-8535-4d6b-8eaa-fb31ac0e6ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194161562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4194161562
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3975410520
Short name T31
Test name
Test status
Simulation time 1091105307 ps
CPU time 222.16 seconds
Started Aug 15 06:11:38 PM PDT 24
Finished Aug 15 06:15:21 PM PDT 24
Peak memory 238324 kb
Host smart-963c6d59-225b-4366-a4d1-74df4d96cb69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975410520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3975410520
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3252061985
Short name T8
Test name
Test status
Simulation time 701869576 ps
CPU time 10.06 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:11:47 PM PDT 24
Peak memory 219172 kb
Host smart-87090b42-c2a3-4c53-86b6-3f8b27db9cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252061985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3252061985
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1945132724
Short name T224
Test name
Test status
Simulation time 397452100 ps
CPU time 23.43 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:12:11 PM PDT 24
Peak memory 219156 kb
Host smart-76aeb675-469c-42ca-8709-8a4624ef135c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945132724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1945132724
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4227283710
Short name T50
Test name
Test status
Simulation time 2645640703 ps
CPU time 51.63 seconds
Started Aug 15 06:11:39 PM PDT 24
Finished Aug 15 06:12:31 PM PDT 24
Peak memory 224264 kb
Host smart-d9dbc6c8-7e2a-4cc3-b8f2-d885e163bd13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227283710 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4227283710
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.598503156
Short name T319
Test name
Test status
Simulation time 1081663351 ps
CPU time 9.59 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:11:58 PM PDT 24
Peak memory 218348 kb
Host smart-abb58823-9759-4e45-b148-df40c2ce4df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598503156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.598503156
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2290840675
Short name T170
Test name
Test status
Simulation time 15984342874 ps
CPU time 410.73 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:18:34 PM PDT 24
Peak memory 217504 kb
Host smart-f510a0fe-8281-47db-9742-0f40a36154d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290840675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2290840675
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.251803230
Short name T164
Test name
Test status
Simulation time 2149073402 ps
CPU time 21.31 seconds
Started Aug 15 06:11:56 PM PDT 24
Finished Aug 15 06:12:18 PM PDT 24
Peak memory 218716 kb
Host smart-d977875a-1f9e-4222-a8c4-b7b437a8f728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251803230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.251803230
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2625336736
Short name T145
Test name
Test status
Simulation time 350263259 ps
CPU time 9.91 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:11:58 PM PDT 24
Peak memory 218940 kb
Host smart-15f22648-8a9a-4fc1-923b-7f40405787d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625336736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2625336736
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1379942122
Short name T335
Test name
Test status
Simulation time 2967703792 ps
CPU time 20.81 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:12:06 PM PDT 24
Peak memory 219236 kb
Host smart-5fd20b14-7742-485f-a3ed-dbb7e3f78556
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379942122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1379942122
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1130850655
Short name T297
Test name
Test status
Simulation time 514286192 ps
CPU time 9.49 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:11:56 PM PDT 24
Peak memory 218460 kb
Host smart-323461c9-0da5-47db-9759-bf39749a1915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130850655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1130850655
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1212595494
Short name T181
Test name
Test status
Simulation time 38279293903 ps
CPU time 146.36 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:14:04 PM PDT 24
Peak memory 243428 kb
Host smart-53c0eae7-0b04-41d0-89d9-6c3473c88691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212595494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1212595494
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3504662526
Short name T352
Test name
Test status
Simulation time 3940372457 ps
CPU time 29.09 seconds
Started Aug 15 06:12:52 PM PDT 24
Finished Aug 15 06:13:22 PM PDT 24
Peak memory 219160 kb
Host smart-9b0a57dc-ecf6-4384-abd5-5e19cda3aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504662526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3504662526
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1253990764
Short name T334
Test name
Test status
Simulation time 265969618 ps
CPU time 11.67 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:11:57 PM PDT 24
Peak memory 218544 kb
Host smart-18572fe2-b5f4-4ef9-a5ff-cdfd931f57f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253990764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1253990764
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2919257263
Short name T37
Test name
Test status
Simulation time 527299270 ps
CPU time 31.85 seconds
Started Aug 15 06:11:52 PM PDT 24
Finished Aug 15 06:12:24 PM PDT 24
Peak memory 219204 kb
Host smart-033c6c9c-85ee-4f90-a022-58dfca671a03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919257263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2919257263
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.789416037
Short name T312
Test name
Test status
Simulation time 10871930497 ps
CPU time 108.45 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:13:32 PM PDT 24
Peak memory 226512 kb
Host smart-5f325485-1e1a-4a38-a40e-c717de613848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789416037 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.789416037
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3864652767
Short name T25
Test name
Test status
Simulation time 19766755085 ps
CPU time 216.29 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:15:21 PM PDT 24
Peak memory 218664 kb
Host smart-c46a09e3-18ae-4f85-bb82-89f5a97bfc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864652767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3864652767
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1919561330
Short name T130
Test name
Test status
Simulation time 1226656635 ps
CPU time 18.6 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218592 kb
Host smart-35a2dd34-bb07-4a74-8d24-75838059e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919561330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1919561330
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3782550067
Short name T194
Test name
Test status
Simulation time 703796625 ps
CPU time 10.02 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218888 kb
Host smart-07035540-c25e-40c5-849c-8f1b5094098d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782550067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3782550067
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.571027719
Short name T329
Test name
Test status
Simulation time 5884191531 ps
CPU time 37.36 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:24 PM PDT 24
Peak memory 222496 kb
Host smart-e2bdd918-075e-4766-9527-02b09e07bde9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571027719 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.571027719
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4083239019
Short name T292
Test name
Test status
Simulation time 4101003095 ps
CPU time 13.85 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218472 kb
Host smart-1dd549c2-b483-4aff-9941-d564448cb9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083239019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4083239019
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4057910734
Short name T245
Test name
Test status
Simulation time 17721062321 ps
CPU time 237.82 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:15:41 PM PDT 24
Peak memory 237812 kb
Host smart-3474299c-7752-4f19-a59f-6a0025f05803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057910734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4057910734
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.527603604
Short name T258
Test name
Test status
Simulation time 1021747863 ps
CPU time 11.51 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 218576 kb
Host smart-d6fdba5b-ab6f-4663-80aa-caaf7cf55561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527603604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.527603604
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2731074840
Short name T232
Test name
Test status
Simulation time 507399170 ps
CPU time 22.02 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:12:08 PM PDT 24
Peak memory 219080 kb
Host smart-8e34ed96-5bcb-4b3d-8b16-01598a9495a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731074840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2731074840
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3216965564
Short name T15
Test name
Test status
Simulation time 13039813428 ps
CPU time 139.65 seconds
Started Aug 15 06:12:01 PM PDT 24
Finished Aug 15 06:14:21 PM PDT 24
Peak memory 227212 kb
Host smart-74044241-6570-4558-aeab-e8959d12cc99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216965564 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3216965564
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2509117702
Short name T172
Test name
Test status
Simulation time 332639205 ps
CPU time 7.92 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218124 kb
Host smart-826eafed-28b9-4b13-a004-8ced742e73df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509117702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2509117702
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4199195760
Short name T345
Test name
Test status
Simulation time 16723111029 ps
CPU time 201.63 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:15:10 PM PDT 24
Peak memory 241772 kb
Host smart-22018586-fb3a-4e74-94c1-514414630638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199195760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4199195760
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1040846212
Short name T141
Test name
Test status
Simulation time 517854509 ps
CPU time 20.92 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:12:08 PM PDT 24
Peak memory 218312 kb
Host smart-523fe44e-7c17-4f9f-a245-8df68741da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040846212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1040846212
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4068071162
Short name T241
Test name
Test status
Simulation time 180113754 ps
CPU time 10.17 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218544 kb
Host smart-5db8dd84-91fa-420a-8035-c50718990a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068071162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4068071162
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1913450292
Short name T347
Test name
Test status
Simulation time 1425733289 ps
CPU time 22.99 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:12:08 PM PDT 24
Peak memory 219168 kb
Host smart-3c7fa7a6-c947-46f7-9924-3a024c93329a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913450292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1913450292
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2205551253
Short name T203
Test name
Test status
Simulation time 2305745584 ps
CPU time 87.92 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:13:26 PM PDT 24
Peak memory 223900 kb
Host smart-83c89eb0-33ba-423b-9512-e2f71ad8cfb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205551253 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2205551253
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1089541271
Short name T289
Test name
Test status
Simulation time 170790167 ps
CPU time 8.16 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218232 kb
Host smart-df6c322b-15d7-4a70-bf79-8ec310b5e652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089541271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1089541271
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2604627208
Short name T137
Test name
Test status
Simulation time 8250956779 ps
CPU time 242.71 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:15:47 PM PDT 24
Peak memory 241556 kb
Host smart-c3b40eca-da92-4bbe-b2be-d09e418bda45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604627208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2604627208
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3687365150
Short name T179
Test name
Test status
Simulation time 1384518316 ps
CPU time 18.48 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 218800 kb
Host smart-7e36fa69-f562-476e-ab59-992586fe4d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687365150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3687365150
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.176819532
Short name T154
Test name
Test status
Simulation time 276756602 ps
CPU time 12.25 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:12 PM PDT 24
Peak memory 218956 kb
Host smart-4640c83f-4fc2-4cbe-a3c5-2b03095325fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176819532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.176819532
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3243416826
Short name T225
Test name
Test status
Simulation time 29580500210 ps
CPU time 206.95 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:15:17 PM PDT 24
Peak memory 235644 kb
Host smart-6572119a-c6e3-49b9-bf15-819c817eb0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243416826 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3243416826
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1053166045
Short name T29
Test name
Test status
Simulation time 498177734 ps
CPU time 9.28 seconds
Started Aug 15 06:11:51 PM PDT 24
Finished Aug 15 06:12:00 PM PDT 24
Peak memory 218276 kb
Host smart-6a19e0c6-ac28-4c5f-b06b-12d89fb8bf2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053166045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1053166045
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2139856612
Short name T305
Test name
Test status
Simulation time 19949971817 ps
CPU time 255.22 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:16:10 PM PDT 24
Peak memory 237976 kb
Host smart-c6131e87-26f0-43e9-a40f-195c6fed2744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139856612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2139856612
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1350041598
Short name T223
Test name
Test status
Simulation time 284000926 ps
CPU time 9.91 seconds
Started Aug 15 06:11:59 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218980 kb
Host smart-7475933d-d972-44b6-82b2-4b79573284ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350041598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1350041598
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1731197065
Short name T251
Test name
Test status
Simulation time 446873795 ps
CPU time 13.6 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:11 PM PDT 24
Peak memory 219108 kb
Host smart-36447e2e-0ba9-454e-b9b5-559825c4895f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731197065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1731197065
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2107899241
Short name T342
Test name
Test status
Simulation time 34529034484 ps
CPU time 252.61 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:16:07 PM PDT 24
Peak memory 235712 kb
Host smart-a9f5303c-7ded-4db0-979c-1e26f3954cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107899241 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2107899241
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.261567593
Short name T243
Test name
Test status
Simulation time 201324039 ps
CPU time 7.88 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 218408 kb
Host smart-827f681e-a457-4c38-a3fb-a384a211a652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261567593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.261567593
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.291704800
Short name T2
Test name
Test status
Simulation time 4721613097 ps
CPU time 18.92 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:12:04 PM PDT 24
Peak memory 218996 kb
Host smart-d0f68e8d-8f0c-4d29-9005-a491b8c93d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291704800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.291704800
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1935316804
Short name T187
Test name
Test status
Simulation time 186269218 ps
CPU time 10.45 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218692 kb
Host smart-a29026a4-d169-4c7c-8bec-56e845ca3806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935316804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1935316804
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3491086291
Short name T153
Test name
Test status
Simulation time 2316582350 ps
CPU time 30.98 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 219228 kb
Host smart-36fc6c3b-34fe-4716-9398-a94f22bc3b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491086291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3491086291
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3631529926
Short name T210
Test name
Test status
Simulation time 3245252411 ps
CPU time 65.61 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:55 PM PDT 24
Peak memory 224984 kb
Host smart-ff7dd6ab-a7ce-455e-8d7f-b65726b9ec20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631529926 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3631529926
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.443967026
Short name T138
Test name
Test status
Simulation time 168300798 ps
CPU time 7.83 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:12:10 PM PDT 24
Peak memory 218384 kb
Host smart-6f33b29e-bbd7-4f0d-9982-3f5d10f457c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443967026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.443967026
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.913091751
Short name T339
Test name
Test status
Simulation time 7111563078 ps
CPU time 164.11 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:14:42 PM PDT 24
Peak memory 236884 kb
Host smart-2aa081f4-1155-493c-a8da-ba5809f59756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913091751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.913091751
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2737200324
Short name T234
Test name
Test status
Simulation time 1982774712 ps
CPU time 21.6 seconds
Started Aug 15 06:11:51 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 218940 kb
Host smart-c120f787-1d9d-4a2b-9935-53a6c25c4964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737200324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2737200324
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4144286658
Short name T264
Test name
Test status
Simulation time 617528446 ps
CPU time 10.25 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:11:53 PM PDT 24
Peak memory 218972 kb
Host smart-411b3007-80a2-4957-a046-509becd7285a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144286658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4144286658
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2404541359
Short name T13
Test name
Test status
Simulation time 212540943 ps
CPU time 18.06 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:12:04 PM PDT 24
Peak memory 219060 kb
Host smart-694c10ea-1433-4721-a61b-89ac22d32371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404541359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2404541359
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2789781096
Short name T49
Test name
Test status
Simulation time 7923733665 ps
CPU time 78.49 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:13:04 PM PDT 24
Peak memory 227628 kb
Host smart-4bd2d220-ea8f-4bd8-add0-10f7fdc086bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789781096 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2789781096
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3946313375
Short name T328
Test name
Test status
Simulation time 826787693 ps
CPU time 7.75 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:07 PM PDT 24
Peak memory 218380 kb
Host smart-a3dcb841-5ecc-406a-9e9b-7c700ef4b3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946313375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3946313375
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4012230582
Short name T303
Test name
Test status
Simulation time 22670004158 ps
CPU time 283.9 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:16:39 PM PDT 24
Peak memory 237688 kb
Host smart-2da7b499-4265-4a88-9b45-6facbec45c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012230582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4012230582
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.110159203
Short name T122
Test name
Test status
Simulation time 1386396670 ps
CPU time 18.09 seconds
Started Aug 15 06:11:59 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218932 kb
Host smart-378383a6-550f-48de-9cd0-d9278ff874da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110159203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.110159203
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.290497056
Short name T190
Test name
Test status
Simulation time 734052484 ps
CPU time 9.93 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:00 PM PDT 24
Peak memory 218724 kb
Host smart-2e8703db-59d7-48e1-a428-310700817706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290497056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.290497056
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1660072244
Short name T147
Test name
Test status
Simulation time 1759392667 ps
CPU time 22.54 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:12:07 PM PDT 24
Peak memory 219172 kb
Host smart-4f362a75-0b77-4417-855d-08594bf5c2bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660072244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1660072244
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2511046763
Short name T114
Test name
Test status
Simulation time 4457303473 ps
CPU time 40.7 seconds
Started Aug 15 06:12:01 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 221936 kb
Host smart-993ad889-c7ef-4d9a-aa85-0c7aad4dd1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511046763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2511046763
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1670859107
Short name T354
Test name
Test status
Simulation time 262141058 ps
CPU time 9.48 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:11:47 PM PDT 24
Peak memory 218412 kb
Host smart-7b6c40ca-4b06-4e27-aa88-f780d0dfd143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670859107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1670859107
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.166893891
Short name T1
Test name
Test status
Simulation time 17846291298 ps
CPU time 324.66 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:17:32 PM PDT 24
Peak memory 219008 kb
Host smart-a820f274-837e-40a8-b62c-df7fcefd9c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166893891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.166893891
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3764805823
Short name T152
Test name
Test status
Simulation time 1078547684 ps
CPU time 21.78 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:04 PM PDT 24
Peak memory 218844 kb
Host smart-65c9276b-a33a-49ba-8adb-1ada6a6c78be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764805823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3764805823
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1606051567
Short name T133
Test name
Test status
Simulation time 737749383 ps
CPU time 10.05 seconds
Started Aug 15 06:11:40 PM PDT 24
Finished Aug 15 06:11:50 PM PDT 24
Peak memory 218616 kb
Host smart-64510607-4287-4073-8adb-e8321fdaa146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606051567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1606051567
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1671110482
Short name T259
Test name
Test status
Simulation time 720064594 ps
CPU time 9.56 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:11:57 PM PDT 24
Peak memory 219156 kb
Host smart-5b69342d-b456-47cf-9c4d-517804e001fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671110482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1671110482
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2059672395
Short name T36
Test name
Test status
Simulation time 771801693 ps
CPU time 13.97 seconds
Started Aug 15 06:11:26 PM PDT 24
Finished Aug 15 06:11:40 PM PDT 24
Peak memory 219108 kb
Host smart-62fe6495-97ca-419e-8a5d-44cc48591f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059672395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2059672395
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1897751864
Short name T327
Test name
Test status
Simulation time 3235515124 ps
CPU time 122.03 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:13:48 PM PDT 24
Peak memory 232872 kb
Host smart-604c4326-d165-4bee-938c-e316b6b5af7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897751864 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1897751864
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2394259984
Short name T98
Test name
Test status
Simulation time 661514185 ps
CPU time 7.94 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 218340 kb
Host smart-14d95df0-3abf-4c8a-8dc9-ff200849851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394259984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2394259984
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1879322353
Short name T316
Test name
Test status
Simulation time 33483760231 ps
CPU time 395.5 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:18:48 PM PDT 24
Peak memory 239856 kb
Host smart-9e4ed73f-e2c7-4cc5-a303-92e3d18a02b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879322353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1879322353
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1888228225
Short name T300
Test name
Test status
Simulation time 4103286910 ps
CPU time 28.86 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:12:15 PM PDT 24
Peak memory 219200 kb
Host smart-2abf1e01-439c-4d65-b244-0e19a6879f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888228225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1888228225
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.776213959
Short name T247
Test name
Test status
Simulation time 1066413861 ps
CPU time 11.59 seconds
Started Aug 15 06:11:51 PM PDT 24
Finished Aug 15 06:12:03 PM PDT 24
Peak memory 218872 kb
Host smart-d5ff909f-c9dc-4df2-af78-66a03e2a8be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776213959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.776213959
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.642387636
Short name T333
Test name
Test status
Simulation time 744603164 ps
CPU time 30.49 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:30 PM PDT 24
Peak memory 219184 kb
Host smart-72bfbf31-ace5-43c4-8dca-902d30b0aeb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642387636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.642387636
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2085694070
Short name T7
Test name
Test status
Simulation time 15512982332 ps
CPU time 220.45 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:15:44 PM PDT 24
Peak memory 226424 kb
Host smart-b9174cb3-a210-40b5-9a61-ded0469c583e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085694070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2085694070
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1049350141
Short name T128
Test name
Test status
Simulation time 250305369 ps
CPU time 9.36 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:11:59 PM PDT 24
Peak memory 218464 kb
Host smart-72cbd1ec-9361-4e1a-a2a7-8fa9478f7529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049350141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1049350141
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1349203352
Short name T275
Test name
Test status
Simulation time 2359397050 ps
CPU time 172.48 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:14:38 PM PDT 24
Peak memory 239896 kb
Host smart-6bc2bed7-471c-433f-b173-3aecc235ef2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349203352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1349203352
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3698082413
Short name T46
Test name
Test status
Simulation time 9889494709 ps
CPU time 21.66 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:04 PM PDT 24
Peak memory 219236 kb
Host smart-0df8f23f-d21b-4790-bfc2-6a3a75abbff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698082413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3698082413
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.347177842
Short name T348
Test name
Test status
Simulation time 4000393770 ps
CPU time 14.75 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:12:10 PM PDT 24
Peak memory 219256 kb
Host smart-62f6578e-b97b-47da-adea-1491730274f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347177842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.347177842
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4226190372
Short name T201
Test name
Test status
Simulation time 556755442 ps
CPU time 32.99 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:26 PM PDT 24
Peak memory 219160 kb
Host smart-f3b892fc-7ace-4cc7-b0c7-f688891a1848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226190372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4226190372
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3207208015
Short name T163
Test name
Test status
Simulation time 256452074 ps
CPU time 9.49 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218464 kb
Host smart-95bd8db0-e92d-4f98-8e87-224cfe768b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207208015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3207208015
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2040529204
Short name T355
Test name
Test status
Simulation time 8692599838 ps
CPU time 168.86 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:14:37 PM PDT 24
Peak memory 239768 kb
Host smart-af7586d8-d89e-4422-9710-9e678c63e23c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040529204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2040529204
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2312124220
Short name T350
Test name
Test status
Simulation time 332496311 ps
CPU time 18.51 seconds
Started Aug 15 06:11:52 PM PDT 24
Finished Aug 15 06:12:11 PM PDT 24
Peak memory 218920 kb
Host smart-edd12d12-465a-461d-a939-34c2c739d218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312124220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2312124220
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3169473635
Short name T282
Test name
Test status
Simulation time 346699855 ps
CPU time 9.82 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 218672 kb
Host smart-d8bf5d2b-a52a-4387-8917-893be69c4567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169473635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3169473635
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.836150340
Short name T317
Test name
Test status
Simulation time 773729363 ps
CPU time 26.96 seconds
Started Aug 15 06:11:52 PM PDT 24
Finished Aug 15 06:12:19 PM PDT 24
Peak memory 219156 kb
Host smart-077d9214-2ef9-4c47-b153-f15040a8faae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836150340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.836150340
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2086772895
Short name T149
Test name
Test status
Simulation time 4078373935 ps
CPU time 67.64 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:57 PM PDT 24
Peak memory 225760 kb
Host smart-3a57b492-5c3f-4570-a113-ed2b97f19a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086772895 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2086772895
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3502163968
Short name T197
Test name
Test status
Simulation time 257874079 ps
CPU time 9.57 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:11:54 PM PDT 24
Peak memory 218452 kb
Host smart-0a4dd46a-366d-422d-9756-4deda359dc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502163968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3502163968
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.649282706
Short name T42
Test name
Test status
Simulation time 22575625657 ps
CPU time 183.85 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:15:07 PM PDT 24
Peak memory 237304 kb
Host smart-871b1b75-eb8a-49d2-9c80-89f6dc819cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649282706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.649282706
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3539396692
Short name T120
Test name
Test status
Simulation time 519416290 ps
CPU time 21.48 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:12 PM PDT 24
Peak memory 218572 kb
Host smart-24a193fd-fa19-4900-b3fe-fcdf92e40f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539396692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3539396692
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.517443368
Short name T185
Test name
Test status
Simulation time 179619426 ps
CPU time 10.06 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:00 PM PDT 24
Peak memory 218932 kb
Host smart-930f52b8-a5c7-4d5d-b023-9c047d30e08b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517443368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.517443368
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3233709720
Short name T61
Test name
Test status
Simulation time 1853265754 ps
CPU time 36.4 seconds
Started Aug 15 06:11:52 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 219136 kb
Host smart-fffbb9c5-471f-4395-bc50-20da9b34f132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233709720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3233709720
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3016920981
Short name T274
Test name
Test status
Simulation time 10049105770 ps
CPU time 87.3 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:13:17 PM PDT 24
Peak memory 225440 kb
Host smart-e9e9b943-a195-4a03-afde-75d2836681f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016920981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3016920981
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1415087341
Short name T140
Test name
Test status
Simulation time 174649045 ps
CPU time 7.97 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218356 kb
Host smart-92f2ba4b-805d-4f11-8f7e-1ed1187ec1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415087341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1415087341
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2166024329
Short name T208
Test name
Test status
Simulation time 6872409381 ps
CPU time 215.29 seconds
Started Aug 15 06:12:15 PM PDT 24
Finished Aug 15 06:15:51 PM PDT 24
Peak memory 243072 kb
Host smart-d7f7a173-2ba2-48bc-b9d2-6415010dd1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166024329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2166024329
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1695612694
Short name T101
Test name
Test status
Simulation time 342564681 ps
CPU time 11.51 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 218608 kb
Host smart-492ec3a8-593a-414b-bd5c-ba5561f54806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695612694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1695612694
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.697462544
Short name T60
Test name
Test status
Simulation time 359994741 ps
CPU time 19.5 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 219176 kb
Host smart-f25eec63-d635-4bad-b8f1-89dc9ff29254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697462544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.697462544
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1596634342
Short name T117
Test name
Test status
Simulation time 20171572261 ps
CPU time 190.19 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:15:05 PM PDT 24
Peak memory 235720 kb
Host smart-ae91328a-8d33-4967-8fd7-927f833e92df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596634342 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1596634342
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.220226266
Short name T30
Test name
Test status
Simulation time 1102000231 ps
CPU time 8.14 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:11:52 PM PDT 24
Peak memory 218400 kb
Host smart-d046e9ae-65af-4e29-9daf-b498168b8e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220226266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.220226266
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.40586290
Short name T268
Test name
Test status
Simulation time 7553187694 ps
CPU time 226.01 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:15:34 PM PDT 24
Peak memory 219024 kb
Host smart-74ae3f60-7319-4e81-8b45-31ab2d1374c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.40586290
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2999376052
Short name T188
Test name
Test status
Simulation time 368973908 ps
CPU time 18.02 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:16 PM PDT 24
Peak memory 218532 kb
Host smart-cb4aef3b-70b4-48fe-89fd-53215c82d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999376052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2999376052
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.448902126
Short name T272
Test name
Test status
Simulation time 260719321 ps
CPU time 11.82 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218944 kb
Host smart-5c900bef-d56a-4214-9303-3d9c3d896c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448902126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.448902126
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.595628642
Short name T73
Test name
Test status
Simulation time 2087777046 ps
CPU time 22.5 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 219128 kb
Host smart-0f4e782f-077b-456d-91a8-648c0ea77cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595628642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.595628642
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.382288005
Short name T14
Test name
Test status
Simulation time 4962973842 ps
CPU time 232.02 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:15:38 PM PDT 24
Peak memory 228008 kb
Host smart-ddb6fa60-1cf6-4236-99b6-b1322dce90ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382288005 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.382288005
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.794861956
Short name T326
Test name
Test status
Simulation time 266140036 ps
CPU time 9.62 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:16 PM PDT 24
Peak memory 218464 kb
Host smart-4f98f69b-4be8-4718-a3d1-cdad3abd9ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794861956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.794861956
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.356571860
Short name T310
Test name
Test status
Simulation time 9809556055 ps
CPU time 477.41 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:20:07 PM PDT 24
Peak memory 218864 kb
Host smart-5b833d79-da34-4ccb-8aad-aa9abf5bb9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356571860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.356571860
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3120118386
Short name T280
Test name
Test status
Simulation time 11684500446 ps
CPU time 29.27 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 218756 kb
Host smart-178e8c92-0571-49b0-a219-4cdba957aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120118386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3120118386
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3328063027
Short name T338
Test name
Test status
Simulation time 1089767492 ps
CPU time 12.01 seconds
Started Aug 15 06:12:14 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 218892 kb
Host smart-417156b8-9354-47e5-b60d-68df82336423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328063027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3328063027
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.424598957
Short name T218
Test name
Test status
Simulation time 790340868 ps
CPU time 39.11 seconds
Started Aug 15 06:12:19 PM PDT 24
Finished Aug 15 06:12:58 PM PDT 24
Peak memory 219408 kb
Host smart-47ee9422-142c-4dd2-99dd-7d7d7fa8bb4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424598957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.424598957
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.782758998
Short name T200
Test name
Test status
Simulation time 12953452706 ps
CPU time 128.92 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:14:11 PM PDT 24
Peak memory 235692 kb
Host smart-2076fdd5-fd8b-41d2-a8ed-b7e56ac680a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782758998 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.782758998
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2760979834
Short name T124
Test name
Test status
Simulation time 259189340 ps
CPU time 9.78 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 218336 kb
Host smart-c79a368b-5f6d-46b7-9b12-f6f6f0ee5aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760979834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2760979834
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3063672633
Short name T213
Test name
Test status
Simulation time 24739878155 ps
CPU time 354.81 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:18:02 PM PDT 24
Peak memory 237712 kb
Host smart-65dbe42b-56a5-4233-a134-3a4eedb24ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063672633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3063672633
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3136499924
Short name T299
Test name
Test status
Simulation time 976328989 ps
CPU time 18.09 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:25 PM PDT 24
Peak memory 218512 kb
Host smart-0375ae6b-b85b-445f-9283-fdefbdb53aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136499924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3136499924
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.377670731
Short name T306
Test name
Test status
Simulation time 1059771756 ps
CPU time 11.05 seconds
Started Aug 15 06:12:15 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 218824 kb
Host smart-d0cb3c18-6e04-42cf-81eb-bc44d8cbdbdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377670731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.377670731
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.224212575
Short name T75
Test name
Test status
Simulation time 544901135 ps
CPU time 38.18 seconds
Started Aug 15 06:12:29 PM PDT 24
Finished Aug 15 06:13:08 PM PDT 24
Peak memory 219296 kb
Host smart-e1e471f0-42a1-452d-ab8f-07edcff909d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224212575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.224212575
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3978382803
Short name T150
Test name
Test status
Simulation time 8594270672 ps
CPU time 106.48 seconds
Started Aug 15 06:12:18 PM PDT 24
Finished Aug 15 06:14:05 PM PDT 24
Peak memory 227484 kb
Host smart-102b36d5-8300-4ad8-bbea-74c44d375a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978382803 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3978382803
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2566482598
Short name T283
Test name
Test status
Simulation time 340755266 ps
CPU time 7.93 seconds
Started Aug 15 06:12:31 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 218356 kb
Host smart-258ff10b-3a1e-4baf-82d4-15f7e4e60862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566482598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2566482598
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1095896521
Short name T227
Test name
Test status
Simulation time 3551859283 ps
CPU time 250.62 seconds
Started Aug 15 06:12:01 PM PDT 24
Finished Aug 15 06:16:12 PM PDT 24
Peak memory 241376 kb
Host smart-afbe016f-ad5b-4672-9319-08362ac00e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095896521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1095896521
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.169761787
Short name T19
Test name
Test status
Simulation time 419971906 ps
CPU time 18.92 seconds
Started Aug 15 06:12:17 PM PDT 24
Finished Aug 15 06:12:36 PM PDT 24
Peak memory 218524 kb
Host smart-0cfb96e0-cab5-4ffc-9c69-f1c17be70812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169761787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.169761787
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3006858669
Short name T96
Test name
Test status
Simulation time 367798125 ps
CPU time 10.01 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:08 PM PDT 24
Peak memory 218672 kb
Host smart-d360592a-c151-409b-bcb8-c8938416fc1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006858669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3006858669
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.579578913
Short name T51
Test name
Test status
Simulation time 172163933 ps
CPU time 13.15 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:07 PM PDT 24
Peak memory 218548 kb
Host smart-beab6cf1-f1dc-4e43-a67c-f740196f55ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579578913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.579578913
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3248617143
Short name T353
Test name
Test status
Simulation time 2246146982 ps
CPU time 86.66 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:13:36 PM PDT 24
Peak memory 225780 kb
Host smart-e44371a9-f214-4c1a-8842-6b4e8f44c713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248617143 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3248617143
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.803023084
Short name T99
Test name
Test status
Simulation time 3100463659 ps
CPU time 9.44 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:14 PM PDT 24
Peak memory 218468 kb
Host smart-9c5fe996-7025-402c-8491-919a28033fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803023084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.803023084
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1266788525
Short name T255
Test name
Test status
Simulation time 4668389661 ps
CPU time 181.34 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:15:06 PM PDT 24
Peak memory 239336 kb
Host smart-7b543708-55b4-4842-a8ba-38da6d06911b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266788525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1266788525
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3464377350
Short name T157
Test name
Test status
Simulation time 519388761 ps
CPU time 21.58 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:22 PM PDT 24
Peak memory 218604 kb
Host smart-8d14ec9e-913b-4a8c-b12a-abe996bce410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464377350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3464377350
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2645301930
Short name T192
Test name
Test status
Simulation time 779654131 ps
CPU time 9.71 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218916 kb
Host smart-eb300364-635d-400b-90a4-39da93b189d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645301930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2645301930
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2817102034
Short name T3
Test name
Test status
Simulation time 2741643243 ps
CPU time 36.04 seconds
Started Aug 15 06:12:56 PM PDT 24
Finished Aug 15 06:13:32 PM PDT 24
Peak memory 219188 kb
Host smart-0c735fb1-2078-4ea9-8930-b677db987625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817102034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2817102034
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3261013480
Short name T257
Test name
Test status
Simulation time 7648793909 ps
CPU time 210.32 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:15:35 PM PDT 24
Peak memory 228220 kb
Host smart-d23c486b-b346-4969-9271-77117cfd2763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261013480 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3261013480
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.758231642
Short name T321
Test name
Test status
Simulation time 1035094167 ps
CPU time 9.61 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:11:52 PM PDT 24
Peak memory 219116 kb
Host smart-e1cb52a8-5fc6-4bce-96be-5bb45cf8745f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758231642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.758231642
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1428484892
Short name T43
Test name
Test status
Simulation time 6118940053 ps
CPU time 293.64 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:16:42 PM PDT 24
Peak memory 218924 kb
Host smart-e86744bf-1aa4-48a8-bfab-b034be0630cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428484892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1428484892
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.612466485
Short name T233
Test name
Test status
Simulation time 516349851 ps
CPU time 22.12 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 218632 kb
Host smart-546c42a9-1311-4b06-abf7-77213ab52a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612466485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.612466485
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2929799005
Short name T212
Test name
Test status
Simulation time 1041526103 ps
CPU time 11.64 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:06 PM PDT 24
Peak memory 218672 kb
Host smart-37d02d09-c986-4349-9547-ce7331af6018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929799005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2929799005
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3649821587
Short name T27
Test name
Test status
Simulation time 380321868 ps
CPU time 119.25 seconds
Started Aug 15 06:11:27 PM PDT 24
Finished Aug 15 06:13:26 PM PDT 24
Peak memory 238084 kb
Host smart-f3008448-32be-4a7a-8c91-08612276de03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649821587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3649821587
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4151702442
Short name T100
Test name
Test status
Simulation time 276304760 ps
CPU time 11.65 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:11:55 PM PDT 24
Peak memory 218532 kb
Host smart-4cb1d0a7-51c0-4b21-8cbd-a2190f1abd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151702442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4151702442
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.368103988
Short name T182
Test name
Test status
Simulation time 3213683880 ps
CPU time 41.33 seconds
Started Aug 15 06:11:37 PM PDT 24
Finished Aug 15 06:12:18 PM PDT 24
Peak memory 219236 kb
Host smart-a460ae0d-1620-4d3d-a87d-6b04e8668807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368103988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.368103988
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1014284213
Short name T307
Test name
Test status
Simulation time 5233131531 ps
CPU time 297.56 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:16:42 PM PDT 24
Peak memory 226340 kb
Host smart-24bf1354-62e8-4e0f-b45c-3b44e5641e43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014284213 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1014284213
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3909763371
Short name T231
Test name
Test status
Simulation time 468611726 ps
CPU time 9.45 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:12:25 PM PDT 24
Peak memory 218472 kb
Host smart-4e2db3e5-030a-46fa-b4fc-b991688b5dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909763371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3909763371
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1623153816
Short name T340
Test name
Test status
Simulation time 7999762202 ps
CPU time 198.88 seconds
Started Aug 15 06:12:12 PM PDT 24
Finished Aug 15 06:15:31 PM PDT 24
Peak memory 227604 kb
Host smart-09cbc828-6411-4e45-99d9-f1251be15340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623153816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1623153816
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.736794276
Short name T196
Test name
Test status
Simulation time 2066646435 ps
CPU time 18.59 seconds
Started Aug 15 06:12:19 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 218824 kb
Host smart-03996d63-5bc4-4cdf-b9cf-7ae87c77a41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736794276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.736794276
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3196072723
Short name T173
Test name
Test status
Simulation time 203536624 ps
CPU time 10.19 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218588 kb
Host smart-c7a0d6ef-b9cf-4406-b70e-4d70ad8f3806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196072723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3196072723
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1011169517
Short name T324
Test name
Test status
Simulation time 692171541 ps
CPU time 13.16 seconds
Started Aug 15 06:12:06 PM PDT 24
Finished Aug 15 06:12:24 PM PDT 24
Peak memory 218472 kb
Host smart-fe8ec671-0d69-4c1a-b3ae-6f306c4e6d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011169517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1011169517
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1107672634
Short name T293
Test name
Test status
Simulation time 1793172580 ps
CPU time 67.95 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:13:19 PM PDT 24
Peak memory 224704 kb
Host smart-49bcb46d-f9b9-4f90-80f3-385665b94d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107672634 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1107672634
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3757564373
Short name T148
Test name
Test status
Simulation time 993960971 ps
CPU time 9.2 seconds
Started Aug 15 06:13:30 PM PDT 24
Finished Aug 15 06:13:39 PM PDT 24
Peak memory 218372 kb
Host smart-2f4b4f1f-bba1-4a85-97df-ecbef592571e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757564373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3757564373
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1271540807
Short name T256
Test name
Test status
Simulation time 13759937819 ps
CPU time 205.57 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:15:41 PM PDT 24
Peak memory 233580 kb
Host smart-27cc6af9-69a5-4b4c-ad29-75fc72fa712b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271540807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1271540807
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1339643583
Short name T239
Test name
Test status
Simulation time 1318801590 ps
CPU time 18.42 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 218508 kb
Host smart-7e434805-60f6-4f7c-a99c-bb4575e67fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339643583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1339643583
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1980589593
Short name T290
Test name
Test status
Simulation time 262062586 ps
CPU time 11.51 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:12:22 PM PDT 24
Peak memory 218532 kb
Host smart-81cbee05-dafc-463d-a072-47e861d3cbc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980589593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1980589593
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3125929615
Short name T126
Test name
Test status
Simulation time 294113041 ps
CPU time 22.63 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:12:25 PM PDT 24
Peak memory 219184 kb
Host smart-cd04d245-a30e-4efa-846a-0bbb168c9de1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125929615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3125929615
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4015238910
Short name T238
Test name
Test status
Simulation time 4143671976 ps
CPU time 173.61 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:14:57 PM PDT 24
Peak memory 235724 kb
Host smart-55b69c33-0514-4d01-beb5-ab7f361c6eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015238910 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4015238910
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1458335277
Short name T191
Test name
Test status
Simulation time 661511804 ps
CPU time 7.99 seconds
Started Aug 15 06:12:20 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 218356 kb
Host smart-c2a31e13-5b76-4172-9665-4746001cd7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458335277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1458335277
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2968447887
Short name T158
Test name
Test status
Simulation time 4374222905 ps
CPU time 208.88 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:15:42 PM PDT 24
Peak memory 217520 kb
Host smart-94489a78-e358-4d73-a1a0-696258a7216a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968447887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2968447887
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1965364566
Short name T221
Test name
Test status
Simulation time 518081494 ps
CPU time 21.76 seconds
Started Aug 15 06:12:08 PM PDT 24
Finished Aug 15 06:12:30 PM PDT 24
Peak memory 218580 kb
Host smart-beb25acd-881c-4b38-aaaa-0c3a0ece82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965364566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1965364566
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2328393433
Short name T40
Test name
Test status
Simulation time 349386456 ps
CPU time 10.31 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218816 kb
Host smart-94092750-af6f-43fa-b43b-2afad140bb56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328393433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2328393433
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3620277187
Short name T127
Test name
Test status
Simulation time 539688151 ps
CPU time 22.1 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 219112 kb
Host smart-1417b12a-fc32-4120-b5e8-6754bd72f158
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620277187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3620277187
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3960028909
Short name T325
Test name
Test status
Simulation time 9030829709 ps
CPU time 98.42 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:13:42 PM PDT 24
Peak memory 225440 kb
Host smart-d122c071-d995-4bd6-8191-88ba4a7c62c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960028909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3960028909
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.660890730
Short name T214
Test name
Test status
Simulation time 16358842764 ps
CPU time 13.36 seconds
Started Aug 15 06:12:06 PM PDT 24
Finished Aug 15 06:12:19 PM PDT 24
Peak memory 218332 kb
Host smart-97ddda43-d03d-4962-989e-18161c651696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660890730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.660890730
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.134079989
Short name T265
Test name
Test status
Simulation time 8778030972 ps
CPU time 268.41 seconds
Started Aug 15 06:12:17 PM PDT 24
Finished Aug 15 06:16:45 PM PDT 24
Peak memory 237440 kb
Host smart-df77c993-1eac-46de-880d-86370bb9879a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134079989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.134079989
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1407511612
Short name T125
Test name
Test status
Simulation time 350736929 ps
CPU time 18.26 seconds
Started Aug 15 06:12:19 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 218616 kb
Host smart-ec4a341f-c93f-4af2-962a-3ea02833baa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407511612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1407511612
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3924992043
Short name T229
Test name
Test status
Simulation time 179142232 ps
CPU time 9.64 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:12:03 PM PDT 24
Peak memory 218852 kb
Host smart-69e0b0e1-094c-402f-937d-b4cbb4869894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924992043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3924992043
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1041924264
Short name T254
Test name
Test status
Simulation time 1458061613 ps
CPU time 21.85 seconds
Started Aug 15 06:12:20 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 219184 kb
Host smart-35bbf4fc-6fc4-4315-bca9-7f3537973ab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041924264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1041924264
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.720116541
Short name T349
Test name
Test status
Simulation time 506237945 ps
CPU time 9.54 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 218412 kb
Host smart-88376b73-c1cf-4911-b96d-32276dfdc718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720116541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.720116541
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1518736838
Short name T193
Test name
Test status
Simulation time 53008951863 ps
CPU time 308.72 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:17:16 PM PDT 24
Peak memory 218068 kb
Host smart-3ebe4736-1509-4658-bc07-e2d3a5b1f4d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518736838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1518736838
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.117145101
Short name T5
Test name
Test status
Simulation time 511940610 ps
CPU time 21.77 seconds
Started Aug 15 06:12:23 PM PDT 24
Finished Aug 15 06:12:45 PM PDT 24
Peak memory 218604 kb
Host smart-c0f77696-c411-4257-b9b4-9acca76ab61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117145101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.117145101
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3358182411
Short name T20
Test name
Test status
Simulation time 387704175 ps
CPU time 11.21 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:23 PM PDT 24
Peak memory 218788 kb
Host smart-e3814695-7768-46fa-8f13-1ad791661d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358182411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3358182411
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4021500485
Short name T308
Test name
Test status
Simulation time 3214457119 ps
CPU time 23.22 seconds
Started Aug 15 06:12:14 PM PDT 24
Finished Aug 15 06:12:37 PM PDT 24
Peak memory 219120 kb
Host smart-4de090b4-4b95-496f-9029-3e8e54af665f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021500485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4021500485
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1962663048
Short name T216
Test name
Test status
Simulation time 3072165342 ps
CPU time 154.81 seconds
Started Aug 15 06:12:28 PM PDT 24
Finished Aug 15 06:15:03 PM PDT 24
Peak memory 224376 kb
Host smart-eecd8c5a-5aaa-4598-a577-613e0d403d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962663048 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1962663048
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3616896152
Short name T341
Test name
Test status
Simulation time 1074917043 ps
CPU time 9.58 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:12:26 PM PDT 24
Peak memory 218296 kb
Host smart-445e5168-6e0e-4882-8547-449ae1c7c280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616896152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3616896152
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2904616284
Short name T24
Test name
Test status
Simulation time 2712581322 ps
CPU time 177.5 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:14:56 PM PDT 24
Peak memory 237592 kb
Host smart-a613f679-0619-417d-aeb5-180e78a66eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904616284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2904616284
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3522182591
Short name T330
Test name
Test status
Simulation time 3299970553 ps
CPU time 18.27 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 218964 kb
Host smart-c67f8152-707d-4f39-90f5-32c69dd8ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522182591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3522182591
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.26022481
Short name T343
Test name
Test status
Simulation time 1069614217 ps
CPU time 11.23 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 218896 kb
Host smart-3edff9f4-b70e-4ea5-94da-6286ee86182d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26022481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.26022481
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3145477507
Short name T253
Test name
Test status
Simulation time 1179485708 ps
CPU time 32.41 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:12:46 PM PDT 24
Peak memory 219128 kb
Host smart-5a5e79f3-1588-4a73-8135-96f475038bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145477507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3145477507
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2742377785
Short name T313
Test name
Test status
Simulation time 2658096535 ps
CPU time 123.53 seconds
Started Aug 15 06:12:15 PM PDT 24
Finished Aug 15 06:14:18 PM PDT 24
Peak memory 231664 kb
Host smart-22b61c15-1703-4535-8e0b-41834a0ab347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742377785 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2742377785
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.802145770
Short name T6
Test name
Test status
Simulation time 249145705 ps
CPU time 9.45 seconds
Started Aug 15 06:12:12 PM PDT 24
Finished Aug 15 06:12:22 PM PDT 24
Peak memory 218472 kb
Host smart-0822f8c2-26e8-48c0-9cf2-2b6e101b4183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802145770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.802145770
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3890645728
Short name T184
Test name
Test status
Simulation time 32882482415 ps
CPU time 303.38 seconds
Started Aug 15 06:12:06 PM PDT 24
Finished Aug 15 06:17:09 PM PDT 24
Peak memory 238580 kb
Host smart-217a0009-b4e5-49d4-8f04-e7060dd5e23e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890645728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3890645728
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1216093168
Short name T131
Test name
Test status
Simulation time 2555011653 ps
CPU time 18.38 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:29 PM PDT 24
Peak memory 218780 kb
Host smart-5b308df7-795d-4779-8f91-35eb2ad29308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216093168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1216093168
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2262156627
Short name T215
Test name
Test status
Simulation time 524171834 ps
CPU time 11.52 seconds
Started Aug 15 06:12:18 PM PDT 24
Finished Aug 15 06:12:30 PM PDT 24
Peak memory 218596 kb
Host smart-f80a1939-8ab3-4140-b453-ffb7dd7f82e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262156627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2262156627
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.455723077
Short name T314
Test name
Test status
Simulation time 510543828 ps
CPU time 26.52 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:24 PM PDT 24
Peak memory 219172 kb
Host smart-166c9f86-f9f2-4be6-9772-c7b55fd91031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455723077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.455723077
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1609063288
Short name T34
Test name
Test status
Simulation time 14390844342 ps
CPU time 203.86 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:15:36 PM PDT 24
Peak memory 227040 kb
Host smart-03cd6a11-5123-4bbc-8cf8-9c467e43e281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609063288 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1609063288
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3155963471
Short name T356
Test name
Test status
Simulation time 250144931 ps
CPU time 9.4 seconds
Started Aug 15 06:12:17 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 218312 kb
Host smart-8837c83b-03bb-4630-8d90-4cde9110f317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155963471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3155963471
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1044221783
Short name T260
Test name
Test status
Simulation time 16155480618 ps
CPU time 325.69 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:17:30 PM PDT 24
Peak memory 237636 kb
Host smart-64653fea-7c26-4907-8d2a-7e6f729f8056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044221783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1044221783
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1008277552
Short name T160
Test name
Test status
Simulation time 3133720980 ps
CPU time 28.76 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 219180 kb
Host smart-5486820b-00ea-478d-86ec-2510d2a69732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008277552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1008277552
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3416128521
Short name T176
Test name
Test status
Simulation time 179636149 ps
CPU time 9.97 seconds
Started Aug 15 06:12:51 PM PDT 24
Finished Aug 15 06:13:01 PM PDT 24
Peak memory 218656 kb
Host smart-79b03ac0-a368-4c7f-8ca5-ef3c531a11c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416128521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3416128521
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.759272753
Short name T76
Test name
Test status
Simulation time 1483886419 ps
CPU time 36.86 seconds
Started Aug 15 06:12:14 PM PDT 24
Finished Aug 15 06:12:51 PM PDT 24
Peak memory 219468 kb
Host smart-82c65eb8-fe73-47e4-80c9-59763d219917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759272753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.759272753
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1097591753
Short name T315
Test name
Test status
Simulation time 6494051258 ps
CPU time 125.58 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:14:04 PM PDT 24
Peak memory 225568 kb
Host smart-fe23f91e-72f3-43ca-be9a-bfe9a4a607ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097591753 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1097591753
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1293723435
Short name T156
Test name
Test status
Simulation time 252249277 ps
CPU time 9.65 seconds
Started Aug 15 06:12:08 PM PDT 24
Finished Aug 15 06:12:18 PM PDT 24
Peak memory 218440 kb
Host smart-a65fb0ba-b730-4b5b-b05b-1d6207881bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293723435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1293723435
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2563466456
Short name T38
Test name
Test status
Simulation time 10300085257 ps
CPU time 154.86 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:14:48 PM PDT 24
Peak memory 239336 kb
Host smart-e237d3ab-18f8-4b3f-8feb-98b21c871534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563466456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2563466456
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3666826818
Short name T205
Test name
Test status
Simulation time 1940132197 ps
CPU time 18.26 seconds
Started Aug 15 06:12:01 PM PDT 24
Finished Aug 15 06:12:19 PM PDT 24
Peak memory 218836 kb
Host smart-bc3d8e49-616d-4dd7-904a-c480da66e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666826818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3666826818
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4165804718
Short name T41
Test name
Test status
Simulation time 2862707844 ps
CPU time 10.34 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218984 kb
Host smart-050b4ff3-9fa7-4837-9cde-b65c6772a51c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165804718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4165804718
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2987721872
Short name T174
Test name
Test status
Simulation time 2589070201 ps
CPU time 22.11 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:33 PM PDT 24
Peak memory 219236 kb
Host smart-b7a15a87-6e73-4686-b909-530950f2d159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987721872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2987721872
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4144799781
Short name T287
Test name
Test status
Simulation time 16458997616 ps
CPU time 155.96 seconds
Started Aug 15 06:11:51 PM PDT 24
Finished Aug 15 06:14:27 PM PDT 24
Peak memory 235628 kb
Host smart-3065b8d8-db4f-4b7d-8c93-5a5d0f652e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144799781 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4144799781
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3947650156
Short name T132
Test name
Test status
Simulation time 719367271 ps
CPU time 8.09 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 218360 kb
Host smart-23578c8d-8fe3-480c-837c-6212a569cbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947650156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3947650156
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.464027581
Short name T271
Test name
Test status
Simulation time 4647915224 ps
CPU time 314.36 seconds
Started Aug 15 06:12:15 PM PDT 24
Finished Aug 15 06:17:30 PM PDT 24
Peak memory 243376 kb
Host smart-d8410818-2a5d-4aac-90ee-67f04e1be74a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464027581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.464027581
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3501021272
Short name T18
Test name
Test status
Simulation time 676942060 ps
CPU time 18.24 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 218620 kb
Host smart-99c12b9a-df87-4b50-9093-d69ab86c4280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501021272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3501021272
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.139592139
Short name T236
Test name
Test status
Simulation time 727668175 ps
CPU time 9.9 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218508 kb
Host smart-eeba1731-e9e5-4eeb-8d61-f5e8c06a86ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139592139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.139592139
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.88273148
Short name T242
Test name
Test status
Simulation time 1463084020 ps
CPU time 23.53 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:31 PM PDT 24
Peak memory 219184 kb
Host smart-c68c8f1b-72b7-4fac-8d69-78ae22efd337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88273148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.88273148
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.751795654
Short name T358
Test name
Test status
Simulation time 2838464262 ps
CPU time 160.16 seconds
Started Aug 15 06:12:18 PM PDT 24
Finished Aug 15 06:14:58 PM PDT 24
Peak memory 225416 kb
Host smart-a5d69e6a-5fff-4b64-919d-224cd0201217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751795654 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.751795654
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2648441444
Short name T118
Test name
Test status
Simulation time 259972822 ps
CPU time 9 seconds
Started Aug 15 06:12:53 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 218292 kb
Host smart-1e0230dc-773d-46ad-9124-8c733338de69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648441444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2648441444
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2088600195
Short name T278
Test name
Test status
Simulation time 4993915921 ps
CPU time 242.63 seconds
Started Aug 15 06:11:46 PM PDT 24
Finished Aug 15 06:15:49 PM PDT 24
Peak memory 237300 kb
Host smart-57ed6d30-bde5-4681-809c-5ca396656371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088600195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2088600195
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3141878245
Short name T45
Test name
Test status
Simulation time 365815406 ps
CPU time 18.08 seconds
Started Aug 15 06:11:39 PM PDT 24
Finished Aug 15 06:11:57 PM PDT 24
Peak memory 218460 kb
Host smart-550ad3d5-9857-4311-8201-ed9d4a766adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141878245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3141878245
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1107519684
Short name T134
Test name
Test status
Simulation time 1365126152 ps
CPU time 11.77 seconds
Started Aug 15 06:11:39 PM PDT 24
Finished Aug 15 06:11:51 PM PDT 24
Peak memory 218888 kb
Host smart-413eb7ea-8db8-413b-a3fa-2b5a57cef7fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107519684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1107519684
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3618615599
Short name T28
Test name
Test status
Simulation time 613408461 ps
CPU time 118.66 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:13:42 PM PDT 24
Peak memory 238028 kb
Host smart-2b9c9ab9-4e0c-4622-aae1-35ab23dfc5f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618615599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3618615599
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.924597786
Short name T302
Test name
Test status
Simulation time 176756049 ps
CPU time 10.01 seconds
Started Aug 15 06:11:35 PM PDT 24
Finished Aug 15 06:11:46 PM PDT 24
Peak memory 219140 kb
Host smart-b6f97809-7dc0-4b9a-85ae-000a1558b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924597786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.924597786
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3993834596
Short name T235
Test name
Test status
Simulation time 1680690760 ps
CPU time 33.87 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 219144 kb
Host smart-cfb5b02f-967e-4d1a-b142-8b7a478c27a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993834596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3993834596
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3895173251
Short name T294
Test name
Test status
Simulation time 2237855834 ps
CPU time 107.78 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:13:32 PM PDT 24
Peak memory 224400 kb
Host smart-69c7e9e8-d0f3-4b2b-8b75-cd53de221b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895173251 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3895173251
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2008919186
Short name T199
Test name
Test status
Simulation time 3904089901 ps
CPU time 13.26 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:12:16 PM PDT 24
Peak memory 218436 kb
Host smart-f54f8625-b666-41b3-95b7-91f0940f72a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008919186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2008919186
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.538365647
Short name T165
Test name
Test status
Simulation time 20009262110 ps
CPU time 320.27 seconds
Started Aug 15 06:12:14 PM PDT 24
Finished Aug 15 06:17:34 PM PDT 24
Peak memory 219148 kb
Host smart-27aa3810-7fcc-4a99-81a9-7d7268d82759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538365647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.538365647
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3916798323
Short name T311
Test name
Test status
Simulation time 1650891768 ps
CPU time 19.09 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:19 PM PDT 24
Peak memory 218912 kb
Host smart-2714cdab-d1dc-4c79-bd20-6d7c09be8be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916798323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3916798323
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3910697367
Short name T351
Test name
Test status
Simulation time 180689480 ps
CPU time 9.91 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:12:23 PM PDT 24
Peak memory 218636 kb
Host smart-3c3519d6-9932-403a-973b-50640a5bd1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910697367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3910697367
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1797046373
Short name T78
Test name
Test status
Simulation time 2122431258 ps
CPU time 30.87 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 219128 kb
Host smart-ce51ce1b-664a-4b4b-9979-5e3ec14ed2d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797046373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1797046373
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3246918023
Short name T177
Test name
Test status
Simulation time 2610032947 ps
CPU time 38.69 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:50 PM PDT 24
Peak memory 221752 kb
Host smart-3806b9f8-32d2-4694-89db-f61d2cfe028d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246918023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3246918023
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3412341473
Short name T167
Test name
Test status
Simulation time 1022594835 ps
CPU time 13.57 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:12:24 PM PDT 24
Peak memory 219104 kb
Host smart-96302971-8fd9-4e9e-8a31-18d529c9c4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412341473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3412341473
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4229618631
Short name T273
Test name
Test status
Simulation time 9247209721 ps
CPU time 181.56 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:14:57 PM PDT 24
Peak memory 241224 kb
Host smart-3428720c-7343-4e07-9c2c-dff4deda12c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229618631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4229618631
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.774770016
Short name T119
Test name
Test status
Simulation time 333256416 ps
CPU time 18.63 seconds
Started Aug 15 06:12:08 PM PDT 24
Finished Aug 15 06:12:27 PM PDT 24
Peak memory 218620 kb
Host smart-04c67328-f9c5-4ef6-8e2f-8e76f5480e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774770016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.774770016
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3499157364
Short name T309
Test name
Test status
Simulation time 3213238303 ps
CPU time 11.48 seconds
Started Aug 15 06:11:59 PM PDT 24
Finished Aug 15 06:12:11 PM PDT 24
Peak memory 218980 kb
Host smart-f8f2cd81-9804-4b1b-ba0b-cf2c87e40120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499157364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3499157364
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2054637940
Short name T220
Test name
Test status
Simulation time 10545266448 ps
CPU time 28.8 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 219228 kb
Host smart-29918a96-a55c-4fdc-ac3d-a89090eeeed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054637940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2054637940
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.660709184
Short name T240
Test name
Test status
Simulation time 3802759529 ps
CPU time 84.03 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:13:41 PM PDT 24
Peak memory 224420 kb
Host smart-a8869d63-ca72-433a-9451-a2501894345e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660709184 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.660709184
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2181816679
Short name T248
Test name
Test status
Simulation time 4090383884 ps
CPU time 13.06 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218336 kb
Host smart-37615e87-da4f-4936-96a9-2ab89c584222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181816679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2181816679
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3434779448
Short name T320
Test name
Test status
Simulation time 17852774508 ps
CPU time 289.13 seconds
Started Aug 15 06:13:30 PM PDT 24
Finished Aug 15 06:18:19 PM PDT 24
Peak memory 225612 kb
Host smart-eb1b6455-cdcc-4952-87fe-31746dc4e56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434779448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3434779448
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2234577638
Short name T123
Test name
Test status
Simulation time 3537072597 ps
CPU time 21.11 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:12:40 PM PDT 24
Peak memory 218908 kb
Host smart-6aea9bc4-2de9-45a3-922a-94f607355ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234577638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2234577638
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4186937765
Short name T97
Test name
Test status
Simulation time 271354935 ps
CPU time 11.8 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218576 kb
Host smart-709346e5-4917-40ff-bd00-60b3733e20d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186937765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4186937765
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4270501625
Short name T284
Test name
Test status
Simulation time 452365106 ps
CPU time 17.92 seconds
Started Aug 15 06:12:17 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 219156 kb
Host smart-d8b0dd21-ed31-43ca-aa82-9b410eec7146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270501625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4270501625
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4257057534
Short name T35
Test name
Test status
Simulation time 10146931676 ps
CPU time 101.28 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:13:44 PM PDT 24
Peak memory 225716 kb
Host smart-a7627cce-ca3d-4554-a02f-756000963cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257057534 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4257057534
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2818611767
Short name T296
Test name
Test status
Simulation time 1178184174 ps
CPU time 7.84 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:12:10 PM PDT 24
Peak memory 218308 kb
Host smart-c974ce2f-7b4b-409c-aa06-1f9e94d8c9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818611767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2818611767
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.936388168
Short name T267
Test name
Test status
Simulation time 5054433340 ps
CPU time 173.47 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:15:00 PM PDT 24
Peak memory 241916 kb
Host smart-8afeee85-47d1-41bf-bf34-8a5164433c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936388168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.936388168
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3201718139
Short name T209
Test name
Test status
Simulation time 13119076502 ps
CPU time 29.83 seconds
Started Aug 15 06:12:11 PM PDT 24
Finished Aug 15 06:12:41 PM PDT 24
Peak memory 219248 kb
Host smart-41f02488-d882-448d-9227-4658e1d18206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201718139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3201718139
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1592452439
Short name T161
Test name
Test status
Simulation time 343437272 ps
CPU time 10.23 seconds
Started Aug 15 06:11:59 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218656 kb
Host smart-127ae49a-7fe6-4ead-896e-c824988710db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592452439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1592452439
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3705115447
Short name T72
Test name
Test status
Simulation time 808771016 ps
CPU time 45.89 seconds
Started Aug 15 06:12:17 PM PDT 24
Finished Aug 15 06:13:03 PM PDT 24
Peak memory 219104 kb
Host smart-6cbcd635-4cec-46d5-801c-6f1f8b07f400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705115447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3705115447
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.601859628
Short name T146
Test name
Test status
Simulation time 3713331947 ps
CPU time 144.05 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:14:33 PM PDT 24
Peak memory 235704 kb
Host smart-f266310f-bf20-46f5-a111-ca4918a80eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601859628 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.601859628
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1323580628
Short name T206
Test name
Test status
Simulation time 168245521 ps
CPU time 8.19 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 218368 kb
Host smart-098d2e3d-aa1d-4a3a-8674-cfe478a8aca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323580628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1323580628
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.319725371
Short name T4
Test name
Test status
Simulation time 1187914233 ps
CPU time 106.42 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:13:57 PM PDT 24
Peak memory 243280 kb
Host smart-79cfa955-1017-4409-90e7-78523cb043aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319725371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.319725371
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1892304295
Short name T266
Test name
Test status
Simulation time 332431836 ps
CPU time 18.5 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 218636 kb
Host smart-595d1420-ca15-45d2-9aaf-b1f7eacdb348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892304295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1892304295
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2602991076
Short name T166
Test name
Test status
Simulation time 218155955 ps
CPU time 9.59 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:12:07 PM PDT 24
Peak memory 218672 kb
Host smart-b2b09770-cc31-4dcc-a956-433acca306cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602991076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2602991076
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4029745530
Short name T269
Test name
Test status
Simulation time 2676047871 ps
CPU time 31.28 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:12:42 PM PDT 24
Peak memory 219276 kb
Host smart-0ee01a56-12a8-4897-94e0-e58e0f4385d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029745530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4029745530
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.159386789
Short name T116
Test name
Test status
Simulation time 12135351687 ps
CPU time 110.22 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:13:58 PM PDT 24
Peak memory 226736 kb
Host smart-2a1b4e77-d731-4aaa-9030-60c197b3c1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159386789 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.159386789
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4069571499
Short name T202
Test name
Test status
Simulation time 989890279 ps
CPU time 13.35 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:12:15 PM PDT 24
Peak memory 218292 kb
Host smart-69e3321d-bf2d-4e09-833e-743fc3e715c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069571499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4069571499
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.659196172
Short name T180
Test name
Test status
Simulation time 20726873667 ps
CPU time 239.54 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:16:04 PM PDT 24
Peak memory 241240 kb
Host smart-b300d8cb-27c5-4b2b-bb51-5284011b26bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659196172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.659196172
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.141417386
Short name T279
Test name
Test status
Simulation time 511137135 ps
CPU time 18.07 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:12:16 PM PDT 24
Peak memory 218624 kb
Host smart-6d126a44-dbff-4cd7-b7af-9bf95496e15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141417386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.141417386
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3785788448
Short name T155
Test name
Test status
Simulation time 1029048401 ps
CPU time 11.53 seconds
Started Aug 15 06:12:08 PM PDT 24
Finished Aug 15 06:12:20 PM PDT 24
Peak memory 218644 kb
Host smart-d959b71f-d8f0-491d-a8ea-a8b8db7bbcb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785788448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3785788448
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1070742123
Short name T144
Test name
Test status
Simulation time 2018376312 ps
CPU time 26.32 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:12:26 PM PDT 24
Peak memory 219184 kb
Host smart-1bdae4f8-e0d9-4235-90ee-1eef189f4d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070742123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1070742123
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1878947748
Short name T48
Test name
Test status
Simulation time 9073430515 ps
CPU time 114.81 seconds
Started Aug 15 06:12:35 PM PDT 24
Finished Aug 15 06:14:30 PM PDT 24
Peak memory 226132 kb
Host smart-57c4ec1d-ede1-4cc4-b3c8-b3ace79c99c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878947748 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1878947748
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1789072199
Short name T21
Test name
Test status
Simulation time 950963555 ps
CPU time 9.75 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:14 PM PDT 24
Peak memory 218360 kb
Host smart-2146b0c4-71fd-4169-8c7d-32ef9c769777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789072199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1789072199
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1275802118
Short name T47
Test name
Test status
Simulation time 2711548981 ps
CPU time 146.12 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:14:35 PM PDT 24
Peak memory 228572 kb
Host smart-167c63bf-931e-46d0-89f0-7ce0205f3300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275802118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1275802118
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3038358058
Short name T244
Test name
Test status
Simulation time 332566948 ps
CPU time 18.66 seconds
Started Aug 15 06:12:26 PM PDT 24
Finished Aug 15 06:12:45 PM PDT 24
Peak memory 218520 kb
Host smart-9f94cd27-0fdb-4d5b-828b-23f5a69a9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038358058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3038358058
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3790567143
Short name T304
Test name
Test status
Simulation time 682889453 ps
CPU time 9.62 seconds
Started Aug 15 06:12:13 PM PDT 24
Finished Aug 15 06:12:22 PM PDT 24
Peak memory 218564 kb
Host smart-91924c95-ba8a-4468-8047-e1ef2afaac97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790567143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3790567143
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1699987599
Short name T262
Test name
Test status
Simulation time 552598105 ps
CPU time 23.2 seconds
Started Aug 15 06:12:08 PM PDT 24
Finished Aug 15 06:12:31 PM PDT 24
Peak memory 219156 kb
Host smart-7281ee0a-9a6e-44f9-a85c-f25b305fefaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699987599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1699987599
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1208525107
Short name T11
Test name
Test status
Simulation time 6635090217 ps
CPU time 196.8 seconds
Started Aug 15 06:12:02 PM PDT 24
Finished Aug 15 06:15:19 PM PDT 24
Peak memory 234696 kb
Host smart-9d0cf97d-adad-43d2-8bd5-0ee3b78f5242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208525107 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1208525107
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1729465394
Short name T336
Test name
Test status
Simulation time 167791217 ps
CPU time 8.19 seconds
Started Aug 15 06:12:23 PM PDT 24
Finished Aug 15 06:12:32 PM PDT 24
Peak memory 218384 kb
Host smart-37492e14-fbab-47e7-96ee-7cd7652c4644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729465394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1729465394
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2473657126
Short name T222
Test name
Test status
Simulation time 21861912713 ps
CPU time 241.19 seconds
Started Aug 15 06:12:10 PM PDT 24
Finished Aug 15 06:16:11 PM PDT 24
Peak memory 237752 kb
Host smart-29e18dc7-6478-4406-a219-71c5b218ff8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473657126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2473657126
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1694803165
Short name T295
Test name
Test status
Simulation time 2063255405 ps
CPU time 21.51 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:12:38 PM PDT 24
Peak memory 218788 kb
Host smart-8c24dac0-9fce-4e3f-b124-067290487cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694803165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1694803165
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2594375685
Short name T151
Test name
Test status
Simulation time 266480341 ps
CPU time 11.5 seconds
Started Aug 15 06:12:27 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 218580 kb
Host smart-036735a8-ff91-464d-a1ee-40c23eddfb79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594375685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2594375685
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3831422124
Short name T168
Test name
Test status
Simulation time 268218336 ps
CPU time 14.62 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:12:18 PM PDT 24
Peak memory 219124 kb
Host smart-48a57c41-bd09-46b6-98b4-6e081d725d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831422124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3831422124
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4159504912
Short name T331
Test name
Test status
Simulation time 2050692988 ps
CPU time 78.19 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:13:35 PM PDT 24
Peak memory 228692 kb
Host smart-fa0f9605-93d5-4a11-9121-4151663bcb3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159504912 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4159504912
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1593093374
Short name T276
Test name
Test status
Simulation time 1219329148 ps
CPU time 14.03 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:12:11 PM PDT 24
Peak memory 218408 kb
Host smart-13e4fa1c-4cf8-43c6-9980-40066d4e63ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593093374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1593093374
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.350798780
Short name T142
Test name
Test status
Simulation time 3294542863 ps
CPU time 102.32 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:13:59 PM PDT 24
Peak memory 240360 kb
Host smart-d8e60cbe-f486-4c3a-9e47-844ff8dc8a55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350798780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.350798780
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.652877322
Short name T136
Test name
Test status
Simulation time 517946780 ps
CPU time 21.77 seconds
Started Aug 15 06:12:04 PM PDT 24
Finished Aug 15 06:12:25 PM PDT 24
Peak memory 218760 kb
Host smart-1088ff1d-bbb9-4db7-89e5-1a03e5ae404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652877322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.652877322
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1539318182
Short name T198
Test name
Test status
Simulation time 186963131 ps
CPU time 10.55 seconds
Started Aug 15 06:12:19 PM PDT 24
Finished Aug 15 06:12:29 PM PDT 24
Peak memory 218624 kb
Host smart-07123726-3d40-4431-a91e-54a791c37cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539318182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1539318182
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2382905176
Short name T175
Test name
Test status
Simulation time 2387813852 ps
CPU time 33 seconds
Started Aug 15 06:12:16 PM PDT 24
Finished Aug 15 06:12:49 PM PDT 24
Peak memory 219236 kb
Host smart-ff56a918-d7c9-4e9c-b1b8-685ef139d397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382905176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2382905176
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4033470565
Short name T246
Test name
Test status
Simulation time 280080304 ps
CPU time 14.1 seconds
Started Aug 15 06:12:14 PM PDT 24
Finished Aug 15 06:12:28 PM PDT 24
Peak memory 220368 kb
Host smart-08570495-2485-43d7-b663-b100f1d84632
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033470565 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4033470565
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2486858559
Short name T323
Test name
Test status
Simulation time 917739897 ps
CPU time 9.59 seconds
Started Aug 15 06:12:07 PM PDT 24
Finished Aug 15 06:12:17 PM PDT 24
Peak memory 218288 kb
Host smart-e25f0b8b-af45-4a19-9f2e-23e9645d5be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486858559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2486858559
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2426687003
Short name T249
Test name
Test status
Simulation time 2831676202 ps
CPU time 198.47 seconds
Started Aug 15 06:12:23 PM PDT 24
Finished Aug 15 06:15:41 PM PDT 24
Peak memory 236288 kb
Host smart-dcc674c9-1e2e-4de2-b6d7-566e0da46c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426687003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2426687003
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1498714403
Short name T318
Test name
Test status
Simulation time 1500402313 ps
CPU time 18.58 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:12:21 PM PDT 24
Peak memory 218836 kb
Host smart-f76ce9c8-ea8b-4127-a4dc-16c03f4b64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498714403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1498714403
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1339477807
Short name T237
Test name
Test status
Simulation time 511904160 ps
CPU time 11.42 seconds
Started Aug 15 06:12:06 PM PDT 24
Finished Aug 15 06:12:18 PM PDT 24
Peak memory 218596 kb
Host smart-0c45defb-187b-4d4c-8f92-a215e4d6ae0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339477807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1339477807
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2471327518
Short name T135
Test name
Test status
Simulation time 1479388370 ps
CPU time 46.3 seconds
Started Aug 15 06:12:09 PM PDT 24
Finished Aug 15 06:12:56 PM PDT 24
Peak memory 219172 kb
Host smart-9d08356c-b2db-4b49-945c-658aa1c15b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471327518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2471327518
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1272508654
Short name T171
Test name
Test status
Simulation time 3035430041 ps
CPU time 51.09 seconds
Started Aug 15 06:12:05 PM PDT 24
Finished Aug 15 06:12:56 PM PDT 24
Peak memory 221824 kb
Host smart-30e992a0-2977-4350-b1c8-074d1e00df75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272508654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1272508654
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1060929175
Short name T143
Test name
Test status
Simulation time 362396298 ps
CPU time 7.97 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:11:52 PM PDT 24
Peak memory 218448 kb
Host smart-7301d6dc-cacf-4c50-9ea1-356708cfa279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060929175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1060929175
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.495757592
Short name T357
Test name
Test status
Simulation time 10549964829 ps
CPU time 175.07 seconds
Started Aug 15 06:11:36 PM PDT 24
Finished Aug 15 06:14:31 PM PDT 24
Peak memory 228368 kb
Host smart-6b7756eb-6761-42e8-947f-0a0668b716f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495757592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.495757592
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4184559812
Short name T285
Test name
Test status
Simulation time 1501027266 ps
CPU time 18.8 seconds
Started Aug 15 06:11:41 PM PDT 24
Finished Aug 15 06:12:00 PM PDT 24
Peak memory 218568 kb
Host smart-69ad83cf-9c7f-49ad-864b-8afdb2542002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184559812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4184559812
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4191463938
Short name T332
Test name
Test status
Simulation time 2552981080 ps
CPU time 11.75 seconds
Started Aug 15 06:11:39 PM PDT 24
Finished Aug 15 06:11:51 PM PDT 24
Peak memory 218792 kb
Host smart-c1ecfe8c-fda8-4e32-bf3e-43cdc4559ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191463938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4191463938
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3109460324
Short name T298
Test name
Test status
Simulation time 260720001 ps
CPU time 11.72 seconds
Started Aug 15 06:11:40 PM PDT 24
Finished Aug 15 06:11:52 PM PDT 24
Peak memory 219164 kb
Host smart-1594c271-8ab7-4a83-a2e8-eeeccda86f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109460324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3109460324
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2021317768
Short name T228
Test name
Test status
Simulation time 2293728137 ps
CPU time 26.73 seconds
Started Aug 15 06:11:42 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 219180 kb
Host smart-dbdb5a54-4a1c-4cf4-85dd-6f51d2ec1d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021317768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2021317768
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1208361457
Short name T217
Test name
Test status
Simulation time 8729335318 ps
CPU time 95.2 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:13:20 PM PDT 24
Peak memory 235660 kb
Host smart-44a2cf8f-cbf7-4cc5-8514-fffa69ed9b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208361457 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1208361457
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.391949835
Short name T139
Test name
Test status
Simulation time 751945882 ps
CPU time 8.02 seconds
Started Aug 15 06:11:57 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 218368 kb
Host smart-649912cf-a456-478a-909d-90e2107b88b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391949835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.391949835
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.14712676
Short name T33
Test name
Test status
Simulation time 6524928071 ps
CPU time 166.01 seconds
Started Aug 15 06:11:54 PM PDT 24
Finished Aug 15 06:14:40 PM PDT 24
Peak memory 236112 kb
Host smart-f5f60a00-0d1e-4dc1-bab4-807ed73c51a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_cor
rupt_sig_fatal_chk.14712676
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3989316196
Short name T207
Test name
Test status
Simulation time 1984215447 ps
CPU time 21.82 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:12 PM PDT 24
Peak memory 218652 kb
Host smart-f733dd52-1187-4362-9ec9-1ae50fae4384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989316196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3989316196
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2996078527
Short name T195
Test name
Test status
Simulation time 1030780684 ps
CPU time 11.34 seconds
Started Aug 15 06:11:33 PM PDT 24
Finished Aug 15 06:11:45 PM PDT 24
Peak memory 218876 kb
Host smart-34b8aac9-4a14-4e65-b177-6e5648a6e233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996078527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2996078527
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.371523792
Short name T77
Test name
Test status
Simulation time 1057486955 ps
CPU time 16.48 seconds
Started Aug 15 06:11:40 PM PDT 24
Finished Aug 15 06:11:57 PM PDT 24
Peak memory 219120 kb
Host smart-ae8baf5f-e5b9-4fd9-bfe9-468514c04e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371523792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.371523792
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.257061462
Short name T183
Test name
Test status
Simulation time 363005446 ps
CPU time 25.96 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:12:10 PM PDT 24
Peak memory 219148 kb
Host smart-6ebe0b40-d3d1-45a0-b0da-17d354f2283b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257061462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.257061462
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3189696959
Short name T346
Test name
Test status
Simulation time 2255555008 ps
CPU time 9.49 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 218512 kb
Host smart-84e790dc-bc6b-466c-ad47-fe9cc115b2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189696959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3189696959
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.564836677
Short name T186
Test name
Test status
Simulation time 3478301229 ps
CPU time 175.21 seconds
Started Aug 15 06:11:58 PM PDT 24
Finished Aug 15 06:14:53 PM PDT 24
Peak memory 243412 kb
Host smart-edaf8cfb-056c-4886-932b-3aad5d1dc342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564836677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.564836677
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3008173552
Short name T263
Test name
Test status
Simulation time 347241392 ps
CPU time 18.55 seconds
Started Aug 15 06:11:43 PM PDT 24
Finished Aug 15 06:12:02 PM PDT 24
Peak memory 218560 kb
Host smart-6387e239-03d2-4ea7-955b-380ae471e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008173552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3008173552
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1419302333
Short name T286
Test name
Test status
Simulation time 497333680 ps
CPU time 11.44 seconds
Started Aug 15 06:11:49 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 218836 kb
Host smart-954f368f-6ee4-45bb-9b90-a651b434ec58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419302333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1419302333
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3126793955
Short name T74
Test name
Test status
Simulation time 1036623173 ps
CPU time 10.08 seconds
Started Aug 15 06:11:44 PM PDT 24
Finished Aug 15 06:11:54 PM PDT 24
Peak memory 219096 kb
Host smart-492fcba2-b6ed-40b5-8ea8-d04e0d509724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126793955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3126793955
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.16688894
Short name T159
Test name
Test status
Simulation time 760488597 ps
CPU time 10.15 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 219088 kb
Host smart-9b5fff89-b46e-40be-8ebd-b55db2ad4484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.rom_ctrl_stress_all.16688894
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1364707612
Short name T16
Test name
Test status
Simulation time 342142255 ps
CPU time 15.56 seconds
Started Aug 15 06:11:55 PM PDT 24
Finished Aug 15 06:12:10 PM PDT 24
Peak memory 221556 kb
Host smart-f1aa973e-efab-48ff-97cb-2dedaa8b826f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364707612 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1364707612
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4189172870
Short name T129
Test name
Test status
Simulation time 991618209 ps
CPU time 9.41 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:03 PM PDT 24
Peak memory 218660 kb
Host smart-928f3e26-d599-403e-a083-318c03edbe06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189172870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4189172870
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1862369579
Short name T322
Test name
Test status
Simulation time 4074238236 ps
CPU time 239.43 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:15:49 PM PDT 24
Peak memory 236556 kb
Host smart-5d597398-09f2-47af-baac-fb5009e3063f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862369579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1862369579
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2657776235
Short name T288
Test name
Test status
Simulation time 1766352992 ps
CPU time 21.03 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:14 PM PDT 24
Peak memory 218896 kb
Host smart-a7b29ab9-e6fc-47b9-8b83-386fdc5a1475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657776235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2657776235
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1262822262
Short name T169
Test name
Test status
Simulation time 1024773070 ps
CPU time 14.99 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:05 PM PDT 24
Peak memory 219204 kb
Host smart-53c5ad46-6a47-49de-8b4c-fa63df66a13b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262822262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1262822262
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1002948716
Short name T204
Test name
Test status
Simulation time 515193673 ps
CPU time 11.99 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:03 PM PDT 24
Peak memory 218492 kb
Host smart-3a3c618a-1626-4751-b68a-3e72daa62bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002948716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1002948716
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2543543921
Short name T291
Test name
Test status
Simulation time 1117313498 ps
CPU time 16.34 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:12:04 PM PDT 24
Peak memory 219120 kb
Host smart-15888e1c-7edf-4e94-a78b-be30145b4804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543543921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2543543921
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.135864892
Short name T261
Test name
Test status
Simulation time 2809306856 ps
CPU time 47.04 seconds
Started Aug 15 06:11:48 PM PDT 24
Finished Aug 15 06:12:35 PM PDT 24
Peak memory 223608 kb
Host smart-506ae039-6a7f-4796-be2f-986ce322533f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135864892 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.135864892
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1890939519
Short name T162
Test name
Test status
Simulation time 662154931 ps
CPU time 7.91 seconds
Started Aug 15 06:11:53 PM PDT 24
Finished Aug 15 06:12:01 PM PDT 24
Peak memory 218440 kb
Host smart-d38d6946-0ced-47d2-8509-7170b06d8318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890939519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1890939519
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4026801990
Short name T230
Test name
Test status
Simulation time 14046940176 ps
CPU time 223.38 seconds
Started Aug 15 06:12:00 PM PDT 24
Finished Aug 15 06:15:44 PM PDT 24
Peak memory 233724 kb
Host smart-ab7e4889-9665-42b4-bd70-2ee1c952e51d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026801990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4026801990
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3974654025
Short name T121
Test name
Test status
Simulation time 544996951 ps
CPU time 21.62 seconds
Started Aug 15 06:11:47 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 218564 kb
Host smart-d32997f0-a77b-4168-8c4f-31d156159a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974654025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3974654025
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2511310230
Short name T39
Test name
Test status
Simulation time 273437600 ps
CPU time 11.63 seconds
Started Aug 15 06:11:45 PM PDT 24
Finished Aug 15 06:11:56 PM PDT 24
Peak memory 218648 kb
Host smart-2b006734-7914-4d10-bdbe-6e8f2399dc03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511310230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2511310230
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3440488013
Short name T219
Test name
Test status
Simulation time 187954128 ps
CPU time 10.05 seconds
Started Aug 15 06:12:03 PM PDT 24
Finished Aug 15 06:12:13 PM PDT 24
Peak memory 219136 kb
Host smart-8f2d02dc-cd16-4104-9408-ac59cb7fa412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440488013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3440488013
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.83818955
Short name T301
Test name
Test status
Simulation time 2891990964 ps
CPU time 41.67 seconds
Started Aug 15 06:11:50 PM PDT 24
Finished Aug 15 06:12:32 PM PDT 24
Peak memory 219228 kb
Host smart-ff795c61-a38a-4410-9291-92a960488825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83818955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.rom_ctrl_stress_all.83818955
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.357658084
Short name T277
Test name
Test status
Simulation time 10510736197 ps
CPU time 100.01 seconds
Started Aug 15 06:11:41 PM PDT 24
Finished Aug 15 06:13:21 PM PDT 24
Peak memory 226808 kb
Host smart-e9cc3a02-2dc8-4108-a658-9d8aa3de75d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357658084 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.357658084
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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