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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.89 92.70 97.68 100.00 98.97 97.90 98.83


Total test records in report: 455
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T296 /workspace/coverage/default/6.rom_ctrl_smoke.184129071 Aug 16 04:54:27 PM PDT 24 Aug 16 04:54:38 PM PDT 24 531115084 ps
T297 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2332429771 Aug 16 04:54:08 PM PDT 24 Aug 16 05:00:03 PM PDT 24 5621194829 ps
T298 /workspace/coverage/default/44.rom_ctrl_alert_test.2860762662 Aug 16 04:54:45 PM PDT 24 Aug 16 04:54:54 PM PDT 24 1031565071 ps
T299 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3389874337 Aug 16 04:54:36 PM PDT 24 Aug 16 04:54:58 PM PDT 24 1030649499 ps
T300 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1408363660 Aug 16 04:54:12 PM PDT 24 Aug 16 04:54:24 PM PDT 24 263139430 ps
T301 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1614692223 Aug 16 04:54:15 PM PDT 24 Aug 16 04:57:13 PM PDT 24 5966459305 ps
T302 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.946361870 Aug 16 04:54:39 PM PDT 24 Aug 16 04:54:49 PM PDT 24 729308717 ps
T303 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.407931494 Aug 16 04:54:04 PM PDT 24 Aug 16 04:54:26 PM PDT 24 1030483081 ps
T304 /workspace/coverage/default/3.rom_ctrl_stress_all.3488768369 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:33 PM PDT 24 564993501 ps
T305 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4206142748 Aug 16 04:54:49 PM PDT 24 Aug 16 04:55:01 PM PDT 24 266562016 ps
T306 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.501469878 Aug 16 04:54:52 PM PDT 24 Aug 16 04:55:14 PM PDT 24 1978368180 ps
T307 /workspace/coverage/default/35.rom_ctrl_alert_test.1004726588 Aug 16 04:54:41 PM PDT 24 Aug 16 04:54:49 PM PDT 24 170408882 ps
T308 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.638239137 Aug 16 04:54:28 PM PDT 24 Aug 16 04:58:32 PM PDT 24 3484891294 ps
T309 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1157960353 Aug 16 04:54:27 PM PDT 24 Aug 16 04:54:48 PM PDT 24 518445987 ps
T310 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.118157962 Aug 16 04:54:44 PM PDT 24 Aug 16 04:56:34 PM PDT 24 6853532283 ps
T311 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2349436969 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:12 PM PDT 24 269395441 ps
T312 /workspace/coverage/default/14.rom_ctrl_alert_test.3095635465 Aug 16 04:54:24 PM PDT 24 Aug 16 04:54:33 PM PDT 24 507286977 ps
T313 /workspace/coverage/default/2.rom_ctrl_alert_test.1089871763 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:06 PM PDT 24 332582675 ps
T314 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2796551341 Aug 16 04:54:46 PM PDT 24 Aug 16 04:57:33 PM PDT 24 3018224200 ps
T315 /workspace/coverage/default/45.rom_ctrl_alert_test.3681694100 Aug 16 04:54:46 PM PDT 24 Aug 16 04:54:55 PM PDT 24 2251176960 ps
T316 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2084560768 Aug 16 04:54:47 PM PDT 24 Aug 16 04:55:10 PM PDT 24 2347783553 ps
T317 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2410598799 Aug 16 04:54:08 PM PDT 24 Aug 16 04:58:15 PM PDT 24 58513469032 ps
T318 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1563902850 Aug 16 04:54:38 PM PDT 24 Aug 16 04:54:57 PM PDT 24 4129722300 ps
T319 /workspace/coverage/default/11.rom_ctrl_alert_test.4170814731 Aug 16 04:54:07 PM PDT 24 Aug 16 04:54:16 PM PDT 24 249501030 ps
T51 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1112646282 Aug 16 04:54:06 PM PDT 24 Aug 16 04:54:24 PM PDT 24 1326037991 ps
T320 /workspace/coverage/default/44.rom_ctrl_stress_all.356489924 Aug 16 04:54:45 PM PDT 24 Aug 16 04:55:04 PM PDT 24 1408698149 ps
T23 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.766408576 Aug 16 04:54:03 PM PDT 24 Aug 16 04:56:09 PM PDT 24 3152238126 ps
T321 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1586709617 Aug 16 04:54:33 PM PDT 24 Aug 16 04:57:37 PM PDT 24 23751919806 ps
T322 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2926598139 Aug 16 04:54:33 PM PDT 24 Aug 16 04:56:26 PM PDT 24 26997558152 ps
T323 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1539099826 Aug 16 04:54:08 PM PDT 24 Aug 16 04:54:27 PM PDT 24 1376683161 ps
T324 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2696689696 Aug 16 04:54:36 PM PDT 24 Aug 16 04:54:49 PM PDT 24 261439392 ps
T325 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1668711427 Aug 16 04:54:54 PM PDT 24 Aug 16 04:55:05 PM PDT 24 1015776036 ps
T326 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1509948936 Aug 16 04:54:28 PM PDT 24 Aug 16 04:54:49 PM PDT 24 2063146389 ps
T327 /workspace/coverage/default/12.rom_ctrl_stress_all.1510729814 Aug 16 04:54:06 PM PDT 24 Aug 16 04:54:33 PM PDT 24 382929795 ps
T328 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3307674580 Aug 16 04:54:10 PM PDT 24 Aug 16 04:59:14 PM PDT 24 8178606503 ps
T329 /workspace/coverage/default/48.rom_ctrl_stress_all.1610534437 Aug 16 04:54:52 PM PDT 24 Aug 16 04:55:30 PM PDT 24 759537463 ps
T330 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3659758753 Aug 16 04:54:39 PM PDT 24 Aug 16 04:54:50 PM PDT 24 2132859520 ps
T331 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4190449931 Aug 16 04:54:35 PM PDT 24 Aug 16 04:54:47 PM PDT 24 1210388645 ps
T332 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1412348752 Aug 16 04:54:52 PM PDT 24 Aug 16 04:59:12 PM PDT 24 9640873930 ps
T333 /workspace/coverage/default/43.rom_ctrl_stress_all.1271180551 Aug 16 04:54:47 PM PDT 24 Aug 16 04:55:15 PM PDT 24 1608729270 ps
T334 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1530827842 Aug 16 04:54:46 PM PDT 24 Aug 16 04:54:57 PM PDT 24 271892835 ps
T335 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2716543609 Aug 16 04:54:45 PM PDT 24 Aug 16 04:58:08 PM PDT 24 3081738612 ps
T336 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4293094884 Aug 16 04:54:39 PM PDT 24 Aug 16 04:58:52 PM PDT 24 27395945629 ps
T337 /workspace/coverage/default/23.rom_ctrl_alert_test.1452760459 Aug 16 04:54:31 PM PDT 24 Aug 16 04:54:41 PM PDT 24 262572792 ps
T338 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3719194817 Aug 16 04:54:04 PM PDT 24 Aug 16 04:58:13 PM PDT 24 4774587432 ps
T339 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.29676522 Aug 16 04:54:21 PM PDT 24 Aug 16 04:54:40 PM PDT 24 5512589223 ps
T340 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2064940987 Aug 16 04:54:36 PM PDT 24 Aug 16 04:54:48 PM PDT 24 1076008197 ps
T341 /workspace/coverage/default/48.rom_ctrl_alert_test.67492697 Aug 16 04:54:52 PM PDT 24 Aug 16 04:55:02 PM PDT 24 259838977 ps
T342 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3338606860 Aug 16 04:54:29 PM PDT 24 Aug 16 04:55:44 PM PDT 24 2870244139 ps
T343 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2970003552 Aug 16 04:54:39 PM PDT 24 Aug 16 05:00:30 PM PDT 24 66835570293 ps
T344 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3074266257 Aug 16 04:54:06 PM PDT 24 Aug 16 04:54:18 PM PDT 24 1067550565 ps
T345 /workspace/coverage/default/10.rom_ctrl_alert_test.3589596037 Aug 16 04:54:09 PM PDT 24 Aug 16 04:54:17 PM PDT 24 551838824 ps
T346 /workspace/coverage/default/7.rom_ctrl_smoke.570878715 Aug 16 04:54:03 PM PDT 24 Aug 16 04:54:13 PM PDT 24 2165371572 ps
T347 /workspace/coverage/default/3.rom_ctrl_alert_test.3066096798 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:09 PM PDT 24 660836196 ps
T348 /workspace/coverage/default/0.rom_ctrl_stress_all.1450301608 Aug 16 04:54:07 PM PDT 24 Aug 16 04:54:37 PM PDT 24 2088531631 ps
T349 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2504287828 Aug 16 04:54:34 PM PDT 24 Aug 16 04:57:08 PM PDT 24 26343307376 ps
T350 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1396765944 Aug 16 04:54:01 PM PDT 24 Aug 16 04:56:50 PM PDT 24 4058115905 ps
T351 /workspace/coverage/default/26.rom_ctrl_alert_test.3887536804 Aug 16 04:54:40 PM PDT 24 Aug 16 04:54:49 PM PDT 24 203755763 ps
T352 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3886515015 Aug 16 04:54:52 PM PDT 24 Aug 16 05:00:09 PM PDT 24 5456596526 ps
T353 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4041641940 Aug 16 04:54:05 PM PDT 24 Aug 16 04:54:24 PM PDT 24 1223766054 ps
T60 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2356291320 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:04 PM PDT 24 688074674 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1290580726 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:00 PM PDT 24 986573661 ps
T354 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.752474692 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:12 PM PDT 24 1032256532 ps
T62 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3115117844 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:06 PM PDT 24 167435945 ps
T355 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.895984090 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:01 PM PDT 24 260148998 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4215921109 Aug 16 04:53:54 PM PDT 24 Aug 16 04:54:08 PM PDT 24 1461812794 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.144316900 Aug 16 04:53:49 PM PDT 24 Aug 16 04:53:57 PM PDT 24 174336510 ps
T357 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.94146178 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:57 PM PDT 24 495063313 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.634702800 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:12 PM PDT 24 1116850169 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2097004392 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:38 PM PDT 24 1022865499 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.775036944 Aug 16 04:53:48 PM PDT 24 Aug 16 04:54:03 PM PDT 24 260267907 ps
T359 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3482353147 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:11 PM PDT 24 260468239 ps
T92 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.620289071 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:08 PM PDT 24 1499066101 ps
T360 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4110726188 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:09 PM PDT 24 549586679 ps
T57 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.908073929 Aug 16 04:53:56 PM PDT 24 Aug 16 04:56:28 PM PDT 24 1480194889 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.930737921 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:03 PM PDT 24 1502289335 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3846911184 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:56 PM PDT 24 245249037 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2713493092 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:11 PM PDT 24 4095621462 ps
T58 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3039777999 Aug 16 04:53:54 PM PDT 24 Aug 16 04:55:17 PM PDT 24 346661870 ps
T59 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2476795352 Aug 16 04:53:50 PM PDT 24 Aug 16 04:56:21 PM PDT 24 328637363 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2744239857 Aug 16 04:54:02 PM PDT 24 Aug 16 04:54:15 PM PDT 24 1976628310 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2637629844 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:02 PM PDT 24 1029134695 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.55585465 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:07 PM PDT 24 1833293030 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1017090339 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:04 PM PDT 24 260781684 ps
T363 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3336988457 Aug 16 04:54:02 PM PDT 24 Aug 16 04:54:13 PM PDT 24 635712334 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.615414262 Aug 16 04:54:09 PM PDT 24 Aug 16 04:54:18 PM PDT 24 1078679613 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1278862597 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:07 PM PDT 24 825472844 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2003309768 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:06 PM PDT 24 331828379 ps
T366 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3241650709 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:09 PM PDT 24 518668959 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3202404405 Aug 16 04:53:48 PM PDT 24 Aug 16 04:56:24 PM PDT 24 900842198 ps
T94 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.214939613 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:55 PM PDT 24 1610064996 ps
T71 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3435651301 Aug 16 04:53:47 PM PDT 24 Aug 16 04:53:57 PM PDT 24 249457753 ps
T105 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3096157145 Aug 16 04:54:04 PM PDT 24 Aug 16 04:55:26 PM PDT 24 1139101547 ps
T72 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2414361377 Aug 16 04:54:13 PM PDT 24 Aug 16 04:54:26 PM PDT 24 1991964294 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2541072967 Aug 16 04:53:55 PM PDT 24 Aug 16 04:55:12 PM PDT 24 308534840 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1393448675 Aug 16 04:53:59 PM PDT 24 Aug 16 04:55:21 PM PDT 24 2155855697 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3331576866 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:07 PM PDT 24 494438714 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2595178376 Aug 16 04:54:06 PM PDT 24 Aug 16 04:55:01 PM PDT 24 6413333266 ps
T369 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2654492244 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:07 PM PDT 24 1355442030 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1332871470 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:13 PM PDT 24 19697639915 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3634685592 Aug 16 04:54:08 PM PDT 24 Aug 16 04:54:18 PM PDT 24 2231871219 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2162558778 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:45 PM PDT 24 4479097660 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2792016138 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:11 PM PDT 24 2024263086 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3132226732 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:09 PM PDT 24 289052365 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2766888917 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:01 PM PDT 24 664973042 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2279292228 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:04 PM PDT 24 174156506 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2079008541 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:55 PM PDT 24 1596258930 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4163219234 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:05 PM PDT 24 174169349 ps
T377 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1932343495 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:16 PM PDT 24 1545214252 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.298078234 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:06 PM PDT 24 347750712 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2152338139 Aug 16 04:54:07 PM PDT 24 Aug 16 04:54:16 PM PDT 24 259496641 ps
T83 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2485079486 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:56 PM PDT 24 1038669205 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1257649646 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:30 PM PDT 24 4024783663 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4249184301 Aug 16 04:53:54 PM PDT 24 Aug 16 04:54:03 PM PDT 24 689269706 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2332996509 Aug 16 04:54:03 PM PDT 24 Aug 16 04:54:39 PM PDT 24 6830863675 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1458019018 Aug 16 04:53:49 PM PDT 24 Aug 16 04:54:25 PM PDT 24 1378686008 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1934918066 Aug 16 04:54:02 PM PDT 24 Aug 16 04:54:10 PM PDT 24 173080209 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4186001153 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:10 PM PDT 24 659752348 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2441981923 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:11 PM PDT 24 984071681 ps
T381 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2291370635 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:11 PM PDT 24 250583637 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2995782938 Aug 16 04:53:49 PM PDT 24 Aug 16 04:54:03 PM PDT 24 250337043 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4183441141 Aug 16 04:53:57 PM PDT 24 Aug 16 04:56:29 PM PDT 24 315092988 ps
T102 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3458900421 Aug 16 04:53:58 PM PDT 24 Aug 16 04:56:32 PM PDT 24 461794054 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3746442160 Aug 16 04:54:06 PM PDT 24 Aug 16 04:54:19 PM PDT 24 261457601 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2769759496 Aug 16 04:54:00 PM PDT 24 Aug 16 04:55:21 PM PDT 24 907615409 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1542529909 Aug 16 04:54:06 PM PDT 24 Aug 16 04:54:17 PM PDT 24 615164121 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.413043156 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:10 PM PDT 24 4139516384 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2404335318 Aug 16 04:53:50 PM PDT 24 Aug 16 04:53:58 PM PDT 24 362461951 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.925003318 Aug 16 04:53:50 PM PDT 24 Aug 16 04:54:00 PM PDT 24 1378157914 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2411176043 Aug 16 04:53:48 PM PDT 24 Aug 16 04:53:58 PM PDT 24 260792290 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3105876627 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:17 PM PDT 24 270522115 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.205901327 Aug 16 04:53:49 PM PDT 24 Aug 16 04:53:57 PM PDT 24 634959609 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2371310938 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:04 PM PDT 24 1028419346 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2242579426 Aug 16 04:53:57 PM PDT 24 Aug 16 04:56:32 PM PDT 24 1573694974 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1960902196 Aug 16 04:53:50 PM PDT 24 Aug 16 04:53:59 PM PDT 24 504484512 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3547253808 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:10 PM PDT 24 661544428 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2801411814 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:59 PM PDT 24 3094195277 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1882836009 Aug 16 04:54:03 PM PDT 24 Aug 16 04:54:11 PM PDT 24 353516121 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1744481466 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:03 PM PDT 24 1184416736 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.892126361 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:10 PM PDT 24 688843761 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.210284913 Aug 16 04:54:03 PM PDT 24 Aug 16 04:55:23 PM PDT 24 475922551 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.356250507 Aug 16 04:53:48 PM PDT 24 Aug 16 04:54:24 PM PDT 24 1359741559 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1184746462 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:04 PM PDT 24 340763789 ps
T401 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1925545290 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:11 PM PDT 24 569599401 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2659627319 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:01 PM PDT 24 517796982 ps
T403 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.863762970 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:10 PM PDT 24 383025992 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1611762187 Aug 16 04:53:46 PM PDT 24 Aug 16 04:54:02 PM PDT 24 1002153789 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3673455852 Aug 16 04:53:50 PM PDT 24 Aug 16 04:54:00 PM PDT 24 1321927997 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3818410958 Aug 16 04:53:49 PM PDT 24 Aug 16 04:54:52 PM PDT 24 4479814391 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3706909387 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:06 PM PDT 24 333954731 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.617762397 Aug 16 04:54:00 PM PDT 24 Aug 16 04:56:32 PM PDT 24 2065353467 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3575483047 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:35 PM PDT 24 1970549859 ps
T408 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4177331813 Aug 16 04:53:58 PM PDT 24 Aug 16 04:56:31 PM PDT 24 1547215906 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1585983941 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:07 PM PDT 24 387042279 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.517959163 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:28 PM PDT 24 6197714311 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1963564458 Aug 16 04:53:58 PM PDT 24 Aug 16 04:56:30 PM PDT 24 380352111 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3844412052 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:06 PM PDT 24 1033086156 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2292620552 Aug 16 04:53:49 PM PDT 24 Aug 16 04:54:02 PM PDT 24 786352724 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1283121905 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:10 PM PDT 24 1304561304 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.199412160 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:08 PM PDT 24 340290466 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.33942399 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:05 PM PDT 24 1967294110 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4104878452 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:04 PM PDT 24 172735736 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2778868160 Aug 16 04:53:51 PM PDT 24 Aug 16 04:53:59 PM PDT 24 751813620 ps
T419 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2431028243 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:10 PM PDT 24 172762131 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2705777596 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:37 PM PDT 24 2849559522 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.862160729 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:06 PM PDT 24 1077998843 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3933761321 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:05 PM PDT 24 772591028 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4140218700 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:50 PM PDT 24 2142849725 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1677054522 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:51 PM PDT 24 49298542528 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2057744450 Aug 16 04:53:51 PM PDT 24 Aug 16 04:53:59 PM PDT 24 353113564 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2069502649 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:07 PM PDT 24 254459015 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.908529430 Aug 16 04:54:05 PM PDT 24 Aug 16 04:54:41 PM PDT 24 2993355849 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1255785425 Aug 16 04:53:49 PM PDT 24 Aug 16 04:53:59 PM PDT 24 259426109 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3942731683 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:09 PM PDT 24 497997208 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.872977523 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:12 PM PDT 24 497330846 ps
T103 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2892311728 Aug 16 04:53:57 PM PDT 24 Aug 16 04:56:36 PM PDT 24 469660547 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.493928288 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:08 PM PDT 24 1839590582 ps
T432 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2906019855 Aug 16 04:54:02 PM PDT 24 Aug 16 04:54:12 PM PDT 24 1065989461 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2399302492 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:02 PM PDT 24 372554160 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3812927521 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:06 PM PDT 24 1037769120 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.380131800 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:04 PM PDT 24 379517824 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1102155863 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:03 PM PDT 24 404064513 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3529307300 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:01 PM PDT 24 172513222 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2001352722 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:10 PM PDT 24 257350938 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2048090616 Aug 16 04:53:56 PM PDT 24 Aug 16 04:54:10 PM PDT 24 4916904167 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1053086430 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:12 PM PDT 24 12361676868 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2964659851 Aug 16 04:53:58 PM PDT 24 Aug 16 04:54:11 PM PDT 24 176384122 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3302387593 Aug 16 04:53:49 PM PDT 24 Aug 16 04:55:13 PM PDT 24 3835910034 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.343386068 Aug 16 04:53:55 PM PDT 24 Aug 16 04:54:49 PM PDT 24 6068822079 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.379436426 Aug 16 04:53:52 PM PDT 24 Aug 16 04:54:05 PM PDT 24 986709404 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.842340855 Aug 16 04:54:07 PM PDT 24 Aug 16 04:54:50 PM PDT 24 4413827728 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2637964568 Aug 16 04:54:01 PM PDT 24 Aug 16 04:54:14 PM PDT 24 2116855826 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3089117789 Aug 16 04:53:51 PM PDT 24 Aug 16 04:54:05 PM PDT 24 1024046465 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1515210454 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:01 PM PDT 24 1032958541 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.875350442 Aug 16 04:54:02 PM PDT 24 Aug 16 04:54:13 PM PDT 24 510712362 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3719907733 Aug 16 04:53:46 PM PDT 24 Aug 16 04:54:01 PM PDT 24 1234735284 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3334483244 Aug 16 04:54:06 PM PDT 24 Aug 16 04:55:29 PM PDT 24 426926609 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2284556088 Aug 16 04:53:58 PM PDT 24 Aug 16 04:56:30 PM PDT 24 383966099 ps
T89 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2214905963 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:05 PM PDT 24 2746363698 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1521455546 Aug 16 04:53:52 PM PDT 24 Aug 16 04:55:14 PM PDT 24 1230986360 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.712128698 Aug 16 04:53:57 PM PDT 24 Aug 16 04:54:11 PM PDT 24 3962860370 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.437948924 Aug 16 04:53:53 PM PDT 24 Aug 16 04:54:03 PM PDT 24 250217346 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1655349546 Aug 16 04:54:00 PM PDT 24 Aug 16 04:54:09 PM PDT 24 730037765 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1624205785 Aug 16 04:53:59 PM PDT 24 Aug 16 04:54:12 PM PDT 24 1573611829 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3560364489 Aug 16 04:53:51 PM PDT 24 Aug 16 04:53:59 PM PDT 24 1105147836 ps

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1876219877
Short name T10
Test name
Test status
Simulation time 1555326948 ps
CPU time 78.48 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 233312 kb
Host smart-80d71c7a-9029-4ae0-a17b-a17a64adb380
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876219877 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1876219877
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2422625454
Short name T19
Test name
Test status
Simulation time 12318870070 ps
CPU time 316.29 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:59:59 PM PDT 24
Peak memory 240408 kb
Host smart-5d838d64-3207-472a-871e-1d771e792ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422625454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2422625454
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4135286603
Short name T2
Test name
Test status
Simulation time 8772876671 ps
CPU time 38.71 seconds
Started Aug 16 04:54:14 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 219604 kb
Host smart-d41730e7-5c92-485b-aaa0-ee26e9e093ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135286603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4135286603
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2476795352
Short name T59
Test name
Test status
Simulation time 328637363 ps
CPU time 150.2 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:56:21 PM PDT 24
Peak memory 214812 kb
Host smart-5f3bb83b-f14b-43f4-a820-424d85aed3c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476795352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2476795352
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1241565738
Short name T13
Test name
Test status
Simulation time 12945270769 ps
CPU time 121.72 seconds
Started Aug 16 04:54:13 PM PDT 24
Finished Aug 16 04:56:15 PM PDT 24
Peak memory 228888 kb
Host smart-78d8e012-88b7-4976-a2de-2564e864c127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241565738 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1241565738
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1902838516
Short name T26
Test name
Test status
Simulation time 2063709025 ps
CPU time 228 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:57:47 PM PDT 24
Peak memory 238748 kb
Host smart-58e25a21-93ab-418f-930f-3c1f161e5ebb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902838516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1902838516
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3846911184
Short name T66
Test name
Test status
Simulation time 245249037 ps
CPU time 8.03 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:56 PM PDT 24
Peak memory 211804 kb
Host smart-ffe21872-4ac2-4056-b7dc-472ecac5af1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846911184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3846911184
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1781040692
Short name T7
Test name
Test status
Simulation time 4095537221 ps
CPU time 13.36 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:01 PM PDT 24
Peak memory 218264 kb
Host smart-5635a0d1-1dec-4289-a47f-a1361c1120a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781040692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1781040692
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.908073929
Short name T57
Test name
Test status
Simulation time 1480194889 ps
CPU time 151.19 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:56:28 PM PDT 24
Peak memory 219576 kb
Host smart-f66587f9-b5d3-4284-a487-63a8a719dd1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908073929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.908073929
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2031220334
Short name T24
Test name
Test status
Simulation time 2712977325 ps
CPU time 93.84 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:55:33 PM PDT 24
Peak memory 223856 kb
Host smart-815ad904-c3ae-450a-bc68-069d2398c777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031220334 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2031220334
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.764544929
Short name T9
Test name
Test status
Simulation time 357232637 ps
CPU time 18.65 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:19 PM PDT 24
Peak memory 218480 kb
Host smart-4aae189a-3370-4639-ada3-39bf73b30016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764544929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.764544929
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1112646282
Short name T51
Test name
Test status
Simulation time 1326037991 ps
CPU time 17.43 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 218856 kb
Host smart-16b70347-424c-42fc-8621-5b0099a5ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112646282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1112646282
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3695264917
Short name T137
Test name
Test status
Simulation time 528705064 ps
CPU time 21.5 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 218564 kb
Host smart-a43067f4-50ef-4f8f-b104-e739eb294275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695264917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3695264917
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2892311728
Short name T103
Test name
Test status
Simulation time 469660547 ps
CPU time 158.64 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:56:36 PM PDT 24
Peak memory 215660 kb
Host smart-8670789e-c444-4ad6-99c3-2d16a7aee9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892311728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2892311728
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1685865517
Short name T152
Test name
Test status
Simulation time 20448431079 ps
CPU time 273 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:59:02 PM PDT 24
Peak memory 237656 kb
Host smart-cc8e70be-5ee0-4ff9-8baa-82b719b3f71c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685865517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1685865517
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3818410958
Short name T88
Test name
Test status
Simulation time 4479814391 ps
CPU time 62.63 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 215552 kb
Host smart-8f8d8095-a54a-4d1a-a6d0-1b2e07a427d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818410958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3818410958
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.617762397
Short name T106
Test name
Test status
Simulation time 2065353467 ps
CPU time 152.02 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:56:32 PM PDT 24
Peak memory 213772 kb
Host smart-27b13d89-a620-404a-9d3e-6a02c2236a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617762397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.617762397
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.297844791
Short name T97
Test name
Test status
Simulation time 412674261 ps
CPU time 11.26 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:40 PM PDT 24
Peak memory 218504 kb
Host smart-667b7892-4d49-44b0-a0f7-91f77c56bfd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297844791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.297844791
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1592596076
Short name T22
Test name
Test status
Simulation time 4932072468 ps
CPU time 211.33 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:58:14 PM PDT 24
Peak memory 225860 kb
Host smart-1e71fd45-3b19-4d9a-8857-8d3690dff1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592596076 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1592596076
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1290580726
Short name T61
Test name
Test status
Simulation time 986573661 ps
CPU time 9.2 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:00 PM PDT 24
Peak memory 211740 kb
Host smart-d094bf85-574d-41a0-a084-574b1549749b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290580726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1290580726
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1184746462
Short name T400
Test name
Test status
Simulation time 340763789 ps
CPU time 8.34 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 211528 kb
Host smart-d183eef6-c403-4dc7-8259-5ac24a893919
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184746462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1184746462
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3105876627
Short name T389
Test name
Test status
Simulation time 270522115 ps
CPU time 16.87 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:17 PM PDT 24
Peak memory 212552 kb
Host smart-39e44653-6bb7-4969-8f33-e7b61c760db4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105876627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3105876627
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.930737921
Short name T361
Test name
Test status
Simulation time 1502289335 ps
CPU time 10.71 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 217804 kb
Host smart-767c8383-69ee-4203-9541-a9ba6d2e46f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930737921 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.930737921
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1278862597
Short name T365
Test name
Test status
Simulation time 825472844 ps
CPU time 7.93 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 211932 kb
Host smart-c6f9749b-5166-4110-b3da-b1a8abafde06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278862597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1278862597
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.94146178
Short name T357
Test name
Test status
Simulation time 495063313 ps
CPU time 9.18 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:57 PM PDT 24
Peak memory 211340 kb
Host smart-528f7621-f8c4-49dc-b876-f3a150989ecc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94146178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_
mem_partial_access.94146178
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2057744450
Short name T425
Test name
Test status
Simulation time 353113564 ps
CPU time 7.83 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 211296 kb
Host smart-93781b65-6da4-4c49-bd23-cc9bcea66242
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057744450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2057744450
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.144316900
Short name T91
Test name
Test status
Simulation time 174336510 ps
CPU time 7.85 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:53:57 PM PDT 24
Peak memory 211652 kb
Host smart-dd8cf49c-81f9-4e47-9030-e9fa237b8a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144316900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.144316900
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.775036944
Short name T358
Test name
Test status
Simulation time 260267907 ps
CPU time 14.55 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 218248 kb
Host smart-135e74c4-f088-4347-babc-cf17f5e7390e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775036944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.775036944
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3302387593
Short name T104
Test name
Test status
Simulation time 3835910034 ps
CPU time 83.86 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:55:13 PM PDT 24
Peak memory 214672 kb
Host smart-fbf26b1a-d84e-4613-8567-0db1cb5b47a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302387593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3302387593
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2003309768
Short name T70
Test name
Test status
Simulation time 331828379 ps
CPU time 8.05 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 211444 kb
Host smart-e43ad9c1-4be6-4e9e-865c-c3eaa839b600
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003309768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2003309768
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2399302492
Short name T433
Test name
Test status
Simulation time 372554160 ps
CPU time 9.75 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:02 PM PDT 24
Peak memory 211440 kb
Host smart-1632ca4e-4cda-4be0-a006-84166ca67e41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399302492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2399302492
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.634702800
Short name T95
Test name
Test status
Simulation time 1116850169 ps
CPU time 15.26 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 212796 kb
Host smart-0a2f1681-5e80-4800-b6d2-77e8760fa74e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634702800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.634702800
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.712128698
Short name T451
Test name
Test status
Simulation time 3962860370 ps
CPU time 13.72 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 217772 kb
Host smart-46cb8d2a-ed70-463e-92fe-d513077af2b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712128698 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.712128698
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.298078234
Short name T81
Test name
Test status
Simulation time 347750712 ps
CPU time 8.02 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 211408 kb
Host smart-844436e8-953e-4982-9724-a58cedf83c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298078234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.298078234
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3089117789
Short name T446
Test name
Test status
Simulation time 1024046465 ps
CPU time 13.42 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 211280 kb
Host smart-5b64a416-128f-4179-97e2-f954d58c20cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089117789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3089117789
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2659627319
Short name T402
Test name
Test status
Simulation time 517796982 ps
CPU time 9.26 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 211344 kb
Host smart-8e9870c4-7fd9-470e-a235-b9387feb2bcc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659627319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2659627319
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.356250507
Short name T399
Test name
Test status
Simulation time 1359741559 ps
CPU time 36.11 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 213368 kb
Host smart-37a7eb18-5808-4cd5-bd81-c18c034f9f82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356250507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.356250507
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.925003318
Short name T387
Test name
Test status
Simulation time 1378157914 ps
CPU time 9.83 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:54:00 PM PDT 24
Peak memory 211992 kb
Host smart-4fc7cd27-bf53-4aa9-9019-f5d13c22f281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925003318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.925003318
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2995782938
Short name T382
Test name
Test status
Simulation time 250337043 ps
CPU time 13.9 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 218424 kb
Host smart-75c3d22a-dec5-47f3-a2d1-e96dbbefdd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995782938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2995782938
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2242579426
Short name T392
Test name
Test status
Simulation time 1573694974 ps
CPU time 154.56 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:56:32 PM PDT 24
Peak memory 214740 kb
Host smart-0a58adc6-2f1f-4bdf-88b4-96db33c655bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242579426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2242579426
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1053086430
Short name T440
Test name
Test status
Simulation time 12361676868 ps
CPU time 13.49 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 219764 kb
Host smart-447d1e56-66e0-4add-a299-1bc98c9588a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053086430 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1053086430
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3933761321
Short name T422
Test name
Test status
Simulation time 772591028 ps
CPU time 9.83 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 211440 kb
Host smart-131eef00-d88a-411e-85db-cb2c092fe918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933761321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3933761321
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4140218700
Short name T423
Test name
Test status
Simulation time 2142849725 ps
CPU time 54.15 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 214656 kb
Host smart-85e19b8f-5f59-4ffe-bc8e-871c13da319d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140218700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4140218700
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1960902196
Short name T393
Test name
Test status
Simulation time 504484512 ps
CPU time 9.33 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 211908 kb
Host smart-d88c3975-9482-4a9b-8568-cffad31ad15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960902196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1960902196
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.752474692
Short name T354
Test name
Test status
Simulation time 1032256532 ps
CPU time 12.84 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 218136 kb
Host smart-420676a1-894f-42c5-8d17-8fe380e3df6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752474692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.752474692
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2541072967
Short name T110
Test name
Test status
Simulation time 308534840 ps
CPU time 77.71 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:55:12 PM PDT 24
Peak memory 219552 kb
Host smart-b57ade86-9276-468a-b015-56d982eaee51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541072967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2541072967
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2654492244
Short name T369
Test name
Test status
Simulation time 1355442030 ps
CPU time 10.04 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 217532 kb
Host smart-95f964a2-0202-4af4-ba1d-fee141c5a652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654492244 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2654492244
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2713493092
Short name T67
Test name
Test status
Simulation time 4095621462 ps
CPU time 13.41 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 212968 kb
Host smart-5a860d23-2708-49be-ac2c-3cf834495454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713493092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2713493092
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.517959163
Short name T410
Test name
Test status
Simulation time 6197714311 ps
CPU time 34.72 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:28 PM PDT 24
Peak memory 214588 kb
Host smart-fcfff83b-f0ae-431b-b42f-adc7b8079b08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517959163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.517959163
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.55585465
Short name T69
Test name
Test status
Simulation time 1833293030 ps
CPU time 7.87 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 212088 kb
Host smart-807d871b-66d8-4b84-80cb-c71b51062f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55585465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ct
rl_same_csr_outstanding.55585465
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.872977523
Short name T430
Test name
Test status
Simulation time 497330846 ps
CPU time 12.03 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 217952 kb
Host smart-560919a1-1bd2-4110-941f-fc65ec9d4883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872977523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.872977523
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3458900421
Short name T102
Test name
Test status
Simulation time 461794054 ps
CPU time 153.96 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:56:32 PM PDT 24
Peak memory 214940 kb
Host smart-7dff5d3b-d74b-4f29-a6d8-f890c40915be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458900421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3458900421
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2279292228
Short name T375
Test name
Test status
Simulation time 174156506 ps
CPU time 8.63 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 216448 kb
Host smart-4ca3c445-c6ec-4021-9b5c-4aee30eff6ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279292228 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2279292228
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4104878452
Short name T417
Test name
Test status
Simulation time 172735736 ps
CPU time 7.71 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 211532 kb
Host smart-8eadbf36-36f3-448c-a553-01b0fd7b9f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104878452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4104878452
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.214939613
Short name T94
Test name
Test status
Simulation time 1610064996 ps
CPU time 63 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 214476 kb
Host smart-ac672f42-3070-4c53-a7fc-fd304929dc53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214939613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.214939613
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.863762970
Short name T403
Test name
Test status
Simulation time 383025992 ps
CPU time 11.72 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 213160 kb
Host smart-54b91466-c0dc-4dfa-8976-a9a978abbee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863762970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.863762970
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3482353147
Short name T359
Test name
Test status
Simulation time 260468239 ps
CPU time 12.92 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 217924 kb
Host smart-e122705a-4b58-438f-a81f-9d8f691bd55d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482353147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3482353147
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.413043156
Short name T385
Test name
Test status
Simulation time 4139516384 ps
CPU time 13.73 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 219708 kb
Host smart-ae03a452-8cf4-4407-8fb1-605b11a97657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413043156 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.413043156
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2214905963
Short name T89
Test name
Test status
Simulation time 2746363698 ps
CPU time 7.6 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 211620 kb
Host smart-8dadc1da-ea53-443c-a2af-34eca82bebb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214905963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2214905963
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.842340855
Short name T444
Test name
Test status
Simulation time 4413827728 ps
CPU time 42.44 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 214676 kb
Host smart-c1b116f2-20ee-4903-857b-0a1db2ada93a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842340855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.842340855
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.33942399
Short name T416
Test name
Test status
Simulation time 1967294110 ps
CPU time 13.26 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 213148 kb
Host smart-1b88a92a-60c0-423e-9dc1-1628e07ac3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.33942399
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2964659851
Short name T441
Test name
Test status
Simulation time 176384122 ps
CPU time 12.05 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 219180 kb
Host smart-c0c0ea18-585f-467d-b067-0470eb127fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964659851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2964659851
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4177331813
Short name T408
Test name
Test status
Simulation time 1547215906 ps
CPU time 153.17 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:56:31 PM PDT 24
Peak memory 215528 kb
Host smart-6f73322d-e3e8-4458-a531-5ab711a89d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177331813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4177331813
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1332871470
Short name T370
Test name
Test status
Simulation time 19697639915 ps
CPU time 14.12 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 218000 kb
Host smart-2cf8da00-96a4-4950-ad69-f75504594b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332871470 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1332871470
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1283121905
Short name T414
Test name
Test status
Simulation time 1304561304 ps
CPU time 9.34 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 211792 kb
Host smart-608b0d0a-ea99-4f8e-a61b-5635bd1cd440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283121905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1283121905
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3575483047
Short name T407
Test name
Test status
Simulation time 1970549859 ps
CPU time 35.12 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:35 PM PDT 24
Peak memory 213520 kb
Host smart-637d7cfa-23c1-4e98-9473-34abb95ddb7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575483047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3575483047
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3942731683
Short name T429
Test name
Test status
Simulation time 497997208 ps
CPU time 9.12 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 212128 kb
Host smart-b2d551fb-7285-41e7-a96d-286ff8dc6f4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942731683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3942731683
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1925545290
Short name T401
Test name
Test status
Simulation time 569599401 ps
CPU time 13.58 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 218304 kb
Host smart-5ce6e63b-009f-4481-af42-f54879592e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925545290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1925545290
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2906019855
Short name T432
Test name
Test status
Simulation time 1065989461 ps
CPU time 9.58 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 217080 kb
Host smart-c9f7a1cd-5f1c-449c-b3c2-df51df374d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906019855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2906019855
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1744481466
Short name T396
Test name
Test status
Simulation time 1184416736 ps
CPU time 7.81 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 212052 kb
Host smart-47cbd9de-c6cb-4025-8b60-71800c853670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744481466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1744481466
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2801411814
Short name T394
Test name
Test status
Simulation time 3094195277 ps
CPU time 63.2 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:59 PM PDT 24
Peak memory 215880 kb
Host smart-baa5c71f-0717-401a-b38e-b353fb9b758b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801411814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2801411814
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3746442160
Short name T383
Test name
Test status
Simulation time 261457601 ps
CPU time 12.9 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:19 PM PDT 24
Peak memory 213192 kb
Host smart-64d2824c-d0c6-4ea8-8be2-4e415a75a0d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746442160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3746442160
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2291370635
Short name T381
Test name
Test status
Simulation time 250583637 ps
CPU time 14.23 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 218240 kb
Host smart-04d12902-9f8a-4c97-85aa-4215eedb1485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291370635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2291370635
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.875350442
Short name T448
Test name
Test status
Simulation time 510712362 ps
CPU time 10.48 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 219636 kb
Host smart-494268e7-874d-4ce7-9ad4-d2225800d8da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875350442 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.875350442
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.620289071
Short name T92
Test name
Test status
Simulation time 1499066101 ps
CPU time 7.83 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:08 PM PDT 24
Peak memory 211788 kb
Host smart-08ab91b9-be9f-4223-80ac-2b8aac40277e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620289071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.620289071
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.908529430
Short name T427
Test name
Test status
Simulation time 2993355849 ps
CPU time 36.21 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:41 PM PDT 24
Peak memory 214560 kb
Host smart-2c8e28fb-0615-4251-91ca-da20503bc074
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908529430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.908529430
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2744239857
Short name T93
Test name
Test status
Simulation time 1976628310 ps
CPU time 13.22 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:15 PM PDT 24
Peak memory 211996 kb
Host smart-4a109541-5014-4c06-ba85-f2c867152eea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744239857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2744239857
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3336988457
Short name T363
Test name
Test status
Simulation time 635712334 ps
CPU time 11.38 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 218136 kb
Host smart-1e5f2e82-1059-4fe1-8cff-de967d47700e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336988457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3336988457
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2769759496
Short name T108
Test name
Test status
Simulation time 907615409 ps
CPU time 80.94 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:55:21 PM PDT 24
Peak memory 213348 kb
Host smart-87c72cc4-190c-4e4c-9811-2fa2fb6f588a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769759496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2769759496
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3634685592
Short name T371
Test name
Test status
Simulation time 2231871219 ps
CPU time 9.5 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 219768 kb
Host smart-174de624-dfa7-40ac-9545-8d0d094b887e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634685592 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3634685592
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3547253808
Short name T87
Test name
Test status
Simulation time 661544428 ps
CPU time 8.03 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 211992 kb
Host smart-75e57fb3-ca34-47dd-b4a6-e5b1daf71194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547253808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3547253808
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2485079486
Short name T83
Test name
Test status
Simulation time 1038669205 ps
CPU time 54.54 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:56 PM PDT 24
Peak memory 214588 kb
Host smart-36abc9e1-c30c-42b3-9dbd-a91c43ef58d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485079486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2485079486
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2637964568
Short name T445
Test name
Test status
Simulation time 2116855826 ps
CPU time 13.12 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:14 PM PDT 24
Peak memory 213456 kb
Host smart-5d69d0d1-55e5-4fda-9332-492dcc05e543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637964568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2637964568
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4110726188
Short name T360
Test name
Test status
Simulation time 549586679 ps
CPU time 11.84 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 217508 kb
Host smart-b6738518-1cad-4f19-a54b-1fba9c393653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110726188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4110726188
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.210284913
Short name T398
Test name
Test status
Simulation time 475922551 ps
CPU time 79.73 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:55:23 PM PDT 24
Peak memory 214516 kb
Host smart-0a6dcc8f-e908-40d6-9e42-8d489c57cbda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210284913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.210284913
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1882836009
Short name T395
Test name
Test status
Simulation time 353516121 ps
CPU time 8.51 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 219616 kb
Host smart-b4691d11-d967-43e1-87d5-2e1aa48363fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882836009 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1882836009
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2152338139
Short name T82
Test name
Test status
Simulation time 259496641 ps
CPU time 8.65 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:16 PM PDT 24
Peak memory 211284 kb
Host smart-4a9372a8-4922-4b46-8971-fcdb54904ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152338139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2152338139
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2705777596
Short name T420
Test name
Test status
Simulation time 2849559522 ps
CPU time 35.77 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:37 PM PDT 24
Peak memory 214592 kb
Host smart-9d00f6fe-0c5f-4da2-9891-a9957fceb652
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705777596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2705777596
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2414361377
Short name T72
Test name
Test status
Simulation time 1991964294 ps
CPU time 12.8 seconds
Started Aug 16 04:54:13 PM PDT 24
Finished Aug 16 04:54:26 PM PDT 24
Peak memory 212964 kb
Host smart-889fd6eb-6a1d-4f6d-9a35-3f19b94c1217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414361377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2414361377
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1542529909
Short name T384
Test name
Test status
Simulation time 615164121 ps
CPU time 11.25 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:17 PM PDT 24
Peak memory 217864 kb
Host smart-6de75382-cb0a-48be-b22c-a9bf9555e557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542529909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1542529909
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2284556088
Short name T107
Test name
Test status
Simulation time 383966099 ps
CPU time 151.14 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:56:30 PM PDT 24
Peak memory 215760 kb
Host smart-07145999-f540-4c4e-9ef8-993027c17844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284556088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2284556088
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.615414262
Short name T364
Test name
Test status
Simulation time 1078679613 ps
CPU time 8.28 seconds
Started Aug 16 04:54:09 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 216552 kb
Host smart-a7755ca0-a74e-4535-946f-d53b378a46fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615414262 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.615414262
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1934918066
Short name T378
Test name
Test status
Simulation time 173080209 ps
CPU time 7.94 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 211608 kb
Host smart-3e9f87f1-608b-46e7-9e39-8237a4136917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934918066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1934918066
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2332996509
Short name T90
Test name
Test status
Simulation time 6830863675 ps
CPU time 36.15 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:39 PM PDT 24
Peak memory 215764 kb
Host smart-d209b2f0-96a6-4cf1-9d3b-b4fe9af1a282
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332996509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2332996509
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1624205785
Short name T454
Test name
Test status
Simulation time 1573611829 ps
CPU time 12.79 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 213100 kb
Host smart-c3b6a1cd-9080-4fe9-9ddd-3d04c575fbe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624205785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1624205785
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1932343495
Short name T377
Test name
Test status
Simulation time 1545214252 ps
CPU time 14.98 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:16 PM PDT 24
Peak memory 218332 kb
Host smart-d9a96a67-9d38-4ca4-b98b-dfceb640ed7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932343495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1932343495
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3096157145
Short name T105
Test name
Test status
Simulation time 1139101547 ps
CPU time 82.17 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:55:26 PM PDT 24
Peak memory 214096 kb
Host smart-b3fb2822-eac5-4ff1-b7bd-8ea23d8361aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096157145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3096157145
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.205901327
Short name T390
Test name
Test status
Simulation time 634959609 ps
CPU time 7.69 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:53:57 PM PDT 24
Peak memory 211424 kb
Host smart-c42ab419-d5e7-49d9-a585-14dabf97a96c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205901327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.205901327
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.895984090
Short name T355
Test name
Test status
Simulation time 260148998 ps
CPU time 9.78 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 211800 kb
Host smart-c296dc81-8c71-4e91-9062-f2e50ed532bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895984090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.895984090
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3706909387
Short name T406
Test name
Test status
Simulation time 333954731 ps
CPU time 13.38 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 212372 kb
Host smart-99925325-36ef-44ef-a6bc-f749fa402c56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706909387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3706909387
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3331576866
Short name T367
Test name
Test status
Simulation time 494438714 ps
CPU time 10.48 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 218064 kb
Host smart-21158ccb-4887-4bb4-a3b1-ec17263a5339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331576866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3331576866
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.379436426
Short name T443
Test name
Test status
Simulation time 986709404 ps
CPU time 13.34 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 211356 kb
Host smart-fcd64a9a-437b-4344-abac-1147849ae710
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379436426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.379436426
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1017090339
Short name T362
Test name
Test status
Simulation time 260781684 ps
CPU time 9.09 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 211292 kb
Host smart-407f63a5-a592-4c5b-ad79-b5f3d637ccee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017090339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1017090339
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1257649646
Short name T84
Test name
Test status
Simulation time 4024783663 ps
CPU time 36.88 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:30 PM PDT 24
Peak memory 214940 kb
Host smart-0cc07b4e-ab81-4218-9477-2c49b8e0d95f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257649646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1257649646
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2371310938
Short name T391
Test name
Test status
Simulation time 1028419346 ps
CPU time 9.29 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 211972 kb
Host smart-fe16d015-ff94-4f22-bd59-505805116628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371310938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2371310938
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2069502649
Short name T426
Test name
Test status
Simulation time 254459015 ps
CPU time 14.89 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 218448 kb
Host smart-2d1c9c52-26fb-41a7-a567-48eeb7d54dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069502649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2069502649
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3202404405
Short name T101
Test name
Test status
Simulation time 900842198 ps
CPU time 155.5 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:56:24 PM PDT 24
Peak memory 216128 kb
Host smart-2188ba50-8190-4639-b445-edf15ba19dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202404405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3202404405
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1255785425
Short name T428
Test name
Test status
Simulation time 259426109 ps
CPU time 9.34 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 211364 kb
Host smart-babfb180-4450-4bc5-80da-3f5da2b7139f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255785425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1255785425
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3529307300
Short name T437
Test name
Test status
Simulation time 172513222 ps
CPU time 7.97 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 211336 kb
Host smart-b93c702b-cd0a-426f-8fea-fd8a73bf009c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529307300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3529307300
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2792016138
Short name T372
Test name
Test status
Simulation time 2024263086 ps
CPU time 16.34 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 212460 kb
Host smart-0e402c84-0e66-450e-868e-6bca0f1e9129
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792016138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2792016138
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4215921109
Short name T356
Test name
Test status
Simulation time 1461812794 ps
CPU time 13.69 seconds
Started Aug 16 04:53:54 PM PDT 24
Finished Aug 16 04:54:08 PM PDT 24
Peak memory 219576 kb
Host smart-5c922aa5-c729-4652-805b-5c9d15ec6992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215921109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4215921109
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2637629844
Short name T68
Test name
Test status
Simulation time 1029134695 ps
CPU time 9.25 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:02 PM PDT 24
Peak memory 211340 kb
Host smart-10dd5493-9e22-4c37-b858-c7b2e85798f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637629844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2637629844
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2766888917
Short name T374
Test name
Test status
Simulation time 664973042 ps
CPU time 7.83 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 211380 kb
Host smart-3110687a-7196-4827-81da-3201b9650f1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766888917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2766888917
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2404335318
Short name T386
Test name
Test status
Simulation time 362461951 ps
CPU time 8.2 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:53:58 PM PDT 24
Peak memory 211316 kb
Host smart-15610fbb-118f-4871-865b-f73d56245aee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404335318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2404335318
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1458019018
Short name T86
Test name
Test status
Simulation time 1378686008 ps
CPU time 36.03 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:54:25 PM PDT 24
Peak memory 214588 kb
Host smart-26037ec9-1ae2-442f-b565-6e2a18826424
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458019018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1458019018
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3435651301
Short name T71
Test name
Test status
Simulation time 249457753 ps
CPU time 10.06 seconds
Started Aug 16 04:53:47 PM PDT 24
Finished Aug 16 04:53:57 PM PDT 24
Peak memory 212068 kb
Host smart-66c8bd85-8ac8-4b75-83ce-c112be6d1d06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435651301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3435651301
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2292620552
Short name T413
Test name
Test status
Simulation time 786352724 ps
CPU time 12.74 seconds
Started Aug 16 04:53:49 PM PDT 24
Finished Aug 16 04:54:02 PM PDT 24
Peak memory 218132 kb
Host smart-9b57d119-5809-4f00-b6a6-4a903e1bbfb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292620552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2292620552
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1521455546
Short name T450
Test name
Test status
Simulation time 1230986360 ps
CPU time 81.85 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:55:14 PM PDT 24
Peak memory 214116 kb
Host smart-4d14668f-13b6-4187-a501-5f17a4c92a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521455546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1521455546
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.437948924
Short name T452
Test name
Test status
Simulation time 250217346 ps
CPU time 9.78 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 211416 kb
Host smart-b6133176-d30e-4346-83e4-fe5b0626c9a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437948924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.437948924
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2778868160
Short name T418
Test name
Test status
Simulation time 751813620 ps
CPU time 8.31 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 211384 kb
Host smart-b18b498f-5513-4c65-8b93-9a324e3e8606
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778868160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2778868160
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1611762187
Short name T404
Test name
Test status
Simulation time 1002153789 ps
CPU time 16.54 seconds
Started Aug 16 04:53:46 PM PDT 24
Finished Aug 16 04:54:02 PM PDT 24
Peak memory 212804 kb
Host smart-b8e5cfed-1bea-42f2-a478-8bdbf4e04334
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611762187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1611762187
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4186001153
Short name T379
Test name
Test status
Simulation time 659752348 ps
CPU time 10.57 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 219636 kb
Host smart-4cc49ce2-28bc-468e-8638-a3be593e9c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186001153 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4186001153
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2411176043
Short name T388
Test name
Test status
Simulation time 260792290 ps
CPU time 9.29 seconds
Started Aug 16 04:53:48 PM PDT 24
Finished Aug 16 04:53:58 PM PDT 24
Peak memory 211472 kb
Host smart-e1b4b85e-5463-4831-bbdf-94650c72de82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411176043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2411176043
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3560364489
Short name T455
Test name
Test status
Simulation time 1105147836 ps
CPU time 7.76 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:53:59 PM PDT 24
Peak memory 211348 kb
Host smart-edcbd9dc-70a6-4a03-bb00-1b392f55761f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560364489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3560364489
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1515210454
Short name T447
Test name
Test status
Simulation time 1032958541 ps
CPU time 7.68 seconds
Started Aug 16 04:53:53 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 211316 kb
Host smart-fc3dda97-a8d0-4d75-9e39-eb29d7ced521
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515210454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1515210454
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2162558778
Short name T79
Test name
Test status
Simulation time 4479097660 ps
CPU time 54.16 seconds
Started Aug 16 04:53:51 PM PDT 24
Finished Aug 16 04:54:45 PM PDT 24
Peak memory 216640 kb
Host smart-5de6b48e-225e-4937-b59c-ed7a761a69f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162558778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2162558778
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.199412160
Short name T415
Test name
Test status
Simulation time 340290466 ps
CPU time 8.04 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:08 PM PDT 24
Peak memory 211972 kb
Host smart-61bd3e2b-c7f2-4f24-b200-d39c308cf11c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199412160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.199412160
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3719907733
Short name T449
Test name
Test status
Simulation time 1234735284 ps
CPU time 15.39 seconds
Started Aug 16 04:53:46 PM PDT 24
Finished Aug 16 04:54:01 PM PDT 24
Peak memory 218352 kb
Host smart-4e13dc9d-85bf-44d6-aace-85c3ac6d6acc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719907733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3719907733
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3673455852
Short name T405
Test name
Test status
Simulation time 1321927997 ps
CPU time 9.83 seconds
Started Aug 16 04:53:50 PM PDT 24
Finished Aug 16 04:54:00 PM PDT 24
Peak memory 217736 kb
Host smart-fd2aeb3f-9852-46c8-b8bd-857ba8f79f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673455852 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3673455852
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.493928288
Short name T431
Test name
Test status
Simulation time 1839590582 ps
CPU time 7.76 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:08 PM PDT 24
Peak memory 212008 kb
Host smart-4fe7761f-1b97-4c90-adb9-d83b19c7f927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493928288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.493928288
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2097004392
Short name T96
Test name
Test status
Simulation time 1022865499 ps
CPU time 42.17 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:38 PM PDT 24
Peak memory 214436 kb
Host smart-3720aa4b-d2ec-492c-9334-5d8b66390ce8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097004392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2097004392
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4163219234
Short name T376
Test name
Test status
Simulation time 174169349 ps
CPU time 7.83 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:05 PM PDT 24
Peak memory 211872 kb
Host smart-0743bf53-3616-4db6-9ae6-7cb065eb4586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163219234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4163219234
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2048090616
Short name T439
Test name
Test status
Simulation time 4916904167 ps
CPU time 14.23 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 218860 kb
Host smart-7c9676b8-9619-41f2-bcec-7181326ee46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048090616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2048090616
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4183441141
Short name T109
Test name
Test status
Simulation time 315092988 ps
CPU time 151.31 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:56:29 PM PDT 24
Peak memory 214572 kb
Host smart-40ae3c77-28e4-4f03-a330-d056ed6a65ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183441141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4183441141
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3844412052
Short name T412
Test name
Test status
Simulation time 1033086156 ps
CPU time 9.5 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 214096 kb
Host smart-a3692013-5f28-48f3-b1eb-0501d0eccb07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844412052 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3844412052
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3132226732
Short name T373
Test name
Test status
Simulation time 289052365 ps
CPU time 9.07 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 211500 kb
Host smart-1ae57d21-3f0b-49b5-b1b5-516db965517a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132226732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3132226732
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1677054522
Short name T424
Test name
Test status
Simulation time 49298542528 ps
CPU time 56.32 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:51 PM PDT 24
Peak memory 214592 kb
Host smart-48aafddc-7f6d-4aa4-a04f-c0a49aeb2445
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677054522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1677054522
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2441981923
Short name T380
Test name
Test status
Simulation time 984071681 ps
CPU time 13.66 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 213328 kb
Host smart-3682561c-6e4f-4358-996f-507650b86b3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441981923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2441981923
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2431028243
Short name T419
Test name
Test status
Simulation time 172762131 ps
CPU time 11.62 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 218192 kb
Host smart-7d812375-da3c-415b-8828-456167531443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431028243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2431028243
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1393448675
Short name T111
Test name
Test status
Simulation time 2155855697 ps
CPU time 82.38 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:55:21 PM PDT 24
Peak memory 214588 kb
Host smart-3f3d7d64-2462-4374-ac0c-e1e09d8a218a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393448675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1393448675
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1655349546
Short name T453
Test name
Test status
Simulation time 730037765 ps
CPU time 8.45 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 219636 kb
Host smart-8e508ff2-86aa-4915-be42-3073a9833da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655349546 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1655349546
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4249184301
Short name T85
Test name
Test status
Simulation time 689269706 ps
CPU time 8.07 seconds
Started Aug 16 04:53:54 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 211996 kb
Host smart-070cc280-4f8b-4876-95d5-67947861e756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249184301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4249184301
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2079008541
Short name T80
Test name
Test status
Simulation time 1596258930 ps
CPU time 62.77 seconds
Started Aug 16 04:53:52 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 215584 kb
Host smart-52920a0a-4c92-494d-8c23-19e752238b45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079008541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2079008541
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3812927521
Short name T434
Test name
Test status
Simulation time 1037769120 ps
CPU time 9.63 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 212052 kb
Host smart-49565fa2-2d01-4ceb-bc94-4eb5f53027d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812927521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3812927521
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3241650709
Short name T366
Test name
Test status
Simulation time 518668959 ps
CPU time 11.41 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 218512 kb
Host smart-1da7c007-92c3-48cc-af90-2f0a0e6ea068
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241650709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3241650709
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1963564458
Short name T411
Test name
Test status
Simulation time 380352111 ps
CPU time 151.9 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:56:30 PM PDT 24
Peak memory 215676 kb
Host smart-861945ca-3123-478f-9c50-af9015d90957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963564458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1963564458
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1585983941
Short name T409
Test name
Test status
Simulation time 387042279 ps
CPU time 8.06 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:54:07 PM PDT 24
Peak memory 219636 kb
Host smart-311fbc6b-0253-4f89-9c5d-c6ecc68cc26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585983941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1585983941
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2356291320
Short name T60
Test name
Test status
Simulation time 688074674 ps
CPU time 7.93 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 212000 kb
Host smart-e0c4ceaf-a745-411d-a2da-1e925c459c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356291320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2356291320
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2595178376
Short name T368
Test name
Test status
Simulation time 6413333266 ps
CPU time 54.49 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:55:01 PM PDT 24
Peak memory 216584 kb
Host smart-a302e909-0248-4c01-a75f-163c6e71148b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595178376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2595178376
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.862160729
Short name T421
Test name
Test status
Simulation time 1077998843 ps
CPU time 9.63 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 212056 kb
Host smart-a17ece88-8938-44b6-986e-ff214e3b9251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862160729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.862160729
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2001352722
Short name T438
Test name
Test status
Simulation time 257350938 ps
CPU time 14.08 seconds
Started Aug 16 04:53:56 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 218196 kb
Host smart-5cb71cf0-abb3-4345-a8ec-ceb4617a8050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001352722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2001352722
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3039777999
Short name T58
Test name
Test status
Simulation time 346661870 ps
CPU time 82.47 seconds
Started Aug 16 04:53:54 PM PDT 24
Finished Aug 16 04:55:17 PM PDT 24
Peak memory 219576 kb
Host smart-2e36fb7f-ced5-4b34-8a8d-44cabf9084bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039777999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3039777999
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.380131800
Short name T435
Test name
Test status
Simulation time 379517824 ps
CPU time 8.99 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:04 PM PDT 24
Peak memory 217860 kb
Host smart-af696e87-3a60-431c-a4a8-409f72e62935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380131800 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.380131800
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3115117844
Short name T62
Test name
Test status
Simulation time 167435945 ps
CPU time 7.67 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 211320 kb
Host smart-9765e8aa-cf0a-4a64-b385-74e7c88bd0d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115117844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3115117844
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.343386068
Short name T442
Test name
Test status
Simulation time 6068822079 ps
CPU time 53.41 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 214916 kb
Host smart-c6a6b27e-4628-40ec-9844-9bb57c03bb83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343386068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.343386068
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1102155863
Short name T436
Test name
Test status
Simulation time 404064513 ps
CPU time 7.69 seconds
Started Aug 16 04:53:55 PM PDT 24
Finished Aug 16 04:54:03 PM PDT 24
Peak memory 212008 kb
Host smart-d6e28b69-3638-4be8-b84f-ca213a335d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102155863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1102155863
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.892126361
Short name T397
Test name
Test status
Simulation time 688843761 ps
CPU time 11.18 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 218216 kb
Host smart-dd2631c6-b8fb-4864-b3cc-79bff1e99f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892126361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.892126361
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3334483244
Short name T112
Test name
Test status
Simulation time 426926609 ps
CPU time 82.71 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:55:29 PM PDT 24
Peak memory 219536 kb
Host smart-0329917c-8939-4b25-aecf-35c4b3e73b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334483244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3334483244
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.731109405
Short name T3
Test name
Test status
Simulation time 590996987 ps
CPU time 7.47 seconds
Started Aug 16 04:54:14 PM PDT 24
Finished Aug 16 04:54:21 PM PDT 24
Peak memory 218244 kb
Host smart-10be805b-88c3-45e5-bf50-3c46d13ee84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731109405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.731109405
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1473933742
Short name T233
Test name
Test status
Simulation time 18601164071 ps
CPU time 245.93 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:58:34 PM PDT 24
Peak memory 243236 kb
Host smart-c4427a2d-2343-46b5-8ab6-8f6780c2fd8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473933742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1473933742
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2226727921
Short name T35
Test name
Test status
Simulation time 260341041 ps
CPU time 11.4 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 218468 kb
Host smart-cc8a0041-fb0e-4d4a-aae3-f91974744fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226727921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2226727921
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1446203154
Short name T168
Test name
Test status
Simulation time 185337241 ps
CPU time 9.83 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 219020 kb
Host smart-2b2d448d-59c7-4b49-8ad0-f14e901ceb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446203154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1446203154
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1450301608
Short name T348
Test name
Test status
Simulation time 2088531631 ps
CPU time 29.63 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:37 PM PDT 24
Peak memory 219056 kb
Host smart-e4ad2d44-49c3-43b0-be40-f2e1ff73b02b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450301608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1450301608
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2880882993
Short name T122
Test name
Test status
Simulation time 516056146 ps
CPU time 9.48 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 218308 kb
Host smart-90254b6f-05f4-4c50-829d-66f027ff67ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880882993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2880882993
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.35401298
Short name T40
Test name
Test status
Simulation time 62994441651 ps
CPU time 279.01 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:58:37 PM PDT 24
Peak memory 241688 kb
Host smart-9a444315-003d-4a99-b6aa-2fc57f6c81dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35401298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.35401298
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.458403579
Short name T163
Test name
Test status
Simulation time 1096431386 ps
CPU time 15.5 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:14 PM PDT 24
Peak memory 219036 kb
Host smart-61ee6412-d5e3-4f4b-9c75-8c46d0c95467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458403579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.458403579
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.868092967
Short name T27
Test name
Test status
Simulation time 300516570 ps
CPU time 115.86 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 238956 kb
Host smart-93f83c39-1246-4b6f-936a-30013d469b4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868092967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.868092967
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1579965396
Short name T277
Test name
Test status
Simulation time 367995266 ps
CPU time 9.4 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:54:19 PM PDT 24
Peak memory 219008 kb
Host smart-4e2b21e8-066d-4ab7-bfa7-145da53ff49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579965396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1579965396
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1443884399
Short name T142
Test name
Test status
Simulation time 656161542 ps
CPU time 26.99 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:32 PM PDT 24
Peak memory 219028 kb
Host smart-9ee5c6ec-6f89-4a5b-8be3-4f4272900cb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443884399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1443884399
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1396765944
Short name T350
Test name
Test status
Simulation time 4058115905 ps
CPU time 169.34 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:56:50 PM PDT 24
Peak memory 235656 kb
Host smart-8087620d-790b-4acd-a73b-a1eee087e7f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396765944 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1396765944
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3589596037
Short name T345
Test name
Test status
Simulation time 551838824 ps
CPU time 7.97 seconds
Started Aug 16 04:54:09 PM PDT 24
Finished Aug 16 04:54:17 PM PDT 24
Peak memory 218380 kb
Host smart-3e4c9a6a-1973-4e2b-84df-bbc140182f91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589596037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3589596037
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1872678412
Short name T240
Test name
Test status
Simulation time 20005110982 ps
CPU time 275.51 seconds
Started Aug 16 04:54:11 PM PDT 24
Finished Aug 16 04:58:46 PM PDT 24
Peak memory 228472 kb
Host smart-2349fa5f-58e7-44f6-a9ca-26559b3d2cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872678412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1872678412
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3164304828
Short name T293
Test name
Test status
Simulation time 368087851 ps
CPU time 9.95 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 218624 kb
Host smart-3016b65f-4732-48c1-aa62-219b3bbf709c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164304828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3164304828
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2089931351
Short name T254
Test name
Test status
Simulation time 411271500 ps
CPU time 20.59 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:23 PM PDT 24
Peak memory 219120 kb
Host smart-87ff999a-03c5-46d2-a63b-a69fce334a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089931351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2089931351
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3136360337
Short name T134
Test name
Test status
Simulation time 2372591212 ps
CPU time 90.18 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:55:32 PM PDT 24
Peak memory 227532 kb
Host smart-4e9de57e-5a7e-487a-baac-2291255e20c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136360337 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3136360337
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4170814731
Short name T319
Test name
Test status
Simulation time 249501030 ps
CPU time 9.4 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:16 PM PDT 24
Peak memory 218316 kb
Host smart-29c60586-7e11-4fca-881d-1be6de1dadbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170814731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4170814731
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2562636070
Short name T247
Test name
Test status
Simulation time 4871680109 ps
CPU time 131.68 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 243384 kb
Host smart-07e7f1b1-12c6-49ea-a43a-c71d64002515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562636070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2562636070
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1539099826
Short name T323
Test name
Test status
Simulation time 1376683161 ps
CPU time 18.37 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:54:27 PM PDT 24
Peak memory 218732 kb
Host smart-e76e8cf3-6971-409a-b3f0-533a03005d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539099826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1539099826
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.222426746
Short name T176
Test name
Test status
Simulation time 266447669 ps
CPU time 11.36 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:14 PM PDT 24
Peak memory 218836 kb
Host smart-7bfecfc2-ec4b-48ca-b64c-f9a5b709333e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222426746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.222426746
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3119613168
Short name T206
Test name
Test status
Simulation time 1509982968 ps
CPU time 23.64 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:54:34 PM PDT 24
Peak memory 219104 kb
Host smart-2c54b549-a578-4d9e-971d-031f986d33c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119613168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3119613168
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1252875337
Short name T218
Test name
Test status
Simulation time 3862907762 ps
CPU time 78.65 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:55:27 PM PDT 24
Peak memory 232232 kb
Host smart-50a04f79-63a2-48d2-9aa1-5c9b7fa462ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252875337 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1252875337
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2878398776
Short name T126
Test name
Test status
Simulation time 339482002 ps
CPU time 7.99 seconds
Started Aug 16 04:54:18 PM PDT 24
Finished Aug 16 04:54:26 PM PDT 24
Peak memory 218328 kb
Host smart-97a8111c-bfaa-48a5-b2fe-98c8408a390d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878398776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2878398776
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3317176396
Short name T241
Test name
Test status
Simulation time 12800401294 ps
CPU time 196.83 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:57:28 PM PDT 24
Peak memory 218528 kb
Host smart-0516f9e0-a937-46e3-bd6b-548f95ae9503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317176396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3317176396
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.29676522
Short name T339
Test name
Test status
Simulation time 5512589223 ps
CPU time 18.8 seconds
Started Aug 16 04:54:21 PM PDT 24
Finished Aug 16 04:54:40 PM PDT 24
Peak memory 218928 kb
Host smart-a7f8db7c-41e9-48b3-8584-c48a8da44576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29676522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.29676522
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.112978563
Short name T124
Test name
Test status
Simulation time 360272905 ps
CPU time 10.7 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 218516 kb
Host smart-e69e09a4-21e0-4930-8db9-6eb562daf35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112978563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.112978563
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1510729814
Short name T327
Test name
Test status
Simulation time 382929795 ps
CPU time 26.96 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:33 PM PDT 24
Peak memory 219152 kb
Host smart-7166fdb7-270b-43eb-97f6-cdd4eab80a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510729814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1510729814
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4283789780
Short name T208
Test name
Test status
Simulation time 19393239043 ps
CPU time 259.52 seconds
Started Aug 16 04:54:35 PM PDT 24
Finished Aug 16 04:58:55 PM PDT 24
Peak memory 235552 kb
Host smart-4f6d91f2-6064-43ef-ac22-ba151f81309d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283789780 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4283789780
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2353610210
Short name T284
Test name
Test status
Simulation time 434712801 ps
CPU time 9.64 seconds
Started Aug 16 04:54:17 PM PDT 24
Finished Aug 16 04:54:27 PM PDT 24
Peak memory 218288 kb
Host smart-19a09e4c-ac44-46cc-bd73-b8a6a80231ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353610210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2353610210
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3071003540
Short name T263
Test name
Test status
Simulation time 28300917692 ps
CPU time 388.24 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 05:00:39 PM PDT 24
Peak memory 237816 kb
Host smart-babc1d2d-44f6-476a-84cf-92a21ea61ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071003540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3071003540
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1509948936
Short name T326
Test name
Test status
Simulation time 2063146389 ps
CPU time 21.2 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218768 kb
Host smart-b4f01254-fe71-4b35-a027-514a89b5c1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509948936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1509948936
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1445823177
Short name T279
Test name
Test status
Simulation time 529722147 ps
CPU time 11.46 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:54:36 PM PDT 24
Peak memory 218500 kb
Host smart-33cc6df5-ca15-4e84-9b9a-70b0bd308236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445823177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1445823177
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1143278799
Short name T209
Test name
Test status
Simulation time 3399683249 ps
CPU time 36.21 seconds
Started Aug 16 04:54:17 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 219200 kb
Host smart-fbb6640d-6627-4360-913e-ab18867110a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143278799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1143278799
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1915510770
Short name T56
Test name
Test status
Simulation time 18725641472 ps
CPU time 255.76 seconds
Started Aug 16 04:54:16 PM PDT 24
Finished Aug 16 04:58:32 PM PDT 24
Peak memory 235656 kb
Host smart-f0544956-7d4a-4ffc-928f-895b5680a891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915510770 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1915510770
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3095635465
Short name T312
Test name
Test status
Simulation time 507286977 ps
CPU time 9.61 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:54:33 PM PDT 24
Peak memory 218180 kb
Host smart-3bf0b963-8c1a-4975-9349-84dc2997112b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095635465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3095635465
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3982405092
Short name T133
Test name
Test status
Simulation time 993025903 ps
CPU time 21.82 seconds
Started Aug 16 04:54:17 PM PDT 24
Finished Aug 16 04:54:39 PM PDT 24
Peak memory 218568 kb
Host smart-8aad9ec8-c9ec-4b20-99a5-14442bbe6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982405092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3982405092
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1408363660
Short name T300
Test name
Test status
Simulation time 263139430 ps
CPU time 11.4 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 218532 kb
Host smart-f6308eed-c951-4997-b002-4a05dea30ffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408363660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1408363660
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1791420032
Short name T73
Test name
Test status
Simulation time 2225873095 ps
CPU time 24.52 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 219212 kb
Host smart-104cbc0b-0d45-4ee8-9b40-a2c8bf7fef21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791420032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1791420032
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1425745126
Short name T289
Test name
Test status
Simulation time 6437874117 ps
CPU time 167.47 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:57:00 PM PDT 24
Peak memory 225284 kb
Host smart-5f21c01a-a6b3-4520-bfe5-270ecd988f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425745126 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1425745126
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.244848406
Short name T211
Test name
Test status
Simulation time 515737576 ps
CPU time 9.68 seconds
Started Aug 16 04:54:13 PM PDT 24
Finished Aug 16 04:54:23 PM PDT 24
Peak memory 218376 kb
Host smart-d66cadd7-1182-4e1d-9fed-7a27f826916f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244848406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.244848406
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.955665649
Short name T41
Test name
Test status
Simulation time 8470363090 ps
CPU time 244.73 seconds
Started Aug 16 04:54:14 PM PDT 24
Finished Aug 16 04:58:19 PM PDT 24
Peak memory 225236 kb
Host smart-42309f78-62fb-453c-8cc0-8f6446403353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955665649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.955665649
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3879173244
Short name T145
Test name
Test status
Simulation time 357176979 ps
CPU time 18.15 seconds
Started Aug 16 04:54:35 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 218484 kb
Host smart-daa24893-5eec-4bca-8a5f-7ea9f85e1603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879173244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3879173244
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3680466648
Short name T215
Test name
Test status
Simulation time 1119229826 ps
CPU time 31.79 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:54:44 PM PDT 24
Peak memory 219144 kb
Host smart-13fb27c5-affa-4d89-8ae3-34dabb5ba765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680466648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3680466648
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2384121980
Short name T183
Test name
Test status
Simulation time 1454648494 ps
CPU time 9.75 seconds
Started Aug 16 04:54:22 PM PDT 24
Finished Aug 16 04:54:32 PM PDT 24
Peak memory 218380 kb
Host smart-3cc738dc-6e58-494b-9ee4-c03975f89ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384121980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2384121980
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3307674580
Short name T328
Test name
Test status
Simulation time 8178606503 ps
CPU time 303.24 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:59:14 PM PDT 24
Peak memory 243356 kb
Host smart-16de1535-dd10-429f-b839-575b17424f00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307674580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3307674580
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3815418157
Short name T158
Test name
Test status
Simulation time 2060363993 ps
CPU time 22.02 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 218644 kb
Host smart-864ab566-b0ee-4426-a6f1-90341179d4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815418157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3815418157
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.411977226
Short name T151
Test name
Test status
Simulation time 181244690 ps
CPU time 9.77 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:54:22 PM PDT 24
Peak memory 218816 kb
Host smart-962638dc-ab98-46c3-a953-5da3eab380a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411977226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.411977226
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2981844344
Short name T283
Test name
Test status
Simulation time 220856100 ps
CPU time 18.2 seconds
Started Aug 16 04:54:23 PM PDT 24
Finished Aug 16 04:54:41 PM PDT 24
Peak memory 219096 kb
Host smart-71d84a83-e374-4837-91af-8a56253d304c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981844344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2981844344
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3058470508
Short name T63
Test name
Test status
Simulation time 260744878 ps
CPU time 9.53 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:38 PM PDT 24
Peak memory 218288 kb
Host smart-83d5232e-ed57-48ec-9f53-49248630ae3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058470508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3058470508
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2926598139
Short name T322
Test name
Test status
Simulation time 26997558152 ps
CPU time 112.23 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:56:26 PM PDT 24
Peak memory 218408 kb
Host smart-43ab15d2-5fa1-471a-966a-308847419d85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926598139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2926598139
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3093633420
Short name T226
Test name
Test status
Simulation time 335540362 ps
CPU time 18.28 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:54:42 PM PDT 24
Peak memory 218556 kb
Host smart-c5f03f98-939d-4640-a484-7db83e42d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093633420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3093633420
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1255071647
Short name T203
Test name
Test status
Simulation time 831972581 ps
CPU time 11.48 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 218788 kb
Host smart-2ade97b2-15a8-49d2-ac99-b707a52ec95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255071647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1255071647
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3186541418
Short name T193
Test name
Test status
Simulation time 3182719503 ps
CPU time 34.33 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:55:03 PM PDT 24
Peak memory 219552 kb
Host smart-5888b166-1064-4ce3-aebb-3d1964fc6b58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186541418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3186541418
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.853399817
Short name T199
Test name
Test status
Simulation time 1873689643 ps
CPU time 68.69 seconds
Started Aug 16 04:54:12 PM PDT 24
Finished Aug 16 04:55:21 PM PDT 24
Peak memory 224520 kb
Host smart-dff8fa88-2952-4b06-9ae0-53b101837414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853399817 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.853399817
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1625187016
Short name T248
Test name
Test status
Simulation time 4895576338 ps
CPU time 13.91 seconds
Started Aug 16 04:54:16 PM PDT 24
Finished Aug 16 04:54:30 PM PDT 24
Peak memory 218276 kb
Host smart-f2b83ff9-dfbe-4caf-990d-ac0f9c51069c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625187016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1625187016
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.638239137
Short name T308
Test name
Test status
Simulation time 3484891294 ps
CPU time 243.69 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:58:32 PM PDT 24
Peak memory 236712 kb
Host smart-e0ea0128-1a64-4d91-b481-5f796a17830c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638239137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.638239137
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1076465320
Short name T242
Test name
Test status
Simulation time 1010716290 ps
CPU time 21.8 seconds
Started Aug 16 04:54:30 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 218740 kb
Host smart-b8992169-9c9e-4964-9924-6bba81969b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076465320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1076465320
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.505031354
Short name T185
Test name
Test status
Simulation time 269625981 ps
CPU time 11.15 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:54:40 PM PDT 24
Peak memory 218456 kb
Host smart-884736dd-eae7-426c-96b5-1afd697032d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505031354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.505031354
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2707606077
Short name T288
Test name
Test status
Simulation time 543423119 ps
CPU time 36.74 seconds
Started Aug 16 04:54:32 PM PDT 24
Finished Aug 16 04:55:09 PM PDT 24
Peak memory 219008 kb
Host smart-337cdf92-6d6d-4f89-bedc-254de6d100be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707606077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2707606077
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3526030108
Short name T187
Test name
Test status
Simulation time 1813080584 ps
CPU time 83.69 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:55:35 PM PDT 24
Peak memory 234592 kb
Host smart-e8c2ae79-9ab8-4933-9323-e68379dd6fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526030108 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3526030108
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2712205157
Short name T221
Test name
Test status
Simulation time 1032507627 ps
CPU time 9.69 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:54:44 PM PDT 24
Peak memory 218300 kb
Host smart-2aee0d31-e171-4de9-b087-a9dd5b801141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712205157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2712205157
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1614692223
Short name T301
Test name
Test status
Simulation time 5966459305 ps
CPU time 177.92 seconds
Started Aug 16 04:54:15 PM PDT 24
Finished Aug 16 04:57:13 PM PDT 24
Peak memory 240828 kb
Host smart-84e24655-e2af-4166-9ca8-4a3a04d33162
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614692223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1614692223
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3320382276
Short name T204
Test name
Test status
Simulation time 5515040758 ps
CPU time 18.69 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218924 kb
Host smart-59e5581b-a92a-4f42-a64c-2cdc02e232e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320382276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3320382276
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.849938759
Short name T260
Test name
Test status
Simulation time 1021545168 ps
CPU time 11.47 seconds
Started Aug 16 04:54:18 PM PDT 24
Finished Aug 16 04:54:29 PM PDT 24
Peak memory 218896 kb
Host smart-79d33ee9-c302-404d-9dd6-80447317daff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849938759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.849938759
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2682049342
Short name T194
Test name
Test status
Simulation time 7415005090 ps
CPU time 110.62 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:56:15 PM PDT 24
Peak memory 224492 kb
Host smart-d8bf8452-010e-431d-825d-fe4fa338e49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682049342 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2682049342
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1089871763
Short name T313
Test name
Test status
Simulation time 332582675 ps
CPU time 7.88 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:06 PM PDT 24
Peak memory 218348 kb
Host smart-1775f6db-6b27-4b35-95fd-f807d069ec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089871763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1089871763
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1498408510
Short name T113
Test name
Test status
Simulation time 18997413647 ps
CPU time 203.62 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:57:32 PM PDT 24
Peak memory 218400 kb
Host smart-615aa4ce-5719-4ded-8a83-0d1108d5d4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498408510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1498408510
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.267940442
Short name T266
Test name
Test status
Simulation time 512629112 ps
CPU time 21.33 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:23 PM PDT 24
Peak memory 218496 kb
Host smart-3c141d6f-10a8-409a-bcf8-ade5829d6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267940442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.267940442
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3425987204
Short name T14
Test name
Test status
Simulation time 268041473 ps
CPU time 11.38 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:54:22 PM PDT 24
Peak memory 218552 kb
Host smart-9c334a22-3c21-4b02-a064-72f4e448569e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425987204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3425987204
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4089226900
Short name T29
Test name
Test status
Simulation time 761583415 ps
CPU time 224.9 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:57:51 PM PDT 24
Peak memory 238444 kb
Host smart-d52f2c2b-a53b-43d6-b1e5-5f403c136fec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089226900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4089226900
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2305944603
Short name T99
Test name
Test status
Simulation time 3974583683 ps
CPU time 15.48 seconds
Started Aug 16 04:53:57 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 219132 kb
Host smart-072cf8ba-efe7-4938-94ed-7f055364457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305944603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2305944603
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1850364768
Short name T180
Test name
Test status
Simulation time 611124305 ps
CPU time 22.64 seconds
Started Aug 16 04:54:13 PM PDT 24
Finished Aug 16 04:54:36 PM PDT 24
Peak memory 219032 kb
Host smart-1c5d1ad8-19c6-49d4-b0f4-579d6ea3e03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850364768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1850364768
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2772471443
Short name T65
Test name
Test status
Simulation time 175266629 ps
CPU time 7.93 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:47 PM PDT 24
Peak memory 218348 kb
Host smart-bf186822-04f0-4d02-ab6a-dedb83e94ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772471443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2772471443
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3461925991
Short name T201
Test name
Test status
Simulation time 24686764225 ps
CPU time 333.58 seconds
Started Aug 16 04:54:31 PM PDT 24
Finished Aug 16 05:00:05 PM PDT 24
Peak memory 237668 kb
Host smart-8f3234f5-f824-4a50-bf1a-cdcc22a0fefb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461925991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3461925991
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3874471273
Short name T135
Test name
Test status
Simulation time 2996066227 ps
CPU time 17.91 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:55:00 PM PDT 24
Peak memory 218696 kb
Host smart-babb29ed-7663-4d5b-bcbb-94b796bd2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874471273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3874471273
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2694359981
Short name T153
Test name
Test status
Simulation time 1039246984 ps
CPU time 12.03 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:54:46 PM PDT 24
Peak memory 218856 kb
Host smart-12db9cfb-41bd-47f8-a463-644b74743669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694359981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2694359981
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.682659852
Short name T281
Test name
Test status
Simulation time 753831752 ps
CPU time 20.58 seconds
Started Aug 16 04:54:32 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 218952 kb
Host smart-74071f31-1a22-482c-813e-8c2bd2b76073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682659852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.682659852
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2504287828
Short name T349
Test name
Test status
Simulation time 26343307376 ps
CPU time 153.58 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:57:08 PM PDT 24
Peak memory 228308 kb
Host smart-7729e4cf-f1f5-435b-9527-fcb0d2cb9fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504287828 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2504287828
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3560506951
Short name T117
Test name
Test status
Simulation time 1271740148 ps
CPU time 7.88 seconds
Started Aug 16 04:54:32 PM PDT 24
Finished Aug 16 04:54:40 PM PDT 24
Peak memory 218344 kb
Host smart-d3150dbe-b22c-41b0-adfb-f5d996c8facc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560506951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3560506951
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2970003552
Short name T343
Test name
Test status
Simulation time 66835570293 ps
CPU time 350.87 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 05:00:30 PM PDT 24
Peak memory 237592 kb
Host smart-45762db0-09ce-4568-81d5-26b495715c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970003552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2970003552
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1157960353
Short name T309
Test name
Test status
Simulation time 518445987 ps
CPU time 21.27 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218468 kb
Host smart-b5e19c0a-7fba-4aef-ad8d-cf1a030ae066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157960353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1157960353
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4046389379
Short name T223
Test name
Test status
Simulation time 391752323 ps
CPU time 10.32 seconds
Started Aug 16 04:54:30 PM PDT 24
Finished Aug 16 04:54:41 PM PDT 24
Peak memory 218812 kb
Host smart-c9f27e9c-fb84-4788-a900-2d5fac4223d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046389379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4046389379
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.215409205
Short name T16
Test name
Test status
Simulation time 625296799 ps
CPU time 32.08 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:55:07 PM PDT 24
Peak memory 219040 kb
Host smart-177a033e-14eb-45ed-a17e-31b20d891ca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215409205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.215409205
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.624137859
Short name T115
Test name
Test status
Simulation time 11241420536 ps
CPU time 192.5 seconds
Started Aug 16 04:54:32 PM PDT 24
Finished Aug 16 04:57:44 PM PDT 24
Peak memory 235624 kb
Host smart-0915688c-2460-446e-87d1-4d24acc44021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624137859 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.624137859
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.497385230
Short name T128
Test name
Test status
Simulation time 169250516 ps
CPU time 7.96 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:36 PM PDT 24
Peak memory 217744 kb
Host smart-9b26f512-0c92-499b-babd-740065ae3150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497385230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.497385230
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.184789097
Short name T33
Test name
Test status
Simulation time 18085169794 ps
CPU time 341.37 seconds
Started Aug 16 04:54:38 PM PDT 24
Finished Aug 16 05:00:20 PM PDT 24
Peak memory 242168 kb
Host smart-e7a8595c-ccf6-4456-a3f6-22e3d8fc5cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184789097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.184789097
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4228441130
Short name T217
Test name
Test status
Simulation time 8251858767 ps
CPU time 21.49 seconds
Started Aug 16 04:54:31 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 218816 kb
Host smart-cede4ae9-a925-4b17-b856-adcb08c6af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228441130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4228441130
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4190449931
Short name T331
Test name
Test status
Simulation time 1210388645 ps
CPU time 11.64 seconds
Started Aug 16 04:54:35 PM PDT 24
Finished Aug 16 04:54:47 PM PDT 24
Peak memory 218572 kb
Host smart-e9d72326-c3cd-4358-a1f1-019aea8e52af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190449931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4190449931
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3659577961
Short name T239
Test name
Test status
Simulation time 2180509113 ps
CPU time 45.16 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:55:18 PM PDT 24
Peak memory 219524 kb
Host smart-d153620d-7ba2-49e5-a679-14a4ff84cdfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659577961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3659577961
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3338606860
Short name T342
Test name
Test status
Simulation time 2870244139 ps
CPU time 74.29 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:55:44 PM PDT 24
Peak memory 223624 kb
Host smart-d0d5fa68-599c-4135-9c66-533e477ccbb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338606860 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3338606860
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1452760459
Short name T337
Test name
Test status
Simulation time 262572792 ps
CPU time 9.67 seconds
Started Aug 16 04:54:31 PM PDT 24
Finished Aug 16 04:54:41 PM PDT 24
Peak memory 218336 kb
Host smart-3829bd50-9ed9-4832-8bf3-337d3aa56c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452760459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1452760459
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.768878228
Short name T272
Test name
Test status
Simulation time 3174966971 ps
CPU time 212.54 seconds
Started Aug 16 04:54:24 PM PDT 24
Finished Aug 16 04:57:57 PM PDT 24
Peak memory 228152 kb
Host smart-cc95bce5-0ca6-4f99-be8a-072571312d85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768878228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.768878228
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1563902850
Short name T318
Test name
Test status
Simulation time 4129722300 ps
CPU time 18.55 seconds
Started Aug 16 04:54:38 PM PDT 24
Finished Aug 16 04:54:57 PM PDT 24
Peak memory 218796 kb
Host smart-46260640-62f4-47a5-8271-eec3cc5f2b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563902850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1563902850
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3135779710
Short name T98
Test name
Test status
Simulation time 1030108247 ps
CPU time 11.79 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:39 PM PDT 24
Peak memory 218852 kb
Host smart-01593d17-d221-4f9a-8279-e62a8562a1eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135779710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3135779710
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3198112345
Short name T32
Test name
Test status
Simulation time 272355083 ps
CPU time 12.53 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:41 PM PDT 24
Peak memory 218460 kb
Host smart-733c885c-99d4-48a8-aea9-be5ff65e6ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198112345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3198112345
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.986242782
Short name T37
Test name
Test status
Simulation time 495008705 ps
CPU time 9.67 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:54:44 PM PDT 24
Peak memory 219020 kb
Host smart-5112b85f-bed7-49e0-98cd-643591d728e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986242782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.986242782
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2827267753
Short name T291
Test name
Test status
Simulation time 33155275100 ps
CPU time 183.3 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:57:36 PM PDT 24
Peak memory 238732 kb
Host smart-ce4662aa-4287-4228-be7f-bcaa34d824a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827267753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2827267753
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.536819525
Short name T253
Test name
Test status
Simulation time 2153693940 ps
CPU time 20.87 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 218812 kb
Host smart-6b5f5169-497e-437c-ab4a-0b3a5328ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536819525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.536819525
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2064385943
Short name T237
Test name
Test status
Simulation time 948051502 ps
CPU time 11.81 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218484 kb
Host smart-6cd5d79d-321f-4b81-b967-1c907f2f469c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064385943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2064385943
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2861468653
Short name T77
Test name
Test status
Simulation time 312162445 ps
CPU time 20.78 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 219144 kb
Host smart-4b7483dc-2086-42b9-a9e0-b23e4671ec2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861468653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2861468653
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3144498970
Short name T171
Test name
Test status
Simulation time 9424989344 ps
CPU time 87.51 seconds
Started Aug 16 04:54:32 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 225452 kb
Host smart-4acd20d1-4c57-46a3-a619-0f7bc04ae4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144498970 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3144498970
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1889503868
Short name T149
Test name
Test status
Simulation time 495690625 ps
CPU time 9.53 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:37 PM PDT 24
Peak memory 218316 kb
Host smart-5206db49-37fb-4509-b7a9-aaee054f5901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889503868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1889503868
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2908141560
Short name T213
Test name
Test status
Simulation time 12808478074 ps
CPU time 255.67 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:58:53 PM PDT 24
Peak memory 237672 kb
Host smart-2a749629-fe95-4d5a-9cd4-859dcec9f478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908141560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2908141560
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1506899101
Short name T48
Test name
Test status
Simulation time 1057774587 ps
CPU time 22.73 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 218852 kb
Host smart-b3f72f68-82af-4bf6-9586-56ccd3a48c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506899101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1506899101
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3718986910
Short name T274
Test name
Test status
Simulation time 729516047 ps
CPU time 9.68 seconds
Started Aug 16 04:54:29 PM PDT 24
Finished Aug 16 04:54:39 PM PDT 24
Peak memory 218840 kb
Host smart-fa327ac4-7927-4621-8a84-cbdaded05ceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718986910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3718986910
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1952259139
Short name T38
Test name
Test status
Simulation time 3903905629 ps
CPU time 36.97 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:55:17 PM PDT 24
Peak memory 219152 kb
Host smart-84f7a99b-0c68-4b4e-b266-27801953e126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952259139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1952259139
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2551783024
Short name T132
Test name
Test status
Simulation time 2034033109 ps
CPU time 80.95 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:55:54 PM PDT 24
Peak memory 223816 kb
Host smart-66b052ef-fec1-4ce4-9492-c1a233509f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551783024 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2551783024
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3887536804
Short name T351
Test name
Test status
Simulation time 203755763 ps
CPU time 7.88 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218212 kb
Host smart-be145734-8bf0-433f-9288-b7136a66e8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887536804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3887536804
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.802908793
Short name T17
Test name
Test status
Simulation time 11786382444 ps
CPU time 215.48 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:58:09 PM PDT 24
Peak memory 242024 kb
Host smart-963b0d90-ce4e-460f-bebb-d8717c3d9812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802908793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.802908793
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.849505299
Short name T229
Test name
Test status
Simulation time 507785685 ps
CPU time 21.6 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 218860 kb
Host smart-3aca5bdf-8194-4703-a7a9-fd1ce3d7d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849505299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.849505299
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2223318451
Short name T1
Test name
Test status
Simulation time 263609582 ps
CPU time 11.59 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:54:51 PM PDT 24
Peak memory 218712 kb
Host smart-25818ef4-5a36-40e5-8f77-28f62f9ea486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223318451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2223318451
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1358927362
Short name T130
Test name
Test status
Simulation time 551738378 ps
CPU time 26.32 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:55:00 PM PDT 24
Peak memory 219132 kb
Host smart-e86834e1-79ca-41ed-91d5-388274f7afd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358927362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1358927362
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.610669072
Short name T294
Test name
Test status
Simulation time 8042494270 ps
CPU time 133.25 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:56:47 PM PDT 24
Peak memory 225104 kb
Host smart-2c5e1d39-cdc3-4289-9bcf-71df0f51e403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610669072 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.610669072
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2499575959
Short name T234
Test name
Test status
Simulation time 662175297 ps
CPU time 8.28 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:54:46 PM PDT 24
Peak memory 218388 kb
Host smart-492405ae-289e-45bc-a0c8-a879cc27354a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499575959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2499575959
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2123583304
Short name T271
Test name
Test status
Simulation time 26245084294 ps
CPU time 325.8 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 05:00:08 PM PDT 24
Peak memory 239888 kb
Host smart-ea154b62-9b92-492a-a35b-4f752c012572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123583304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2123583304
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1974691197
Short name T177
Test name
Test status
Simulation time 688702759 ps
CPU time 18.8 seconds
Started Aug 16 04:54:31 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 218816 kb
Host smart-2f7f20d0-0286-4cc6-b588-09d959befc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974691197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1974691197
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2064940987
Short name T340
Test name
Test status
Simulation time 1076008197 ps
CPU time 11.98 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218804 kb
Host smart-a31b07d6-e5c8-4eb2-9be6-194e237e6f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064940987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2064940987
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3424015316
Short name T231
Test name
Test status
Simulation time 408691349 ps
CPU time 10.74 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:38 PM PDT 24
Peak memory 219104 kb
Host smart-d6b1fd3e-b119-4194-8928-d7349dfe7c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424015316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3424015316
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1586709617
Short name T321
Test name
Test status
Simulation time 23751919806 ps
CPU time 183.83 seconds
Started Aug 16 04:54:33 PM PDT 24
Finished Aug 16 04:57:37 PM PDT 24
Peak memory 235640 kb
Host smart-221f389a-1641-40cd-a544-6c4146185a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586709617 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1586709617
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1035700150
Short name T146
Test name
Test status
Simulation time 688580512 ps
CPU time 7.74 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 218276 kb
Host smart-2982171d-1918-4add-a183-c2915ebb0817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035700150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1035700150
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4279021404
Short name T219
Test name
Test status
Simulation time 9130726574 ps
CPU time 125.35 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:56:41 PM PDT 24
Peak memory 239384 kb
Host smart-4ddba56b-eae4-4a8e-b6df-cca176f3affd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279021404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4279021404
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1791472089
Short name T139
Test name
Test status
Simulation time 1969871640 ps
CPU time 29 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:55:11 PM PDT 24
Peak memory 219012 kb
Host smart-618db16c-ac0b-4660-809e-abecd5c0a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791472089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1791472089
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1399134441
Short name T195
Test name
Test status
Simulation time 186522400 ps
CPU time 10.3 seconds
Started Aug 16 04:54:28 PM PDT 24
Finished Aug 16 04:54:39 PM PDT 24
Peak memory 218592 kb
Host smart-e3c10a4c-9a87-4313-b6b2-fb948fcbb60d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399134441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1399134441
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1825485590
Short name T11
Test name
Test status
Simulation time 404699630 ps
CPU time 24.98 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:55:06 PM PDT 24
Peak memory 219156 kb
Host smart-0e5ca8ab-85f8-4a20-88bb-e8d12e9a2f9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825485590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1825485590
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3934015355
Short name T20
Test name
Test status
Simulation time 8321043014 ps
CPU time 165.81 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:57:20 PM PDT 24
Peak memory 225472 kb
Host smart-98e0cc49-8253-409d-81c1-102c6f4e0be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934015355 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3934015355
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.605999012
Short name T44
Test name
Test status
Simulation time 173201895 ps
CPU time 7.8 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218292 kb
Host smart-7ce1c3f1-3082-42e6-9aad-d3a449f15037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605999012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.605999012
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4293094884
Short name T336
Test name
Test status
Simulation time 27395945629 ps
CPU time 252.17 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:58:52 PM PDT 24
Peak memory 236544 kb
Host smart-f41e293e-1d29-4ea7-8493-8e5807592925
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293094884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4293094884
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.914774631
Short name T47
Test name
Test status
Simulation time 3094916583 ps
CPU time 21.87 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 218816 kb
Host smart-ba45da15-72d7-460a-9ed8-989141d9ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914774631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.914774631
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2265732901
Short name T121
Test name
Test status
Simulation time 985958688 ps
CPU time 11.43 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 218808 kb
Host smart-16d51a9d-9c78-41cc-8e5b-d9725f0852be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265732901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2265732901
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1376661046
Short name T225
Test name
Test status
Simulation time 7842010213 ps
CPU time 23.68 seconds
Started Aug 16 04:54:38 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 219104 kb
Host smart-e4b22fd1-f2a6-4769-8581-1ce10cb5822c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376661046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1376661046
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3380686242
Short name T53
Test name
Test status
Simulation time 7011710383 ps
CPU time 92.09 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 224688 kb
Host smart-8887d4aa-03e9-4238-a771-f0e0a6e8112b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380686242 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3380686242
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3066096798
Short name T347
Test name
Test status
Simulation time 660836196 ps
CPU time 7.87 seconds
Started Aug 16 04:54:01 PM PDT 24
Finished Aug 16 04:54:09 PM PDT 24
Peak memory 218328 kb
Host smart-36a44449-2d13-43fe-a4b4-cd13bd7e77a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066096798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3066096798
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4092303668
Short name T15
Test name
Test status
Simulation time 20632904480 ps
CPU time 197.29 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:57:19 PM PDT 24
Peak memory 240028 kb
Host smart-43e36f59-4c1f-42e6-b1f8-883454760378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092303668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4092303668
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4041641940
Short name T353
Test name
Test status
Simulation time 1223766054 ps
CPU time 17.66 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:24 PM PDT 24
Peak memory 218732 kb
Host smart-2d748f01-42b7-4d88-937b-471c3ac9d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041641940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4041641940
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4047690569
Short name T173
Test name
Test status
Simulation time 1172634275 ps
CPU time 11.58 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 218800 kb
Host smart-0ddbc9a9-b29e-4816-9229-62f20a434aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047690569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4047690569
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3956978814
Short name T25
Test name
Test status
Simulation time 1405814547 ps
CPU time 115.73 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 238708 kb
Host smart-eca5f2c9-41e6-430e-a1d0-458dcdbf6625
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956978814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3956978814
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3917404306
Short name T78
Test name
Test status
Simulation time 183413745 ps
CPU time 10.45 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 219056 kb
Host smart-d55d2872-1e91-4ba7-884e-67baef55e8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917404306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3917404306
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3488768369
Short name T304
Test name
Test status
Simulation time 564993501 ps
CPU time 32.78 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:33 PM PDT 24
Peak memory 219016 kb
Host smart-7471ece4-61f7-4538-a197-11cb8e1640ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488768369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3488768369
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1622941002
Short name T224
Test name
Test status
Simulation time 14655146309 ps
CPU time 137.55 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 225668 kb
Host smart-97b543c9-5b0b-4488-8d8c-2c869aa2c8ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622941002 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1622941002
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1454701001
Short name T264
Test name
Test status
Simulation time 168311638 ps
CPU time 8.13 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:54:51 PM PDT 24
Peak memory 218368 kb
Host smart-bcd7a79d-b1d6-43b1-ac13-9abe0c9b79b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454701001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1454701001
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.118157962
Short name T310
Test name
Test status
Simulation time 6853532283 ps
CPU time 109.25 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:56:34 PM PDT 24
Peak memory 219244 kb
Host smart-3a2a3e48-88fd-4cb3-9123-b2ca1bf3093d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118157962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.118157962
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3349345746
Short name T42
Test name
Test status
Simulation time 391148817 ps
CPU time 18.25 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:57 PM PDT 24
Peak memory 218532 kb
Host smart-b12b8378-9ead-492a-b539-02daa6e8b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349345746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3349345746
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3175815833
Short name T238
Test name
Test status
Simulation time 326540702 ps
CPU time 11.74 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 218740 kb
Host smart-df2bd779-e33b-4b4e-afe3-87c39d446589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175815833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3175815833
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.73095907
Short name T255
Test name
Test status
Simulation time 1086421906 ps
CPU time 31.77 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:55:08 PM PDT 24
Peak memory 219120 kb
Host smart-f9aa5046-829e-48a2-8f56-4f3a099908c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73095907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.rom_ctrl_stress_all.73095907
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1203706755
Short name T164
Test name
Test status
Simulation time 1305565281 ps
CPU time 51.17 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:55:32 PM PDT 24
Peak memory 223400 kb
Host smart-7b04a985-66f4-40d1-b7a3-469cd9edd0d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203706755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1203706755
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2355584571
Short name T144
Test name
Test status
Simulation time 1072211098 ps
CPU time 9.21 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 219036 kb
Host smart-8c039ba8-28e2-4edc-9b5e-d4425a857894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355584571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2355584571
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1537668793
Short name T167
Test name
Test status
Simulation time 3425251054 ps
CPU time 204.13 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:58:04 PM PDT 24
Peak memory 219112 kb
Host smart-82c5342c-17dc-4b29-ab04-4ae22cd8a50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537668793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1537668793
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2878699708
Short name T276
Test name
Test status
Simulation time 1985042819 ps
CPU time 20.98 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 218568 kb
Host smart-1a3dd115-586f-43a6-8dad-168fe19ecfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878699708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2878699708
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.576094414
Short name T136
Test name
Test status
Simulation time 264459016 ps
CPU time 11.92 seconds
Started Aug 16 04:54:35 PM PDT 24
Finished Aug 16 04:54:47 PM PDT 24
Peak memory 218616 kb
Host smart-2ab09760-e798-49a0-923d-5575a4c82ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576094414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.576094414
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2908597111
Short name T175
Test name
Test status
Simulation time 351926682 ps
CPU time 23.58 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 219092 kb
Host smart-1433be5b-b64e-4d77-adbf-a892f83724fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908597111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2908597111
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2436594545
Short name T192
Test name
Test status
Simulation time 1752078209 ps
CPU time 75.45 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 224016 kb
Host smart-dc66b7b7-5362-4376-b645-294e15bb1814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436594545 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2436594545
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2911167289
Short name T220
Test name
Test status
Simulation time 992850692 ps
CPU time 9.66 seconds
Started Aug 16 04:54:35 PM PDT 24
Finished Aug 16 04:54:45 PM PDT 24
Peak memory 218296 kb
Host smart-da47c040-ac4d-48ca-b982-5683135282ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911167289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2911167289
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2928177678
Short name T235
Test name
Test status
Simulation time 10928394438 ps
CPU time 234.14 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:58:35 PM PDT 24
Peak memory 227152 kb
Host smart-ddb1b0e4-3bcf-4816-b228-dc09282a259c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928177678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2928177678
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3082774449
Short name T212
Test name
Test status
Simulation time 2153654833 ps
CPU time 21.4 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 218812 kb
Host smart-17990a1e-cfac-46f3-afdc-752e17539c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082774449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3082774449
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4014659503
Short name T249
Test name
Test status
Simulation time 1036338038 ps
CPU time 11.55 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218460 kb
Host smart-fdaa2a16-854a-425e-8f1a-773dcb45210f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014659503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4014659503
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3170616678
Short name T214
Test name
Test status
Simulation time 2521101021 ps
CPU time 35.89 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:55:16 PM PDT 24
Peak memory 219148 kb
Host smart-6511dcfd-b46e-47ae-9b08-dbc1aaf44679
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170616678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3170616678
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2111803302
Short name T55
Test name
Test status
Simulation time 5127659321 ps
CPU time 96.2 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:56:16 PM PDT 24
Peak memory 224540 kb
Host smart-c9dd91d6-2834-430d-8919-c201be0f6811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111803302 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2111803302
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3281852015
Short name T216
Test name
Test status
Simulation time 180119971 ps
CPU time 7.99 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218248 kb
Host smart-04c11ef9-e988-44c4-ae56-5414714dfc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281852015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3281852015
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2389361175
Short name T207
Test name
Test status
Simulation time 664055875 ps
CPU time 17.85 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:55:03 PM PDT 24
Peak memory 218688 kb
Host smart-3e444c76-fbb5-4b56-8dc5-c206b311eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389361175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2389361175
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.946361870
Short name T302
Test name
Test status
Simulation time 729308717 ps
CPU time 10.11 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218880 kb
Host smart-f6e5ef2d-e8b8-4f0c-a41e-cbb475b073a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946361870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.946361870
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.8470589
Short name T170
Test name
Test status
Simulation time 3040367088 ps
CPU time 33.36 seconds
Started Aug 16 04:54:34 PM PDT 24
Finished Aug 16 04:55:08 PM PDT 24
Peak memory 219196 kb
Host smart-a7821551-a068-4a99-b37a-ecbd9d89a1c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8470589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.rom_ctrl_stress_all.8470589
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2442602037
Short name T114
Test name
Test status
Simulation time 17502297027 ps
CPU time 184.84 seconds
Started Aug 16 04:54:37 PM PDT 24
Finished Aug 16 04:57:42 PM PDT 24
Peak memory 235620 kb
Host smart-990052c8-7e1f-4b07-804b-ff9a0604f6c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442602037 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2442602037
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2360184686
Short name T157
Test name
Test status
Simulation time 2710249973 ps
CPU time 192.34 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:57:54 PM PDT 24
Peak memory 224480 kb
Host smart-d8041293-db0a-47aa-bdc0-118fb34c2593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360184686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2360184686
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3389874337
Short name T299
Test name
Test status
Simulation time 1030649499 ps
CPU time 21.55 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 218852 kb
Host smart-864969d2-9603-4963-bb76-93a4ae9fa170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389874337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3389874337
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2696689696
Short name T324
Test name
Test status
Simulation time 261439392 ps
CPU time 11.81 seconds
Started Aug 16 04:54:36 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218424 kb
Host smart-b0230384-6bcd-4970-a678-180ae1b81a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696689696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2696689696
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.161630547
Short name T172
Test name
Test status
Simulation time 1104155757 ps
CPU time 32.83 seconds
Started Aug 16 04:54:38 PM PDT 24
Finished Aug 16 04:55:12 PM PDT 24
Peak memory 219136 kb
Host smart-5d65aaee-cd3a-4057-a475-3b0326273bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161630547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.161630547
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1004726588
Short name T307
Test name
Test status
Simulation time 170408882 ps
CPU time 8.06 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:54:49 PM PDT 24
Peak memory 218240 kb
Host smart-e02d9465-1dff-4252-a92f-87db75e36cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004726588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1004726588
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.766779947
Short name T202
Test name
Test status
Simulation time 9142541450 ps
CPU time 332.5 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 05:00:20 PM PDT 24
Peak memory 241696 kb
Host smart-a86915e5-5a47-43d5-9895-cf16dd9a2d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766779947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.766779947
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3747290027
Short name T46
Test name
Test status
Simulation time 990670045 ps
CPU time 21.27 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 218796 kb
Host smart-97da9c90-0263-4d42-a8a9-e467419776fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747290027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3747290027
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3340563818
Short name T118
Test name
Test status
Simulation time 259862380 ps
CPU time 11.81 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:54:53 PM PDT 24
Peak memory 218924 kb
Host smart-aba664df-4b7f-4c4e-ac54-2cd57dba1413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340563818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3340563818
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3944931317
Short name T200
Test name
Test status
Simulation time 1784169910 ps
CPU time 25.58 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:55:12 PM PDT 24
Peak memory 219076 kb
Host smart-a40ce3c2-09f8-432e-b03a-01af68d5ed17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944931317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3944931317
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2082296541
Short name T160
Test name
Test status
Simulation time 751217673 ps
CPU time 7.93 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 04:54:48 PM PDT 24
Peak memory 218296 kb
Host smart-4465d25d-b704-4989-8d26-981eeba8564e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082296541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2082296541
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3889265448
Short name T166
Test name
Test status
Simulation time 7042600847 ps
CPU time 364.96 seconds
Started Aug 16 04:54:40 PM PDT 24
Finished Aug 16 05:00:45 PM PDT 24
Peak memory 217656 kb
Host smart-7d293fd6-67e6-4b50-b5fe-7bdf6a40eefb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889265448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3889265448
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1217285576
Short name T155
Test name
Test status
Simulation time 1979298492 ps
CPU time 21.32 seconds
Started Aug 16 04:54:48 PM PDT 24
Finished Aug 16 04:55:09 PM PDT 24
Peak memory 218760 kb
Host smart-512cbaf2-e662-42db-8662-e0b7aeb943c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217285576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1217285576
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3103815020
Short name T123
Test name
Test status
Simulation time 180961730 ps
CPU time 9.86 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 218592 kb
Host smart-dabbcc7a-eb0e-4819-b260-5fad61acda17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103815020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3103815020
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.337054130
Short name T148
Test name
Test status
Simulation time 950984343 ps
CPU time 22.17 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:55:07 PM PDT 24
Peak memory 212080 kb
Host smart-dbb0c4cc-2c2a-469a-a621-1fb9e08158ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337054130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.337054130
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3557414270
Short name T197
Test name
Test status
Simulation time 206670447 ps
CPU time 8.14 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:54:51 PM PDT 24
Peak memory 218272 kb
Host smart-29816a86-63d6-4a99-9fc6-cfd3bb7497d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557414270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3557414270
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1169719393
Short name T245
Test name
Test status
Simulation time 8593877216 ps
CPU time 249.81 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:58:55 PM PDT 24
Peak memory 237848 kb
Host smart-66e9e292-84df-4bb5-b8d0-4befa499097b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169719393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1169719393
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3442816351
Short name T49
Test name
Test status
Simulation time 661677109 ps
CPU time 18.88 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 218840 kb
Host smart-0142f9b9-e9d4-42c9-ade8-9da7c02bc001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442816351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3442816351
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1530827842
Short name T334
Test name
Test status
Simulation time 271892835 ps
CPU time 11.38 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:54:57 PM PDT 24
Peak memory 218520 kb
Host smart-b06c469c-f752-4549-8a6d-fcb200996bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530827842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1530827842
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.668502696
Short name T75
Test name
Test status
Simulation time 737725206 ps
CPU time 26.43 seconds
Started Aug 16 04:54:48 PM PDT 24
Finished Aug 16 04:55:15 PM PDT 24
Peak memory 219096 kb
Host smart-088433ad-94f5-4f41-a89e-9b9e401647bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668502696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.668502696
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2230740292
Short name T256
Test name
Test status
Simulation time 2090508170 ps
CPU time 75.43 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 223660 kb
Host smart-4209e7f4-7cfe-47b1-a04e-e8165e50df2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230740292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2230740292
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2585456571
Short name T28
Test name
Test status
Simulation time 249799961 ps
CPU time 9.46 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:54:54 PM PDT 24
Peak memory 218340 kb
Host smart-82ee3466-657e-4b77-92fd-a4c577d8d679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585456571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2585456571
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2716543609
Short name T335
Test name
Test status
Simulation time 3081738612 ps
CPU time 203.26 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:58:08 PM PDT 24
Peak memory 236676 kb
Host smart-b50046f5-0c64-46ff-9471-07d75923453d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716543609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2716543609
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1818571724
Short name T141
Test name
Test status
Simulation time 1078348511 ps
CPU time 21.74 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:09 PM PDT 24
Peak memory 218772 kb
Host smart-67f5a1b5-462f-49db-bd24-692989ba5d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818571724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1818571724
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3659758753
Short name T330
Test name
Test status
Simulation time 2132859520 ps
CPU time 11.53 seconds
Started Aug 16 04:54:39 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 218792 kb
Host smart-dde41a6a-204b-4422-afc5-a839eb7643eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659758753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3659758753
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1288909700
Short name T18
Test name
Test status
Simulation time 726430210 ps
CPU time 23.07 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:55:08 PM PDT 24
Peak memory 219064 kb
Host smart-c9636d6d-b323-4bef-8d42-11fdae4be572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288909700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1288909700
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2897800457
Short name T138
Test name
Test status
Simulation time 249776468 ps
CPU time 9.6 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 218376 kb
Host smart-d147337e-48d9-4a71-951e-d4a50e8875ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897800457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2897800457
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1025125853
Short name T232
Test name
Test status
Simulation time 10946679947 ps
CPU time 271.11 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:59:21 PM PDT 24
Peak memory 242132 kb
Host smart-5539fd95-c3fb-4800-ad22-d7efcefec9ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025125853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1025125853
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2860047631
Short name T243
Test name
Test status
Simulation time 1009981448 ps
CPU time 21.51 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:55:10 PM PDT 24
Peak memory 218808 kb
Host smart-1cb1b38b-fa7c-4935-91fb-e069bbb7b4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860047631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2860047631
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4206142748
Short name T305
Test name
Test status
Simulation time 266562016 ps
CPU time 11.81 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:55:01 PM PDT 24
Peak memory 218540 kb
Host smart-34e19918-f3ce-4a0c-b834-64a2842b85f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206142748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4206142748
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3144303840
Short name T257
Test name
Test status
Simulation time 1341264680 ps
CPU time 22.23 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 219120 kb
Host smart-8d3f66cb-0248-4782-9309-afe491d005bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144303840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3144303840
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3500105414
Short name T54
Test name
Test status
Simulation time 2258861480 ps
CPU time 94.16 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 224068 kb
Host smart-bfde3610-0219-4f01-a849-b056e5dd51a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500105414 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3500105414
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2204103803
Short name T186
Test name
Test status
Simulation time 824626815 ps
CPU time 9.28 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:15 PM PDT 24
Peak memory 218260 kb
Host smart-1ab876af-04b3-4c40-9880-d4f8c2352217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204103803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2204103803
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.563813283
Short name T196
Test name
Test status
Simulation time 17654646572 ps
CPU time 197.24 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:57:20 PM PDT 24
Peak memory 233748 kb
Host smart-434b09f2-7f42-4c0f-a149-f43661718636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563813283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.563813283
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.734511184
Short name T268
Test name
Test status
Simulation time 497735128 ps
CPU time 21.43 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:25 PM PDT 24
Peak memory 218544 kb
Host smart-8b155e48-4d65-45da-954c-ee75b1e66479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734511184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.734511184
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2349436969
Short name T311
Test name
Test status
Simulation time 269395441 ps
CPU time 11.43 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:12 PM PDT 24
Peak memory 218552 kb
Host smart-c5899300-f8f0-4439-b94a-aec55fd62a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349436969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2349436969
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3147416317
Short name T30
Test name
Test status
Simulation time 459640174 ps
CPU time 116.93 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 238644 kb
Host smart-5781093d-4c2b-4291-86ee-c894975c03c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147416317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3147416317
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1008433432
Short name T280
Test name
Test status
Simulation time 5142168532 ps
CPU time 11.59 seconds
Started Aug 16 04:53:58 PM PDT 24
Finished Aug 16 04:54:10 PM PDT 24
Peak memory 219136 kb
Host smart-67e1cdfc-fcb9-491d-a985-868fb397495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008433432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1008433432
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.309671320
Short name T189
Test name
Test status
Simulation time 1240076928 ps
CPU time 44.58 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 219156 kb
Host smart-27954786-65d1-4d1a-86bd-88b8b389bd3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309671320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.309671320
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2332429771
Short name T297
Test name
Test status
Simulation time 5621194829 ps
CPU time 354.88 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 05:00:03 PM PDT 24
Peak memory 235684 kb
Host smart-9ca8e123-de96-4950-9bc7-174e3808be22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332429771 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2332429771
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.243626376
Short name T116
Test name
Test status
Simulation time 286102074 ps
CPU time 9.13 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:54:52 PM PDT 24
Peak memory 218368 kb
Host smart-d14f16d9-0181-4512-8bdc-ff70f79d60d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243626376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.243626376
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3273032353
Short name T52
Test name
Test status
Simulation time 18373117426 ps
CPU time 223.48 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:58:28 PM PDT 24
Peak memory 242236 kb
Host smart-efda48a8-68b2-432a-a0ad-8c1ef3a2a7e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273032353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3273032353
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4070151076
Short name T174
Test name
Test status
Simulation time 1975636017 ps
CPU time 22.04 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:55:07 PM PDT 24
Peak memory 218760 kb
Host smart-58b33359-07b9-4a8e-930f-3671e089be53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070151076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4070151076
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4045627532
Short name T259
Test name
Test status
Simulation time 1037319161 ps
CPU time 11.76 seconds
Started Aug 16 04:54:57 PM PDT 24
Finished Aug 16 04:55:09 PM PDT 24
Peak memory 218728 kb
Host smart-369a43f7-72b0-40af-a733-e7b5812e33a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045627532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4045627532
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1163367924
Short name T4
Test name
Test status
Simulation time 3106524220 ps
CPU time 40.69 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:55:24 PM PDT 24
Peak memory 219152 kb
Host smart-2517b4ad-203f-4670-8afc-f4062f428c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163367924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1163367924
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.665575843
Short name T179
Test name
Test status
Simulation time 1296946212 ps
CPU time 53.59 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:55:43 PM PDT 24
Peak memory 222256 kb
Host smart-9f3f93e5-85aa-4d6d-8ec4-f49fc31ef0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665575843 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.665575843
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.960243053
Short name T258
Test name
Test status
Simulation time 346610930 ps
CPU time 8.17 seconds
Started Aug 16 04:54:41 PM PDT 24
Finished Aug 16 04:54:50 PM PDT 24
Peak memory 218060 kb
Host smart-a032d1b4-0592-4103-90b9-4f7761807386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960243053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.960243053
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3129277893
Short name T265
Test name
Test status
Simulation time 7539351460 ps
CPU time 230.4 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:58:40 PM PDT 24
Peak memory 236920 kb
Host smart-e4124912-c02c-483c-8dc1-b28ce1243ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129277893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3129277893
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2625391740
Short name T120
Test name
Test status
Simulation time 516287337 ps
CPU time 20.91 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 218456 kb
Host smart-676a255a-9734-43dd-8704-a09095127c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625391740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2625391740
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3833118322
Short name T198
Test name
Test status
Simulation time 177752862 ps
CPU time 9.92 seconds
Started Aug 16 04:54:48 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 218464 kb
Host smart-73e97458-1d32-4093-b5aa-9690afbd38ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833118322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3833118322
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.734015219
Short name T275
Test name
Test status
Simulation time 1370741730 ps
CPU time 21.89 seconds
Started Aug 16 04:54:44 PM PDT 24
Finished Aug 16 04:55:07 PM PDT 24
Peak memory 219072 kb
Host smart-d11bb198-3127-4ed5-a6e6-5f248c3a277e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734015219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.734015219
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3184062520
Short name T36
Test name
Test status
Simulation time 939516998 ps
CPU time 34.49 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:55:20 PM PDT 24
Peak memory 223296 kb
Host smart-f07afbaa-9e3f-4837-b093-6bd5a499b28d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184062520 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3184062520
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3605222019
Short name T43
Test name
Test status
Simulation time 502165502 ps
CPU time 7.87 seconds
Started Aug 16 04:54:48 PM PDT 24
Finished Aug 16 04:54:56 PM PDT 24
Peak memory 218372 kb
Host smart-1769abbe-547a-4d5d-9971-312440d3d57c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605222019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3605222019
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2796551341
Short name T314
Test name
Test status
Simulation time 3018224200 ps
CPU time 167.49 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:57:33 PM PDT 24
Peak memory 240248 kb
Host smart-9ab82fc2-2656-4e99-b33d-ebb0ed18d853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796551341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2796551341
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4092410310
Short name T5
Test name
Test status
Simulation time 590696890 ps
CPU time 21.54 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:55:10 PM PDT 24
Peak memory 218644 kb
Host smart-649fe317-fe4d-414a-a28d-9e482103e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092410310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4092410310
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2211166987
Short name T252
Test name
Test status
Simulation time 660515145 ps
CPU time 9.81 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:54:56 PM PDT 24
Peak memory 218440 kb
Host smart-f782504a-897c-44da-8607-4da4e7a1c846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211166987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2211166987
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.182854675
Short name T262
Test name
Test status
Simulation time 370485072 ps
CPU time 19.82 seconds
Started Aug 16 04:54:43 PM PDT 24
Finished Aug 16 04:55:03 PM PDT 24
Peak memory 219108 kb
Host smart-cf08ec38-9215-49d4-8687-db9521acc93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182854675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.182854675
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3593014819
Short name T21
Test name
Test status
Simulation time 9644703915 ps
CPU time 102.02 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:56:28 PM PDT 24
Peak memory 226460 kb
Host smart-159ea9bb-39f8-48d1-ab92-05e8a445ebf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593014819 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3593014819
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2397534036
Short name T181
Test name
Test status
Simulation time 262647666 ps
CPU time 9.44 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 218360 kb
Host smart-3451681b-8b37-422f-994e-5543c8c38f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397534036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2397534036
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2765553233
Short name T169
Test name
Test status
Simulation time 21879786397 ps
CPU time 284.3 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:59:32 PM PDT 24
Peak memory 242944 kb
Host smart-c018c28f-4dbb-48d7-9642-ff67b64f4875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765553233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2765553233
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2991375616
Short name T131
Test name
Test status
Simulation time 337592417 ps
CPU time 18.38 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 218736 kb
Host smart-250c4ca3-584f-4890-a233-f432f0c90dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991375616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2991375616
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3782208494
Short name T127
Test name
Test status
Simulation time 675661159 ps
CPU time 10.14 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:54:59 PM PDT 24
Peak memory 218772 kb
Host smart-14975e32-d136-44a1-9704-f0625a2d1695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782208494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3782208494
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1271180551
Short name T333
Test name
Test status
Simulation time 1608729270 ps
CPU time 27.71 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:15 PM PDT 24
Peak memory 219132 kb
Host smart-32d7ddfc-42eb-410c-8fcb-8d46ef4b05bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271180551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1271180551
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3720641582
Short name T143
Test name
Test status
Simulation time 2781025192 ps
CPU time 129.86 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:56:56 PM PDT 24
Peak memory 227972 kb
Host smart-ed476a0c-fcb7-4bc9-ad24-fa2e3c932628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720641582 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3720641582
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2860762662
Short name T298
Test name
Test status
Simulation time 1031565071 ps
CPU time 9.25 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:54:54 PM PDT 24
Peak memory 218280 kb
Host smart-99eaf09f-6065-4387-9672-0489452b7428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860762662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2860762662
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2151748035
Short name T188
Test name
Test status
Simulation time 3722952584 ps
CPU time 183.35 seconds
Started Aug 16 04:54:42 PM PDT 24
Finished Aug 16 04:57:45 PM PDT 24
Peak memory 233708 kb
Host smart-d6e81dc3-e2d6-40c8-84d2-03c3af57b122
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151748035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2151748035
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1144512806
Short name T251
Test name
Test status
Simulation time 518391996 ps
CPU time 20.77 seconds
Started Aug 16 04:54:49 PM PDT 24
Finished Aug 16 04:55:10 PM PDT 24
Peak memory 218520 kb
Host smart-598019c4-fc1f-4c34-8bcf-ed3318aa0f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144512806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1144512806
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3150675836
Short name T156
Test name
Test status
Simulation time 798535710 ps
CPU time 9.82 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:54:56 PM PDT 24
Peak memory 218884 kb
Host smart-bea51c2c-fb8d-4f6b-9fb5-9ac196b03cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150675836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3150675836
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.356489924
Short name T320
Test name
Test status
Simulation time 1408698149 ps
CPU time 18.88 seconds
Started Aug 16 04:54:45 PM PDT 24
Finished Aug 16 04:55:04 PM PDT 24
Peak memory 219092 kb
Host smart-053e737c-d38a-48c9-b5dd-f378c73a8a8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356489924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.356489924
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1930306752
Short name T159
Test name
Test status
Simulation time 76714524679 ps
CPU time 245.71 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:58:56 PM PDT 24
Peak memory 230440 kb
Host smart-20e232c9-fafb-43b8-a14a-102e113a3ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930306752 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1930306752
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3681694100
Short name T315
Test name
Test status
Simulation time 2251176960 ps
CPU time 9.32 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:54:55 PM PDT 24
Peak memory 218524 kb
Host smart-8e8a51af-704b-49a3-bd80-341bcfba20e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681694100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3681694100
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3067441968
Short name T261
Test name
Test status
Simulation time 3888271151 ps
CPU time 236.22 seconds
Started Aug 16 04:54:46 PM PDT 24
Finished Aug 16 04:58:43 PM PDT 24
Peak memory 239604 kb
Host smart-9dee2555-c51e-4d36-93a3-e8d1742eb2c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067441968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3067441968
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.760158549
Short name T287
Test name
Test status
Simulation time 346134507 ps
CPU time 18.49 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:06 PM PDT 24
Peak memory 218576 kb
Host smart-2d95281d-c2d9-4c89-9d10-84de5de0e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760158549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.760158549
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3826659665
Short name T285
Test name
Test status
Simulation time 360702866 ps
CPU time 9.96 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:54:57 PM PDT 24
Peak memory 218628 kb
Host smart-47b8aca8-b4ef-4a8d-a838-c741bd759f47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826659665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3826659665
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.485566569
Short name T227
Test name
Test status
Simulation time 819480707 ps
CPU time 21.36 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:08 PM PDT 24
Peak memory 219156 kb
Host smart-4f09aae2-f1a0-4d90-8e2e-d7de01c94113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485566569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.485566569
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2084560768
Short name T316
Test name
Test status
Simulation time 2347783553 ps
CPU time 22.97 seconds
Started Aug 16 04:54:47 PM PDT 24
Finished Aug 16 04:55:10 PM PDT 24
Peak memory 222408 kb
Host smart-7c98be12-ee2e-4bd2-b8fd-c252421f5187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084560768 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2084560768
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3480874446
Short name T236
Test name
Test status
Simulation time 2362247843 ps
CPU time 8.07 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:00 PM PDT 24
Peak memory 218416 kb
Host smart-377dff30-68fb-4ff5-9005-8d1f4e1053bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480874446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3480874446
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3886515015
Short name T352
Test name
Test status
Simulation time 5456596526 ps
CPU time 316.92 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 05:00:09 PM PDT 24
Peak memory 239680 kb
Host smart-e22bb9f1-ebfe-44ef-a36b-b07e8bd76545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886515015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3886515015
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.273653198
Short name T6
Test name
Test status
Simulation time 2153944362 ps
CPU time 21.95 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:14 PM PDT 24
Peak memory 218836 kb
Host smart-145c6640-1df9-4133-b6da-4cfe95e1c66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273653198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.273653198
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1668711427
Short name T325
Test name
Test status
Simulation time 1015776036 ps
CPU time 11.22 seconds
Started Aug 16 04:54:54 PM PDT 24
Finished Aug 16 04:55:05 PM PDT 24
Peak memory 218796 kb
Host smart-9547ce54-0143-4b01-bb86-4d35d07a3108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668711427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1668711427
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2085233922
Short name T140
Test name
Test status
Simulation time 2453451315 ps
CPU time 10.27 seconds
Started Aug 16 04:54:48 PM PDT 24
Finished Aug 16 04:54:58 PM PDT 24
Peak memory 219132 kb
Host smart-d8fd0c20-6bc0-499b-ad5b-062dfb53dac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085233922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2085233922
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1245371533
Short name T125
Test name
Test status
Simulation time 7710566056 ps
CPU time 96.17 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:56:29 PM PDT 24
Peak memory 225272 kb
Host smart-86fa3434-1f10-4c5b-8f97-e83987d5a32d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245371533 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1245371533
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3129232646
Short name T190
Test name
Test status
Simulation time 172812965 ps
CPU time 7.96 seconds
Started Aug 16 04:54:53 PM PDT 24
Finished Aug 16 04:55:01 PM PDT 24
Peak memory 218364 kb
Host smart-44d21972-51c3-4b96-a8f5-8b8f568f9810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129232646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3129232646
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4006536097
Short name T250
Test name
Test status
Simulation time 4068354413 ps
CPU time 253.2 seconds
Started Aug 16 04:54:55 PM PDT 24
Finished Aug 16 04:59:09 PM PDT 24
Peak memory 218480 kb
Host smart-0fe986ef-9b3c-4fe6-bf9b-5f027aa30a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006536097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4006536097
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.501469878
Short name T306
Test name
Test status
Simulation time 1978368180 ps
CPU time 21.58 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:14 PM PDT 24
Peak memory 218564 kb
Host smart-3bee7895-5122-41b0-a492-be073e2cd1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501469878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.501469878
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.533019383
Short name T8
Test name
Test status
Simulation time 183274283 ps
CPU time 10.43 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:03 PM PDT 24
Peak memory 218540 kb
Host smart-77122acb-0a6d-4c68-9833-ff32b08b7590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533019383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.533019383
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3371552502
Short name T165
Test name
Test status
Simulation time 17622642829 ps
CPU time 49.24 seconds
Started Aug 16 04:54:58 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 219204 kb
Host smart-f93f64c8-2769-4ea9-8229-bca3ab1e6814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371552502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3371552502
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2220459700
Short name T267
Test name
Test status
Simulation time 14910948417 ps
CPU time 169.53 seconds
Started Aug 16 04:54:53 PM PDT 24
Finished Aug 16 04:57:42 PM PDT 24
Peak memory 235580 kb
Host smart-9cf42887-ec1d-4eaf-b243-61cf32c7e216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220459700 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2220459700
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.67492697
Short name T341
Test name
Test status
Simulation time 259838977 ps
CPU time 9.55 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:02 PM PDT 24
Peak memory 217628 kb
Host smart-139630e4-feb5-49cc-b3c9-26128ef9724f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67492697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.67492697
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1893609335
Short name T290
Test name
Test status
Simulation time 5976414915 ps
CPU time 304.73 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:59:55 PM PDT 24
Peak memory 238676 kb
Host smart-3f435dcb-323d-4110-8852-8eda7f0186d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893609335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1893609335
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3006915244
Short name T119
Test name
Test status
Simulation time 4483380000 ps
CPU time 21.65 seconds
Started Aug 16 04:54:50 PM PDT 24
Finished Aug 16 04:55:12 PM PDT 24
Peak memory 218924 kb
Host smart-382df9b9-99d8-4f84-b31c-e4dedbe206fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006915244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3006915244
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.947649063
Short name T292
Test name
Test status
Simulation time 179288440 ps
CPU time 10.3 seconds
Started Aug 16 04:54:53 PM PDT 24
Finished Aug 16 04:55:03 PM PDT 24
Peak memory 218528 kb
Host smart-00db32cb-36b7-48ec-9166-cb40dd8deac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947649063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.947649063
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1610534437
Short name T329
Test name
Test status
Simulation time 759537463 ps
CPU time 37.87 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:55:30 PM PDT 24
Peak memory 219136 kb
Host smart-2224f375-75ce-49d7-b520-68b98daf3624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610534437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1610534437
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2503835490
Short name T244
Test name
Test status
Simulation time 35737812665 ps
CPU time 148.66 seconds
Started Aug 16 04:54:53 PM PDT 24
Finished Aug 16 04:57:22 PM PDT 24
Peak memory 228112 kb
Host smart-945c83c3-a75c-4fe3-98b7-b31ff2eed9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503835490 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2503835490
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2020228005
Short name T222
Test name
Test status
Simulation time 987360071 ps
CPU time 9.57 seconds
Started Aug 16 04:54:51 PM PDT 24
Finished Aug 16 04:55:01 PM PDT 24
Peak memory 217976 kb
Host smart-3c3d30c1-8597-41e2-84ad-378bc2e916d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020228005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2020228005
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1412348752
Short name T332
Test name
Test status
Simulation time 9640873930 ps
CPU time 260.31 seconds
Started Aug 16 04:54:52 PM PDT 24
Finished Aug 16 04:59:12 PM PDT 24
Peak memory 237768 kb
Host smart-84d26b9a-0557-4ddd-888e-f5ff9b4c7f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412348752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1412348752
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.481015768
Short name T230
Test name
Test status
Simulation time 511471365 ps
CPU time 21.73 seconds
Started Aug 16 04:54:51 PM PDT 24
Finished Aug 16 04:55:13 PM PDT 24
Peak memory 218476 kb
Host smart-45ad6559-f351-4ce0-bc7f-88e0babb7b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481015768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.481015768
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1634428823
Short name T228
Test name
Test status
Simulation time 723742122 ps
CPU time 10.24 seconds
Started Aug 16 04:54:54 PM PDT 24
Finished Aug 16 04:55:04 PM PDT 24
Peak memory 218708 kb
Host smart-92fe52eb-0a60-46c0-9f8a-b4798134b7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634428823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1634428823
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2868081291
Short name T191
Test name
Test status
Simulation time 16662689119 ps
CPU time 34.42 seconds
Started Aug 16 04:54:53 PM PDT 24
Finished Aug 16 04:55:27 PM PDT 24
Peak memory 219180 kb
Host smart-153ee273-3ddf-40d9-b5ef-6a2f75724941
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868081291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2868081291
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2081116435
Short name T12
Test name
Test status
Simulation time 8172566832 ps
CPU time 89.52 seconds
Started Aug 16 04:54:51 PM PDT 24
Finished Aug 16 04:56:21 PM PDT 24
Peak memory 232260 kb
Host smart-ea1233e8-7a2f-4c91-a087-cae82b411938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081116435 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2081116435
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3093364127
Short name T147
Test name
Test status
Simulation time 3080163889 ps
CPU time 8.92 seconds
Started Aug 16 04:54:13 PM PDT 24
Finished Aug 16 04:54:22 PM PDT 24
Peak memory 218332 kb
Host smart-b83575dc-a935-4a35-9a3c-e9b9542a0e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093364127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3093364127
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4199651905
Short name T39
Test name
Test status
Simulation time 3174754124 ps
CPU time 207.03 seconds
Started Aug 16 04:53:59 PM PDT 24
Finished Aug 16 04:57:26 PM PDT 24
Peak memory 236812 kb
Host smart-24ce4329-dcfe-4fbc-b25b-fc42abbe802f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199651905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4199651905
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3660078732
Short name T269
Test name
Test status
Simulation time 2059384263 ps
CPU time 20.45 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:54:28 PM PDT 24
Peak memory 218768 kb
Host smart-9d67e482-a433-40ce-936d-d6b2b227a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660078732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3660078732
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.311295003
Short name T129
Test name
Test status
Simulation time 729325344 ps
CPU time 10.37 seconds
Started Aug 16 04:54:00 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 218912 kb
Host smart-e7e80970-7b83-4d79-9fbe-da00df932d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311295003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.311295003
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1016121547
Short name T295
Test name
Test status
Simulation time 1498492352 ps
CPU time 12.35 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:16 PM PDT 24
Peak memory 215172 kb
Host smart-41776576-3de7-4a8b-a7e1-24ba46bcb839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016121547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1016121547
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3631217176
Short name T210
Test name
Test status
Simulation time 531461793 ps
CPU time 25.34 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:54:36 PM PDT 24
Peak memory 219028 kb
Host smart-ad69b848-bf23-4ea2-88d7-80de81ebfd14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631217176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3631217176
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2440461171
Short name T270
Test name
Test status
Simulation time 6128702962 ps
CPU time 171.88 seconds
Started Aug 16 04:54:09 PM PDT 24
Finished Aug 16 04:57:02 PM PDT 24
Peak memory 226356 kb
Host smart-b9b32e65-ab1c-441a-a20a-0ce9e2e74d4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440461171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2440461171
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.845815071
Short name T286
Test name
Test status
Simulation time 950187983 ps
CPU time 9.47 seconds
Started Aug 16 04:54:09 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 218312 kb
Host smart-9b43886d-9735-4a24-a0f3-3b7c76430118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845815071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.845815071
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2215921928
Short name T162
Test name
Test status
Simulation time 4971265152 ps
CPU time 286.85 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:58:50 PM PDT 24
Peak memory 229948 kb
Host smart-bdd714c3-29a4-4cd1-8cf6-1193b908710e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215921928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2215921928
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.407931494
Short name T303
Test name
Test status
Simulation time 1030483081 ps
CPU time 22.18 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:54:26 PM PDT 24
Peak memory 218476 kb
Host smart-3b77d360-1181-423e-affc-e53cc5fa19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407931494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.407931494
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2481823200
Short name T45
Test name
Test status
Simulation time 272005480 ps
CPU time 11.43 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:16 PM PDT 24
Peak memory 218600 kb
Host smart-145a609e-1f4d-47cc-b3d9-a73eb82b619c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481823200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2481823200
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.184129071
Short name T296
Test name
Test status
Simulation time 531115084 ps
CPU time 10.96 seconds
Started Aug 16 04:54:27 PM PDT 24
Finished Aug 16 04:54:38 PM PDT 24
Peak memory 218912 kb
Host smart-2a658339-5e55-47b0-b128-d82a1b524f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184129071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.184129071
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.179982116
Short name T150
Test name
Test status
Simulation time 11313045058 ps
CPU time 19.92 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:54:28 PM PDT 24
Peak memory 219240 kb
Host smart-d85fbdd2-eb68-4885-bb72-81db2902714c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179982116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.179982116
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3419406374
Short name T31
Test name
Test status
Simulation time 2378760500 ps
CPU time 129.55 seconds
Started Aug 16 04:54:09 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 223812 kb
Host smart-f32b900f-3eba-4b5e-b8ce-bfe4f40ac986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419406374 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3419406374
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.216762832
Short name T64
Test name
Test status
Simulation time 250725011 ps
CPU time 9.34 seconds
Started Aug 16 04:54:02 PM PDT 24
Finished Aug 16 04:54:11 PM PDT 24
Peak memory 218244 kb
Host smart-a5123caa-7538-4ce8-ab8a-3a60455d93fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216762832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.216762832
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1061862141
Short name T34
Test name
Test status
Simulation time 4724394787 ps
CPU time 224.98 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:57:49 PM PDT 24
Peak memory 237676 kb
Host smart-8c707c2d-9637-4733-90b1-303d2de26911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061862141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1061862141
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1827186957
Short name T50
Test name
Test status
Simulation time 346322065 ps
CPU time 18.61 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:54:23 PM PDT 24
Peak memory 218468 kb
Host smart-03616be2-5655-4820-9302-3ee0cead4f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827186957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1827186957
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3074266257
Short name T344
Test name
Test status
Simulation time 1067550565 ps
CPU time 11.45 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:18 PM PDT 24
Peak memory 218820 kb
Host smart-233f00d3-31c8-43a4-b76e-58736fb6b88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074266257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3074266257
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.570878715
Short name T346
Test name
Test status
Simulation time 2165371572 ps
CPU time 10.11 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 215228 kb
Host smart-c2fa21f8-456c-4011-91ae-1f196dd0e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570878715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.570878715
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4168453210
Short name T246
Test name
Test status
Simulation time 747991872 ps
CPU time 45.36 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:56 PM PDT 24
Peak memory 219096 kb
Host smart-3269ebde-aecc-4963-bb3f-c6d6a321d2de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168453210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4168453210
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3719194817
Short name T338
Test name
Test status
Simulation time 4774587432 ps
CPU time 248.55 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:58:13 PM PDT 24
Peak memory 225172 kb
Host smart-84a760fc-236c-48c5-b3d5-f4a11808e08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719194817 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3719194817
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4144275452
Short name T161
Test name
Test status
Simulation time 347017210 ps
CPU time 8.18 seconds
Started Aug 16 04:54:07 PM PDT 24
Finished Aug 16 04:54:15 PM PDT 24
Peak memory 218308 kb
Host smart-abaa99f8-63b2-487e-ba37-c322784754f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144275452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4144275452
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2811228020
Short name T154
Test name
Test status
Simulation time 2744101804 ps
CPU time 160.7 seconds
Started Aug 16 04:54:30 PM PDT 24
Finished Aug 16 04:57:11 PM PDT 24
Peak memory 236620 kb
Host smart-d26dfb9f-86d3-4424-b2c5-f802011faf51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811228020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2811228020
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3306646347
Short name T273
Test name
Test status
Simulation time 448095421 ps
CPU time 18.41 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:23 PM PDT 24
Peak memory 218740 kb
Host smart-13c0f81f-b583-43ba-ba0a-5d46e302d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306646347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3306646347
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.537157720
Short name T278
Test name
Test status
Simulation time 702852946 ps
CPU time 10.28 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 218984 kb
Host smart-404c4be6-e1ff-4d0c-9f84-67812ff61aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537157720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.537157720
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3042537503
Short name T182
Test name
Test status
Simulation time 1085094106 ps
CPU time 12.15 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:15 PM PDT 24
Peak memory 219128 kb
Host smart-ee8e3110-8d04-4123-a8af-4c69b3f7fe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042537503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3042537503
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3851392309
Short name T76
Test name
Test status
Simulation time 289790357 ps
CPU time 19.36 seconds
Started Aug 16 04:54:10 PM PDT 24
Finished Aug 16 04:54:30 PM PDT 24
Peak memory 219024 kb
Host smart-d1b92d92-1e24-497f-9f8c-d722492d5870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851392309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3851392309
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.766408576
Short name T23
Test name
Test status
Simulation time 3152238126 ps
CPU time 125.16 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 225836 kb
Host smart-9b75def3-8ba0-4db8-b3c0-2c8d26a47c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766408576 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.766408576
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3516265862
Short name T282
Test name
Test status
Simulation time 1004604961 ps
CPU time 13.29 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:54:20 PM PDT 24
Peak memory 218244 kb
Host smart-ac86a2f3-2865-412e-bb11-d2f2f800052b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516265862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3516265862
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2410598799
Short name T317
Test name
Test status
Simulation time 58513469032 ps
CPU time 246.49 seconds
Started Aug 16 04:54:08 PM PDT 24
Finished Aug 16 04:58:15 PM PDT 24
Peak memory 233368 kb
Host smart-29b7c943-1eba-4bb9-8750-e5dcca8be70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410598799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2410598799
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3828895777
Short name T205
Test name
Test status
Simulation time 2071122282 ps
CPU time 21.5 seconds
Started Aug 16 04:54:05 PM PDT 24
Finished Aug 16 04:54:28 PM PDT 24
Peak memory 218852 kb
Host smart-ef9824a7-b32e-4733-86d9-64d8464de657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828895777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3828895777
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.586512222
Short name T100
Test name
Test status
Simulation time 2908400878 ps
CPU time 10.14 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:13 PM PDT 24
Peak memory 219172 kb
Host smart-5d58550b-941c-4f6f-a1c0-27a9d0b6fd77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586512222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.586512222
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.203810066
Short name T74
Test name
Test status
Simulation time 349736116 ps
CPU time 11.89 seconds
Started Aug 16 04:54:03 PM PDT 24
Finished Aug 16 04:54:15 PM PDT 24
Peak memory 219100 kb
Host smart-777e59ad-7d88-43cb-9aed-84a99a621abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203810066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.203810066
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1281315203
Short name T184
Test name
Test status
Simulation time 2267046939 ps
CPU time 30.5 seconds
Started Aug 16 04:54:04 PM PDT 24
Finished Aug 16 04:54:34 PM PDT 24
Peak memory 219172 kb
Host smart-f239fc08-d6f7-4cc9-ac59-9722e4f6c7f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281315203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1281315203
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3415505817
Short name T178
Test name
Test status
Simulation time 4736092762 ps
CPU time 124.32 seconds
Started Aug 16 04:54:06 PM PDT 24
Finished Aug 16 04:56:11 PM PDT 24
Peak memory 224888 kb
Host smart-43a5d4ff-bfd7-4693-9085-37d8a79e5f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415505817 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3415505817
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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