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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.49 96.89 92.13 97.68 100.00 98.62 98.05 99.06


Total test records in report: 459
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T294 /workspace/coverage/default/29.rom_ctrl_stress_all.3234509820 Aug 17 04:55:48 PM PDT 24 Aug 17 04:56:22 PM PDT 24 574065979 ps
T295 /workspace/coverage/default/4.rom_ctrl_stress_all.3418585607 Aug 17 04:55:23 PM PDT 24 Aug 17 04:56:14 PM PDT 24 8580741170 ps
T296 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.522179396 Aug 17 04:55:55 PM PDT 24 Aug 17 04:56:06 PM PDT 24 1101146780 ps
T297 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1799612500 Aug 17 04:55:31 PM PDT 24 Aug 17 04:57:22 PM PDT 24 2258300889 ps
T298 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1019719106 Aug 17 04:55:41 PM PDT 24 Aug 17 04:59:49 PM PDT 24 7177063078 ps
T299 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4290954262 Aug 17 04:55:51 PM PDT 24 Aug 17 04:57:02 PM PDT 24 3437801841 ps
T300 /workspace/coverage/default/26.rom_ctrl_stress_all.791187754 Aug 17 04:55:36 PM PDT 24 Aug 17 04:56:04 PM PDT 24 2120650228 ps
T301 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3618007362 Aug 17 04:55:34 PM PDT 24 Aug 17 04:55:56 PM PDT 24 507540482 ps
T302 /workspace/coverage/default/1.rom_ctrl_alert_test.3555589651 Aug 17 04:55:21 PM PDT 24 Aug 17 04:55:29 PM PDT 24 395992712 ps
T303 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3042162602 Aug 17 04:55:51 PM PDT 24 Aug 17 04:56:10 PM PDT 24 1324196641 ps
T304 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.718760934 Aug 17 04:55:48 PM PDT 24 Aug 17 04:56:21 PM PDT 24 3001571309 ps
T305 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3892680667 Aug 17 04:55:11 PM PDT 24 Aug 17 04:57:44 PM PDT 24 5362367357 ps
T306 /workspace/coverage/default/27.rom_ctrl_stress_all.1949499435 Aug 17 04:55:38 PM PDT 24 Aug 17 04:55:57 PM PDT 24 3919217782 ps
T307 /workspace/coverage/default/16.rom_ctrl_alert_test.2363714065 Aug 17 04:55:25 PM PDT 24 Aug 17 04:55:34 PM PDT 24 2054158177 ps
T308 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2224896366 Aug 17 04:55:31 PM PDT 24 Aug 17 04:58:41 PM PDT 24 4418542164 ps
T309 /workspace/coverage/default/3.rom_ctrl_alert_test.4055415070 Aug 17 04:55:21 PM PDT 24 Aug 17 04:55:29 PM PDT 24 174377087 ps
T310 /workspace/coverage/default/0.rom_ctrl_smoke.1780433093 Aug 17 04:55:21 PM PDT 24 Aug 17 04:55:31 PM PDT 24 728649491 ps
T311 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1829757447 Aug 17 04:55:48 PM PDT 24 Aug 17 05:00:13 PM PDT 24 8471742948 ps
T312 /workspace/coverage/default/48.rom_ctrl_stress_all.3624921822 Aug 17 04:56:04 PM PDT 24 Aug 17 04:56:31 PM PDT 24 757936873 ps
T313 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3385314039 Aug 17 04:55:49 PM PDT 24 Aug 17 04:56:07 PM PDT 24 1321348921 ps
T314 /workspace/coverage/default/22.rom_ctrl_stress_all.791022692 Aug 17 04:55:49 PM PDT 24 Aug 17 04:56:33 PM PDT 24 17227678058 ps
T315 /workspace/coverage/default/39.rom_ctrl_stress_all.991097475 Aug 17 04:55:50 PM PDT 24 Aug 17 04:56:13 PM PDT 24 1491884043 ps
T316 /workspace/coverage/default/49.rom_ctrl_alert_test.4128952641 Aug 17 04:56:07 PM PDT 24 Aug 17 04:56:17 PM PDT 24 249719468 ps
T317 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1179075760 Aug 17 04:55:37 PM PDT 24 Aug 17 04:59:49 PM PDT 24 4321001563 ps
T318 /workspace/coverage/default/45.rom_ctrl_alert_test.172149801 Aug 17 04:56:03 PM PDT 24 Aug 17 04:56:13 PM PDT 24 249195818 ps
T319 /workspace/coverage/default/30.rom_ctrl_stress_all.3882438281 Aug 17 04:55:50 PM PDT 24 Aug 17 04:56:31 PM PDT 24 799441778 ps
T320 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3252266605 Aug 17 04:56:06 PM PDT 24 Aug 17 04:56:17 PM PDT 24 1016454118 ps
T321 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1254865628 Aug 17 04:55:55 PM PDT 24 Aug 17 04:56:06 PM PDT 24 272135963 ps
T322 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1526110481 Aug 17 04:56:04 PM PDT 24 Aug 17 04:59:43 PM PDT 24 34568834990 ps
T323 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3276967949 Aug 17 04:55:49 PM PDT 24 Aug 17 05:01:01 PM PDT 24 19483334310 ps
T324 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.623611577 Aug 17 04:56:03 PM PDT 24 Aug 17 04:56:22 PM PDT 24 420895431 ps
T325 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2724019406 Aug 17 04:55:26 PM PDT 24 Aug 17 05:00:04 PM PDT 24 6063632539 ps
T326 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3261683493 Aug 17 04:56:11 PM PDT 24 Aug 17 04:56:21 PM PDT 24 265585335 ps
T327 /workspace/coverage/default/23.rom_ctrl_alert_test.720588691 Aug 17 04:55:54 PM PDT 24 Aug 17 04:56:04 PM PDT 24 1033258975 ps
T328 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4003490115 Aug 17 04:55:30 PM PDT 24 Aug 17 04:55:42 PM PDT 24 538105399 ps
T329 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1524828887 Aug 17 04:55:27 PM PDT 24 Aug 17 04:55:37 PM PDT 24 358167858 ps
T330 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2005561304 Aug 17 04:55:31 PM PDT 24 Aug 17 04:58:45 PM PDT 24 4333650165 ps
T331 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4171526036 Aug 17 04:55:27 PM PDT 24 Aug 17 04:55:49 PM PDT 24 1976174668 ps
T332 /workspace/coverage/default/6.rom_ctrl_alert_test.198381688 Aug 17 04:55:24 PM PDT 24 Aug 17 04:55:34 PM PDT 24 251772848 ps
T333 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.337465206 Aug 17 04:55:22 PM PDT 24 Aug 17 04:55:32 PM PDT 24 2462135122 ps
T334 /workspace/coverage/default/32.rom_ctrl_stress_all.4245015526 Aug 17 04:55:55 PM PDT 24 Aug 17 04:56:20 PM PDT 24 2041322784 ps
T335 /workspace/coverage/default/14.rom_ctrl_stress_all.3989317410 Aug 17 04:55:26 PM PDT 24 Aug 17 04:56:00 PM PDT 24 314430265 ps
T336 /workspace/coverage/default/44.rom_ctrl_stress_all.3937204262 Aug 17 04:55:53 PM PDT 24 Aug 17 04:56:31 PM PDT 24 819293418 ps
T337 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.536047921 Aug 17 04:55:49 PM PDT 24 Aug 17 04:56:07 PM PDT 24 688547794 ps
T338 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3757552364 Aug 17 04:55:44 PM PDT 24 Aug 17 04:58:23 PM PDT 24 8876986082 ps
T339 /workspace/coverage/default/46.rom_ctrl_stress_all.1339649629 Aug 17 04:56:09 PM PDT 24 Aug 17 04:56:24 PM PDT 24 396213020 ps
T340 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.844873523 Aug 17 04:55:42 PM PDT 24 Aug 17 04:55:53 PM PDT 24 262437441 ps
T341 /workspace/coverage/default/8.rom_ctrl_stress_all.308520267 Aug 17 04:55:23 PM PDT 24 Aug 17 04:55:35 PM PDT 24 558131912 ps
T342 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3432068420 Aug 17 04:55:25 PM PDT 24 Aug 17 04:55:35 PM PDT 24 179831624 ps
T343 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2146163538 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:30 PM PDT 24 4098119254 ps
T344 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1647726606 Aug 17 04:55:37 PM PDT 24 Aug 17 04:55:55 PM PDT 24 971943893 ps
T345 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3798999768 Aug 17 04:55:25 PM PDT 24 Aug 17 04:55:37 PM PDT 24 271790578 ps
T346 /workspace/coverage/default/34.rom_ctrl_alert_test.1161436352 Aug 17 04:55:52 PM PDT 24 Aug 17 04:56:00 PM PDT 24 345583995 ps
T347 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2656855364 Aug 17 04:55:27 PM PDT 24 Aug 17 04:55:38 PM PDT 24 1067661393 ps
T348 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.659411993 Aug 17 04:55:23 PM PDT 24 Aug 17 04:57:52 PM PDT 24 2157926611 ps
T349 /workspace/coverage/default/13.rom_ctrl_stress_all.3453111620 Aug 17 04:55:29 PM PDT 24 Aug 17 04:55:40 PM PDT 24 853498522 ps
T350 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2590854687 Aug 17 04:55:47 PM PDT 24 Aug 17 05:01:25 PM PDT 24 11535703089 ps
T351 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.583651955 Aug 17 04:55:48 PM PDT 24 Aug 17 05:00:36 PM PDT 24 5787053918 ps
T352 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4090441175 Aug 17 04:55:51 PM PDT 24 Aug 17 04:57:57 PM PDT 24 1772008515 ps
T353 /workspace/coverage/default/18.rom_ctrl_stress_all.2282203763 Aug 17 04:55:29 PM PDT 24 Aug 17 04:55:45 PM PDT 24 291818590 ps
T354 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.905140885 Aug 17 04:55:29 PM PDT 24 Aug 17 04:55:39 PM PDT 24 699089157 ps
T355 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2420063460 Aug 17 04:56:09 PM PDT 24 Aug 17 04:57:27 PM PDT 24 1776597153 ps
T356 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3167853671 Aug 17 04:55:52 PM PDT 24 Aug 17 04:56:03 PM PDT 24 1023903242 ps
T357 /workspace/coverage/default/10.rom_ctrl_alert_test.527378376 Aug 17 04:55:19 PM PDT 24 Aug 17 04:55:29 PM PDT 24 605399319 ps
T48 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2861434478 Aug 17 04:55:05 PM PDT 24 Aug 17 04:56:25 PM PDT 24 1460500535 ps
T51 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2332618382 Aug 17 04:54:44 PM PDT 24 Aug 17 04:54:59 PM PDT 24 700400873 ps
T52 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4169693437 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:01 PM PDT 24 180631487 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1219637092 Aug 17 04:55:19 PM PDT 24 Aug 17 04:55:29 PM PDT 24 250618744 ps
T358 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.851195113 Aug 17 04:55:09 PM PDT 24 Aug 17 04:55:18 PM PDT 24 254749530 ps
T359 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2414535281 Aug 17 04:54:47 PM PDT 24 Aug 17 04:54:55 PM PDT 24 3294407167 ps
T56 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1066136701 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:21 PM PDT 24 592559098 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.901069882 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:02 PM PDT 24 513408662 ps
T49 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3858651430 Aug 17 04:55:17 PM PDT 24 Aug 17 04:56:38 PM PDT 24 5358196098 ps
T57 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3288411331 Aug 17 04:54:51 PM PDT 24 Aug 17 04:55:04 PM PDT 24 1036133874 ps
T50 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3251488283 Aug 17 04:55:09 PM PDT 24 Aug 17 04:57:43 PM PDT 24 436372567 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2685807625 Aug 17 04:55:16 PM PDT 24 Aug 17 04:55:28 PM PDT 24 176416136 ps
T58 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1225798999 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:26 PM PDT 24 1025479177 ps
T59 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.600814424 Aug 17 04:54:48 PM PDT 24 Aug 17 04:55:30 PM PDT 24 1080689364 ps
T60 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4203643684 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:55 PM PDT 24 5253989465 ps
T96 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3082634786 Aug 17 04:55:16 PM PDT 24 Aug 17 04:56:41 PM PDT 24 23777328551 ps
T94 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3859769941 Aug 17 04:55:22 PM PDT 24 Aug 17 04:55:35 PM PDT 24 270374973 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3518422908 Aug 17 04:55:00 PM PDT 24 Aug 17 04:55:09 PM PDT 24 336608256 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3606592268 Aug 17 04:55:11 PM PDT 24 Aug 17 04:56:04 PM PDT 24 1064744796 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.826103966 Aug 17 04:55:15 PM PDT 24 Aug 17 04:56:34 PM PDT 24 234304461 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.895566824 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:03 PM PDT 24 992469264 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4199437071 Aug 17 04:54:49 PM PDT 24 Aug 17 04:54:57 PM PDT 24 167500623 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2692631440 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:00 PM PDT 24 1378758009 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2741922543 Aug 17 04:55:01 PM PDT 24 Aug 17 04:55:13 PM PDT 24 675777794 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.639956809 Aug 17 04:54:58 PM PDT 24 Aug 17 04:55:06 PM PDT 24 174717337 ps
T103 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4023142886 Aug 17 04:55:08 PM PDT 24 Aug 17 04:56:31 PM PDT 24 5225029849 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3389610451 Aug 17 04:54:50 PM PDT 24 Aug 17 04:55:06 PM PDT 24 1047508749 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2500749926 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:13 PM PDT 24 214258841 ps
T64 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2846212530 Aug 17 04:55:07 PM PDT 24 Aug 17 04:56:09 PM PDT 24 1594926468 ps
T73 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4220036176 Aug 17 04:55:11 PM PDT 24 Aug 17 04:55:19 PM PDT 24 174476417 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1828940073 Aug 17 04:55:14 PM PDT 24 Aug 17 04:57:45 PM PDT 24 376240936 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1877387667 Aug 17 04:54:49 PM PDT 24 Aug 17 04:54:57 PM PDT 24 694416378 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1518155121 Aug 17 04:55:05 PM PDT 24 Aug 17 04:56:28 PM PDT 24 2520270233 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3413490260 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:08 PM PDT 24 477461055 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3321094257 Aug 17 04:54:57 PM PDT 24 Aug 17 04:55:06 PM PDT 24 2246249712 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2202037942 Aug 17 04:54:55 PM PDT 24 Aug 17 04:55:04 PM PDT 24 916529012 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3160097118 Aug 17 04:54:51 PM PDT 24 Aug 17 04:55:01 PM PDT 24 1259926168 ps
T372 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3358263249 Aug 17 04:55:09 PM PDT 24 Aug 17 04:55:19 PM PDT 24 256585939 ps
T105 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2661658413 Aug 17 04:55:12 PM PDT 24 Aug 17 04:56:33 PM PDT 24 283445060 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3828084153 Aug 17 04:55:14 PM PDT 24 Aug 17 04:55:55 PM PDT 24 5069490159 ps
T75 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4141281835 Aug 17 04:55:19 PM PDT 24 Aug 17 04:55:27 PM PDT 24 662816116 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2072151307 Aug 17 04:54:49 PM PDT 24 Aug 17 04:54:59 PM PDT 24 260243756 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1071329962 Aug 17 04:55:01 PM PDT 24 Aug 17 04:55:43 PM PDT 24 5969004375 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2050090642 Aug 17 04:54:55 PM PDT 24 Aug 17 04:55:04 PM PDT 24 1552496239 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1959588262 Aug 17 04:55:16 PM PDT 24 Aug 17 04:57:51 PM PDT 24 3058860238 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1363007988 Aug 17 04:55:08 PM PDT 24 Aug 17 04:55:17 PM PDT 24 601650549 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.364918772 Aug 17 04:54:44 PM PDT 24 Aug 17 04:56:07 PM PDT 24 24721283330 ps
T377 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1092469159 Aug 17 04:55:03 PM PDT 24 Aug 17 04:55:15 PM PDT 24 603398779 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3596939661 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:10 PM PDT 24 348218991 ps
T379 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3663151126 Aug 17 04:55:21 PM PDT 24 Aug 17 04:55:30 PM PDT 24 190521030 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.272731044 Aug 17 04:55:02 PM PDT 24 Aug 17 04:55:10 PM PDT 24 170666466 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4130434760 Aug 17 04:55:11 PM PDT 24 Aug 17 04:56:05 PM PDT 24 2465269553 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2732304852 Aug 17 04:54:57 PM PDT 24 Aug 17 04:55:34 PM PDT 24 2071629885 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2413180010 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:01 PM PDT 24 947418631 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2995209369 Aug 17 04:55:09 PM PDT 24 Aug 17 04:55:17 PM PDT 24 167905528 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1612076216 Aug 17 04:55:14 PM PDT 24 Aug 17 04:55:25 PM PDT 24 174349229 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4136222900 Aug 17 04:54:59 PM PDT 24 Aug 17 04:55:09 PM PDT 24 1061127904 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.476092895 Aug 17 04:54:54 PM PDT 24 Aug 17 04:55:05 PM PDT 24 639141075 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.920644846 Aug 17 04:54:50 PM PDT 24 Aug 17 04:57:25 PM PDT 24 1231548325 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2483409690 Aug 17 04:55:00 PM PDT 24 Aug 17 04:55:10 PM PDT 24 1088155457 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1153178146 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:01 PM PDT 24 173297701 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4175514102 Aug 17 04:54:44 PM PDT 24 Aug 17 04:54:57 PM PDT 24 254132772 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3673402251 Aug 17 04:55:12 PM PDT 24 Aug 17 04:57:44 PM PDT 24 323670409 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1484266912 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:41 PM PDT 24 2455005972 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1284063041 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:00 PM PDT 24 2361632158 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3883980691 Aug 17 04:54:54 PM PDT 24 Aug 17 04:55:06 PM PDT 24 661395998 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2433228770 Aug 17 04:54:48 PM PDT 24 Aug 17 04:54:56 PM PDT 24 688051570 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1256760269 Aug 17 04:54:55 PM PDT 24 Aug 17 04:55:05 PM PDT 24 978091065 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1230777499 Aug 17 04:55:16 PM PDT 24 Aug 17 04:55:27 PM PDT 24 174611786 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3565650831 Aug 17 04:54:57 PM PDT 24 Aug 17 04:55:06 PM PDT 24 413109299 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3584455909 Aug 17 04:55:14 PM PDT 24 Aug 17 04:55:24 PM PDT 24 254066700 ps
T78 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3705480549 Aug 17 04:55:08 PM PDT 24 Aug 17 04:56:11 PM PDT 24 16850624800 ps
T395 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3450492240 Aug 17 04:55:29 PM PDT 24 Aug 17 04:55:38 PM PDT 24 1120663811 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3545042323 Aug 17 04:55:14 PM PDT 24 Aug 17 04:55:26 PM PDT 24 752346200 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.475257261 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:01 PM PDT 24 249623521 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.398774143 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:03 PM PDT 24 1452977317 ps
T398 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1807631553 Aug 17 04:55:17 PM PDT 24 Aug 17 04:55:25 PM PDT 24 244989804 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.134186596 Aug 17 04:55:09 PM PDT 24 Aug 17 04:55:20 PM PDT 24 178033754 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1976474042 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:22 PM PDT 24 1107931616 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3499480407 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:21 PM PDT 24 255369295 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1044139942 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:48 PM PDT 24 2855171051 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1875409782 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:30 PM PDT 24 700840727 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2304786007 Aug 17 04:55:18 PM PDT 24 Aug 17 04:55:31 PM PDT 24 366544945 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1960550953 Aug 17 04:55:20 PM PDT 24 Aug 17 04:55:31 PM PDT 24 345816573 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2796460428 Aug 17 04:55:04 PM PDT 24 Aug 17 04:55:17 PM PDT 24 249510741 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2397219354 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:14 PM PDT 24 176359079 ps
T115 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3090224321 Aug 17 04:55:00 PM PDT 24 Aug 17 04:56:22 PM PDT 24 341846400 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2295230402 Aug 17 04:55:13 PM PDT 24 Aug 17 04:56:33 PM PDT 24 1272197644 ps
T408 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4010311643 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:20 PM PDT 24 2523385631 ps
T409 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1353536455 Aug 17 04:54:53 PM PDT 24 Aug 17 04:56:19 PM PDT 24 4190104386 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2711355731 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:25 PM PDT 24 518079801 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1223523784 Aug 17 04:54:52 PM PDT 24 Aug 17 04:55:02 PM PDT 24 250561916 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1492107351 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:23 PM PDT 24 972079008 ps
T413 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4264440120 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:54 PM PDT 24 4420233198 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1425641840 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:40 PM PDT 24 706708726 ps
T415 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3311867158 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:15 PM PDT 24 247941883 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3907593782 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:03 PM PDT 24 955404667 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1581437167 Aug 17 04:54:51 PM PDT 24 Aug 17 04:55:55 PM PDT 24 11662985431 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1233914729 Aug 17 04:55:04 PM PDT 24 Aug 17 04:55:40 PM PDT 24 2867830673 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4015265948 Aug 17 04:54:53 PM PDT 24 Aug 17 04:55:04 PM PDT 24 487470089 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.885154088 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:51 PM PDT 24 3132405621 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2139259132 Aug 17 04:55:14 PM PDT 24 Aug 17 04:55:22 PM PDT 24 660877115 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.193845956 Aug 17 04:55:11 PM PDT 24 Aug 17 04:55:24 PM PDT 24 1039707024 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4258802751 Aug 17 04:54:54 PM PDT 24 Aug 17 04:55:03 PM PDT 24 4091582901 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.907034962 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:15 PM PDT 24 974700953 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1821198264 Aug 17 04:55:04 PM PDT 24 Aug 17 04:55:11 PM PDT 24 692526354 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4220905659 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:15 PM PDT 24 261224229 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3330114640 Aug 17 04:54:59 PM PDT 24 Aug 17 04:55:07 PM PDT 24 438144240 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2679475911 Aug 17 04:55:11 PM PDT 24 Aug 17 04:55:19 PM PDT 24 211447093 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.507958352 Aug 17 04:55:20 PM PDT 24 Aug 17 04:55:28 PM PDT 24 333673941 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.651776649 Aug 17 04:54:47 PM PDT 24 Aug 17 04:56:11 PM PDT 24 1292556281 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2855512528 Aug 17 04:55:04 PM PDT 24 Aug 17 04:55:16 PM PDT 24 661105407 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3012908346 Aug 17 04:55:10 PM PDT 24 Aug 17 04:55:18 PM PDT 24 167962009 ps
T433 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2157189644 Aug 17 04:55:11 PM PDT 24 Aug 17 04:55:24 PM PDT 24 988509599 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.820875183 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:15 PM PDT 24 270686602 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3281812728 Aug 17 04:54:55 PM PDT 24 Aug 17 04:55:07 PM PDT 24 339187571 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2113974566 Aug 17 04:54:50 PM PDT 24 Aug 17 04:55:00 PM PDT 24 614427332 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.368156873 Aug 17 04:54:59 PM PDT 24 Aug 17 04:55:12 PM PDT 24 259910231 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.652578728 Aug 17 04:55:11 PM PDT 24 Aug 17 04:55:25 PM PDT 24 3953988095 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2117983478 Aug 17 04:54:47 PM PDT 24 Aug 17 04:55:01 PM PDT 24 1179153034 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2997555189 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:15 PM PDT 24 993653837 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3779697860 Aug 17 04:54:51 PM PDT 24 Aug 17 04:55:00 PM PDT 24 253979647 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1829650317 Aug 17 04:55:05 PM PDT 24 Aug 17 04:56:07 PM PDT 24 6351212248 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.320806467 Aug 17 04:55:18 PM PDT 24 Aug 17 04:55:28 PM PDT 24 269145770 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2451597866 Aug 17 04:54:50 PM PDT 24 Aug 17 04:55:00 PM PDT 24 1036205152 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4237245748 Aug 17 04:55:06 PM PDT 24 Aug 17 04:55:18 PM PDT 24 700414519 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1072332591 Aug 17 04:54:50 PM PDT 24 Aug 17 04:54:58 PM PDT 24 242195590 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1056685312 Aug 17 04:55:01 PM PDT 24 Aug 17 04:57:34 PM PDT 24 1331057715 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4099896600 Aug 17 04:55:12 PM PDT 24 Aug 17 04:55:20 PM PDT 24 689883730 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3351148497 Aug 17 04:54:58 PM PDT 24 Aug 17 04:55:11 PM PDT 24 4070457600 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2956874347 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:25 PM PDT 24 521407145 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2346424304 Aug 17 04:55:12 PM PDT 24 Aug 17 04:56:34 PM PDT 24 352549629 ps
T450 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.70493133 Aug 17 04:55:18 PM PDT 24 Aug 17 04:55:27 PM PDT 24 711944674 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3553869465 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:25 PM PDT 24 652330641 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3650292779 Aug 17 04:55:15 PM PDT 24 Aug 17 04:56:36 PM PDT 24 1409867799 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1956616219 Aug 17 04:54:59 PM PDT 24 Aug 17 04:55:12 PM PDT 24 1034485585 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3961132147 Aug 17 04:55:20 PM PDT 24 Aug 17 04:55:37 PM PDT 24 4111933919 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3047918273 Aug 17 04:55:21 PM PDT 24 Aug 17 04:55:31 PM PDT 24 259923158 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.649541058 Aug 17 04:54:54 PM PDT 24 Aug 17 04:55:08 PM PDT 24 296927149 ps
T456 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3681537544 Aug 17 04:55:10 PM PDT 24 Aug 17 04:55:19 PM PDT 24 717341448 ps
T114 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.986654405 Aug 17 04:55:17 PM PDT 24 Aug 17 04:56:37 PM PDT 24 976709404 ps
T457 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1244431496 Aug 17 04:55:05 PM PDT 24 Aug 17 04:55:17 PM PDT 24 507436327 ps
T116 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1066247182 Aug 17 04:54:59 PM PDT 24 Aug 17 04:57:30 PM PDT 24 1221434953 ps
T458 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2589628420 Aug 17 04:55:15 PM PDT 24 Aug 17 04:55:22 PM PDT 24 1035089268 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2135582203 Aug 17 04:54:51 PM PDT 24 Aug 17 04:55:00 PM PDT 24 296715330 ps

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.251863059
Short name T7
Test name
Test status
Simulation time 15666679972 ps
CPU time 197.04 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:58:44 PM PDT 24
Peak memory 227668 kb
Host smart-0be03538-1fdd-4fda-8da3-e01911c87399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251863059 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.251863059
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.791128739
Short name T9
Test name
Test status
Simulation time 7770095383 ps
CPU time 330.76 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 05:01:17 PM PDT 24
Peak memory 240448 kb
Host smart-d83ee61f-e4d9-4248-bd7b-ade7abc71562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791128739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.791128739
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3778268949
Short name T41
Test name
Test status
Simulation time 3423115272 ps
CPU time 155.86 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:58:04 PM PDT 24
Peak memory 219280 kb
Host smart-f7517336-e464-4f0f-a8d3-d5fc2ad34c0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778268949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3778268949
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2861434478
Short name T48
Test name
Test status
Simulation time 1460500535 ps
CPU time 79.6 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 214516 kb
Host smart-b5df7c68-9fd6-4eca-8ad2-9dbd7a08fe0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861434478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2861434478
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3012328033
Short name T65
Test name
Test status
Simulation time 518437566 ps
CPU time 29.67 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 219100 kb
Host smart-873c9c15-3c3b-457e-9af0-7e380148b379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012328033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3012328033
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4203643684
Short name T60
Test name
Test status
Simulation time 5253989465 ps
CPU time 63.17 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 216652 kb
Host smart-0c5e8995-8659-4ef0-8935-11ff4be26a1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203643684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4203643684
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4201522633
Short name T17
Test name
Test status
Simulation time 1462677759 ps
CPU time 119.45 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:57:18 PM PDT 24
Peak memory 238788 kb
Host smart-db393338-92d4-47ef-966c-1dcc1e819eb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201522633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4201522633
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3673402251
Short name T109
Test name
Test status
Simulation time 323670409 ps
CPU time 151.6 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:57:44 PM PDT 24
Peak memory 214752 kb
Host smart-627f1ba3-2578-459e-8781-1fa04fa9c51e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673402251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3673402251
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3380891557
Short name T21
Test name
Test status
Simulation time 8563761367 ps
CPU time 29.43 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:56:16 PM PDT 24
Peak memory 219432 kb
Host smart-889c354f-0d77-47d6-bd95-6d8d297f46d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380891557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3380891557
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4135569952
Short name T27
Test name
Test status
Simulation time 4072494995 ps
CPU time 14.25 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:42 PM PDT 24
Peak memory 218420 kb
Host smart-d80ad814-d1b6-4423-9175-4b1d9b0acaac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135569952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4135569952
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1056685312
Short name T110
Test name
Test status
Simulation time 1331057715 ps
CPU time 152.82 seconds
Started Aug 17 04:55:01 PM PDT 24
Finished Aug 17 04:57:34 PM PDT 24
Peak memory 214904 kb
Host smart-6185b9c1-c94c-4617-ae51-0a195a7661df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056685312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1056685312
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2873545436
Short name T45
Test name
Test status
Simulation time 4105585802 ps
CPU time 103.81 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:57:16 PM PDT 24
Peak memory 226012 kb
Host smart-ed573d4f-0b0b-49e8-810b-3e059d56d69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873545436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2873545436
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1779840376
Short name T194
Test name
Test status
Simulation time 332419295 ps
CPU time 18.12 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 04:55:51 PM PDT 24
Peak memory 218524 kb
Host smart-d87045ab-c371-4fe4-8274-cee32c8a2c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779840376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1779840376
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2756213721
Short name T42
Test name
Test status
Simulation time 497363069 ps
CPU time 21.47 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 218512 kb
Host smart-fc13af3c-4188-45ed-a3fe-23f52d4a0aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756213721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2756213721
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3251488283
Short name T50
Test name
Test status
Simulation time 436372567 ps
CPU time 153.88 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:57:43 PM PDT 24
Peak memory 219528 kb
Host smart-e36e354d-ee6b-4ca0-8057-226853071d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251488283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3251488283
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2846212530
Short name T64
Test name
Test status
Simulation time 1594926468 ps
CPU time 62.82 seconds
Started Aug 17 04:55:07 PM PDT 24
Finished Aug 17 04:56:09 PM PDT 24
Peak memory 214832 kb
Host smart-6cca717b-c168-416d-9a6a-ad3bfbd02d53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846212530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2846212530
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.986654405
Short name T114
Test name
Test status
Simulation time 976709404 ps
CPU time 80.71 seconds
Started Aug 17 04:55:17 PM PDT 24
Finished Aug 17 04:56:37 PM PDT 24
Peak memory 213500 kb
Host smart-4a18646f-04aa-412a-8d80-777916a6ad13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986654405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.986654405
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1162130451
Short name T84
Test name
Test status
Simulation time 702986485 ps
CPU time 10.23 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 218524 kb
Host smart-39a57e1a-52b1-4c32-8b76-d1792d29ac43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162130451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1162130451
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3779697860
Short name T441
Test name
Test status
Simulation time 253979647 ps
CPU time 9.51 seconds
Started Aug 17 04:54:51 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 211540 kb
Host smart-189b1498-7ee4-4e52-95e0-6c25951062c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779697860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3779697860
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2202037942
Short name T370
Test name
Test status
Simulation time 916529012 ps
CPU time 8.31 seconds
Started Aug 17 04:54:55 PM PDT 24
Finished Aug 17 04:55:04 PM PDT 24
Peak memory 211544 kb
Host smart-63bc6019-f708-402a-a30b-e177388f5c75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202037942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2202037942
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4175514102
Short name T81
Test name
Test status
Simulation time 254132772 ps
CPU time 13.03 seconds
Started Aug 17 04:54:44 PM PDT 24
Finished Aug 17 04:54:57 PM PDT 24
Peak memory 211444 kb
Host smart-e28a09eb-24ed-4f79-bf21-3daab97b5855
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175514102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4175514102
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.901069882
Short name T360
Test name
Test status
Simulation time 513408662 ps
CPU time 9.76 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:02 PM PDT 24
Peak memory 219548 kb
Host smart-91fdda93-7d9b-4f99-85a2-1cd25a7c9115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901069882 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.901069882
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2050090642
Short name T375
Test name
Test status
Simulation time 1552496239 ps
CPU time 9.63 seconds
Started Aug 17 04:54:55 PM PDT 24
Finished Aug 17 04:55:04 PM PDT 24
Peak memory 211820 kb
Host smart-b273d441-00f7-4f88-beb3-a1dcdfdf09c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050090642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2050090642
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4099896600
Short name T446
Test name
Test status
Simulation time 689883730 ps
CPU time 7.82 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:20 PM PDT 24
Peak memory 211232 kb
Host smart-aa71cbf3-1c83-4b6d-ab80-a8a3c628c4f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099896600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4099896600
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2692631440
Short name T365
Test name
Test status
Simulation time 1378758009 ps
CPU time 7.64 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 211252 kb
Host smart-e1dbd794-7d2f-48c8-aa99-c540d6411890
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692631440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2692631440
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.364918772
Short name T76
Test name
Test status
Simulation time 24721283330 ps
CPU time 82.83 seconds
Started Aug 17 04:54:44 PM PDT 24
Finished Aug 17 04:56:07 PM PDT 24
Peak memory 216676 kb
Host smart-9641dd3a-d5f8-46ad-9bbe-6f3216ff32b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364918772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.364918772
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3565650831
Short name T393
Test name
Test status
Simulation time 413109299 ps
CPU time 9.33 seconds
Started Aug 17 04:54:57 PM PDT 24
Finished Aug 17 04:55:06 PM PDT 24
Peak memory 211844 kb
Host smart-9d5b97c5-913b-4e36-a1da-7e804f30a2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565650831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3565650831
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.649541058
Short name T455
Test name
Test status
Simulation time 296927149 ps
CPU time 14.1 seconds
Started Aug 17 04:54:54 PM PDT 24
Finished Aug 17 04:55:08 PM PDT 24
Peak memory 218188 kb
Host smart-16dc2cc7-01e6-4d76-87c1-ee4c3ff46413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649541058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.649541058
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2135582203
Short name T459
Test name
Test status
Simulation time 296715330 ps
CPU time 9.28 seconds
Started Aug 17 04:54:51 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 211364 kb
Host smart-2b719891-78bb-4920-bfaa-c0fa28c82d66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135582203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2135582203
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.895566824
Short name T363
Test name
Test status
Simulation time 992469264 ps
CPU time 9.57 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:03 PM PDT 24
Peak memory 211328 kb
Host smart-7e8c1053-248f-45ba-9deb-9372b15bf67b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895566824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.895566824
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3389610451
Short name T367
Test name
Test status
Simulation time 1047508749 ps
CPU time 16.65 seconds
Started Aug 17 04:54:50 PM PDT 24
Finished Aug 17 04:55:06 PM PDT 24
Peak memory 212840 kb
Host smart-2637107f-953f-45c9-bbf0-bd4826705fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389610451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3389610451
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3160097118
Short name T371
Test name
Test status
Simulation time 1259926168 ps
CPU time 9.96 seconds
Started Aug 17 04:54:51 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 219628 kb
Host smart-ec311c3e-8924-4600-afc3-59099deb3116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160097118 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3160097118
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1223523784
Short name T411
Test name
Test status
Simulation time 250561916 ps
CPU time 9.46 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:02 PM PDT 24
Peak memory 211580 kb
Host smart-9d85cb6e-bc96-41ce-b2bc-08cbe11d9aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223523784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1223523784
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2414535281
Short name T359
Test name
Test status
Simulation time 3294407167 ps
CPU time 7.71 seconds
Started Aug 17 04:54:47 PM PDT 24
Finished Aug 17 04:54:55 PM PDT 24
Peak memory 211424 kb
Host smart-437d249e-25b3-484e-9cc2-d9456caa7502
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414535281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2414535281
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1284063041
Short name T388
Test name
Test status
Simulation time 2361632158 ps
CPU time 7.7 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 211368 kb
Host smart-796a507b-5e50-48a9-8620-fec004c095f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284063041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1284063041
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.600814424
Short name T59
Test name
Test status
Simulation time 1080689364 ps
CPU time 41.98 seconds
Started Aug 17 04:54:48 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 214556 kb
Host smart-e70a6d9d-85fc-4029-87fb-ff7670d9153d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600814424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.600814424
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3321094257
Short name T95
Test name
Test status
Simulation time 2246249712 ps
CPU time 9.54 seconds
Started Aug 17 04:54:57 PM PDT 24
Finished Aug 17 04:55:06 PM PDT 24
Peak memory 212184 kb
Host smart-d8a0ab3d-45c3-4d1e-bb87-29f4d2f8dc80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321094257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3321094257
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3281812728
Short name T435
Test name
Test status
Simulation time 339187571 ps
CPU time 11.71 seconds
Started Aug 17 04:54:55 PM PDT 24
Finished Aug 17 04:55:07 PM PDT 24
Peak memory 216976 kb
Host smart-e2fa0ff7-baec-4fb1-b6db-1303e3a71f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281812728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3281812728
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3090224321
Short name T115
Test name
Test status
Simulation time 341846400 ps
CPU time 81.87 seconds
Started Aug 17 04:55:00 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 219564 kb
Host smart-6f55878c-8ba3-4d49-b117-b14b41fa5262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090224321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3090224321
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4010311643
Short name T408
Test name
Test status
Simulation time 2523385631 ps
CPU time 8.43 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:20 PM PDT 24
Peak memory 219692 kb
Host smart-a707d3e8-37c2-4bfe-8c94-902ae5322bad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010311643 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4010311643
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4220036176
Short name T73
Test name
Test status
Simulation time 174476417 ps
CPU time 8.18 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:19 PM PDT 24
Peak memory 211576 kb
Host smart-5227a192-98a9-420a-bc11-9b0df20a2a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220036176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4220036176
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4130434760
Short name T77
Test name
Test status
Simulation time 2465269553 ps
CPU time 53.97 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:56:05 PM PDT 24
Peak memory 214648 kb
Host smart-37013f29-13a5-4d7f-864d-4abc3a6b6a0f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130434760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4130434760
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3358263249
Short name T372
Test name
Test status
Simulation time 256585939 ps
CPU time 9.83 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:55:19 PM PDT 24
Peak memory 211812 kb
Host smart-99179bc0-eacf-495f-9aa9-bd19fc728c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358263249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3358263249
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1956616219
Short name T452
Test name
Test status
Simulation time 1034485585 ps
CPU time 13.82 seconds
Started Aug 17 04:54:59 PM PDT 24
Finished Aug 17 04:55:12 PM PDT 24
Peak memory 218416 kb
Host smart-936c97a6-0e30-487b-8de8-180dc89a1846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956616219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1956616219
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1828940073
Short name T106
Test name
Test status
Simulation time 376240936 ps
CPU time 150.94 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:57:45 PM PDT 24
Peak memory 219544 kb
Host smart-601c4863-034e-46fe-9ba8-ba0a708856b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828940073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1828940073
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3681537544
Short name T456
Test name
Test status
Simulation time 717341448 ps
CPU time 8.76 seconds
Started Aug 17 04:55:10 PM PDT 24
Finished Aug 17 04:55:19 PM PDT 24
Peak memory 218092 kb
Host smart-e7e99fc4-b4ef-43e5-95c4-f79dd5e03b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681537544 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3681537544
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2139259132
Short name T421
Test name
Test status
Simulation time 660877115 ps
CPU time 7.9 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:55:22 PM PDT 24
Peak memory 211604 kb
Host smart-7fc052c3-d7e5-4338-b2f0-49e8aba8aed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139259132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2139259132
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1829650317
Short name T79
Test name
Test status
Simulation time 6351212248 ps
CPU time 61.59 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:56:07 PM PDT 24
Peak memory 216636 kb
Host smart-62b26e42-448e-4bcc-bfe5-546f34e31f8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829650317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1829650317
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3311867158
Short name T415
Test name
Test status
Simulation time 247941883 ps
CPU time 9.52 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 211436 kb
Host smart-904738fb-d037-46f8-b5ee-5131ada80026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311867158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3311867158
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2157189644
Short name T433
Test name
Test status
Simulation time 988509599 ps
CPU time 13.02 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:24 PM PDT 24
Peak memory 219392 kb
Host smart-e8b96e74-a9f4-413a-88d1-d944db71b411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157189644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2157189644
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4023142886
Short name T103
Test name
Test status
Simulation time 5225029849 ps
CPU time 82.55 seconds
Started Aug 17 04:55:08 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 213712 kb
Host smart-1a1adfc4-2da8-4057-82f7-deec728d2645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023142886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4023142886
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.70493133
Short name T450
Test name
Test status
Simulation time 711944674 ps
CPU time 8.4 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:55:27 PM PDT 24
Peak memory 217108 kb
Host smart-e2a50327-0bd4-4b9e-b4d0-294f69dc3a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70493133 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.70493133
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4141281835
Short name T75
Test name
Test status
Simulation time 662816116 ps
CPU time 7.7 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:55:27 PM PDT 24
Peak memory 211784 kb
Host smart-b0351214-e5fe-4014-b1a5-f22e48f75a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141281835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4141281835
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1425641840
Short name T414
Test name
Test status
Simulation time 706708726 ps
CPU time 35.4 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 214432 kb
Host smart-4cf52f73-eac4-4449-b24c-a6a2665f8607
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425641840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1425641840
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2995209369
Short name T382
Test name
Test status
Simulation time 167905528 ps
CPU time 8.1 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:55:17 PM PDT 24
Peak memory 212180 kb
Host smart-b1a7f038-8ce9-45a8-bf09-66e5c8acae9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995209369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2995209369
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1244431496
Short name T457
Test name
Test status
Simulation time 507436327 ps
CPU time 11.59 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:17 PM PDT 24
Peak memory 217664 kb
Host smart-ca8c4688-618e-47ee-911a-10929911e13d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244431496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1244431496
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.820875183
Short name T434
Test name
Test status
Simulation time 270686602 ps
CPU time 10.29 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 219556 kb
Host smart-524ee214-f375-432f-b7c5-d75b5de40ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820875183 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.820875183
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.652578728
Short name T438
Test name
Test status
Simulation time 3953988095 ps
CPU time 13.08 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 211524 kb
Host smart-9264dd79-aca6-457a-8b5c-e9d7b8bd52a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652578728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.652578728
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.193845956
Short name T422
Test name
Test status
Simulation time 1039707024 ps
CPU time 13.05 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:24 PM PDT 24
Peak memory 213264 kb
Host smart-3d3238ca-a4a1-48f5-b68e-f2f6417ab460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193845956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.193845956
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2685807625
Short name T361
Test name
Test status
Simulation time 176416136 ps
CPU time 11.51 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:28 PM PDT 24
Peak memory 218160 kb
Host smart-a7144521-eb4a-4862-8e31-2a7a6d3aaa61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685807625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2685807625
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2711355731
Short name T410
Test name
Test status
Simulation time 518079801 ps
CPU time 9.74 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 219600 kb
Host smart-c56072b0-774c-4abb-9dc7-3eb244ba0806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711355731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2711355731
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2589628420
Short name T458
Test name
Test status
Simulation time 1035089268 ps
CPU time 7.63 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:22 PM PDT 24
Peak memory 211704 kb
Host smart-74b1d8ea-5772-47c6-a3a4-354b4dd31af2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589628420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2589628420
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4264440120
Short name T413
Test name
Test status
Simulation time 4420233198 ps
CPU time 41.69 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 215604 kb
Host smart-2cdcedb0-4b93-49d2-8027-3138ed59d5e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264440120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4264440120
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1492107351
Short name T412
Test name
Test status
Simulation time 972079008 ps
CPU time 8.01 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:23 PM PDT 24
Peak memory 211692 kb
Host smart-ef1abdc0-2487-4814-96d4-9ac9a9ede21e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492107351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1492107351
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1960550953
Short name T405
Test name
Test status
Simulation time 345816573 ps
CPU time 11.46 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:31 PM PDT 24
Peak memory 218020 kb
Host smart-a0bd7c49-4359-4e2c-a519-d0cc8d5c04d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960550953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1960550953
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.907034962
Short name T424
Test name
Test status
Simulation time 974700953 ps
CPU time 9.86 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 215988 kb
Host smart-ae849e54-31fb-4062-9d93-5ebf88bff9d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907034962 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.907034962
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1807631553
Short name T398
Test name
Test status
Simulation time 244989804 ps
CPU time 7.96 seconds
Started Aug 17 04:55:17 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 211792 kb
Host smart-44842461-3ba4-45b0-b59c-05edcabe7ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807631553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1807631553
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3828084153
Short name T74
Test name
Test status
Simulation time 5069490159 ps
CPU time 40.91 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 214580 kb
Host smart-2e4425c5-0f1e-4d92-865e-e4225d5683dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828084153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3828084153
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.507958352
Short name T429
Test name
Test status
Simulation time 333673941 ps
CPU time 8.04 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:28 PM PDT 24
Peak memory 211884 kb
Host smart-9d922e5e-af28-452d-8bc7-10c22f90561f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507958352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.507958352
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3499480407
Short name T401
Test name
Test status
Simulation time 255369295 ps
CPU time 14.67 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:21 PM PDT 24
Peak memory 218136 kb
Host smart-453ccdb9-ff77-4e6f-95ec-0df44396d16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499480407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3499480407
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1518155121
Short name T104
Test name
Test status
Simulation time 2520270233 ps
CPU time 82.34 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:56:28 PM PDT 24
Peak memory 213168 kb
Host smart-d5845a05-9f37-4bae-b8f1-178238c17337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518155121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1518155121
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2956874347
Short name T448
Test name
Test status
Simulation time 521407145 ps
CPU time 9.58 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 219548 kb
Host smart-8ca02d65-48e2-4fe6-8a80-19762022bfb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956874347 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2956874347
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3450492240
Short name T395
Test name
Test status
Simulation time 1120663811 ps
CPU time 9.38 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 211668 kb
Host smart-c12dc673-c813-4ee2-b473-0823d38bf729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450492240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3450492240
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1044139942
Short name T402
Test name
Test status
Simulation time 2855171051 ps
CPU time 35.86 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:48 PM PDT 24
Peak memory 214548 kb
Host smart-ab4fa088-68e5-4b76-aee3-03a8e6de0066
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044139942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1044139942
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2679475911
Short name T428
Test name
Test status
Simulation time 211447093 ps
CPU time 8.15 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:19 PM PDT 24
Peak memory 212180 kb
Host smart-dd3f6087-0f0d-4f1f-8314-7f97ab3f66c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679475911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2679475911
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1612076216
Short name T383
Test name
Test status
Simulation time 174349229 ps
CPU time 10.91 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 218020 kb
Host smart-20c2c1ea-0860-4128-8a6d-3f88b7925d36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612076216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1612076216
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1959588262
Short name T111
Test name
Test status
Simulation time 3058860238 ps
CPU time 154.27 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:57:51 PM PDT 24
Peak memory 219676 kb
Host smart-2bf9141d-08bb-4885-9875-ddd96532e71b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959588262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1959588262
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1363007988
Short name T376
Test name
Test status
Simulation time 601650549 ps
CPU time 8.25 seconds
Started Aug 17 04:55:08 PM PDT 24
Finished Aug 17 04:55:17 PM PDT 24
Peak memory 219624 kb
Host smart-2d6868df-57c1-4ec7-9305-2be7f61c8c1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363007988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1363007988
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1225798999
Short name T58
Test name
Test status
Simulation time 1025479177 ps
CPU time 13.13 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:26 PM PDT 24
Peak memory 211380 kb
Host smart-c7aa185b-e1cc-4431-91d2-ff7eef3da64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225798999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1225798999
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3082634786
Short name T96
Test name
Test status
Simulation time 23777328551 ps
CPU time 84.85 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 215560 kb
Host smart-e34c1a53-8fa1-4281-89aa-be8df0d2ab4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082634786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3082634786
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3859769941
Short name T94
Test name
Test status
Simulation time 270374973 ps
CPU time 13.04 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:35 PM PDT 24
Peak memory 212908 kb
Host smart-d9635487-ea6a-4c60-9052-8127748c1417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859769941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3859769941
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2304786007
Short name T404
Test name
Test status
Simulation time 366544945 ps
CPU time 13.18 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:55:31 PM PDT 24
Peak memory 218108 kb
Host smart-672359cc-fe83-4e7f-86ef-6b1947131a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304786007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2304786007
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.826103966
Short name T107
Test name
Test status
Simulation time 234304461 ps
CPU time 78.21 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 214108 kb
Host smart-e06ba978-d6b6-4c6a-91fe-f51808cbeb0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826103966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.826103966
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3663151126
Short name T379
Test name
Test status
Simulation time 190521030 ps
CPU time 8.73 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 219588 kb
Host smart-cd337186-8aa9-4e53-b0f3-bc5f7d1963e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663151126 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3663151126
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3553869465
Short name T451
Test name
Test status
Simulation time 652330641 ps
CPU time 9.29 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:25 PM PDT 24
Peak memory 211804 kb
Host smart-c7d1b9e5-0eb5-45fe-9e64-d68905363929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553869465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3553869465
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3606592268
Short name T61
Test name
Test status
Simulation time 1064744796 ps
CPU time 52.93 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 219580 kb
Host smart-79b9ed91-bfe2-4771-98b6-0894f8db013d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606592268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3606592268
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3961132147
Short name T453
Test name
Test status
Simulation time 4111933919 ps
CPU time 16.95 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 213416 kb
Host smart-c14edc25-7a90-4df3-bb9a-4f100379970d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961132147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3961132147
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3545042323
Short name T396
Test name
Test status
Simulation time 752346200 ps
CPU time 12.01 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:55:26 PM PDT 24
Peak memory 217936 kb
Host smart-cd3b382d-1eb3-45fe-beee-ffcbbf4e2bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545042323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3545042323
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2661658413
Short name T105
Test name
Test status
Simulation time 283445060 ps
CPU time 80.87 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 213464 kb
Host smart-73b4d28e-e49e-4369-ba09-3cb563abd4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661658413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2661658413
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3584455909
Short name T394
Test name
Test status
Simulation time 254066700 ps
CPU time 9.8 seconds
Started Aug 17 04:55:14 PM PDT 24
Finished Aug 17 04:55:24 PM PDT 24
Peak memory 219680 kb
Host smart-f398900f-18ef-4b0f-82b6-b767f9534eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584455909 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3584455909
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3047918273
Short name T454
Test name
Test status
Simulation time 259923158 ps
CPU time 9.23 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:31 PM PDT 24
Peak memory 211640 kb
Host smart-95947458-5c32-45ae-9620-293df7d47ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047918273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3047918273
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.885154088
Short name T420
Test name
Test status
Simulation time 3132405621 ps
CPU time 36.5 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:51 PM PDT 24
Peak memory 214492 kb
Host smart-9a1710f0-c2a5-4899-9acb-7efd5f76b211
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885154088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.885154088
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1219637092
Short name T93
Test name
Test status
Simulation time 250618744 ps
CPU time 9.5 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:55:29 PM PDT 24
Peak memory 211556 kb
Host smart-683cdf4d-420a-474d-9629-48944cbda79c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219637092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1219637092
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1230777499
Short name T392
Test name
Test status
Simulation time 174611786 ps
CPU time 10.82 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:27 PM PDT 24
Peak memory 217768 kb
Host smart-ab757157-479d-410a-ba19-bdfab11903aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230777499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1230777499
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3650292779
Short name T113
Test name
Test status
Simulation time 1409867799 ps
CPU time 80.54 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:56:36 PM PDT 24
Peak memory 213376 kb
Host smart-8ab2747a-d531-4b7a-8db2-7911eb083a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650292779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3650292779
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2413180010
Short name T381
Test name
Test status
Simulation time 947418631 ps
CPU time 9.44 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 211804 kb
Host smart-ba588dfa-2376-41e0-8c5c-f726fb82849d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413180010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2413180010
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.475257261
Short name T397
Test name
Test status
Simulation time 249623521 ps
CPU time 9.3 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 211324 kb
Host smart-45130240-865e-4a2e-a457-5af735f1479c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475257261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.475257261
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2332618382
Short name T51
Test name
Test status
Simulation time 700400873 ps
CPU time 14.74 seconds
Started Aug 17 04:54:44 PM PDT 24
Finished Aug 17 04:54:59 PM PDT 24
Peak memory 212420 kb
Host smart-4530900c-59c7-45ea-85d2-c5019da5efb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332618382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2332618382
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1877387667
Short name T368
Test name
Test status
Simulation time 694416378 ps
CPU time 8.42 seconds
Started Aug 17 04:54:49 PM PDT 24
Finished Aug 17 04:54:57 PM PDT 24
Peak memory 216636 kb
Host smart-ea296ddc-cbf1-48db-aa0a-f86f7bae0fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877387667 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1877387667
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.398774143
Short name T82
Test name
Test status
Simulation time 1452977317 ps
CPU time 9.3 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:03 PM PDT 24
Peak memory 211536 kb
Host smart-cc14fe1e-c443-4152-9191-0884f73b530b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398774143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.398774143
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2433228770
Short name T390
Test name
Test status
Simulation time 688051570 ps
CPU time 7.76 seconds
Started Aug 17 04:54:48 PM PDT 24
Finished Aug 17 04:54:56 PM PDT 24
Peak memory 211348 kb
Host smart-24c5a2c2-80fd-4662-925f-32ceb12b0990
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433228770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2433228770
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2072151307
Short name T373
Test name
Test status
Simulation time 260243756 ps
CPU time 9.32 seconds
Started Aug 17 04:54:49 PM PDT 24
Finished Aug 17 04:54:59 PM PDT 24
Peak memory 211300 kb
Host smart-9deaf8ed-a21d-4a1c-ac04-3ef420223d1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072151307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2072151307
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2732304852
Short name T80
Test name
Test status
Simulation time 2071629885 ps
CPU time 36.22 seconds
Started Aug 17 04:54:57 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 214500 kb
Host smart-231db40f-048a-4100-867d-53b9f74595b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732304852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2732304852
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2117983478
Short name T439
Test name
Test status
Simulation time 1179153034 ps
CPU time 13.19 seconds
Started Aug 17 04:54:47 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 213296 kb
Host smart-8fcc79f0-cc91-44de-877d-f66d9260526b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117983478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2117983478
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.368156873
Short name T437
Test name
Test status
Simulation time 259910231 ps
CPU time 13.35 seconds
Started Aug 17 04:54:59 PM PDT 24
Finished Aug 17 04:55:12 PM PDT 24
Peak memory 218212 kb
Host smart-bf05f8c1-d864-4a5e-8acd-8729d60c04dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368156873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.368156873
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.651776649
Short name T430
Test name
Test status
Simulation time 1292556281 ps
CPU time 83.13 seconds
Started Aug 17 04:54:47 PM PDT 24
Finished Aug 17 04:56:11 PM PDT 24
Peak memory 213444 kb
Host smart-65f82fcf-3558-4daf-8841-06e644560979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651776649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.651776649
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2500749926
Short name T63
Test name
Test status
Simulation time 214258841 ps
CPU time 7.9 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:13 PM PDT 24
Peak memory 211376 kb
Host smart-b54b5f23-7b3e-4db6-9e9a-a9d4f8be1265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500749926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2500749926
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.851195113
Short name T358
Test name
Test status
Simulation time 254749530 ps
CPU time 9.6 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:55:18 PM PDT 24
Peak memory 211420 kb
Host smart-cefcf2aa-3778-46d5-b25c-78be5aa8f1e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851195113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.851195113
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3288411331
Short name T57
Test name
Test status
Simulation time 1036133874 ps
CPU time 12.89 seconds
Started Aug 17 04:54:51 PM PDT 24
Finished Aug 17 04:55:04 PM PDT 24
Peak memory 211584 kb
Host smart-83c8e85a-cb6b-46e6-83ee-16b91c4dd142
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288411331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3288411331
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2483409690
Short name T386
Test name
Test status
Simulation time 1088155457 ps
CPU time 10.16 seconds
Started Aug 17 04:55:00 PM PDT 24
Finished Aug 17 04:55:10 PM PDT 24
Peak memory 219600 kb
Host smart-a03802be-05d4-4bae-b740-e8aaa7df4ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483409690 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2483409690
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.272731044
Short name T380
Test name
Test status
Simulation time 170666466 ps
CPU time 8.1 seconds
Started Aug 17 04:55:02 PM PDT 24
Finished Aug 17 04:55:10 PM PDT 24
Peak memory 211716 kb
Host smart-a9cbcfdf-4999-450d-97a7-5c2a8b1423a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272731044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.272731044
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2397219354
Short name T407
Test name
Test status
Simulation time 176359079 ps
CPU time 7.87 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:14 PM PDT 24
Peak memory 211324 kb
Host smart-82406754-a4aa-485d-a367-743a709e1a01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397219354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2397219354
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4199437071
Short name T364
Test name
Test status
Simulation time 167500623 ps
CPU time 7.81 seconds
Started Aug 17 04:54:49 PM PDT 24
Finished Aug 17 04:54:57 PM PDT 24
Peak memory 211344 kb
Host smart-43ea7eb0-94a6-4295-a93a-c99bba6618ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199437071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4199437071
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1875409782
Short name T403
Test name
Test status
Simulation time 700840727 ps
CPU time 36.29 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 214400 kb
Host smart-00e34921-67f5-4d0d-b7e4-f30fad51d3d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875409782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1875409782
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.134186596
Short name T399
Test name
Test status
Simulation time 178033754 ps
CPU time 11.52 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:55:20 PM PDT 24
Peak memory 213520 kb
Host smart-0a0678f6-6016-400a-b0cb-20856dbc0b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134186596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.134186596
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2113974566
Short name T436
Test name
Test status
Simulation time 614427332 ps
CPU time 10.72 seconds
Started Aug 17 04:54:50 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 218092 kb
Host smart-0dff7b1a-2467-4dbd-8c4a-c8053bc272ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113974566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2113974566
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.920644846
Short name T108
Test name
Test status
Simulation time 1231548325 ps
CPU time 155.15 seconds
Started Aug 17 04:54:50 PM PDT 24
Finished Aug 17 04:57:25 PM PDT 24
Peak memory 213792 kb
Host smart-55e278a9-fad9-4951-a312-3b866e9c7224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920644846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.920644846
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3907593782
Short name T416
Test name
Test status
Simulation time 955404667 ps
CPU time 9.23 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:03 PM PDT 24
Peak memory 211404 kb
Host smart-aa5ce2d3-7016-4576-80f5-b7f6e52329aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907593782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3907593782
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.639956809
Short name T366
Test name
Test status
Simulation time 174717337 ps
CPU time 8.16 seconds
Started Aug 17 04:54:58 PM PDT 24
Finished Aug 17 04:55:06 PM PDT 24
Peak memory 211328 kb
Host smart-a2f43cdd-21d9-4376-ac88-5f65f9a7b02c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639956809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.639956809
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3596939661
Short name T378
Test name
Test status
Simulation time 348218991 ps
CPU time 11.57 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:10 PM PDT 24
Peak memory 211380 kb
Host smart-3f8b3853-66a5-45a3-bb47-c4027b1ad710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596939661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3596939661
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2451597866
Short name T443
Test name
Test status
Simulation time 1036205152 ps
CPU time 9.62 seconds
Started Aug 17 04:54:50 PM PDT 24
Finished Aug 17 04:55:00 PM PDT 24
Peak memory 215900 kb
Host smart-ffef8d19-0f92-4b78-bdb4-72dd2ead8606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451597866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2451597866
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3330114640
Short name T427
Test name
Test status
Simulation time 438144240 ps
CPU time 8.08 seconds
Started Aug 17 04:54:59 PM PDT 24
Finished Aug 17 04:55:07 PM PDT 24
Peak memory 211472 kb
Host smart-28c1fb8f-f9fc-42b4-8564-867aca171d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330114640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3330114640
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1821198264
Short name T425
Test name
Test status
Simulation time 692526354 ps
CPU time 7.6 seconds
Started Aug 17 04:55:04 PM PDT 24
Finished Aug 17 04:55:11 PM PDT 24
Peak memory 211300 kb
Host smart-3bf4244b-06a4-49f4-89ab-05a5aef2f389
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821198264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1821198264
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3518422908
Short name T362
Test name
Test status
Simulation time 336608256 ps
CPU time 9.32 seconds
Started Aug 17 04:55:00 PM PDT 24
Finished Aug 17 04:55:09 PM PDT 24
Peak memory 211280 kb
Host smart-48bafcd9-e333-498a-b870-87ce310a48a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518422908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3518422908
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1071329962
Short name T374
Test name
Test status
Simulation time 5969004375 ps
CPU time 42.39 seconds
Started Aug 17 04:55:01 PM PDT 24
Finished Aug 17 04:55:43 PM PDT 24
Peak memory 215536 kb
Host smart-017fd7a5-6869-489c-98f2-73b56e9838b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071329962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1071329962
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1072332591
Short name T445
Test name
Test status
Simulation time 242195590 ps
CPU time 7.86 seconds
Started Aug 17 04:54:50 PM PDT 24
Finished Aug 17 04:54:58 PM PDT 24
Peak memory 211960 kb
Host smart-66b7aaaa-9e06-4b93-9bca-c788c820099c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072332591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1072332591
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2796460428
Short name T406
Test name
Test status
Simulation time 249510741 ps
CPU time 12.19 seconds
Started Aug 17 04:55:04 PM PDT 24
Finished Aug 17 04:55:17 PM PDT 24
Peak memory 217668 kb
Host smart-3152f0e4-f54e-447d-8309-ff3cf0280540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796460428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2796460428
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2346424304
Short name T449
Test name
Test status
Simulation time 352549629 ps
CPU time 81.79 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 214448 kb
Host smart-bdf66015-c64b-42ab-b950-dc0d77bffc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346424304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2346424304
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4169693437
Short name T52
Test name
Test status
Simulation time 180631487 ps
CPU time 8.77 seconds
Started Aug 17 04:54:52 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 218172 kb
Host smart-3e576346-af19-449f-af15-caf1405fc897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169693437 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4169693437
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4220905659
Short name T426
Test name
Test status
Simulation time 261224229 ps
CPU time 9.37 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 211620 kb
Host smart-c725501a-71ca-45b8-a024-af0f21e9903d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220905659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4220905659
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3351148497
Short name T447
Test name
Test status
Simulation time 4070457600 ps
CPU time 13.16 seconds
Started Aug 17 04:54:58 PM PDT 24
Finished Aug 17 04:55:11 PM PDT 24
Peak memory 211772 kb
Host smart-4256a26b-48f7-455b-8143-d04104a268f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351148497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3351148497
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4015265948
Short name T419
Test name
Test status
Simulation time 487470089 ps
CPU time 11.14 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:04 PM PDT 24
Peak memory 218036 kb
Host smart-ac9ab6f1-3c42-4db9-ae2a-d37e47baad65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015265948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4015265948
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1353536455
Short name T409
Test name
Test status
Simulation time 4190104386 ps
CPU time 85.55 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:56:19 PM PDT 24
Peak memory 214508 kb
Host smart-4df6ffe8-19ac-4c5f-badd-96cc70375a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353536455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1353536455
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1976474042
Short name T400
Test name
Test status
Simulation time 1107931616 ps
CPU time 9.66 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:22 PM PDT 24
Peak memory 219608 kb
Host smart-166a9443-6588-41e2-a09a-bb92dc535c1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976474042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1976474042
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1153178146
Short name T387
Test name
Test status
Simulation time 173297701 ps
CPU time 7.82 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:01 PM PDT 24
Peak memory 211528 kb
Host smart-69a0c1f6-a0be-4013-bcc8-0b00e7d6cdb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153178146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1153178146
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3705480549
Short name T78
Test name
Test status
Simulation time 16850624800 ps
CPU time 63.55 seconds
Started Aug 17 04:55:08 PM PDT 24
Finished Aug 17 04:56:11 PM PDT 24
Peak memory 216608 kb
Host smart-eaa986e0-6b27-4733-8268-28ca2b54dffe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705480549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3705480549
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3883980691
Short name T389
Test name
Test status
Simulation time 661395998 ps
CPU time 7.73 seconds
Started Aug 17 04:54:54 PM PDT 24
Finished Aug 17 04:55:06 PM PDT 24
Peak memory 211828 kb
Host smart-86b70e04-cbb3-44ca-9c42-e03126fb29cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883980691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3883980691
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1092469159
Short name T377
Test name
Test status
Simulation time 603398779 ps
CPU time 12.37 seconds
Started Aug 17 04:55:03 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 217012 kb
Host smart-fb8342bb-0ca5-4da1-a8e4-37df8a7ea3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092469159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1092469159
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1256760269
Short name T391
Test name
Test status
Simulation time 978091065 ps
CPU time 10.05 seconds
Started Aug 17 04:54:55 PM PDT 24
Finished Aug 17 04:55:05 PM PDT 24
Peak memory 217796 kb
Host smart-61888b1d-46a5-4b63-b6d9-c87cb1e6f417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256760269 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1256760269
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1066136701
Short name T56
Test name
Test status
Simulation time 592559098 ps
CPU time 9.17 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:55:21 PM PDT 24
Peak memory 211668 kb
Host smart-5870c377-0a15-4e3b-a5ff-b325e5bfd276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066136701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1066136701
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1581437167
Short name T417
Test name
Test status
Simulation time 11662985431 ps
CPU time 63.94 seconds
Started Aug 17 04:54:51 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 215756 kb
Host smart-58597e03-80f0-40de-bebb-d6df0737377c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581437167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1581437167
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2741922543
Short name T62
Test name
Test status
Simulation time 675777794 ps
CPU time 11.69 seconds
Started Aug 17 04:55:01 PM PDT 24
Finished Aug 17 04:55:13 PM PDT 24
Peak memory 213424 kb
Host smart-a968536d-02b4-4523-a0f8-618c7517874b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741922543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2741922543
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.476092895
Short name T385
Test name
Test status
Simulation time 639141075 ps
CPU time 11.09 seconds
Started Aug 17 04:54:54 PM PDT 24
Finished Aug 17 04:55:05 PM PDT 24
Peak memory 217744 kb
Host smart-bcb2aaf5-3f05-4c17-8e97-41ba58711527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476092895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.476092895
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3858651430
Short name T49
Test name
Test status
Simulation time 5358196098 ps
CPU time 81.38 seconds
Started Aug 17 04:55:17 PM PDT 24
Finished Aug 17 04:56:38 PM PDT 24
Peak memory 213756 kb
Host smart-4420de58-750d-4f5a-be59-96058bd59ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858651430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3858651430
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4136222900
Short name T384
Test name
Test status
Simulation time 1061127904 ps
CPU time 9.98 seconds
Started Aug 17 04:54:59 PM PDT 24
Finished Aug 17 04:55:09 PM PDT 24
Peak memory 219668 kb
Host smart-1ba0d85d-35fa-4284-bb9f-923a26f8e081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136222900 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4136222900
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4258802751
Short name T423
Test name
Test status
Simulation time 4091582901 ps
CPU time 9.38 seconds
Started Aug 17 04:54:54 PM PDT 24
Finished Aug 17 04:55:03 PM PDT 24
Peak memory 211684 kb
Host smart-35979d50-a9b0-46e7-bc0f-a64884552757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258802751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4258802751
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1484266912
Short name T83
Test name
Test status
Simulation time 2455005972 ps
CPU time 35.9 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:41 PM PDT 24
Peak memory 214600 kb
Host smart-8b9080f8-248e-4d3b-87a5-5481c0a733e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484266912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1484266912
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4237245748
Short name T444
Test name
Test status
Simulation time 700414519 ps
CPU time 11.85 seconds
Started Aug 17 04:55:06 PM PDT 24
Finished Aug 17 04:55:18 PM PDT 24
Peak memory 213096 kb
Host smart-29b93dd8-636b-4dd5-ad4e-6ed06cda16f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237245748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4237245748
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3413490260
Short name T369
Test name
Test status
Simulation time 477461055 ps
CPU time 14.22 seconds
Started Aug 17 04:54:53 PM PDT 24
Finished Aug 17 04:55:08 PM PDT 24
Peak memory 218280 kb
Host smart-d92764f0-8772-45fa-abd8-6439deba95d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413490260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3413490260
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1066247182
Short name T116
Test name
Test status
Simulation time 1221434953 ps
CPU time 151.76 seconds
Started Aug 17 04:54:59 PM PDT 24
Finished Aug 17 04:57:30 PM PDT 24
Peak memory 214936 kb
Host smart-c0c66959-f28e-413b-9b15-1e9c76c94807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066247182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1066247182
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.320806467
Short name T442
Test name
Test status
Simulation time 269145770 ps
CPU time 9.95 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:55:28 PM PDT 24
Peak memory 218088 kb
Host smart-4a0692da-64f3-435c-8ae8-bd4dd4989029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320806467 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.320806467
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2997555189
Short name T440
Test name
Test status
Simulation time 993653837 ps
CPU time 9.43 seconds
Started Aug 17 04:55:05 PM PDT 24
Finished Aug 17 04:55:15 PM PDT 24
Peak memory 211320 kb
Host smart-33c33800-f362-419c-a494-81a5ecf40b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997555189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2997555189
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1233914729
Short name T418
Test name
Test status
Simulation time 2867830673 ps
CPU time 36.42 seconds
Started Aug 17 04:55:04 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 214600 kb
Host smart-1f67c6d5-111e-4c51-87eb-c7546b2615ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233914729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1233914729
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3012908346
Short name T432
Test name
Test status
Simulation time 167962009 ps
CPU time 8.07 seconds
Started Aug 17 04:55:10 PM PDT 24
Finished Aug 17 04:55:18 PM PDT 24
Peak memory 211972 kb
Host smart-9ceef9f8-7588-4e88-9514-5ca8d82fd724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012908346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3012908346
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2855512528
Short name T431
Test name
Test status
Simulation time 661105407 ps
CPU time 11.26 seconds
Started Aug 17 04:55:04 PM PDT 24
Finished Aug 17 04:55:16 PM PDT 24
Peak memory 218148 kb
Host smart-3253b274-1eaf-43a1-8583-5ce43dfacc98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855512528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2855512528
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2295230402
Short name T112
Test name
Test status
Simulation time 1272197644 ps
CPU time 80.69 seconds
Started Aug 17 04:55:13 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 214000 kb
Host smart-c5234bb6-17df-42c4-93b7-209682cd6f46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295230402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2295230402
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4267940337
Short name T287
Test name
Test status
Simulation time 991080866 ps
CPU time 9.39 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 218360 kb
Host smart-a9a41b13-5239-48b5-b126-96ff37733847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267940337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4267940337
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3892680667
Short name T305
Test name
Test status
Simulation time 5362367357 ps
CPU time 153.07 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:57:44 PM PDT 24
Peak memory 224228 kb
Host smart-114d8b18-a350-48f9-a9df-35a87f44cd48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892680667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3892680667
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2442024549
Short name T91
Test name
Test status
Simulation time 8240151540 ps
CPU time 22.17 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218880 kb
Host smart-2df87d7f-d448-4705-8f3a-8e7061ba448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442024549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2442024549
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1519219332
Short name T165
Test name
Test status
Simulation time 1719070771 ps
CPU time 11.61 seconds
Started Aug 17 04:55:09 PM PDT 24
Finished Aug 17 04:55:21 PM PDT 24
Peak memory 218932 kb
Host smart-07ce3e0d-6112-48aa-b3f2-99d87f4da34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519219332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1519219332
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1780433093
Short name T310
Test name
Test status
Simulation time 728649491 ps
CPU time 10.05 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:31 PM PDT 24
Peak memory 219164 kb
Host smart-435dde64-89a8-4581-af2f-91fe6a771182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780433093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1780433093
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3271179071
Short name T211
Test name
Test status
Simulation time 2190486060 ps
CPU time 25.61 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:42 PM PDT 24
Peak memory 219172 kb
Host smart-1adcbce1-c62a-47a2-80b2-8e9ac2605a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271179071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3271179071
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3695967975
Short name T217
Test name
Test status
Simulation time 5368603612 ps
CPU time 275.01 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:59:50 PM PDT 24
Peak memory 226632 kb
Host smart-aff6f027-34ad-49ec-a60c-48056e69a652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695967975 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3695967975
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3555589651
Short name T302
Test name
Test status
Simulation time 395992712 ps
CPU time 7.98 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:29 PM PDT 24
Peak memory 218328 kb
Host smart-eb59da54-7095-44a4-959f-946f9d779d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555589651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3555589651
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.371259966
Short name T137
Test name
Test status
Simulation time 14430135433 ps
CPU time 238.51 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:59:20 PM PDT 24
Peak memory 240708 kb
Host smart-4fc5bb6f-680b-492e-b334-b52c58e83575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371259966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.371259966
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1142481083
Short name T274
Test name
Test status
Simulation time 1981489864 ps
CPU time 22.15 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:33 PM PDT 24
Peak memory 218640 kb
Host smart-578b553e-d6f2-497b-807a-cc72b4f5e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142481083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1142481083
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.994676540
Short name T282
Test name
Test status
Simulation time 729163595 ps
CPU time 9.87 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 218872 kb
Host smart-8cbc3309-944a-4320-941f-ce6977ce558f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994676540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.994676540
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.970274746
Short name T18
Test name
Test status
Simulation time 1136325885 ps
CPU time 226.33 seconds
Started Aug 17 04:55:12 PM PDT 24
Finished Aug 17 04:58:59 PM PDT 24
Peak memory 238644 kb
Host smart-10c8823f-9203-48eb-836c-18ae96b3f928
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970274746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.970274746
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3563964066
Short name T101
Test name
Test status
Simulation time 914030176 ps
CPU time 11.21 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 218496 kb
Host smart-1db54fb7-4f6b-49cc-9b1d-086fc78a5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563964066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3563964066
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1668782610
Short name T247
Test name
Test status
Simulation time 213023406 ps
CPU time 10.92 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:27 PM PDT 24
Peak memory 215088 kb
Host smart-fd74fdd3-5941-45d4-af4a-edf567c731a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668782610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1668782610
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1167855749
Short name T155
Test name
Test status
Simulation time 2043247403 ps
CPU time 111.55 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:57:09 PM PDT 24
Peak memory 224808 kb
Host smart-f6b68a59-860f-4ffd-9844-230417bdd4c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167855749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1167855749
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.527378376
Short name T357
Test name
Test status
Simulation time 605399319 ps
CPU time 9.76 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:55:29 PM PDT 24
Peak memory 218268 kb
Host smart-a12abaf0-3e58-44e1-8fc6-4f40baa372ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527378376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.527378376
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4153884467
Short name T31
Test name
Test status
Simulation time 18575532339 ps
CPU time 240.47 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:59:20 PM PDT 24
Peak memory 233704 kb
Host smart-e1f40f06-820f-4fea-80b8-6859f375956d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153884467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4153884467
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3478567244
Short name T121
Test name
Test status
Simulation time 333215423 ps
CPU time 18.97 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218528 kb
Host smart-37de02c1-fe1d-4946-bf5c-64727158699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478567244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3478567244
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3618666133
Short name T261
Test name
Test status
Simulation time 265451127 ps
CPU time 11.55 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 218512 kb
Host smart-2fe6da73-324c-4add-bb0d-ff1e68974fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618666133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3618666133
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.880990058
Short name T123
Test name
Test status
Simulation time 996935545 ps
CPU time 15.24 seconds
Started Aug 17 04:55:19 PM PDT 24
Finished Aug 17 04:55:35 PM PDT 24
Peak memory 218924 kb
Host smart-91b32780-f8bb-4358-8cde-2ee31d274f99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880990058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.880990058
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1406972787
Short name T85
Test name
Test status
Simulation time 10155105559 ps
CPU time 131.08 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:57:33 PM PDT 24
Peak memory 234984 kb
Host smart-de8e9653-31c1-4c6a-b24d-dabb0261b11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406972787 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1406972787
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1008772028
Short name T14
Test name
Test status
Simulation time 10171661285 ps
CPU time 166.9 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:58:14 PM PDT 24
Peak memory 239528 kb
Host smart-566a8292-e6ee-4441-99b5-311df1176924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008772028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1008772028
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4171526036
Short name T331
Test name
Test status
Simulation time 1976174668 ps
CPU time 21.54 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:49 PM PDT 24
Peak memory 218380 kb
Host smart-9a023ee7-02c4-445a-9545-1f19814161f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171526036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4171526036
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.337465206
Short name T333
Test name
Test status
Simulation time 2462135122 ps
CPU time 10.15 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:32 PM PDT 24
Peak memory 218952 kb
Host smart-65ce64a4-9ed6-4a09-b7f8-ebc26c568648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337465206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.337465206
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2709869695
Short name T148
Test name
Test status
Simulation time 4184148153 ps
CPU time 44.27 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:56:09 PM PDT 24
Peak memory 220600 kb
Host smart-a48b86f9-0889-4488-a6af-f40650d43ae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709869695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2709869695
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3317657038
Short name T168
Test name
Test status
Simulation time 9749246435 ps
CPU time 196.95 seconds
Started Aug 17 04:55:30 PM PDT 24
Finished Aug 17 04:58:47 PM PDT 24
Peak memory 235648 kb
Host smart-b8d347d5-bc6e-4a7d-9956-8c50297a1e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317657038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3317657038
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4161733114
Short name T26
Test name
Test status
Simulation time 2466998365 ps
CPU time 9.32 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 218404 kb
Host smart-45c17bf9-3297-414a-a08b-b8d15a7f993f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161733114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4161733114
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2005561304
Short name T330
Test name
Test status
Simulation time 4333650165 ps
CPU time 193.34 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:58:45 PM PDT 24
Peak memory 219204 kb
Host smart-737d3d7f-60d1-48d6-970f-297e5918c64c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005561304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2005561304
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.228460980
Short name T224
Test name
Test status
Simulation time 532252480 ps
CPU time 11.41 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:36 PM PDT 24
Peak memory 218592 kb
Host smart-28e4af16-dc24-4deb-bfc5-ea14f49991da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228460980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.228460980
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3309032751
Short name T182
Test name
Test status
Simulation time 540304428 ps
CPU time 33.7 seconds
Started Aug 17 04:55:30 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 219104 kb
Host smart-6a4c3ab9-4ff0-4b45-8055-66472e90a5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309032751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3309032751
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3879560542
Short name T243
Test name
Test status
Simulation time 16765447247 ps
CPU time 206.59 seconds
Started Aug 17 04:55:30 PM PDT 24
Finished Aug 17 04:58:56 PM PDT 24
Peak memory 227116 kb
Host smart-de287be0-32fc-4c78-b31e-79c99d81e8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879560542 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3879560542
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3175653743
Short name T213
Test name
Test status
Simulation time 429467659 ps
CPU time 9.63 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 218284 kb
Host smart-6c29c783-e04d-42ee-9d0e-cef3d9dbe061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175653743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3175653743
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2724019406
Short name T325
Test name
Test status
Simulation time 6063632539 ps
CPU time 277.48 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 05:00:04 PM PDT 24
Peak memory 218908 kb
Host smart-a36d8102-339f-4783-b43d-c04fda60d145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724019406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2724019406
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3986165410
Short name T196
Test name
Test status
Simulation time 565545293 ps
CPU time 21.07 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:46 PM PDT 24
Peak memory 218420 kb
Host smart-41a0dec7-3dac-4b6b-ad01-9928bcf56917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986165410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3986165410
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2656855364
Short name T347
Test name
Test status
Simulation time 1067661393 ps
CPU time 11.44 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 218856 kb
Host smart-0e1301b5-40f5-447f-9b22-1503529d1ee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656855364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2656855364
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3453111620
Short name T349
Test name
Test status
Simulation time 853498522 ps
CPU time 11.41 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 219176 kb
Host smart-6bc18eb0-c0c2-4adb-8a92-6aa22aff15c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453111620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3453111620
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2725333853
Short name T280
Test name
Test status
Simulation time 497808806 ps
CPU time 9.4 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218384 kb
Host smart-45bdbf0c-fd4b-486e-8ac8-109d87edafad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725333853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2725333853
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.401133050
Short name T136
Test name
Test status
Simulation time 663701682 ps
CPU time 18.5 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:55:51 PM PDT 24
Peak memory 218636 kb
Host smart-b982c9a1-5d94-45fe-b20f-9dccee3b666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401133050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.401133050
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4003490115
Short name T328
Test name
Test status
Simulation time 538105399 ps
CPU time 11.63 seconds
Started Aug 17 04:55:30 PM PDT 24
Finished Aug 17 04:55:42 PM PDT 24
Peak memory 218756 kb
Host smart-b1d8de8d-997e-4cc0-aadc-1e4b3848ce8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003490115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4003490115
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3989317410
Short name T335
Test name
Test status
Simulation time 314430265 ps
CPU time 34.7 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 219032 kb
Host smart-3d22f594-e772-4f47-86bc-abc5862a8a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989317410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3989317410
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1451189108
Short name T117
Test name
Test status
Simulation time 14733944751 ps
CPU time 118.52 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:57:33 PM PDT 24
Peak memory 235676 kb
Host smart-c1c2dc7c-87a0-4975-b5f6-d63716f6344f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451189108 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1451189108
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2065998147
Short name T203
Test name
Test status
Simulation time 275428724 ps
CPU time 9.49 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 218268 kb
Host smart-95c9c3f2-9c23-48a4-9ba1-a08ccd5e4cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065998147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2065998147
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.429990597
Short name T157
Test name
Test status
Simulation time 15692185479 ps
CPU time 258.88 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:59:56 PM PDT 24
Peak memory 233548 kb
Host smart-f3fc2aa9-09fa-49c7-8799-0fa62732cf9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429990597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.429990597
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4106786101
Short name T268
Test name
Test status
Simulation time 1014091161 ps
CPU time 21.86 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:47 PM PDT 24
Peak memory 218688 kb
Host smart-8a795d4e-ad0d-440f-aed5-ae6b09a11efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106786101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4106786101
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1680715283
Short name T185
Test name
Test status
Simulation time 1128221097 ps
CPU time 18.95 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:55:45 PM PDT 24
Peak memory 218956 kb
Host smart-f2ef9ad3-a6ee-4baa-96f9-1efb3e8c0ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680715283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1680715283
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.654559189
Short name T161
Test name
Test status
Simulation time 34617904566 ps
CPU time 150.86 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:58:03 PM PDT 24
Peak memory 235564 kb
Host smart-a5afe319-2bc8-46db-9935-85441f19691b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654559189 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.654559189
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2363714065
Short name T307
Test name
Test status
Simulation time 2054158177 ps
CPU time 9.45 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 218416 kb
Host smart-9a8079e9-7911-44b0-95fb-e99ebf13b61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363714065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2363714065
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2821532128
Short name T257
Test name
Test status
Simulation time 7164228262 ps
CPU time 136.57 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:57:45 PM PDT 24
Peak memory 218620 kb
Host smart-c2218b8b-355e-43ab-b0d2-3348b0a78d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821532128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2821532128
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2719562409
Short name T92
Test name
Test status
Simulation time 7900387613 ps
CPU time 27.7 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 219148 kb
Host smart-e1ab2e7e-caf2-402e-a3cc-086c7ab1d665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719562409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2719562409
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.905140885
Short name T354
Test name
Test status
Simulation time 699089157 ps
CPU time 10.14 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218788 kb
Host smart-6689ce00-1a6f-49a7-bfc8-13d0a3ab94f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905140885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.905140885
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4198185217
Short name T275
Test name
Test status
Simulation time 3039990312 ps
CPU time 126.37 seconds
Started Aug 17 04:55:36 PM PDT 24
Finished Aug 17 04:57:43 PM PDT 24
Peak memory 224528 kb
Host smart-88c0e267-86de-4bf2-9455-e4cf4bd291d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198185217 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.4198185217
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3654450732
Short name T3
Test name
Test status
Simulation time 993786079 ps
CPU time 9.61 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218428 kb
Host smart-8891c151-b701-4058-9941-77871ea7efe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654450732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3654450732
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3948500324
Short name T204
Test name
Test status
Simulation time 16829245696 ps
CPU time 429.01 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 05:02:37 PM PDT 24
Peak memory 233788 kb
Host smart-37896ef1-01b1-411f-8a8f-31389280f512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948500324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3948500324
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3500458611
Short name T20
Test name
Test status
Simulation time 990745681 ps
CPU time 21.31 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 218808 kb
Host smart-8b17e374-bab7-45a1-b936-6bae1337cb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500458611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3500458611
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3798999768
Short name T345
Test name
Test status
Simulation time 271790578 ps
CPU time 12.17 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218588 kb
Host smart-ec475f69-c991-426d-b1b5-5de2955d3a8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798999768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3798999768
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.480171308
Short name T288
Test name
Test status
Simulation time 3261546634 ps
CPU time 50.58 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 219804 kb
Host smart-45e6a585-0de9-4371-9c90-75a8ba7fa665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480171308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.480171308
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3437812890
Short name T244
Test name
Test status
Simulation time 15562582004 ps
CPU time 153.73 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:58:23 PM PDT 24
Peak memory 235628 kb
Host smart-7a1913bf-5895-4a40-a5ca-60b52b756b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437812890 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3437812890
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3943302329
Short name T265
Test name
Test status
Simulation time 259696188 ps
CPU time 9.65 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218356 kb
Host smart-e27cbdb2-b127-4c1f-a786-b94febec695c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943302329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3943302329
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1579308202
Short name T269
Test name
Test status
Simulation time 19946412956 ps
CPU time 298.45 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 05:00:32 PM PDT 24
Peak memory 219252 kb
Host smart-011d84d1-8ba6-4539-a57d-5d129a21862e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579308202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1579308202
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2280709870
Short name T38
Test name
Test status
Simulation time 346278352 ps
CPU time 18.78 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:55:53 PM PDT 24
Peak memory 218620 kb
Host smart-f495baef-b46f-46ac-bdd3-9ea271dc74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280709870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2280709870
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1744716880
Short name T160
Test name
Test status
Simulation time 182298600 ps
CPU time 9.83 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218572 kb
Host smart-046d26f5-021c-4983-89ef-fc3875d212fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744716880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1744716880
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2282203763
Short name T353
Test name
Test status
Simulation time 291818590 ps
CPU time 15.91 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:45 PM PDT 24
Peak memory 219196 kb
Host smart-028b8856-a4ed-4fbe-901b-11391ad0e66b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282203763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2282203763
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1931379181
Short name T270
Test name
Test status
Simulation time 346167766 ps
CPU time 8.1 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:55:50 PM PDT 24
Peak memory 217948 kb
Host smart-86c1d4f8-b3ec-420e-ad39-92bc37464db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931379181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1931379181
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1799612500
Short name T297
Test name
Test status
Simulation time 2258300889 ps
CPU time 110.36 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:57:22 PM PDT 24
Peak memory 218844 kb
Host smart-2f19dda0-b82c-4875-9bb0-eac8a1f146fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799612500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1799612500
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2917238554
Short name T87
Test name
Test status
Simulation time 332850633 ps
CPU time 18.43 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:46 PM PDT 24
Peak memory 218732 kb
Host smart-1535382a-325a-4aad-93d5-5ebe87bebf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917238554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2917238554
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3529437783
Short name T175
Test name
Test status
Simulation time 271074042 ps
CPU time 11.43 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 218476 kb
Host smart-7b65f8e1-1ae9-4d1f-b6f2-003498964430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529437783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3529437783
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2516392040
Short name T139
Test name
Test status
Simulation time 2094450477 ps
CPU time 28.04 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 219092 kb
Host smart-fc6c8f7d-f35d-4af7-a12f-b6a9afbb9d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516392040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2516392040
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3753458075
Short name T222
Test name
Test status
Simulation time 4243958865 ps
CPU time 43.87 seconds
Started Aug 17 04:55:30 PM PDT 24
Finished Aug 17 04:56:14 PM PDT 24
Peak memory 231436 kb
Host smart-3d568b74-7cee-4578-9860-7c420625e164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753458075 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3753458075
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1043268812
Short name T170
Test name
Test status
Simulation time 1040013895 ps
CPU time 9.42 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:32 PM PDT 24
Peak memory 218256 kb
Host smart-d84441da-e9c9-40c0-a0a9-ff9ab9aa1b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043268812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1043268812
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1793060225
Short name T5
Test name
Test status
Simulation time 73128505524 ps
CPU time 262.59 seconds
Started Aug 17 04:55:10 PM PDT 24
Finished Aug 17 04:59:33 PM PDT 24
Peak memory 219200 kb
Host smart-73407dfa-627a-4745-9959-61efd54b11e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793060225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1793060225
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4001314688
Short name T225
Test name
Test status
Simulation time 2054702962 ps
CPU time 21.74 seconds
Started Aug 17 04:55:16 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 218912 kb
Host smart-36b5df14-4fbe-4822-9f6f-6526eb805b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001314688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4001314688
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2146163538
Short name T343
Test name
Test status
Simulation time 4098119254 ps
CPU time 15.43 seconds
Started Aug 17 04:55:15 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 219144 kb
Host smart-68a9bb7c-5f59-42c3-b804-385b78535478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146163538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2146163538
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3440691089
Short name T19
Test name
Test status
Simulation time 298612365 ps
CPU time 117.31 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:57:24 PM PDT 24
Peak memory 237712 kb
Host smart-b88b5091-277f-4c50-b8d7-d865578a9adf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440691089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3440691089
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3062050914
Short name T293
Test name
Test status
Simulation time 174672408 ps
CPU time 10.3 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:36 PM PDT 24
Peak memory 219072 kb
Host smart-0cdf7a7f-779f-4a1c-a213-44c14e442ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062050914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3062050914
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2095263526
Short name T150
Test name
Test status
Simulation time 563469957 ps
CPU time 30.33 seconds
Started Aug 17 04:55:11 PM PDT 24
Finished Aug 17 04:55:42 PM PDT 24
Peak memory 219088 kb
Host smart-202abfa6-ffe1-46b7-895e-2fbd7ca0a3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095263526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2095263526
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3371229728
Short name T180
Test name
Test status
Simulation time 3628326898 ps
CPU time 179.32 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:58:21 PM PDT 24
Peak memory 233312 kb
Host smart-257f32fe-97f9-4c8a-a130-03e56b42d6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371229728 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3371229728
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.831878393
Short name T154
Test name
Test status
Simulation time 531386124 ps
CPU time 9.54 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:55:41 PM PDT 24
Peak memory 218920 kb
Host smart-1bf83faa-b0d0-4720-9018-95b49417836c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831878393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.831878393
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2936926827
Short name T242
Test name
Test status
Simulation time 1459425350 ps
CPU time 163.98 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:58:32 PM PDT 24
Peak memory 236224 kb
Host smart-c566cde9-a95f-4554-b5f3-b763dd5328f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936926827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2936926827
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1346297315
Short name T164
Test name
Test status
Simulation time 1378463392 ps
CPU time 18.33 seconds
Started Aug 17 04:55:29 PM PDT 24
Finished Aug 17 04:55:47 PM PDT 24
Peak memory 218520 kb
Host smart-3b0b5e5b-7b55-4cae-bb75-b1c32c285c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346297315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1346297315
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.841754750
Short name T195
Test name
Test status
Simulation time 1424566352 ps
CPU time 9.79 seconds
Started Aug 17 04:55:36 PM PDT 24
Finished Aug 17 04:55:45 PM PDT 24
Peak memory 218904 kb
Host smart-d4c29be1-22d0-4e3e-97ff-8fb407af45e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841754750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.841754750
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3021140665
Short name T72
Test name
Test status
Simulation time 2006061230 ps
CPU time 27.48 seconds
Started Aug 17 04:55:43 PM PDT 24
Finished Aug 17 04:56:10 PM PDT 24
Peak memory 219120 kb
Host smart-092606c2-29fa-4509-b571-a52de9989706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021140665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3021140665
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.503835143
Short name T1
Test name
Test status
Simulation time 13032322714 ps
CPU time 139.5 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:57:45 PM PDT 24
Peak memory 227456 kb
Host smart-4950fc6f-6eb2-48d9-809d-4e26ce519732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503835143 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.503835143
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1992256501
Short name T40
Test name
Test status
Simulation time 496247575 ps
CPU time 9.66 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:56:01 PM PDT 24
Peak memory 218320 kb
Host smart-a3a649d7-9fa6-434e-bc9d-fe3a75c5ad54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992256501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1992256501
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3269975132
Short name T246
Test name
Test status
Simulation time 24949601850 ps
CPU time 330.34 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 05:01:19 PM PDT 24
Peak memory 229528 kb
Host smart-bcd2ccdd-2929-4282-9492-4a23958868f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269975132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3269975132
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3618007362
Short name T301
Test name
Test status
Simulation time 507540482 ps
CPU time 21.57 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:55:56 PM PDT 24
Peak memory 218820 kb
Host smart-676689c3-2d89-4026-b160-37afc426e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618007362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3618007362
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2064436625
Short name T281
Test name
Test status
Simulation time 1035589773 ps
CPU time 11.62 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 218840 kb
Host smart-58589841-c211-4f37-b487-6720c07debbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064436625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2064436625
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3223342826
Short name T223
Test name
Test status
Simulation time 2096718775 ps
CPU time 30.1 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 219116 kb
Host smart-35231fc8-221a-4025-bb1f-c95ef930e8af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223342826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3223342826
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2905889682
Short name T192
Test name
Test status
Simulation time 3019843832 ps
CPU time 52.2 seconds
Started Aug 17 04:55:54 PM PDT 24
Finished Aug 17 04:56:47 PM PDT 24
Peak memory 223660 kb
Host smart-6846bea0-5863-4953-8e83-de3f0e9def8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905889682 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2905889682
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.24672328
Short name T256
Test name
Test status
Simulation time 689553987 ps
CPU time 7.9 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 04:55:41 PM PDT 24
Peak memory 218360 kb
Host smart-4256afd5-d25f-4252-a6d0-e3cf4a9e292a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.24672328
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.804524048
Short name T143
Test name
Test status
Simulation time 2892864318 ps
CPU time 155.4 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:58:06 PM PDT 24
Peak memory 239340 kb
Host smart-afdc1acb-0c11-4221-89ee-c7923da8b001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804524048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.804524048
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3463872796
Short name T144
Test name
Test status
Simulation time 677152124 ps
CPU time 18.25 seconds
Started Aug 17 04:55:35 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 218592 kb
Host smart-63cbe988-4c32-4795-b7ac-be92e21313ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463872796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3463872796
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3134086807
Short name T236
Test name
Test status
Simulation time 259085800 ps
CPU time 11.32 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 218532 kb
Host smart-f3d8c3b3-e45e-440c-9067-f3be499d10c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134086807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3134086807
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.791022692
Short name T314
Test name
Test status
Simulation time 17227678058 ps
CPU time 43.48 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 220744 kb
Host smart-30e66560-99a8-4bd0-a2e0-7d80e74634be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791022692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.791022692
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2715107960
Short name T235
Test name
Test status
Simulation time 37958618485 ps
CPU time 221.35 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 04:59:14 PM PDT 24
Peak memory 229420 kb
Host smart-436a235a-2d5d-4320-9efe-e1217d5d1c53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715107960 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2715107960
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.720588691
Short name T327
Test name
Test status
Simulation time 1033258975 ps
CPU time 9.87 seconds
Started Aug 17 04:55:54 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 218344 kb
Host smart-f5770ecd-7e65-4820-a642-10b48f66f0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720588691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.720588691
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2673810732
Short name T198
Test name
Test status
Simulation time 83664998141 ps
CPU time 257.91 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:59:50 PM PDT 24
Peak memory 219188 kb
Host smart-f4bad697-fd5f-4efb-80b7-d30e587b0c42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673810732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2673810732
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.353960998
Short name T89
Test name
Test status
Simulation time 521753965 ps
CPU time 11.01 seconds
Started Aug 17 04:55:38 PM PDT 24
Finished Aug 17 04:55:49 PM PDT 24
Peak memory 218568 kb
Host smart-0c2da275-d034-40a4-814d-8e0d0d94c61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353960998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.353960998
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2827412173
Short name T189
Test name
Test status
Simulation time 354321620 ps
CPU time 13.15 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:02 PM PDT 24
Peak memory 218864 kb
Host smart-b1b028fe-ba3d-490b-9063-cf4e1ff28c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827412173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2827412173
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2100975415
Short name T186
Test name
Test status
Simulation time 43438730682 ps
CPU time 110.01 seconds
Started Aug 17 04:55:35 PM PDT 24
Finished Aug 17 04:57:26 PM PDT 24
Peak memory 235600 kb
Host smart-e4c40c5f-83b9-4ca5-bce2-ead7c2672c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100975415 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2100975415
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.85829611
Short name T146
Test name
Test status
Simulation time 249575469 ps
CPU time 9.87 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 218176 kb
Host smart-b71d52f4-122d-4f3f-af56-7f4bbd7f6fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85829611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.85829611
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.583651955
Short name T351
Test name
Test status
Simulation time 5787053918 ps
CPU time 287.22 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 05:00:36 PM PDT 24
Peak memory 217800 kb
Host smart-47063e9e-5582-4595-b957-ae5d9ad4663c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583651955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.583651955
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.394392642
Short name T278
Test name
Test status
Simulation time 2077910772 ps
CPU time 27.79 seconds
Started Aug 17 04:55:38 PM PDT 24
Finished Aug 17 04:56:06 PM PDT 24
Peak memory 219132 kb
Host smart-c188e43f-1fba-4529-9e06-ed628ce17e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394392642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.394392642
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2993589298
Short name T263
Test name
Test status
Simulation time 9938067289 ps
CPU time 14.83 seconds
Started Aug 17 04:55:41 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 219116 kb
Host smart-53cc3f70-4ddc-400a-bc78-0e75b7cfa673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993589298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2993589298
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3787687347
Short name T66
Test name
Test status
Simulation time 1160979287 ps
CPU time 36.93 seconds
Started Aug 17 04:55:44 PM PDT 24
Finished Aug 17 04:56:21 PM PDT 24
Peak memory 219088 kb
Host smart-6b1abbdb-bb93-410c-8005-e02dc81878be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787687347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3787687347
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1067748142
Short name T267
Test name
Test status
Simulation time 4070651250 ps
CPU time 171.92 seconds
Started Aug 17 04:55:35 PM PDT 24
Finished Aug 17 04:58:27 PM PDT 24
Peak memory 234248 kb
Host smart-c8f7be4e-aa19-4c73-9045-c4aae01e09b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067748142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1067748142
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3123270028
Short name T208
Test name
Test status
Simulation time 1547226367 ps
CPU time 9.69 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:55:46 PM PDT 24
Peak memory 218264 kb
Host smart-15b986ef-9135-4091-ae2b-ea6bc7262bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123270028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3123270028
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2427445508
Short name T35
Test name
Test status
Simulation time 19275986117 ps
CPU time 152.95 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 04:58:06 PM PDT 24
Peak memory 237440 kb
Host smart-ceacdc73-98f4-4ead-8828-4e7d289ce7cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427445508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2427445508
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3509035498
Short name T152
Test name
Test status
Simulation time 991415798 ps
CPU time 21.1 seconds
Started Aug 17 04:55:38 PM PDT 24
Finished Aug 17 04:55:59 PM PDT 24
Peak memory 218536 kb
Host smart-7aa134a7-5eb8-403d-a8fc-34800d680e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509035498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3509035498
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.522179396
Short name T296
Test name
Test status
Simulation time 1101146780 ps
CPU time 11.44 seconds
Started Aug 17 04:55:55 PM PDT 24
Finished Aug 17 04:56:06 PM PDT 24
Peak memory 218888 kb
Host smart-0de91b3d-0215-40d0-bbfa-cdc57124ff18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522179396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.522179396
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2101568001
Short name T276
Test name
Test status
Simulation time 580460834 ps
CPU time 37.82 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:56:29 PM PDT 24
Peak memory 219092 kb
Host smart-9814a0e7-8a09-4fe7-afe4-374dbc3f5525
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101568001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2101568001
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3171940925
Short name T264
Test name
Test status
Simulation time 1725767167 ps
CPU time 68.1 seconds
Started Aug 17 04:55:44 PM PDT 24
Finished Aug 17 04:56:52 PM PDT 24
Peak memory 223712 kb
Host smart-d5cbe653-813e-4113-86c8-4a6120efdf71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171940925 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3171940925
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1836236431
Short name T10
Test name
Test status
Simulation time 613184785 ps
CPU time 7.8 seconds
Started Aug 17 04:55:32 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 218432 kb
Host smart-1e2098bc-4a5a-441d-8684-67b723c7bf0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836236431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1836236431
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4108572873
Short name T202
Test name
Test status
Simulation time 11090599984 ps
CPU time 294.14 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 05:00:46 PM PDT 24
Peak memory 236056 kb
Host smart-369bb3d1-5dcf-4e5c-a665-ade94dee5cde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108572873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4108572873
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1252963081
Short name T258
Test name
Test status
Simulation time 2007911674 ps
CPU time 28.71 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:19 PM PDT 24
Peak memory 219092 kb
Host smart-26a3aec2-2fa5-420c-be96-c21261e3108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252963081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1252963081
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.56524041
Short name T132
Test name
Test status
Simulation time 519045834 ps
CPU time 11.69 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:55:48 PM PDT 24
Peak memory 218880 kb
Host smart-6b05a018-1536-4946-8d77-40be1a1eac36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56524041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.56524041
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.791187754
Short name T300
Test name
Test status
Simulation time 2120650228 ps
CPU time 28.15 seconds
Started Aug 17 04:55:36 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 219208 kb
Host smart-79171e18-9bf6-49de-9a4b-de877dd9a69e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791187754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.791187754
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1179075760
Short name T317
Test name
Test status
Simulation time 4321001563 ps
CPU time 252.02 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:59:49 PM PDT 24
Peak memory 226212 kb
Host smart-c2d21c59-186a-47c7-9882-c55994ab3369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179075760 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1179075760
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2041452995
Short name T245
Test name
Test status
Simulation time 253059115 ps
CPU time 9.63 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:55:43 PM PDT 24
Peak memory 218464 kb
Host smart-708af8e5-3640-430e-8f35-2dae0e9cc857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041452995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2041452995
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3530335289
Short name T181
Test name
Test status
Simulation time 3315272022 ps
CPU time 214.53 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:59:23 PM PDT 24
Peak memory 233564 kb
Host smart-d69b6404-8b82-4edc-a017-27bed0261804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530335289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3530335289
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.69324740
Short name T210
Test name
Test status
Simulation time 1707705508 ps
CPU time 21.9 seconds
Started Aug 17 04:55:35 PM PDT 24
Finished Aug 17 04:55:57 PM PDT 24
Peak memory 218580 kb
Host smart-82424737-d67a-4b75-b1b9-d231ad31e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69324740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.69324740
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2804211784
Short name T266
Test name
Test status
Simulation time 364350292 ps
CPU time 10.33 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:55:42 PM PDT 24
Peak memory 218604 kb
Host smart-080cafd1-7b79-4f65-9c29-a13752bbd80b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804211784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2804211784
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1949499435
Short name T306
Test name
Test status
Simulation time 3919217782 ps
CPU time 19.06 seconds
Started Aug 17 04:55:38 PM PDT 24
Finished Aug 17 04:55:57 PM PDT 24
Peak memory 216940 kb
Host smart-352a8b81-4ffb-4b4f-be51-7a8e969a6ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949499435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1949499435
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2383922588
Short name T118
Test name
Test status
Simulation time 6790128594 ps
CPU time 119.12 seconds
Started Aug 17 04:55:36 PM PDT 24
Finished Aug 17 04:57:35 PM PDT 24
Peak memory 225164 kb
Host smart-5ce07692-512b-453f-9a4b-89dccf50b795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383922588 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2383922588
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1989985559
Short name T191
Test name
Test status
Simulation time 869742538 ps
CPU time 8.06 seconds
Started Aug 17 04:55:38 PM PDT 24
Finished Aug 17 04:55:46 PM PDT 24
Peak memory 218324 kb
Host smart-52456f89-2b68-4550-af4a-deae1dc9a29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989985559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1989985559
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1139942167
Short name T292
Test name
Test status
Simulation time 3923510988 ps
CPU time 278.38 seconds
Started Aug 17 04:55:33 PM PDT 24
Finished Aug 17 05:00:12 PM PDT 24
Peak memory 237720 kb
Host smart-1eda8ba6-016a-45ca-9723-a541ca7a78b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139942167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1139942167
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1647726606
Short name T344
Test name
Test status
Simulation time 971943893 ps
CPU time 18.16 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 218764 kb
Host smart-0471bde3-49b1-489a-a759-5c6a4be7de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647726606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1647726606
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3018001896
Short name T149
Test name
Test status
Simulation time 708527797 ps
CPU time 10.24 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:55:47 PM PDT 24
Peak memory 218936 kb
Host smart-44b1b3b1-93d6-407b-be52-505eccbf141e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018001896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3018001896
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.645398246
Short name T241
Test name
Test status
Simulation time 3227756326 ps
CPU time 37.27 seconds
Started Aug 17 04:55:35 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 219236 kb
Host smart-49796057-db75-40a2-8eb8-df32f05d7e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645398246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.645398246
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3938248170
Short name T234
Test name
Test status
Simulation time 1109204756 ps
CPU time 64.38 seconds
Started Aug 17 04:55:40 PM PDT 24
Finished Aug 17 04:56:45 PM PDT 24
Peak memory 222948 kb
Host smart-8dee075c-5570-47c7-92a2-884db9e581a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938248170 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3938248170
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.844270200
Short name T119
Test name
Test status
Simulation time 256407111 ps
CPU time 9.73 seconds
Started Aug 17 04:55:44 PM PDT 24
Finished Aug 17 04:55:54 PM PDT 24
Peak memory 218260 kb
Host smart-7cd3f678-2d1c-4269-b957-01b03495fe2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844270200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.844270200
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.780227416
Short name T29
Test name
Test status
Simulation time 21075959703 ps
CPU time 269.53 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 05:00:18 PM PDT 24
Peak memory 242836 kb
Host smart-1af23cef-cfff-4e99-8d2e-58a7775e1c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780227416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.780227416
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1254865628
Short name T321
Test name
Test status
Simulation time 272135963 ps
CPU time 11.48 seconds
Started Aug 17 04:55:55 PM PDT 24
Finished Aug 17 04:56:06 PM PDT 24
Peak memory 218652 kb
Host smart-81037552-0982-4272-97c1-6421cef8ff58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254865628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1254865628
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3234509820
Short name T294
Test name
Test status
Simulation time 574065979 ps
CPU time 33.56 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 219068 kb
Host smart-1bdf417c-d958-4f28-85c1-9bb7b2d09952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234509820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3234509820
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2761196272
Short name T12
Test name
Test status
Simulation time 5176067914 ps
CPU time 117.91 seconds
Started Aug 17 04:55:40 PM PDT 24
Finished Aug 17 04:57:38 PM PDT 24
Peak memory 235328 kb
Host smart-dd23ec60-8ff5-4f53-8377-f95b3afb47d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761196272 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2761196272
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4055415070
Short name T309
Test name
Test status
Simulation time 174377087 ps
CPU time 8.02 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:29 PM PDT 24
Peak memory 218420 kb
Host smart-1fb14a77-8611-4c24-abfa-8c5413907c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055415070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4055415070
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.909698580
Short name T215
Test name
Test status
Simulation time 1814229970 ps
CPU time 132.69 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:57:41 PM PDT 24
Peak memory 226976 kb
Host smart-cb504015-7d45-42c4-b310-430db2967d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909698580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.909698580
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1805621634
Short name T153
Test name
Test status
Simulation time 7882581431 ps
CPU time 28.79 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:51 PM PDT 24
Peak memory 219248 kb
Host smart-defc71b5-f4be-4bd7-84e7-defda8958cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805621634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1805621634
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1688355893
Short name T197
Test name
Test status
Simulation time 271387765 ps
CPU time 11.51 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:36 PM PDT 24
Peak memory 218576 kb
Host smart-6ea4d2dd-0b5d-499c-8f2c-c3ea9b772a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688355893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1688355893
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3733542439
Short name T23
Test name
Test status
Simulation time 1931858089 ps
CPU time 226.77 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:59:14 PM PDT 24
Peak memory 237428 kb
Host smart-9b5f7962-0648-4bd7-917a-72211af1825e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733542439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3733542439
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3520151977
Short name T98
Test name
Test status
Simulation time 2327560592 ps
CPU time 11.28 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:38 PM PDT 24
Peak memory 219064 kb
Host smart-3f1e1ed7-4ff2-421e-80c4-45cca3e8337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520151977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3520151977
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2645273214
Short name T145
Test name
Test status
Simulation time 813591579 ps
CPU time 23.22 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:55:49 PM PDT 24
Peak memory 219092 kb
Host smart-8b1d52c2-d22a-41f7-be42-0427c53a710d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645273214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2645273214
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3041541863
Short name T262
Test name
Test status
Simulation time 9841479399 ps
CPU time 140.28 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:57:41 PM PDT 24
Peak memory 228188 kb
Host smart-bc839433-e9f5-4719-903d-8ebf7e6ceeb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041541863 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3041541863
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3906231965
Short name T200
Test name
Test status
Simulation time 2750824536 ps
CPU time 8.2 seconds
Started Aug 17 04:55:45 PM PDT 24
Finished Aug 17 04:55:53 PM PDT 24
Peak memory 218368 kb
Host smart-8eb19c5a-bb6e-4634-bad6-47b864c9c199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906231965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3906231965
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3276967949
Short name T323
Test name
Test status
Simulation time 19483334310 ps
CPU time 311.9 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 05:01:01 PM PDT 24
Peak memory 237720 kb
Host smart-9b3355ee-4cc7-4a43-a24d-74e6da2376da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276967949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3276967949
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4198531973
Short name T39
Test name
Test status
Simulation time 2202323493 ps
CPU time 18.71 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:09 PM PDT 24
Peak memory 218876 kb
Host smart-0e4dd6b1-78b2-43ec-85d7-4de4822051aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198531973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4198531973
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4243120690
Short name T133
Test name
Test status
Simulation time 183160981 ps
CPU time 10.01 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 218840 kb
Host smart-e70d7fe6-a56c-4598-9cd3-d967f423e6bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243120690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4243120690
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3882438281
Short name T319
Test name
Test status
Simulation time 799441778 ps
CPU time 40.91 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 219112 kb
Host smart-cbfb6f1b-ea62-4481-9ae6-2987dcb09b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882438281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3882438281
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3344087833
Short name T131
Test name
Test status
Simulation time 2008540493 ps
CPU time 45.21 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:56:32 PM PDT 24
Peak memory 223296 kb
Host smart-7ee4533d-8421-4b6a-906b-54786efa4021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344087833 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3344087833
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.550302605
Short name T141
Test name
Test status
Simulation time 494401039 ps
CPU time 9.57 seconds
Started Aug 17 04:55:39 PM PDT 24
Finished Aug 17 04:55:49 PM PDT 24
Peak memory 218380 kb
Host smart-d3ca1f48-7905-4803-ab80-3c4e58f670bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550302605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.550302605
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1530609693
Short name T220
Test name
Test status
Simulation time 26407365769 ps
CPU time 158.18 seconds
Started Aug 17 04:55:37 PM PDT 24
Finished Aug 17 04:58:15 PM PDT 24
Peak memory 238792 kb
Host smart-a8dca389-0ea2-4680-b726-79eec0b5ff17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530609693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1530609693
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3863307309
Short name T240
Test name
Test status
Simulation time 346154737 ps
CPU time 18.28 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:09 PM PDT 24
Peak memory 218468 kb
Host smart-b6357af2-8ec1-4c85-a325-c8f01470af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863307309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3863307309
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.126010206
Short name T97
Test name
Test status
Simulation time 1017534027 ps
CPU time 11.29 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:01 PM PDT 24
Peak memory 218652 kb
Host smart-6d327683-d5ab-4a6c-a30d-aaaee6ff6c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126010206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.126010206
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1203057181
Short name T68
Test name
Test status
Simulation time 268804382 ps
CPU time 15.93 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:08 PM PDT 24
Peak memory 219084 kb
Host smart-e87d8f54-29e1-49a8-9870-dc8475efe207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203057181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1203057181
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.718760934
Short name T304
Test name
Test status
Simulation time 3001571309 ps
CPU time 32.82 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:56:21 PM PDT 24
Peak memory 223100 kb
Host smart-d3620661-ab4d-40f0-819c-0d69d5531f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718760934 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.718760934
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3897275975
Short name T130
Test name
Test status
Simulation time 248798618 ps
CPU time 9.32 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 218396 kb
Host smart-b164eb41-6f04-4d96-a578-4488c819384d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897275975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3897275975
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1019719106
Short name T298
Test name
Test status
Simulation time 7177063078 ps
CPU time 247.43 seconds
Started Aug 17 04:55:41 PM PDT 24
Finished Aug 17 04:59:49 PM PDT 24
Peak memory 240312 kb
Host smart-8c84762d-5626-47ba-9c93-5a9bf17dd77d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019719106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1019719106
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2945031900
Short name T255
Test name
Test status
Simulation time 524490943 ps
CPU time 21.63 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:12 PM PDT 24
Peak memory 218600 kb
Host smart-ab462162-a842-459e-9090-177b32537792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945031900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2945031900
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1182486392
Short name T286
Test name
Test status
Simulation time 4146328938 ps
CPU time 15.08 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 219152 kb
Host smart-42f72214-723a-4ad6-9079-85b064b369da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182486392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1182486392
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4245015526
Short name T334
Test name
Test status
Simulation time 2041322784 ps
CPU time 25.27 seconds
Started Aug 17 04:55:55 PM PDT 24
Finished Aug 17 04:56:20 PM PDT 24
Peak memory 219128 kb
Host smart-06519295-9e34-4bf0-9f42-8104acd38dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245015526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4245015526
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1021616086
Short name T171
Test name
Test status
Simulation time 1763617998 ps
CPU time 84.35 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:57:15 PM PDT 24
Peak memory 230512 kb
Host smart-16bb8b59-c26f-41e9-9b5e-78ea01bb23df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021616086 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1021616086
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3793042046
Short name T124
Test name
Test status
Simulation time 338765737 ps
CPU time 7.8 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:55:50 PM PDT 24
Peak memory 218360 kb
Host smart-ec9a5248-88b9-4647-b633-821475c0d063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793042046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3793042046
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.328932180
Short name T183
Test name
Test status
Simulation time 15460373936 ps
CPU time 203.64 seconds
Started Aug 17 04:55:53 PM PDT 24
Finished Aug 17 04:59:16 PM PDT 24
Peak memory 239848 kb
Host smart-fae9ec72-3b21-4015-89dd-0df7318f6677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328932180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.328932180
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.536047921
Short name T337
Test name
Test status
Simulation time 688547794 ps
CPU time 18.28 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:07 PM PDT 24
Peak memory 218544 kb
Host smart-c81e7291-6384-40f5-b68f-5b327bc48367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536047921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.536047921
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.783987115
Short name T178
Test name
Test status
Simulation time 723669382 ps
CPU time 9.96 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:55:57 PM PDT 24
Peak memory 219084 kb
Host smart-7524dd34-eb17-4ec4-bc03-af9e6e1ea8fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783987115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.783987115
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1100032736
Short name T227
Test name
Test status
Simulation time 2119956083 ps
CPU time 30.74 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 219360 kb
Host smart-25e17bdf-76e1-479c-8cea-59c9b1f4905b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100032736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1100032736
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4262811900
Short name T44
Test name
Test status
Simulation time 2060734980 ps
CPU time 77.84 seconds
Started Aug 17 04:55:41 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 223484 kb
Host smart-d6ab979c-a382-4769-98bc-7066af28ac8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262811900 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4262811900
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1161436352
Short name T346
Test name
Test status
Simulation time 345583995 ps
CPU time 8.05 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 218308 kb
Host smart-da3a51d1-00f1-4fda-b067-380835c14ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161436352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1161436352
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2999912323
Short name T33
Test name
Test status
Simulation time 4827915408 ps
CPU time 253.41 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 05:00:00 PM PDT 24
Peak memory 241836 kb
Host smart-32648928-d9f8-4d88-82ec-a0c4230aa92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999912323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2999912323
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4028477848
Short name T207
Test name
Test status
Simulation time 1380247779 ps
CPU time 18.39 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:56:01 PM PDT 24
Peak memory 218800 kb
Host smart-8363b61d-e011-4414-a750-d3d9eba0835b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028477848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4028477848
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.844873523
Short name T340
Test name
Test status
Simulation time 262437441 ps
CPU time 11.48 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:55:53 PM PDT 24
Peak memory 218820 kb
Host smart-c1795323-a1ee-4740-bc60-31065d6fad02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844873523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.844873523
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2739517661
Short name T16
Test name
Test status
Simulation time 299233794 ps
CPU time 13.31 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:55:55 PM PDT 24
Peak memory 219172 kb
Host smart-4aa3d210-07b1-4d5f-a751-fe78eb67fe12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739517661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2739517661
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4290954262
Short name T299
Test name
Test status
Simulation time 3437801841 ps
CPU time 70.93 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:57:02 PM PDT 24
Peak memory 227736 kb
Host smart-0d5feab8-7c83-4266-8051-9299c8865495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290954262 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4290954262
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3277052921
Short name T251
Test name
Test status
Simulation time 251181652 ps
CPU time 9.75 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:55:57 PM PDT 24
Peak memory 218648 kb
Host smart-90002a75-9bcf-41f6-bea6-08a012418356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277052921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3277052921
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3643634611
Short name T30
Test name
Test status
Simulation time 14405910142 ps
CPU time 225.76 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:59:28 PM PDT 24
Peak memory 241752 kb
Host smart-771453d0-7963-4080-bfd6-b5ed31f2f691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643634611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3643634611
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3385314039
Short name T313
Test name
Test status
Simulation time 1321348921 ps
CPU time 17.93 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:07 PM PDT 24
Peak memory 218788 kb
Host smart-fce8adf6-98ad-4109-b2e2-db9015461cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385314039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3385314039
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.988510085
Short name T284
Test name
Test status
Simulation time 710198306 ps
CPU time 10.53 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:02 PM PDT 24
Peak memory 218984 kb
Host smart-5621073f-ca55-4111-a778-03a9d7c7546e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988510085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.988510085
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3089486327
Short name T67
Test name
Test status
Simulation time 2093855202 ps
CPU time 25.22 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:56:12 PM PDT 24
Peak memory 219108 kb
Host smart-c3d539ee-41d4-4599-87bf-4223dffdcbd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089486327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3089486327
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3757552364
Short name T338
Test name
Test status
Simulation time 8876986082 ps
CPU time 158.17 seconds
Started Aug 17 04:55:44 PM PDT 24
Finished Aug 17 04:58:23 PM PDT 24
Peak memory 228920 kb
Host smart-b00d6ddf-3633-4dda-be10-91d61b0405d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757552364 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3757552364
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1184232201
Short name T163
Test name
Test status
Simulation time 176235654 ps
CPU time 7.73 seconds
Started Aug 17 04:55:54 PM PDT 24
Finished Aug 17 04:56:02 PM PDT 24
Peak memory 218396 kb
Host smart-9f6d8550-997f-4ba6-b9bc-01507218f656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184232201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1184232201
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1131181293
Short name T156
Test name
Test status
Simulation time 3099837263 ps
CPU time 211.72 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:59:23 PM PDT 24
Peak memory 218820 kb
Host smart-ad7f1697-4d8f-4559-993e-49dba77fc69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131181293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1131181293
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1527845269
Short name T4
Test name
Test status
Simulation time 519420053 ps
CPU time 21.53 seconds
Started Aug 17 04:55:39 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 218628 kb
Host smart-2db8048c-753e-4dea-b1c3-4b5248f8e189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527845269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1527845269
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2767228420
Short name T253
Test name
Test status
Simulation time 736269391 ps
CPU time 9.78 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:55:52 PM PDT 24
Peak memory 218928 kb
Host smart-fbd68555-c91b-4a0a-b32c-6dea30f6c831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767228420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2767228420
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2462567025
Short name T277
Test name
Test status
Simulation time 343795515 ps
CPU time 19.26 seconds
Started Aug 17 04:55:40 PM PDT 24
Finished Aug 17 04:55:59 PM PDT 24
Peak memory 219148 kb
Host smart-2b0483ce-22f9-4381-bf84-0662813e7664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462567025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2462567025
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1678217023
Short name T226
Test name
Test status
Simulation time 6158473755 ps
CPU time 117.65 seconds
Started Aug 17 04:55:44 PM PDT 24
Finished Aug 17 04:57:42 PM PDT 24
Peak memory 227836 kb
Host smart-a461cc9f-a147-4fd1-8e83-0bebc032511f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678217023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1678217023
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1197608221
Short name T53
Test name
Test status
Simulation time 307709510 ps
CPU time 9.41 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:55:56 PM PDT 24
Peak memory 218552 kb
Host smart-f80394e0-1df0-4f52-8248-1ffa9de8814d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197608221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1197608221
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.826861302
Short name T238
Test name
Test status
Simulation time 3871245479 ps
CPU time 197.19 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:59:05 PM PDT 24
Peak memory 228812 kb
Host smart-fe850ff4-86b2-42ee-873f-5f654dfb2e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826861302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.826861302
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2592117682
Short name T239
Test name
Test status
Simulation time 5484556443 ps
CPU time 21.62 seconds
Started Aug 17 04:55:42 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 218864 kb
Host smart-a12727c0-1a34-445c-9d9e-be13a753715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592117682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2592117682
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1017196185
Short name T218
Test name
Test status
Simulation time 704580149 ps
CPU time 11.71 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:56:03 PM PDT 24
Peak memory 218684 kb
Host smart-86cc2959-6ebd-4175-9117-1cea3673ea18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017196185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1017196185
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.373823724
Short name T158
Test name
Test status
Simulation time 7543552132 ps
CPU time 23.75 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:16 PM PDT 24
Peak memory 219248 kb
Host smart-38e14620-77c2-4912-ad1d-c33579dd5492
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373823724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.373823724
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.44932928
Short name T214
Test name
Test status
Simulation time 4774390916 ps
CPU time 235.89 seconds
Started Aug 17 04:55:45 PM PDT 24
Finished Aug 17 04:59:41 PM PDT 24
Peak memory 235588 kb
Host smart-949c4a6f-724e-4fd8-b90b-82616d5dc9d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44932928 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.44932928
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1611371010
Short name T138
Test name
Test status
Simulation time 254894001 ps
CPU time 9.51 seconds
Started Aug 17 04:55:56 PM PDT 24
Finished Aug 17 04:56:06 PM PDT 24
Peak memory 218308 kb
Host smart-554b1e7b-31ca-421a-8a4e-e99a71c4ec1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611371010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1611371010
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4090441175
Short name T352
Test name
Test status
Simulation time 1772008515 ps
CPU time 125.82 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:57:57 PM PDT 24
Peak memory 226952 kb
Host smart-afaf0744-d668-4a80-9cb0-e64f754d45da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090441175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4090441175
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4015232324
Short name T43
Test name
Test status
Simulation time 1013036785 ps
CPU time 21.82 seconds
Started Aug 17 04:55:54 PM PDT 24
Finished Aug 17 04:56:16 PM PDT 24
Peak memory 218828 kb
Host smart-4f2e96b3-355c-491d-b3c9-0de0c35dca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015232324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4015232324
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.159727695
Short name T134
Test name
Test status
Simulation time 2533145578 ps
CPU time 11.4 seconds
Started Aug 17 04:55:58 PM PDT 24
Finished Aug 17 04:56:10 PM PDT 24
Peak memory 219012 kb
Host smart-37cd2e4e-6ce4-4ab9-9157-a3170c7afeb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159727695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.159727695
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1923291361
Short name T71
Test name
Test status
Simulation time 2123630872 ps
CPU time 29.5 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 219088 kb
Host smart-50610de1-e309-4289-9056-2e1cee3bf1dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923291361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1923291361
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2141089086
Short name T36
Test name
Test status
Simulation time 3976424725 ps
CPU time 226.04 seconds
Started Aug 17 04:55:57 PM PDT 24
Finished Aug 17 04:59:44 PM PDT 24
Peak memory 226168 kb
Host smart-a7cc4e9c-d5a3-421d-bbda-73bdcc88187b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141089086 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2141089086
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3350660235
Short name T122
Test name
Test status
Simulation time 362153739 ps
CPU time 7.95 seconds
Started Aug 17 04:56:08 PM PDT 24
Finished Aug 17 04:56:16 PM PDT 24
Peak memory 218356 kb
Host smart-21a4aec2-2d5e-4b61-99d1-20d22b8f05f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350660235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3350660235
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4168619278
Short name T221
Test name
Test status
Simulation time 497321446 ps
CPU time 21.21 seconds
Started Aug 17 04:55:56 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 218508 kb
Host smart-3d292a3a-96d8-40cb-99ba-4c7a74e3fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168619278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4168619278
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2961016707
Short name T176
Test name
Test status
Simulation time 367504686 ps
CPU time 9.85 seconds
Started Aug 17 04:55:55 PM PDT 24
Finished Aug 17 04:56:05 PM PDT 24
Peak memory 218548 kb
Host smart-190620b5-1b21-4f0e-9460-3d38c0851aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961016707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2961016707
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.991097475
Short name T315
Test name
Test status
Simulation time 1491884043 ps
CPU time 23.1 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 219152 kb
Host smart-b9cfcfe8-57bd-4106-8dcf-0eb9a6a23a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991097475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.991097475
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2144809550
Short name T291
Test name
Test status
Simulation time 13776563508 ps
CPU time 49.02 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 235576 kb
Host smart-6f8fe159-0f90-42f8-91ed-d3d0017f76a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144809550 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2144809550
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1288029317
Short name T249
Test name
Test status
Simulation time 394252274 ps
CPU time 7.9 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:32 PM PDT 24
Peak memory 218276 kb
Host smart-cfb30aeb-f13d-4401-a9c0-2cd9a8a27c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288029317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1288029317
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4208243421
Short name T252
Test name
Test status
Simulation time 6011730563 ps
CPU time 325.8 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 05:00:50 PM PDT 24
Peak memory 225624 kb
Host smart-a5d6198c-89a0-4ff0-a02d-f2fa87cef667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208243421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4208243421
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2272423404
Short name T174
Test name
Test status
Simulation time 2064272923 ps
CPU time 22.31 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:48 PM PDT 24
Peak memory 218796 kb
Host smart-bcdf7541-a282-449b-884a-2f3a4e220825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272423404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2272423404
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1524828887
Short name T329
Test name
Test status
Simulation time 358167858 ps
CPU time 10.14 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218792 kb
Host smart-20a0e2dd-4cc5-40fa-9175-66f81fc6b14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524828887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1524828887
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.658872573
Short name T22
Test name
Test status
Simulation time 230368257 ps
CPU time 116.88 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:57:19 PM PDT 24
Peak memory 238952 kb
Host smart-afa41df2-57df-4d6d-8df0-67f053699959
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658872573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.658872573
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.133978015
Short name T8
Test name
Test status
Simulation time 318964408 ps
CPU time 11.4 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:39 PM PDT 24
Peak memory 219036 kb
Host smart-6909bc5c-2cc5-4e65-ba9d-fecc01c54d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133978015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.133978015
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3418585607
Short name T295
Test name
Test status
Simulation time 8580741170 ps
CPU time 50.34 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:56:14 PM PDT 24
Peak memory 219220 kb
Host smart-1eb41400-51fd-4717-8c96-b0c1af4bafbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418585607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3418585607
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3825068039
Short name T6
Test name
Test status
Simulation time 591692706 ps
CPU time 7.91 seconds
Started Aug 17 04:55:49 PM PDT 24
Finished Aug 17 04:55:57 PM PDT 24
Peak memory 218376 kb
Host smart-ca8cb7c4-f58b-45bf-b6ff-0340054ef08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825068039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3825068039
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2399129144
Short name T32
Test name
Test status
Simulation time 8181239046 ps
CPU time 414.49 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 05:02:45 PM PDT 24
Peak memory 236896 kb
Host smart-ae1dfabf-5982-48b0-9012-5a1d35956774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399129144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2399129144
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2813866123
Short name T228
Test name
Test status
Simulation time 501090360 ps
CPU time 21.46 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 218548 kb
Host smart-40c22c4a-e27d-4ac5-96d4-a394c2d72066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813866123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2813866123
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2912364269
Short name T142
Test name
Test status
Simulation time 1835792206 ps
CPU time 11.49 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:56:03 PM PDT 24
Peak memory 218868 kb
Host smart-d3560c39-78a4-4ada-8bf7-bcede8882f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912364269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2912364269
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4261772924
Short name T70
Test name
Test status
Simulation time 878679335 ps
CPU time 13.98 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:56:02 PM PDT 24
Peak memory 219032 kb
Host smart-e7b01824-1d01-4b37-987b-9e8cd7c6f8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261772924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4261772924
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1526110481
Short name T322
Test name
Test status
Simulation time 34568834990 ps
CPU time 219.1 seconds
Started Aug 17 04:56:04 PM PDT 24
Finished Aug 17 04:59:43 PM PDT 24
Peak memory 235640 kb
Host smart-ab125dce-d66e-46a1-b756-381c9d1a296f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526110481 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1526110481
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1228780162
Short name T237
Test name
Test status
Simulation time 262661714 ps
CPU time 9.27 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:55:56 PM PDT 24
Peak memory 219032 kb
Host smart-99f82d36-06f9-49e0-9d04-7eeaffcb9dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228780162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1228780162
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1500184511
Short name T2
Test name
Test status
Simulation time 10122982470 ps
CPU time 118.6 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:57:46 PM PDT 24
Peak memory 240352 kb
Host smart-567ca4f0-ce66-4fc5-8b1b-8907e149ac50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500184511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1500184511
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3042162602
Short name T303
Test name
Test status
Simulation time 1324196641 ps
CPU time 18.37 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:56:10 PM PDT 24
Peak memory 218824 kb
Host smart-f649e50f-800e-4c56-97f2-f130e54f4d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042162602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3042162602
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3451721146
Short name T201
Test name
Test status
Simulation time 361612917 ps
CPU time 10.55 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 218992 kb
Host smart-d69ed3c7-dee0-400d-bdc8-43c7365d6468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451721146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3451721146
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1482062364
Short name T272
Test name
Test status
Simulation time 3113103023 ps
CPU time 30.19 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 219248 kb
Host smart-c6e1dc0b-050d-44bb-bdb5-b4c67e4f4555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482062364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1482062364
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3969652584
Short name T254
Test name
Test status
Simulation time 2358097819 ps
CPU time 115.33 seconds
Started Aug 17 04:55:57 PM PDT 24
Finished Aug 17 04:57:53 PM PDT 24
Peak memory 223808 kb
Host smart-86854c9c-4a49-4175-adc8-21069a660107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969652584 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3969652584
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2784644362
Short name T88
Test name
Test status
Simulation time 1032303887 ps
CPU time 7.97 seconds
Started Aug 17 04:55:51 PM PDT 24
Finished Aug 17 04:55:59 PM PDT 24
Peak memory 218336 kb
Host smart-ec09a04f-63a0-437d-bdf6-a8ec285f272f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784644362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2784644362
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1829757447
Short name T311
Test name
Test status
Simulation time 8471742948 ps
CPU time 264.93 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 05:00:13 PM PDT 24
Peak memory 237720 kb
Host smart-fc6ee926-5569-4bf9-bddb-5b57a32e86e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829757447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1829757447
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3646400391
Short name T120
Test name
Test status
Simulation time 2067032085 ps
CPU time 21.34 seconds
Started Aug 17 04:55:53 PM PDT 24
Finished Aug 17 04:56:14 PM PDT 24
Peak memory 218832 kb
Host smart-aa0a4519-ad3d-47eb-a14b-5ae3e5a18fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646400391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3646400391
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3141557019
Short name T289
Test name
Test status
Simulation time 187105890 ps
CPU time 9.99 seconds
Started Aug 17 04:55:53 PM PDT 24
Finished Aug 17 04:56:03 PM PDT 24
Peak memory 218856 kb
Host smart-c02ed179-e319-4454-9be0-4f5a56d8e119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141557019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3141557019
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4128941676
Short name T206
Test name
Test status
Simulation time 2013336587 ps
CPU time 25.09 seconds
Started Aug 17 04:55:58 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 219112 kb
Host smart-bfdb4cf4-d071-4829-ab01-7320ca02fc38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128941676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4128941676
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2182984292
Short name T127
Test name
Test status
Simulation time 5026652357 ps
CPU time 189.66 seconds
Started Aug 17 04:56:01 PM PDT 24
Finished Aug 17 04:59:11 PM PDT 24
Peak memory 234068 kb
Host smart-91cd0670-d3aa-4e93-8b96-4995846b6f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182984292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2182984292
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1132393579
Short name T129
Test name
Test status
Simulation time 175008246 ps
CPU time 8.1 seconds
Started Aug 17 04:55:54 PM PDT 24
Finished Aug 17 04:56:03 PM PDT 24
Peak memory 218328 kb
Host smart-4616b948-e8fc-4912-bac5-90394169a85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132393579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1132393579
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4207299305
Short name T285
Test name
Test status
Simulation time 18883767895 ps
CPU time 174.35 seconds
Started Aug 17 04:55:46 PM PDT 24
Finished Aug 17 04:58:41 PM PDT 24
Peak memory 233760 kb
Host smart-885b7d13-bfd8-4254-ab23-ce03ff4279b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207299305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4207299305
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.391702027
Short name T128
Test name
Test status
Simulation time 511756669 ps
CPU time 22.45 seconds
Started Aug 17 04:55:55 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 218536 kb
Host smart-597df1c6-10f7-49a9-ab4c-a7805f009da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391702027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.391702027
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3701401874
Short name T250
Test name
Test status
Simulation time 189061604 ps
CPU time 9.76 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:55:58 PM PDT 24
Peak memory 218872 kb
Host smart-c7b76435-485b-4988-b497-5ffa5e0ffbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701401874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3701401874
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2582330961
Short name T199
Test name
Test status
Simulation time 3267171818 ps
CPU time 44.79 seconds
Started Aug 17 04:56:03 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 219164 kb
Host smart-7de71862-36dd-4941-8853-ededb553d6f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582330961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2582330961
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3651085083
Short name T248
Test name
Test status
Simulation time 8581162323 ps
CPU time 220.27 seconds
Started Aug 17 04:55:50 PM PDT 24
Finished Aug 17 04:59:30 PM PDT 24
Peak memory 226876 kb
Host smart-6956f904-0972-46f9-9f79-e7fae7d7e635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651085083 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3651085083
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1682009741
Short name T162
Test name
Test status
Simulation time 990111421 ps
CPU time 9.93 seconds
Started Aug 17 04:56:08 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 218364 kb
Host smart-e7dbfb0f-db04-404b-b9ef-a8f22ac618cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682009741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1682009741
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2590854687
Short name T350
Test name
Test status
Simulation time 11535703089 ps
CPU time 337.47 seconds
Started Aug 17 04:55:47 PM PDT 24
Finished Aug 17 05:01:25 PM PDT 24
Peak memory 233648 kb
Host smart-e569cbee-8ccf-4d3b-8a2e-f8ecc180c41f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590854687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2590854687
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3566073175
Short name T34
Test name
Test status
Simulation time 1031655539 ps
CPU time 21.99 seconds
Started Aug 17 04:55:48 PM PDT 24
Finished Aug 17 04:56:10 PM PDT 24
Peak memory 218560 kb
Host smart-d73cfcd8-e964-4aeb-bfe0-55d7d7c07131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566073175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3566073175
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3167853671
Short name T356
Test name
Test status
Simulation time 1023903242 ps
CPU time 11.39 seconds
Started Aug 17 04:55:52 PM PDT 24
Finished Aug 17 04:56:03 PM PDT 24
Peak memory 218988 kb
Host smart-cfeadfa2-6626-46c1-bd7f-c7e8100e9d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167853671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3167853671
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3937204262
Short name T336
Test name
Test status
Simulation time 819293418 ps
CPU time 37.94 seconds
Started Aug 17 04:55:53 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 219160 kb
Host smart-c9183f54-2b4c-46fb-9f8c-69cb68656825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937204262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3937204262
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2420063460
Short name T355
Test name
Test status
Simulation time 1776597153 ps
CPU time 77.85 seconds
Started Aug 17 04:56:09 PM PDT 24
Finished Aug 17 04:57:27 PM PDT 24
Peak memory 223776 kb
Host smart-d617a73e-8f90-4e38-818c-997e01893f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420063460 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2420063460
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.172149801
Short name T318
Test name
Test status
Simulation time 249195818 ps
CPU time 9.76 seconds
Started Aug 17 04:56:03 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 218380 kb
Host smart-59834705-1ac9-4fdf-9e9f-ef5355beee9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172149801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.172149801
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4179479098
Short name T28
Test name
Test status
Simulation time 20816868734 ps
CPU time 264.39 seconds
Started Aug 17 04:56:02 PM PDT 24
Finished Aug 17 05:00:27 PM PDT 24
Peak memory 244964 kb
Host smart-b4b6b449-d000-4274-aa07-e387ea72f358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179479098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4179479098
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1404828433
Short name T166
Test name
Test status
Simulation time 2066963116 ps
CPU time 28.81 seconds
Started Aug 17 04:56:01 PM PDT 24
Finished Aug 17 04:56:30 PM PDT 24
Peak memory 219072 kb
Host smart-f8515b7a-63b4-4ff1-a233-ab5e5d5e5727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404828433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1404828433
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.855435788
Short name T24
Test name
Test status
Simulation time 1828298578 ps
CPU time 11.74 seconds
Started Aug 17 04:56:02 PM PDT 24
Finished Aug 17 04:56:14 PM PDT 24
Peak memory 218880 kb
Host smart-c5d5402a-0953-4585-a2fa-510bf48813db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855435788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.855435788
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3380247498
Short name T69
Test name
Test status
Simulation time 342880392 ps
CPU time 19.11 seconds
Started Aug 17 04:56:04 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 219196 kb
Host smart-02d7c9a6-63df-46da-9e67-cd160d5431f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380247498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3380247498
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2241021
Short name T151
Test name
Test status
Simulation time 11498690968 ps
CPU time 150.68 seconds
Started Aug 17 04:56:05 PM PDT 24
Finished Aug 17 04:58:36 PM PDT 24
Peak memory 235116 kb
Host smart-7f51f85d-9f2f-4dba-976d-2745edccd39c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241021 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2241021
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3451731514
Short name T219
Test name
Test status
Simulation time 175034046 ps
CPU time 7.94 seconds
Started Aug 17 04:56:05 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 218404 kb
Host smart-dc1dbbe5-5f32-4713-a112-9673c560b707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451731514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3451731514
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2291992711
Short name T135
Test name
Test status
Simulation time 28556257123 ps
CPU time 241.01 seconds
Started Aug 17 04:56:08 PM PDT 24
Finished Aug 17 05:00:09 PM PDT 24
Peak memory 240020 kb
Host smart-6d2f3700-bc93-4be7-a25b-f5cdead9c560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291992711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2291992711
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.623611577
Short name T324
Test name
Test status
Simulation time 420895431 ps
CPU time 18.46 seconds
Started Aug 17 04:56:03 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 218552 kb
Host smart-6dd97664-54f1-49d2-975d-335e97b43059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623611577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.623611577
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.415004930
Short name T126
Test name
Test status
Simulation time 352008040 ps
CPU time 10.04 seconds
Started Aug 17 04:56:02 PM PDT 24
Finished Aug 17 04:56:12 PM PDT 24
Peak memory 218784 kb
Host smart-b0987af0-37bf-414c-a78b-df3b48d51356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415004930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.415004930
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1339649629
Short name T339
Test name
Test status
Simulation time 396213020 ps
CPU time 14.79 seconds
Started Aug 17 04:56:09 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 219060 kb
Host smart-12d96762-ec9d-4562-9cf7-ccea5dc26bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339649629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1339649629
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4175351284
Short name T46
Test name
Test status
Simulation time 1726888251 ps
CPU time 29.28 seconds
Started Aug 17 04:56:08 PM PDT 24
Finished Aug 17 04:56:37 PM PDT 24
Peak memory 222884 kb
Host smart-4f4ab145-21e7-4ea8-94e4-0dd3452634af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175351284 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4175351284
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2070546244
Short name T209
Test name
Test status
Simulation time 1000420251 ps
CPU time 13.04 seconds
Started Aug 17 04:56:07 PM PDT 24
Finished Aug 17 04:56:20 PM PDT 24
Peak memory 218280 kb
Host smart-76eb3286-d278-420b-9194-175d070e5bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070546244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2070546244
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.546542487
Short name T15
Test name
Test status
Simulation time 4940979867 ps
CPU time 133.65 seconds
Started Aug 17 04:56:03 PM PDT 24
Finished Aug 17 04:58:17 PM PDT 24
Peak memory 227776 kb
Host smart-767fa429-c495-46d2-aa68-82d62b4046f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546542487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.546542487
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1232433989
Short name T230
Test name
Test status
Simulation time 346972283 ps
CPU time 18.56 seconds
Started Aug 17 04:56:05 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 218464 kb
Host smart-a3c301af-f8a7-4aa8-aafe-c880aa9467c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232433989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1232433989
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3252266605
Short name T320
Test name
Test status
Simulation time 1016454118 ps
CPU time 11.22 seconds
Started Aug 17 04:56:06 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 218944 kb
Host smart-24d302e0-b8d3-4f01-8ed9-fb1ab35f5500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252266605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3252266605
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4199983186
Short name T179
Test name
Test status
Simulation time 532196761 ps
CPU time 27.51 seconds
Started Aug 17 04:56:08 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 219192 kb
Host smart-36ebc482-df62-435f-ace7-2882282cdf00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199983186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4199983186
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2970029107
Short name T47
Test name
Test status
Simulation time 41311943837 ps
CPU time 134.46 seconds
Started Aug 17 04:56:05 PM PDT 24
Finished Aug 17 04:58:19 PM PDT 24
Peak memory 235608 kb
Host smart-22744007-54f5-494f-bd7d-ce6b90cc3e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970029107 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2970029107
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4251526788
Short name T140
Test name
Test status
Simulation time 250667340 ps
CPU time 9.37 seconds
Started Aug 17 04:56:02 PM PDT 24
Finished Aug 17 04:56:12 PM PDT 24
Peak memory 218360 kb
Host smart-c5200650-6e61-4430-b3a9-34e5b94120f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251526788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4251526788
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1829808964
Short name T159
Test name
Test status
Simulation time 2125809590 ps
CPU time 120.82 seconds
Started Aug 17 04:56:10 PM PDT 24
Finished Aug 17 04:58:11 PM PDT 24
Peak memory 226316 kb
Host smart-059897e2-85a4-4145-9c4c-382cae4a4bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829808964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1829808964
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1486792809
Short name T205
Test name
Test status
Simulation time 1591435374 ps
CPU time 21.7 seconds
Started Aug 17 04:56:10 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 218848 kb
Host smart-74d964ff-80c6-4f29-96c7-94393efca6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486792809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1486792809
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.699185099
Short name T172
Test name
Test status
Simulation time 1033000760 ps
CPU time 11.68 seconds
Started Aug 17 04:56:07 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 218880 kb
Host smart-de4a38a3-ea01-4eb2-8a26-45ec1e93b817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699185099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.699185099
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3624921822
Short name T312
Test name
Test status
Simulation time 757936873 ps
CPU time 26.92 seconds
Started Aug 17 04:56:04 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 219088 kb
Host smart-85429ebd-020e-4869-8dd5-bd211a022639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624921822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3624921822
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2796917763
Short name T90
Test name
Test status
Simulation time 13233572137 ps
CPU time 312.4 seconds
Started Aug 17 04:55:59 PM PDT 24
Finished Aug 17 05:01:12 PM PDT 24
Peak memory 235676 kb
Host smart-627c6d1d-9540-4a5c-95f2-fa857c620e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796917763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2796917763
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4128952641
Short name T316
Test name
Test status
Simulation time 249719468 ps
CPU time 9.38 seconds
Started Aug 17 04:56:07 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 218260 kb
Host smart-11bbe260-776b-4b35-a3a4-cc44d8e1a3ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128952641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4128952641
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2718762412
Short name T273
Test name
Test status
Simulation time 30783454664 ps
CPU time 206.79 seconds
Started Aug 17 04:56:06 PM PDT 24
Finished Aug 17 04:59:33 PM PDT 24
Peak memory 235608 kb
Host smart-2e046e22-559b-4682-8312-5fdefe13ce35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718762412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2718762412
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3731855427
Short name T169
Test name
Test status
Simulation time 1379836120 ps
CPU time 18.39 seconds
Started Aug 17 04:56:09 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 218844 kb
Host smart-50240ca8-5144-4a08-a55c-f9b51c2858cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731855427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3731855427
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3261683493
Short name T326
Test name
Test status
Simulation time 265585335 ps
CPU time 10.07 seconds
Started Aug 17 04:56:11 PM PDT 24
Finished Aug 17 04:56:21 PM PDT 24
Peak memory 218696 kb
Host smart-aef248ec-d5a8-4052-b3ed-6916d549912e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261683493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3261683493
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4251464554
Short name T13
Test name
Test status
Simulation time 1438599058 ps
CPU time 19.2 seconds
Started Aug 17 04:56:05 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 219132 kb
Host smart-07cf814d-382d-415a-a808-de0de84e157a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251464554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4251464554
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4045259088
Short name T167
Test name
Test status
Simulation time 10024826678 ps
CPU time 209.97 seconds
Started Aug 17 04:56:02 PM PDT 24
Finished Aug 17 04:59:32 PM PDT 24
Peak memory 225636 kb
Host smart-bb1b7195-a4e8-48b8-a8dc-32c9c33d95b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045259088 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4045259088
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.942196681
Short name T188
Test name
Test status
Simulation time 338517888 ps
CPU time 8.07 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218396 kb
Host smart-005b0d95-e741-4134-99aa-aeb8f87befcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942196681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.942196681
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1799623467
Short name T184
Test name
Test status
Simulation time 21341234237 ps
CPU time 252.08 seconds
Started Aug 17 04:55:28 PM PDT 24
Finished Aug 17 04:59:46 PM PDT 24
Peak memory 236660 kb
Host smart-a4b3914d-5ff5-46de-8b8d-2c3848f153d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799623467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1799623467
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3483145349
Short name T259
Test name
Test status
Simulation time 678882028 ps
CPU time 18.27 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:40 PM PDT 24
Peak memory 218808 kb
Host smart-76bb6761-30ee-446c-8213-60919c78e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483145349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3483145349
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1486174867
Short name T231
Test name
Test status
Simulation time 930547843 ps
CPU time 10.33 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:32 PM PDT 24
Peak memory 218768 kb
Host smart-d10b03c1-7959-4572-ac32-70e7b955c705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486174867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1486174867
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3447471459
Short name T216
Test name
Test status
Simulation time 271494282 ps
CPU time 12.13 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:33 PM PDT 24
Peak memory 219100 kb
Host smart-3dc4e8f4-cf4c-40a3-9a4c-3e31af943091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447471459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3447471459
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3153631631
Short name T232
Test name
Test status
Simulation time 807357856 ps
CPU time 33.68 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:56:00 PM PDT 24
Peak memory 219152 kb
Host smart-281e64b6-5e7e-4346-acd4-de7445bd3b48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153631631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3153631631
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4195890369
Short name T193
Test name
Test status
Simulation time 23228179957 ps
CPU time 73.08 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 226240 kb
Host smart-9f23a24c-a339-4976-85c7-c203b32c7c9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195890369 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4195890369
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.198381688
Short name T332
Test name
Test status
Simulation time 251772848 ps
CPU time 9.47 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 218432 kb
Host smart-e06e150d-0544-46e6-bd04-46c725e2fd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198381688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.198381688
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2034958735
Short name T271
Test name
Test status
Simulation time 12260081786 ps
CPU time 298.58 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 05:00:23 PM PDT 24
Peak memory 241340 kb
Host smart-1a8e2e0d-936d-43b9-b3bb-b6a17a920c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034958735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2034958735
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3344080406
Short name T37
Test name
Test status
Simulation time 728651658 ps
CPU time 21.13 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:55:44 PM PDT 24
Peak memory 218924 kb
Host smart-26961abd-c1b8-43ef-96e3-d4c988d5d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344080406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3344080406
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.122186627
Short name T290
Test name
Test status
Simulation time 835802291 ps
CPU time 9.98 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:31 PM PDT 24
Peak memory 218824 kb
Host smart-d50b25d3-5a2d-42d2-b2fb-0a21f6a02f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122186627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.122186627
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.44823247
Short name T54
Test name
Test status
Simulation time 181373697 ps
CPU time 10.02 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:55:34 PM PDT 24
Peak memory 219136 kb
Host smart-75d5c7bf-56c5-40a4-a46b-4c1d511a2305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44823247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.44823247
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3972685527
Short name T86
Test name
Test status
Simulation time 1365514836 ps
CPU time 26.93 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:52 PM PDT 24
Peak memory 219076 kb
Host smart-c7431aa6-0cd9-488e-8553-939e8fb4bee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972685527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3972685527
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2289674630
Short name T260
Test name
Test status
Simulation time 7340229238 ps
CPU time 77.85 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 234836 kb
Host smart-24ae58f9-0cbe-4211-bdcd-9f5bec979d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289674630 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2289674630
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3507842583
Short name T173
Test name
Test status
Simulation time 338894359 ps
CPU time 7.84 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:28 PM PDT 24
Peak memory 218312 kb
Host smart-651dcb5c-2bd2-44ce-991d-7b00895c95e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507842583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3507842583
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2224896366
Short name T308
Test name
Test status
Simulation time 4418542164 ps
CPU time 190.4 seconds
Started Aug 17 04:55:31 PM PDT 24
Finished Aug 17 04:58:41 PM PDT 24
Peak memory 237568 kb
Host smart-fc9a6330-8eb4-4cd3-896d-7bcd0dc60fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224896366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2224896366
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3119935278
Short name T125
Test name
Test status
Simulation time 1147427156 ps
CPU time 18.5 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:46 PM PDT 24
Peak memory 218688 kb
Host smart-0422aac6-9f5d-48f5-b402-a18a62cec9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119935278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3119935278
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3432068420
Short name T342
Test name
Test status
Simulation time 179831624 ps
CPU time 10.04 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:35 PM PDT 24
Peak memory 217560 kb
Host smart-33f85515-8d26-4e18-8de5-e216b191408b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432068420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3432068420
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2738287939
Short name T102
Test name
Test status
Simulation time 992521760 ps
CPU time 15.45 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:43 PM PDT 24
Peak memory 219140 kb
Host smart-f94b6865-68cd-4e20-ae6b-465118e5b844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738287939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2738287939
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3824323190
Short name T55
Test name
Test status
Simulation time 534093252 ps
CPU time 36.97 seconds
Started Aug 17 04:55:24 PM PDT 24
Finished Aug 17 04:56:01 PM PDT 24
Peak memory 219092 kb
Host smart-aec65b8c-b47a-4b9f-94b4-ebeb76302eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824323190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3824323190
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4117650018
Short name T187
Test name
Test status
Simulation time 1668200263 ps
CPU time 77.56 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:56:39 PM PDT 24
Peak memory 223664 kb
Host smart-d93cfa3c-0fc2-40cb-9474-22d599ac8b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117650018 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4117650018
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3224272893
Short name T190
Test name
Test status
Simulation time 992097835 ps
CPU time 9.39 seconds
Started Aug 17 04:55:34 PM PDT 24
Finished Aug 17 04:55:43 PM PDT 24
Peak memory 218316 kb
Host smart-9823d541-bc55-44ab-bf45-a1c30eec83cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224272893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3224272893
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1556460470
Short name T147
Test name
Test status
Simulation time 11434219180 ps
CPU time 176.52 seconds
Started Aug 17 04:55:22 PM PDT 24
Finished Aug 17 04:58:18 PM PDT 24
Peak memory 241452 kb
Host smart-1b521a38-4081-4313-bb9c-6b88f306af56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556460470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1556460470
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3606845569
Short name T233
Test name
Test status
Simulation time 1034310096 ps
CPU time 21.42 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:49 PM PDT 24
Peak memory 217796 kb
Host smart-d1d1e52a-f0e9-485b-952f-ff66324e3b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606845569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3606845569
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.870532318
Short name T99
Test name
Test status
Simulation time 356298951 ps
CPU time 9.86 seconds
Started Aug 17 04:55:18 PM PDT 24
Finished Aug 17 04:55:28 PM PDT 24
Peak memory 218612 kb
Host smart-a4e45f4f-bdd0-40d0-a6b3-083fec9db2e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870532318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.870532318
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1576313928
Short name T212
Test name
Test status
Simulation time 1015874933 ps
CPU time 11.49 seconds
Started Aug 17 04:55:21 PM PDT 24
Finished Aug 17 04:55:32 PM PDT 24
Peak memory 219080 kb
Host smart-e8ef19e6-fcd7-432f-8643-a4f57e426732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576313928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1576313928
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.308520267
Short name T341
Test name
Test status
Simulation time 558131912 ps
CPU time 12.57 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:55:35 PM PDT 24
Peak memory 219112 kb
Host smart-0f88c9c1-88b5-4a75-a2de-22bf4fa14266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308520267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.308520267
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1740203643
Short name T25
Test name
Test status
Simulation time 2052976452 ps
CPU time 114.68 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:57:17 PM PDT 24
Peak memory 228180 kb
Host smart-72abb925-d98a-4fe8-a984-19c83aeda698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740203643 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1740203643
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2166235044
Short name T100
Test name
Test status
Simulation time 259448696 ps
CPU time 9.41 seconds
Started Aug 17 04:55:27 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218372 kb
Host smart-d3642a37-547b-42ec-a0f3-c710b2a7b2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166235044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2166235044
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.659411993
Short name T348
Test name
Test status
Simulation time 2157926611 ps
CPU time 148.88 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:57:52 PM PDT 24
Peak memory 239100 kb
Host smart-db07cfd0-e3a7-4e5d-9f37-255dcfd0a1ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659411993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.659411993
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2530344880
Short name T229
Test name
Test status
Simulation time 512777296 ps
CPU time 21.24 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:55:44 PM PDT 24
Peak memory 218472 kb
Host smart-e9f512af-eaf0-4c39-ba1f-c75b56dba6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530344880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2530344880
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.625468233
Short name T279
Test name
Test status
Simulation time 266350146 ps
CPU time 11.91 seconds
Started Aug 17 04:55:25 PM PDT 24
Finished Aug 17 04:55:37 PM PDT 24
Peak memory 218632 kb
Host smart-54a426f1-fc69-4613-a5a5-89be8f404fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625468233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.625468233
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1537578909
Short name T177
Test name
Test status
Simulation time 696446117 ps
CPU time 10.04 seconds
Started Aug 17 04:55:20 PM PDT 24
Finished Aug 17 04:55:30 PM PDT 24
Peak memory 219072 kb
Host smart-164a5b34-94fb-4638-9d7f-b89300a64633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537578909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1537578909
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1883871445
Short name T283
Test name
Test status
Simulation time 1633236298 ps
CPU time 37.22 seconds
Started Aug 17 04:55:26 PM PDT 24
Finished Aug 17 04:56:04 PM PDT 24
Peak memory 219124 kb
Host smart-df74d3bb-ef73-43b1-9dff-51048f3f1d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883871445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1883871445
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3594340514
Short name T11
Test name
Test status
Simulation time 27916293786 ps
CPU time 90.02 seconds
Started Aug 17 04:55:23 PM PDT 24
Finished Aug 17 04:56:53 PM PDT 24
Peak memory 234300 kb
Host smart-ea7ff0ef-12aa-4297-9fd7-56a227a7eb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594340514 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3594340514
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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