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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 96.89 91.99 97.68 100.00 98.28 98.05 99.06


Total test records in report: 458
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T296 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3699354536 Aug 19 04:32:27 PM PDT 24 Aug 19 04:35:03 PM PDT 24 2767160522 ps
T297 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2666375685 Aug 19 04:31:48 PM PDT 24 Aug 19 04:32:43 PM PDT 24 1200013710 ps
T298 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.930646529 Aug 19 04:31:57 PM PDT 24 Aug 19 04:35:20 PM PDT 24 2745634741 ps
T299 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.653786729 Aug 19 04:31:44 PM PDT 24 Aug 19 04:34:29 PM PDT 24 2999747876 ps
T300 /workspace/coverage/default/32.rom_ctrl_stress_all.2297179898 Aug 19 04:31:56 PM PDT 24 Aug 19 04:32:28 PM PDT 24 562894714 ps
T301 /workspace/coverage/default/14.rom_ctrl_stress_all.1324157378 Aug 19 04:31:50 PM PDT 24 Aug 19 04:32:20 PM PDT 24 566791430 ps
T302 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1540349968 Aug 19 04:32:00 PM PDT 24 Aug 19 04:37:07 PM PDT 24 21620614998 ps
T303 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1972747611 Aug 19 04:32:59 PM PDT 24 Aug 19 04:34:41 PM PDT 24 2961840862 ps
T304 /workspace/coverage/default/3.rom_ctrl_smoke.1486140794 Aug 19 04:31:42 PM PDT 24 Aug 19 04:31:54 PM PDT 24 271111737 ps
T305 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1921443259 Aug 19 04:32:57 PM PDT 24 Aug 19 04:36:31 PM PDT 24 60731818114 ps
T306 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.525645894 Aug 19 04:33:08 PM PDT 24 Aug 19 04:36:23 PM PDT 24 5574346891 ps
T307 /workspace/coverage/default/8.rom_ctrl_stress_all.3140374236 Aug 19 04:31:44 PM PDT 24 Aug 19 04:32:06 PM PDT 24 358496890 ps
T308 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.642867291 Aug 19 04:32:05 PM PDT 24 Aug 19 04:32:56 PM PDT 24 2621349484 ps
T309 /workspace/coverage/default/43.rom_ctrl_stress_all.1208809188 Aug 19 04:32:10 PM PDT 24 Aug 19 04:32:32 PM PDT 24 367155781 ps
T310 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.221121380 Aug 19 04:31:58 PM PDT 24 Aug 19 04:35:16 PM PDT 24 4443950050 ps
T311 /workspace/coverage/default/2.rom_ctrl_smoke.3608384639 Aug 19 04:31:45 PM PDT 24 Aug 19 04:31:55 PM PDT 24 673923707 ps
T312 /workspace/coverage/default/48.rom_ctrl_alert_test.1034657398 Aug 19 04:32:10 PM PDT 24 Aug 19 04:32:18 PM PDT 24 1503713577 ps
T313 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3676277039 Aug 19 04:32:00 PM PDT 24 Aug 19 04:32:11 PM PDT 24 2319868608 ps
T314 /workspace/coverage/default/10.rom_ctrl_alert_test.2722238836 Aug 19 04:31:57 PM PDT 24 Aug 19 04:32:07 PM PDT 24 290074622 ps
T315 /workspace/coverage/default/22.rom_ctrl_stress_all.532553501 Aug 19 04:32:02 PM PDT 24 Aug 19 04:32:23 PM PDT 24 407453385 ps
T316 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1955962136 Aug 19 04:31:48 PM PDT 24 Aug 19 04:32:07 PM PDT 24 718755729 ps
T317 /workspace/coverage/default/46.rom_ctrl_stress_all.1897596683 Aug 19 04:32:13 PM PDT 24 Aug 19 04:32:44 PM PDT 24 574134077 ps
T318 /workspace/coverage/default/41.rom_ctrl_alert_test.1265285379 Aug 19 04:32:10 PM PDT 24 Aug 19 04:32:18 PM PDT 24 338469992 ps
T319 /workspace/coverage/default/26.rom_ctrl_alert_test.2211854445 Aug 19 04:32:08 PM PDT 24 Aug 19 04:32:16 PM PDT 24 222453015 ps
T320 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2408967320 Aug 19 04:32:15 PM PDT 24 Aug 19 04:34:13 PM PDT 24 2347461646 ps
T321 /workspace/coverage/default/3.rom_ctrl_alert_test.3962179098 Aug 19 04:31:52 PM PDT 24 Aug 19 04:32:00 PM PDT 24 169156690 ps
T322 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4012657292 Aug 19 04:31:59 PM PDT 24 Aug 19 04:34:34 PM PDT 24 18321058069 ps
T323 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1208450926 Aug 19 04:31:35 PM PDT 24 Aug 19 04:31:56 PM PDT 24 1986893351 ps
T324 /workspace/coverage/default/7.rom_ctrl_alert_test.1452230030 Aug 19 04:31:46 PM PDT 24 Aug 19 04:32:01 PM PDT 24 496314001 ps
T325 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3211666306 Aug 19 04:32:02 PM PDT 24 Aug 19 04:36:11 PM PDT 24 19081091535 ps
T326 /workspace/coverage/default/0.rom_ctrl_stress_all.1938118989 Aug 19 04:31:44 PM PDT 24 Aug 19 04:32:14 PM PDT 24 534682219 ps
T327 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1366926032 Aug 19 04:32:09 PM PDT 24 Aug 19 04:34:53 PM PDT 24 4555292843 ps
T328 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2750223017 Aug 19 04:32:15 PM PDT 24 Aug 19 04:33:05 PM PDT 24 5046415032 ps
T329 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.183873529 Aug 19 04:32:53 PM PDT 24 Aug 19 04:33:21 PM PDT 24 1999797010 ps
T330 /workspace/coverage/default/5.rom_ctrl_stress_all.494937508 Aug 19 04:31:50 PM PDT 24 Aug 19 04:32:10 PM PDT 24 1085687075 ps
T331 /workspace/coverage/default/11.rom_ctrl_stress_all.1074145823 Aug 19 04:31:55 PM PDT 24 Aug 19 04:32:11 PM PDT 24 872160244 ps
T332 /workspace/coverage/default/47.rom_ctrl_alert_test.313314663 Aug 19 04:32:13 PM PDT 24 Aug 19 04:32:21 PM PDT 24 171095242 ps
T333 /workspace/coverage/default/3.rom_ctrl_stress_all.1262576238 Aug 19 04:32:02 PM PDT 24 Aug 19 04:32:42 PM PDT 24 2026523351 ps
T334 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3158503120 Aug 19 04:32:15 PM PDT 24 Aug 19 04:32:32 PM PDT 24 1060421470 ps
T335 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3707712563 Aug 19 04:32:15 PM PDT 24 Aug 19 04:32:36 PM PDT 24 536648079 ps
T336 /workspace/coverage/default/9.rom_ctrl_smoke.1365158129 Aug 19 04:31:45 PM PDT 24 Aug 19 04:31:57 PM PDT 24 259570340 ps
T337 /workspace/coverage/default/22.rom_ctrl_alert_test.2942320244 Aug 19 04:31:51 PM PDT 24 Aug 19 04:32:01 PM PDT 24 1124286577 ps
T338 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4169466502 Aug 19 04:32:06 PM PDT 24 Aug 19 04:35:09 PM PDT 24 10588412958 ps
T339 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2617635111 Aug 19 04:31:48 PM PDT 24 Aug 19 04:32:07 PM PDT 24 1940898330 ps
T340 /workspace/coverage/default/7.rom_ctrl_stress_all.3855306141 Aug 19 04:31:45 PM PDT 24 Aug 19 04:32:17 PM PDT 24 535285572 ps
T341 /workspace/coverage/default/11.rom_ctrl_alert_test.708848074 Aug 19 04:31:47 PM PDT 24 Aug 19 04:31:55 PM PDT 24 175107615 ps
T342 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1426890943 Aug 19 04:31:52 PM PDT 24 Aug 19 04:35:26 PM PDT 24 3043913437 ps
T343 /workspace/coverage/default/5.rom_ctrl_smoke.421967018 Aug 19 04:31:47 PM PDT 24 Aug 19 04:31:57 PM PDT 24 2460445202 ps
T344 /workspace/coverage/default/47.rom_ctrl_stress_all.3040361235 Aug 19 04:32:12 PM PDT 24 Aug 19 04:32:36 PM PDT 24 1548755665 ps
T345 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3824497406 Aug 19 04:32:14 PM PDT 24 Aug 19 04:32:35 PM PDT 24 523533823 ps
T346 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3222894931 Aug 19 04:31:51 PM PDT 24 Aug 19 04:33:35 PM PDT 24 6575508903 ps
T347 /workspace/coverage/default/38.rom_ctrl_stress_all.20986269 Aug 19 04:32:12 PM PDT 24 Aug 19 04:32:38 PM PDT 24 8361018982 ps
T348 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.4089167995 Aug 19 04:31:52 PM PDT 24 Aug 19 04:35:02 PM PDT 24 18119211825 ps
T349 /workspace/coverage/default/19.rom_ctrl_stress_all.2851014865 Aug 19 04:32:54 PM PDT 24 Aug 19 04:33:16 PM PDT 24 511477263 ps
T350 /workspace/coverage/default/40.rom_ctrl_alert_test.377506729 Aug 19 04:32:11 PM PDT 24 Aug 19 04:32:21 PM PDT 24 249243398 ps
T351 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2308197800 Aug 19 04:32:13 PM PDT 24 Aug 19 04:32:23 PM PDT 24 373568547 ps
T26 /workspace/coverage/default/2.rom_ctrl_sec_cm.3196459408 Aug 19 04:31:54 PM PDT 24 Aug 19 04:35:40 PM PDT 24 279467918 ps
T352 /workspace/coverage/default/6.rom_ctrl_stress_all.1493970023 Aug 19 04:31:56 PM PDT 24 Aug 19 04:32:20 PM PDT 24 2577787572 ps
T353 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.597180834 Aug 19 04:32:11 PM PDT 24 Aug 19 04:32:33 PM PDT 24 2057400971 ps
T354 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1278713357 Aug 19 04:31:44 PM PDT 24 Aug 19 04:34:23 PM PDT 24 8454901822 ps
T355 /workspace/coverage/default/43.rom_ctrl_alert_test.4185582224 Aug 19 04:32:11 PM PDT 24 Aug 19 04:32:19 PM PDT 24 186102234 ps
T356 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4073040085 Aug 19 04:32:07 PM PDT 24 Aug 19 04:32:19 PM PDT 24 1016974317 ps
T357 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2622196292 Aug 19 04:32:14 PM PDT 24 Aug 19 04:32:24 PM PDT 24 182914188 ps
T358 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3860567186 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:44 PM PDT 24 167488338 ps
T359 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2202252841 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:43 PM PDT 24 991936928 ps
T56 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1634539761 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:39 PM PDT 24 1073066703 ps
T360 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3779237143 Aug 19 04:29:45 PM PDT 24 Aug 19 04:29:56 PM PDT 24 789708708 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4088870574 Aug 19 04:29:46 PM PDT 24 Aug 19 04:32:17 PM PDT 24 5021013396 ps
T57 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2027556257 Aug 19 04:29:29 PM PDT 24 Aug 19 04:30:36 PM PDT 24 6300944306 ps
T101 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1418993063 Aug 19 04:29:45 PM PDT 24 Aug 19 04:29:57 PM PDT 24 706105624 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2568660375 Aug 19 04:29:15 PM PDT 24 Aug 19 04:29:26 PM PDT 24 662259015 ps
T54 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2026076278 Aug 19 04:29:28 PM PDT 24 Aug 19 04:31:59 PM PDT 24 330655601 ps
T55 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.76192227 Aug 19 04:29:28 PM PDT 24 Aug 19 04:30:48 PM PDT 24 1095351361 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.325324495 Aug 19 04:29:20 PM PDT 24 Aug 19 04:29:27 PM PDT 24 2072443778 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.550946737 Aug 19 04:29:29 PM PDT 24 Aug 19 04:29:37 PM PDT 24 175187850 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1798468325 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:45 PM PDT 24 176238718 ps
T363 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.117811939 Aug 19 04:29:48 PM PDT 24 Aug 19 04:30:00 PM PDT 24 307926759 ps
T115 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.362665423 Aug 19 04:29:08 PM PDT 24 Aug 19 04:30:30 PM PDT 24 3667809507 ps
T65 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2905241956 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:41 PM PDT 24 250415836 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4183720208 Aug 19 04:29:35 PM PDT 24 Aug 19 04:29:45 PM PDT 24 1034457295 ps
T66 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1119887759 Aug 19 04:29:48 PM PDT 24 Aug 19 04:30:24 PM PDT 24 703532482 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2992987858 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:55 PM PDT 24 1125121095 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3367482401 Aug 19 04:29:48 PM PDT 24 Aug 19 04:29:56 PM PDT 24 333705119 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3162341050 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:41 PM PDT 24 175569731 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1359170348 Aug 19 04:29:16 PM PDT 24 Aug 19 04:30:10 PM PDT 24 1089419259 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.30112191 Aug 19 04:29:44 PM PDT 24 Aug 19 04:29:52 PM PDT 24 1107448132 ps
T68 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1439392295 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:44 PM PDT 24 662052874 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1434101251 Aug 19 04:29:51 PM PDT 24 Aug 19 04:30:00 PM PDT 24 250510708 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.918042491 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:53 PM PDT 24 174417563 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.399883313 Aug 19 04:29:38 PM PDT 24 Aug 19 04:29:48 PM PDT 24 517372869 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3726579157 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:43 PM PDT 24 182592754 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1818298722 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:56 PM PDT 24 506813100 ps
T70 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810828069 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:44 PM PDT 24 346906232 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3578375622 Aug 19 04:29:51 PM PDT 24 Aug 19 04:29:59 PM PDT 24 169576820 ps
T76 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1544774470 Aug 19 04:29:15 PM PDT 24 Aug 19 04:30:18 PM PDT 24 1555472939 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3756733415 Aug 19 04:29:18 PM PDT 24 Aug 19 04:29:35 PM PDT 24 999333781 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2321241520 Aug 19 04:29:28 PM PDT 24 Aug 19 04:29:38 PM PDT 24 174402235 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.220178306 Aug 19 04:29:36 PM PDT 24 Aug 19 04:29:45 PM PDT 24 199706778 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2981033665 Aug 19 04:29:34 PM PDT 24 Aug 19 04:29:43 PM PDT 24 785556191 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2961641539 Aug 19 04:29:09 PM PDT 24 Aug 19 04:31:42 PM PDT 24 1279675183 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.891336268 Aug 19 04:29:37 PM PDT 24 Aug 19 04:31:00 PM PDT 24 28351469985 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3829633477 Aug 19 04:29:12 PM PDT 24 Aug 19 04:29:20 PM PDT 24 723182369 ps
T113 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1201758008 Aug 19 04:29:39 PM PDT 24 Aug 19 04:31:03 PM PDT 24 336126356 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.699321003 Aug 19 04:29:38 PM PDT 24 Aug 19 04:29:52 PM PDT 24 4125755743 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1979909533 Aug 19 04:29:41 PM PDT 24 Aug 19 04:31:01 PM PDT 24 237737782 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2911173976 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:55 PM PDT 24 516823934 ps
T119 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1800867981 Aug 19 04:29:30 PM PDT 24 Aug 19 04:30:51 PM PDT 24 346794164 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4247245196 Aug 19 04:29:39 PM PDT 24 Aug 19 04:29:48 PM PDT 24 1177608845 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3673950036 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:03 PM PDT 24 1651780679 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4105551040 Aug 19 04:29:39 PM PDT 24 Aug 19 04:29:48 PM PDT 24 991584735 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.440243293 Aug 19 04:29:38 PM PDT 24 Aug 19 04:29:48 PM PDT 24 264650165 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1991503524 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:20 PM PDT 24 333006684 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.996936393 Aug 19 04:29:51 PM PDT 24 Aug 19 04:31:12 PM PDT 24 2524754819 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.97942002 Aug 19 04:29:45 PM PDT 24 Aug 19 04:29:55 PM PDT 24 186810027 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3717486791 Aug 19 04:29:29 PM PDT 24 Aug 19 04:30:10 PM PDT 24 3908741833 ps
T77 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3260480576 Aug 19 04:29:32 PM PDT 24 Aug 19 04:30:25 PM PDT 24 7896723330 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.891243368 Aug 19 04:29:19 PM PDT 24 Aug 19 04:29:29 PM PDT 24 260160458 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.718196344 Aug 19 04:29:41 PM PDT 24 Aug 19 04:29:49 PM PDT 24 613095283 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1234661669 Aug 19 04:29:26 PM PDT 24 Aug 19 04:32:01 PM PDT 24 503106244 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2998973109 Aug 19 04:29:35 PM PDT 24 Aug 19 04:30:09 PM PDT 24 691884120 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3155351465 Aug 19 04:29:47 PM PDT 24 Aug 19 04:29:56 PM PDT 24 250011608 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3605145606 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:39 PM PDT 24 500884055 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1355618733 Aug 19 04:29:26 PM PDT 24 Aug 19 04:29:39 PM PDT 24 5203701845 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2437847673 Aug 19 04:29:24 PM PDT 24 Aug 19 04:29:33 PM PDT 24 887420566 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2317566241 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:40 PM PDT 24 262029212 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.347031042 Aug 19 04:29:45 PM PDT 24 Aug 19 04:29:55 PM PDT 24 4957044022 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3651606013 Aug 19 04:29:35 PM PDT 24 Aug 19 04:29:47 PM PDT 24 367934924 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3391942015 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:58 PM PDT 24 689727510 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1956020976 Aug 19 04:29:39 PM PDT 24 Aug 19 04:30:15 PM PDT 24 2009440533 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1523896063 Aug 19 04:29:35 PM PDT 24 Aug 19 04:32:07 PM PDT 24 354050133 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2150912117 Aug 19 04:29:27 PM PDT 24 Aug 19 04:29:37 PM PDT 24 257529332 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2944833274 Aug 19 04:29:54 PM PDT 24 Aug 19 04:30:02 PM PDT 24 424643070 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3097173259 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:42 PM PDT 24 174249678 ps
T81 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2802077139 Aug 19 04:29:47 PM PDT 24 Aug 19 04:30:28 PM PDT 24 2868797004 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2083180151 Aug 19 04:29:29 PM PDT 24 Aug 19 04:30:11 PM PDT 24 1020345438 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.508503434 Aug 19 04:29:36 PM PDT 24 Aug 19 04:29:44 PM PDT 24 359901064 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.115795124 Aug 19 04:29:10 PM PDT 24 Aug 19 04:29:46 PM PDT 24 2743930906 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.513558434 Aug 19 04:29:13 PM PDT 24 Aug 19 04:29:22 PM PDT 24 518701919 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3097229933 Aug 19 04:29:29 PM PDT 24 Aug 19 04:30:51 PM PDT 24 318768623 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2128021741 Aug 19 04:29:12 PM PDT 24 Aug 19 04:29:22 PM PDT 24 264265526 ps
T404 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3379562800 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:46 PM PDT 24 257384773 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1494859150 Aug 19 04:29:39 PM PDT 24 Aug 19 04:29:47 PM PDT 24 173219445 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.678820835 Aug 19 04:29:42 PM PDT 24 Aug 19 04:29:50 PM PDT 24 660381117 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.945556138 Aug 19 04:29:41 PM PDT 24 Aug 19 04:29:49 PM PDT 24 345556926 ps
T408 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.292647434 Aug 19 04:29:41 PM PDT 24 Aug 19 04:30:38 PM PDT 24 16524836642 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2143547480 Aug 19 04:29:40 PM PDT 24 Aug 19 04:29:53 PM PDT 24 258443476 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3537124662 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:41 PM PDT 24 499324773 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1313473041 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:38 PM PDT 24 752472976 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.776502637 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:43 PM PDT 24 2081691860 ps
T112 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1236518084 Aug 19 04:29:29 PM PDT 24 Aug 19 04:32:02 PM PDT 24 359272854 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1282214045 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:47 PM PDT 24 708586118 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1928831919 Aug 19 04:29:38 PM PDT 24 Aug 19 04:29:48 PM PDT 24 1074858917 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2762187597 Aug 19 04:29:27 PM PDT 24 Aug 19 04:29:42 PM PDT 24 1001095458 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1673302149 Aug 19 04:29:47 PM PDT 24 Aug 19 04:29:59 PM PDT 24 733868803 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2776587798 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:43 PM PDT 24 259860835 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3275679412 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:40 PM PDT 24 174186729 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1278647608 Aug 19 04:29:48 PM PDT 24 Aug 19 04:30:25 PM PDT 24 1447948047 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3556067489 Aug 19 04:29:28 PM PDT 24 Aug 19 04:29:38 PM PDT 24 1381387358 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1512073603 Aug 19 04:29:51 PM PDT 24 Aug 19 04:30:51 PM PDT 24 6041508893 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.609002006 Aug 19 04:29:28 PM PDT 24 Aug 19 04:30:50 PM PDT 24 374118366 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3899735371 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:45 PM PDT 24 826364870 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3499845619 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:28 PM PDT 24 4116486747 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.111818743 Aug 19 04:29:16 PM PDT 24 Aug 19 04:29:25 PM PDT 24 1128394675 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2990559215 Aug 19 04:29:47 PM PDT 24 Aug 19 04:30:28 PM PDT 24 2037075547 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1504781363 Aug 19 04:29:19 PM PDT 24 Aug 19 04:29:27 PM PDT 24 175538122 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2068597433 Aug 19 04:29:20 PM PDT 24 Aug 19 04:29:40 PM PDT 24 4137791153 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4263763419 Aug 19 04:29:49 PM PDT 24 Aug 19 04:31:09 PM PDT 24 1554324812 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2829411541 Aug 19 04:29:24 PM PDT 24 Aug 19 04:29:32 PM PDT 24 332878996 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2447905054 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:42 PM PDT 24 1040426977 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2023452957 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:41 PM PDT 24 182286935 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3257683332 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:03 PM PDT 24 1041376914 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1847574528 Aug 19 04:29:46 PM PDT 24 Aug 19 04:29:56 PM PDT 24 326412626 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.131386202 Aug 19 04:29:14 PM PDT 24 Aug 19 04:29:23 PM PDT 24 252384650 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2176264993 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:45 PM PDT 24 624289585 ps
T430 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463110724 Aug 19 04:29:41 PM PDT 24 Aug 19 04:30:35 PM PDT 24 1039666814 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1322834511 Aug 19 04:29:24 PM PDT 24 Aug 19 04:29:33 PM PDT 24 515473150 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.616605006 Aug 19 04:29:26 PM PDT 24 Aug 19 04:29:34 PM PDT 24 1030164819 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.742960903 Aug 19 04:29:23 PM PDT 24 Aug 19 04:29:31 PM PDT 24 171567992 ps
T433 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2960271400 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:44 PM PDT 24 346180828 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2279764830 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:46 PM PDT 24 1977929463 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1545296498 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:39 PM PDT 24 307428952 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3243227644 Aug 19 04:29:26 PM PDT 24 Aug 19 04:29:35 PM PDT 24 987139255 ps
T90 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2174714672 Aug 19 04:29:30 PM PDT 24 Aug 19 04:30:38 PM PDT 24 6114381479 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.294436072 Aug 19 04:29:31 PM PDT 24 Aug 19 04:32:05 PM PDT 24 483721059 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.513970682 Aug 19 04:29:38 PM PDT 24 Aug 19 04:29:48 PM PDT 24 2126627429 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1376217275 Aug 19 04:29:12 PM PDT 24 Aug 19 04:31:51 PM PDT 24 725858754 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4112978449 Aug 19 04:29:40 PM PDT 24 Aug 19 04:29:47 PM PDT 24 663949832 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2237471970 Aug 19 04:29:34 PM PDT 24 Aug 19 04:29:47 PM PDT 24 515724745 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2913618506 Aug 19 04:29:28 PM PDT 24 Aug 19 04:29:36 PM PDT 24 332987950 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2188092542 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:09 PM PDT 24 340201666 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3682664322 Aug 19 04:29:37 PM PDT 24 Aug 19 04:30:55 PM PDT 24 470668077 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2516218758 Aug 19 04:29:19 PM PDT 24 Aug 19 04:29:28 PM PDT 24 539422152 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.582149316 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:42 PM PDT 24 661583813 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1518741030 Aug 19 04:29:25 PM PDT 24 Aug 19 04:29:38 PM PDT 24 228433869 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4217068299 Aug 19 04:29:12 PM PDT 24 Aug 19 04:29:20 PM PDT 24 661623495 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1637566840 Aug 19 04:29:33 PM PDT 24 Aug 19 04:29:45 PM PDT 24 255536886 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2314136574 Aug 19 04:29:53 PM PDT 24 Aug 19 04:30:03 PM PDT 24 638408178 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3405059201 Aug 19 04:29:19 PM PDT 24 Aug 19 04:30:11 PM PDT 24 1068216072 ps
T450 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.38158454 Aug 19 04:29:28 PM PDT 24 Aug 19 04:29:42 PM PDT 24 348019026 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2666617788 Aug 19 04:29:35 PM PDT 24 Aug 19 04:29:47 PM PDT 24 178773118 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2020884622 Aug 19 04:29:29 PM PDT 24 Aug 19 04:29:37 PM PDT 24 789945762 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.383877949 Aug 19 04:29:34 PM PDT 24 Aug 19 04:30:54 PM PDT 24 266081368 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3071015444 Aug 19 04:29:21 PM PDT 24 Aug 19 04:30:23 PM PDT 24 3971281524 ps
T455 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1162437217 Aug 19 04:29:48 PM PDT 24 Aug 19 04:29:56 PM PDT 24 176527193 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2349040666 Aug 19 04:29:33 PM PDT 24 Aug 19 04:30:55 PM PDT 24 1688320466 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1703567552 Aug 19 04:29:29 PM PDT 24 Aug 19 04:29:39 PM PDT 24 250282798 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1835527259 Aug 19 04:29:37 PM PDT 24 Aug 19 04:29:45 PM PDT 24 827183805 ps
T458 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1480244723 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:45 PM PDT 24 185887090 ps

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4289134698
Short name T2
Test name
Test status
Simulation time 16905453977 ps
CPU time 168.9 seconds
Started Aug 19 04:32:05 PM PDT 24
Finished Aug 19 04:34:54 PM PDT 24
Peak memory 228280 kb
Host smart-1c205465-4731-469c-a059-fe98887c004c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289134698 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4289134698
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4240604269
Short name T3
Test name
Test status
Simulation time 20039848221 ps
CPU time 343.67 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:37:28 PM PDT 24
Peak memory 228968 kb
Host smart-dbc5f1bd-7117-474c-b9a8-55b74f21bc64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240604269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4240604269
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1957612956
Short name T12
Test name
Test status
Simulation time 13846731032 ps
CPU time 114.05 seconds
Started Aug 19 04:31:37 PM PDT 24
Finished Aug 19 04:33:32 PM PDT 24
Peak memory 233764 kb
Host smart-bee2dbec-751c-4a48-ada4-eded7b00552a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957612956 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1957612956
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2026076278
Short name T54
Test name
Test status
Simulation time 330655601 ps
CPU time 150.71 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 214812 kb
Host smart-c48ee231-b3bc-4713-89de-b060a8fd27a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026076278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2026076278
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2436610253
Short name T6
Test name
Test status
Simulation time 4478820339 ps
CPU time 256.74 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 237644 kb
Host smart-740dffa3-ca89-46f2-8817-645ce0dd01c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436610253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2436610253
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1960256650
Short name T19
Test name
Test status
Simulation time 984237927 ps
CPU time 114.12 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:33:41 PM PDT 24
Peak memory 238824 kb
Host smart-1d91be9b-b9d7-4d24-8420-8963edceb10f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960256650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1960256650
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1359170348
Short name T67
Test name
Test status
Simulation time 1089419259 ps
CPU time 53.31 seconds
Started Aug 19 04:29:16 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 214532 kb
Host smart-ff9f6a22-c370-49ac-bc6b-7c2b63aeeab8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359170348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1359170348
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1713154927
Short name T21
Test name
Test status
Simulation time 2350717706 ps
CPU time 7.98 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218464 kb
Host smart-42f46c49-feb3-4181-bf28-c9a29b1d5dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713154927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1713154927
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1236518084
Short name T112
Test name
Test status
Simulation time 359272854 ps
CPU time 153.01 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:32:02 PM PDT 24
Peak memory 214736 kb
Host smart-1cf2add2-c7ae-4267-a92e-c44d793f83f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236518084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1236518084
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4051818133
Short name T5
Test name
Test status
Simulation time 12628002517 ps
CPU time 32.51 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 219688 kb
Host smart-b710bd24-9273-4368-b155-eab2f38e901e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051818133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4051818133
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2174714672
Short name T90
Test name
Test status
Simulation time 6114381479 ps
CPU time 63 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:30:38 PM PDT 24
Peak memory 216584 kb
Host smart-3b18121c-1a46-4ce6-bcdb-d27bee0a7f00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174714672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2174714672
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2599099488
Short name T45
Test name
Test status
Simulation time 1377192946 ps
CPU time 18.19 seconds
Started Aug 19 04:31:31 PM PDT 24
Finished Aug 19 04:31:49 PM PDT 24
Peak memory 218696 kb
Host smart-156a1b4d-2cee-4113-82bf-ee72e0b12538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599099488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2599099488
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.463062622
Short name T192
Test name
Test status
Simulation time 1013750578 ps
CPU time 21.49 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:12 PM PDT 24
Peak memory 218812 kb
Host smart-41f5ea82-eefb-4606-ba14-3900a8d3da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463062622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.463062622
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1234661669
Short name T114
Test name
Test status
Simulation time 503106244 ps
CPU time 155.41 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:32:01 PM PDT 24
Peak memory 219532 kb
Host smart-6b9bd1bb-623e-4998-ba6f-8e4d12b74d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234661669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1234661669
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1195579283
Short name T72
Test name
Test status
Simulation time 28671331025 ps
CPU time 34.41 seconds
Started Aug 19 04:32:05 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 216804 kb
Host smart-adc01100-1d0d-49cd-99b4-235b75be9a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195579283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1195579283
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2961641539
Short name T110
Test name
Test status
Simulation time 1279675183 ps
CPU time 152.18 seconds
Started Aug 19 04:29:09 PM PDT 24
Finished Aug 19 04:31:42 PM PDT 24
Peak memory 214712 kb
Host smart-dd54b280-1fd0-4acf-987d-78aac861b115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961641539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2961641539
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.996936393
Short name T108
Test name
Test status
Simulation time 2524754819 ps
CPU time 80.95 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 214724 kb
Host smart-0039d0bc-bfc6-41c1-91a4-db78cb77a922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996936393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.996936393
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4217068299
Short name T87
Test name
Test status
Simulation time 661623495 ps
CPU time 7.67 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 211632 kb
Host smart-c43c64cc-a6b0-4b81-a5c2-c6d42b805406
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217068299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4217068299
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.476174869
Short name T169
Test name
Test status
Simulation time 2570218622 ps
CPU time 120.04 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 233512 kb
Host smart-96980e38-8cbc-4404-9ff8-590f4a191f8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476174869 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.476174869
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2600263806
Short name T92
Test name
Test status
Simulation time 263710482 ps
CPU time 11.95 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218976 kb
Host smart-e57ef646-9788-4842-a62b-1be994f3cb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600263806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2600263806
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1991503524
Short name T385
Test name
Test status
Simulation time 333006684 ps
CPU time 8.23 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 211752 kb
Host smart-017094ab-4ed9-4fc2-b4e6-8882e26d05eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991503524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1991503524
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1798468325
Short name T64
Test name
Test status
Simulation time 176238718 ps
CPU time 14.55 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 212280 kb
Host smart-ed7d9728-7cc8-4a21-b2ca-98ce3fb5e05a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798468325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1798468325
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3556067489
Short name T418
Test name
Test status
Simulation time 1381387358 ps
CPU time 9.34 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 214556 kb
Host smart-17c454d8-7ea0-4aa8-b5e8-b8b838201779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556067489 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3556067489
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1504781363
Short name T84
Test name
Test status
Simulation time 175538122 ps
CPU time 7.72 seconds
Started Aug 19 04:29:19 PM PDT 24
Finished Aug 19 04:29:27 PM PDT 24
Peak memory 211364 kb
Host smart-390a7ae1-66f3-4e48-b411-b94dc1ec0e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504781363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1504781363
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.325324495
Short name T362
Test name
Test status
Simulation time 2072443778 ps
CPU time 7.55 seconds
Started Aug 19 04:29:20 PM PDT 24
Finished Aug 19 04:29:27 PM PDT 24
Peak memory 211356 kb
Host smart-71512ce6-547e-4980-8493-028825025dfa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325324495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.325324495
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.111818743
Short name T421
Test name
Test status
Simulation time 1128394675 ps
CPU time 8.85 seconds
Started Aug 19 04:29:16 PM PDT 24
Finished Aug 19 04:29:25 PM PDT 24
Peak memory 211280 kb
Host smart-8f3b5490-782f-4a66-b894-789d606eb96d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111818743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
111818743
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3405059201
Short name T449
Test name
Test status
Simulation time 1068216072 ps
CPU time 51.87 seconds
Started Aug 19 04:29:19 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 214492 kb
Host smart-a71407bc-3cfa-4b4d-bff4-d38901db8351
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405059201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3405059201
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2913618506
Short name T441
Test name
Test status
Simulation time 332987950 ps
CPU time 7.71 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:36 PM PDT 24
Peak memory 212088 kb
Host smart-327a4778-7917-48bb-be0f-f992b314abae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913618506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2913618506
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.776502637
Short name T411
Test name
Test status
Simulation time 2081691860 ps
CPU time 12.39 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:43 PM PDT 24
Peak memory 218164 kb
Host smart-cf74562f-c9e0-4da2-9f85-c03325f67fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776502637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.776502637
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.513558434
Short name T83
Test name
Test status
Simulation time 518701919 ps
CPU time 9.5 seconds
Started Aug 19 04:29:13 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 211552 kb
Host smart-49e6a6f4-65f8-4820-b2e5-96e237353c44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513558434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.513558434
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2020884622
Short name T452
Test name
Test status
Simulation time 789945762 ps
CPU time 8.08 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 211420 kb
Host smart-0b24e151-27ee-4365-b2e3-26bff436c7df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020884622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2020884622
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2762187597
Short name T414
Test name
Test status
Simulation time 1001095458 ps
CPU time 15.11 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 212852 kb
Host smart-3b612920-b2c4-4a17-8867-9adabba46a2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762187597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2762187597
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2516218758
Short name T444
Test name
Test status
Simulation time 539422152 ps
CPU time 9.67 seconds
Started Aug 19 04:29:19 PM PDT 24
Finished Aug 19 04:29:28 PM PDT 24
Peak memory 219548 kb
Host smart-0acddb17-9bd7-4391-8b7d-c14be722c7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516218758 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2516218758
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.131386202
Short name T428
Test name
Test status
Simulation time 252384650 ps
CPU time 9.33 seconds
Started Aug 19 04:29:14 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 211876 kb
Host smart-96645a18-133b-4e65-8055-a3642fed09fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131386202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.131386202
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3829633477
Short name T377
Test name
Test status
Simulation time 723182369 ps
CPU time 7.8 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 211284 kb
Host smart-624326c5-7233-4945-97d1-9ff24fd4611d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829633477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3829633477
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2437847673
Short name T393
Test name
Test status
Simulation time 887420566 ps
CPU time 9.34 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 211356 kb
Host smart-613a19e6-fc8b-438c-a7ca-e4a29375e64f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437847673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2437847673
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.115795124
Short name T401
Test name
Test status
Simulation time 2743930906 ps
CPU time 35.99 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:46 PM PDT 24
Peak memory 214520 kb
Host smart-10e40655-b72c-41b7-b035-d090a7f190f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115795124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.115795124
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3756733415
Short name T372
Test name
Test status
Simulation time 999333781 ps
CPU time 16.98 seconds
Started Aug 19 04:29:18 PM PDT 24
Finished Aug 19 04:29:35 PM PDT 24
Peak memory 212944 kb
Host smart-a84d27b3-edc9-4b67-b8bc-c52897a2eb4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756733415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3756733415
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3499845619
Short name T420
Test name
Test status
Simulation time 4116486747 ps
CPU time 16.65 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:28 PM PDT 24
Peak memory 219392 kb
Host smart-659083ab-a195-46fd-90ca-4a530e715b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499845619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3499845619
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.362665423
Short name T115
Test name
Test status
Simulation time 3667809507 ps
CPU time 82.58 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:30:30 PM PDT 24
Peak memory 213236 kb
Host smart-e3a7d271-9e0f-4b80-8af8-47aaf3985568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362665423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.362665423
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.513970682
Short name T438
Test name
Test status
Simulation time 2126627429 ps
CPU time 9.9 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 219648 kb
Host smart-09dab0ac-9336-4ce9-8fee-c25565f1e99b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513970682 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.513970682
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1835527259
Short name T457
Test name
Test status
Simulation time 827183805 ps
CPU time 7.92 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 211772 kb
Host smart-f5acad2f-bab1-44a6-931b-3053bbd5fb8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835527259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1835527259
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2083180151
Short name T88
Test name
Test status
Simulation time 1020345438 ps
CPU time 41.99 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 215524 kb
Host smart-11861fc7-c320-453d-8c25-eafda46c50de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083180151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2083180151
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2905241956
Short name T65
Test name
Test status
Simulation time 250415836 ps
CPU time 9.14 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:41 PM PDT 24
Peak memory 212000 kb
Host smart-6b532b4f-b1d2-48fe-8019-505e2f2551cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905241956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2905241956
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3391942015
Short name T396
Test name
Test status
Simulation time 689727510 ps
CPU time 10.92 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 218112 kb
Host smart-8a6a1e19-619a-4940-a16f-ab5a151428e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391942015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3391942015
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4105551040
Short name T383
Test name
Test status
Simulation time 991584735 ps
CPU time 9.05 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 214188 kb
Host smart-989633f8-748f-4bcc-bcc4-ac57479389d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105551040 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4105551040
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2960271400
Short name T433
Test name
Test status
Simulation time 346180828 ps
CPU time 7.87 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 211340 kb
Host smart-37786c04-e548-445d-8db0-1cbc39a3f15f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960271400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2960271400
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1956020976
Short name T80
Test name
Test status
Simulation time 2009440533 ps
CPU time 35.49 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:30:15 PM PDT 24
Peak memory 215568 kb
Host smart-cf186799-57ec-441f-9113-e679a3297b05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956020976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1956020976
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1928831919
Short name T413
Test name
Test status
Simulation time 1074858917 ps
CPU time 9.39 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 211908 kb
Host smart-c937fce7-10ce-4fed-8573-ce2b329b6c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928831919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1928831919
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3097173259
Short name T399
Test name
Test status
Simulation time 174249678 ps
CPU time 11.88 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 218172 kb
Host smart-159e62dd-51c7-4671-8e6e-91756dfb0ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097173259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3097173259
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1523896063
Short name T117
Test name
Test status
Simulation time 354050133 ps
CPU time 151.83 seconds
Started Aug 19 04:29:35 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 219472 kb
Host smart-ce2d23ea-dd5e-44d5-84bf-9fe0d5b7c2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523896063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1523896063
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3257683332
Short name T426
Test name
Test status
Simulation time 1041376914 ps
CPU time 9.64 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 214988 kb
Host smart-4d4b6b1f-fcb9-4a4c-bf83-20a551eb89a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257683332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3257683332
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810828069
Short name T70
Test name
Test status
Simulation time 346906232 ps
CPU time 7.48 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 211544 kb
Host smart-eacac6cb-e0c7-44f4-8693-d2e6e4beb5fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810828069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.810828069
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1278647608
Short name T89
Test name
Test status
Simulation time 1447948047 ps
CPU time 36.23 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 214488 kb
Host smart-aa9a2904-f796-4d43-ba98-9c43d2fde410
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278647608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1278647608
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.699321003
Short name T378
Test name
Test status
Simulation time 4125755743 ps
CPU time 13.27 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 213228 kb
Host smart-9283f648-8a0b-4cc7-a4af-929a0729990f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699321003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.699321003
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.582149316
Short name T445
Test name
Test status
Simulation time 661583813 ps
CPU time 11.72 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 218296 kb
Host smart-a1064b8e-a013-4f88-91c1-1a32ea4fd3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582149316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.582149316
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.383877949
Short name T453
Test name
Test status
Simulation time 266081368 ps
CPU time 79.47 seconds
Started Aug 19 04:29:34 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 219592 kb
Host smart-811453a1-ccbb-4a36-9435-4a975d78fc01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383877949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.383877949
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2314136574
Short name T448
Test name
Test status
Simulation time 638408178 ps
CPU time 9.84 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 218512 kb
Host smart-06722902-6ae9-44af-adaf-ae53cffb4f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314136574 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2314136574
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.678820835
Short name T406
Test name
Test status
Simulation time 660381117 ps
CPU time 7.62 seconds
Started Aug 19 04:29:42 PM PDT 24
Finished Aug 19 04:29:50 PM PDT 24
Peak memory 211784 kb
Host smart-c569a0bd-fead-4a63-93a1-954a1ed4d67c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678820835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.678820835
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1119887759
Short name T66
Test name
Test status
Simulation time 703532482 ps
CPU time 35.63 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:30:24 PM PDT 24
Peak memory 214540 kb
Host smart-6b1366d6-c62b-4f63-98f7-6a3ddced92fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119887759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1119887759
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3578375622
Short name T371
Test name
Test status
Simulation time 169576820 ps
CPU time 8.01 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 211556 kb
Host smart-e29509b0-1ed7-4074-996f-1a914419ca9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578375622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3578375622
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2202252841
Short name T359
Test name
Test status
Simulation time 991936928 ps
CPU time 12.34 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:43 PM PDT 24
Peak memory 217876 kb
Host smart-ecf25454-61a1-4102-b76c-d0aaa0dad90c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202252841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2202252841
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3537124662
Short name T410
Test name
Test status
Simulation time 499324773 ps
CPU time 9.18 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:41 PM PDT 24
Peak memory 214480 kb
Host smart-6efe5328-fbe2-49a7-a9ce-be857e4cd7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537124662 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3537124662
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2911173976
Short name T380
Test name
Test status
Simulation time 516823934 ps
CPU time 9.26 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 211456 kb
Host smart-0ae4b229-a126-4ca9-a35a-d42b1d72b5b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911173976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2911173976
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2802077139
Short name T81
Test name
Test status
Simulation time 2868797004 ps
CPU time 35.98 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 213504 kb
Host smart-a3c3bdb6-59b0-403a-b009-5a016043faeb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802077139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2802077139
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3673950036
Short name T382
Test name
Test status
Simulation time 1651780679 ps
CPU time 9.48 seconds
Started Aug 19 04:29:53 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 212216 kb
Host smart-6478b72f-e5ac-4647-abb9-1a2772ac2f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673950036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3673950036
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2188092542
Short name T442
Test name
Test status
Simulation time 340201666 ps
CPU time 10.44 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 217884 kb
Host smart-18b2b5f8-62d4-4ff2-9cf2-d68032df9be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188092542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2188092542
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.609002006
Short name T109
Test name
Test status
Simulation time 374118366 ps
CPU time 82 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:30:50 PM PDT 24
Peak memory 214200 kb
Host smart-76e2540e-b9a5-43d5-85ac-8d87c7f23a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609002006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.609002006
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1480244723
Short name T458
Test name
Test status
Simulation time 185887090 ps
CPU time 8.55 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 217064 kb
Host smart-5a981dd6-cea9-4f4f-8510-baa9a3097293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480244723 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1480244723
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3379562800
Short name T404
Test name
Test status
Simulation time 257384773 ps
CPU time 9.39 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:46 PM PDT 24
Peak memory 211440 kb
Host smart-7747dbc2-2736-41a6-a52e-9ae1416669d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379562800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3379562800
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.292647434
Short name T408
Test name
Test status
Simulation time 16524836642 ps
CPU time 56.58 seconds
Started Aug 19 04:29:41 PM PDT 24
Finished Aug 19 04:30:38 PM PDT 24
Peak memory 214984 kb
Host smart-a618f48b-fbd4-4ec3-bf3f-b36af5e453d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292647434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.292647434
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3651606013
Short name T395
Test name
Test status
Simulation time 367934924 ps
CPU time 11.58 seconds
Started Aug 19 04:29:35 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 211932 kb
Host smart-bcd209be-9c1d-4d27-ab4b-3b05e5989bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651606013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3651606013
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.117811939
Short name T363
Test name
Test status
Simulation time 307926759 ps
CPU time 12.06 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 219364 kb
Host smart-67823af9-b745-4366-bed3-ab5f240e9be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117811939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.117811939
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.294436072
Short name T437
Test name
Test status
Simulation time 483721059 ps
CPU time 153.86 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:32:05 PM PDT 24
Peak memory 214752 kb
Host smart-d7a4c5f8-cbcf-443c-bafd-daf38fd490a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294436072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.294436072
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.97942002
Short name T386
Test name
Test status
Simulation time 186810027 ps
CPU time 9.07 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 218052 kb
Host smart-1c71508f-4b8c-40b4-b26e-85c2c086845a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97942002 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.97942002
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1703567552
Short name T456
Test name
Test status
Simulation time 250282798 ps
CPU time 9.19 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 211628 kb
Host smart-b4eb2504-9a85-41d6-ba53-823b2632007a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703567552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1703567552
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3260480576
Short name T77
Test name
Test status
Simulation time 7896723330 ps
CPU time 53.64 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 215780 kb
Host smart-327a6405-6c9b-49da-993d-857055765d2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260480576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3260480576
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1162437217
Short name T455
Test name
Test status
Simulation time 176527193 ps
CPU time 7.62 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 211804 kb
Host smart-b6662195-f0fb-40fd-83bc-b28d22c9c711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162437217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1162437217
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2321241520
Short name T373
Test name
Test status
Simulation time 174402235 ps
CPU time 10.77 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 217928 kb
Host smart-6f3b68cd-19b0-4c4e-ba84-d845f0015604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321241520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2321241520
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2349040666
Short name T116
Test name
Test status
Simulation time 1688320466 ps
CPU time 82.05 seconds
Started Aug 19 04:29:33 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 213500 kb
Host smart-f94ef8ad-6e82-4b8a-8444-710ee5c05a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349040666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2349040666
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.508503434
Short name T400
Test name
Test status
Simulation time 359901064 ps
CPU time 7.99 seconds
Started Aug 19 04:29:36 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 219560 kb
Host smart-67a2563b-e707-4bc6-ad87-cbef2ebab47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508503434 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.508503434
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4247245196
Short name T381
Test name
Test status
Simulation time 1177608845 ps
CPU time 9.52 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 211764 kb
Host smart-f0302e28-9c0a-4669-9db1-3477c24f4550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247245196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4247245196
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1512073603
Short name T91
Test name
Test status
Simulation time 6041508893 ps
CPU time 60.43 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:30:51 PM PDT 24
Peak memory 216728 kb
Host smart-e5315a47-6073-4aee-bd80-8711944825d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512073603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1512073603
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1418993063
Short name T101
Test name
Test status
Simulation time 706105624 ps
CPU time 11.5 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 213272 kb
Host smart-2f930b10-8120-439e-b904-a09f730f3e18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418993063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1418993063
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3162341050
Short name T365
Test name
Test status
Simulation time 175569731 ps
CPU time 11.02 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:41 PM PDT 24
Peak memory 217996 kb
Host smart-8e9756c2-0463-4a1e-a23a-d70593658baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162341050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3162341050
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4263763419
Short name T111
Test name
Test status
Simulation time 1554324812 ps
CPU time 79.48 seconds
Started Aug 19 04:29:49 PM PDT 24
Finished Aug 19 04:31:09 PM PDT 24
Peak memory 215164 kb
Host smart-57d3117a-cc46-4695-bc0b-04139d29075a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263763419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4263763419
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.347031042
Short name T394
Test name
Test status
Simulation time 4957044022 ps
CPU time 9.74 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 219772 kb
Host smart-90994af6-8648-4571-9a4d-9e513212ccda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347031042 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.347031042
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.945556138
Short name T407
Test name
Test status
Simulation time 345556926 ps
CPU time 7.72 seconds
Started Aug 19 04:29:41 PM PDT 24
Finished Aug 19 04:29:49 PM PDT 24
Peak memory 211904 kb
Host smart-7565efa4-9a55-4789-af68-2356141d5316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945556138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.945556138
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463110724
Short name T430
Test name
Test status
Simulation time 1039666814 ps
CPU time 54.6 seconds
Started Aug 19 04:29:41 PM PDT 24
Finished Aug 19 04:30:35 PM PDT 24
Peak memory 215524 kb
Host smart-58113c04-fee5-4588-8d35-ea5a8c1e55b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463110724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1463110724
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3367482401
Short name T103
Test name
Test status
Simulation time 333705119 ps
CPU time 8.03 seconds
Started Aug 19 04:29:48 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 211856 kb
Host smart-9ce75025-d85e-49bc-bf13-c8f8a3423973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367482401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3367482401
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3779237143
Short name T360
Test name
Test status
Simulation time 789708708 ps
CPU time 10.65 seconds
Started Aug 19 04:29:45 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 218088 kb
Host smart-e08934b9-f90a-4b5e-b7aa-8b4a32ebdbf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779237143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3779237143
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1201758008
Short name T113
Test name
Test status
Simulation time 336126356 ps
CPU time 83.18 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 214112 kb
Host smart-a7169a56-9052-42f0-a996-2a6d31e4d8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201758008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1201758008
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2981033665
Short name T375
Test name
Test status
Simulation time 785556191 ps
CPU time 9.34 seconds
Started Aug 19 04:29:34 PM PDT 24
Finished Aug 19 04:29:43 PM PDT 24
Peak memory 219652 kb
Host smart-07e5b4ae-866d-4126-9ba4-b0c43f7ad2c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981033665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2981033665
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.718196344
Short name T389
Test name
Test status
Simulation time 613095283 ps
CPU time 8.1 seconds
Started Aug 19 04:29:41 PM PDT 24
Finished Aug 19 04:29:49 PM PDT 24
Peak memory 212060 kb
Host smart-c6bccfc1-d487-4433-b4c2-d4611c1442f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718196344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.718196344
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3717486791
Short name T387
Test name
Test status
Simulation time 3908741833 ps
CPU time 41.48 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 214000 kb
Host smart-2b965246-2c13-4765-9ef3-faac61ffee3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717486791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3717486791
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2666617788
Short name T451
Test name
Test status
Simulation time 178773118 ps
CPU time 12.06 seconds
Started Aug 19 04:29:35 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 213076 kb
Host smart-9c0e644a-d140-4ad3-b8bb-beaef008a5ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666617788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2666617788
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2143547480
Short name T409
Test name
Test status
Simulation time 258443476 ps
CPU time 12.7 seconds
Started Aug 19 04:29:40 PM PDT 24
Finished Aug 19 04:29:53 PM PDT 24
Peak memory 218364 kb
Host smart-c2af72e8-e7d7-4731-9d93-1cda273a275a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143547480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2143547480
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2829411541
Short name T85
Test name
Test status
Simulation time 332878996 ps
CPU time 7.9 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:32 PM PDT 24
Peak memory 211612 kb
Host smart-5acfa94b-a040-470c-a4b0-91869e898c4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829411541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2829411541
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1494859150
Short name T405
Test name
Test status
Simulation time 173219445 ps
CPU time 8.1 seconds
Started Aug 19 04:29:39 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 211416 kb
Host smart-89953951-4c96-44d6-9cfa-028f9c72805f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494859150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1494859150
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2068597433
Short name T423
Test name
Test status
Simulation time 4137791153 ps
CPU time 20.48 seconds
Started Aug 19 04:29:20 PM PDT 24
Finished Aug 19 04:29:40 PM PDT 24
Peak memory 212720 kb
Host smart-19b918de-8d17-4041-8cff-02df382debb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068597433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2068597433
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1355618733
Short name T392
Test name
Test status
Simulation time 5203701845 ps
CPU time 13.68 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 218688 kb
Host smart-93323575-5d5a-49b3-bc1f-c1f95124d8ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355618733 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1355618733
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.742960903
Short name T86
Test name
Test status
Simulation time 171567992 ps
CPU time 7.98 seconds
Started Aug 19 04:29:23 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 211716 kb
Host smart-63245f3e-76ae-499c-8a88-b77210c34cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742960903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.742960903
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2128021741
Short name T403
Test name
Test status
Simulation time 264265526 ps
CPU time 9.03 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 211360 kb
Host smart-3935fb2f-5585-4569-b21a-007a7c92baf2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128021741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2128021741
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1322834511
Short name T431
Test name
Test status
Simulation time 515473150 ps
CPU time 8.91 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 211268 kb
Host smart-745573f7-220b-409f-be6f-97434c712d78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322834511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1322834511
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3243227644
Short name T436
Test name
Test status
Simulation time 987139255 ps
CPU time 9.33 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:29:35 PM PDT 24
Peak memory 212060 kb
Host smart-6d0bf4cf-e7ce-4344-9548-c01ca3af4f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243227644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3243227644
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2568660375
Short name T361
Test name
Test status
Simulation time 662259015 ps
CPU time 11.04 seconds
Started Aug 19 04:29:15 PM PDT 24
Finished Aug 19 04:29:26 PM PDT 24
Peak memory 218068 kb
Host smart-29346338-036f-4c60-874f-b2c129737932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568660375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2568660375
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1376217275
Short name T118
Test name
Test status
Simulation time 725858754 ps
CPU time 158.67 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:31:51 PM PDT 24
Peak memory 215860 kb
Host smart-2fce2dae-f054-424d-a61f-0997fdd768e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376217275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1376217275
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2944833274
Short name T398
Test name
Test status
Simulation time 424643070 ps
CPU time 7.76 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 211544 kb
Host smart-1882129e-fe25-41f7-b199-3b24ee4c7c28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944833274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2944833274
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.616605006
Short name T432
Test name
Test status
Simulation time 1030164819 ps
CPU time 8.03 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:29:34 PM PDT 24
Peak memory 211404 kb
Host smart-a072919b-bce2-444c-9f5e-21e784ff7f1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616605006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.616605006
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2176264993
Short name T429
Test name
Test status
Simulation time 624289585 ps
CPU time 14.36 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 212632 kb
Host smart-f8704a2a-e668-494b-bad4-5b89658dcd53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176264993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2176264993
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.440243293
Short name T384
Test name
Test status
Simulation time 264650165 ps
CPU time 9.91 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 215324 kb
Host smart-0e8b721f-14a3-446b-9053-5d8b313df963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440243293 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.440243293
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1313473041
Short name T82
Test name
Test status
Simulation time 752472976 ps
CPU time 8.03 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 211816 kb
Host smart-3f44566a-adf3-4f5c-a9ae-c83e57f341c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313473041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1313473041
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2992987858
Short name T364
Test name
Test status
Simulation time 1125121095 ps
CPU time 8.92 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 211312 kb
Host smart-fafae543-2219-4a42-ad9a-b616dbe6792c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992987858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2992987858
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.918042491
Short name T368
Test name
Test status
Simulation time 174417563 ps
CPU time 7.65 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:53 PM PDT 24
Peak memory 211332 kb
Host smart-7c05d47b-1a16-4de5-92b0-dd9f063d285b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918042491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
918042491
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2998973109
Short name T78
Test name
Test status
Simulation time 691884120 ps
CPU time 34.15 seconds
Started Aug 19 04:29:35 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 214508 kb
Host smart-3131b80e-2b7a-4ff0-b6bd-b5d18b212bd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998973109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2998973109
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3726579157
Short name T69
Test name
Test status
Simulation time 182592754 ps
CPU time 11.6 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:43 PM PDT 24
Peak memory 213180 kb
Host smart-e76cb500-aa67-48a4-8fa1-1ba249ebea79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726579157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3726579157
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3860567186
Short name T358
Test name
Test status
Simulation time 167488338 ps
CPU time 12.22 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 217200 kb
Host smart-b8d1deef-5df3-497e-9fd4-5b281031a2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860567186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3860567186
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3682664322
Short name T443
Test name
Test status
Simulation time 470668077 ps
CPU time 77.84 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 214404 kb
Host smart-87a1e7e2-b0b5-435f-af96-fd69d1035f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682664322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3682664322
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1818298722
Short name T370
Test name
Test status
Simulation time 506813100 ps
CPU time 9.51 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 211388 kb
Host smart-7fec9b28-3894-4d6d-ba4c-f2410252101b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818298722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1818298722
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3275679412
Short name T417
Test name
Test status
Simulation time 174186729 ps
CPU time 8.02 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:40 PM PDT 24
Peak memory 211348 kb
Host smart-29df483f-e717-48bc-955f-6d1457cfc3ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275679412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3275679412
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1282214045
Short name T412
Test name
Test status
Simulation time 708586118 ps
CPU time 15.23 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 212760 kb
Host smart-a71301b9-425d-44ca-81e4-5501569c82d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282214045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1282214045
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3605145606
Short name T391
Test name
Test status
Simulation time 500884055 ps
CPU time 9.46 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 219652 kb
Host smart-b9ec88fa-8269-429e-8462-6f1705fe7c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605145606 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3605145606
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.550946737
Short name T63
Test name
Test status
Simulation time 175187850 ps
CPU time 8.05 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 211804 kb
Host smart-ee805a36-8ccf-47dc-a6d5-0147dd605cf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550946737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.550946737
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1434101251
Short name T367
Test name
Test status
Simulation time 250510708 ps
CPU time 9.06 seconds
Started Aug 19 04:29:51 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 211336 kb
Host smart-2befe54b-ef78-44d4-a0a6-80354aa4d75f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434101251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1434101251
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1545296498
Short name T435
Test name
Test status
Simulation time 307428952 ps
CPU time 7.68 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 211368 kb
Host smart-f62d239d-7372-4036-a6c8-f10b104b6c7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545296498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1545296498
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3071015444
Short name T454
Test name
Test status
Simulation time 3971281524 ps
CPU time 56.95 seconds
Started Aug 19 04:29:21 PM PDT 24
Finished Aug 19 04:30:23 PM PDT 24
Peak memory 214660 kb
Host smart-cd04aa3b-6738-4246-9725-8c70d8b3f1d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071015444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3071015444
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1634539761
Short name T56
Test name
Test status
Simulation time 1073066703 ps
CPU time 9.2 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 211908 kb
Host smart-30ee4848-3d3b-4ea6-a1ba-8acb6bbb5acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634539761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1634539761
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2776587798
Short name T416
Test name
Test status
Simulation time 259860835 ps
CPU time 12.15 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:43 PM PDT 24
Peak memory 217876 kb
Host smart-5308c064-57d0-4ed7-9704-92d26614e104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776587798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2776587798
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1979909533
Short name T379
Test name
Test status
Simulation time 237737782 ps
CPU time 80.22 seconds
Started Aug 19 04:29:41 PM PDT 24
Finished Aug 19 04:31:01 PM PDT 24
Peak memory 214556 kb
Host smart-78ac2cbb-34b4-4912-929f-82ba99cc32ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979909533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1979909533
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.30112191
Short name T366
Test name
Test status
Simulation time 1107448132 ps
CPU time 7.75 seconds
Started Aug 19 04:29:44 PM PDT 24
Finished Aug 19 04:29:52 PM PDT 24
Peak memory 219644 kb
Host smart-33d09860-35ba-4035-b8e1-833527261f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30112191 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.30112191
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4183720208
Short name T102
Test name
Test status
Simulation time 1034457295 ps
CPU time 9.19 seconds
Started Aug 19 04:29:35 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 211856 kb
Host smart-c9951dd1-c930-40cb-80e5-d967f9a1c0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183720208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4183720208
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2990559215
Short name T422
Test name
Test status
Simulation time 2037075547 ps
CPU time 41.5 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 214456 kb
Host smart-679ba1d2-e31c-484b-ba1c-97b4d85a9f44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990559215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2990559215
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3155351465
Short name T390
Test name
Test status
Simulation time 250011608 ps
CPU time 9.19 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 212148 kb
Host smart-eedf99fc-109b-4910-8497-f0ab32888cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155351465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3155351465
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.38158454
Short name T450
Test name
Test status
Simulation time 348019026 ps
CPU time 14.05 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 218232 kb
Host smart-a74c63d3-1f86-4d29-ad33-ab6a1806fce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.38158454
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2023452957
Short name T425
Test name
Test status
Simulation time 182286935 ps
CPU time 8.99 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:41 PM PDT 24
Peak memory 219576 kb
Host smart-e258e703-a532-4cfa-9b53-1104680684fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023452957 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2023452957
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.891243368
Short name T388
Test name
Test status
Simulation time 260160458 ps
CPU time 9.56 seconds
Started Aug 19 04:29:19 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 211472 kb
Host smart-ea962494-ac65-40d7-a697-d6bdee3ce65f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891243368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.891243368
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1544774470
Short name T76
Test name
Test status
Simulation time 1555472939 ps
CPU time 62.46 seconds
Started Aug 19 04:29:15 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 215480 kb
Host smart-a23475d5-7448-43be-87ee-9ed4b676ad10
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544774470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1544774470
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1439392295
Short name T68
Test name
Test status
Simulation time 662052874 ps
CPU time 7.65 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:44 PM PDT 24
Peak memory 212032 kb
Host smart-c2c939f9-c1ba-4e6b-9d60-6881293c4a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439392295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1439392295
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1518741030
Short name T446
Test name
Test status
Simulation time 228433869 ps
CPU time 12.95 seconds
Started Aug 19 04:29:25 PM PDT 24
Finished Aug 19 04:29:38 PM PDT 24
Peak memory 218280 kb
Host smart-f355b918-5a1d-4b9d-9c70-328c7eb9026f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518741030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1518741030
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3097229933
Short name T402
Test name
Test status
Simulation time 318768623 ps
CPU time 81.4 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:30:51 PM PDT 24
Peak memory 214360 kb
Host smart-15fcb4ff-89eb-48fb-8788-950ce3ea2444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097229933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3097229933
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2279764830
Short name T434
Test name
Test status
Simulation time 1977929463 ps
CPU time 13.59 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:46 PM PDT 24
Peak memory 217060 kb
Host smart-68ec8899-8607-4ba3-9444-c974c3aaa497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279764830 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2279764830
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4112978449
Short name T439
Test name
Test status
Simulation time 663949832 ps
CPU time 7.55 seconds
Started Aug 19 04:29:40 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 211624 kb
Host smart-482cf92a-9096-403f-9efe-998762bc726a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112978449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4112978449
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.891336268
Short name T376
Test name
Test status
Simulation time 28351469985 ps
CPU time 83.2 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 215736 kb
Host smart-97dd03db-96e2-4d49-8d82-e140be988048
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891336268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.891336268
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3899735371
Short name T419
Test name
Test status
Simulation time 826364870 ps
CPU time 8.13 seconds
Started Aug 19 04:29:37 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 211908 kb
Host smart-83bd2a55-f014-401f-819a-6f74e7427150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899735371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3899735371
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1637566840
Short name T447
Test name
Test status
Simulation time 255536886 ps
CPU time 12.29 seconds
Started Aug 19 04:29:33 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 218188 kb
Host smart-351c41dd-ff18-4dbf-bca9-9719071e399b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637566840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1637566840
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.76192227
Short name T55
Test name
Test status
Simulation time 1095351361 ps
CPU time 80.04 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 215268 kb
Host smart-755b2d32-5a48-48be-a550-17b6f11697e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76192227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg
_err.76192227
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2447905054
Short name T424
Test name
Test status
Simulation time 1040426977 ps
CPU time 9.99 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:42 PM PDT 24
Peak memory 217128 kb
Host smart-d5847a10-3d90-4ff0-93b7-c9e32bdb539d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447905054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2447905054
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2317566241
Short name T79
Test name
Test status
Simulation time 262029212 ps
CPU time 9.26 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:40 PM PDT 24
Peak memory 211348 kb
Host smart-375fdeb3-dd74-4c6d-81cd-145f499740f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317566241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2317566241
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2027556257
Short name T57
Test name
Test status
Simulation time 6300944306 ps
CPU time 61.71 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:30:36 PM PDT 24
Peak memory 219640 kb
Host smart-e5f05b26-c047-47df-aa1b-a1539683fca5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027556257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2027556257
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2150912117
Short name T397
Test name
Test status
Simulation time 257529332 ps
CPU time 9.29 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 212168 kb
Host smart-a9261ea1-f44d-434e-b473-c04847cc256f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150912117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2150912117
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1847574528
Short name T427
Test name
Test status
Simulation time 326412626 ps
CPU time 10.3 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 217880 kb
Host smart-2c7d8154-35e0-4849-94d4-d9bf98d247c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847574528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1847574528
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1800867981
Short name T119
Test name
Test status
Simulation time 346794164 ps
CPU time 80.48 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:30:51 PM PDT 24
Peak memory 214212 kb
Host smart-c396e73b-798b-455d-bbdd-e9fd9b4a7a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800867981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1800867981
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.220178306
Short name T374
Test name
Test status
Simulation time 199706778 ps
CPU time 9.07 seconds
Started Aug 19 04:29:36 PM PDT 24
Finished Aug 19 04:29:45 PM PDT 24
Peak memory 217864 kb
Host smart-28bb2c7d-3252-40d3-897e-b09122dd4727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220178306 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.220178306
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.399883313
Short name T369
Test name
Test status
Simulation time 517372869 ps
CPU time 9.47 seconds
Started Aug 19 04:29:38 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 211616 kb
Host smart-467b31f5-d38e-45ba-9865-36f4bd66f46e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399883313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.399883313
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1673302149
Short name T415
Test name
Test status
Simulation time 733868803 ps
CPU time 11.48 seconds
Started Aug 19 04:29:47 PM PDT 24
Finished Aug 19 04:29:59 PM PDT 24
Peak memory 212068 kb
Host smart-9575e6dd-f104-4b9c-90fd-5982d0d1a5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673302149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1673302149
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2237471970
Short name T440
Test name
Test status
Simulation time 515724745 ps
CPU time 13.07 seconds
Started Aug 19 04:29:34 PM PDT 24
Finished Aug 19 04:29:47 PM PDT 24
Peak memory 218160 kb
Host smart-6e19e866-77e1-4eed-a825-01dc2c5c4c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237471970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2237471970
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4088870574
Short name T53
Test name
Test status
Simulation time 5021013396 ps
CPU time 150.62 seconds
Started Aug 19 04:29:46 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 215260 kb
Host smart-a86c8ffa-5b47-490b-9d37-c8c49e74abca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088870574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4088870574
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1907518850
Short name T257
Test name
Test status
Simulation time 326917216 ps
CPU time 7.89 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 218312 kb
Host smart-4c713e05-bb4f-4b13-9498-36e062c58f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907518850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1907518850
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1645563510
Short name T135
Test name
Test status
Simulation time 3165323630 ps
CPU time 231.52 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 236696 kb
Host smart-fba50140-7979-41fa-a594-d5c366f3d002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645563510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1645563510
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1060527286
Short name T170
Test name
Test status
Simulation time 1944930843 ps
CPU time 18.17 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 218760 kb
Host smart-014d4bda-43c1-4d7d-8cda-8a1591dc6064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060527286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1060527286
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3604858841
Short name T11
Test name
Test status
Simulation time 1079671406 ps
CPU time 11.28 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218828 kb
Host smart-f612f1ee-2569-49ae-8ef8-310ae0ab3c4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604858841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3604858841
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.905722920
Short name T216
Test name
Test status
Simulation time 274167909 ps
CPU time 11.77 seconds
Started Aug 19 04:31:37 PM PDT 24
Finished Aug 19 04:31:49 PM PDT 24
Peak memory 218456 kb
Host smart-4ac855a2-d8da-4c2f-ad9d-9b14c07a7be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905722920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.905722920
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1938118989
Short name T326
Test name
Test status
Simulation time 534682219 ps
CPU time 29.89 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:32:14 PM PDT 24
Peak memory 219128 kb
Host smart-132282b6-ec6a-4640-8d7e-56e6be2fbbfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938118989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1938118989
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4043551646
Short name T218
Test name
Test status
Simulation time 261083332 ps
CPU time 9.76 seconds
Started Aug 19 04:31:36 PM PDT 24
Finished Aug 19 04:31:46 PM PDT 24
Peak memory 218296 kb
Host smart-1b892fa3-660b-433a-a145-0b2296f844d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043551646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4043551646
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.868502609
Short name T284
Test name
Test status
Simulation time 26228361294 ps
CPU time 354.08 seconds
Started Aug 19 04:31:40 PM PDT 24
Finished Aug 19 04:37:34 PM PDT 24
Peak memory 237668 kb
Host smart-f46201ff-0a9d-4d12-afea-d978804bdfad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868502609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.868502609
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1208450926
Short name T323
Test name
Test status
Simulation time 1986893351 ps
CPU time 21.41 seconds
Started Aug 19 04:31:35 PM PDT 24
Finished Aug 19 04:31:56 PM PDT 24
Peak memory 218784 kb
Host smart-d3920bb4-5335-4b70-bc32-dacd01836de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208450926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1208450926
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1813542014
Short name T132
Test name
Test status
Simulation time 702741994 ps
CPU time 9.74 seconds
Started Aug 19 04:31:30 PM PDT 24
Finished Aug 19 04:31:39 PM PDT 24
Peak memory 218932 kb
Host smart-bf7d3afc-63b0-4ff5-a98d-643385965c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813542014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1813542014
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.22759950
Short name T20
Test name
Test status
Simulation time 241940581 ps
CPU time 117.68 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 237644 kb
Host smart-b2979317-ec85-4def-b03e-98848fbf5788
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.22759950
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2325211816
Short name T14
Test name
Test status
Simulation time 729976079 ps
CPU time 9.81 seconds
Started Aug 19 04:31:33 PM PDT 24
Finished Aug 19 04:31:43 PM PDT 24
Peak memory 219076 kb
Host smart-3a7f2911-769a-4e39-8613-7cb978ead437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325211816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2325211816
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3614343637
Short name T293
Test name
Test status
Simulation time 761963372 ps
CPU time 24.08 seconds
Started Aug 19 04:31:54 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 219052 kb
Host smart-4cc7001d-a2f1-425d-9985-c9aeb0114cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614343637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3614343637
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2666375685
Short name T297
Test name
Test status
Simulation time 1200013710 ps
CPU time 55.32 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 222968 kb
Host smart-af408903-508c-4b48-9332-a6abf9cc7fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666375685 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2666375685
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2722238836
Short name T314
Test name
Test status
Simulation time 290074622 ps
CPU time 9.54 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 219052 kb
Host smart-cab1e91e-3eeb-4996-8e2e-a1d4f79b05c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722238836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2722238836
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2164256749
Short name T279
Test name
Test status
Simulation time 7392723989 ps
CPU time 132.08 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 225164 kb
Host smart-260b0f54-5d27-4e0c-b3a7-abcdbbbd336f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164256749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2164256749
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3284711317
Short name T201
Test name
Test status
Simulation time 1989404139 ps
CPU time 27.98 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 219096 kb
Host smart-cc4d6e01-64a6-4072-9390-7a51bb21ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284711317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3284711317
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1018774636
Short name T93
Test name
Test status
Simulation time 268744261 ps
CPU time 11.07 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218540 kb
Host smart-36637ada-58fe-4e86-8df2-a544501c9c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018774636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1018774636
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4058974538
Short name T285
Test name
Test status
Simulation time 2172455942 ps
CPU time 30.54 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:33:19 PM PDT 24
Peak memory 217480 kb
Host smart-01701883-a013-45b9-a3ed-c71a19d19f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058974538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4058974538
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.653786729
Short name T299
Test name
Test status
Simulation time 2999747876 ps
CPU time 164.52 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 223936 kb
Host smart-de3ead6d-0fdf-469d-b5c4-88cfa2319d18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653786729 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.653786729
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.708848074
Short name T341
Test name
Test status
Simulation time 175107615 ps
CPU time 7.86 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 218368 kb
Host smart-8f583c59-277e-47c1-b009-7d78fea87142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708848074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.708848074
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.720989348
Short name T177
Test name
Test status
Simulation time 7713623206 ps
CPU time 142.1 seconds
Started Aug 19 04:31:59 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 236224 kb
Host smart-6b86ef64-8d76-4ce3-8122-b3c1b295f0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720989348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.720989348
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2750915940
Short name T1
Test name
Test status
Simulation time 3985041155 ps
CPU time 14.84 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 219068 kb
Host smart-65ee74b1-0c00-44eb-8f0d-9d9c477e8fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750915940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2750915940
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1074145823
Short name T331
Test name
Test status
Simulation time 872160244 ps
CPU time 16.27 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:32:11 PM PDT 24
Peak memory 219116 kb
Host smart-b029f9d6-b078-472a-bbbb-2ce6ceb57c6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074145823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1074145823
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4012657292
Short name T322
Test name
Test status
Simulation time 18321058069 ps
CPU time 154.78 seconds
Started Aug 19 04:31:59 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 226788 kb
Host smart-f80ce12d-1dc8-43c3-b241-e5d7ec3d032c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012657292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.4012657292
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2060226557
Short name T215
Test name
Test status
Simulation time 325509124 ps
CPU time 7.43 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:01 PM PDT 24
Peak memory 217928 kb
Host smart-c1031aec-42c3-4582-b18c-6cc899a2f6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060226557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2060226557
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1921443259
Short name T305
Test name
Test status
Simulation time 60731818114 ps
CPU time 213 seconds
Started Aug 19 04:32:57 PM PDT 24
Finished Aug 19 04:36:31 PM PDT 24
Peak memory 223944 kb
Host smart-c5c73ac3-a5ab-47d8-96b9-480da896220f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921443259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1921443259
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2185993835
Short name T180
Test name
Test status
Simulation time 2200060864 ps
CPU time 18.36 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:32:24 PM PDT 24
Peak memory 218828 kb
Host smart-acb16add-e7b5-4f17-84d2-ec57e6f2894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185993835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2185993835
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3619317433
Short name T8
Test name
Test status
Simulation time 688220669 ps
CPU time 9.64 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 218528 kb
Host smart-b5113c9e-6187-474a-a80e-1a1da0a02e6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619317433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3619317433
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4275043299
Short name T163
Test name
Test status
Simulation time 380559970 ps
CPU time 30.4 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 219064 kb
Host smart-bdfc6052-64c2-479a-bbe2-0033d9b64fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275043299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4275043299
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.878719404
Short name T152
Test name
Test status
Simulation time 9158619790 ps
CPU time 285.35 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:36:34 PM PDT 24
Peak memory 227340 kb
Host smart-08c08300-148c-49af-95a7-408b8ac2b6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878719404 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.878719404
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1657268345
Short name T43
Test name
Test status
Simulation time 718898986 ps
CPU time 7.93 seconds
Started Aug 19 04:32:04 PM PDT 24
Finished Aug 19 04:32:12 PM PDT 24
Peak memory 218272 kb
Host smart-15e13774-6d52-4588-8a6b-56fc23597c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657268345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1657268345
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1173398601
Short name T13
Test name
Test status
Simulation time 8160104566 ps
CPU time 151.38 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 236612 kb
Host smart-eeff8b23-dd7a-4872-bb80-4a3677c0224b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173398601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1173398601
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2283991320
Short name T159
Test name
Test status
Simulation time 541601518 ps
CPU time 21.67 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:13 PM PDT 24
Peak memory 218436 kb
Host smart-d7ecf606-0ef1-45d5-b9a4-f15bd583c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283991320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2283991320
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.972219796
Short name T179
Test name
Test status
Simulation time 986848970 ps
CPU time 10.91 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:06 PM PDT 24
Peak memory 218160 kb
Host smart-0d07a31d-10db-4f91-b397-08ecefa29dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972219796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.972219796
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1163012474
Short name T105
Test name
Test status
Simulation time 2566945107 ps
CPU time 25.44 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 219068 kb
Host smart-9b574ffd-424f-4482-bffc-d7b8517f0edf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163012474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1163012474
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3388383271
Short name T265
Test name
Test status
Simulation time 5206092120 ps
CPU time 262.8 seconds
Started Aug 19 04:32:59 PM PDT 24
Finished Aug 19 04:37:22 PM PDT 24
Peak memory 235228 kb
Host smart-80b0cb78-b35a-4388-a42b-5fe79ad2c4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388383271 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3388383271
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.550720815
Short name T58
Test name
Test status
Simulation time 3083739952 ps
CPU time 9.28 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:00 PM PDT 24
Peak memory 219116 kb
Host smart-a08a7021-f3bd-4b19-a991-429f43486a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550720815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.550720815
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3064641693
Short name T38
Test name
Test status
Simulation time 12495157693 ps
CPU time 203.32 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 219276 kb
Host smart-11339d95-d772-421a-833c-f9f51697f4de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064641693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3064641693
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3273834653
Short name T270
Test name
Test status
Simulation time 517709464 ps
CPU time 21.51 seconds
Started Aug 19 04:31:41 PM PDT 24
Finished Aug 19 04:32:03 PM PDT 24
Peak memory 218796 kb
Host smart-b6bf5b76-f8e2-4468-b03e-ebf6610c056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273834653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3273834653
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3946842383
Short name T130
Test name
Test status
Simulation time 188857498 ps
CPU time 9.97 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:31:58 PM PDT 24
Peak memory 218544 kb
Host smart-95952eae-5f9f-418b-8422-222fcd323485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946842383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3946842383
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1324157378
Short name T301
Test name
Test status
Simulation time 566791430 ps
CPU time 29.71 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 219116 kb
Host smart-9868d5a7-3148-4b90-84a8-f591f02a56f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324157378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1324157378
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1381407968
Short name T267
Test name
Test status
Simulation time 3152891142 ps
CPU time 36.3 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:24 PM PDT 24
Peak memory 224484 kb
Host smart-37435ecc-4131-4acf-9f16-42a23a23e816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381407968 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1381407968
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3770233055
Short name T259
Test name
Test status
Simulation time 174165010 ps
CPU time 7.74 seconds
Started Aug 19 04:31:35 PM PDT 24
Finished Aug 19 04:31:43 PM PDT 24
Peak memory 218260 kb
Host smart-2258c8fb-32e7-49b1-b162-ab772551db08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770233055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3770233055
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3314351380
Short name T27
Test name
Test status
Simulation time 8534874159 ps
CPU time 267.41 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:36:14 PM PDT 24
Peak memory 237184 kb
Host smart-a0b8e13c-a6ca-494f-979f-b7509f860b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314351380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3314351380
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1955962136
Short name T316
Test name
Test status
Simulation time 718755729 ps
CPU time 18.82 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 218708 kb
Host smart-61be8255-7f7e-47ba-8cea-3c07663001e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955962136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1955962136
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2074713938
Short name T238
Test name
Test status
Simulation time 274597007 ps
CPU time 11.54 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:32:01 PM PDT 24
Peak memory 218752 kb
Host smart-aea0d9f0-5c30-4235-abea-0c498a4a9cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074713938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2074713938
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4082086767
Short name T31
Test name
Test status
Simulation time 760853220 ps
CPU time 10.91 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 219140 kb
Host smart-ca545b68-a99f-4f09-a871-f3f1ce0e0794
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082086767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4082086767
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2804974880
Short name T243
Test name
Test status
Simulation time 2986831584 ps
CPU time 160.48 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 225624 kb
Host smart-767883d3-76a7-443c-99e7-b7870fb89be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804974880 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2804974880
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3169067124
Short name T194
Test name
Test status
Simulation time 517617464 ps
CPU time 8.88 seconds
Started Aug 19 04:32:58 PM PDT 24
Finished Aug 19 04:33:07 PM PDT 24
Peak memory 217980 kb
Host smart-5b3b667d-3b74-4e41-92c8-a0da0aac4ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169067124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3169067124
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2942441020
Short name T263
Test name
Test status
Simulation time 2640778991 ps
CPU time 170.47 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:34:40 PM PDT 24
Peak memory 241628 kb
Host smart-7f825aab-7ea2-44d0-893a-7dd07d8165f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942441020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2942441020
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2617635111
Short name T339
Test name
Test status
Simulation time 1940898330 ps
CPU time 18.51 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 218776 kb
Host smart-d11a8940-3d32-41d9-ba93-70c9b79bf76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617635111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2617635111
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2042087050
Short name T133
Test name
Test status
Simulation time 981922822 ps
CPU time 11.14 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:32:09 PM PDT 24
Peak memory 218456 kb
Host smart-2a2a467d-906b-4be9-bbb9-26dc71a20545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042087050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2042087050
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3785446043
Short name T190
Test name
Test status
Simulation time 8894450073 ps
CPU time 31.92 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 219192 kb
Host smart-170171d3-c75d-4ddb-abea-6dcf6545468c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785446043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3785446043
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1972747611
Short name T303
Test name
Test status
Simulation time 2961840862 ps
CPU time 101.82 seconds
Started Aug 19 04:32:59 PM PDT 24
Finished Aug 19 04:34:41 PM PDT 24
Peak memory 232088 kb
Host smart-29916d3b-f34b-4c09-9cb8-fcf7b500db53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972747611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1972747611
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2098333196
Short name T165
Test name
Test status
Simulation time 256695175 ps
CPU time 8.67 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:03 PM PDT 24
Peak memory 217896 kb
Host smart-d16ae67d-8b84-4946-a9a2-5af3cb07ccd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098333196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2098333196
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1900922844
Short name T261
Test name
Test status
Simulation time 6878982483 ps
CPU time 191.62 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 218452 kb
Host smart-d7a19057-b7f9-4933-b58d-ad58724bc4be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900922844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1900922844
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3197338930
Short name T290
Test name
Test status
Simulation time 497494858 ps
CPU time 20.22 seconds
Started Aug 19 04:32:58 PM PDT 24
Finished Aug 19 04:33:18 PM PDT 24
Peak memory 218080 kb
Host smart-3e36015e-4b78-4a17-ade8-dcabea1a1ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197338930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3197338930
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2447474311
Short name T30
Test name
Test status
Simulation time 357147392 ps
CPU time 9.97 seconds
Started Aug 19 04:31:41 PM PDT 24
Finished Aug 19 04:31:51 PM PDT 24
Peak memory 218808 kb
Host smart-919cb728-10a8-495f-8728-5b263cb207a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447474311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2447474311
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4064623932
Short name T104
Test name
Test status
Simulation time 294544034 ps
CPU time 15.41 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:32:00 PM PDT 24
Peak memory 219028 kb
Host smart-b092b115-6da5-498d-92af-5b567302b406
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064623932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4064623932
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3841790853
Short name T235
Test name
Test status
Simulation time 2831660571 ps
CPU time 61.32 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 224072 kb
Host smart-aaaf4fb6-1b65-4785-8647-a7b40e149a4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841790853 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3841790853
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.326107234
Short name T230
Test name
Test status
Simulation time 2749644508 ps
CPU time 7.66 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:02 PM PDT 24
Peak memory 218012 kb
Host smart-3a395d3c-5bd6-48bf-8617-d703e5234f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326107234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.326107234
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1719156635
Short name T17
Test name
Test status
Simulation time 7975480003 ps
CPU time 239.44 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 237748 kb
Host smart-65d6d1e6-da0e-4a35-bb8e-8c3a358ab057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719156635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1719156635
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.982329465
Short name T146
Test name
Test status
Simulation time 1983113612 ps
CPU time 20.35 seconds
Started Aug 19 04:32:58 PM PDT 24
Finished Aug 19 04:33:19 PM PDT 24
Peak memory 218368 kb
Host smart-9b0686e4-5cf3-4a8d-a5b4-d68e7752dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982329465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.982329465
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1485571507
Short name T99
Test name
Test status
Simulation time 525343806 ps
CPU time 10.73 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:05 PM PDT 24
Peak memory 218448 kb
Host smart-6b1079be-4d93-4cb2-9188-e264b6e6cec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485571507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1485571507
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2765701421
Short name T278
Test name
Test status
Simulation time 1888056925 ps
CPU time 32.75 seconds
Started Aug 19 04:31:43 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 219124 kb
Host smart-b4d711d7-e2c5-44a3-8d41-a4166d288c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765701421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2765701421
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3710851361
Short name T167
Test name
Test status
Simulation time 3710699524 ps
CPU time 143.59 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 235712 kb
Host smart-eb71084e-98c1-42bf-83fa-7fa46e04c034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710851361 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3710851361
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1769186751
Short name T275
Test name
Test status
Simulation time 509028430 ps
CPU time 8.94 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:33:18 PM PDT 24
Peak memory 218020 kb
Host smart-e9e116d2-5049-4b71-93f2-0d72e1d10e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769186751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1769186751
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3326181497
Short name T217
Test name
Test status
Simulation time 4590001473 ps
CPU time 211.04 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:36:20 PM PDT 24
Peak memory 233772 kb
Host smart-d224fcf3-8492-43c2-89b5-412fcaf35959
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326181497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3326181497
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2838024573
Short name T288
Test name
Test status
Simulation time 676755882 ps
CPU time 16.99 seconds
Started Aug 19 04:32:43 PM PDT 24
Finished Aug 19 04:33:01 PM PDT 24
Peak memory 217808 kb
Host smart-8b5e5924-fe22-4a26-b9c1-5bbbbcef82e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838024573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2838024573
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3598820109
Short name T202
Test name
Test status
Simulation time 439761990 ps
CPU time 11.36 seconds
Started Aug 19 04:32:48 PM PDT 24
Finished Aug 19 04:33:00 PM PDT 24
Peak memory 216328 kb
Host smart-d0929fc2-3b4d-46c4-95d1-7c50b5f20174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598820109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3598820109
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2851014865
Short name T349
Test name
Test status
Simulation time 511477263 ps
CPU time 22.02 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:16 PM PDT 24
Peak memory 218728 kb
Host smart-3731d767-5a6f-4339-b468-2aa6a4ffcb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851014865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2851014865
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4270445322
Short name T244
Test name
Test status
Simulation time 3739587341 ps
CPU time 151.92 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 233528 kb
Host smart-5aaf2fad-6144-43d9-b6bf-a0b10eb1b1f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270445322 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.4270445322
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4163998327
Short name T197
Test name
Test status
Simulation time 175492978 ps
CPU time 7.77 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:31:53 PM PDT 24
Peak memory 218276 kb
Host smart-04e2b91c-03da-4f3a-b1ce-752f4c5e320b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163998327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4163998327
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.641281931
Short name T289
Test name
Test status
Simulation time 6344254738 ps
CPU time 143.97 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 243236 kb
Host smart-97499260-594d-4f07-93cd-abbfb8f92670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641281931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.641281931
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.986584445
Short name T161
Test name
Test status
Simulation time 546930289 ps
CPU time 11.14 seconds
Started Aug 19 04:31:39 PM PDT 24
Finished Aug 19 04:31:50 PM PDT 24
Peak memory 218784 kb
Host smart-197ffd50-b976-41b6-ac09-0bf52e2c3c92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986584445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.986584445
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3196459408
Short name T26
Test name
Test status
Simulation time 279467918 ps
CPU time 225.82 seconds
Started Aug 19 04:31:54 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 237380 kb
Host smart-1630eaac-80be-4d1b-91c1-46a21cbaa0d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196459408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3196459408
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3608384639
Short name T311
Test name
Test status
Simulation time 673923707 ps
CPU time 10.05 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 219152 kb
Host smart-0d587748-124b-4247-a63a-ccb78c32aa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608384639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3608384639
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2427601225
Short name T250
Test name
Test status
Simulation time 2479220630 ps
CPU time 27.09 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 219112 kb
Host smart-29bdef57-90d1-4328-ba42-09a506f1a496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427601225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2427601225
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3851479097
Short name T124
Test name
Test status
Simulation time 4217090282 ps
CPU time 83.83 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:33:11 PM PDT 24
Peak memory 224736 kb
Host smart-c7e23e9f-14cc-4ff1-9d69-44d6ca821514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851479097 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3851479097
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2851200256
Short name T148
Test name
Test status
Simulation time 10883442433 ps
CPU time 13.47 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218256 kb
Host smart-4851922e-f985-4c50-842c-eb76e85eadbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851200256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2851200256
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3957205021
Short name T145
Test name
Test status
Simulation time 12480772321 ps
CPU time 330.18 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 237660 kb
Host smart-77994329-009f-4b58-94ce-2919a2276272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957205021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3957205021
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.183873529
Short name T329
Test name
Test status
Simulation time 1999797010 ps
CPU time 27.65 seconds
Started Aug 19 04:32:53 PM PDT 24
Finished Aug 19 04:33:21 PM PDT 24
Peak memory 218744 kb
Host smart-e5ad7280-6446-49db-a155-b523361cf7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183873529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.183873529
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3879395454
Short name T16
Test name
Test status
Simulation time 734984918 ps
CPU time 9.7 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:33:18 PM PDT 24
Peak memory 218284 kb
Host smart-697efa9a-8990-4835-b85b-ddb8b682706e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879395454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3879395454
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4255800564
Short name T136
Test name
Test status
Simulation time 1541160205 ps
CPU time 19.16 seconds
Started Aug 19 04:32:54 PM PDT 24
Finished Aug 19 04:33:14 PM PDT 24
Peak memory 218756 kb
Host smart-75e0007f-ee35-4bb5-9ada-cbeb15199a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255800564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4255800564
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.814347509
Short name T48
Test name
Test status
Simulation time 1765018094 ps
CPU time 88 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:33:26 PM PDT 24
Peak memory 227448 kb
Host smart-6b615a29-e505-4c6b-87bd-0ff2a435c05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814347509 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.814347509
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3430275486
Short name T280
Test name
Test status
Simulation time 6558373441 ps
CPU time 318.24 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:37:09 PM PDT 24
Peak memory 218616 kb
Host smart-7b6dbb42-491d-4477-a227-cb2c65df5b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430275486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3430275486
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3607983642
Short name T208
Test name
Test status
Simulation time 1324268571 ps
CPU time 18.12 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 218868 kb
Host smart-890570aa-0e46-4d93-95fd-174b06439c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607983642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3607983642
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1755427850
Short name T107
Test name
Test status
Simulation time 1128719428 ps
CPU time 11.65 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 218776 kb
Host smart-8d28fce6-9b8b-4692-8513-5cea2422c96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755427850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1755427850
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2856860488
Short name T75
Test name
Test status
Simulation time 1125792023 ps
CPU time 30.84 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 219120 kb
Host smart-04f1af9e-214e-41b5-886c-ec3d5ef4b2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856860488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2856860488
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2131754915
Short name T174
Test name
Test status
Simulation time 3708094068 ps
CPU time 71.03 seconds
Started Aug 19 04:32:27 PM PDT 24
Finished Aug 19 04:33:38 PM PDT 24
Peak memory 224592 kb
Host smart-c7fac2b6-d93a-4eea-8290-fc418c0d4088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131754915 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2131754915
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2942320244
Short name T337
Test name
Test status
Simulation time 1124286577 ps
CPU time 9.57 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:01 PM PDT 24
Peak memory 218240 kb
Host smart-a5858937-3a21-42d9-8d6d-7f0c2af8dc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942320244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2942320244
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2405321795
Short name T155
Test name
Test status
Simulation time 23028769351 ps
CPU time 173.45 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 239124 kb
Host smart-63449fb2-a006-4b9a-913b-e342e2cebaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405321795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2405321795
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1143790672
Short name T141
Test name
Test status
Simulation time 737412633 ps
CPU time 18.33 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:32:25 PM PDT 24
Peak memory 218372 kb
Host smart-ca68a918-9bf6-4565-a701-858b3354441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143790672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1143790672
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1314677858
Short name T254
Test name
Test status
Simulation time 184039274 ps
CPU time 10.04 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 218544 kb
Host smart-321b7f5a-319d-4118-8156-bd81cf1f6f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314677858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1314677858
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.532553501
Short name T315
Test name
Test status
Simulation time 407453385 ps
CPU time 21.06 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 219076 kb
Host smart-202aa22d-1cfe-466e-bc26-539c9186cad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532553501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.532553501
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.461772382
Short name T212
Test name
Test status
Simulation time 6247148313 ps
CPU time 139.6 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 233416 kb
Host smart-1c75fd28-6857-43e8-8993-136d0c8aed06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461772382 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.461772382
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2585211922
Short name T195
Test name
Test status
Simulation time 176353841 ps
CPU time 7.86 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 218240 kb
Host smart-810b2cda-f60b-46dc-87f2-32a5877d68c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585211922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2585211922
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.100573044
Short name T121
Test name
Test status
Simulation time 22053080455 ps
CPU time 393.63 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:38:43 PM PDT 24
Peak memory 239468 kb
Host smart-a47d17c7-b291-45ab-b0f3-0c73a6a56ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100573044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.100573044
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.367003659
Short name T42
Test name
Test status
Simulation time 1435615737 ps
CPU time 18.28 seconds
Started Aug 19 04:32:04 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 218884 kb
Host smart-66729381-369b-4cdc-84c1-d2258dc43c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367003659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.367003659
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.336104066
Short name T199
Test name
Test status
Simulation time 1687171540 ps
CPU time 11.15 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 218836 kb
Host smart-4f0362fe-6313-4187-a0d2-d80190372aa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336104066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.336104066
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.4089167995
Short name T348
Test name
Test status
Simulation time 18119211825 ps
CPU time 189.77 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 228248 kb
Host smart-7e1ac189-264f-49ce-b2be-d0355e48745c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089167995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.4089167995
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3555782515
Short name T231
Test name
Test status
Simulation time 339080365 ps
CPU time 7.95 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:04 PM PDT 24
Peak memory 218236 kb
Host smart-ca7afafe-fa97-4117-a187-05d09e35cd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555782515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3555782515
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4169466502
Short name T338
Test name
Test status
Simulation time 10588412958 ps
CPU time 183.07 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:35:09 PM PDT 24
Peak memory 218816 kb
Host smart-89037aa8-75cc-4764-9a9b-7d6a80546e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169466502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4169466502
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3162798182
Short name T131
Test name
Test status
Simulation time 517431931 ps
CPU time 21.15 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 218780 kb
Host smart-5b79b433-0190-401a-9de9-598ab4ff91a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162798182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3162798182
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3676277039
Short name T313
Test name
Test status
Simulation time 2319868608 ps
CPU time 11.54 seconds
Started Aug 19 04:32:00 PM PDT 24
Finished Aug 19 04:32:11 PM PDT 24
Peak memory 218864 kb
Host smart-accf4a34-c734-4487-a4a7-abc7ee979e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676277039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3676277039
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1424097185
Short name T46
Test name
Test status
Simulation time 1021350393 ps
CPU time 29.09 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:32:27 PM PDT 24
Peak memory 219020 kb
Host smart-1728dba2-831a-4af5-877a-5fa29d6294db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424097185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1424097185
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1377226064
Short name T47
Test name
Test status
Simulation time 811093732 ps
CPU time 32.88 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 222660 kb
Host smart-9a622d14-683a-4b9b-9e54-f599ed87518b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377226064 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1377226064
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3823195768
Short name T143
Test name
Test status
Simulation time 250035810 ps
CPU time 9.51 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 218312 kb
Host smart-36a5d996-a200-4835-a1a8-5a4dd087b43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823195768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3823195768
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1889115960
Short name T98
Test name
Test status
Simulation time 10905058209 ps
CPU time 291.18 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:37:07 PM PDT 24
Peak memory 236040 kb
Host smart-5eed2834-302b-42ff-a3fa-99cf02e0bb03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889115960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1889115960
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1195502655
Short name T41
Test name
Test status
Simulation time 349951328 ps
CPU time 17.77 seconds
Started Aug 19 04:32:18 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 218456 kb
Host smart-0a5fa589-d031-4867-8650-ba5313cb5148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195502655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1195502655
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.612985897
Short name T233
Test name
Test status
Simulation time 1914336082 ps
CPU time 15.73 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 219116 kb
Host smart-c8892ed8-e858-4560-babf-83a7fe1056c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612985897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.612985897
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4279704764
Short name T211
Test name
Test status
Simulation time 2748351302 ps
CPU time 44.49 seconds
Started Aug 19 04:32:30 PM PDT 24
Finished Aug 19 04:33:14 PM PDT 24
Peak memory 219148 kb
Host smart-c8931f7d-099e-4025-889d-818707d102c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279704764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4279704764
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.11698372
Short name T122
Test name
Test status
Simulation time 59596954710 ps
CPU time 157.07 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 230020 kb
Host smart-f53e54cc-b0d7-40d6-86e9-d56d8271844c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698372 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.11698372
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2211854445
Short name T319
Test name
Test status
Simulation time 222453015 ps
CPU time 7.98 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 218276 kb
Host smart-43f8547f-339a-45ea-a5ba-b0cfe8350ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211854445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2211854445
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1540349968
Short name T302
Test name
Test status
Simulation time 21620614998 ps
CPU time 307.55 seconds
Started Aug 19 04:32:00 PM PDT 24
Finished Aug 19 04:37:07 PM PDT 24
Peak memory 237808 kb
Host smart-a2c07832-2ded-4b3f-abf3-e013623af2e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540349968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1540349968
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1585950282
Short name T154
Test name
Test status
Simulation time 994470526 ps
CPU time 21.22 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:32:19 PM PDT 24
Peak memory 218476 kb
Host smart-79c2dcf5-187b-4f4a-a2ff-64948666a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585950282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1585950282
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4105851620
Short name T189
Test name
Test status
Simulation time 717507764 ps
CPU time 9.76 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 218936 kb
Host smart-e09dc419-d238-4f4c-9c62-24342e7dc8d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105851620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4105851620
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2009670706
Short name T240
Test name
Test status
Simulation time 3295243077 ps
CPU time 34.04 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 219200 kb
Host smart-c641ddff-050a-49b2-848c-9c067d87fc1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009670706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2009670706
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.940729745
Short name T262
Test name
Test status
Simulation time 1899151945 ps
CPU time 72.18 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:33:25 PM PDT 24
Peak memory 224188 kb
Host smart-07169fa0-21f4-4813-a379-9a1dedbf9c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940729745 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.940729745
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3772272114
Short name T186
Test name
Test status
Simulation time 987910790 ps
CPU time 9.38 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 218304 kb
Host smart-1321a9fe-4371-4b89-a413-5fa2c25ac76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772272114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3772272114
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3085370167
Short name T94
Test name
Test status
Simulation time 23729225604 ps
CPU time 225.91 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 219036 kb
Host smart-8cba7e97-6738-4706-9c5d-0b2a805a694f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085370167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3085370167
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2120766448
Short name T149
Test name
Test status
Simulation time 517449080 ps
CPU time 21.15 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:13 PM PDT 24
Peak memory 218508 kb
Host smart-c94e9fdd-e469-443b-978f-5a9e95f18d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120766448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2120766448
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1320636514
Short name T140
Test name
Test status
Simulation time 518707646 ps
CPU time 11.23 seconds
Started Aug 19 04:32:17 PM PDT 24
Finished Aug 19 04:32:28 PM PDT 24
Peak memory 218568 kb
Host smart-39c66851-2c7d-40f6-a679-2cdad1347189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320636514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1320636514
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3664994616
Short name T292
Test name
Test status
Simulation time 347048601 ps
CPU time 26.59 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 219072 kb
Host smart-4681e630-ece2-41e2-90cc-08c50e7719a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664994616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3664994616
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1564842124
Short name T183
Test name
Test status
Simulation time 6638095826 ps
CPU time 133.47 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 226276 kb
Host smart-e4ec239c-1792-42ee-a879-9a9077afe464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564842124 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1564842124
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.339964846
Short name T239
Test name
Test status
Simulation time 994465993 ps
CPU time 9.8 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 218320 kb
Host smart-5c2813af-63fc-4d73-9df5-50e632050e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339964846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.339964846
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.745452438
Short name T175
Test name
Test status
Simulation time 7942609355 ps
CPU time 134.17 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 236768 kb
Host smart-6b7138f1-f0e8-4d1d-af3f-661ef510afe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745452438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.745452438
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.280167969
Short name T188
Test name
Test status
Simulation time 2205851446 ps
CPU time 18.41 seconds
Started Aug 19 04:31:56 PM PDT 24
Finished Aug 19 04:32:14 PM PDT 24
Peak memory 218532 kb
Host smart-4c754059-db8d-475a-9f7e-9b0ae4294495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280167969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.280167969
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3902179883
Short name T200
Test name
Test status
Simulation time 710920231 ps
CPU time 9.45 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218852 kb
Host smart-5855401a-5a89-4fa0-af48-12e6ed32aba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902179883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3902179883
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1251578770
Short name T258
Test name
Test status
Simulation time 539922524 ps
CPU time 32.53 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:43 PM PDT 24
Peak memory 219124 kb
Host smart-3603edfb-9c25-49f6-ac6a-57ef8d7d7627
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251578770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1251578770
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2413953355
Short name T291
Test name
Test status
Simulation time 589930269 ps
CPU time 7.89 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:32:05 PM PDT 24
Peak memory 218328 kb
Host smart-88e0e502-33b8-40da-aba2-da542fe46857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413953355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2413953355
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1252495862
Short name T232
Test name
Test status
Simulation time 689498704 ps
CPU time 18.78 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:32:08 PM PDT 24
Peak memory 218784 kb
Host smart-d70b00fa-9ca7-4bf9-9fd5-a4eb5170bf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252495862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1252495862
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1390015891
Short name T247
Test name
Test status
Simulation time 185549758 ps
CPU time 9.93 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:00 PM PDT 24
Peak memory 218572 kb
Host smart-91a76636-72f1-44ec-993e-2a97f5c3a284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390015891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1390015891
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.750104843
Short name T126
Test name
Test status
Simulation time 4242036477 ps
CPU time 47.92 seconds
Started Aug 19 04:32:01 PM PDT 24
Finished Aug 19 04:32:49 PM PDT 24
Peak memory 219528 kb
Host smart-9753fbe8-964f-4b77-bd62-53a91c8e892d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750104843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.750104843
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.642867291
Short name T308
Test name
Test status
Simulation time 2621349484 ps
CPU time 51.08 seconds
Started Aug 19 04:32:05 PM PDT 24
Finished Aug 19 04:32:56 PM PDT 24
Peak memory 223036 kb
Host smart-803c8c70-207f-4283-93fa-299cfc6f71bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642867291 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.642867291
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3962179098
Short name T321
Test name
Test status
Simulation time 169156690 ps
CPU time 7.72 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:00 PM PDT 24
Peak memory 218348 kb
Host smart-bef24579-b7a1-445f-acea-a601d892035f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962179098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3962179098
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4225928263
Short name T95
Test name
Test status
Simulation time 2746872026 ps
CPU time 18.47 seconds
Started Aug 19 04:31:42 PM PDT 24
Finished Aug 19 04:32:01 PM PDT 24
Peak memory 218840 kb
Host smart-42a5febf-907a-437c-a97e-0b5076bf7ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225928263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4225928263
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2697886053
Short name T283
Test name
Test status
Simulation time 185040263 ps
CPU time 9.86 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:31:58 PM PDT 24
Peak memory 218524 kb
Host smart-53d61c91-5391-4f95-86b8-5572795ab461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697886053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2697886053
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3648142411
Short name T25
Test name
Test status
Simulation time 1337236818 ps
CPU time 225.06 seconds
Started Aug 19 04:31:31 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 238680 kb
Host smart-116436ff-2d8b-4091-9e90-1c293f87e253
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648142411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3648142411
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1486140794
Short name T304
Test name
Test status
Simulation time 271111737 ps
CPU time 11.91 seconds
Started Aug 19 04:31:42 PM PDT 24
Finished Aug 19 04:31:54 PM PDT 24
Peak memory 218336 kb
Host smart-496ec357-c5d0-4c3b-a58c-409116cc8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486140794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1486140794
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1262576238
Short name T333
Test name
Test status
Simulation time 2026523351 ps
CPU time 39.46 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 219112 kb
Host smart-fbcbfb0c-ef8b-442c-be6d-bf4b87c6143c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262576238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1262576238
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3100247806
Short name T51
Test name
Test status
Simulation time 3004000710 ps
CPU time 110.34 seconds
Started Aug 19 04:31:43 PM PDT 24
Finished Aug 19 04:33:34 PM PDT 24
Peak memory 226196 kb
Host smart-fdfd741f-f2bb-477e-9506-fa39ad9645d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100247806 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3100247806
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3027334431
Short name T171
Test name
Test status
Simulation time 688652256 ps
CPU time 7.88 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 218320 kb
Host smart-6da4f5eb-261c-4d40-b419-55343b315702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027334431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3027334431
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1430075161
Short name T97
Test name
Test status
Simulation time 2072686490 ps
CPU time 152.22 seconds
Started Aug 19 04:31:53 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 243124 kb
Host smart-c092cde3-d367-4301-912f-769952e869f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430075161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1430075161
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3704266950
Short name T182
Test name
Test status
Simulation time 340093237 ps
CPU time 19.13 seconds
Started Aug 19 04:32:26 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 218608 kb
Host smart-da6709b9-c6df-4523-8a3c-1221b1372959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704266950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3704266950
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2383217957
Short name T204
Test name
Test status
Simulation time 264521981 ps
CPU time 11.91 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:04 PM PDT 24
Peak memory 219184 kb
Host smart-06954f5e-f0a5-4627-8a9f-68b34115636a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383217957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2383217957
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4205381556
Short name T142
Test name
Test status
Simulation time 370102161 ps
CPU time 23.18 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:15 PM PDT 24
Peak memory 219120 kb
Host smart-0a216559-ffe8-40d7-a2e6-6fe6a815bfa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205381556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4205381556
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1213495801
Short name T268
Test name
Test status
Simulation time 20054507795 ps
CPU time 47.33 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:32:42 PM PDT 24
Peak memory 232652 kb
Host smart-2b59c189-72d8-404c-a3f1-dd08ff20f386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213495801 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1213495801
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1723954779
Short name T156
Test name
Test status
Simulation time 649759852 ps
CPU time 9.02 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:33:18 PM PDT 24
Peak memory 217968 kb
Host smart-0c1c7ecb-4f8e-47df-87b4-fe27aac2dcd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723954779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1723954779
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.930646529
Short name T298
Test name
Test status
Simulation time 2745634741 ps
CPU time 202.79 seconds
Started Aug 19 04:31:57 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 226716 kb
Host smart-e7bc37fc-86b1-4025-b048-07422b2b0f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930646529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.930646529
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.644869076
Short name T273
Test name
Test status
Simulation time 2906101044 ps
CPU time 22.07 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 218748 kb
Host smart-32ff15eb-54cf-4623-ab30-684e9566f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644869076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.644869076
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.259422806
Short name T266
Test name
Test status
Simulation time 527290744 ps
CPU time 11.54 seconds
Started Aug 19 04:32:04 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 218760 kb
Host smart-18ab2283-332b-49c8-a7c9-66de98139252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259422806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.259422806
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3608567230
Short name T172
Test name
Test status
Simulation time 216392222 ps
CPU time 10.37 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 219072 kb
Host smart-7a69608a-a63d-41a0-8d20-471c4ca21302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608567230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3608567230
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4181403718
Short name T49
Test name
Test status
Simulation time 5835209668 ps
CPU time 64.03 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:52 PM PDT 24
Peak memory 232920 kb
Host smart-e1bbc91a-bad5-434d-9407-3fae0e90916e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181403718 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4181403718
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3295908702
Short name T187
Test name
Test status
Simulation time 257472461 ps
CPU time 9.68 seconds
Started Aug 19 04:32:04 PM PDT 24
Finished Aug 19 04:32:13 PM PDT 24
Peak memory 218400 kb
Host smart-75a0d313-b17b-42a4-8db4-f61268089e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295908702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3295908702
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2951864313
Short name T282
Test name
Test status
Simulation time 29805287475 ps
CPU time 308.52 seconds
Started Aug 19 04:32:55 PM PDT 24
Finished Aug 19 04:38:04 PM PDT 24
Peak memory 239868 kb
Host smart-3b81667c-5afd-4541-bb69-eaa2479b2ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951864313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2951864313
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1522552567
Short name T224
Test name
Test status
Simulation time 1380714824 ps
CPU time 18.71 seconds
Started Aug 19 04:31:59 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 218340 kb
Host smart-4fb091f8-2a6e-4320-8159-59420c023ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522552567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1522552567
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3235097245
Short name T220
Test name
Test status
Simulation time 184862330 ps
CPU time 10.21 seconds
Started Aug 19 04:32:00 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 218620 kb
Host smart-d0f06744-75b2-4ed0-9333-bcb426b9a024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235097245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3235097245
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2297179898
Short name T300
Test name
Test status
Simulation time 562894714 ps
CPU time 31.07 seconds
Started Aug 19 04:31:56 PM PDT 24
Finished Aug 19 04:32:28 PM PDT 24
Peak memory 218988 kb
Host smart-a8302530-a028-4d46-9bf9-1e6902ec4b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297179898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2297179898
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.525645894
Short name T306
Test name
Test status
Simulation time 5574346891 ps
CPU time 194.03 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:36:23 PM PDT 24
Peak memory 234504 kb
Host smart-c1d1b9b2-975a-43ed-ae52-c2344d0a8909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525645894 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.525645894
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3007753346
Short name T22
Test name
Test status
Simulation time 661407489 ps
CPU time 8.09 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 218324 kb
Host smart-2dd43216-385e-41ee-ae71-dabf051ccc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007753346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3007753346
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3795250392
Short name T40
Test name
Test status
Simulation time 4099526574 ps
CPU time 205.96 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:36:35 PM PDT 24
Peak memory 236948 kb
Host smart-65f509ea-e337-4b35-ac68-3e6f77131a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795250392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3795250392
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3707712563
Short name T335
Test name
Test status
Simulation time 536648079 ps
CPU time 20.88 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 218504 kb
Host smart-f0882eb5-e6fa-4ddc-a406-e0487a1fb303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707712563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3707712563
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1735352892
Short name T241
Test name
Test status
Simulation time 525436905 ps
CPU time 11.72 seconds
Started Aug 19 04:31:56 PM PDT 24
Finished Aug 19 04:32:08 PM PDT 24
Peak memory 218724 kb
Host smart-bf561ace-17e6-4533-bab2-1c7dc65ba49d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735352892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1735352892
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.33020107
Short name T271
Test name
Test status
Simulation time 12555781187 ps
CPU time 48.96 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 220620 kb
Host smart-566acb09-f9dd-48ce-b82a-4c2da3b5ebf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.rom_ctrl_stress_all.33020107
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1977340104
Short name T184
Test name
Test status
Simulation time 2535401072 ps
CPU time 96.85 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 223932 kb
Host smart-6db83acd-1489-44e9-9fbd-19024e0e5650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977340104 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1977340104
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4095628224
Short name T61
Test name
Test status
Simulation time 250272951 ps
CPU time 9.54 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:32:08 PM PDT 24
Peak memory 218200 kb
Host smart-606ad369-235e-4862-896a-dd45f32b3f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095628224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4095628224
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1761187838
Short name T138
Test name
Test status
Simulation time 8686141225 ps
CPU time 175.5 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 240676 kb
Host smart-2a5a0a86-a289-4405-8ec0-e73a979aaf27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761187838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1761187838
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2468656682
Short name T229
Test name
Test status
Simulation time 5943491269 ps
CPU time 30.03 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 219168 kb
Host smart-b51700ba-b245-4c5a-b751-31bef58e134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468656682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2468656682
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1557365091
Short name T269
Test name
Test status
Simulation time 799302904 ps
CPU time 9.51 seconds
Started Aug 19 04:33:08 PM PDT 24
Finished Aug 19 04:33:18 PM PDT 24
Peak memory 218392 kb
Host smart-3eaf3254-bafc-4048-874c-fa98c0b36e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557365091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1557365091
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1325588106
Short name T15
Test name
Test status
Simulation time 1747814234 ps
CPU time 19.5 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 219024 kb
Host smart-54cc5d79-4575-4d13-a887-5a3baf5f08b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325588106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1325588106
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2672605145
Short name T50
Test name
Test status
Simulation time 10286368505 ps
CPU time 123.2 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 235664 kb
Host smart-82972ae6-56b5-4202-bb39-fdd1b163c540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672605145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2672605145
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3906387798
Short name T60
Test name
Test status
Simulation time 917967395 ps
CPU time 7.96 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 218204 kb
Host smart-fe314729-0a85-4e5b-8b4f-87bcd3bba2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906387798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3906387798
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2579973754
Short name T234
Test name
Test status
Simulation time 1495500672 ps
CPU time 113.71 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:34:00 PM PDT 24
Peak memory 235756 kb
Host smart-4caf402f-49cf-4413-ad16-da8d8ab9c305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579973754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2579973754
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.597180834
Short name T353
Test name
Test status
Simulation time 2057400971 ps
CPU time 21.77 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:33 PM PDT 24
Peak memory 218788 kb
Host smart-a5ddf8c3-7a4f-439e-8df4-adba9788fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597180834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.597180834
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2308197800
Short name T351
Test name
Test status
Simulation time 373568547 ps
CPU time 9.91 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 218844 kb
Host smart-0b2e0bad-7307-4e1e-afc4-c50f46dc447f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308197800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2308197800
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2132881140
Short name T264
Test name
Test status
Simulation time 364609916 ps
CPU time 13.31 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:03 PM PDT 24
Peak memory 218828 kb
Host smart-a76c1901-e234-4152-a490-60438156b9cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132881140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2132881140
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3707740453
Short name T151
Test name
Test status
Simulation time 21547183354 ps
CPU time 195.88 seconds
Started Aug 19 04:31:59 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 235540 kb
Host smart-30c30cab-8628-475a-9a0b-adb8fb8a50f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707740453 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3707740453
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3443054136
Short name T59
Test name
Test status
Simulation time 338878900 ps
CPU time 7.82 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 218296 kb
Host smart-68eb7a7f-daf3-47b5-8a0e-b45af99adc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443054136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3443054136
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3862108038
Short name T222
Test name
Test status
Simulation time 8712340049 ps
CPU time 281.07 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 229396 kb
Host smart-be626c19-7fee-4664-a8b1-5dae5405ef9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862108038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3862108038
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3970078320
Short name T44
Test name
Test status
Simulation time 502067726 ps
CPU time 21.17 seconds
Started Aug 19 04:31:53 PM PDT 24
Finished Aug 19 04:32:14 PM PDT 24
Peak memory 218888 kb
Host smart-3bbeac20-bc69-4ede-80c0-58a3b78277c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970078320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3970078320
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2348887320
Short name T219
Test name
Test status
Simulation time 798515006 ps
CPU time 10.36 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:32:30 PM PDT 24
Peak memory 218868 kb
Host smart-cbd52360-8236-466a-9e27-4f2d6587e98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348887320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2348887320
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.603601427
Short name T274
Test name
Test status
Simulation time 574008812 ps
CPU time 23.45 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:32:13 PM PDT 24
Peak memory 219120 kb
Host smart-7ba385d6-30da-473e-9cf3-874b2b822af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603601427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.603601427
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3519966171
Short name T281
Test name
Test status
Simulation time 376978476 ps
CPU time 8.05 seconds
Started Aug 19 04:32:01 PM PDT 24
Finished Aug 19 04:32:09 PM PDT 24
Peak memory 218240 kb
Host smart-add4d498-fd39-460b-b2cc-99f1bdb7bc20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519966171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3519966171
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3239017552
Short name T39
Test name
Test status
Simulation time 5716743343 ps
CPU time 191.14 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 233624 kb
Host smart-9fd4976c-1c2e-4e20-8d5e-86827fd3c78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239017552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3239017552
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.427147256
Short name T246
Test name
Test status
Simulation time 2064163787 ps
CPU time 21.01 seconds
Started Aug 19 04:31:54 PM PDT 24
Finished Aug 19 04:32:15 PM PDT 24
Peak memory 218896 kb
Host smart-e702d926-ca15-4a19-b02b-8c073457b1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427147256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.427147256
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2622196292
Short name T357
Test name
Test status
Simulation time 182914188 ps
CPU time 9.81 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:24 PM PDT 24
Peak memory 218472 kb
Host smart-be001c2e-3f13-4cef-b706-54f634631f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622196292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2622196292
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1047182899
Short name T71
Test name
Test status
Simulation time 4819603884 ps
CPU time 29.53 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:32:46 PM PDT 24
Peak memory 219184 kb
Host smart-a185b041-c8b7-4ead-ac20-dcf524697583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047182899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1047182899
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2750223017
Short name T328
Test name
Test status
Simulation time 5046415032 ps
CPU time 50.44 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:33:05 PM PDT 24
Peak memory 224356 kb
Host smart-89d192f9-582f-4d11-a5d2-5b0ab7be8520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750223017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2750223017
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1712239564
Short name T100
Test name
Test status
Simulation time 1645344678 ps
CPU time 9.27 seconds
Started Aug 19 04:32:23 PM PDT 24
Finished Aug 19 04:32:32 PM PDT 24
Peak memory 218248 kb
Host smart-a5d960b2-d594-4553-a023-6457fe4d4096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712239564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1712239564
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.854376915
Short name T226
Test name
Test status
Simulation time 20113097262 ps
CPU time 263.46 seconds
Started Aug 19 04:32:24 PM PDT 24
Finished Aug 19 04:36:47 PM PDT 24
Peak memory 236360 kb
Host smart-49843144-4d63-49d2-8117-1d044ae4798d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854376915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.854376915
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1047351830
Short name T287
Test name
Test status
Simulation time 503631956 ps
CPU time 21.11 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 218792 kb
Host smart-a0fafeed-4c90-42ea-aac0-ab7994692058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047351830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1047351830
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2161839402
Short name T106
Test name
Test status
Simulation time 175767118 ps
CPU time 9.87 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 218572 kb
Host smart-5f28609a-69a7-4e74-9138-3ff94e86f947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161839402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2161839402
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.20986269
Short name T347
Test name
Test status
Simulation time 8361018982 ps
CPU time 25.89 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 219164 kb
Host smart-27782a9b-88f5-49e1-971a-c4257f6e0f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.rom_ctrl_stress_all.20986269
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3699354536
Short name T296
Test name
Test status
Simulation time 2767160522 ps
CPU time 156.61 seconds
Started Aug 19 04:32:27 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 224252 kb
Host smart-a858f79a-b682-4075-a642-15032641380c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699354536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3699354536
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2622318042
Short name T129
Test name
Test status
Simulation time 692936043 ps
CPU time 8.22 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:32:28 PM PDT 24
Peak memory 218316 kb
Host smart-3fe04445-b583-4bab-9c8c-e01ee2ebaa77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622318042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2622318042
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3211666306
Short name T325
Test name
Test status
Simulation time 19081091535 ps
CPU time 248.86 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:36:11 PM PDT 24
Peak memory 219504 kb
Host smart-7a679076-7467-4b36-ae16-e839936664aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211666306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3211666306
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3115739048
Short name T252
Test name
Test status
Simulation time 530922276 ps
CPU time 21.35 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 218504 kb
Host smart-aaa4be60-9f06-43b0-ac31-c37c0afd2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115739048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3115739048
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3045534818
Short name T147
Test name
Test status
Simulation time 259325176 ps
CPU time 11.66 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:32:19 PM PDT 24
Peak memory 218820 kb
Host smart-0e088131-25f8-49e0-995b-a6c9c563d189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045534818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3045534818
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3460307614
Short name T29
Test name
Test status
Simulation time 808641230 ps
CPU time 37.75 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:48 PM PDT 24
Peak memory 219076 kb
Host smart-c0b0bb0a-3c2f-435f-b048-e31292bf9d72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460307614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3460307614
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1366926032
Short name T327
Test name
Test status
Simulation time 4555292843 ps
CPU time 163.76 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 235668 kb
Host smart-28e19a43-61af-4a17-8a75-fb7b07bdac3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366926032 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1366926032
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1853860319
Short name T168
Test name
Test status
Simulation time 449513189 ps
CPU time 7.74 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 218364 kb
Host smart-98c8f9a6-fb96-4731-93af-7c6547119340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853860319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1853860319
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3222894931
Short name T346
Test name
Test status
Simulation time 6575508903 ps
CPU time 104.25 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:33:35 PM PDT 24
Peak memory 224388 kb
Host smart-42459a77-a800-497b-9dec-e53cbb622b2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222894931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3222894931
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1617184671
Short name T191
Test name
Test status
Simulation time 1380647093 ps
CPU time 18.55 seconds
Started Aug 19 04:31:41 PM PDT 24
Finished Aug 19 04:31:59 PM PDT 24
Peak memory 218680 kb
Host smart-3f63c587-1200-4a76-8198-3b0feda80f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617184671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1617184671
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.304216730
Short name T18
Test name
Test status
Simulation time 627164772 ps
CPU time 118.17 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 237724 kb
Host smart-78ec5a38-40d0-461a-862b-39d386d3786b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304216730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.304216730
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.470778358
Short name T35
Test name
Test status
Simulation time 269819998 ps
CPU time 11.67 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 219124 kb
Host smart-05c11f69-e722-43f0-92d1-c06688a3feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470778358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.470778358
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4162650715
Short name T62
Test name
Test status
Simulation time 1708169074 ps
CPU time 22.05 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 219416 kb
Host smart-b2da8529-6f64-4129-bbc2-9344a3c55f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162650715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4162650715
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.377506729
Short name T350
Test name
Test status
Simulation time 249243398 ps
CPU time 9.27 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 218320 kb
Host smart-d55d313b-6fc2-444c-ba53-9352853b24de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377506729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.377506729
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1944465107
Short name T225
Test name
Test status
Simulation time 49685098139 ps
CPU time 181.74 seconds
Started Aug 19 04:32:07 PM PDT 24
Finished Aug 19 04:35:09 PM PDT 24
Peak memory 238804 kb
Host smart-0efdd982-30c1-41df-9453-7d06f2343edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944465107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1944465107
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2613040012
Short name T286
Test name
Test status
Simulation time 8246050754 ps
CPU time 21.71 seconds
Started Aug 19 04:32:16 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 218836 kb
Host smart-e1e677c0-b8f3-414a-a0d4-c3e9ae997d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613040012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2613040012
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.815992672
Short name T96
Test name
Test status
Simulation time 267061425 ps
CPU time 11.32 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:32:34 PM PDT 24
Peak memory 218852 kb
Host smart-6f69fa8d-2d4d-4d98-a20d-a1733308998a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815992672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.815992672
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3209322749
Short name T127
Test name
Test status
Simulation time 527241118 ps
CPU time 25.14 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:38 PM PDT 24
Peak memory 219040 kb
Host smart-b5b8e91e-8404-4be3-80c7-68c6dcbcddec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209322749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3209322749
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1741574710
Short name T28
Test name
Test status
Simulation time 2282745620 ps
CPU time 98.51 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:33:50 PM PDT 24
Peak memory 224244 kb
Host smart-3202023e-de36-45de-abe3-af636b4832f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741574710 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1741574710
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1265285379
Short name T318
Test name
Test status
Simulation time 338469992 ps
CPU time 7.66 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 218328 kb
Host smart-68001d70-c728-4c54-97a3-3bdc0c6872ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265285379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1265285379
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1288487949
Short name T36
Test name
Test status
Simulation time 2872649241 ps
CPU time 182.43 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 218528 kb
Host smart-430e0502-ee1e-4ea8-b794-40fad96327ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288487949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1288487949
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2498206154
Short name T253
Test name
Test status
Simulation time 339218988 ps
CPU time 18.37 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:32:26 PM PDT 24
Peak memory 218472 kb
Host smart-dcbf46ed-3a79-43b6-8323-f3f909c8f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498206154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2498206154
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1526834656
Short name T221
Test name
Test status
Simulation time 719834707 ps
CPU time 11.75 seconds
Started Aug 19 04:32:23 PM PDT 24
Finished Aug 19 04:32:35 PM PDT 24
Peak memory 218860 kb
Host smart-44baacf3-5103-491a-aad7-4e255e0e6b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526834656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1526834656
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.500907083
Short name T150
Test name
Test status
Simulation time 1698178663 ps
CPU time 26.11 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:39 PM PDT 24
Peak memory 219148 kb
Host smart-965f2008-6a54-4002-a275-524bab2c047c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500907083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.500907083
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3497077582
Short name T123
Test name
Test status
Simulation time 6479357876 ps
CPU time 121.13 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 226092 kb
Host smart-3e8e3b90-0b9e-42cf-9b1f-cda4f2058655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497077582 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3497077582
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2617787529
Short name T205
Test name
Test status
Simulation time 1127737029 ps
CPU time 9.62 seconds
Started Aug 19 04:32:07 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 219000 kb
Host smart-590c5b8a-4f64-4108-a54f-b03dbbcfb3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617787529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2617787529
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.576385083
Short name T276
Test name
Test status
Simulation time 11108015562 ps
CPU time 172.06 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 219140 kb
Host smart-c7e2be92-a1f9-4623-ae78-7596887882bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576385083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.576385083
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1874530111
Short name T4
Test name
Test status
Simulation time 357174416 ps
CPU time 18.5 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:33 PM PDT 24
Peak memory 218524 kb
Host smart-2247af04-985f-48a6-a455-e9e4246d64b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874530111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1874530111
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1826064320
Short name T248
Test name
Test status
Simulation time 348123391 ps
CPU time 10.05 seconds
Started Aug 19 04:32:35 PM PDT 24
Finished Aug 19 04:32:45 PM PDT 24
Peak memory 218772 kb
Host smart-38b2cce9-8d9e-4e5e-86d3-208a4b823d31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826064320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1826064320
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2819884412
Short name T176
Test name
Test status
Simulation time 10824578018 ps
CPU time 27.67 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 219108 kb
Host smart-c84ddce7-3457-420c-b3d8-5117f36905d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819884412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2819884412
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1697332593
Short name T10
Test name
Test status
Simulation time 1024846280 ps
CPU time 41.84 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:33:01 PM PDT 24
Peak memory 222824 kb
Host smart-14f2831e-65fa-4a9b-aab1-c04d1827ed6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697332593 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1697332593
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4185582224
Short name T355
Test name
Test status
Simulation time 186102234 ps
CPU time 7.98 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:19 PM PDT 24
Peak memory 218340 kb
Host smart-c55cba90-624e-4271-b52d-603164426c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185582224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4185582224
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4078552449
Short name T173
Test name
Test status
Simulation time 12616415434 ps
CPU time 152.07 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:34:47 PM PDT 24
Peak memory 233508 kb
Host smart-d367cd31-fc14-4f38-97f3-0842dfbc2ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078552449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4078552449
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2598404500
Short name T139
Test name
Test status
Simulation time 497681535 ps
CPU time 22.1 seconds
Started Aug 19 04:32:06 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 218696 kb
Host smart-86be7cb1-270a-4830-b4a2-f2ae2a59d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598404500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2598404500
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4073040085
Short name T356
Test name
Test status
Simulation time 1016974317 ps
CPU time 11.44 seconds
Started Aug 19 04:32:07 PM PDT 24
Finished Aug 19 04:32:19 PM PDT 24
Peak memory 218864 kb
Host smart-2e6d8815-41b9-44ec-9951-eca62474d5e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073040085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4073040085
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1208809188
Short name T309
Test name
Test status
Simulation time 367155781 ps
CPU time 22.47 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:32 PM PDT 24
Peak memory 219072 kb
Host smart-4ad28cc1-7189-4438-a68f-98a7d30d96c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208809188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1208809188
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1589219147
Short name T210
Test name
Test status
Simulation time 6691480875 ps
CPU time 81.52 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:33:40 PM PDT 24
Peak memory 224656 kb
Host smart-a585da02-1bec-42b2-8590-da1fd24c906c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589219147 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1589219147
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3619224833
Short name T209
Test name
Test status
Simulation time 1185652750 ps
CPU time 8.21 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 218284 kb
Host smart-a31c5606-4c81-4bc5-bcc2-50c28f6024b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619224833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3619224833
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.748333628
Short name T37
Test name
Test status
Simulation time 15440204307 ps
CPU time 238.91 seconds
Started Aug 19 04:32:08 PM PDT 24
Finished Aug 19 04:36:07 PM PDT 24
Peak memory 240476 kb
Host smart-73efd906-0d63-4908-b399-cbcb856256fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748333628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.748333628
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3824497406
Short name T345
Test name
Test status
Simulation time 523533823 ps
CPU time 21.43 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:35 PM PDT 24
Peak memory 218588 kb
Host smart-6bd4733e-f9f1-437d-8b34-f6eef281fe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824497406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3824497406
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2411446371
Short name T34
Test name
Test status
Simulation time 1938310802 ps
CPU time 11.24 seconds
Started Aug 19 04:32:19 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 218920 kb
Host smart-184406c0-e1da-48fd-a1ef-5bab3967dd0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411446371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2411446371
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.718975169
Short name T295
Test name
Test status
Simulation time 2582976826 ps
CPU time 95.35 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 223756 kb
Host smart-34ddceec-e54e-4879-9a51-cae651eae755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718975169 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.718975169
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1033740153
Short name T207
Test name
Test status
Simulation time 2353467395 ps
CPU time 7.71 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 218384 kb
Host smart-23990ede-0457-4b9f-a40c-cefc7a6b3ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033740153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1033740153
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1477519392
Short name T120
Test name
Test status
Simulation time 13393444864 ps
CPU time 375.35 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:38:25 PM PDT 24
Peak memory 218996 kb
Host smart-a938da04-fa8e-446c-a2ca-e50e868cc8dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477519392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1477519392
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.18833480
Short name T23
Test name
Test status
Simulation time 8221665315 ps
CPU time 20.99 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:32:30 PM PDT 24
Peak memory 218868 kb
Host smart-29101524-efd0-4a37-95c1-4517f98a885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18833480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.18833480
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1858301935
Short name T153
Test name
Test status
Simulation time 9050386361 ps
CPU time 15.66 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:32:37 PM PDT 24
Peak memory 219100 kb
Host smart-d5e4c956-0ba5-43b9-a887-e75cb37858ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858301935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1858301935
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.124228966
Short name T74
Test name
Test status
Simulation time 524779580 ps
CPU time 27.07 seconds
Started Aug 19 04:32:28 PM PDT 24
Finished Aug 19 04:32:55 PM PDT 24
Peak memory 219164 kb
Host smart-d1d4a488-dcf4-466c-8295-0acdcbcc6a96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124228966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.124228966
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2408967320
Short name T320
Test name
Test status
Simulation time 2347461646 ps
CPU time 118.18 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:34:13 PM PDT 24
Peak memory 224784 kb
Host smart-b3fac9aa-cac1-47c2-8057-c21259bcc027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408967320 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2408967320
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.541931771
Short name T128
Test name
Test status
Simulation time 2064650492 ps
CPU time 9.65 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 218416 kb
Host smart-7cec5753-2c74-4387-b4e5-c5f7521a813e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541931771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.541931771
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.788862770
Short name T256
Test name
Test status
Simulation time 6099385565 ps
CPU time 148.81 seconds
Started Aug 19 04:32:24 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 238840 kb
Host smart-a3d4af0a-01d5-4db8-9eb4-cfa9b54fd8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788862770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.788862770
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2900458646
Short name T272
Test name
Test status
Simulation time 1376891607 ps
CPU time 18.14 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 218860 kb
Host smart-66b44289-625f-4ca9-9830-6b295d5ed77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900458646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2900458646
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3828511213
Short name T166
Test name
Test status
Simulation time 1067436547 ps
CPU time 11.12 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 218616 kb
Host smart-a4481486-770a-408f-8766-1c225ab8659d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828511213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3828511213
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1897596683
Short name T317
Test name
Test status
Simulation time 574134077 ps
CPU time 30.88 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:44 PM PDT 24
Peak memory 219120 kb
Host smart-55e33355-4ecc-4220-8340-d3129f309ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897596683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1897596683
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2274319026
Short name T251
Test name
Test status
Simulation time 4279502309 ps
CPU time 172.45 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:35:04 PM PDT 24
Peak memory 235608 kb
Host smart-7418dc42-46d7-4de1-87e8-e9331d965fd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274319026 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2274319026
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.313314663
Short name T332
Test name
Test status
Simulation time 171095242 ps
CPU time 8.14 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:21 PM PDT 24
Peak memory 218376 kb
Host smart-423754fe-37e7-4e21-bdf6-da6a8cbac782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313314663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.313314663
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2103079988
Short name T33
Test name
Test status
Simulation time 12603693464 ps
CPU time 256.54 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:36:29 PM PDT 24
Peak memory 241724 kb
Host smart-cc87bf65-758f-454e-b73f-c38763b54a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103079988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2103079988
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2515517087
Short name T294
Test name
Test status
Simulation time 675936434 ps
CPU time 17.83 seconds
Started Aug 19 04:32:11 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 218672 kb
Host smart-932df75f-1c25-4ef1-a89c-079005daac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515517087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2515517087
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3158503120
Short name T334
Test name
Test status
Simulation time 1060421470 ps
CPU time 11.58 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:32:32 PM PDT 24
Peak memory 218852 kb
Host smart-3e7b741d-113d-4cc7-9fab-d302abfedbba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158503120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3158503120
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3040361235
Short name T344
Test name
Test status
Simulation time 1548755665 ps
CPU time 23.93 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 219072 kb
Host smart-dd0ab253-cd21-414f-a243-79600807fd66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040361235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3040361235
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2728143607
Short name T245
Test name
Test status
Simulation time 653785222 ps
CPU time 26.8 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:40 PM PDT 24
Peak memory 223016 kb
Host smart-8a929926-b1dd-49aa-831a-6b139707241a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728143607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2728143607
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1034657398
Short name T312
Test name
Test status
Simulation time 1503713577 ps
CPU time 7.86 seconds
Started Aug 19 04:32:10 PM PDT 24
Finished Aug 19 04:32:18 PM PDT 24
Peak memory 219088 kb
Host smart-65764783-9108-4309-8e10-f45bdc137c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034657398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1034657398
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3731261994
Short name T203
Test name
Test status
Simulation time 1032733761 ps
CPU time 21.43 seconds
Started Aug 19 04:32:14 PM PDT 24
Finished Aug 19 04:32:36 PM PDT 24
Peak memory 218780 kb
Host smart-7f74541e-0a3f-4978-b0ee-4f26cb43aa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731261994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3731261994
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1094232307
Short name T9
Test name
Test status
Simulation time 186420606 ps
CPU time 9.7 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:32:23 PM PDT 24
Peak memory 218544 kb
Host smart-72c7157c-e23a-4432-b3a2-ecc99e60c83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094232307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1094232307
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3365524618
Short name T157
Test name
Test status
Simulation time 567828945 ps
CPU time 26.7 seconds
Started Aug 19 04:32:24 PM PDT 24
Finished Aug 19 04:32:50 PM PDT 24
Peak memory 219100 kb
Host smart-8250ab80-61f3-4d73-a34f-3d7b195daa5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365524618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3365524618
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.25074358
Short name T125
Test name
Test status
Simulation time 6834657823 ps
CPU time 116.91 seconds
Started Aug 19 04:32:22 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 225356 kb
Host smart-37bb1eb8-537f-4683-b972-ec8ff18bf948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074358 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.25074358
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.265967512
Short name T181
Test name
Test status
Simulation time 261810103 ps
CPU time 9.47 seconds
Started Aug 19 04:32:21 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 218396 kb
Host smart-47bb55ea-d24d-43c1-b99f-2b915955cc49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265967512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.265967512
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2290026617
Short name T206
Test name
Test status
Simulation time 13380015235 ps
CPU time 227.49 seconds
Started Aug 19 04:32:13 PM PDT 24
Finished Aug 19 04:36:01 PM PDT 24
Peak memory 237180 kb
Host smart-79ed86f1-8fa8-4733-9426-e35336941392
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290026617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2290026617
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2412459384
Short name T24
Test name
Test status
Simulation time 512359681 ps
CPU time 21.67 seconds
Started Aug 19 04:32:12 PM PDT 24
Finished Aug 19 04:32:34 PM PDT 24
Peak memory 218560 kb
Host smart-398fd07d-f8b4-4c47-9cce-0ab011a40de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412459384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2412459384
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3215238375
Short name T137
Test name
Test status
Simulation time 722066407 ps
CPU time 9.92 seconds
Started Aug 19 04:32:31 PM PDT 24
Finished Aug 19 04:32:41 PM PDT 24
Peak memory 218928 kb
Host smart-47c165f2-372e-4fc0-a74e-0ea32132fa51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215238375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3215238375
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1946195640
Short name T249
Test name
Test status
Simulation time 784225562 ps
CPU time 23.19 seconds
Started Aug 19 04:32:31 PM PDT 24
Finished Aug 19 04:32:54 PM PDT 24
Peak memory 219036 kb
Host smart-9e975f00-1629-44d7-8856-54be066a3d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946195640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1946195640
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1542181944
Short name T236
Test name
Test status
Simulation time 4762689861 ps
CPU time 129.2 seconds
Started Aug 19 04:32:15 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 235652 kb
Host smart-8aff7765-3ba5-41ab-a0e1-74c44622b193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542181944 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1542181944
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1673565358
Short name T7
Test name
Test status
Simulation time 339292210 ps
CPU time 7.86 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 218404 kb
Host smart-a68487db-9263-40e9-8c6d-86deeac388c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673565358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1673565358
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1426890943
Short name T342
Test name
Test status
Simulation time 3043913437 ps
CPU time 214.44 seconds
Started Aug 19 04:31:52 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 224308 kb
Host smart-9646ff03-dbe7-471e-93a8-57bc2b137d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426890943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1426890943
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.594313879
Short name T223
Test name
Test status
Simulation time 4559594441 ps
CPU time 29.29 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:32:16 PM PDT 24
Peak memory 219192 kb
Host smart-2c38b4d3-1f5d-4316-820e-ff4950508581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594313879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.594313879
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.910134318
Short name T228
Test name
Test status
Simulation time 344137054 ps
CPU time 10.52 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:31:56 PM PDT 24
Peak memory 218856 kb
Host smart-7fe1e542-f194-4224-988d-831f1b83f130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910134318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.910134318
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.421967018
Short name T343
Test name
Test status
Simulation time 2460445202 ps
CPU time 9.92 seconds
Started Aug 19 04:31:47 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 219076 kb
Host smart-4596ee43-5187-4737-a2b5-01717b87796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421967018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.421967018
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.494937508
Short name T330
Test name
Test status
Simulation time 1085687075 ps
CPU time 15.13 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 219004 kb
Host smart-41adf862-9547-4b92-9c23-8ca5fe3df4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494937508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.494937508
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1278713357
Short name T354
Test name
Test status
Simulation time 8454901822 ps
CPU time 159.04 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 234004 kb
Host smart-9279db16-2632-4806-9f39-0fa8f28d20a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278713357 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1278713357
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3210538599
Short name T260
Test name
Test status
Simulation time 258213735 ps
CPU time 9.83 seconds
Started Aug 19 04:31:33 PM PDT 24
Finished Aug 19 04:31:48 PM PDT 24
Peak memory 218324 kb
Host smart-5fd43233-fcab-466c-9901-1589b950931d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210538599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3210538599
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2915022000
Short name T134
Test name
Test status
Simulation time 10670725082 ps
CPU time 121.67 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 219476 kb
Host smart-a91100c5-2eb8-4c78-9844-7a1faef673b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915022000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2915022000
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.958974501
Short name T242
Test name
Test status
Simulation time 512400983 ps
CPU time 21.14 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 218596 kb
Host smart-6a7e2e60-0e48-46d8-b70a-92d512fa5e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958974501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.958974501
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.428129262
Short name T158
Test name
Test status
Simulation time 1061151616 ps
CPU time 11.39 seconds
Started Aug 19 04:31:54 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 218744 kb
Host smart-9358bbe2-dc28-41a9-b088-eff12ff25a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428129262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.428129262
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3088859914
Short name T164
Test name
Test status
Simulation time 266823032 ps
CPU time 11.51 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:31:55 PM PDT 24
Peak memory 219096 kb
Host smart-32b2ed9a-a8a6-4d8a-ac57-93eb3b0fd3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088859914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3088859914
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1493970023
Short name T352
Test name
Test status
Simulation time 2577787572 ps
CPU time 23.24 seconds
Started Aug 19 04:31:56 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 219108 kb
Host smart-d203e453-d9ef-4b6d-865f-044ca49be3be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493970023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1493970023
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.949472209
Short name T227
Test name
Test status
Simulation time 29666504310 ps
CPU time 213.9 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 235652 kb
Host smart-b1b1fbce-b729-46f1-8ab0-d1bd66efa560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949472209 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.949472209
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1452230030
Short name T324
Test name
Test status
Simulation time 496314001 ps
CPU time 9.09 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:32:01 PM PDT 24
Peak memory 218312 kb
Host smart-d89f25e4-045d-4904-83c5-62d2abe8b088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452230030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1452230030
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.221121380
Short name T310
Test name
Test status
Simulation time 4443950050 ps
CPU time 197.67 seconds
Started Aug 19 04:31:58 PM PDT 24
Finished Aug 19 04:35:16 PM PDT 24
Peak memory 239784 kb
Host smart-d5f323da-6f76-4af9-a28f-2e6e845be784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221121380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.221121380
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1578647161
Short name T144
Test name
Test status
Simulation time 340289959 ps
CPU time 18.02 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:32:05 PM PDT 24
Peak memory 218576 kb
Host smart-bb447d36-11b0-48f6-9439-d859e3300dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578647161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1578647161
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.168511752
Short name T277
Test name
Test status
Simulation time 1015671887 ps
CPU time 14.66 seconds
Started Aug 19 04:32:02 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 219060 kb
Host smart-ca2f9c97-1648-4a0e-8e22-3033050c9981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168511752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.168511752
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2921751788
Short name T32
Test name
Test status
Simulation time 311012545 ps
CPU time 11.47 seconds
Started Aug 19 04:31:48 PM PDT 24
Finished Aug 19 04:32:00 PM PDT 24
Peak memory 218644 kb
Host smart-7f248555-6874-467a-8bd3-5f35f65aaadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921751788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2921751788
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3855306141
Short name T340
Test name
Test status
Simulation time 535285572 ps
CPU time 31.88 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:32:17 PM PDT 24
Peak memory 219132 kb
Host smart-32211814-60a2-4a64-85a9-e90d18e9582a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855306141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3855306141
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1073167602
Short name T52
Test name
Test status
Simulation time 7899968669 ps
CPU time 183.67 seconds
Started Aug 19 04:31:35 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 225296 kb
Host smart-0eee7f80-927c-4886-bb80-6d960592b197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073167602 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1073167602
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.425963013
Short name T213
Test name
Test status
Simulation time 3301640335 ps
CPU time 8.36 seconds
Started Aug 19 04:31:34 PM PDT 24
Finished Aug 19 04:31:43 PM PDT 24
Peak memory 218268 kb
Host smart-c64d9df2-ddfd-4f97-8347-baa5833d6ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425963013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.425963013
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2799553419
Short name T196
Test name
Test status
Simulation time 2682858625 ps
CPU time 171.98 seconds
Started Aug 19 04:31:40 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 239328 kb
Host smart-95c74ce6-e01e-4028-90d2-3a6b2d8218dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799553419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2799553419
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3433261049
Short name T214
Test name
Test status
Simulation time 8241402767 ps
CPU time 21.6 seconds
Started Aug 19 04:31:42 PM PDT 24
Finished Aug 19 04:32:04 PM PDT 24
Peak memory 218944 kb
Host smart-12897cd0-589c-461e-be80-582ac4f0b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433261049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3433261049
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3415177408
Short name T198
Test name
Test status
Simulation time 1007306582 ps
CPU time 15.41 seconds
Started Aug 19 04:32:07 PM PDT 24
Finished Aug 19 04:32:22 PM PDT 24
Peak memory 219088 kb
Host smart-a6efb72d-9d49-47c7-84db-68daf6140744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415177408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3415177408
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3302777667
Short name T178
Test name
Test status
Simulation time 257361409 ps
CPU time 11.15 seconds
Started Aug 19 04:31:43 PM PDT 24
Finished Aug 19 04:31:54 PM PDT 24
Peak memory 219108 kb
Host smart-5c418332-6311-42bd-881c-774f9a05dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302777667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3302777667
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3140374236
Short name T307
Test name
Test status
Simulation time 358496890 ps
CPU time 19.07 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:32:06 PM PDT 24
Peak memory 219152 kb
Host smart-760bd0dd-4098-4b3d-92df-8452187b6970
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140374236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3140374236
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.955126499
Short name T160
Test name
Test status
Simulation time 7944502064 ps
CPU time 81.2 seconds
Started Aug 19 04:31:50 PM PDT 24
Finished Aug 19 04:33:11 PM PDT 24
Peak memory 233020 kb
Host smart-3616ea82-52e6-4799-90cf-3abe31501513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955126499 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.955126499
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1574173943
Short name T162
Test name
Test status
Simulation time 1272576505 ps
CPU time 8.04 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 218288 kb
Host smart-7a608de1-448b-44e5-8868-c47c227e1a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574173943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1574173943
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3755885824
Short name T255
Test name
Test status
Simulation time 3561257237 ps
CPU time 253.73 seconds
Started Aug 19 04:31:44 PM PDT 24
Finished Aug 19 04:35:58 PM PDT 24
Peak memory 238356 kb
Host smart-ee7ef4b7-b8c8-4535-8827-874250491340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755885824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3755885824
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.202682469
Short name T237
Test name
Test status
Simulation time 2361147992 ps
CPU time 17.51 seconds
Started Aug 19 04:32:58 PM PDT 24
Finished Aug 19 04:33:16 PM PDT 24
Peak memory 218416 kb
Host smart-ded5694a-72a9-4f3f-a046-e86d759ad599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202682469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.202682469
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.336401655
Short name T185
Test name
Test status
Simulation time 259512975 ps
CPU time 11 seconds
Started Aug 19 04:31:46 PM PDT 24
Finished Aug 19 04:31:58 PM PDT 24
Peak memory 218864 kb
Host smart-39041798-8134-4f9a-bf22-09004762a0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336401655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.336401655
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1365158129
Short name T336
Test name
Test status
Simulation time 259570340 ps
CPU time 9.96 seconds
Started Aug 19 04:31:45 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 219120 kb
Host smart-689ce720-de0c-4125-8b86-110c7df5e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365158129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1365158129
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.263379590
Short name T73
Test name
Test status
Simulation time 1148778642 ps
CPU time 18.14 seconds
Started Aug 19 04:31:51 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 219148 kb
Host smart-9629f1d4-85f0-4e38-ade9-d2aa2ece5812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263379590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.263379590
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1693712932
Short name T193
Test name
Test status
Simulation time 2255736690 ps
CPU time 82.85 seconds
Started Aug 19 04:31:49 PM PDT 24
Finished Aug 19 04:33:12 PM PDT 24
Peak memory 223944 kb
Host smart-01374ad0-bf07-44d1-ac9b-d9b673aa36e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693712932 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1693712932
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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