Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_fatal_alert_cause_integrity_error.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_0.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_1.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_2.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_3.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_4.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_5.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_6.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_digest_7.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_0.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_1.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_2.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_3.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_4.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_5.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_6.wr_en_data_arb	100.00	100.00
tb.dut.u_reg_regs.u_exp_digest_7.wr_en_data_arb	100.00	100.00

---

Module Instance : tb.dut.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_fatal_alert_cause_checker_error

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_fatal_alert_cause_integrity_error.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_fatal_alert_cause_integrity_error

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_4.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_5.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_5

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_6.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_6

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_digest_7.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_digest_7

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_4.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_5.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_5

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_6.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_6

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_exp_digest_7.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_exp_digest_7

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_fatal_alert_cause_integrity_error.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_4.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_5.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_6.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_digest_7.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_4.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_5.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_6.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg_regs.u_exp_digest_7.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T2 T3 
44         1/1              assign wr_data = d;
           Tests:       T1 T2 T3 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;