25be3439125be34391| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rstmgr_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 20 | 20 | 100.00 |
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | reset_stretcher | rstmgr_por_stretcher | 50 | 50 | 100.00 |
| V2 | sw_rst | rstmgr_sw_rst | 50 | 50 | 100.00 |
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 50 | 50 | 100.00 |
| V2 | reset_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | cpu_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | alert_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | reset_info_capture | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | stress_all | rstmgr_stress_all | 50 | 50 | 100.00 |
| V2 | alert_test | rstmgr_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |
| V2S | tl_intg_err | rstmgr_tl_intg_err | 20 | 20 | 100.00 |
| V2S | prim_count_check | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 45 | 50 | 90.00 |
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 25 | 50 | 50.00 |
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 0 | 50 | 0.00 |
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V2S | TOTAL | 95 | 175 | 54.29 | |
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 48 | 50 | 96.00 |
| V3 | TOTAL | 48 | 50 | 96.00 | |
| TOTAL | 588 | 670 | 87.76 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.17 | 99.46 | 81.00 | 99.80 | -- | 99.79 | 98.37 | 92.59 |
UVM_ERROR (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath)) has 50 failures:
0.rstmgr_leaf_rst_shadow_attack.1734703645
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/out/run.log
UVM_ERROR @ 28881514 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
UVM_INFO @ 28881514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rstmgr_leaf_rst_shadow_attack.1011435844
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/out/run.log
UVM_ERROR @ 28440266 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
UVM_INFO @ 28440266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault has 23 failures:
0.rstmgr_leaf_rst_cnsty.2871665225
Line 60, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/out/run.log
UVM_FATAL @ 121822247 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
UVM_INFO @ 121822247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rstmgr_leaf_rst_cnsty.4008424080
Line 60, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/out/run.log
UVM_FATAL @ 140142752 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
UVM_INFO @ 140142752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset has 4 failures:
1.rstmgr_sec_cm_scan_intersig_mubi.1232588336
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
UVM_ERROR @ 31199063 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
UVM_INFO @ 31199063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rstmgr_sec_cm_scan_intersig_mubi.2760843539
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
UVM_ERROR @ 28319998 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
UVM_INFO @ 28319998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
41.rstmgr_stress_all_with_rand_reset.1165419999
Line 44, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/41.rstmgr_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rstmgr_stress_all_with_rand_reset.173764113
Line 790, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/43.rstmgr_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(gen_assertions[*].rst_cause || (!rst_ens[*]))' has 1 failures:
19.rstmgr_leaf_rst_cnsty.1021256414
Line 197, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/out/run.log
Offending '(gen_assertions[7].rst_cause || (!rst_ens[7]))'
UVM_ERROR @ 750789075 ps: (rstmgr_sw_rst_sva_if.sv:41) [ASSERT FAILED] RstEnOff_A
UVM_INFO @ 750789075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!aon_por_n_i) || resets_o.rst_por_aon_n[*])' has 1 failures:
34.rstmgr_sec_cm_scan_intersig_mubi.378614104
Line 40, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
Offending '((!aon_por_n_i) || resets_o.rst_por_aon_n[0])'
UVM_ERROR @ 27962383 ps: (rstmgr_cascading_sva_if.sv:116) [ASSERT FAILED] StablePorToAonRise_A
UVM_INFO @ 27962383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rst_lc_src_n[rstmgr_pkg::DomainAonSel]) || resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])' has 1 failures:
36.rstmgr_leaf_rst_cnsty.3372442886
Line 113, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/out/run.log
Offending '((!rst_lc_src_n[rstmgr_pkg::DomainAonSel]) || resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])'
UVM_ERROR @ 360998097 ps: (rstmgr_cascading_sva_if.sv:180) [ASSERT FAILED] CascadeLcToLcAonAboveRise_A
UVM_INFO @ 360998097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---