a13b9b8eda13b9b8ed| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rstmgr_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 20 | 20 | 100.00 |
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | reset_stretcher | rstmgr_por_stretcher | 50 | 50 | 100.00 |
| V2 | sw_rst | rstmgr_sw_rst | 50 | 50 | 100.00 |
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 50 | 50 | 100.00 |
| V2 | reset_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | cpu_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | alert_info | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | reset_info_capture | rstmgr_reset | 50 | 50 | 100.00 |
| V2 | stress_all | rstmgr_stress_all | 50 | 50 | 100.00 |
| V2 | alert_test | rstmgr_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |
| V2S | tl_intg_err | rstmgr_tl_intg_err | 20 | 20 | 100.00 |
| V2S | prim_count_check | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 40 | 50 | 80.00 |
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 27 | 50 | 54.00 |
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 0 | 50 | 0.00 |
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 5 | 5 | 100.00 |
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 20 | 20 | 100.00 |
| V2S | TOTAL | 92 | 175 | 52.57 | |
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |
| TOTAL | 583 | 670 | 87.01 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.16 | 99.42 | 81.00 | 99.80 | -- | 99.79 | 98.37 | 92.59 |
UVM_ERROR (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath)) has 50 failures:
0.rstmgr_leaf_rst_shadow_attack.2105093913
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/out/run.log
UVM_ERROR @ 28599372 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
UVM_INFO @ 28599372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rstmgr_leaf_rst_shadow_attack.1683328283
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/out/run.log
UVM_ERROR @ 28545304 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
UVM_INFO @ 28545304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault has 22 failures:
1.rstmgr_leaf_rst_cnsty.1086817095
Line 60, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/out/run.log
UVM_FATAL @ 124645148 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
UVM_INFO @ 124645148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rstmgr_leaf_rst_cnsty.606142715
Line 56, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/out/run.log
UVM_FATAL @ 166994796 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
UVM_INFO @ 166994796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset has 8 failures:
0.rstmgr_sec_cm_scan_intersig_mubi.3515189341
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
UVM_ERROR @ 28740291 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
UVM_INFO @ 28740291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rstmgr_sec_cm_scan_intersig_mubi.699466702
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
UVM_ERROR @ 28565084 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
UVM_INFO @ 28565084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
5.rstmgr_stress_all_with_rand_reset.1106697149
Line 285, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rstmgr_stress_all_with_rand_reset.2068135178
Line 841, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '((!aon_por_n_i) || resets_o.rst_por_aon_n[*])' has 2 failures:
5.rstmgr_sec_cm_scan_intersig_mubi.3217742041
Line 40, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
Offending '((!aon_por_n_i) || resets_o.rst_por_aon_n[0])'
UVM_ERROR @ 27998403 ps: (rstmgr_cascading_sva_if.sv:116) [ASSERT FAILED] StablePorToAonRise_A
UVM_INFO @ 27998403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rstmgr_sec_cm_scan_intersig_mubi.3839655456
Line 40, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/out/run.log
Offending '((!aon_por_n_i) || resets_o.rst_por_aon_n[0])'
UVM_ERROR @ 27974189 ps: (rstmgr_cascading_sva_if.sv:116) [ASSERT FAILED] StablePorToAonRise_A
UVM_INFO @ 27974189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rst_lc_src_n[*]) || resets_o.rst_lc_io_div4_shadowed_n[*])' has 1 failures:
9.rstmgr_leaf_rst_cnsty.2275932608
Line 128, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/out/run.log
Offending '((!rst_lc_src_n[0]) || resets_o.rst_lc_io_div4_shadowed_n[0])'
UVM_ERROR @ 408141409 ps: (rstmgr_cascading_sva_if.sv:159) [ASSERT FAILED] CascadeLcToLcIoDiv4ShadowedAboveRise_A
UVM_INFO @ 408141409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:62) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) has 1 failures:
31.rstmgr_stress_all_with_rand_reset.923758789
Line 571, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/31.rstmgr_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 8006544465 ps: (tl_host_driver.sv:62) [uvm_test_top.env.m_tl_agent_rstmgr_reg_block.driver] Check failed seq_item_port.has_do_available() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8006544465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---