RSTMGR Simulation Results

Tuesday May 17 2022 08:06:55 UTC

GitHub Revision: `6a92ed265`
Foundry Revision: `6a92ed265`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2306330853

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
V1		TOTAL	105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	50	50	100.00
V2	reset_info	rstmgr_reset	50	50	100.00
V2	cpu_info	rstmgr_reset	50	50	100.00
V2	alert_info	rstmgr_reset	50	50	100.00
V2	reset_info_capture	rstmgr_reset	50	50	100.00
V2	stress_all	rstmgr_stress_all	50	50	100.00
V2	alert_test	rstmgr_alert_test	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	5	5	100.00
		rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
		rstmgr_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	5	5	100.00
		rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
		rstmgr_same_csr_outstanding	20	20	100.00
V2		TOTAL	340	340	100.00
V2S	tl_intg_err	rstmgr_tl_intg_err	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	44	50	88.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	27	50	54.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	0	50	0.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	20	20	100.00
V2S		TOTAL	96	175	54.86
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset	48	50	96.00
V3		TOTAL	48	50	96.00
		TOTAL	589	670	87.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	2	40.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.16	99.42	81.00	99.80	--	99.79	98.37	92.59

Failure Buckets

UVM_ERROR (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))

has 50 failures:

Test rstmgr_leaf_rst_shadow_attack has 50 failures.

0.rstmgr_leaf_rst_shadow_attack.2971512912
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/out/run.log

  UVM_ERROR @  28611663 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
  UVM_INFO @  28611663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rstmgr_leaf_rst_shadow_attack.4160381015
Line 38, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/out/run.log

  UVM_ERROR @  28330136 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
  UVM_INFO @  28330136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_FATAL (dv_utils_pkg.sv:147) [rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault has 23 failures:

Test rstmgr_leaf_rst_cnsty has 23 failures.

1.rstmgr_leaf_rst_cnsty.1585408410
Line 61, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/out/run.log

  UVM_FATAL @ 125958152 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
  UVM_INFO @ 125958152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rstmgr_leaf_rst_cnsty.2815371090
Line 56, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/out/run.log

  UVM_FATAL @ 123834082 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault
  UVM_INFO @ 123834082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.

UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset

has 6 failures:

Test rstmgr_sec_cm_scan_intersig_mubi has 6 failures.

0.rstmgr_sec_cm_scan_intersig_mubi.2083162432
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/out/run.log

  UVM_ERROR @  28885883 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
  UVM_INFO @  28885883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rstmgr_sec_cm_scan_intersig_mubi.986640361
Line 39, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/out/run.log

  UVM_ERROR @  30582400 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
  UVM_INFO @  30582400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test rstmgr_stress_all_with_rand_reset has 2 failures.

17.rstmgr_stress_all_with_rand_reset.2445856760
Line 690, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/17.rstmgr_stress_all_with_rand_reset/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.rstmgr_stress_all_with_rand_reset.3782188524
Line 1315, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/23.rstmgr_stress_all_with_rand_reset/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---