V1 |
smoke |
rstmgr_smoke |
1.480s |
249.657us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
rstmgr_csr_hw_reset |
0.870s |
136.706us |
5 |
5 |
100.00 |
V1 |
csr_rw |
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
rstmgr_csr_bit_bash |
8.240s |
2.006ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
rstmgr_csr_aliasing |
2.300s |
401.612us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
rstmgr_csr_mem_rw_with_rand_reset |
1.500s |
161.744us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.300s |
401.612us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
reset_stretcher |
rstmgr_por_stretcher |
0.930s |
245.863us |
50 |
50 |
100.00 |
V2 |
sw_rst |
rstmgr_sw_rst |
2.670s |
387.584us |
50 |
50 |
100.00 |
V2 |
sw_rst_reset_race |
rstmgr_sw_rst_reset_race |
1.510s |
285.442us |
50 |
50 |
100.00 |
V2 |
reset_info |
rstmgr_reset |
7.250s |
1.858ms |
50 |
50 |
100.00 |
V2 |
cpu_info |
rstmgr_reset |
7.250s |
1.858ms |
50 |
50 |
100.00 |
V2 |
alert_info |
rstmgr_reset |
7.250s |
1.858ms |
50 |
50 |
100.00 |
V2 |
reset_info_capture |
rstmgr_reset |
7.250s |
1.858ms |
50 |
50 |
100.00 |
V2 |
stress_all |
rstmgr_stress_all |
44.230s |
15.336ms |
50 |
50 |
100.00 |
V2 |
alert_test |
rstmgr_alert_test |
0.860s |
76.524us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
rstmgr_tl_errors |
3.940s |
713.421us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
rstmgr_tl_errors |
3.940s |
713.421us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
rstmgr_csr_hw_reset |
0.870s |
136.706us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.300s |
401.612us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.510s |
233.333us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
rstmgr_csr_hw_reset |
0.870s |
136.706us |
5 |
5 |
100.00 |
|
|
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
|
|
rstmgr_csr_aliasing |
2.300s |
401.612us |
5 |
5 |
100.00 |
|
|
rstmgr_same_csr_outstanding |
1.510s |
233.333us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
340 |
340 |
100.00 |
V2S |
tl_intg_err |
rstmgr_sec_cm |
23.910s |
16.531ms |
5 |
5 |
100.00 |
|
|
rstmgr_tl_intg_err |
2.910s |
1.025ms |
20 |
20 |
100.00 |
V2S |
prim_count_check |
rstmgr_sec_cm |
23.910s |
16.531ms |
5 |
5 |
100.00 |
V2S |
prim_fsm_check |
rstmgr_sec_cm |
23.910s |
16.531ms |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
rstmgr_tl_intg_err |
2.910s |
1.025ms |
20 |
20 |
100.00 |
V2S |
sec_cm_scan_intersig_mubi |
rstmgr_sec_cm_scan_intersig_mubi |
1.240s |
188.120us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_bkgn_chk |
rstmgr_leaf_rst_cnsty |
8.330s |
2.364ms |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_rst_shadow |
rstmgr_leaf_rst_shadow_attack |
1.140s |
243.828us |
50 |
50 |
100.00 |
V2S |
sec_cm_leaf_fsm_sparse |
rstmgr_sec_cm |
23.910s |
16.531ms |
5 |
5 |
100.00 |
V2S |
sec_cm_sw_rst_config_regwen |
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
V2S |
sec_cm_dump_ctrl_config_regwen |
rstmgr_csr_rw |
0.820s |
77.816us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
175 |
175 |
100.00 |
V3 |
stress_all_with_rand_reset |
rstmgr_stress_all_with_rand_reset |
|
|
0 |
0 |
-- |
V3 |
|
TOTAL |
|
|
0 |
0 |
-- |
|
|
TOTAL |
|
|
620 |
620 |
100.00 |