RSTMGR Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.480s	260.204us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.870s	119.701us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	7.090s	1.545ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.500s	462.486us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.740s	195.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
		rstmgr_csr_aliasing	2.500s	462.486us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.950s	205.864us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.700s	506.320us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.550s	295.285us	50	50	100.00
V2	reset_info	rstmgr_reset	7.840s	1.965ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.840s	1.965ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.840s	1.965ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.840s	1.965ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.360s	14.519ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.830s	99.366us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.880s	665.296us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.880s	665.296us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.870s	119.701us	5	5	100.00
		rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
		rstmgr_csr_aliasing	2.500s	462.486us	5	5	100.00
		rstmgr_same_csr_outstanding	1.520s	225.367us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.870s	119.701us	5	5	100.00
		rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
		rstmgr_csr_aliasing	2.500s	462.486us	5	5	100.00
		rstmgr_same_csr_outstanding	1.520s	225.367us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	14.920s	8.281ms	5	5	100.00
		rstmgr_tl_intg_err	3.090s	894.451us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	14.920s	8.281ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	14.920s	8.281ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.090s	894.451us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.160s	159.275us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.800s	2.346ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.120s	243.791us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	14.920s	8.281ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.850s	78.119us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.53	99.41	99.31	99.88	--	99.83	100.00	98.77

Past Results

• Latest
• 2023.05.22_19.44.32
• 2023.05.21_20.21.17
• 2023.05.20_19.37.45
• 2023.05.19_16.19.50
• 2023.05.18_19.21.26
• 2023.05.17_18.06.01
• 2023.05.16_19.29.19