RSTMGR Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.570s	261.246us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.810s	118.868us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	8.450s	2.289ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.280s	346.402us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.780s	186.860us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	346.402us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.950s	248.208us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.490s	515.115us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.470s	238.366us	50	50	100.00
V2	reset_info	rstmgr_reset	6.670s	2.028ms	50	50	100.00
V2	cpu_info	rstmgr_reset	6.670s	2.028ms	50	50	100.00
V2	alert_info	rstmgr_reset	6.670s	2.028ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	6.670s	2.028ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	57.360s	19.508ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.910s	135.025us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.570s	525.782us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.570s	525.782us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.810s	118.868us	5	5	100.00
		rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	346.402us	5	5	100.00
		rstmgr_same_csr_outstanding	1.440s	238.368us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.810s	118.868us	5	5	100.00
		rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	346.402us	5	5	100.00
		rstmgr_same_csr_outstanding	1.440s	238.368us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	22.600s	16.514ms	5	5	100.00
		rstmgr_tl_intg_err	3.370s	1.310ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	22.600s	16.514ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	22.600s	16.514ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.370s	1.310ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.240s	146.570us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.220s	2.370ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.130s	244.244us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	22.600s	16.514ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.840s	83.485us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.52	99.41	99.24	99.88	--	99.83	100.00	98.77

Past Results

• Latest
• 2023.05.27_19.04.30
• 2023.05.26_19.07.10
• 2023.05.25_18.20.04
• 2023.05.24_17.39.41
• 2023.05.23_17.59.17
• 2023.05.22_19.44.32
• 2023.05.21_20.21.17