Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7667

1

T2

21

T14

4

T21

18

auto[1]

10803

1

T2

30

T3

4

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5750	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6299	1			T1	1		T2	18		T3	2
reset_info_cp[2]	2760	1			T2	11		T3	1		T5	1
reset_info_cp[4]	3700	1			T2	4		T3	1		T5	1
reset_info_cp[8]	128	1			T113	2		T52	2		T149	3
reset_info_cp[16]	128	1			T14	1		T94	1		T98	1
reset_info_cp[32]	114	1			T2	1		T24	1		T51	2
reset_info_cp[64]	115	1			T2	1		T3	1		T21	1
reset_info_cp[128]	96	1			T21	1		T24	2		T52	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3000	1			T2	6		T21	18		T24	7
reset_info_cp[1]	auto[1]	2679	1			T2	11		T3	1		T5	1
reset_info_cp[2]	auto[0]	844	1			T2	4		T24	5		T113	6
reset_info_cp[2]	auto[1]	1916	1			T2	7		T3	1		T5	1
reset_info_cp[4]	auto[0]	1248	1			T2	1		T24	10		T51	4
reset_info_cp[4]	auto[1]	2452	1			T2	3		T3	1		T5	1
reset_info_cp[8]	auto[0]	52	1			T113	1		T52	2		T149	3
reset_info_cp[8]	auto[1]	76	1			T113	1		T40	1		T45	1
reset_info_cp[16]	auto[0]	57	1			T14	1		T113	1		T52	1
reset_info_cp[16]	auto[1]	71	1			T94	1		T98	1		T26	1
reset_info_cp[32]	auto[0]	47	1			T39	1		T114	1		T117	2
reset_info_cp[32]	auto[1]	67	1			T2	1		T24	1		T51	2
reset_info_cp[64]	auto[0]	47	1			T2	1		T51	1		T52	1
reset_info_cp[64]	auto[1]	68	1			T3	1		T21	1		T52	1
reset_info_cp[128]	auto[0]	34	1			T24	1		T149	1		T151	1
reset_info_cp[128]	auto[1]	62	1			T21	1		T24	1		T52	1