Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7867 |
1 |
|
|
T2 |
33 |
|
T14 |
4 |
|
T21 |
18 |
auto[1] |
10603 |
1 |
|
|
T2 |
18 |
|
T3 |
4 |
|
T5 |
4 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
5750 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
6299 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T3 |
2 |
reset_info_cp[2] |
2760 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T5 |
1 |
reset_info_cp[4] |
3700 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T5 |
1 |
reset_info_cp[8] |
128 |
1 |
|
|
T113 |
2 |
|
T52 |
2 |
|
T149 |
3 |
reset_info_cp[16] |
128 |
1 |
|
|
T14 |
1 |
|
T94 |
1 |
|
T98 |
1 |
reset_info_cp[32] |
114 |
1 |
|
|
T2 |
1 |
|
T24 |
1 |
|
T51 |
2 |
reset_info_cp[64] |
115 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T21 |
1 |
reset_info_cp[128] |
96 |
1 |
|
|
T21 |
1 |
|
T24 |
2 |
|
T52 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3038 |
1 |
|
|
T2 |
14 |
|
T21 |
18 |
|
T24 |
7 |
reset_info_cp[1] |
auto[1] |
2641 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T5 |
1 |
reset_info_cp[2] |
auto[0] |
881 |
1 |
|
|
T2 |
6 |
|
T24 |
5 |
|
T51 |
2 |
reset_info_cp[2] |
auto[1] |
1879 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T5 |
1 |
reset_info_cp[4] |
auto[0] |
1312 |
1 |
|
|
T2 |
2 |
|
T24 |
9 |
|
T51 |
6 |
reset_info_cp[4] |
auto[1] |
2388 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
1 |
reset_info_cp[8] |
auto[0] |
51 |
1 |
|
|
T113 |
1 |
|
T52 |
1 |
|
T149 |
3 |
reset_info_cp[8] |
auto[1] |
77 |
1 |
|
|
T113 |
1 |
|
T52 |
1 |
|
T40 |
1 |
reset_info_cp[16] |
auto[0] |
59 |
1 |
|
|
T14 |
1 |
|
T113 |
1 |
|
T52 |
1 |
reset_info_cp[16] |
auto[1] |
69 |
1 |
|
|
T94 |
1 |
|
T98 |
1 |
|
T26 |
1 |
reset_info_cp[32] |
auto[0] |
44 |
1 |
|
|
T2 |
1 |
|
T51 |
1 |
|
T39 |
1 |
reset_info_cp[32] |
auto[1] |
70 |
1 |
|
|
T24 |
1 |
|
T51 |
1 |
|
T52 |
1 |
reset_info_cp[64] |
auto[0] |
51 |
1 |
|
|
T2 |
1 |
|
T149 |
2 |
|
T150 |
1 |
reset_info_cp[64] |
auto[1] |
64 |
1 |
|
|
T3 |
1 |
|
T21 |
1 |
|
T51 |
1 |
reset_info_cp[128] |
auto[0] |
35 |
1 |
|
|
T149 |
1 |
|
T151 |
1 |
|
T144 |
2 |
reset_info_cp[128] |
auto[1] |
61 |
1 |
|
|
T21 |
1 |
|
T24 |
2 |
|
T52 |
1 |